From 09e826e09a10ba9aca2caf44139fdb39cd9b9dfc Mon Sep 17 00:00:00 2001 From: "bernard.xiong@gmail.com" Date: Thu, 20 Oct 2011 23:38:20 +0000 Subject: [PATCH] add STM32F40x porting (uncompleted) git-svn-id: https://rt-thread.googlecode.com/svn/trunk@1769 bbd45198-f89e-11dd-88c7-29a3b14d5316 --- .../CMSIS END USER LICENCE AGREEMENT.pdf | Bin 0 -> 51511 bytes .../Source/ARM/arm_cortexM0x_math.uvopt | 3711 +++++++++ .../Source/ARM/arm_cortexM0x_math.uvproj | 3269 ++++++++ .../Source/ARM/arm_cortexM3x_math.uvopt | 3711 +++++++++ .../Source/ARM/arm_cortexM3x_math.uvproj | 3269 ++++++++ .../Source/ARM/arm_cortexM4x_math.uvopt | 3969 ++++++++++ .../Source/ARM/arm_cortexM4x_math.uvproj | 6527 +++++++++++++++ .../Source/ARM/arm_cortexMx_math_Build.bat | 14 + .../Source/BasicMathFunctions/arm_abs_f32.c | 122 + .../Source/BasicMathFunctions/arm_abs_q15.c | 170 + .../Source/BasicMathFunctions/arm_abs_q31.c | 120 + .../Source/BasicMathFunctions/arm_abs_q7.c | 143 + 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..\FilteringFunctions\arm_conv_partial_fast_q15.c + + + arm_conv_partial_fast_q31.c + 1 + ..\FilteringFunctions\arm_conv_partial_fast_q31.c + + + arm_conv_partial_q7.c + 1 + ..\FilteringFunctions\arm_conv_partial_q7.c + + + arm_conv_partial_q15.c + 1 + ..\FilteringFunctions\arm_conv_partial_q15.c + + + arm_conv_partial_q31.c + 1 + ..\FilteringFunctions\arm_conv_partial_q31.c + + + arm_conv_q7.c + 1 + ..\FilteringFunctions\arm_conv_q7.c + + + arm_conv_q15.c + 1 + ..\FilteringFunctions\arm_conv_q15.c + + + arm_conv_q31.c + 1 + ..\FilteringFunctions\arm_conv_q31.c + + + arm_correlate_f32.c + 1 + ..\FilteringFunctions\arm_correlate_f32.c + + + arm_correlate_fast_q15.c + 1 + ..\FilteringFunctions\arm_correlate_fast_q15.c + + + arm_correlate_fast_q31.c + 1 + ..\FilteringFunctions\arm_correlate_fast_q31.c + + + arm_correlate_q7.c + 1 + ..\FilteringFunctions\arm_correlate_q7.c + + + arm_correlate_q15.c + 1 + ..\FilteringFunctions\arm_correlate_q15.c + + + arm_correlate_q31.c + 1 + ..\FilteringFunctions\arm_correlate_q31.c + + + arm_fir_decimate_f32.c + 1 + ..\FilteringFunctions\arm_fir_decimate_f32.c + + + arm_fir_decimate_fast_q15.c + 1 + ..\FilteringFunctions\arm_fir_decimate_fast_q15.c + + + arm_fir_decimate_fast_q31.c + 1 + ..\FilteringFunctions\arm_fir_decimate_fast_q31.c + + + arm_fir_decimate_init_f32.c + 1 + ..\FilteringFunctions\arm_fir_decimate_init_f32.c + + + arm_fir_decimate_init_q15.c + 1 + ..\FilteringFunctions\arm_fir_decimate_init_q15.c + + + arm_fir_decimate_init_q31.c + 1 + ..\FilteringFunctions\arm_fir_decimate_init_q31.c + + + arm_fir_decimate_q15.c + 1 + ..\FilteringFunctions\arm_fir_decimate_q15.c + + + arm_fir_decimate_q31.c + 1 + ..\FilteringFunctions\arm_fir_decimate_q31.c + + + arm_fir_f32.c + 1 + ..\FilteringFunctions\arm_fir_f32.c + + + arm_fir_fast_q15.c + 1 + ..\FilteringFunctions\arm_fir_fast_q15.c + + + arm_fir_fast_q31.c + 1 + ..\FilteringFunctions\arm_fir_fast_q31.c + + + arm_fir_init_f32.c + 1 + ..\FilteringFunctions\arm_fir_init_f32.c + + + arm_fir_init_q7.c + 1 + ..\FilteringFunctions\arm_fir_init_q7.c + + + arm_fir_init_q15.c + 1 + ..\FilteringFunctions\arm_fir_init_q15.c + + + arm_fir_init_q31.c + 1 + ..\FilteringFunctions\arm_fir_init_q31.c + + + arm_fir_interpolate_f32.c + 1 + ..\FilteringFunctions\arm_fir_interpolate_f32.c + + + arm_fir_interpolate_init_f32.c + 1 + ..\FilteringFunctions\arm_fir_interpolate_init_f32.c + + + arm_fir_interpolate_init_q15.c + 1 + ..\FilteringFunctions\arm_fir_interpolate_init_q15.c + + + arm_fir_interpolate_init_q31.c + 1 + ..\FilteringFunctions\arm_fir_interpolate_init_q31.c + + + arm_fir_interpolate_q15.c + 1 + ..\FilteringFunctions\arm_fir_interpolate_q15.c + + + arm_fir_interpolate_q31.c + 1 + ..\FilteringFunctions\arm_fir_interpolate_q31.c + + + arm_fir_lattice_f32.c + 1 + ..\FilteringFunctions\arm_fir_lattice_f32.c + + + arm_fir_lattice_init_f32.c + 1 + ..\FilteringFunctions\arm_fir_lattice_init_f32.c + + + arm_fir_lattice_init_q15.c + 1 + ..\FilteringFunctions\arm_fir_lattice_init_q15.c + + + arm_fir_lattice_init_q31.c + 1 + ..\FilteringFunctions\arm_fir_lattice_init_q31.c + + + arm_fir_lattice_q15.c + 1 + ..\FilteringFunctions\arm_fir_lattice_q15.c + + + arm_fir_lattice_q31.c + 1 + ..\FilteringFunctions\arm_fir_lattice_q31.c + + + arm_fir_q7.c + 1 + ..\FilteringFunctions\arm_fir_q7.c + + + arm_fir_q15.c + 1 + ..\FilteringFunctions\arm_fir_q15.c + + + arm_fir_q31.c + 1 + ..\FilteringFunctions\arm_fir_q31.c + + + arm_fir_sparse_f32.c + 1 + ..\FilteringFunctions\arm_fir_sparse_f32.c + + + arm_fir_sparse_init_f32.c + 1 + ..\FilteringFunctions\arm_fir_sparse_init_f32.c + + + arm_fir_sparse_init_q7.c + 1 + ..\FilteringFunctions\arm_fir_sparse_init_q7.c + + + arm_fir_sparse_init_q15.c + 1 + ..\FilteringFunctions\arm_fir_sparse_init_q15.c + + + arm_fir_sparse_init_q31.c + 1 + ..\FilteringFunctions\arm_fir_sparse_init_q31.c + + + arm_fir_sparse_q7.c + 1 + ..\FilteringFunctions\arm_fir_sparse_q7.c + + + arm_fir_sparse_q15.c + 1 + ..\FilteringFunctions\arm_fir_sparse_q15.c + + + arm_fir_sparse_q31.c + 1 + ..\FilteringFunctions\arm_fir_sparse_q31.c + + + arm_iir_lattice_f32.c + 1 + ..\FilteringFunctions\arm_iir_lattice_f32.c + + + arm_iir_lattice_init_f32.c + 1 + ..\FilteringFunctions\arm_iir_lattice_init_f32.c + + + arm_iir_lattice_init_q15.c + 1 + ..\FilteringFunctions\arm_iir_lattice_init_q15.c + + + arm_iir_lattice_init_q31.c + 1 + ..\FilteringFunctions\arm_iir_lattice_init_q31.c + + + arm_iir_lattice_q15.c + 1 + ..\FilteringFunctions\arm_iir_lattice_q15.c + + + arm_iir_lattice_q31.c + 1 + ..\FilteringFunctions\arm_iir_lattice_q31.c + + + arm_lms_f32.c + 1 + ..\FilteringFunctions\arm_lms_f32.c + + + arm_lms_init_f32.c + 1 + ..\FilteringFunctions\arm_lms_init_f32.c + + + arm_lms_init_q15.c + 1 + ..\FilteringFunctions\arm_lms_init_q15.c + + + arm_lms_init_q31.c + 1 + ..\FilteringFunctions\arm_lms_init_q31.c + + + arm_lms_norm_f32.c + 1 + ..\FilteringFunctions\arm_lms_norm_f32.c + + + arm_lms_norm_init_f32.c + 1 + ..\FilteringFunctions\arm_lms_norm_init_f32.c + + + arm_lms_norm_init_q15.c + 1 + ..\FilteringFunctions\arm_lms_norm_init_q15.c + + + arm_lms_norm_init_q31.c + 1 + ..\FilteringFunctions\arm_lms_norm_init_q31.c + + + arm_lms_norm_q15.c + 1 + ..\FilteringFunctions\arm_lms_norm_q15.c + + + arm_lms_norm_q31.c + 1 + ..\FilteringFunctions\arm_lms_norm_q31.c + + + arm_lms_q15.c + 1 + ..\FilteringFunctions\arm_lms_q15.c + + + arm_lms_q31.c + 1 + ..\FilteringFunctions\arm_lms_q31.c + + + + + MatrixFunctions + + + arm_mat_add_f32.c + 1 + ..\MatrixFunctions\arm_mat_add_f32.c + + + arm_mat_add_q15.c + 1 + ..\MatrixFunctions\arm_mat_add_q15.c + + + arm_mat_add_q31.c + 1 + ..\MatrixFunctions\arm_mat_add_q31.c + + + arm_mat_init_f32.c + 1 + ..\MatrixFunctions\arm_mat_init_f32.c + + + arm_mat_init_q15.c + 1 + ..\MatrixFunctions\arm_mat_init_q15.c + + + arm_mat_init_q31.c + 1 + ..\MatrixFunctions\arm_mat_init_q31.c + + + arm_mat_inverse_f32.c + 1 + ..\MatrixFunctions\arm_mat_inverse_f32.c + + + arm_mat_mult_f32.c + 1 + ..\MatrixFunctions\arm_mat_mult_f32.c + + + arm_mat_mult_fast_q15.c + 1 + ..\MatrixFunctions\arm_mat_mult_fast_q15.c + + + arm_mat_mult_fast_q31.c + 1 + ..\MatrixFunctions\arm_mat_mult_fast_q31.c + + + arm_mat_mult_q15.c + 1 + ..\MatrixFunctions\arm_mat_mult_q15.c + + + arm_mat_mult_q31.c + 1 + ..\MatrixFunctions\arm_mat_mult_q31.c + + + arm_mat_scale_f32.c + 1 + ..\MatrixFunctions\arm_mat_scale_f32.c + + + arm_mat_scale_q15.c + 1 + ..\MatrixFunctions\arm_mat_scale_q15.c + + + arm_mat_scale_q31.c + 1 + ..\MatrixFunctions\arm_mat_scale_q31.c + + + arm_mat_sub_f32.c + 1 + ..\MatrixFunctions\arm_mat_sub_f32.c + + + arm_mat_sub_q15.c + 1 + ..\MatrixFunctions\arm_mat_sub_q15.c + + + arm_mat_sub_q31.c + 1 + ..\MatrixFunctions\arm_mat_sub_q31.c + + + arm_mat_trans_f32.c + 1 + ..\MatrixFunctions\arm_mat_trans_f32.c + + + arm_mat_trans_q15.c + 1 + ..\MatrixFunctions\arm_mat_trans_q15.c + + + arm_mat_trans_q31.c + 1 + ..\MatrixFunctions\arm_mat_trans_q31.c + + + + + TransformFunctions + + + arm_cfft_radix4_f32.c + 1 + ..\TransformFunctions\arm_cfft_radix4_f32.c + + + arm_cfft_radix4_init_f32.c + 1 + ..\TransformFunctions\arm_cfft_radix4_init_f32.c + + + arm_cfft_radix4_init_q15.c + 1 + ..\TransformFunctions\arm_cfft_radix4_init_q15.c + + + arm_cfft_radix4_init_q31.c + 1 + ..\TransformFunctions\arm_cfft_radix4_init_q31.c + + + arm_cfft_radix4_q15.c + 1 + ..\TransformFunctions\arm_cfft_radix4_q15.c + + + arm_cfft_radix4_q31.c + 1 + ..\TransformFunctions\arm_cfft_radix4_q31.c + + + arm_dct4_f32.c + 1 + ..\TransformFunctions\arm_dct4_f32.c + + + arm_dct4_init_f32.c + 1 + ..\TransformFunctions\arm_dct4_init_f32.c + + + arm_dct4_init_q15.c + 1 + ..\TransformFunctions\arm_dct4_init_q15.c + + + arm_dct4_init_q31.c + 1 + ..\TransformFunctions\arm_dct4_init_q31.c + + + arm_dct4_q15.c + 1 + ..\TransformFunctions\arm_dct4_q15.c + + + arm_dct4_q31.c + 1 + ..\TransformFunctions\arm_dct4_q31.c + + + arm_rfft_f32.c + 1 + ..\TransformFunctions\arm_rfft_f32.c + + + arm_rfft_init_f32.c + 1 + ..\TransformFunctions\arm_rfft_init_f32.c + + + arm_rfft_init_q15.c + 1 + ..\TransformFunctions\arm_rfft_init_q15.c + + + arm_rfft_init_q31.c + 1 + ..\TransformFunctions\arm_rfft_init_q31.c + + + arm_rfft_q15.c + 1 + ..\TransformFunctions\arm_rfft_q15.c + + + arm_rfft_q31.c + 1 + ..\TransformFunctions\arm_rfft_q31.c + + + + + ControllerFunctions + + + arm_pid_init_f32.c + 1 + ..\ControllerFunctions\arm_pid_init_f32.c + + + arm_pid_init_q15.c + 1 + ..\ControllerFunctions\arm_pid_init_q15.c + + + arm_pid_init_q31.c + 1 + ..\ControllerFunctions\arm_pid_init_q31.c + + + arm_pid_reset_f32.c + 1 + ..\ControllerFunctions\arm_pid_reset_f32.c + + + arm_pid_reset_q15.c + 1 + ..\ControllerFunctions\arm_pid_reset_q15.c + + + arm_pid_reset_q31.c + 1 + ..\ControllerFunctions\arm_pid_reset_q31.c + + + arm_sin_cos_f32.c + 1 + ..\ControllerFunctions\arm_sin_cos_f32.c + + + arm_sin_cos_q31.c + 1 + ..\ControllerFunctions\arm_sin_cos_q31.c + + + + + StatisticsFunctions + + + arm_max_f32.c + 1 + ..\StatisticsFunctions\arm_max_f32.c + + + arm_max_q7.c + 1 + ..\StatisticsFunctions\arm_max_q7.c + + + arm_max_q15.c + 1 + ..\StatisticsFunctions\arm_max_q15.c + + + arm_max_q31.c + 1 + ..\StatisticsFunctions\arm_max_q31.c + + + arm_mean_f32.c + 1 + ..\StatisticsFunctions\arm_mean_f32.c + + + arm_mean_q7.c + 1 + ..\StatisticsFunctions\arm_mean_q7.c + + + arm_mean_q15.c + 1 + ..\StatisticsFunctions\arm_mean_q15.c + + + arm_mean_q31.c + 1 + ..\StatisticsFunctions\arm_mean_q31.c + + + arm_min_f32.c + 1 + ..\StatisticsFunctions\arm_min_f32.c + + + arm_min_q7.c + 1 + ..\StatisticsFunctions\arm_min_q7.c + + + arm_min_q15.c + 1 + ..\StatisticsFunctions\arm_min_q15.c + + + arm_min_q31.c + 1 + ..\StatisticsFunctions\arm_min_q31.c + + + arm_power_f32.c + 1 + ..\StatisticsFunctions\arm_power_f32.c + + + arm_power_q7.c + 1 + ..\StatisticsFunctions\arm_power_q7.c + + + arm_power_q15.c + 1 + ..\StatisticsFunctions\arm_power_q15.c + + + arm_power_q31.c + 1 + ..\StatisticsFunctions\arm_power_q31.c + + + arm_rms_f32.c + 1 + ..\StatisticsFunctions\arm_rms_f32.c + + + arm_rms_q15.c + 1 + ..\StatisticsFunctions\arm_rms_q15.c + + + arm_rms_q31.c + 1 + ..\StatisticsFunctions\arm_rms_q31.c + + + arm_std_f32.c + 1 + ..\StatisticsFunctions\arm_std_f32.c + + + arm_std_q15.c + 1 + ..\StatisticsFunctions\arm_std_q15.c + + + arm_std_q31.c + 1 + ..\StatisticsFunctions\arm_std_q31.c + + + arm_var_f32.c + 1 + ..\StatisticsFunctions\arm_var_f32.c + + + arm_var_q15.c + 1 + ..\StatisticsFunctions\arm_var_q15.c + + + arm_var_q31.c + 1 + ..\StatisticsFunctions\arm_var_q31.c + + + + + SupportFunctions + + + arm_copy_f32.c + 1 + ..\SupportFunctions\arm_copy_f32.c + + + arm_copy_q7.c + 1 + ..\SupportFunctions\arm_copy_q7.c + + + arm_copy_q15.c + 1 + ..\SupportFunctions\arm_copy_q15.c + + + arm_copy_q31.c + 1 + ..\SupportFunctions\arm_copy_q31.c + + + arm_fill_f32.c + 1 + ..\SupportFunctions\arm_fill_f32.c + + + arm_fill_q7.c + 1 + ..\SupportFunctions\arm_fill_q7.c + + + arm_fill_q15.c + 1 + ..\SupportFunctions\arm_fill_q15.c + + + arm_fill_q31.c + 1 + ..\SupportFunctions\arm_fill_q31.c + + + arm_float_to_q7.c + 1 + ..\SupportFunctions\arm_float_to_q7.c + + + arm_float_to_q15.c + 1 + ..\SupportFunctions\arm_float_to_q15.c + + + arm_float_to_q31.c + 1 + ..\SupportFunctions\arm_float_to_q31.c + + + arm_q7_to_float.c + 1 + ..\SupportFunctions\arm_q7_to_float.c + + + arm_q7_to_q15.c + 1 + ..\SupportFunctions\arm_q7_to_q15.c + + + arm_q7_to_q31.c + 1 + ..\SupportFunctions\arm_q7_to_q31.c + + + arm_q15_to_float.c + 1 + ..\SupportFunctions\arm_q15_to_float.c + + + arm_q15_to_q7.c + 1 + ..\SupportFunctions\arm_q15_to_q7.c + + + arm_q15_to_q31.c + 1 + ..\SupportFunctions\arm_q15_to_q31.c + + + arm_q31_to_float.c + 1 + ..\SupportFunctions\arm_q31_to_float.c + + + arm_q31_to_q7.c + 1 + ..\SupportFunctions\arm_q31_to_q7.c + + + arm_q31_to_q15.c + 1 + ..\SupportFunctions\arm_q31_to_q15.c + + + + + CommonTables + + + arm_common_tables.c + 1 + ..\CommonTables\arm_common_tables.c + + + + + + + +     diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ARM/arm_cortexMx_math_Build.bat b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ARM/arm_cortexMx_math_Build.bat new file mode 100644 index 0000000000..5ce1fe687c --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ARM/arm_cortexMx_math_Build.bat @@ -0,0 +1,14 @@ + +SET TMP=C:\Temp +SET TEMP=C:\Temp + +SET UVEXE=C:\Keil\UV4\UV4.EXE + +%UVEXE% -rb arm_cortexM0x_math.uvproj -t"DSP_Lib CM0 LE" -o"DSP_Lib CM0 LE.txt" +%UVEXE% -rb arm_cortexM0x_math.uvproj -t"DSP_Lib CM0 BE" -o"DSP_Lib CM0 BE.txt" +%UVEXE% -rb arm_cortexM3x_math.uvproj -t"DSP_Lib CM3 LE" -o"DSP_Lib CM3 LE.txt" +%UVEXE% -rb arm_cortexM3x_math.uvproj -t"DSP_Lib CM3 BE" -o"DSP_Lib CM3 BE.txt" +%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE" -o"DSP_Lib CM4 LE.txt" +%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 BE" -o"DSP_Lib CM4 BE.txt" +%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 LE FPU" -o"DSP_Lib CM4 LE FPU.txt" +%UVEXE% -rb arm_cortexM4x_math.uvproj -t"DSP_Lib CM4 BE FPU" -o"DSP_Lib CM4 BE FPU.txt" \ No newline at end of file diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c new file mode 100644 index 0000000000..958fe541cc --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_abs_f32.c +* +* Description: Vector absolute value. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" +#include + +/** + * @ingroup groupMath + */ + +/** + * @defgroup BasicAbs Vector Absolute Value + * + * Computes the absolute value of a vector on an element-by-element basis. + * + * 
       
+ *     pDst[n] = abs(pSrcA[n]),   0 <= n < blockSize.   
+ *
    + * + * The operation can be done in-place by setting the input and output pointers to the same buffer. + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup BasicAbs + * @{ + */ + +/** + * @brief Floating-point vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_abs_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = |A| */ + /* Calculate absolute and then store the results in the destination buffer. */ + *pDst++ = fabsf(*pSrc++); + *pDst++ = fabsf(*pSrc++); + *pDst++ = fabsf(*pSrc++); + *pDst++ = fabsf(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = |A| */ + /* Calculate absolute and then store the results in the destination buffer. */ + *pDst++ = fabsf(*pSrc++); + + /* Decrement the loop counter */ + blkCnt--; + } + +} + +/** + * @} end of BasicAbs group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c new file mode 100644 index 0000000000..5d346fff34 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c @@ -0,0 +1,170 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_abs_q15.c +* +* Description: Q15 vector absolute value. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAbs + * @{ + */ + +/** + * @brief Q15 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. + */ + +void arm_abs_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + q15_t in1; /* Input value1 */ + q15_t in2; /* Input value2 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = |A| */ + /* Read two inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + + + /* Store the Absolute result in the destination buffer by packing the two values, in a single cycle */ + +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = + __PKHBT(((in1 > 0) ? in1 : __SSAT(-in1, 16)), + ((in2 > 0) ? in2 : __SSAT(-in2, 16)), 16); + +#else + + + *__SIMD32(pDst)++ = + __PKHBT(((in2 > 0) ? in2 : __SSAT(-in2, 16)), + ((in1 > 0) ? in1 : __SSAT(-in1, 16)), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = *pSrc++; + in2 = *pSrc++; + + +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = + __PKHBT(((in1 > 0) ? in1 : __SSAT(-in1, 16)), + ((in2 > 0) ? in2 : __SSAT(-in2, 16)), 16); + + +#else + + *__SIMD32(pDst)++ = + __PKHBT(((in2 > 0) ? in2 : __SSAT(-in2, 16)), + ((in1 > 0) ? in1 : __SSAT(-in1, 16)), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = |A| */ + /* Read the input */ + in1 = *pSrc++; + + /* Calculate absolute value of input and then store the result in the destination buffer. */ + *pDst++ = (in1 > 0) ? in1 : __SSAT(-in1, 16); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + q15_t in; /* Temporary input variable */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = |A| */ + /* Read the input */ + in = *pSrc++; + + /* Calculate absolute value of input and then store the result in the destination buffer. */ + *pDst++ = (in > 0) ? in : __SSAT(-in, 16); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of BasicAbs group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c new file mode 100644 index 0000000000..86a0b55b90 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c @@ -0,0 +1,120 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_abs_q31.c +* +* Description: Q31 vector absolute value. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAbs + * @{ + */ + + +/** + * @brief Q31 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +void arm_abs_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + q31_t in; /* Input value */ + +#ifndef ARM_MATH_CM0 + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = |A| */ + /* Calculate absolute of input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */ + in = *pSrc++; + *pDst++ = (in > 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in); + in = *pSrc++; + *pDst++ = (in > 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in); + in = *pSrc++; + *pDst++ = (in > 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in); + in = *pSrc++; + *pDst++ = (in > 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = |A| */ + /* Calculate absolute value of the input (if -1 then saturated to 0x7fffffff) and then store the results in the destination buffer. */ + in = *pSrc++; + *pDst++ = (in > 0) ? in : ((in == 0x80000000) ? 0x7fffffff : -in); + + /* Decrement the loop counter */ + blkCnt--; + } + +} + +/** + * @} end of BasicAbs group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c new file mode 100644 index 0000000000..f1dd27b345 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c @@ -0,0 +1,143 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_abs_q7.c +* +* Description: Q7 vector absolute value. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAbs + * @{ + */ + +/** + * @brief Q7 vector absolute value. + * @param[in] *pSrc points to the input buffer + * @param[out] *pDst points to the output buffer + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. + */ + +void arm_abs_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + + /* Run the below code for Cortex-M4 and Cortex-M3 */ + q7_t in1; /* Input value1 */ + q7_t in2; /* Input value2 */ + q7_t in3; /* Input value3 */ + q7_t in4; /* Input value4 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = |A| */ + /* Read 4 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Store the Absolute result in the destination buffer by packing the 4 values in single cycle */ + *__SIMD32(pDst)++ = + __PACKq7(((in1 > 0) ? in1 : __SSAT(-in1, 8)), + ((in2 > 0) ? in2 : __SSAT(-in2, 8)), + ((in3 > 0) ? in3 : __SSAT(-in3, 8)), + ((in4 > 0) ? in4 : __SSAT(-in4, 8))); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = |A| */ + /* Read the input */ + in1 = *pSrc++; + + /* Store the Absolute result in the destination buffer */ + *pDst++ = (in1 > 0) ? in1 : __SSAT(-in1, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + q7_t in; /* Temporary input varible */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = |A| */ + /* Read the input */ + in = *pSrc++; + + /* Store the Absolute result in the destination buffer */ + *pDst++ = (in > 0) ? in : __SSAT(-in, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of BasicAbs group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c new file mode 100644 index 0000000000..1d7c6ad529 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_add_f32.c +* +* Description: Floating-point vector addition. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup BasicAdd Vector Addition + * + * Element-by-element addition of two vectors. + * + * 
       
+ *     pDst[n] = pSrcA[n] + pSrcB[n],   0 <= n < blockSize.   
+ *
    + * + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup BasicAdd + * @{ + */ + +/** + * @brief Floating-point vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_add_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (*pSrcA++) + (*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicAdd group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c new file mode 100644 index 0000000000..e3a2812005 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c @@ -0,0 +1,127 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_add_q15.c +* +* Description: Q15 vector addition +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAdd + * @{ + */ + +/** + * @brief Q15 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_add_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++); + *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (q15_t) __QADD16(*pSrcA++, *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ + *pSrcB++), 16); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + + +} + +/** + * @} end of BasicAdd group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c new file mode 100644 index 0000000000..58f99d9a21 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c @@ -0,0 +1,129 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_add_q31.c +* +* Description: Q31 vector addition. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAdd + * @{ + */ + + +/** + * @brief Q31 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. + */ + +void arm_add_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = __QADD(*pSrcA++, *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ + *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of BasicAdd group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c new file mode 100644 index 0000000000..c6f4f92fbb --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_add_q7.c +* +* Description: Q7 vector addition. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicAdd + * @{ + */ + +/** + * @brief Q7 vector addition. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_add_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (q7_t) __SSAT(*pSrcA++ + *pSrcB++, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A + B */ + /* Add and then store the results in the destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ + *pSrcB++, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + + +} + +/** + * @} end of BasicAdd group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c new file mode 100644 index 0000000000..ea82aa375b --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_dot_prod_f32.c +* +* Description: Floating-point dot product. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup dot_prod Vector Dot Product + * + * Computes the dot product of two vectors. + * The vectors are multiplied element-by-element and then summed. + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup dot_prod + * @{ + */ + +/** + * @brief Dot product of floating-point vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + */ + + +void arm_dot_prod_f32( + float32_t * pSrcA, + float32_t * pSrcB, + uint32_t blockSize, + float32_t * result) +{ + float32_t sum = 0.0f; /* Temporary result storage */ + uint32_t blkCnt; /* loop counter */ + + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer */ + sum += (*pSrcA++) * (*pSrcB++); + sum += (*pSrcA++) * (*pSrcB++); + sum += (*pSrcA++) * (*pSrcB++); + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + sum += (*pSrcA++) * (*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + /* Store the result back in the destination buffer */ + *result = sum; +} + +/** + * @} end of dot_prod group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c new file mode 100644 index 0000000000..32bfdbc1ab --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c @@ -0,0 +1,132 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_dot_prod_q15.c +* +* Description: Q15 dot product. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup dot_prod + * @{ + */ + +/** + * @brief Dot product of Q15 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The intermediate multiplications are in 1.15 x 1.15 = 2.30 format and these + * results are added to a 64-bit accumulator in 34.30 format. + * Nonsaturating additions are used and given that there are 33 guard bits in the accumulator + * there is no risk of overflow. + * The return result is in 34.30 format. + */ + +void arm_dot_prod_q15( + q15_t * pSrcA, + q15_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + q63_t sum = 0; /* Temporary result storage */ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum); + sum = __SMLALD(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++, sum); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the results in a temporary buffer. */ + sum = __SMLALD(*pSrcA++, *pSrcB++, sum); + + /* Decrement the loop counter */ + blkCnt--; + } + + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the results in a temporary buffer. */ + sum += (q63_t) ((q31_t) * pSrcA++ * *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + + /* Store the result in the destination buffer in 34.30 format */ + *result = sum; + +} + +/** + * @} end of dot_prod group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c new file mode 100644 index 0000000000..eb674c359a --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c @@ -0,0 +1,124 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_dot_prod_q31.c +* +* Description: Q31 dot product. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup dot_prod + * @{ + */ + +/** + * @brief Dot product of Q31 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The intermediate multiplications are in 1.31 x 1.31 = 2.62 format and these + * are truncated to 2.48 format by discarding the lower 14 bits. + * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format. + * There are 15 guard bits in the accumulator and there is no risk of overflow as long as + * the length of the vectors is less than 2^16 elements. + * The return result is in 16.48 format. + */ + +void arm_dot_prod_q31( + q31_t * pSrcA, + q31_t * pSrcB, + uint32_t blockSize, + q63_t * result) +{ + q63_t sum = 0; /* Temporary result storage */ + uint32_t blkCnt; /* loop counter */ + + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u; + sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u; + sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u; + sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Calculate dot product and then store the result in a temporary buffer. */ + sum += ((q63_t) * pSrcA++ * *pSrcB++) >> 14u; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* Store the result in the destination buffer in 16.48 format */ + *result = sum; +} + +/** + * @} end of dot_prod group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c new file mode 100644 index 0000000000..0892732188 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c @@ -0,0 +1,163 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_dot_prod_q7.c +* +* Description: Q7 dot product. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup dot_prod + * @{ + */ + +/** + * @brief Dot product of Q7 vectors. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[in] blockSize number of samples in each vector + * @param[out] *result output result returned here + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The intermediate multiplications are in 1.7 x 1.7 = 2.14 format and these + * results are added to an accumulator in 18.14 format. + * Nonsaturating additions are used and there is no danger of wrap around as long as + * the vectors are less than 2^18 elements long. + * The return result is in 18.14 format. + */ + +void arm_dot_prod_q7( + q7_t * pSrcA, + q7_t * pSrcB, + uint32_t blockSize, + q31_t * result) +{ + uint32_t blkCnt; /* loop counter */ + + q31_t sum = 0; /* Temporary variables to store output */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + q31_t input1, input2; /* Temporary variables to store input */ + q15_t in1, in2; /* Temporary variables to store input */ + + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) * pSrcA++; + in2 = (q15_t) * pSrcA++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) * pSrcB++; + in2 = (q15_t) * pSrcB++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Perform Dot product of 2 packed inputs using SMLALD and store the result in a temporary variable. */ + sum = __SMLAD(input1, input2, sum); + + /* Reading two inputs of SrcA buffer and packing */ + in1 = (q15_t) * pSrcA++; + in2 = (q15_t) * pSrcA++; + input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* Reading two inputs of SrcB buffer and packing */ + in1 = (q15_t) * pSrcB++; + in2 = (q15_t) * pSrcB++; + input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16); + + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Perform Dot product of 2 packed inputs using SMLALD and store the result in a temporary variable. */ + sum = __SMLAD(input1, input2, sum); + + + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Dot product and then store the results in a temporary buffer. */ + sum = __SMLAD(*pSrcA++, *pSrcB++, sum); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A[0]* B[0] + A[1]* B[1] + A[2]* B[2] + .....+ A[blockSize-1]* B[blockSize-1] */ + /* Dot product and then store the results in a temporary buffer. */ + sum += (q31_t) ((q15_t) * pSrcA++ * *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + + + /* Store the result in the destination buffer in 18.14 format */ + *result = sum; +} + +/** + * @} end of dot_prod group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c new file mode 100644 index 0000000000..7b555638ba --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_mult_f32.c +* +* Description: Floating-point vector multiplication. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.5 2010/04/26 +* incorporated review comments and updated with latest CMSIS layer +* +* Version 0.0.3 2010/03/10 +* Initial version +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup BasicMult Vector Multiplication + * + * Element-by-element multiplication of two vectors. + * + * 
       
+ *     pDst[n] = pSrcA[n] * pSrcB[n],   0 <= n < blockSize.   
+ *
    + * + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup BasicMult + * @{ + */ + +/** + * @brief Floating-point vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_mult_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + /* loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and store the results in output buffer */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + *pDst++ = (*pSrcA++) * (*pSrcB++); + *pDst++ = (*pSrcA++) * (*pSrcB++); + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and store the results in output buffer */ + *pDst++ = (*pSrcA++) * (*pSrcB++); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + +} + +/** + * @} end of BasicMult group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c new file mode 100644 index 0000000000..e9728f8477 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c @@ -0,0 +1,119 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_mult_q15.c +* +* Description: Q15 vector multiplication. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.5 2010/04/26 +* incorporated review comments and updated with latest CMSIS layer +* +* Version 0.0.3 2010/03/10 +* Initial version +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicMult + * @{ + */ + + +/** + * @brief Q15 vector multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_mult_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + /* loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q15_t) __SSAT((((q31_t) (*pSrcA++) * (*pSrcB++)) >> 15), 16); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicMult group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c new file mode 100644 index 0000000000..8259a129d9 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c @@ -0,0 +1,121 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_mult_q31.c +* +* Description: Q31 vector multiplication. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.5 2010/04/26 +* incorporated review comments and updated with latest CMSIS layer +* +* Version 0.0.3 2010/03/10 +* Initial version +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicMult + * @{ + */ + +/** + * @brief Q31 vector multiplication. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated. + */ + +void arm_mult_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + /* loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and then store the results in the destination buffer. */ + *pDst++ = + (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31); + *pDst++ = + (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31); + *pDst++ = + (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31); + *pDst++ = + (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and then store the results in the destination buffer. */ + *pDst++ = + (q31_t) clip_q63_to_q31(((q63_t) (*pSrcA++) * (*pSrcB++)) >> 31); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicMult group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c new file mode 100644 index 0000000000..75f075a1f3 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c @@ -0,0 +1,125 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_mult_q7.c +* +* Description: Q7 vector multiplication. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* +* Version 0.0.5 2010/04/26 +* incorporated review comments and updated with latest CMSIS layer +* +* Version 0.0.3 2010/03/10 DP +* Initial version +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicMult + * @{ + */ + +/** + * @brief Q7 vector multiplication + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_mult_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counters */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q7_t out1, out2, out3, out4; /* Temporary variables to store the product */ + + /* loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and store the results in temporary variables */ + out1 = (q7_t) (((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7); + out2 = (q7_t) (((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7); + out3 = (q7_t) (((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7); + out4 = (q7_t) (((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7); + + /* Store the results of 4 inputs in the destination buffer in single cycle by packing */ + *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = A * B */ + /* Multiply the inputs and store the result in the destination buffer */ + *pDst++ = (q7_t) (((q15_t) (*pSrcA++) * (*pSrcB++)) >> 7); + + /* Decrement the blockSize loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicMult group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c new file mode 100644 index 0000000000..265f50ffd8 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c @@ -0,0 +1,117 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_negate_f32.c +* +* Description: Negates floating-point vectors. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup negate Vector Negate + * + * Negates the elements of a vector. + * + * 
       
+ *     pDst[n] = -pSrc[n],   0 <= n < blockSize.   
+ *
    + */ + +/** + * @addtogroup negate + * @{ + */ + +/** + * @brief Negates the elements of a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + +void arm_negate_f32( + float32_t * pSrc, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = -A */ + /* Negate and then store the results in the destination buffer. */ + *pDst++ = -*pSrc++; + *pDst++ = -*pSrc++; + *pDst++ = -*pSrc++; + *pDst++ = -*pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = -A */ + /* Negate and then store the results in the destination buffer. */ + *pDst++ = -*pSrc++; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of negate group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c new file mode 100644 index 0000000000..21122488e4 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c @@ -0,0 +1,140 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_negate_q15.c +* +* Description: Negates Q15 vectors. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup negate + * @{ + */ + +/** + * @brief Negates the elements of a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF. + */ + +void arm_negate_q15( + q15_t * pSrc, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + q15_t in1, in2; /* Temporary variables */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = -A */ + /* Read two inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + /* Negate and then store the results in the destination buffer by packing. */ + +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT(__SSAT(-in1, 16), __SSAT(-in2, 16), 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT(__SSAT(-in2, 16), __SSAT(-in1, 16), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = *pSrc++; + in2 = *pSrc++; + +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT(__SSAT(-in1, 16), __SSAT(-in2, 16), 16); + +#else + + + *__SIMD32(pDst)++ = __PKHBT(__SSAT(-in2, 16), __SSAT(-in1, 16), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = -A */ + /* Negate and then store the result in the destination buffer. */ + *pDst++ = __SSAT(-*pSrc++, 16); + + /* Decrement the loop counter */ + blkCnt--; + } + +} + +/** + * @} end of negate group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c new file mode 100644 index 0000000000..f7de456e52 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c @@ -0,0 +1,119 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_negate_q31.c +* +* Description: Negates Q31 vectors. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup negate + * @{ + */ + +/** + * @brief Negates the elements of a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF. + */ + +void arm_negate_q31( + q31_t * pSrc, + q31_t * pDst, + uint32_t blockSize) +{ + q31_t in; /* Temporary variable */ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = -A */ + /* Negate and then store the results in the destination buffer. */ + in = *pSrc++; + *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in; + in = *pSrc++; + *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in; + in = *pSrc++; + *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in; + in = *pSrc++; + *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = -A */ + /* Negate and then store the result in the destination buffer. */ + in = *pSrc++; + *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of negate group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c new file mode 100644 index 0000000000..795b047ff5 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_negate_q7.c +* +* Description: Negates Q7 vectors. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup negate + * @{ + */ + +/** + * @brief Negates the elements of a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * The Q7 value -1 (0x80) will be saturated to the maximum allowable positive value 0x7F. + */ + +void arm_negate_q7( + q7_t * pSrc, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q7_t in1; /* Input value1 */ + q7_t in2; /* Input value2 */ + q7_t in3; /* Input value3 */ + q7_t in4; /* Input value4 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = -A */ + /* Read four inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Store the Negated results in the destination buffer in a single cycle by packing the results */ + *__SIMD32(pDst)++ = + __PACKq7(__SSAT(-in1, 8), __SSAT(-in2, 8), __SSAT(-in3, 8), + __SSAT(-in4, 8)); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = -A */ + /* Negate and then store the results in the destination buffer. */ + *pDst++ = __SSAT(-*pSrc++, 8); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of negate group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c new file mode 100644 index 0000000000..04ec1fac76 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_offset_f32.c +* +* Description: Floating-point vector offset. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup offset Vector Offset + * + * Adds a constant offset to each element of a vector. + * + * 
       
+ *     pDst[n] = pSrc[n] + offset,   0 <= n < blockSize.   
+ *
    + * + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup offset + * @{ + */ + +/** + * @brief Adds a constant offset to a floating-point vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + +void arm_offset_f32( + float32_t * pSrc, + float32_t offset, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination buffer. */ + *pDst++ = (*pSrc++) + offset; + *pDst++ = (*pSrc++) + offset; + *pDst++ = (*pSrc++) + offset; + *pDst++ = (*pSrc++) + offset; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the result in the destination buffer. */ + *pDst++ = (*pSrc++) + offset; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of offset group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c new file mode 100644 index 0000000000..e9106f3229 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c @@ -0,0 +1,128 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_offset_q15.c +* +* Description: Q15 vector offset. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup offset + * @{ + */ + +/** + * @brief Adds a constant offset to a Q15 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] are saturated. + */ + +void arm_offset_q15( + q15_t * pSrc, + q15_t offset, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t offset_packed; /* Offset packed to 32 bit */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* Offset is packed to 32 bit in order to use SIMD32 for addition */ + offset_packed = __PKHBT(offset, offset, 16); + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination buffer, 2 samples at a time. */ + *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed); + *__SIMD32(pDst)++ = __QADD16(*__SIMD32(pSrc)++, offset_packed); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination buffer. */ + *pDst++ = (q15_t) __QADD16(*pSrc++, offset); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination buffer. */ + *pDst++ = (q15_t) __SSAT(((q31_t) * pSrc++ + offset), 16); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of offset group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c new file mode 100644 index 0000000000..ff0f6f786c --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c @@ -0,0 +1,126 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_offset_q31.c +* +* Description: Q31 vector offset. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup offset + * @{ + */ + +/** + * @brief Adds a constant offset to a Q31 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] are saturated. + */ + +void arm_offset_q31( + q31_t * pSrc, + q31_t offset, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination buffer. */ + *pDst++ = __QADD(*pSrc++, offset); + *pDst++ = __QADD(*pSrc++, offset); + *pDst++ = __QADD(*pSrc++, offset); + *pDst++ = __QADD(*pSrc++, offset); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the result in the destination buffer. */ + *pDst++ = __QADD(*pSrc++, offset); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the result in the destination buffer. */ + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrc++ + offset); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of offset group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c new file mode 100644 index 0000000000..7526648a2b --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c @@ -0,0 +1,127 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_offset_q7.c +* +* Description: Q7 vector offset. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup offset + * @{ + */ + +/** + * @brief Adds a constant offset to a Q7 vector. + * @param[in] *pSrc points to the input vector + * @param[in] offset is the offset to be added + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] are saturated. + */ + +void arm_offset_q7( + q7_t * pSrc, + q7_t offset, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q31_t offset_packed; /* Offset packed to 32 bit */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* Offset is packed to 32 bit in order to use SIMD32 for addition */ + offset_packed = __PACKq7(offset, offset, offset, offset); + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the results in the destination bufferfor 4 samples at a time. */ + *__SIMD32(pDst)++ = __QADD8(*__SIMD32(pSrc)++, offset_packed); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the result in the destination buffer. */ + *pDst++ = (q7_t) __SSAT(*pSrc++ + offset, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A + offset */ + /* Add offset and then store the result in the destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) * pSrc++ + offset, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of offset group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c new file mode 100644 index 0000000000..cf516ad7c0 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c @@ -0,0 +1,133 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_scale_f32.c +* +* Description: Multiplies a floating-point vector by a scalar. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup scale Vector Scale + * + * Multiply a vector by a scalar value. For floating-point data, the algorithm used is: + * + * 
       
+ *     pDst[n] = pSrc[n] * scale,   0 <= n < blockSize.   
+ *
    + * + * In the fixed-point Q7, Q15, and Q31 functions, scale is represented by + * a fractional multiplication scaleFract and an arithmetic shift shift. + * The shift allows the gain of the scaling operation to exceed 1.0. + * The algorithm used with fixed-point data is: + * + * 
       
+ *     pDst[n] = (pSrc[n] * scaleFract) << shift,   0 <= n < blockSize.   
+ *
    + * + * The overall scale factor applied to the fixed-point data is + * 
       
+ *     scale = scaleFract * 2^shift.   
+ *
    + */ + +/** + * @addtogroup scale + * @{ + */ + +/** + * @brief Multiplies a floating-point vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scale scale factor to be applied + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + */ + + +void arm_scale_f32( + float32_t * pSrc, + float32_t scale, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the results in the destination buffer. */ + *pDst++ = (*pSrc++) * scale; + *pDst++ = (*pSrc++) * scale; + *pDst++ = (*pSrc++) * scale; + *pDst++ = (*pSrc++) * scale; + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = (*pSrc++) * scale; + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of scale group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c new file mode 100644 index 0000000000..ac3f5bb8f4 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c @@ -0,0 +1,162 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_scale_q15.c +* +* Description: Multiplies a Q15 vector by a scalar. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup scale + * @{ + */ + +/** + * @brief Multiplies a Q15 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The input data *pSrc and scaleFract are in 1.15 format. + * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format. + */ + + +void arm_scale_q15( + q15_t * pSrc, + q15_t scaleFract, + int8_t shift, + q15_t * pDst, + uint32_t blockSize) +{ + int8_t kShift = 15 - shift; /* shift to apply after scaling */ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + q15_t in1, in2; /* Temporary variables */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* Reading 2 inputs from memory */ + in1 = *pSrc++; + in2 = *pSrc++; + /* C = A * scale */ + /* Scale the inputs and then store the 2 results in the destination buffer + * in single cycle by packing the outputs */ +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = + __PKHBT(__SSAT((in1 * scaleFract) >> kShift, 16), + __SSAT((in2 * scaleFract) >> kShift, 16), 16); + +#else + + *__SIMD32(pDst)++ = + __PKHBT(__SSAT((in2 * scaleFract) >> kShift, 16), + __SSAT((in1 * scaleFract) >> kShift, 16), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = *pSrc++; + in2 = *pSrc++; + +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = + __PKHBT(__SSAT((in1 * scaleFract) >> kShift, 16), + __SSAT((in2 * scaleFract) >> kShift, 16), 16); + +#else + + *__SIMD32(pDst)++ = + __PKHBT(__SSAT((in2 * scaleFract) >> kShift, 16), + __SSAT((in1 * scaleFract) >> kShift, 16), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 16)); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = (q15_t) (__SSAT(((q31_t) * pSrc++ * scaleFract) >> kShift, 16)); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of scale group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c new file mode 100644 index 0000000000..c265eedd74 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c @@ -0,0 +1,117 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_scale_q31.c +* +* Description: Multiplies a Q31 vector by a scalar. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup scale + * @{ + */ + +/** + * @brief Multiplies a Q31 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The input data *pSrc and scaleFract are in 1.31 format. + * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format. + */ + +void arm_scale_q31( + q31_t * pSrc, + q31_t scaleFract, + int8_t shift, + q31_t * pDst, + uint32_t blockSize) +{ + int8_t kShift = 31 - shift; /* Shift to apply after scaling */ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the results in the destination buffer. */ + *pDst++ = clip_q63_to_q31(((q63_t) * pSrc++ * scaleFract) >> kShift); + *pDst++ = clip_q63_to_q31(((q63_t) * pSrc++ * scaleFract) >> kShift); + *pDst++ = clip_q63_to_q31(((q63_t) * pSrc++ * scaleFract) >> kShift); + *pDst++ = clip_q63_to_q31(((q63_t) * pSrc++ * scaleFract) >> kShift); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = clip_q63_to_q31(((q63_t) * pSrc++ * scaleFract) >> kShift); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of scale group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c new file mode 100644 index 0000000000..743d205078 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c @@ -0,0 +1,141 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_scale_q7.c +* +* Description: Multiplies a Q7 vector by a scalar. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup scale + * @{ + */ + +/** + * @brief Multiplies a Q7 vector by a scalar. + * @param[in] *pSrc points to the input vector + * @param[in] scaleFract fractional portion of the scale value + * @param[in] shift number of bits to shift the result by + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The input data *pSrc and scaleFract are in 1.7 format. + * These are multiplied to yield a 2.14 intermediate result and this is shifted with saturation to 1.7 format. + */ + +void arm_scale_q7( + q7_t * pSrc, + q7_t scaleFract, + int8_t shift, + q7_t * pDst, + uint32_t blockSize) +{ + int8_t kShift = 7 - shift; /* shift to apply after scaling */ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q7_t in1, in2, in3, in4, out1, out2, out3, out4; /* Temporary variables to store input & output */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* Reading 4 inputs from memory */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* C = A * scale */ + /* Scale the inputs and then store the results in the temporary variables. */ + out1 = (q7_t) (__SSAT(((in1) * scaleFract) >> kShift, 8)); + out2 = (q7_t) (__SSAT(((in2) * scaleFract) >> kShift, 8)); + out3 = (q7_t) (__SSAT(((in3) * scaleFract) >> kShift, 8)); + out4 = (q7_t) (__SSAT(((in4) * scaleFract) >> kShift, 8)); + + /* Packing the individual outputs into 32bit and storing in + * destination buffer in single write */ + *__SIMD32(pDst)++ = __PACKq7(out1, out2, out3, out4); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = (q7_t) (__SSAT(((*pSrc++) * scaleFract) >> kShift, 8)); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A * scale */ + /* Scale the input and then store the result in the destination buffer. */ + *pDst++ = (q7_t) (__SSAT((((q15_t) * pSrc++ * scaleFract) >> kShift), 8)); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of scale group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c new file mode 100644 index 0000000000..3dc6ac5340 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c @@ -0,0 +1,239 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_shift_q15.c +* +* Description: Shifts the elements of a Q15 vector by a specified number of bits. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup shift + * @{ + */ + +/** + * @brief Shifts the elements of a Q15 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_shift_q15( + q15_t * pSrc, + int8_t shiftBits, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + uint8_t sign; /* Sign of shiftBits */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + q15_t in1, in2; /* Temporary variables */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* Getting the sign of shiftBits */ + sign = (shiftBits & 0x80); + + /* If the shift value is positive then do right shift else left shift */ + if(sign == 0u) + { + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* Read 2 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + /* C = A << shiftBits */ + /* Shift the inputs and then store the results in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16), + __SSAT((in2 << shiftBits), 16), 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16), + __SSAT((in1 << shiftBits), 16), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = *pSrc++; + in2 = *pSrc++; + +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT(__SSAT((in1 << shiftBits), 16), + __SSAT((in2 << shiftBits), 16), 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT(__SSAT((in2 << shiftBits), 16), + __SSAT((in1 << shiftBits), 16), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A << shiftBits */ + /* Shift and then store the results in the destination buffer. */ + *pDst++ = __SSAT((*pSrc++ << shiftBits), 16); + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* Read 2 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + /* C = A >> shiftBits */ + /* Shift the inputs and then store the results in the destination buffer. */ +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits), + (in2 >> -shiftBits), 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits), + (in1 >> -shiftBits), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + in1 = *pSrc++; + in2 = *pSrc++; + +#ifndef ARM_MATH_BIG_ENDIAN + + *__SIMD32(pDst)++ = __PKHBT((in1 >> -shiftBits), + (in2 >> -shiftBits), 16); + +#else + + *__SIMD32(pDst)++ = __PKHBT((in2 >> -shiftBits), + (in1 >> -shiftBits), 16); + +#endif /* #ifndef ARM_MATH_BIG_ENDIAN */ + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A >> shiftBits */ + /* Shift the inputs and then store the results in the destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Getting the sign of shiftBits */ + sign = (shiftBits & 0x80); + + /* If the shift value is positive then do right shift else left shift */ + if(sign == 0u) + { + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A << shiftBits */ + /* Shift and then store the results in the destination buffer. */ + *pDst++ = __SSAT(((q31_t) * pSrc++ << shiftBits), 16); + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A >> shiftBits */ + /* Shift the inputs and then store the results in the destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of shift group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c new file mode 100644 index 0000000000..8fb989c788 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c @@ -0,0 +1,141 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_shift_q31.c +* +* Description: Shifts the elements of a Q31 vector by a specified number of bits. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ +/** + * @defgroup shift Vector Shift + * + * Shifts the elements of a fixed-point vector by a specified number of bits. + * There are separate functions for Q7, Q15, and Q31 data types. + * The underlying algorithm used is: + * + * 
       
+ *     pDst[n] = pSrc[n] << shift,   0 <= n < blockSize.   
+ *
    + * + * If shift is positive then the elements of the vector are shifted to the left. + * If shift is negative then the elements of the vector are shifted to the right. + */ + +/** + * @addtogroup shift + * @{ + */ + +/** + * @brief Shifts the elements of a Q31 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. + */ + +void arm_shift_q31( + q31_t * pSrc, + int8_t shiftBits, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + uint8_t sign; /* Sign of shiftBits */ + /* Getting the sign of shiftBits */ + sign = (shiftBits & 0x80); + + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A (>> or <<) shiftBits */ + /* Shift the input and then store the results in the destination buffer. */ + *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) : + (*pSrc++ >> -shiftBits); + *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) : + (*pSrc++ >> -shiftBits); + *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) : + (*pSrc++ >> -shiftBits); + *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) : + (*pSrc++ >> -shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = A (>> or <<) shiftBits */ + /* Shift the input and then store the result in the destination buffer. */ + *pDst++ = (sign == 0u) ? clip_q63_to_q31((q63_t) * pSrc++ << shiftBits) : + (*pSrc++ >> -shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + +} + +/** + * @} end of shift group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c new file mode 100644 index 0000000000..f65e244cf9 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c @@ -0,0 +1,202 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_shift_q7.c +* +* Description: Processing function for the Q7 Shifting +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup shift + * @{ + */ + + +/** + * @brief Shifts the elements of a Q7 vector a specified number of bits. + * @param[in] *pSrc points to the input vector + * @param[in] shiftBits number of bits to shift. A positive value shifts left; a negative value shifts right. + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in the vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x8 0x7F] will be saturated. + */ + +void arm_shift_q7( + q7_t * pSrc, + int8_t shiftBits, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + uint8_t sign; /* Sign of shiftBits */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + q7_t in1; /* Input value1 */ + q7_t in2; /* Input value2 */ + q7_t in3; /* Input value3 */ + q7_t in4; /* Input value4 */ + + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* Getting the sign of shiftBits */ + sign = (shiftBits & 0x80); + + /* If the shift value is positive then do right shift else left shift */ + if(sign == 0u) + { + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A << shiftBits */ + /* Read 4 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */ + *__SIMD32(pDst)++ = __PACKq7(__SSAT((in1 << shiftBits), 8), + __SSAT((in2 << shiftBits), 8), + __SSAT((in3 << shiftBits), 8), + __SSAT((in4 << shiftBits), 8)); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A << shiftBits */ + /* Shift the input and then store the result in the destination buffer. */ + *pDst++ = (q7_t) __SSAT((*pSrc++ << shiftBits), 8); + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A >> shiftBits */ + /* Read 4 inputs */ + in1 = *pSrc++; + in2 = *pSrc++; + in3 = *pSrc++; + in4 = *pSrc++; + + /* Store the Shifted result in the destination buffer in single cycle by packing the outputs */ + *__SIMD32(pDst)++ = __PACKq7((in1 >> -shiftBits), (in2 >> -shiftBits), + (in3 >> -shiftBits), (in4 >> -shiftBits)); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A >> shiftBits */ + /* Shift the input and then store the result in the destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Getting the sign of shiftBits */ + sign = (shiftBits & 0x80); + + /* If the shift value is positive then do right shift else left shift */ + if(sign == 0u) + { + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A << shiftBits */ + /* Shift the input and then store the result in the destination buffer. */ + *pDst++ = (q7_t) __SSAT(((q15_t) * pSrc++ << shiftBits), 8); + + /* Decrement the loop counter */ + blkCnt--; + } + } + else + { + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A >> shiftBits */ + /* Shift the input and then store the result in the destination buffer. */ + *pDst++ = (*pSrc++ >> -shiftBits); + + /* Decrement the loop counter */ + blkCnt--; + } + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of shift group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c new file mode 100644 index 0000000000..b09e7d440b --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c @@ -0,0 +1,122 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_sub_f32.c +* +* Description: Floating-point vector subtraction. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @defgroup BasicSub Vector Subtraction + * + * Element-by-element subtraction of two vectors. + * + * 
       
+ *     pDst[n] = pSrcA[n] - pSrcB[n],   0 <= n < blockSize.   
+ *
    + * + * There are separate functions for floating-point, Q7, Q15, and Q31 data types. + */ + +/** + * @addtogroup BasicSub + * @{ + */ + + +/** + * @brief Floating-point vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + */ + +void arm_sub_f32( + float32_t * pSrcA, + float32_t * pSrcB, + float32_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the results in the destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + *pDst++ = (*pSrcA++) - (*pSrcB++); + *pDst++ = (*pSrcA++) - (*pSrcB++); + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + +#endif /* #ifndef ARM_MATH_CM0 */ + + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the results in the destination buffer. */ + *pDst++ = (*pSrcA++) - (*pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } +} + +/** + * @} end of BasicSub group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c new file mode 100644 index 0000000000..2844951b4e --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c @@ -0,0 +1,124 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_sub_q15.c +* +* Description: Q15 vector subtraction. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicSub + * @{ + */ + +/** + * @brief Q15 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated. + */ + +void arm_sub_q15( + q15_t * pSrcA, + q15_t * pSrcB, + q15_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the results in the destination buffer two samples at a time. */ + *__SIMD32(pDst)++ = __QSUB16(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++); + *__SIMD32(pDst)++ = __QSUB16(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = (q15_t) __QSUB16(*pSrcA++, *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = (q15_t) __SSAT(((q31_t) * pSrcA++ - *pSrcB++), 16); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + + +} + +/** + * @} end of BasicSub group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c new file mode 100644 index 0000000000..5ce8a106f3 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c @@ -0,0 +1,125 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_sub_q31.c +* +* Description: Q31 vector subtraction. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicSub + * @{ + */ + +/** + * @brief Q31 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated. + */ + +void arm_sub_q31( + q31_t * pSrcA, + q31_t * pSrcB, + q31_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the results in the destination buffer. */ + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = __QSUB(*pSrcA++, *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = (q31_t) clip_q63_to_q31((q63_t) * pSrcA++ - *pSrcB++); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + +} + +/** + * @} end of BasicSub group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c new file mode 100644 index 0000000000..5497c5a309 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c @@ -0,0 +1,123 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_sub_q7.c +* +* Description: Q7 vector subtraction. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* +* Version 0.0.7 2010/06/10 +* Misra-C changes done +* -------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupMath + */ + +/** + * @addtogroup BasicSub + * @{ + */ + +/** + * @brief Q7 vector subtraction. + * @param[in] *pSrcA points to the first input vector + * @param[in] *pSrcB points to the second input vector + * @param[out] *pDst points to the output vector + * @param[in] blockSize number of samples in each vector + * @return none. + * + * Scaling and Overflow Behavior: + * \par + * The function uses saturating arithmetic. + * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated. + */ + +void arm_sub_q7( + q7_t * pSrcA, + q7_t * pSrcB, + q7_t * pDst, + uint32_t blockSize) +{ + uint32_t blkCnt; /* loop counter */ + +#ifndef ARM_MATH_CM0 + +/* Run the below code for Cortex-M4 and Cortex-M3 */ + + /*loop Unrolling */ + blkCnt = blockSize >> 2u; + + /* First part of the processing with loop unrolling. Compute 4 outputs at a time. + ** a second loop below computes the remaining 1 to 3 samples. */ + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the results in the destination buffer 4 samples at a time. */ + *__SIMD32(pDst)++ = __QSUB8(*__SIMD32(pSrcA)++, *__SIMD32(pSrcB)++); + + /* Decrement the loop counter */ + blkCnt--; + } + + /* If the blockSize is not a multiple of 4, compute any remaining output samples here. + ** No loop unrolling is used. */ + blkCnt = blockSize % 0x4u; + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = __SSAT(*pSrcA++ - *pSrcB++, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#else + + /* Run the below code for Cortex-M0 */ + + /* Initialize blkCnt with number of samples */ + blkCnt = blockSize; + + while(blkCnt > 0u) + { + /* C = A - B */ + /* Subtract and then store the result in the destination buffer. */ + *pDst++ = (q7_t) __SSAT((q15_t) * pSrcA++ - *pSrcB++, 8); + + /* Decrement the loop counter */ + blkCnt--; + } + +#endif /* #ifndef ARM_MATH_CM0 */ + + +} + +/** + * @} end of BasicSub group + */ diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c new file mode 100644 index 0000000000..c1f1491f27 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c @@ -0,0 +1,144 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_common_tables.c +* +* Description: This file has common tables like Bitreverse, reciprocal etc which are used across different functions +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* -------------------------------------------------------------------- */ + + +#include "arm_math.h" + +/** + * @ingroup groupTransforms + */ + +/** + * @addtogroup CFFT_CIFFT + * @{ + */ + +/** +* \par +* Pseudo code for Generation of Bit reversal Table is +* \par +* 
    for(l=1;l <= N/4;l++)   
+* {   
+*   for(i=0;i> 1;   
+*  }
    +* \par +* where N = 1024 logN2 = 10 +* \par +* N is the maximum FFT Size supported +*/ + +/* +* @brief Table for bit reversal process +*/ +const uint16_t armBitRevTable[256] = { + 0x100, 0x80, 0x180, 0x40, 0x140, 0xc0, 0x1c0, + 0x20, 0x120, 0xa0, 0x1a0, 0x60, 0x160, 0xe0, + 0x1e0, 0x10, 0x110, 0x90, 0x190, 0x50, 0x150, + 0xd0, 0x1d0, 0x30, 0x130, 0xb0, 0x1b0, 0x70, + 0x170, 0xf0, 0x1f0, 0x8, 0x108, 0x88, 0x188, + 0x48, 0x148, 0xc8, 0x1c8, 0x28, 0x128, 0xa8, + 0x1a8, 0x68, 0x168, 0xe8, 0x1e8, 0x18, 0x118, + 0x98, 0x198, 0x58, 0x158, 0xd8, 0x1d8, 0x38, + 0x138, 0xb8, 0x1b8, 0x78, 0x178, 0xf8, 0x1f8, + 0x4, 0x104, 0x84, 0x184, 0x44, 0x144, 0xc4, + 0x1c4, 0x24, 0x124, 0xa4, 0x1a4, 0x64, 0x164, + 0xe4, 0x1e4, 0x14, 0x114, 0x94, 0x194, 0x54, + 0x154, 0xd4, 0x1d4, 0x34, 0x134, 0xb4, 0x1b4, + 0x74, 0x174, 0xf4, 0x1f4, 0xc, 0x10c, 0x8c, + 0x18c, 0x4c, 0x14c, 0xcc, 0x1cc, 0x2c, 0x12c, + 0xac, 0x1ac, 0x6c, 0x16c, 0xec, 0x1ec, 0x1c, + 0x11c, 0x9c, 0x19c, 0x5c, 0x15c, 0xdc, 0x1dc, + 0x3c, 0x13c, 0xbc, 0x1bc, 0x7c, 0x17c, 0xfc, + 0x1fc, 0x2, 0x102, 0x82, 0x182, 0x42, 0x142, + 0xc2, 0x1c2, 0x22, 0x122, 0xa2, 0x1a2, 0x62, + 0x162, 0xe2, 0x1e2, 0x12, 0x112, 0x92, 0x192, + 0x52, 0x152, 0xd2, 0x1d2, 0x32, 0x132, 0xb2, + 0x1b2, 0x72, 0x172, 0xf2, 0x1f2, 0xa, 0x10a, + 0x8a, 0x18a, 0x4a, 0x14a, 0xca, 0x1ca, 0x2a, + 0x12a, 0xaa, 0x1aa, 0x6a, 0x16a, 0xea, 0x1ea, + 0x1a, 0x11a, 0x9a, 0x19a, 0x5a, 0x15a, 0xda, + 0x1da, 0x3a, 0x13a, 0xba, 0x1ba, 0x7a, 0x17a, + 0xfa, 0x1fa, 0x6, 0x106, 0x86, 0x186, 0x46, + 0x146, 0xc6, 0x1c6, 0x26, 0x126, 0xa6, 0x1a6, + 0x66, 0x166, 0xe6, 0x1e6, 0x16, 0x116, 0x96, + 0x196, 0x56, 0x156, 0xd6, 0x1d6, 0x36, 0x136, + 0xb6, 0x1b6, 0x76, 0x176, 0xf6, 0x1f6, 0xe, + 0x10e, 0x8e, 0x18e, 0x4e, 0x14e, 0xce, 0x1ce, + 0x2e, 0x12e, 0xae, 0x1ae, 0x6e, 0x16e, 0xee, + 0x1ee, 0x1e, 0x11e, 0x9e, 0x19e, 0x5e, 0x15e, + 0xde, 0x1de, 0x3e, 0x13e, 0xbe, 0x1be, 0x7e, + 0x17e, 0xfe, 0x1fe, 0x1 +}; + +/** + * @} end of CFFT_CIFFT group + */ + +/* +* @brief Q15 table for reciprocal +*/ +const q15_t armRecipTableQ15[64] = { + 0x7F03, 0x7D13, 0x7B31, 0x795E, 0x7798, 0x75E0, + 0x7434, 0x7294, 0x70FF, 0x6F76, 0x6DF6, 0x6C82, + 0x6B16, 0x69B5, 0x685C, 0x670C, 0x65C4, 0x6484, + 0x634C, 0x621C, 0x60F3, 0x5FD0, 0x5EB5, 0x5DA0, + 0x5C91, 0x5B88, 0x5A85, 0x5988, 0x5890, 0x579E, + 0x56B0, 0x55C8, 0x54E4, 0x5405, 0x532B, 0x5255, + 0x5183, 0x50B6, 0x4FEC, 0x4F26, 0x4E64, 0x4DA6, + 0x4CEC, 0x4C34, 0x4B81, 0x4AD0, 0x4A23, 0x4978, + 0x48D1, 0x482D, 0x478C, 0x46ED, 0x4651, 0x45B8, + 0x4521, 0x448D, 0x43FC, 0x436C, 0x42DF, 0x4255, + 0x41CC, 0x4146, 0x40C2, 0x4040 +}; + +/* +* @brief Q31 table for reciprocal +*/ +const q31_t armRecipTableQ31[64] = { + 0x7F03F03F, 0x7D137420, 0x7B31E739, 0x795E9F94, 0x7798FD29, 0x75E06928, + 0x7434554D, 0x72943B4B, 0x70FF9C40, 0x6F760031, 0x6DF6F593, 0x6C8210E3, + 0x6B16EC3A, 0x69B526F6, 0x685C655F, 0x670C505D, 0x65C4952D, 0x6484E519, + 0x634CF53E, 0x621C7E4F, 0x60F33C61, 0x5FD0EEB3, 0x5EB55785, 0x5DA03BEB, + 0x5C9163A1, 0x5B8898E6, 0x5A85A85A, 0x598860DF, 0x58909373, 0x579E1318, + 0x56B0B4B8, 0x55C84F0B, 0x54E4BA80, 0x5405D124, 0x532B6E8F, 0x52556FD0, + 0x5183B35A, 0x50B618F3, 0x4FEC81A2, 0x4F26CFA2, 0x4E64E64E, 0x4DA6AA1D, + 0x4CEC008B, 0x4C34D010, 0x4B810016, 0x4AD078EF, 0x4A2323C4, 0x4978EA96, + 0x48D1B827, 0x482D77FE, 0x478C1657, 0x46ED801D, 0x4651A2E5, 0x45B86CE2, + 0x4521CCE1, 0x448DB244, 0x43FC0CFA, 0x436CCD78, 0x42DFE4B4, 0x42554426, + 0x41CCDDB6, 0x4146A3C6, 0x40C28923, 0x40408102 +}; diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c new file mode 100644 index 0000000000..71cbc45f25 --- /dev/null +++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c @@ -0,0 +1,141 @@ +/* ---------------------------------------------------------------------- +* Copyright (C) 2010 ARM Limited. All rights reserved. +* +* $Date: 15. July 2011 +* $Revision: V1.0.10 +* +* Project: CMSIS DSP Library +* Title: arm_cmplx_conj_f32.c +* +* Description: Floating-point complex conjugate. +* +* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0 +* +* Version 1.0.10 2011/7/15 +* Big Endian support added and Merged M0 and M3/M4 Source code. +* +* Version 1.0.3 2010/11/29 +* Re-organized the CMSIS folders and updated documentation. +* +* Version 1.0.2 2010/11/11 +* Documentation updated. +* +* Version 1.0.1 2010/10/05 +* Production release and review comments incorporated. +* +* Version 1.0.0 2010/09/20 +* Production release and review comments incorporated. +* ---------------------------------------------------------------------------- */ + +#include "arm_math.h" + +/** + * @ingroup groupCmplxMath + */ + +/** + * @defgroup cmplx_conj Complex Conjugate + * + * Conjugates the elements of a complex data vector. + * + * The pSrc points to the source data and + * pDst points to the where the result should be written. + * numSamples specifies the number of complex samples + * and the data in each array is stored in an interleaved fashion + * (real, imag, real, imag, ...). + * Each array has a total of 2*numSamples values. + * The underlying algorithm is used: + * + * 
       
+ * for(n=0; n   
+ *   
+ * There are separate functions for floating-point, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup cmplx_conj   
+ * @{   
+ */
+
+/**   
+ * @brief  Floating-point complex conjugate.   
+ * @param  *pSrc points to the input vector   
+ * @param  *pDst points to the output vector   
+ * @param  numSamples number of complex samples in each vector   
+ * @return none.   
+ */
+
+void arm_cmplx_conj_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut + j (imagOut) = realIn + j (-1) imagIn */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_conj group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
new file mode 100644
index 0000000000..0a1897f751
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
@@ -0,0 +1,123 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_conj_q15.c   
+*   
+* Description:	Q15 complex conjugate.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_conj   
+ * @{   
+ */
+
+/**   
+ * @brief  Q15 complex conjugate.   
+ * @param  *pSrc points to the input vector   
+ * @param  *pDst points to the output vector   
+ * @param  numSamples number of complex samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * The Q15 value -1 (0x8000) will be saturated to the maximum allowable positive value 0x7FFF.   
+ */
+
+void arm_cmplx_conj_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = __SSAT(-*pSrc++, 16);
+    *pDst++ = *pSrc++;
+    *pDst++ = __SSAT(-*pSrc++, 16);
+    *pDst++ = *pSrc++;
+    *pDst++ = __SSAT(-*pSrc++, 16);
+    *pDst++ = *pSrc++;
+    *pDst++ = __SSAT(-*pSrc++, 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = __SSAT(-*pSrc++, 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut + j (imagOut) = realIn+ j (-1) imagIn */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_conj group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
new file mode 100644
index 0000000000..3eaa44e0c2
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
@@ -0,0 +1,131 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_conj_q31.c   
+*   
+* Description:	Q31 complex conjugate.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_conj   
+ * @{   
+ */
+
+/**   
+ * @brief  Q31 complex conjugate.   
+ * @param  *pSrc points to the input vector   
+ * @param  *pDst points to the output vector   
+ * @param  numSamples number of complex samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * The Q31 value -1 (0x80000000) will be saturated to the maximum allowable positive value 0x7FFFFFFF.   
+ */
+
+void arm_cmplx_conj_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+  q31_t in;                                      /* Input value */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0]+jC[1] = A[0]+ j (-1) A[1] */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    /* Saturated to 0x7fffffff if the input is -1(0x80000000) */
+    *pDst++ = *pSrc++;
+    in = *pSrc++;
+    *pDst++ = (in == 0x80000000) ? 0x7fffffff : -in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut + j (imagOut) = realIn+ j (-1) imagIn */
+    /* Calculate Complex Conjugate and then store the results in the destination buffer. */
+    *pDst++ = *pSrc++;
+    *pDst++ = -*pSrc++;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_conj group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
new file mode 100644
index 0000000000..15ab18b170
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_dot_prod_f32.c   
+*   
+* Description:	Floating-point complex dot product   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @defgroup cmplx_dot_prod Complex Dot Product   
+ *   
+ * Computes the dot product of two complex vectors.   
+ * The vectors are multiplied element-by-element and then summed.   
+ *  
+ * The pSrcA points to the first complex input vector and   
+ * pSrcB points to the second complex input vector.   
+ * numSamples specifies the number of complex samples   
+ * and the data in each array is stored in an interleaved fashion   
+ * (real, imag, real, imag, ...).   
+ * Each array has a total of 2*numSamples values.   
+ *   
+ * The underlying algorithm is used:   
+ * 
       
+ * realResult=0;   
+ * imagResult=0;   
+ * for(n=0; n   
+ *   
+ * There are separate functions for floating-point, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup cmplx_dot_prod   
+ * @{   
+ */
+
+/**   
+ * @brief  Floating-point complex dot product   
+ * @param  *pSrcA points to the first input vector   
+ * @param  *pSrcB points to the second input vector   
+ * @param  numSamples number of complex samples in each vector   
+ * @param  *realResult real part of the result returned here   
+ * @param  *imagResult imaginary part of the result returned here   
+ * @return none.   
+ */
+
+void arm_cmplx_dot_prod_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  uint32_t numSamples,
+  float32_t * realResult,
+  float32_t * imagResult)
+{
+  float32_t real_sum = 0.0f, imag_sum = 0.0f;    /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += (*pSrcA++) * (*pSrcB++);
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += (*pSrcA++) * (*pSrcB++);
+
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the real and imaginary results in the destination buffers */
+  *realResult = real_sum;
+  *imagResult = imag_sum;
+}
+
+/**   
+ * @} end of cmplx_dot_prod group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
new file mode 100644
index 0000000000..4194ed6f0a
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
@@ -0,0 +1,141 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_dot_prod_q15.c   
+*   
+* Description:	Processing function for the Q15 Complex Dot product   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_dot_prod   
+ * @{   
+ */
+
+/**   
+ * @brief  Q15 complex dot product   
+ * @param  *pSrcA points to the first input vector   
+ * @param  *pSrcB points to the second input vector   
+ * @param  numSamples number of complex samples in each vector   
+ * @param  *realResult real part of the result returned here   
+ * @param  *imagResult imaginary part of the result returned here   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The intermediate 1.15 by 1.15 multiplications are performed with full precision and yield a 2.30 result.   
+ * These are accumulated in a 64-bit accumulator with 34.30 precision.   
+ * As a final step, the accumulators are converted to 8.24 format.   
+ * The return results realResult and imagResult are in 8.24 format.   
+ */
+
+void arm_cmplx_dot_prod_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  uint32_t numSamples,
+  q31_t * realResult,
+  q31_t * imagResult)
+{
+  q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += ((q31_t) * pSrcA++ * *pSrcB++);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the real and imaginary results in 8.24 format  */
+  /* Convert real data in 34.30 to 8.24 by 6 right shifts */
+  *realResult = (q31_t) (real_sum) >> 6;
+  /* Convert imaginary data in 34.30 to 8.24 by 6 right shifts */
+  *imagResult = (q31_t) (imag_sum) >> 6;
+}
+
+/**   
+ * @} end of cmplx_dot_prod group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
new file mode 100644
index 0000000000..f6ad992cf1
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
@@ -0,0 +1,142 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_dot_prod_q31.c   
+*   
+* Description:	Q31 complex dot product   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_dot_prod   
+ * @{   
+ */
+
+/**   
+ * @brief  Q31 complex dot product   
+ * @param  *pSrcA points to the first input vector   
+ * @param  *pSrcB points to the second input vector   
+ * @param  numSamples number of complex samples in each vector   
+ * @param  *realResult real part of the result returned here   
+ * @param  *imagResult imaginary part of the result returned here   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The intermediate 1.31 by 1.31 multiplications are performed with 64-bit precision and then shifted to 16.48 format.   
+ * The internal real and imaginary accumulators are in 16.48 format and provide 15 guard bits.   
+ * Additions are nonsaturating and no overflow will occur as long as numSamples is less than 32768.   
+ * The return results realResult and imagResult are in 16.48 format.   
+ * Input down scaling is not required.   
+ */
+
+void arm_cmplx_dot_prod_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  uint32_t numSamples,
+  q63_t * realResult,
+  q63_t * imagResult)
+{
+  q63_t real_sum = 0, imag_sum = 0;              /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    /* Convert real data in 2.62 to 16.48 by 14 right shifts */
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    /* Convert imag data in 2.62 to 16.48 by 14 right shifts */
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples  is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* CReal = A[0]* B[0] + A[2]* B[2] + A[4]* B[4] + .....+ A[numSamples-2]* B[numSamples-2] */
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    /* CImag = A[1]* B[1] + A[3]* B[3] + A[5]* B[5] + .....+ A[numSamples-1]* B[numSamples-1] */
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* outReal = realA[0]* realB[0] + realA[2]* realB[2] + realA[4]* realB[4] + .....+ realA[numSamples-2]* realB[numSamples-2] */
+    real_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+    /* outImag = imagA[1]* imagB[1] + imagA[3]* imagB[3] + imagA[5]* imagB[5] + .....+ imagA[numSamples-1]* imagB[numSamples-1] */
+    imag_sum += (q63_t) * pSrcA++ * (*pSrcB++) >> 14;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the real and imaginary results in 16.48 format  */
+  *realResult = real_sum;
+  *imagResult = imag_sum;
+}
+
+/**   
+ * @} end of cmplx_dot_prod group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
new file mode 100644
index 0000000000..309ad6f09a
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_mag_f32.c   
+*   
+* Description:	Floating-point complex magnitude.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @defgroup cmplx_mag Complex Magnitude   
+ *   
+ * Computes the magnitude of the elements of a complex data vector.   
+ *  
+ * The pSrc points to the source data and   
+ * pDst points to the where the result should be written.   
+ * numSamples specifies the number of complex samples   
+ * in the input array and the data is stored in an interleaved fashion   
+ * (real, imag, real, imag, ...).   
+ * The input array has a total of 2*numSamples values;   
+ * the output array has a total of numSamples values.   
+ * The underlying algorithm is used:   
+ *   
+ * 
       
+ * for(n=0; n   
+ *   
+ * There are separate functions for floating-point, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup cmplx_mag   
+ * @{   
+ */
+/**   
+ * @brief Floating-point complex magnitude.   
+ * @param[in]       *pSrc points to complex input buffer   
+ * @param[out]      *pDst points to real output buffer   
+ * @param[in]       numSamples number of complex samples in the input vector   
+ * @return none.   
+ *   
+ */
+
+
+void arm_cmplx_mag_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  float32_t realIn, imagIn;                      /* Temporary variables to hold input values */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    /* store the result in the destination buffer. */
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    /* store the result in the destination buffer. */
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* out = sqrt((real * real) + (imag * imag)) */
+    realIn = *pSrc++;
+    imagIn = *pSrc++;
+    /* store the result in the destination buffer. */
+    arm_sqrt_f32((realIn * realIn) + (imagIn * imagIn), pDst++);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_mag group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
new file mode 100644
index 0000000000..ef5a455d31
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
@@ -0,0 +1,153 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_mag_q15.c   
+*   
+* Description:	Q15 complex magnitude.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_mag   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Q15 complex magnitude   
+ * @param  *pSrc points to the complex input vector   
+ * @param  *pDst points to the real output vector   
+ * @param  numSamples number of complex samples in the input vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 2.14 format.   
+ */
+
+void arm_cmplx_mag_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+  q15_t real, imag;                              /* Temporary variables to hold input values */
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* out = sqrt(real * real + imag * imag) */
+    real = *pSrc++;
+    imag = *pSrc++;
+
+    acc0 = (real * real);
+    acc1 = (imag * imag);
+
+    /* store the result in 2.14 format in the destination buffer. */
+    arm_sqrt_q15((q15_t) (((q63_t) acc0 + acc1) >> 17), pDst++);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_mag group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
new file mode 100644
index 0000000000..ab56304b1c
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
@@ -0,0 +1,151 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_mag_q31.c   
+*   
+* Description:	Q31 complex magnitude   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_mag   
+ * @{   
+ */
+
+/**   
+ * @brief  Q31 complex magnitude   
+ * @param  *pSrc points to the complex input vector   
+ * @param  *pDst points to the real output vector   
+ * @param  numSamples number of complex samples in the input vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 2.30 format.   
+ * Input down scaling is not required.   
+ */
+
+void arm_cmplx_mag_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t real, imag;                              /* Temporary variables to hold input values */
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = sqrt(A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* out = sqrt((real * real) + (imag * imag)) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 2.30 format in the destination buffer. */
+    arm_sqrt_q31(acc0 + acc1, pDst++);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_mag group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
new file mode 100644
index 0000000000..eb6c1baf83
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
@@ -0,0 +1,155 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_mag_squared_f32.c   
+*   
+* Description:	Floating-point complex magnitude squared.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @defgroup cmplx_mag_squared Complex Magnitude Squared   
+ *   
+ * Computes the magnitude squared of the elements of a complex data vector.   
+ *  
+ * The pSrc points to the source data and   
+ * pDst points to the where the result should be written.   
+ * numSamples specifies the number of complex samples   
+ * in the input array and the data is stored in an interleaved fashion   
+ * (real, imag, real, imag, ...).   
+ * The input array has a total of 2*numSamples values;   
+ * the output array has a total of numSamples values.   
+ *   
+ * The underlying algorithm is used:   
+ *   
+ * 
       
+ * for(n=0; n   
+ *   
+ * There are separate functions for floating-point, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup cmplx_mag_squared   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Floating-point complex magnitude squared   
+ * @param[in]  *pSrc points to the complex input vector   
+ * @param[out]  *pDst points to the real output vector   
+ * @param[in]  numSamples number of complex samples in the input vector   
+ * @return none.   
+ */
+
+void arm_cmplx_mag_squared_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  float32_t real, imag;                          /* Temporary variables to store real and imaginary values */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    /* store the result in the destination buffer. */
+    *pDst++ = (real * real) + (imag * imag);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    *pDst++ = (real * real) + (imag * imag);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    *pDst++ = (real * real) + (imag * imag);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    *pDst++ = (real * real) + (imag * imag);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    /* store the result in the destination buffer. */
+    *pDst++ = (real * real) + (imag * imag);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* reading real and imaginary values */
+    real = *pSrc++;
+    imag = *pSrc++;
+
+    /* out = (real * real) + (imag * imag) */
+    /* store the result in the destination buffer. */
+    *pDst++ = (real * real) + (imag * imag);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_mag_squared group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
new file mode 100644
index 0000000000..236199ee59
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
@@ -0,0 +1,148 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_mag_squared_q15.c   
+*   
+* Description:	Q15 complex magnitude squared.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_mag_squared   
+ * @{   
+ */
+
+/**   
+ * @brief  Q15 complex magnitude squared   
+ * @param  *pSrc points to the complex input vector   
+ * @param  *pDst points to the real output vector   
+ * @param  numSamples number of complex samples in the input vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.   
+ */
+
+void arm_cmplx_mag_squared_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+  q15_t real, imag;                              /* Temporary variables to store real and imaginary values */
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /*loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = __SMUAD(real, real);
+    acc1 = __SMUAD(imag, imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* out = ((real * real) + (imag * imag)) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (real * real);
+    acc1 = (imag * imag);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ = (q15_t) (((q63_t) acc0 + acc1) >> 17);
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_mag_squared group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
new file mode 100644
index 0000000000..2ebb98c1f4
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cmplx_mag_squared_q31.c   
+*   
+* Description:	Q31 complex magnitude squared.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup cmplx_mag_squared   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Q31 complex magnitude squared   
+ * @param  *pSrc points to the complex input vector   
+ * @param  *pDst points to the real output vector   
+ * @param  numSamples number of complex samples in the input vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.   
+ * Input down scaling is not required.   
+ */
+
+void arm_cmplx_mag_squared_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t real, imag;                              /* Temporary variables to store real and imaginary values */
+  q31_t acc0, acc1;                              /* Accumulators */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[0] = (A[0] * A[0] + A[1] * A[1]) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* out = ((real * real) + (imag * imag)) */
+    real = *pSrc++;
+    imag = *pSrc++;
+    acc0 = (q31_t) (((q63_t) real * real) >> 33);
+    acc1 = (q31_t) (((q63_t) imag * imag) >> 33);
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = acc0 + acc1;
+
+    /* Decrement the loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of cmplx_mag_squared group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
new file mode 100644
index 0000000000..24b56f69c8
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
@@ -0,0 +1,180 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cmplx_mult_cmplx_f32.c   
+*   
+* Description:	Floating-point complex-by-complex multiplication   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @defgroup CmplxByCmplxMult Complex-by-Complex Multiplication   
+ *   
+ * Multiplies a complex vector by another complex vector and generates a complex result.   
+ * The data in the complex arrays is stored in an interleaved fashion   
+ * (real, imag, real, imag, ...).   
+ * The parameter numSamples represents the number of complex   
+ * samples processed.  The complex arrays have a total of 2*numSamples   
+ * real values.   
+ *   
+ * The underlying algorithm is used:   
+ *   
+ * 
       
+ * for(n=0; n   
+ *   
+ * There are separate functions for floating-point, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup CmplxByCmplxMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Floating-point complex-by-complex multiplication   
+ * @param[in]  *pSrcA points to the first input vector   
+ * @param[in]  *pSrcB points to the second input vector   
+ * @param[out]  *pDst  points to the output vector   
+ * @param[in]  numSamples number of complex samples in each vector   
+ * @return none.   
+ */
+
+void arm_cmplx_mult_cmplx_f32(
+  float32_t * pSrcA,
+  float32_t * pSrcB,
+  float32_t * pDst,
+  uint32_t numSamples)
+{
+  float32_t a, b, c, d;                          /* Temporary variables to store real and imaginary values */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in the destination buffer. */
+    *pDst++ = (a * c) - (b * d);
+    *pDst++ = (a * d) + (b * c);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    *pDst++ = (a * c) - (b * d);
+    *pDst++ = (a * d) + (b * c);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    *pDst++ = (a * c) - (b * d);
+    *pDst++ = (a * d) + (b * c);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    *pDst++ = (a * c) - (b * d);
+    *pDst++ = (a * d) + (b * c);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in the destination buffer. */
+    *pDst++ = (a * c) - (b * d);
+    *pDst++ = (a * d) + (b * c);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in the destination buffer. */
+    *pDst++ = (a * c) - (b * d);
+    *pDst++ = (a * d) + (b * c);
+
+    /* Decrement the numSamples loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of CmplxByCmplxMult group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
new file mode 100644
index 0000000000..ff6606101d
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
@@ -0,0 +1,182 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cmplx_mult_cmplx_q15.c   
+*   
+* Description:	Q15 complex-by-complex multiplication   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup CmplxByCmplxMult   
+ * @{   
+ */
+
+/**   
+ * @brief  Q15 complex-by-complex multiplication   
+ * @param[in]  *pSrcA points to the first input vector   
+ * @param[in]  *pSrcB points to the second input vector   
+ * @param[out]  *pDst  points to the output vector   
+ * @param[in]  numSamples number of complex samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function implements 1.15 by 1.15 multiplications and finally output is converted into 3.13 format.   
+ */
+
+void arm_cmplx_mult_cmplx_q15(
+  q15_t * pSrcA,
+  q15_t * pSrcB,
+  q15_t * pDst,
+  uint32_t numSamples)
+{
+  q15_t a, b, c, d;                              /* Temporary variables to store real and imaginary values */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * c) >> 17) - (((q31_t) b * d) >> 17);
+    /* store the result in 3.13 format in the destination buffer. */
+    *pDst++ =
+      (q15_t) (q31_t) (((q31_t) a * d) >> 17) + (((q31_t) b * c) >> 17);
+
+    /* Decrement the blockSize loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of CmplxByCmplxMult group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
new file mode 100644
index 0000000000..059ae50b19
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
@@ -0,0 +1,209 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cmplx_mult_cmplx_q31.c   
+*   
+* Description:	Q31 complex-by-complex multiplication   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup CmplxByCmplxMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Q31 complex-by-complex multiplication   
+ * @param[in]  *pSrcA points to the first input vector   
+ * @param[in]  *pSrcB points to the second input vector   
+ * @param[out]  *pDst  points to the output vector   
+ * @param[in]  numSamples number of complex samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function implements 1.31 by 1.31 multiplications and finally output is converted into 3.29 format.   
+ * Input down scaling is not required.   
+ */
+
+void arm_cmplx_mult_cmplx_q31(
+  q31_t * pSrcA,
+  q31_t * pSrcB,
+  q31_t * pDst,
+  uint32_t numSamples)
+{
+  q31_t a, b, c, d;                              /* Temporary variables to store real and imaginary values */
+  uint32_t blkCnt;                               /* loop counters */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 1u;
+
+  /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.    
+   ** a second loop below computes the remaining 1 sample. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the real result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the imag result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 2, compute any remaining output samples here.    
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x2u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[2 * i] - A[2 * i + 1] * B[2 * i + 1].  */
+    /* C[2 * i + 1] = A[2 * i] * B[2 * i + 1] + A[2 * i + 1] * B[2 * i].  */
+    a = *pSrcA++;
+    b = *pSrcA++;
+    c = *pSrcB++;
+    d = *pSrcB++;
+
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * c) >> 33) - (((q63_t) b * d) >> 33));
+    /* store the result in 3.29 format in the destination buffer. */
+    *pDst++ = (q31_t) ((((q63_t) a * d) >> 33) + (((q63_t) b * c) >> 33));
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of CmplxByCmplxMult group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
new file mode 100644
index 0000000000..b09c34fddf
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cmplx_mult_real_f32.c   
+*   
+* Description:	Floating-point complex by real multiplication   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @defgroup CmplxByRealMult Complex-by-Real Multiplication   
+ *   
+ * Multiplies a complex vector by a real vector and generates a complex result.   
+ * The data in the complex arrays is stored in an interleaved fashion   
+ * (real, imag, real, imag, ...).   
+ * The parameter numSamples represents the number of complex   
+ * samples processed.  The complex arrays have a total of 2*numSamples   
+ * real values while the real array has a total of numSamples   
+ * real values.   
+ *   
+ * The underlying algorithm is used:   
+ *   
+ * 
       
+ * for(n=0; n   
+ *   
+ * There are separate functions for floating-point, Q15, and Q31 data types.   
+ */
+
+/**   
+ * @addtogroup CmplxByRealMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Floating-point complex-by-real multiplication   
+ * @param[in]  *pSrcCmplx points to the complex input vector   
+ * @param[in]  *pSrcReal points to the real input vector   
+ * @param[out]  *pCmplxDst points to the complex output vector   
+ * @param[in]  numSamples number of samples in each vector   
+ * @return none.   
+ */
+
+void arm_cmplx_mult_real_f32(
+  float32_t * pSrcCmplx,
+  float32_t * pSrcReal,
+  float32_t * pCmplxDst,
+  uint32_t numSamples)
+{
+  float32_t in;                                  /* Temporary variable to store input value */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut = realA * realB.            */
+    /* imagOut = imagA * realB.                */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+    *pCmplxDst++ = (*pSrcCmplx++) * (in);
+
+    /* Decrement the numSamples loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of CmplxByRealMult group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
new file mode 100644
index 0000000000..3f95021b09
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
@@ -0,0 +1,151 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cmplx_mult_real_q15.c   
+*   
+* Description:	Q15 complex by real multiplication   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup CmplxByRealMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Q15 complex-by-real multiplication   
+ * @param[in]  *pSrcCmplx points to the complex input vector   
+ * @param[in]  *pSrcReal points to the real input vector   
+ * @param[out]  *pCmplxDst points to the complex output vector   
+ * @param[in]  numSamples number of samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.   
+ */
+
+void arm_cmplx_mult_real_q15(
+  q15_t * pSrcCmplx,
+  q15_t * pSrcReal,
+  q15_t * pCmplxDst,
+  uint32_t numSamples)
+{
+  q15_t in;                                      /* Temporary variable to store input value */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut = realA * realB.            */
+    /* imagOut = imagA * realB.                */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+    *pCmplxDst++ =
+      (q15_t) __SSAT((((q31_t) (*pSrcCmplx++) * (in)) >> 15), 16);
+
+    /* Decrement the numSamples loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of CmplxByRealMult group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
new file mode 100644
index 0000000000..887222ce7d
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
@@ -0,0 +1,151 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cmplx_mult_real_q31.c   
+*   
+* Description:	Q31 complex by real multiplication   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupCmplxMath   
+ */
+
+/**   
+ * @addtogroup CmplxByRealMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Q31 complex-by-real multiplication   
+ * @param[in]  *pSrcCmplx points to the complex input vector   
+ * @param[in]  *pSrcReal points to the real input vector   
+ * @param[out]  *pCmplxDst points to the complex output vector   
+ * @param[in]  numSamples number of samples in each vector   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.   
+ */
+
+void arm_cmplx_mult_real_q31(
+  q31_t * pSrcCmplx,
+  q31_t * pSrcReal,
+  q31_t * pCmplxDst,
+  uint32_t numSamples)
+{
+  q31_t in;                                      /* Temporary variable to store input value */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+  uint32_t blkCnt;                               /* loop counters */
+
+  /* loop Unrolling */
+  blkCnt = numSamples >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+
+    in = *pSrcReal++;
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+  /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = numSamples % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C[2 * i] = A[2 * i] * B[i].            */
+    /* C[2 * i + 1] = A[2 * i + 1] * B[i].        */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+
+    /* Decrement the numSamples loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(numSamples > 0u)
+  {
+    /* realOut = realA * realB.            */
+    /* imagReal = imagA * realB.               */
+    in = *pSrcReal++;
+    /* store the result in the destination buffer. */
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+    *pCmplxDst++ =
+      (q31_t) clip_q63_to_q31(((q63_t) * pSrcCmplx++ * in) >> 31);
+
+    /* Decrement the numSamples loop counter */
+    numSamples--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of CmplxByRealMult group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c
new file mode 100644
index 0000000000..f8e1c2e051
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c
@@ -0,0 +1,76 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_pid_init_f32.c   
+*   
+* Description:	Floating-point PID Control initialization function   
+*				  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**   
+ * @addtogroup PID   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the floating-point PID Control.  
+ * @param[in,out] *S points to an instance of the PID structure.  
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state & 1 = reset the state.  
+ * @return none.  
+ * \par Description:  
+ * \par   
+ * The resetStateFlag specifies whether to set state to zero or not. \n  
+ * The function computes the structure fields: A0, A1 A2   
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)   
+ * also sets the state variables to all zeros.   
+ */
+
+void arm_pid_init_f32(
+  arm_pid_instance_f32 * S,
+  int32_t resetStateFlag)
+{
+
+  /* Derived coefficient A0 */
+  S->A0 = S->Kp + S->Ki + S->Kd;
+
+  /* Derived coefficient A1 */
+  S->A1 = (-S->Kp) - ((float32_t) 2.0 * S->Kd);
+
+  /* Derived coefficient A2 */
+  S->A2 = S->Kd;
+
+  /* Check whether state needs reset or not */
+  if(resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3u * sizeof(float32_t));
+  }
+
+}
+
+/**   
+ * @} end of PID group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c
new file mode 100644
index 0000000000..f7e1e7e6fe
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c
@@ -0,0 +1,111 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_pid_init_q15.c   
+*   
+* Description:	Q15 PID Control initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**   
+ * @addtogroup PID   
+ * @{   
+ */
+
+/**   
+ * @details   
+ * @param[in,out] *S points to an instance of the Q15 PID structure.   
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.   
+ * @return none.   
+ * \par Description:  
+ * \par   
+ * The resetStateFlag specifies whether to set state to zero or not. \n  
+ * The function computes the structure fields: A0, A1 A2   
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)   
+ * also sets the state variables to all zeros.   
+ */
+
+void arm_pid_init_q15(
+  arm_pid_instance_q15 * S,
+  int32_t resetStateFlag)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Derived coefficient A0 */
+  S->A0 = __QADD16(__QADD16(S->Kp, S->Ki), S->Kd);
+
+  /* Derived coefficients and pack into A1 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+  S->A1 = __PKHBT(-__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), S->Kd, 16);
+
+#else
+
+  S->A1 = __PKHBT(S->Kd, -__QADD16(__QADD16(S->Kd, S->Kd), S->Kp), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+  /* Check whether state needs reset or not */
+  if(resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3u * sizeof(q15_t));
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t temp;                                    /*to store the sum */
+
+  /* Derived coefficient A0 */
+  temp = S->Kp + S->Ki + S->Kd;
+  S->A0 = (q15_t) __SSAT(temp, 16);
+
+  /* Derived coefficients and pack into A1 */
+  temp = -(S->Kd + S->Kd + S->Kp);
+  S->A1 = (q15_t) __SSAT(temp, 16);
+  S->A2 = S->Kd;
+
+
+
+  /* Check whether state needs reset or not */
+  if(resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3u * sizeof(q15_t));
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of PID group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c
new file mode 100644
index 0000000000..22b05f2289
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c
@@ -0,0 +1,96 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_pid_init_q31.c   
+*   
+* Description:	Q31 PID Control initialization function    
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**   
+ * @addtogroup PID   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the Q31 PID Control.  
+ * @param[in,out] *S points to an instance of the Q31 PID structure.  
+ * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.  
+ * @return none.   
+ * \par Description:  
+ * \par   
+ * The resetStateFlag specifies whether to set state to zero or not. \n  
+ * The function computes the structure fields: A0, A1 A2   
+ * using the proportional gain( \c Kp), integral gain( \c Ki) and derivative gain( \c Kd)   
+ * also sets the state variables to all zeros.   
+ */
+
+void arm_pid_init_q31(
+  arm_pid_instance_q31 * S,
+  int32_t resetStateFlag)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Derived coefficient A0 */
+  S->A0 = __QADD(__QADD(S->Kp, S->Ki), S->Kd);
+
+  /* Derived coefficient A1 */
+  S->A1 = -__QADD(__QADD(S->Kd, S->Kd), S->Kp);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t temp;
+
+  /* Derived coefficient A0 */
+  temp = clip_q63_to_q31((q63_t) S->Kp + S->Ki);
+  S->A0 = clip_q63_to_q31((q63_t) temp + S->Kd);
+
+  /* Derived coefficient A1 */
+  temp = clip_q63_to_q31((q63_t) S->Kd + S->Kd);
+  S->A1 = -clip_q63_to_q31((q63_t) temp + S->Kp);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Derived coefficient A2 */
+  S->A2 = S->Kd;
+
+  /* Check whether state needs reset or not */
+  if(resetStateFlag)
+  {
+    /* Clear the state buffer.  The size will be always 3 samples */
+    memset(S->state, 0, 3u * sizeof(q31_t));
+  }
+
+}
+
+/**   
+ * @} end of PID group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c
new file mode 100644
index 0000000000..51baa6fa42
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c
@@ -0,0 +1,54 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_pid_reset_f32.c   
+*   
+* Description:	Floating-point PID Control reset function  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**   
+ * @addtogroup PID   
+ * @{   
+ */
+
+/**   
+* @brief  Reset function for the floating-point PID Control.  
+* @param[in] *S	Instance pointer of PID control data structure.  
+* @return none.   
+* \par Description:  
+* The function resets the state buffer to zeros.   
+*/
+void arm_pid_reset_f32(
+  arm_pid_instance_f32 * S)
+{
+
+  /* Clear the state buffer.  The size will be always 3 samples */
+  memset(S->state, 0, 3u * sizeof(float32_t));
+}
+
+/**   
+ * @} end of PID group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c
new file mode 100644
index 0000000000..e71460c158
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c
@@ -0,0 +1,53 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_pid_reset_q15.c   
+*   
+* Description:	Q15 PID Control reset function  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**   
+ * @addtogroup PID   
+ * @{   
+ */
+
+/**   
+* @brief  Reset function for the Q15 PID Control.  
+* @param[in] *S		Instance pointer of PID control data structure.  
+* @return none.   
+* \par Description:  
+* The function resets the state buffer to zeros.   
+*/
+void arm_pid_reset_q15(
+  arm_pid_instance_q15 * S)
+{
+  /* Reset state to zero, The size will be always 3 samples */
+  memset(S->state, 0, 3u * sizeof(q15_t));
+}
+
+/**   
+ * @} end of PID group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c
new file mode 100644
index 0000000000..9714fed627
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c
@@ -0,0 +1,54 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_pid_reset_q31.c   
+*   
+* Description:	Q31 PID Control reset function  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+ /**   
+ * @addtogroup PID   
+ * @{   
+ */
+
+/**   
+* @brief  Reset function for the Q31 PID Control.  
+* @param[in] *S	Instance pointer of PID control data structure.  
+* @return none.   
+* \par Description:  
+* The function resets the state buffer to zeros.   
+*/
+void arm_pid_reset_q31(
+  arm_pid_instance_q31 * S)
+{
+
+  /* Clear the state buffer.  The size will be always 3 samples */
+  memset(S->state, 0, 3u * sizeof(q31_t));
+}
+
+/**   
+ * @} end of PID group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c
new file mode 100644
index 0000000000..b7c10ec030
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c
@@ -0,0 +1,408 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sin_cos_f32.c   
+*   
+* Description:	Sine and Cosine calculation for floating-point values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupController   
+ */
+
+/**   
+ * @defgroup SinCos Sine Cosine  
+ *   
+ * Computes the trigonometric sine and cosine values using a combination of table lookup  
+ * and linear interpolation.    
+ * There are separate functions for Q31 and floating-point data types.  
+ * The input to the floating-point version is in degrees while the  
+ * fixed-point Q31 have a scaled input with the range  
+ * [-1 1) mapping to [-180 180) degrees.  
+ *  
+ * The implementation is based on table lookup using 360 values together with linear interpolation.  
+ * The steps used are:  
+ *  -# Calculation of the nearest integer table index.  
+ *  -# Compute the fractional portion (fract) of the input.  
+ *  -# Fetch the value corresponding to \c index from sine table to \c y0 and also value from \c index+1 to \c y1.     
+ *  -# Sine value is computed as  *psinVal = y0 + (fract * (y1 - y0)).   
+ *  -# Fetch the value corresponding to \c index from cosine table to \c y0 and also value from \c index+1 to \c y1.     
+ *  -# Cosine value is computed as  *pcosVal = y0 + (fract * (y1 - y0)).   
+ */
+
+ /**   
+ * @addtogroup SinCos   
+ * @{   
+ */
+
+
+/**   
+* \par   
+* Cosine Table is generated from following loop   
+* 
    for(i = 0; i < 360; i++)   
+* {   
+*    cosTable[i]= cos((i-180) * PI/180.0);   
+* } 
      
+*/
+
+static const float32_t cosTable[360] = {
+  -0.999847695156391270f, -0.999390827019095760f, -0.998629534754573830f,
+  -0.997564050259824200f, -0.996194698091745550f, -0.994521895368273290f,
+  -0.992546151641321980f, -0.990268068741570250f,
+  -0.987688340595137660f, -0.984807753012208020f, -0.981627183447663980f,
+  -0.978147600733805690f, -0.974370064785235250f, -0.970295726275996470f,
+  -0.965925826289068200f, -0.961261695938318670f,
+  -0.956304755963035440f, -0.951056516295153530f, -0.945518575599316740f,
+  -0.939692620785908320f, -0.933580426497201740f, -0.927183854566787310f,
+  -0.920504853452440150f, -0.913545457642600760f,
+  -0.906307787036649940f, -0.898794046299167040f, -0.891006524188367790f,
+  -0.882947592858926770f, -0.874619707139395740f, -0.866025403784438710f,
+  -0.857167300702112220f, -0.848048096156425960f,
+  -0.838670567945424160f, -0.829037572555041620f, -0.819152044288991580f,
+  -0.809016994374947340f, -0.798635510047292940f, -0.788010753606721900f,
+  -0.777145961456970680f, -0.766044443118977900f,
+  -0.754709580222772010f, -0.743144825477394130f, -0.731353701619170460f,
+  -0.719339800338651300f, -0.707106781186547460f, -0.694658370458997030f,
+  -0.681998360062498370f, -0.669130606358858240f,
+  -0.656059028990507500f, -0.642787609686539360f, -0.629320391049837280f,
+  -0.615661475325658290f, -0.601815023152048380f, -0.587785252292473030f,
+  -0.573576436351045830f, -0.559192903470746680f,
+  -0.544639035015027080f, -0.529919264233204790f, -0.515038074910054270f,
+  -0.499999999999999780f, -0.484809620246337000f, -0.469471562785890530f,
+  -0.453990499739546750f, -0.438371146789077510f,
+  -0.422618261740699330f, -0.406736643075800100f, -0.390731128489273600f,
+  -0.374606593415912070f, -0.358367949545300270f, -0.342020143325668710f,
+  -0.325568154457156420f, -0.309016994374947340f,
+  -0.292371704722736660f, -0.275637355816999050f, -0.258819045102520850f,
+  -0.241921895599667790f, -0.224951054343864810f, -0.207911690817759120f,
+  -0.190808995376544800f, -0.173648177666930300f,
+  -0.156434465040231040f, -0.139173100960065350f, -0.121869343405147370f,
+  -0.104528463267653330f, -0.087155742747658235f, -0.069756473744125330f,
+  -0.052335956242943620f, -0.034899496702500733f,
+  -0.017452406437283477f, 0.000000000000000061f, 0.017452406437283376f,
+  0.034899496702501080f, 0.052335956242943966f, 0.069756473744125455f,
+  0.087155742747658138f, 0.104528463267653460f,
+  0.121869343405147490f, 0.139173100960065690f, 0.156434465040230920f,
+  0.173648177666930410f, 0.190808995376544920f, 0.207911690817759450f,
+  0.224951054343864920f, 0.241921895599667900f,
+  0.258819045102520740f, 0.275637355816999160f, 0.292371704722736770f,
+  0.309016994374947450f, 0.325568154457156760f, 0.342020143325668820f,
+  0.358367949545300380f, 0.374606593415911960f,
+  0.390731128489273940f, 0.406736643075800210f, 0.422618261740699440f,
+  0.438371146789077460f, 0.453990499739546860f, 0.469471562785890860f,
+  0.484809620246337110f, 0.500000000000000110f,
+  0.515038074910054380f, 0.529919264233204900f, 0.544639035015027200f,
+  0.559192903470746790f, 0.573576436351046050f, 0.587785252292473140f,
+  0.601815023152048270f, 0.615661475325658290f,
+  0.629320391049837500f, 0.642787609686539360f, 0.656059028990507280f,
+  0.669130606358858240f, 0.681998360062498480f, 0.694658370458997370f,
+  0.707106781186547570f, 0.719339800338651190f,
+  0.731353701619170570f, 0.743144825477394240f, 0.754709580222772010f,
+  0.766044443118978010f, 0.777145961456970900f, 0.788010753606722010f,
+  0.798635510047292830f, 0.809016994374947450f,
+  0.819152044288991800f, 0.829037572555041620f, 0.838670567945424050f,
+  0.848048096156425960f, 0.857167300702112330f, 0.866025403784438710f,
+  0.874619707139395740f, 0.882947592858926990f,
+  0.891006524188367900f, 0.898794046299167040f, 0.906307787036649940f,
+  0.913545457642600870f, 0.920504853452440370f, 0.927183854566787420f,
+  0.933580426497201740f, 0.939692620785908430f,
+  0.945518575599316850f, 0.951056516295153530f, 0.956304755963035440f,
+  0.961261695938318890f, 0.965925826289068310f, 0.970295726275996470f,
+  0.974370064785235250f, 0.978147600733805690f,
+  0.981627183447663980f, 0.984807753012208020f, 0.987688340595137770f,
+  0.990268068741570360f, 0.992546151641321980f, 0.994521895368273290f,
+  0.996194698091745550f, 0.997564050259824200f,
+  0.998629534754573830f, 0.999390827019095760f, 0.999847695156391270f,
+  1.000000000000000000f, 0.999847695156391270f, 0.999390827019095760f,
+  0.998629534754573830f, 0.997564050259824200f,
+  0.996194698091745550f, 0.994521895368273290f, 0.992546151641321980f,
+  0.990268068741570360f, 0.987688340595137770f, 0.984807753012208020f,
+  0.981627183447663980f, 0.978147600733805690f,
+  0.974370064785235250f, 0.970295726275996470f, 0.965925826289068310f,
+  0.961261695938318890f, 0.956304755963035440f, 0.951056516295153530f,
+  0.945518575599316850f, 0.939692620785908430f,
+  0.933580426497201740f, 0.927183854566787420f, 0.920504853452440370f,
+  0.913545457642600870f, 0.906307787036649940f, 0.898794046299167040f,
+  0.891006524188367900f, 0.882947592858926990f,
+  0.874619707139395740f, 0.866025403784438710f, 0.857167300702112330f,
+  0.848048096156425960f, 0.838670567945424050f, 0.829037572555041620f,
+  0.819152044288991800f, 0.809016994374947450f,
+  0.798635510047292830f, 0.788010753606722010f, 0.777145961456970900f,
+  0.766044443118978010f, 0.754709580222772010f, 0.743144825477394240f,
+  0.731353701619170570f, 0.719339800338651190f,
+  0.707106781186547570f, 0.694658370458997370f, 0.681998360062498480f,
+  0.669130606358858240f, 0.656059028990507280f, 0.642787609686539360f,
+  0.629320391049837500f, 0.615661475325658290f,
+  0.601815023152048270f, 0.587785252292473140f, 0.573576436351046050f,
+  0.559192903470746790f, 0.544639035015027200f, 0.529919264233204900f,
+  0.515038074910054380f, 0.500000000000000110f,
+  0.484809620246337110f, 0.469471562785890860f, 0.453990499739546860f,
+  0.438371146789077460f, 0.422618261740699440f, 0.406736643075800210f,
+  0.390731128489273940f, 0.374606593415911960f,
+  0.358367949545300380f, 0.342020143325668820f, 0.325568154457156760f,
+  0.309016994374947450f, 0.292371704722736770f, 0.275637355816999160f,
+  0.258819045102520740f, 0.241921895599667900f,
+  0.224951054343864920f, 0.207911690817759450f, 0.190808995376544920f,
+  0.173648177666930410f, 0.156434465040230920f, 0.139173100960065690f,
+  0.121869343405147490f, 0.104528463267653460f,
+  0.087155742747658138f, 0.069756473744125455f, 0.052335956242943966f,
+  0.034899496702501080f, 0.017452406437283376f, 0.000000000000000061f,
+  -0.017452406437283477f, -0.034899496702500733f,
+  -0.052335956242943620f, -0.069756473744125330f, -0.087155742747658235f,
+  -0.104528463267653330f, -0.121869343405147370f, -0.139173100960065350f,
+  -0.156434465040231040f, -0.173648177666930300f,
+  -0.190808995376544800f, -0.207911690817759120f, -0.224951054343864810f,
+  -0.241921895599667790f, -0.258819045102520850f, -0.275637355816999050f,
+  -0.292371704722736660f, -0.309016994374947340f,
+  -0.325568154457156420f, -0.342020143325668710f, -0.358367949545300270f,
+  -0.374606593415912070f, -0.390731128489273600f, -0.406736643075800100f,
+  -0.422618261740699330f, -0.438371146789077510f,
+  -0.453990499739546750f, -0.469471562785890530f, -0.484809620246337000f,
+  -0.499999999999999780f, -0.515038074910054270f, -0.529919264233204790f,
+  -0.544639035015027080f, -0.559192903470746680f,
+  -0.573576436351045830f, -0.587785252292473030f, -0.601815023152048380f,
+  -0.615661475325658290f, -0.629320391049837280f, -0.642787609686539360f,
+  -0.656059028990507500f, -0.669130606358858240f,
+  -0.681998360062498370f, -0.694658370458997030f, -0.707106781186547460f,
+  -0.719339800338651300f, -0.731353701619170460f, -0.743144825477394130f,
+  -0.754709580222772010f, -0.766044443118977900f,
+  -0.777145961456970680f, -0.788010753606721900f, -0.798635510047292940f,
+  -0.809016994374947340f, -0.819152044288991580f, -0.829037572555041620f,
+  -0.838670567945424160f, -0.848048096156425960f,
+  -0.857167300702112220f, -0.866025403784438710f, -0.874619707139395740f,
+  -0.882947592858926770f, -0.891006524188367790f, -0.898794046299167040f,
+  -0.906307787036649940f, -0.913545457642600760f,
+  -0.920504853452440150f, -0.927183854566787310f, -0.933580426497201740f,
+  -0.939692620785908320f, -0.945518575599316740f, -0.951056516295153530f,
+  -0.956304755963035440f, -0.961261695938318670f,
+  -0.965925826289068200f, -0.970295726275996470f, -0.974370064785235250f,
+  -0.978147600733805690f, -0.981627183447663980f, -0.984807753012208020f,
+  -0.987688340595137660f, -0.990268068741570250f,
+  -0.992546151641321980f, -0.994521895368273290f, -0.996194698091745550f,
+  -0.997564050259824200f, -0.998629534754573830f, -0.999390827019095760f,
+  -0.999847695156391270f, -1.000000000000000000f
+};
+
+/**   
+* \par   
+* Sine Table is generated from following loop   
+* 
    for(i = 0; i < 360; i++)   
+* {   
+*    sinTable[i]= sin((i-180) * PI/180.0);   
+* } 
       
+*/
+
+
+static const float32_t sinTable[360] = {
+  -0.017452406437283439f, -0.034899496702500699f, -0.052335956242943807f,
+  -0.069756473744125524f, -0.087155742747658638f, -0.104528463267653730f,
+  -0.121869343405147550f, -0.139173100960065740f,
+  -0.156434465040230980f, -0.173648177666930280f, -0.190808995376544970f,
+  -0.207911690817759310f, -0.224951054343864780f, -0.241921895599667730f,
+  -0.258819045102521020f, -0.275637355816999660f,
+  -0.292371704722737050f, -0.309016994374947510f, -0.325568154457156980f,
+  -0.342020143325668880f, -0.358367949545300210f, -0.374606593415912240f,
+  -0.390731128489274160f, -0.406736643075800430f,
+  -0.422618261740699500f, -0.438371146789077290f, -0.453990499739546860f,
+  -0.469471562785891080f, -0.484809620246337170f, -0.499999999999999940f,
+  -0.515038074910054380f, -0.529919264233204900f,
+  -0.544639035015026860f, -0.559192903470746900f, -0.573576436351046380f,
+  -0.587785252292473250f, -0.601815023152048160f, -0.615661475325658400f,
+  -0.629320391049837720f, -0.642787609686539470f,
+  -0.656059028990507280f, -0.669130606358858350f, -0.681998360062498590f,
+  -0.694658370458997140f, -0.707106781186547570f, -0.719339800338651410f,
+  -0.731353701619170570f, -0.743144825477394240f,
+  -0.754709580222771790f, -0.766044443118978010f, -0.777145961456971010f,
+  -0.788010753606722010f, -0.798635510047292720f, -0.809016994374947450f,
+  -0.819152044288992020f, -0.829037572555041740f,
+  -0.838670567945424050f, -0.848048096156426070f, -0.857167300702112330f,
+  -0.866025403784438710f, -0.874619707139395850f, -0.882947592858927100f,
+  -0.891006524188367900f, -0.898794046299166930f,
+  -0.906307787036650050f, -0.913545457642600980f, -0.920504853452440370f,
+  -0.927183854566787420f, -0.933580426497201740f, -0.939692620785908430f,
+  -0.945518575599316850f, -0.951056516295153640f,
+  -0.956304755963035550f, -0.961261695938318890f, -0.965925826289068310f,
+  -0.970295726275996470f, -0.974370064785235250f, -0.978147600733805690f,
+  -0.981627183447663980f, -0.984807753012208020f,
+  -0.987688340595137660f, -0.990268068741570360f, -0.992546151641322090f,
+  -0.994521895368273400f, -0.996194698091745550f, -0.997564050259824200f,
+  -0.998629534754573830f, -0.999390827019095760f,
+  -0.999847695156391270f, -1.000000000000000000f, -0.999847695156391270f,
+  -0.999390827019095760f, -0.998629534754573830f, -0.997564050259824200f,
+  -0.996194698091745550f, -0.994521895368273290f,
+  -0.992546151641321980f, -0.990268068741570250f, -0.987688340595137770f,
+  -0.984807753012208020f, -0.981627183447663980f, -0.978147600733805580f,
+  -0.974370064785235250f, -0.970295726275996470f,
+  -0.965925826289068310f, -0.961261695938318890f, -0.956304755963035440f,
+  -0.951056516295153530f, -0.945518575599316740f, -0.939692620785908320f,
+  -0.933580426497201740f, -0.927183854566787420f,
+  -0.920504853452440260f, -0.913545457642600870f, -0.906307787036649940f,
+  -0.898794046299167040f, -0.891006524188367790f, -0.882947592858926880f,
+  -0.874619707139395740f, -0.866025403784438600f,
+  -0.857167300702112220f, -0.848048096156426070f, -0.838670567945423940f,
+  -0.829037572555041740f, -0.819152044288991800f, -0.809016994374947450f,
+  -0.798635510047292830f, -0.788010753606722010f,
+  -0.777145961456970790f, -0.766044443118978010f, -0.754709580222772010f,
+  -0.743144825477394240f, -0.731353701619170460f, -0.719339800338651080f,
+  -0.707106781186547460f, -0.694658370458997250f,
+  -0.681998360062498480f, -0.669130606358858240f, -0.656059028990507160f,
+  -0.642787609686539250f, -0.629320391049837390f, -0.615661475325658180f,
+  -0.601815023152048270f, -0.587785252292473140f,
+  -0.573576436351046050f, -0.559192903470746900f, -0.544639035015027080f,
+  -0.529919264233204900f, -0.515038074910054160f, -0.499999999999999940f,
+  -0.484809620246337060f, -0.469471562785890810f,
+  -0.453990499739546750f, -0.438371146789077400f, -0.422618261740699440f,
+  -0.406736643075800150f, -0.390731128489273720f, -0.374606593415912010f,
+  -0.358367949545300270f, -0.342020143325668710f,
+  -0.325568154457156640f, -0.309016994374947400f, -0.292371704722736770f,
+  -0.275637355816999160f, -0.258819045102520740f, -0.241921895599667730f,
+  -0.224951054343865000f, -0.207911690817759310f,
+  -0.190808995376544800f, -0.173648177666930330f, -0.156434465040230870f,
+  -0.139173100960065440f, -0.121869343405147480f, -0.104528463267653460f,
+  -0.087155742747658166f, -0.069756473744125302f,
+  -0.052335956242943828f, -0.034899496702500969f, -0.017452406437283512f,
+  0.000000000000000000f, 0.017452406437283512f, 0.034899496702500969f,
+  0.052335956242943828f, 0.069756473744125302f,
+  0.087155742747658166f, 0.104528463267653460f, 0.121869343405147480f,
+  0.139173100960065440f, 0.156434465040230870f, 0.173648177666930330f,
+  0.190808995376544800f, 0.207911690817759310f,
+  0.224951054343865000f, 0.241921895599667730f, 0.258819045102520740f,
+  0.275637355816999160f, 0.292371704722736770f, 0.309016994374947400f,
+  0.325568154457156640f, 0.342020143325668710f,
+  0.358367949545300270f, 0.374606593415912010f, 0.390731128489273720f,
+  0.406736643075800150f, 0.422618261740699440f, 0.438371146789077400f,
+  0.453990499739546750f, 0.469471562785890810f,
+  0.484809620246337060f, 0.499999999999999940f, 0.515038074910054160f,
+  0.529919264233204900f, 0.544639035015027080f, 0.559192903470746900f,
+  0.573576436351046050f, 0.587785252292473140f,
+  0.601815023152048270f, 0.615661475325658180f, 0.629320391049837390f,
+  0.642787609686539250f, 0.656059028990507160f, 0.669130606358858240f,
+  0.681998360062498480f, 0.694658370458997250f,
+  0.707106781186547460f, 0.719339800338651080f, 0.731353701619170460f,
+  0.743144825477394240f, 0.754709580222772010f, 0.766044443118978010f,
+  0.777145961456970790f, 0.788010753606722010f,
+  0.798635510047292830f, 0.809016994374947450f, 0.819152044288991800f,
+  0.829037572555041740f, 0.838670567945423940f, 0.848048096156426070f,
+  0.857167300702112220f, 0.866025403784438600f,
+  0.874619707139395740f, 0.882947592858926880f, 0.891006524188367790f,
+  0.898794046299167040f, 0.906307787036649940f, 0.913545457642600870f,
+  0.920504853452440260f, 0.927183854566787420f,
+  0.933580426497201740f, 0.939692620785908320f, 0.945518575599316740f,
+  0.951056516295153530f, 0.956304755963035440f, 0.961261695938318890f,
+  0.965925826289068310f, 0.970295726275996470f,
+  0.974370064785235250f, 0.978147600733805580f, 0.981627183447663980f,
+  0.984807753012208020f, 0.987688340595137770f, 0.990268068741570250f,
+  0.992546151641321980f, 0.994521895368273290f,
+  0.996194698091745550f, 0.997564050259824200f, 0.998629534754573830f,
+  0.999390827019095760f, 0.999847695156391270f, 1.000000000000000000f,
+  0.999847695156391270f, 0.999390827019095760f,
+  0.998629534754573830f, 0.997564050259824200f, 0.996194698091745550f,
+  0.994521895368273400f, 0.992546151641322090f, 0.990268068741570360f,
+  0.987688340595137660f, 0.984807753012208020f,
+  0.981627183447663980f, 0.978147600733805690f, 0.974370064785235250f,
+  0.970295726275996470f, 0.965925826289068310f, 0.961261695938318890f,
+  0.956304755963035550f, 0.951056516295153640f,
+  0.945518575599316850f, 0.939692620785908430f, 0.933580426497201740f,
+  0.927183854566787420f, 0.920504853452440370f, 0.913545457642600980f,
+  0.906307787036650050f, 0.898794046299166930f,
+  0.891006524188367900f, 0.882947592858927100f, 0.874619707139395850f,
+  0.866025403784438710f, 0.857167300702112330f, 0.848048096156426070f,
+  0.838670567945424050f, 0.829037572555041740f,
+  0.819152044288992020f, 0.809016994374947450f, 0.798635510047292720f,
+  0.788010753606722010f, 0.777145961456971010f, 0.766044443118978010f,
+  0.754709580222771790f, 0.743144825477394240f,
+  0.731353701619170570f, 0.719339800338651410f, 0.707106781186547570f,
+  0.694658370458997140f, 0.681998360062498590f, 0.669130606358858350f,
+  0.656059028990507280f, 0.642787609686539470f,
+  0.629320391049837720f, 0.615661475325658400f, 0.601815023152048160f,
+  0.587785252292473250f, 0.573576436351046380f, 0.559192903470746900f,
+  0.544639035015026860f, 0.529919264233204900f,
+  0.515038074910054380f, 0.499999999999999940f, 0.484809620246337170f,
+  0.469471562785891080f, 0.453990499739546860f, 0.438371146789077290f,
+  0.422618261740699500f, 0.406736643075800430f,
+  0.390731128489274160f, 0.374606593415912240f, 0.358367949545300210f,
+  0.342020143325668880f, 0.325568154457156980f, 0.309016994374947510f,
+  0.292371704722737050f, 0.275637355816999660f,
+  0.258819045102521020f, 0.241921895599667730f, 0.224951054343864780f,
+  0.207911690817759310f, 0.190808995376544970f, 0.173648177666930280f,
+  0.156434465040230980f, 0.139173100960065740f,
+  0.121869343405147550f, 0.104528463267653730f, 0.087155742747658638f,
+  0.069756473744125524f, 0.052335956242943807f, 0.034899496702500699f,
+  0.017452406437283439f, 0.000000000000000122f
+};
+
+
+/**   
+ * @brief  Floating-point sin_cos function.  
+ * @param[in]  theta    input value in degrees   
+ * @param[out] *pSinVal points to the processed sine output.   
+ * @param[out] *pCosVal points to the processed cos output.   
+ * @return none.  
+ */
+
+
+void arm_sin_cos_f32(
+  float32_t theta,
+  float32_t * pSinVal,
+  float32_t * pCosVal)
+{
+  uint32_t i;                                    /* Index for reading nearwst output values */
+  float32_t x1 = -179.0f;                        /* Initial input value */
+  float32_t y0, y1;                              /* nearest output values */
+  float32_t fract;                               /* fractional part of input */
+
+  /* Calculation of fractional part */
+  if(theta > 0.0f)
+  {
+    fract = theta - (float32_t) ((int32_t) theta);
+  }
+  else
+  {
+    fract = (theta - (float32_t) ((int32_t) theta)) + 1.0f;
+  }
+
+  /* index calculation for reading nearest output values */
+  i = (uint32_t) (theta - x1);
+
+  /* reading nearest sine output values */
+  y0 = sinTable[i];
+  y1 = sinTable[i + 1u];
+
+  /* Calculation of sine value */
+  *pSinVal = y0 + (fract * (y1 - y0));
+
+  /* reading nearest cosine output values */
+  y0 = cosTable[i];
+  y1 = cosTable[i + 1u];
+
+  /* Calculation of cosine value */
+  *pCosVal = y0 + (fract * (y1 - y0));
+
+}
+
+/**   
+ * @} end of SinCos group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c
new file mode 100644
index 0000000000..0ad8bb95bf
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c
@@ -0,0 +1,311 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sin_cos_q31.c   
+*   
+* Description:	Cosine & Sine calculation for Q31 values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupController   
+ */
+
+ /**   
+ * @addtogroup SinCos   
+ * @{   
+ */
+
+/**   
+* \par   
+* Sine Table is generated from following loop   
+* 
    for(i = 0; i < 360; i++)   
+* {   
+*    sinTable[i]= sin((i-180) * PI/180.0);   
+* } 
      
+* Convert above coefficients to fixed point 1.31 format.   
+*/
+
+static const int32_t sinTableQ31[360] = {
+
+  0x0, 0xfdc41e9b, 0xfb8869ce, 0xf94d0e2e, 0xf7123849, 0xf4d814a4, 0xf29ecfb2,
+  0xf06695da,
+  0xee2f9369, 0xebf9f498, 0xe9c5e582, 0xe7939223, 0xe5632654, 0xe334cdc9,
+  0xe108b40d, 0xdedf047d,
+  0xdcb7ea46, 0xda939061, 0xd8722192, 0xd653c860, 0xd438af17, 0xd220ffc0,
+  0xd00ce422, 0xcdfc85bb,
+  0xcbf00dbe, 0xc9e7a512, 0xc7e3744b, 0xc5e3a3a9, 0xc3e85b18, 0xc1f1c224,
+  0xc0000000, 0xbe133b7c,
+  0xbc2b9b05, 0xba4944a2, 0xb86c5df0, 0xb6950c1e, 0xb4c373ee, 0xb2f7b9af,
+  0xb1320139, 0xaf726def,
+  0xadb922b7, 0xac0641fb, 0xaa59eda4, 0xa8b4471a, 0xa7156f3c, 0xa57d8666,
+  0xa3ecac65, 0xa263007d,
+  0xa0e0a15f, 0x9f65ad2d, 0x9df24175, 0x9c867b2c, 0x9b2276b0, 0x99c64fc5,
+  0x98722192, 0x9726069c,
+  0x95e218c9, 0x94a6715d, 0x937328f5, 0x92485786, 0x9126145f, 0x900c7621,
+  0x8efb92c2, 0x8df37f8b,
+  0x8cf45113, 0x8bfe1b3f, 0x8b10f144, 0x8a2ce59f, 0x89520a1a, 0x88806fc4,
+  0x87b826f7, 0x86f93f50,
+  0x8643c7b3, 0x8597ce46, 0x84f56073, 0x845c8ae3, 0x83cd5982, 0x8347d77b,
+  0x82cc0f36, 0x825a0a5b,
+  0x81f1d1ce, 0x81936daf, 0x813ee55b, 0x80f43f69, 0x80b381ac, 0x807cb130,
+  0x804fd23a, 0x802ce84c,
+  0x8013f61d, 0x8004fda0, 0x80000000, 0x8004fda0, 0x8013f61d, 0x802ce84c,
+  0x804fd23a, 0x807cb130,
+  0x80b381ac, 0x80f43f69, 0x813ee55b, 0x81936daf, 0x81f1d1ce, 0x825a0a5b,
+  0x82cc0f36, 0x8347d77b,
+  0x83cd5982, 0x845c8ae3, 0x84f56073, 0x8597ce46, 0x8643c7b3, 0x86f93f50,
+  0x87b826f7, 0x88806fc4,
+  0x89520a1a, 0x8a2ce59f, 0x8b10f144, 0x8bfe1b3f, 0x8cf45113, 0x8df37f8b,
+  0x8efb92c2, 0x900c7621,
+  0x9126145f, 0x92485786, 0x937328f5, 0x94a6715d, 0x95e218c9, 0x9726069c,
+  0x98722192, 0x99c64fc5,
+  0x9b2276b0, 0x9c867b2c, 0x9df24175, 0x9f65ad2d, 0xa0e0a15f, 0xa263007d,
+  0xa3ecac65, 0xa57d8666,
+  0xa7156f3c, 0xa8b4471a, 0xaa59eda4, 0xac0641fb, 0xadb922b7, 0xaf726def,
+  0xb1320139, 0xb2f7b9af,
+  0xb4c373ee, 0xb6950c1e, 0xb86c5df0, 0xba4944a2, 0xbc2b9b05, 0xbe133b7c,
+  0xc0000000, 0xc1f1c224,
+  0xc3e85b18, 0xc5e3a3a9, 0xc7e3744b, 0xc9e7a512, 0xcbf00dbe, 0xcdfc85bb,
+  0xd00ce422, 0xd220ffc0,
+  0xd438af17, 0xd653c860, 0xd8722192, 0xda939061, 0xdcb7ea46, 0xdedf047d,
+  0xe108b40d, 0xe334cdc9,
+  0xe5632654, 0xe7939223, 0xe9c5e582, 0xebf9f498, 0xee2f9369, 0xf06695da,
+  0xf29ecfb2, 0xf4d814a4,
+  0xf7123849, 0xf94d0e2e, 0xfb8869ce, 0xfdc41e9b, 0x0, 0x23be165, 0x4779632,
+  0x6b2f1d2,
+  0x8edc7b7, 0xb27eb5c, 0xd61304e, 0xf996a26, 0x11d06c97, 0x14060b68,
+  0x163a1a7e, 0x186c6ddd,
+  0x1a9cd9ac, 0x1ccb3237, 0x1ef74bf3, 0x2120fb83, 0x234815ba, 0x256c6f9f,
+  0x278dde6e, 0x29ac37a0,
+  0x2bc750e9, 0x2ddf0040, 0x2ff31bde, 0x32037a45, 0x340ff242, 0x36185aee,
+  0x381c8bb5, 0x3a1c5c57,
+  0x3c17a4e8, 0x3e0e3ddc, 0x40000000, 0x41ecc484, 0x43d464fb, 0x45b6bb5e,
+  0x4793a210, 0x496af3e2,
+  0x4b3c8c12, 0x4d084651, 0x4ecdfec7, 0x508d9211, 0x5246dd49, 0x53f9be05,
+  0x55a6125c, 0x574bb8e6,
+  0x58ea90c4, 0x5a82799a, 0x5c13539b, 0x5d9cff83, 0x5f1f5ea1, 0x609a52d3,
+  0x620dbe8b, 0x637984d4,
+  0x64dd8950, 0x6639b03b, 0x678dde6e, 0x68d9f964, 0x6a1de737, 0x6b598ea3,
+  0x6c8cd70b, 0x6db7a87a,
+  0x6ed9eba1, 0x6ff389df, 0x71046d3e, 0x720c8075, 0x730baeed, 0x7401e4c1,
+  0x74ef0ebc, 0x75d31a61,
+  0x76adf5e6, 0x777f903c, 0x7847d909, 0x7906c0b0, 0x79bc384d, 0x7a6831ba,
+  0x7b0a9f8d, 0x7ba3751d,
+  0x7c32a67e, 0x7cb82885, 0x7d33f0ca, 0x7da5f5a5, 0x7e0e2e32, 0x7e6c9251,
+  0x7ec11aa5, 0x7f0bc097,
+  0x7f4c7e54, 0x7f834ed0, 0x7fb02dc6, 0x7fd317b4, 0x7fec09e3, 0x7ffb0260,
+  0x7fffffff, 0x7ffb0260,
+  0x7fec09e3, 0x7fd317b4, 0x7fb02dc6, 0x7f834ed0, 0x7f4c7e54, 0x7f0bc097,
+  0x7ec11aa5, 0x7e6c9251,
+  0x7e0e2e32, 0x7da5f5a5, 0x7d33f0ca, 0x7cb82885, 0x7c32a67e, 0x7ba3751d,
+  0x7b0a9f8d, 0x7a6831ba,
+  0x79bc384d, 0x7906c0b0, 0x7847d909, 0x777f903c, 0x76adf5e6, 0x75d31a61,
+  0x74ef0ebc, 0x7401e4c1,
+  0x730baeed, 0x720c8075, 0x71046d3e, 0x6ff389df, 0x6ed9eba1, 0x6db7a87a,
+  0x6c8cd70b, 0x6b598ea3,
+  0x6a1de737, 0x68d9f964, 0x678dde6e, 0x6639b03b, 0x64dd8950, 0x637984d4,
+  0x620dbe8b, 0x609a52d3,
+  0x5f1f5ea1, 0x5d9cff83, 0x5c13539b, 0x5a82799a, 0x58ea90c4, 0x574bb8e6,
+  0x55a6125c, 0x53f9be05,
+  0x5246dd49, 0x508d9211, 0x4ecdfec7, 0x4d084651, 0x4b3c8c12, 0x496af3e2,
+  0x4793a210, 0x45b6bb5e,
+  0x43d464fb, 0x41ecc484, 0x40000000, 0x3e0e3ddc, 0x3c17a4e8, 0x3a1c5c57,
+  0x381c8bb5, 0x36185aee,
+  0x340ff242, 0x32037a45, 0x2ff31bde, 0x2ddf0040, 0x2bc750e9, 0x29ac37a0,
+  0x278dde6e, 0x256c6f9f,
+  0x234815ba, 0x2120fb83, 0x1ef74bf3, 0x1ccb3237, 0x1a9cd9ac, 0x186c6ddd,
+  0x163a1a7e, 0x14060b68,
+  0x11d06c97, 0xf996a26, 0xd61304e, 0xb27eb5c, 0x8edc7b7, 0x6b2f1d2,
+  0x4779632, 0x23be165,
+
+
+};
+
+/**   
+* \par   
+* Cosine Table is generated from following loop   
+* 
    for(i = 0; i < 360; i++)   
+* {   
+*    cosTable[i]= cos((i-180) * PI/180.0);   
+* } 
      
+* \par   
+* Convert above coefficients to fixed point 1.31 format.   
+*/
+static const int32_t cosTableQ31[360] = {
+  0x80000000, 0x8004fda0, 0x8013f61d, 0x802ce84c, 0x804fd23a, 0x807cb130,
+  0x80b381ac, 0x80f43f69,
+  0x813ee55b, 0x81936daf, 0x81f1d1ce, 0x825a0a5b, 0x82cc0f36, 0x8347d77b,
+  0x83cd5982, 0x845c8ae3,
+  0x84f56073, 0x8597ce46, 0x8643c7b3, 0x86f93f50, 0x87b826f7, 0x88806fc4,
+  0x89520a1a, 0x8a2ce59f,
+  0x8b10f144, 0x8bfe1b3f, 0x8cf45113, 0x8df37f8b, 0x8efb92c2, 0x900c7621,
+  0x9126145f, 0x92485786,
+  0x937328f5, 0x94a6715d, 0x95e218c9, 0x9726069c, 0x98722192, 0x99c64fc5,
+  0x9b2276b0, 0x9c867b2c,
+  0x9df24175, 0x9f65ad2d, 0xa0e0a15f, 0xa263007d, 0xa3ecac65, 0xa57d8666,
+  0xa7156f3c, 0xa8b4471a,
+  0xaa59eda4, 0xac0641fb, 0xadb922b7, 0xaf726def, 0xb1320139, 0xb2f7b9af,
+  0xb4c373ee, 0xb6950c1e,
+  0xb86c5df0, 0xba4944a2, 0xbc2b9b05, 0xbe133b7c, 0xc0000000, 0xc1f1c224,
+  0xc3e85b18, 0xc5e3a3a9,
+  0xc7e3744b, 0xc9e7a512, 0xcbf00dbe, 0xcdfc85bb, 0xd00ce422, 0xd220ffc0,
+  0xd438af17, 0xd653c860,
+  0xd8722192, 0xda939061, 0xdcb7ea46, 0xdedf047d, 0xe108b40d, 0xe334cdc9,
+  0xe5632654, 0xe7939223,
+  0xe9c5e582, 0xebf9f498, 0xee2f9369, 0xf06695da, 0xf29ecfb2, 0xf4d814a4,
+  0xf7123849, 0xf94d0e2e,
+  0xfb8869ce, 0xfdc41e9b, 0x0, 0x23be165, 0x4779632, 0x6b2f1d2, 0x8edc7b7,
+  0xb27eb5c,
+  0xd61304e, 0xf996a26, 0x11d06c97, 0x14060b68, 0x163a1a7e, 0x186c6ddd,
+  0x1a9cd9ac, 0x1ccb3237,
+  0x1ef74bf3, 0x2120fb83, 0x234815ba, 0x256c6f9f, 0x278dde6e, 0x29ac37a0,
+  0x2bc750e9, 0x2ddf0040,
+  0x2ff31bde, 0x32037a45, 0x340ff242, 0x36185aee, 0x381c8bb5, 0x3a1c5c57,
+  0x3c17a4e8, 0x3e0e3ddc,
+  0x40000000, 0x41ecc484, 0x43d464fb, 0x45b6bb5e, 0x4793a210, 0x496af3e2,
+  0x4b3c8c12, 0x4d084651,
+  0x4ecdfec7, 0x508d9211, 0x5246dd49, 0x53f9be05, 0x55a6125c, 0x574bb8e6,
+  0x58ea90c4, 0x5a82799a,
+  0x5c13539b, 0x5d9cff83, 0x5f1f5ea1, 0x609a52d3, 0x620dbe8b, 0x637984d4,
+  0x64dd8950, 0x6639b03b,
+  0x678dde6e, 0x68d9f964, 0x6a1de737, 0x6b598ea3, 0x6c8cd70b, 0x6db7a87a,
+  0x6ed9eba1, 0x6ff389df,
+  0x71046d3e, 0x720c8075, 0x730baeed, 0x7401e4c1, 0x74ef0ebc, 0x75d31a61,
+  0x76adf5e6, 0x777f903c,
+  0x7847d909, 0x7906c0b0, 0x79bc384d, 0x7a6831ba, 0x7b0a9f8d, 0x7ba3751d,
+  0x7c32a67e, 0x7cb82885,
+  0x7d33f0ca, 0x7da5f5a5, 0x7e0e2e32, 0x7e6c9251, 0x7ec11aa5, 0x7f0bc097,
+  0x7f4c7e54, 0x7f834ed0,
+  0x7fb02dc6, 0x7fd317b4, 0x7fec09e3, 0x7ffb0260, 0x7fffffff, 0x7ffb0260,
+  0x7fec09e3, 0x7fd317b4,
+  0x7fb02dc6, 0x7f834ed0, 0x7f4c7e54, 0x7f0bc097, 0x7ec11aa5, 0x7e6c9251,
+  0x7e0e2e32, 0x7da5f5a5,
+  0x7d33f0ca, 0x7cb82885, 0x7c32a67e, 0x7ba3751d, 0x7b0a9f8d, 0x7a6831ba,
+  0x79bc384d, 0x7906c0b0,
+  0x7847d909, 0x777f903c, 0x76adf5e6, 0x75d31a61, 0x74ef0ebc, 0x7401e4c1,
+  0x730baeed, 0x720c8075,
+  0x71046d3e, 0x6ff389df, 0x6ed9eba1, 0x6db7a87a, 0x6c8cd70b, 0x6b598ea3,
+  0x6a1de737, 0x68d9f964,
+  0x678dde6e, 0x6639b03b, 0x64dd8950, 0x637984d4, 0x620dbe8b, 0x609a52d3,
+  0x5f1f5ea1, 0x5d9cff83,
+  0x5c13539b, 0x5a82799a, 0x58ea90c4, 0x574bb8e6, 0x55a6125c, 0x53f9be05,
+  0x5246dd49, 0x508d9211,
+  0x4ecdfec7, 0x4d084651, 0x4b3c8c12, 0x496af3e2, 0x4793a210, 0x45b6bb5e,
+  0x43d464fb, 0x41ecc484,
+  0x40000000, 0x3e0e3ddc, 0x3c17a4e8, 0x3a1c5c57, 0x381c8bb5, 0x36185aee,
+  0x340ff242, 0x32037a45,
+  0x2ff31bde, 0x2ddf0040, 0x2bc750e9, 0x29ac37a0, 0x278dde6e, 0x256c6f9f,
+  0x234815ba, 0x2120fb83,
+  0x1ef74bf3, 0x1ccb3237, 0x1a9cd9ac, 0x186c6ddd, 0x163a1a7e, 0x14060b68,
+  0x11d06c97, 0xf996a26,
+  0xd61304e, 0xb27eb5c, 0x8edc7b7, 0x6b2f1d2, 0x4779632, 0x23be165, 0x0,
+  0xfdc41e9b,
+  0xfb8869ce, 0xf94d0e2e, 0xf7123849, 0xf4d814a4, 0xf29ecfb2, 0xf06695da,
+  0xee2f9369, 0xebf9f498,
+  0xe9c5e582, 0xe7939223, 0xe5632654, 0xe334cdc9, 0xe108b40d, 0xdedf047d,
+  0xdcb7ea46, 0xda939061,
+  0xd8722192, 0xd653c860, 0xd438af17, 0xd220ffc0, 0xd00ce422, 0xcdfc85bb,
+  0xcbf00dbe, 0xc9e7a512,
+  0xc7e3744b, 0xc5e3a3a9, 0xc3e85b18, 0xc1f1c224, 0xc0000000, 0xbe133b7c,
+  0xbc2b9b05, 0xba4944a2,
+  0xb86c5df0, 0xb6950c1e, 0xb4c373ee, 0xb2f7b9af, 0xb1320139, 0xaf726def,
+  0xadb922b7, 0xac0641fb,
+  0xaa59eda4, 0xa8b4471a, 0xa7156f3c, 0xa57d8666, 0xa3ecac65, 0xa263007d,
+  0xa0e0a15f, 0x9f65ad2d,
+  0x9df24175, 0x9c867b2c, 0x9b2276b0, 0x99c64fc5, 0x98722192, 0x9726069c,
+  0x95e218c9, 0x94a6715d,
+  0x937328f5, 0x92485786, 0x9126145f, 0x900c7621, 0x8efb92c2, 0x8df37f8b,
+  0x8cf45113, 0x8bfe1b3f,
+  0x8b10f144, 0x8a2ce59f, 0x89520a1a, 0x88806fc4, 0x87b826f7, 0x86f93f50,
+  0x8643c7b3, 0x8597ce46,
+  0x84f56073, 0x845c8ae3, 0x83cd5982, 0x8347d77b, 0x82cc0f36, 0x825a0a5b,
+  0x81f1d1ce, 0x81936daf,
+  0x813ee55b, 0x80f43f69, 0x80b381ac, 0x807cb130, 0x804fd23a, 0x802ce84c,
+  0x8013f61d, 0x8004fda0,
+
+};
+
+
+/**   
+ * @brief  Q31 sin_cos function.  
+ * @param[in]  theta    scaled input value in degrees   
+ * @param[out] *pSinVal points to the processed sine output.   
+ * @param[out] *pCosVal points to the processed cosine output.   
+ * @return none.  
+ *   
+ * The Q31 input value is in the range [-1 +1) and is mapped to a degree value in the range [-180 180).  
+ *   
+ */
+
+
+void arm_sin_cos_q31(
+  q31_t theta,
+  q31_t * pSinVal,
+  q31_t * pCosVal)
+{
+  q31_t x0;                                      /* Nearest input value */
+  q31_t y0, y1;                                  /* Nearest output values */
+  q31_t xSpacing = INPUT_SPACING;                /* Spaing between inputs */
+  uint32_t i;                                    /* Index */
+  q31_t oneByXSpacing;                           /* 1/ xSpacing value */
+  q31_t out;                                     /* temporary variable */
+  uint32_t sign_bits;                            /* No.of sign bits */
+  uint32_t firstX = 0x80000000;                  /* First X value */
+
+  /* Calculation of index */
+  i = ((uint32_t) theta - firstX) / (uint32_t) xSpacing;
+
+  /* Calculation of first nearest input value */
+  x0 = (q31_t) firstX + ((q31_t) i * xSpacing);
+
+  /* Reading nearest sine output values from table */
+  y0 = sinTableQ31[i];
+  y1 = sinTableQ31[i + 1u];
+
+  /* Calculation of 1/(x1-x0) */
+  /* (x1-x0) is xSpacing which is fixed value */
+  sign_bits = 8u;
+  oneByXSpacing = 0x5A000000;
+
+  /* Calculation of (theta - x0)/(x1-x0) */
+  out =
+    (((q31_t) (((q63_t) (theta - x0) * oneByXSpacing) >> 32)) << sign_bits);
+
+  /* Calculation of y0 + (y1 - y0) * ((theta - x0)/(x1-x0)) */
+  *pSinVal = y0 + ((q31_t) (((q63_t) (y1 - y0) * out) >> 30));
+
+  /* Reading nearest cosine output values from table */
+  y0 = cosTableQ31[i];
+  y1 = cosTableQ31[i + 1u];
+
+  /* Calculation of y0 + (y1 - y0) * ((theta - x0)/(x1-x0)) */
+  *pCosVal = y0 + ((q31_t) (((q63_t) (y1 - y0) * out) >> 30));
+
+}
+
+/**   
+ * @} end of SinCos group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c
new file mode 100644
index 0000000000..c29469fa44
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c
@@ -0,0 +1,254 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cos_f32.c   
+*   
+* Description:	Fast cosine calculation for floating-point values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**   
+ * @ingroup groupFastMath   
+ */
+
+/**   
+ * @defgroup cos Cosine   
+ *   
+ * Computes the trigonometric cosine function using a combination of table lookup  
+ * and cubic interpolation.  There are separate functions for  
+ * Q15, Q31, and floating-point data types.  
+ * The input to the floating-point version is in radians while the  
+ * fixed-point Q15 and Q31 have a scaled input with the range  
+ * [0 1) mapping to [0 2*pi).  
+ *  
+ * The implementation is based on table lookup using 256 values together with cubic interpolation.  
+ * The steps used are:  
+ *  -# Calculation of the nearest integer table index  
+ *  -# Fetch the four table values a, b, c, and d    
+ *  -# Compute the fractional portion (fract) of the table index.  
+ *  -# Calculation of wa, wb, wc, wd   
+ *  -# The final result equals a*wa + b*wb + c*wc + d*wd  
+ *  
+ * where  
+ * 
       
+ *    a=Table[index-1];   
+ *    b=Table[index+0];   
+ *    c=Table[index+1];   
+ *    d=Table[index+2];   
+ * 
      
+ * and  
+ * 
       
+ *    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;   
+ *    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;   
+ *    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;   
+ *    wd=(1/6)*fract.^3 - (1/6)*fract;   
+ * 
       
+ */
+
+ /**   
+ * @addtogroup cos   
+ * @{   
+ */
+
+
+/**   
+* \par   
+* Example code for Generation of Cos Table:  
+* tableSize = 256;   
+* 
    for(n = -1; n < (tableSize + 1); n++)   
+* {   
+*	cosTable[n+1]= cos(2*pi*n/tableSize);   
+* } 
       
+* where pi value is  3.14159265358979   
+*/
+
+static const float32_t cosTable[259] = {
+  0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,
+  0.998795449733734130f, 0.997290432453155520f, 0.995184719562530520f,
+  0.992479562759399410f, 0.989176511764526370f,
+  0.985277652740478520f, 0.980785250663757320f, 0.975702106952667240f,
+  0.970031261444091800f, 0.963776051998138430f, 0.956940352916717530f,
+  0.949528157711029050f, 0.941544055938720700f,
+  0.932992815971374510f, 0.923879504203796390f, 0.914209783077239990f,
+  0.903989315032958980f, 0.893224298954010010f, 0.881921291351318360f,
+  0.870086967945098880f, 0.857728600502014160f,
+  0.844853579998016360f, 0.831469595432281490f, 0.817584812641143800f,
+  0.803207516670227050f, 0.788346409797668460f, 0.773010432720184330f,
+  0.757208824157714840f, 0.740951120853424070f,
+  0.724247097969055180f, 0.707106769084930420f, 0.689540565013885500f,
+  0.671558976173400880f, 0.653172850608825680f, 0.634393274784088130f,
+  0.615231573581695560f, 0.595699310302734380f,
+  0.575808167457580570f, 0.555570244789123540f, 0.534997642040252690f,
+  0.514102756977081300f, 0.492898195981979370f, 0.471396744251251220f,
+  0.449611335992813110f, 0.427555084228515630f,
+  0.405241310596466060f, 0.382683426141738890f, 0.359895050525665280f,
+  0.336889863014221190f, 0.313681751489639280f, 0.290284663438797000f,
+  0.266712754964828490f, 0.242980182170867920f,
+  0.219101235270500180f, 0.195090323686599730f, 0.170961886644363400f,
+  0.146730467677116390f, 0.122410677373409270f, 0.098017141222953796f,
+  0.073564566671848297f, 0.049067676067352295f,
+  0.024541229009628296f, 0.000000000000000061f, -0.024541229009628296f,
+  -0.049067676067352295f, -0.073564566671848297f, -0.098017141222953796f,
+  -0.122410677373409270f, -0.146730467677116390f,
+  -0.170961886644363400f, -0.195090323686599730f, -0.219101235270500180f,
+  -0.242980182170867920f, -0.266712754964828490f, -0.290284663438797000f,
+  -0.313681751489639280f, -0.336889863014221190f,
+  -0.359895050525665280f, -0.382683426141738890f, -0.405241310596466060f,
+  -0.427555084228515630f, -0.449611335992813110f, -0.471396744251251220f,
+  -0.492898195981979370f, -0.514102756977081300f,
+  -0.534997642040252690f, -0.555570244789123540f, -0.575808167457580570f,
+  -0.595699310302734380f, -0.615231573581695560f, -0.634393274784088130f,
+  -0.653172850608825680f, -0.671558976173400880f,
+  -0.689540565013885500f, -0.707106769084930420f, -0.724247097969055180f,
+  -0.740951120853424070f, -0.757208824157714840f, -0.773010432720184330f,
+  -0.788346409797668460f, -0.803207516670227050f,
+  -0.817584812641143800f, -0.831469595432281490f, -0.844853579998016360f,
+  -0.857728600502014160f, -0.870086967945098880f, -0.881921291351318360f,
+  -0.893224298954010010f, -0.903989315032958980f,
+  -0.914209783077239990f, -0.923879504203796390f, -0.932992815971374510f,
+  -0.941544055938720700f, -0.949528157711029050f, -0.956940352916717530f,
+  -0.963776051998138430f, -0.970031261444091800f,
+  -0.975702106952667240f, -0.980785250663757320f, -0.985277652740478520f,
+  -0.989176511764526370f, -0.992479562759399410f, -0.995184719562530520f,
+  -0.997290432453155520f, -0.998795449733734130f,
+  -0.999698817729949950f, -1.000000000000000000f, -0.999698817729949950f,
+  -0.998795449733734130f, -0.997290432453155520f, -0.995184719562530520f,
+  -0.992479562759399410f, -0.989176511764526370f,
+  -0.985277652740478520f, -0.980785250663757320f, -0.975702106952667240f,
+  -0.970031261444091800f, -0.963776051998138430f, -0.956940352916717530f,
+  -0.949528157711029050f, -0.941544055938720700f,
+  -0.932992815971374510f, -0.923879504203796390f, -0.914209783077239990f,
+  -0.903989315032958980f, -0.893224298954010010f, -0.881921291351318360f,
+  -0.870086967945098880f, -0.857728600502014160f,
+  -0.844853579998016360f, -0.831469595432281490f, -0.817584812641143800f,
+  -0.803207516670227050f, -0.788346409797668460f, -0.773010432720184330f,
+  -0.757208824157714840f, -0.740951120853424070f,
+  -0.724247097969055180f, -0.707106769084930420f, -0.689540565013885500f,
+  -0.671558976173400880f, -0.653172850608825680f, -0.634393274784088130f,
+  -0.615231573581695560f, -0.595699310302734380f,
+  -0.575808167457580570f, -0.555570244789123540f, -0.534997642040252690f,
+  -0.514102756977081300f, -0.492898195981979370f, -0.471396744251251220f,
+  -0.449611335992813110f, -0.427555084228515630f,
+  -0.405241310596466060f, -0.382683426141738890f, -0.359895050525665280f,
+  -0.336889863014221190f, -0.313681751489639280f, -0.290284663438797000f,
+  -0.266712754964828490f, -0.242980182170867920f,
+  -0.219101235270500180f, -0.195090323686599730f, -0.170961886644363400f,
+  -0.146730467677116390f, -0.122410677373409270f, -0.098017141222953796f,
+  -0.073564566671848297f, -0.049067676067352295f,
+  -0.024541229009628296f, -0.000000000000000184f, 0.024541229009628296f,
+  0.049067676067352295f, 0.073564566671848297f, 0.098017141222953796f,
+  0.122410677373409270f, 0.146730467677116390f,
+  0.170961886644363400f, 0.195090323686599730f, 0.219101235270500180f,
+  0.242980182170867920f, 0.266712754964828490f, 0.290284663438797000f,
+  0.313681751489639280f, 0.336889863014221190f,
+  0.359895050525665280f, 0.382683426141738890f, 0.405241310596466060f,
+  0.427555084228515630f, 0.449611335992813110f, 0.471396744251251220f,
+  0.492898195981979370f, 0.514102756977081300f,
+  0.534997642040252690f, 0.555570244789123540f, 0.575808167457580570f,
+  0.595699310302734380f, 0.615231573581695560f, 0.634393274784088130f,
+  0.653172850608825680f, 0.671558976173400880f,
+  0.689540565013885500f, 0.707106769084930420f, 0.724247097969055180f,
+  0.740951120853424070f, 0.757208824157714840f, 0.773010432720184330f,
+  0.788346409797668460f, 0.803207516670227050f,
+  0.817584812641143800f, 0.831469595432281490f, 0.844853579998016360f,
+  0.857728600502014160f, 0.870086967945098880f, 0.881921291351318360f,
+  0.893224298954010010f, 0.903989315032958980f,
+  0.914209783077239990f, 0.923879504203796390f, 0.932992815971374510f,
+  0.941544055938720700f, 0.949528157711029050f, 0.956940352916717530f,
+  0.963776051998138430f, 0.970031261444091800f,
+  0.975702106952667240f, 0.980785250663757320f, 0.985277652740478520f,
+  0.989176511764526370f, 0.992479562759399410f, 0.995184719562530520f,
+  0.997290432453155520f, 0.998795449733734130f,
+  0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f
+};
+
+/**  
+ * @brief  Fast approximation to the trigonometric cosine function for floating-point data.  
+ * @param[in] x input value in radians.  
+ * @return cos(x).  
+ */
+
+float32_t arm_cos_f32(
+  float32_t x)
+{
+  float32_t cosVal, fract, in;
+  uint32_t index;
+  uint32_t tableSize = (uint32_t) TABLE_SIZE;
+  float32_t wa, wb, wc, wd;
+  float32_t a, b, c, d;
+  float32_t *tablePtr;
+  int32_t n;
+
+  /* input x is in radians */
+  /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */
+  in = x * 0.159154943092f;
+
+  /* Calculation of floor value of input */
+  n = (int32_t) in;
+
+  /* Make negative values towards -infinity */
+  if(x < 0.0f)
+  {
+    n = n - 1;
+  }
+
+  /* Map input value to [0 1] */
+  in = in - (float32_t) n;
+
+  /* Calculation of index of the table */
+  index = (uint32_t) (tableSize * in);
+
+  /* fractional value calculation */
+  fract = ((float32_t) tableSize * in) - (float32_t) index;
+
+  /* Initialise table pointer */
+  tablePtr = (float32_t *) & cosTable[index];
+
+  /* Read four nearest values of input value from the cos table */
+  a = *tablePtr++;
+  b = *tablePtr++;
+  c = *tablePtr++;
+  d = *tablePtr++;
+
+  /* Cubic interpolation process */
+  wa = -(((0.166666667f) * fract) * (fract * fract)) +
+    (((0.5f) * (fract * fract)) - ((0.3333333333333f) * fract));
+  wb = ((((0.5f) * fract) * (fract * fract)) - (fract * fract)) +
+    (-((0.5f) * fract) + 1.0f);
+  wc = -(((0.5f) * fract) * (fract * fract)) +
+    (((0.5f) * (fract * fract)) + fract);
+  wd = (((0.166666667f) * fract) * (fract * fract)) -
+    ((0.166666667f) * fract);
+
+  /* Calculate cos value */
+  cosVal = ((a * wa) + (b * wb)) + ((c * wc) + (d * wd));
+
+  /* Return the output value */
+  return (cosVal);
+
+}
+
+/**   
+ * @} end of cos group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c
new file mode 100644
index 0000000000..50bfa105eb
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c
@@ -0,0 +1,189 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cos_q15.c   
+*   
+* Description:	Fast cosine calculation for Q15 values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFastMath   
+ */
+
+ /**   
+ * @addtogroup cos   
+ * @{   
+ */
+
+/**  
+* \par   
+* Table Values are in Q15(1.15 Fixed point format) and generation is done in three steps   
+* \par   
+* First Generate cos values in floating point:   
+* tableSize = 256;    
+* 
    for(n = -1; n < (tableSize + 1); n++)   
+* {   
+*	cosTable[n+1]= cos(2*pi*n/tableSize);   
+* }
      
+* where pi value is  3.14159265358979   
+* \par   
+* Secondly Convert Floating point to Q15(Fixed point):   
+*	(cosTable[i] * pow(2, 15))   
+* \par   
+* Finally Rounding to nearest integer is done   
+* 	cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);   
+*/
+
+static const q15_t cosTableQ15[259] = {
+  0x7ff6, 0x7fff, 0x7ff6, 0x7fd9, 0x7fa7, 0x7f62, 0x7f0a, 0x7e9d,
+  0x7e1e, 0x7d8a, 0x7ce4, 0x7c2a, 0x7b5d, 0x7a7d, 0x798a, 0x7885,
+  0x776c, 0x7642, 0x7505, 0x73b6, 0x7255, 0x70e3, 0x6f5f, 0x6dca,
+  0x6c24, 0x6a6e, 0x68a7, 0x66d0, 0x64e9, 0x62f2, 0x60ec, 0x5ed7,
+  0x5cb4, 0x5a82, 0x5843, 0x55f6, 0x539b, 0x5134, 0x4ec0, 0x4c40,
+  0x49b4, 0x471d, 0x447b, 0x41ce, 0x3f17, 0x3c57, 0x398d, 0x36ba,
+  0x33df, 0x30fc, 0x2e11, 0x2b1f, 0x2827, 0x2528, 0x2224, 0x1f1a,
+  0x1c0c, 0x18f9, 0x15e2, 0x12c8, 0xfab, 0xc8c, 0x96b, 0x648,
+  0x324, 0x0, 0xfcdc, 0xf9b8, 0xf695, 0xf374, 0xf055, 0xed38,
+  0xea1e, 0xe707, 0xe3f4, 0xe0e6, 0xdddc, 0xdad8, 0xd7d9, 0xd4e1,
+  0xd1ef, 0xcf04, 0xcc21, 0xc946, 0xc673, 0xc3a9, 0xc0e9, 0xbe32,
+  0xbb85, 0xb8e3, 0xb64c, 0xb3c0, 0xb140, 0xaecc, 0xac65, 0xaa0a,
+  0xa7bd, 0xa57e, 0xa34c, 0xa129, 0x9f14, 0x9d0e, 0x9b17, 0x9930,
+  0x9759, 0x9592, 0x93dc, 0x9236, 0x90a1, 0x8f1d, 0x8dab, 0x8c4a,
+  0x8afb, 0x89be, 0x8894, 0x877b, 0x8676, 0x8583, 0x84a3, 0x83d6,
+  0x831c, 0x8276, 0x81e2, 0x8163, 0x80f6, 0x809e, 0x8059, 0x8027,
+  0x800a, 0x8000, 0x800a, 0x8027, 0x8059, 0x809e, 0x80f6, 0x8163,
+  0x81e2, 0x8276, 0x831c, 0x83d6, 0x84a3, 0x8583, 0x8676, 0x877b,
+  0x8894, 0x89be, 0x8afb, 0x8c4a, 0x8dab, 0x8f1d, 0x90a1, 0x9236,
+  0x93dc, 0x9592, 0x9759, 0x9930, 0x9b17, 0x9d0e, 0x9f14, 0xa129,
+  0xa34c, 0xa57e, 0xa7bd, 0xaa0a, 0xac65, 0xaecc, 0xb140, 0xb3c0,
+  0xb64c, 0xb8e3, 0xbb85, 0xbe32, 0xc0e9, 0xc3a9, 0xc673, 0xc946,
+  0xcc21, 0xcf04, 0xd1ef, 0xd4e1, 0xd7d9, 0xdad8, 0xdddc, 0xe0e6,
+  0xe3f4, 0xe707, 0xea1e, 0xed38, 0xf055, 0xf374, 0xf695, 0xf9b8,
+  0xfcdc, 0x0, 0x324, 0x648, 0x96b, 0xc8c, 0xfab, 0x12c8,
+  0x15e2, 0x18f9, 0x1c0c, 0x1f1a, 0x2224, 0x2528, 0x2827, 0x2b1f,
+  0x2e11, 0x30fc, 0x33df, 0x36ba, 0x398d, 0x3c57, 0x3f17, 0x41ce,
+  0x447b, 0x471d, 0x49b4, 0x4c40, 0x4ec0, 0x5134, 0x539b, 0x55f6,
+  0x5843, 0x5a82, 0x5cb4, 0x5ed7, 0x60ec, 0x62f2, 0x64e9, 0x66d0,
+  0x68a7, 0x6a6e, 0x6c24, 0x6dca, 0x6f5f, 0x70e3, 0x7255, 0x73b6,
+  0x7505, 0x7642, 0x776c, 0x7885, 0x798a, 0x7a7d, 0x7b5d, 0x7c2a,
+  0x7ce4, 0x7d8a, 0x7e1e, 0x7e9d, 0x7f0a, 0x7f62, 0x7fa7, 0x7fd9,
+  0x7ff6, 0x7fff, 0x7ff6
+};
+
+
+/**  
+ * @brief Fast approximation to the trigonometric cosine function for Q15 data.  
+ * @param[in] x Scaled input value in radians.  
+ * @return  cos(x).  
+ *  
+ * The Q15 input value is in the range [0 +1) and is mapped to a radian value in the range [0 2*pi).  
+ */
+
+q15_t arm_cos_q15(
+  q15_t x)
+{
+  q31_t cosVal;                                  /* Temporary variable for output */
+  q15_t *tablePtr;                               /* Pointer to table */
+  q15_t in, in2;                                 /* Temporary variables for input */
+  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */
+  q15_t a, b, c, d;                              /* Four nearest output values */
+  q15_t fract, fractCube, fractSquare;           /* Variables for fractional value */
+  q15_t oneBy6 = 0x1555;                         /* Fixed point value of 1/6 */
+  q15_t tableSpacing = TABLE_SPACING_Q15;        /* Table spacing */
+  int32_t index;                                 /* Index variable */
+
+  in = x;
+
+  /* Calculate the nearest index */
+  index = (int32_t) in / tableSpacing;
+
+  /* Calculate the nearest value of input */
+  in2 = (q15_t) index *tableSpacing;
+
+  /* Calculation of fractional value */
+  fract = (in - in2) << 8;
+
+  /* fractSquare = fract * fract */
+  fractSquare = (q15_t) ((fract * fract) >> 15);
+
+  /* fractCube = fract * fract * fract */
+  fractCube = (q15_t) ((fractSquare * fract) >> 15);
+
+  /* Initialise table pointer */
+  tablePtr = (q15_t *) & cosTableQ15[index];
+
+  /* Cubic interpolation process */
+  /* Calculation of wa */
+  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAA)*fract; */
+  wa = (q31_t) oneBy6 *fractCube;
+  wa += (q31_t) 0x2AAA *fract;
+  wa = -(wa >> 15);
+  wa += (fractSquare >> 1u);
+
+  /* Read first nearest value of output from the cos table */
+  a = *tablePtr++;
+
+  /* cosVal = a * wa */
+  cosVal = a * wa;
+
+  /* Calculation of wb */
+  wb = (((fractCube >> 1u) - fractSquare) - (fract >> 1u)) + 0x7FFF;
+
+  /* Read second nearest value of output from the cos table */
+  b = *tablePtr++;
+
+  /*      cosVal += b*wb */
+  cosVal += b * wb;
+
+  /* Calculation of wc */
+  wc = -(q31_t) fractCube + fractSquare;
+  wc = (wc >> 1u) + fract;
+
+  /* Read third nearest value of output from the cos table */
+  c = *tablePtr++;
+
+  /*      cosVal += c*wc */
+  cosVal += c * wc;
+
+  /* Calculation of wd */
+  /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
+  fractCube = fractCube - fract;
+  wd = ((q15_t) (((q31_t) oneBy6 * fractCube) >> 15));
+
+  /* Read fourth nearest value of output from the cos table */
+  d = *tablePtr++;
+
+  /* cosVal += d*wd; */
+  cosVal += d * wd;
+
+  /* Return the output value in 1.15(q15) format */
+  return ((q15_t) (cosVal >> 15u));
+
+}
+
+/**   
+ * @} end of cos group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c
new file mode 100644
index 0000000000..7203e06c3f
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c
@@ -0,0 +1,225 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_cos_q31.c   
+*   
+* Description:	Fast cosine calculation for Q31 values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFastMath   
+ */
+
+ /**   
+ * @addtogroup cos   
+ * @{   
+ */
+
+/**   
+ * \par   
+ * Table Values are in Q31(1.31 Fixed point format) and generation is done in three steps   
+ * First Generate cos values in floating point:   
+ * tableSize = 256;     
+ * 
    for(n = -1; n < (tableSize + 1); n++)   
+ * {   
+ *	cosTable[n+1]= cos(2*pi*n/tableSize);   
+ * } 
        
+ * where pi value is  3.14159265358979   
+ * \par   
+ * Secondly Convert Floating point to Q31(Fixed point):   
+ *	(cosTable[i] * pow(2, 31))   
+ * \par   
+ * Finally Rounding to nearest integer is done   
+ * 	cosTable[i] += (cosTable[i] > 0 ? 0.5 :-0.5);   
+ */
+
+
+static const q31_t cosTableQ31[259] = {
+  0x7ff62182, 0x7fffffff, 0x7ff62182, 0x7fd8878e, 0x7fa736b4, 0x7f62368f,
+  0x7f0991c4, 0x7e9d55fc,
+  0x7e1d93ea, 0x7d8a5f40, 0x7ce3ceb2, 0x7c29fbee, 0x7b5d039e, 0x7a7d055b,
+  0x798a23b1, 0x78848414,
+  0x776c4edb, 0x7641af3d, 0x7504d345, 0x73b5ebd1, 0x72552c85, 0x70e2cbc6,
+  0x6f5f02b2, 0x6dca0d14,
+  0x6c242960, 0x6a6d98a4, 0x68a69e81, 0x66cf8120, 0x64e88926, 0x62f201ac,
+  0x60ec3830, 0x5ed77c8a,
+  0x5cb420e0, 0x5a82799a, 0x5842dd54, 0x55f5a4d2, 0x539b2af0, 0x5133cc94,
+  0x4ebfe8a5, 0x4c3fdff4,
+  0x49b41533, 0x471cece7, 0x447acd50, 0x41ce1e65, 0x3f1749b8, 0x3c56ba70,
+  0x398cdd32, 0x36ba2014,
+  0x33def287, 0x30fbc54d, 0x2e110a62, 0x2b1f34eb, 0x2826b928, 0x25280c5e,
+  0x2223a4c5, 0x1f19f97b,
+  0x1c0b826a, 0x18f8b83c, 0x15e21445, 0x12c8106f, 0xfab272b, 0xc8bd35e,
+  0x96a9049, 0x647d97c,
+  0x3242abf, 0x0, 0xfcdbd541, 0xf9b82684, 0xf6956fb7, 0xf3742ca2, 0xf054d8d5,
+  0xed37ef91,
+  0xea1debbb, 0xe70747c4, 0xe3f47d96, 0xe0e60685, 0xdddc5b3b, 0xdad7f3a2,
+  0xd7d946d8, 0xd4e0cb15,
+  0xd1eef59e, 0xcf043ab3, 0xcc210d79, 0xc945dfec, 0xc67322ce, 0xc3a94590,
+  0xc0e8b648, 0xbe31e19b,
+  0xbb8532b0, 0xb8e31319, 0xb64beacd, 0xb3c0200c, 0xb140175b, 0xaecc336c,
+  0xac64d510, 0xaa0a5b2e,
+  0xa7bd22ac, 0xa57d8666, 0xa34bdf20, 0xa1288376, 0x9f13c7d0, 0x9d0dfe54,
+  0x9b1776da, 0x99307ee0,
+  0x9759617f, 0x9592675c, 0x93dbd6a0, 0x9235f2ec, 0x90a0fd4e, 0x8f1d343a,
+  0x8daad37b, 0x8c4a142f,
+  0x8afb2cbb, 0x89be50c3, 0x8893b125, 0x877b7bec, 0x8675dc4f, 0x8582faa5,
+  0x84a2fc62, 0x83d60412,
+  0x831c314e, 0x8275a0c0, 0x81e26c16, 0x8162aa04, 0x80f66e3c, 0x809dc971,
+  0x8058c94c, 0x80277872,
+  0x8009de7e, 0x80000000, 0x8009de7e, 0x80277872, 0x8058c94c, 0x809dc971,
+  0x80f66e3c, 0x8162aa04,
+  0x81e26c16, 0x8275a0c0, 0x831c314e, 0x83d60412, 0x84a2fc62, 0x8582faa5,
+  0x8675dc4f, 0x877b7bec,
+  0x8893b125, 0x89be50c3, 0x8afb2cbb, 0x8c4a142f, 0x8daad37b, 0x8f1d343a,
+  0x90a0fd4e, 0x9235f2ec,
+  0x93dbd6a0, 0x9592675c, 0x9759617f, 0x99307ee0, 0x9b1776da, 0x9d0dfe54,
+  0x9f13c7d0, 0xa1288376,
+  0xa34bdf20, 0xa57d8666, 0xa7bd22ac, 0xaa0a5b2e, 0xac64d510, 0xaecc336c,
+  0xb140175b, 0xb3c0200c,
+  0xb64beacd, 0xb8e31319, 0xbb8532b0, 0xbe31e19b, 0xc0e8b648, 0xc3a94590,
+  0xc67322ce, 0xc945dfec,
+  0xcc210d79, 0xcf043ab3, 0xd1eef59e, 0xd4e0cb15, 0xd7d946d8, 0xdad7f3a2,
+  0xdddc5b3b, 0xe0e60685,
+  0xe3f47d96, 0xe70747c4, 0xea1debbb, 0xed37ef91, 0xf054d8d5, 0xf3742ca2,
+  0xf6956fb7, 0xf9b82684,
+  0xfcdbd541, 0x0, 0x3242abf, 0x647d97c, 0x96a9049, 0xc8bd35e, 0xfab272b,
+  0x12c8106f,
+  0x15e21445, 0x18f8b83c, 0x1c0b826a, 0x1f19f97b, 0x2223a4c5, 0x25280c5e,
+  0x2826b928, 0x2b1f34eb,
+  0x2e110a62, 0x30fbc54d, 0x33def287, 0x36ba2014, 0x398cdd32, 0x3c56ba70,
+  0x3f1749b8, 0x41ce1e65,
+  0x447acd50, 0x471cece7, 0x49b41533, 0x4c3fdff4, 0x4ebfe8a5, 0x5133cc94,
+  0x539b2af0, 0x55f5a4d2,
+  0x5842dd54, 0x5a82799a, 0x5cb420e0, 0x5ed77c8a, 0x60ec3830, 0x62f201ac,
+  0x64e88926, 0x66cf8120,
+  0x68a69e81, 0x6a6d98a4, 0x6c242960, 0x6dca0d14, 0x6f5f02b2, 0x70e2cbc6,
+  0x72552c85, 0x73b5ebd1,
+  0x7504d345, 0x7641af3d, 0x776c4edb, 0x78848414, 0x798a23b1, 0x7a7d055b,
+  0x7b5d039e, 0x7c29fbee,
+  0x7ce3ceb2, 0x7d8a5f40, 0x7e1d93ea, 0x7e9d55fc, 0x7f0991c4, 0x7f62368f,
+  0x7fa736b4, 0x7fd8878e,
+  0x7ff62182, 0x7fffffff, 0x7ff62182
+};
+
+/**  
+ * @brief Fast approximation to the trigonometric cosine function for Q31 data.  
+ * @param[in] x Scaled input value in radians.  
+ * @return  cos(x).  
+ *  
+ * The Q31 input value is in the range [0 +1) and is mapped to a radian value in the range [0 2*pi).  
+ */
+
+q31_t arm_cos_q31(
+  q31_t x)
+{
+  q31_t cosVal, in, in2;                         /* Temporary variables for input, output */
+  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */
+  q31_t a, b, c, d;                              /* Four nearest output values */
+  q31_t *tablePtr;                               /* Pointer to table */
+  q31_t fract, fractCube, fractSquare;           /* Temporary values for fractional values */
+  q31_t oneBy6 = 0x15555555;                     /* Fixed point value of 1/6 */
+  q31_t tableSpacing = TABLE_SPACING_Q31;        /* Table spacing */
+  q31_t temp;                                    /* Temporary variable for intermediate process */
+  uint32_t index;                                /* Index variable */
+
+  in = x;
+
+  /* Calculate the nearest index */
+  index = in / tableSpacing;
+
+  /* Calculate the nearest value of input */
+  in2 = ((q31_t) index) * tableSpacing;
+
+  /* Calculation of fractional value */
+  fract = (in - in2) << 8;
+
+  /* fractSquare = fract * fract */
+  fractSquare = ((q31_t) (((q63_t) fract * fract) >> 32));
+  fractSquare = fractSquare << 1;
+
+  /* fractCube = fract * fract * fract */
+  fractCube = ((q31_t) (((q63_t) fractSquare * fract) >> 32));
+  fractCube = fractCube << 1;
+
+  /* Initialise table pointer */
+  tablePtr = (q31_t *) & cosTableQ31[index];
+
+  /* Cubic interpolation process */
+  /* Calculation of wa */
+  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAAAAAA)*fract; */
+  wa = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+  temp = 0x2AAAAAAA;
+  wa = (q31_t) ((((q63_t) wa << 32) + ((q63_t) temp * fract)) >> 32);
+  wa = -(wa << 1u);
+  wa += (fractSquare >> 1u);
+
+  /* Read first nearest value of output from the cos table */
+  a = *tablePtr++;
+
+  /* cosVal = a*wa */
+  cosVal = ((q31_t) (((q63_t) a * wa) >> 32));
+
+  /* q31(1.31) Fixed point value of 1 */
+  temp = 0x7FFFFFFF;
+
+  /* Calculation of wb */
+  wb = ((fractCube >> 1u) - (fractSquare + (fract >> 1u))) + temp;
+  /* Read second nearest value of output from the cos table */
+  b = *tablePtr++;
+
+  /*      cosVal += b*wb */
+  cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) b * (wb))) >> 32);
+
+  /* Calculation of wc */
+  wc = -fractCube + fractSquare;
+  wc = (wc >> 1u) + fract;
+  /* Read third nearest values of output value from the cos table */
+  c = *tablePtr++;
+
+  /*      cosVal += c*wc */
+  cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) c * (wc))) >> 32);
+
+  /* Calculation of wd */
+  /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
+  fractCube = fractCube - fract;
+  wd = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+  wd = (wd << 1u);
+
+  /* Read fourth nearest value of output from the cos table */
+  d = *tablePtr++;
+
+  /* cosVal += d*wd; */
+  cosVal = (q31_t) ((((q63_t) cosVal << 32) + ((q63_t) d * (wd))) >> 32);
+
+  /* convert cosVal in 2.30 format to 1.31 format */
+  return (cosVal << 1u);
+
+}
+
+/**   
+ * @} end of cos group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c
new file mode 100644
index 0000000000..28985cfe1e
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c
@@ -0,0 +1,257 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sin_f32.c   
+*   
+* Description:	Fast sine calculation for floating-point values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFastMath   
+ */
+
+/**   
+ * @defgroup sin Sine   
+ *   
+ * Computes the trigonometric sine function using a combination of table lookup  
+ * and cubic interpolation.  There are separate functions for  
+ * Q15, Q31, and floating-point data types.  
+ * The input to the floating-point version is in radians while the  
+ * fixed-point Q15 and Q31 have a scaled input with the range  
+ * [0 1) mapping to [0 2*pi).  
+ *  
+ * The implementation is based on table lookup using 256 values together with cubic interpolation.  
+ * The steps used are:  
+ *  -# Calculation of the nearest integer table index  
+ *  -# Fetch the four table values a, b, c, and d    
+ *  -# Compute the fractional portion (fract) of the table index.  
+ *  -# Calculation of wa, wb, wc, wd   
+ *  -# The final result equals a*wa + b*wb + c*wc + d*wd  
+ *  
+ * where  
+ * 
       
+ *    a=Table[index-1];   
+ *    b=Table[index+0];   
+ *    c=Table[index+1];   
+ *    d=Table[index+2];   
+ * 
      
+ * and  
+ * 
       
+ *    wa=-(1/6)*fract.^3 + (1/2)*fract.^2 - (1/3)*fract;   
+ *    wb=(1/2)*fract.^3 - fract.^2 - (1/2)*fract + 1;   
+ *    wc=-(1/2)*fract.^3+(1/2)*fract.^2+fract;   
+ *    wd=(1/6)*fract.^3 - (1/6)*fract;   
+ * 
       
+ */
+
+/**   
+ * @addtogroup sin   
+ * @{   
+ */
+
+
+/**  
+ * \par   
+ * Example code for Generation of Floating-point Sin Table:  
+ * tableSize = 256;   
+ * 
    for(n = -1; n < (tableSize + 1); n++)   
+ * {   
+ *	sinTable[n+1]=sin(2*pi*n/tableSize);   
+ * }
       
+ * \par   
+ * where pi value is  3.14159265358979   
+ */
+
+static const float32_t sinTable[259] = {
+  -0.024541229009628296f, 0.000000000000000000f, 0.024541229009628296f,
+  0.049067676067352295f, 0.073564566671848297f, 0.098017141222953796f,
+  0.122410677373409270f, 0.146730467677116390f,
+  0.170961886644363400f, 0.195090323686599730f, 0.219101235270500180f,
+  0.242980182170867920f, 0.266712754964828490f, 0.290284663438797000f,
+  0.313681751489639280f, 0.336889863014221190f,
+  0.359895050525665280f, 0.382683426141738890f, 0.405241310596466060f,
+  0.427555084228515630f, 0.449611335992813110f, 0.471396744251251220f,
+  0.492898195981979370f, 0.514102756977081300f,
+  0.534997642040252690f, 0.555570244789123540f, 0.575808167457580570f,
+  0.595699310302734380f, 0.615231573581695560f, 0.634393274784088130f,
+  0.653172850608825680f, 0.671558976173400880f,
+  0.689540565013885500f, 0.707106769084930420f, 0.724247097969055180f,
+  0.740951120853424070f, 0.757208824157714840f, 0.773010432720184330f,
+  0.788346409797668460f, 0.803207516670227050f,
+  0.817584812641143800f, 0.831469595432281490f, 0.844853579998016360f,
+  0.857728600502014160f, 0.870086967945098880f, 0.881921291351318360f,
+  0.893224298954010010f, 0.903989315032958980f,
+  0.914209783077239990f, 0.923879504203796390f, 0.932992815971374510f,
+  0.941544055938720700f, 0.949528157711029050f, 0.956940352916717530f,
+  0.963776051998138430f, 0.970031261444091800f,
+  0.975702106952667240f, 0.980785250663757320f, 0.985277652740478520f,
+  0.989176511764526370f, 0.992479562759399410f, 0.995184719562530520f,
+  0.997290432453155520f, 0.998795449733734130f,
+  0.999698817729949950f, 1.000000000000000000f, 0.999698817729949950f,
+  0.998795449733734130f, 0.997290432453155520f, 0.995184719562530520f,
+  0.992479562759399410f, 0.989176511764526370f,
+  0.985277652740478520f, 0.980785250663757320f, 0.975702106952667240f,
+  0.970031261444091800f, 0.963776051998138430f, 0.956940352916717530f,
+  0.949528157711029050f, 0.941544055938720700f,
+  0.932992815971374510f, 0.923879504203796390f, 0.914209783077239990f,
+  0.903989315032958980f, 0.893224298954010010f, 0.881921291351318360f,
+  0.870086967945098880f, 0.857728600502014160f,
+  0.844853579998016360f, 0.831469595432281490f, 0.817584812641143800f,
+  0.803207516670227050f, 0.788346409797668460f, 0.773010432720184330f,
+  0.757208824157714840f, 0.740951120853424070f,
+  0.724247097969055180f, 0.707106769084930420f, 0.689540565013885500f,
+  0.671558976173400880f, 0.653172850608825680f, 0.634393274784088130f,
+  0.615231573581695560f, 0.595699310302734380f,
+  0.575808167457580570f, 0.555570244789123540f, 0.534997642040252690f,
+  0.514102756977081300f, 0.492898195981979370f, 0.471396744251251220f,
+  0.449611335992813110f, 0.427555084228515630f,
+  0.405241310596466060f, 0.382683426141738890f, 0.359895050525665280f,
+  0.336889863014221190f, 0.313681751489639280f, 0.290284663438797000f,
+  0.266712754964828490f, 0.242980182170867920f,
+  0.219101235270500180f, 0.195090323686599730f, 0.170961886644363400f,
+  0.146730467677116390f, 0.122410677373409270f, 0.098017141222953796f,
+  0.073564566671848297f, 0.049067676067352295f,
+  0.024541229009628296f, 0.000000000000000122f, -0.024541229009628296f,
+  -0.049067676067352295f, -0.073564566671848297f, -0.098017141222953796f,
+  -0.122410677373409270f, -0.146730467677116390f,
+  -0.170961886644363400f, -0.195090323686599730f, -0.219101235270500180f,
+  -0.242980182170867920f, -0.266712754964828490f, -0.290284663438797000f,
+  -0.313681751489639280f, -0.336889863014221190f,
+  -0.359895050525665280f, -0.382683426141738890f, -0.405241310596466060f,
+  -0.427555084228515630f, -0.449611335992813110f, -0.471396744251251220f,
+  -0.492898195981979370f, -0.514102756977081300f,
+  -0.534997642040252690f, -0.555570244789123540f, -0.575808167457580570f,
+  -0.595699310302734380f, -0.615231573581695560f, -0.634393274784088130f,
+  -0.653172850608825680f, -0.671558976173400880f,
+  -0.689540565013885500f, -0.707106769084930420f, -0.724247097969055180f,
+  -0.740951120853424070f, -0.757208824157714840f, -0.773010432720184330f,
+  -0.788346409797668460f, -0.803207516670227050f,
+  -0.817584812641143800f, -0.831469595432281490f, -0.844853579998016360f,
+  -0.857728600502014160f, -0.870086967945098880f, -0.881921291351318360f,
+  -0.893224298954010010f, -0.903989315032958980f,
+  -0.914209783077239990f, -0.923879504203796390f, -0.932992815971374510f,
+  -0.941544055938720700f, -0.949528157711029050f, -0.956940352916717530f,
+  -0.963776051998138430f, -0.970031261444091800f,
+  -0.975702106952667240f, -0.980785250663757320f, -0.985277652740478520f,
+  -0.989176511764526370f, -0.992479562759399410f, -0.995184719562530520f,
+  -0.997290432453155520f, -0.998795449733734130f,
+  -0.999698817729949950f, -1.000000000000000000f, -0.999698817729949950f,
+  -0.998795449733734130f, -0.997290432453155520f, -0.995184719562530520f,
+  -0.992479562759399410f, -0.989176511764526370f,
+  -0.985277652740478520f, -0.980785250663757320f, -0.975702106952667240f,
+  -0.970031261444091800f, -0.963776051998138430f, -0.956940352916717530f,
+  -0.949528157711029050f, -0.941544055938720700f,
+  -0.932992815971374510f, -0.923879504203796390f, -0.914209783077239990f,
+  -0.903989315032958980f, -0.893224298954010010f, -0.881921291351318360f,
+  -0.870086967945098880f, -0.857728600502014160f,
+  -0.844853579998016360f, -0.831469595432281490f, -0.817584812641143800f,
+  -0.803207516670227050f, -0.788346409797668460f, -0.773010432720184330f,
+  -0.757208824157714840f, -0.740951120853424070f,
+  -0.724247097969055180f, -0.707106769084930420f, -0.689540565013885500f,
+  -0.671558976173400880f, -0.653172850608825680f, -0.634393274784088130f,
+  -0.615231573581695560f, -0.595699310302734380f,
+  -0.575808167457580570f, -0.555570244789123540f, -0.534997642040252690f,
+  -0.514102756977081300f, -0.492898195981979370f, -0.471396744251251220f,
+  -0.449611335992813110f, -0.427555084228515630f,
+  -0.405241310596466060f, -0.382683426141738890f, -0.359895050525665280f,
+  -0.336889863014221190f, -0.313681751489639280f, -0.290284663438797000f,
+  -0.266712754964828490f, -0.242980182170867920f,
+  -0.219101235270500180f, -0.195090323686599730f, -0.170961886644363400f,
+  -0.146730467677116390f, -0.122410677373409270f, -0.098017141222953796f,
+  -0.073564566671848297f, -0.049067676067352295f,
+  -0.024541229009628296f, -0.000000000000000245f, 0.024541229009628296f
+};
+
+
+/**  
+ * @brief  Fast approximation to the trigonometric sine function for floating-point data.  
+ * @param[in] x input value in radians.  
+ * @return  sin(x).  
+ */
+
+float32_t arm_sin_f32(
+  float32_t x)
+{
+  float32_t sinVal, fract, in;                   /* Temporary variables for input, output */
+  uint32_t index;                                /* Index variable */
+  uint32_t tableSize = (uint32_t) TABLE_SIZE;    /* Initialise tablesize */
+  float32_t wa, wb, wc, wd;                      /* Cubic interpolation coefficients */
+  float32_t a, b, c, d;                          /* Four nearest output values */
+  float32_t *tablePtr;                           /* Pointer to table */
+  int32_t n;
+
+  /* input x is in radians */
+  /* Scale the input to [0 1] range from [0 2*PI] , divide input by 2*pi */
+  in = x * 0.159154943092f;
+
+  /* Calculation of floor value of input */
+  n = (int32_t) in;
+
+  /* Make negative values towards -infinity */
+  if(x < 0.0f)
+  {
+    n = n - 1;
+  }
+
+  /* Map input value to [0 1] */
+  in = in - (float32_t) n;
+
+  /* Calculation of index of the table */
+  index = (uint32_t) (tableSize * in);
+
+  /* fractional value calculation */
+  fract = ((float32_t) tableSize * in) - (float32_t) index;
+
+  /* Initialise table pointer */
+  tablePtr = (float32_t *) & sinTable[index];
+
+  /* Read four nearest values of output value from the sin table */
+  a = *tablePtr++;
+  b = *tablePtr++;
+  c = *tablePtr++;
+  d = *tablePtr++;
+
+  /* Cubic interpolation process */
+  wa = -(((0.166666667f) * (fract * (fract * fract))) +
+         ((0.3333333333333f) * fract)) + ((0.5f) * (fract * fract));
+  wb = (((0.5f) * (fract * (fract * fract))) -
+        ((fract * fract) + ((0.5f) * fract))) + 1.0f;
+  wc = (-((0.5f) * (fract * (fract * fract))) +
+        ((0.5f) * (fract * fract))) + fract;
+  wd = ((0.166666667f) * (fract * (fract * fract))) -
+    ((0.166666667f) * fract);
+
+  /* Calculate sin value */
+  sinVal = ((a * wa) + (b * wb)) + ((c * wc) + (d * wd));
+
+  /* Return the output value */
+  return (sinVal);
+
+}
+
+/**   
+ * @} end of sin group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c
new file mode 100644
index 0000000000..d796fc7d43
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c
@@ -0,0 +1,192 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sin_q15.c   
+*   
+* Description:	Fast sine calculation for Q15 values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFastMath   
+ */
+
+ /**   
+ * @addtogroup sin   
+ * @{   
+ */
+
+
+/**   
+ * \par   
+ * Example code for Generation of Q15 Sin Table:  
+ * \par   
+ * 
    tableSize = 256;   
+ * for(n = -1; n < (tableSize + 1); n++)   
+ * {   
+ *	sinTable[n+1]=sin(2*pi*n/tableSize);   
+ * } 
       
+ * where pi value is  3.14159265358979   
+ * \par   
+ * Convert Floating point to Q15(Fixed point):   
+ *	(sinTable[i] * pow(2, 15))   
+ * \par   
+ * rounding to nearest integer is done   
+ * 	sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);   
+ */
+
+
+static const q15_t sinTableQ15[259] = {
+  0xfcdc, 0x0, 0x324, 0x648, 0x96b, 0xc8c, 0xfab, 0x12c8,
+  0x15e2, 0x18f9, 0x1c0c, 0x1f1a, 0x2224, 0x2528, 0x2827, 0x2b1f,
+  0x2e11, 0x30fc, 0x33df, 0x36ba, 0x398d, 0x3c57, 0x3f17, 0x41ce,
+  0x447b, 0x471d, 0x49b4, 0x4c40, 0x4ec0, 0x5134, 0x539b, 0x55f6,
+  0x5843, 0x5a82, 0x5cb4, 0x5ed7, 0x60ec, 0x62f2, 0x64e9, 0x66d0,
+  0x68a7, 0x6a6e, 0x6c24, 0x6dca, 0x6f5f, 0x70e3, 0x7255, 0x73b6,
+  0x7505, 0x7642, 0x776c, 0x7885, 0x798a, 0x7a7d, 0x7b5d, 0x7c2a,
+  0x7ce4, 0x7d8a, 0x7e1e, 0x7e9d, 0x7f0a, 0x7f62, 0x7fa7, 0x7fd9,
+  0x7ff6, 0x7fff, 0x7ff6, 0x7fd9, 0x7fa7, 0x7f62, 0x7f0a, 0x7e9d,
+  0x7e1e, 0x7d8a, 0x7ce4, 0x7c2a, 0x7b5d, 0x7a7d, 0x798a, 0x7885,
+  0x776c, 0x7642, 0x7505, 0x73b6, 0x7255, 0x70e3, 0x6f5f, 0x6dca,
+  0x6c24, 0x6a6e, 0x68a7, 0x66d0, 0x64e9, 0x62f2, 0x60ec, 0x5ed7,
+  0x5cb4, 0x5a82, 0x5843, 0x55f6, 0x539b, 0x5134, 0x4ec0, 0x4c40,
+  0x49b4, 0x471d, 0x447b, 0x41ce, 0x3f17, 0x3c57, 0x398d, 0x36ba,
+  0x33df, 0x30fc, 0x2e11, 0x2b1f, 0x2827, 0x2528, 0x2224, 0x1f1a,
+  0x1c0c, 0x18f9, 0x15e2, 0x12c8, 0xfab, 0xc8c, 0x96b, 0x648,
+  0x324, 0x0, 0xfcdc, 0xf9b8, 0xf695, 0xf374, 0xf055, 0xed38,
+  0xea1e, 0xe707, 0xe3f4, 0xe0e6, 0xdddc, 0xdad8, 0xd7d9, 0xd4e1,
+  0xd1ef, 0xcf04, 0xcc21, 0xc946, 0xc673, 0xc3a9, 0xc0e9, 0xbe32,
+  0xbb85, 0xb8e3, 0xb64c, 0xb3c0, 0xb140, 0xaecc, 0xac65, 0xaa0a,
+  0xa7bd, 0xa57e, 0xa34c, 0xa129, 0x9f14, 0x9d0e, 0x9b17, 0x9930,
+  0x9759, 0x9592, 0x93dc, 0x9236, 0x90a1, 0x8f1d, 0x8dab, 0x8c4a,
+  0x8afb, 0x89be, 0x8894, 0x877b, 0x8676, 0x8583, 0x84a3, 0x83d6,
+  0x831c, 0x8276, 0x81e2, 0x8163, 0x80f6, 0x809e, 0x8059, 0x8027,
+  0x800a, 0x8000, 0x800a, 0x8027, 0x8059, 0x809e, 0x80f6, 0x8163,
+  0x81e2, 0x8276, 0x831c, 0x83d6, 0x84a3, 0x8583, 0x8676, 0x877b,
+  0x8894, 0x89be, 0x8afb, 0x8c4a, 0x8dab, 0x8f1d, 0x90a1, 0x9236,
+  0x93dc, 0x9592, 0x9759, 0x9930, 0x9b17, 0x9d0e, 0x9f14, 0xa129,
+  0xa34c, 0xa57e, 0xa7bd, 0xaa0a, 0xac65, 0xaecc, 0xb140, 0xb3c0,
+  0xb64c, 0xb8e3, 0xbb85, 0xbe32, 0xc0e9, 0xc3a9, 0xc673, 0xc946,
+  0xcc21, 0xcf04, 0xd1ef, 0xd4e1, 0xd7d9, 0xdad8, 0xdddc, 0xe0e6,
+  0xe3f4, 0xe707, 0xea1e, 0xed38, 0xf055, 0xf374, 0xf695, 0xf9b8,
+  0xfcdc, 0x0, 0x324
+};
+
+
+/**  
+ * @brief Fast approximation to the trigonometric sine function for Q15 data.  
+ * @param[in] x Scaled input value in radians.  
+ * @return  sin(x).  
+ *  
+ * The Q15 input value is in the range [0 +1) and is mapped to a radian value in the range [0 2*pi).  
+ */
+
+q15_t arm_sin_q15(
+  q15_t x)
+{
+  q31_t sinVal;                                  /* Temporary variables output */
+  q15_t *tablePtr;                               /* Pointer to table */
+  q15_t fract, in, in2;                          /* Temporary variables for input, output */
+  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */
+  q15_t a, b, c, d;                              /* Four nearest output values */
+  q15_t fractCube, fractSquare;                  /* Temporary values for fractional value */
+  q15_t oneBy6 = 0x1555;                         /* Fixed point value of 1/6 */
+  q15_t tableSpacing = TABLE_SPACING_Q15;        /* Table spacing */
+  int32_t index;                                 /* Index variable */
+
+  in = x;
+
+  /* Calculate the nearest index */
+  index = (int32_t) in / tableSpacing;
+
+  /* Calculate the nearest value of input */
+  in2 = (q15_t) ((index) * tableSpacing);
+
+  /* Calculation of fractional value */
+  fract = (in - in2) << 8;
+
+  /* fractSquare = fract * fract */
+  fractSquare = (q15_t) ((fract * fract) >> 15);
+
+  /* fractCube = fract * fract * fract */
+  fractCube = (q15_t) ((fractSquare * fract) >> 15);
+
+  /* Initialise table pointer */
+  tablePtr = (q15_t *) & sinTableQ15[index];
+
+  /* Cubic interpolation process */
+  /* Calculation of wa */
+  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAA)*fract; */
+  wa = (q31_t) oneBy6 *fractCube;
+  wa += (q31_t) 0x2AAA *fract;
+  wa = -(wa >> 15);
+  wa += ((q31_t) fractSquare >> 1u);
+
+  /* Read first nearest value of output from the sin table */
+  a = *tablePtr++;
+
+  /* sinVal = a * wa */
+  sinVal = a * wa;
+
+  /* Calculation of wb */
+  wb = (((q31_t) fractCube >> 1u) - (q31_t) fractSquare) -
+    (((q31_t) fract >> 1u) - 0x7FFF);
+
+  /* Read second nearest value of output from the sin table */
+  b = *tablePtr++;
+
+  /*      sinVal += b*wb */
+  sinVal += b * wb;
+
+
+  /* Calculation of wc */
+  wc = -(q31_t) fractCube + fractSquare;
+  wc = (wc >> 1u) + fract;
+
+  /* Read third nearest value of output from the sin table */
+  c = *tablePtr++;
+
+  /*      sinVal += c*wc */
+  sinVal += c * wc;
+
+  /* Calculation of wd */
+  /* wd = (oneBy6)*fractCube - (oneBy6)*fract; */
+  fractCube = fractCube - fract;
+  wd = ((q15_t) (((q31_t) oneBy6 * fractCube) >> 15));
+
+  /* Read fourth nearest value of output from the sin table */
+  d = *tablePtr++;
+
+  /* sinVal += d*wd; */
+  sinVal += d * wd;
+
+  /* Return the output value in 1.15(q15) format */
+  return ((q15_t) (sinVal >> 15u));
+
+}
+
+/**   
+ * @} end of sin group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c
new file mode 100644
index 0000000000..0ab10573d7
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c
@@ -0,0 +1,227 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sin_q31.c   
+*   
+* Description:	Fast sine calculation for Q31 values.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFastMath   
+ */
+
+ /**   
+ * @addtogroup sin   
+ * @{   
+ */
+
+/**  
+ * \par   
+ * Tables generated are in Q31(1.31 Fixed point format)   
+ * Generation of sin values in floating point:   
+ * 
    tableSize = 256;     
+ * for(n = -1; n < (tableSize + 1); n++)   
+ * {   
+ *	sinTable[n+1]= sin(2*pi*n/tableSize);   
+ * } 
       
+ * where pi value is  3.14159265358979   
+ * \par   
+ * Convert Floating point to Q31(Fixed point):   
+ *	(sinTable[i] * pow(2, 31))   
+ * \par   
+ * rounding to nearest integer is done   
+ * 	sinTable[i] += (sinTable[i] > 0 ? 0.5 :-0.5);   
+ */
+
+static const q31_t sinTableQ31[259] = {
+  0xfcdbd541, 0x0, 0x3242abf, 0x647d97c, 0x96a9049, 0xc8bd35e, 0xfab272b,
+  0x12c8106f,
+  0x15e21445, 0x18f8b83c, 0x1c0b826a, 0x1f19f97b, 0x2223a4c5, 0x25280c5e,
+  0x2826b928, 0x2b1f34eb,
+  0x2e110a62, 0x30fbc54d, 0x33def287, 0x36ba2014, 0x398cdd32, 0x3c56ba70,
+  0x3f1749b8, 0x41ce1e65,
+  0x447acd50, 0x471cece7, 0x49b41533, 0x4c3fdff4, 0x4ebfe8a5, 0x5133cc94,
+  0x539b2af0, 0x55f5a4d2,
+  0x5842dd54, 0x5a82799a, 0x5cb420e0, 0x5ed77c8a, 0x60ec3830, 0x62f201ac,
+  0x64e88926, 0x66cf8120,
+  0x68a69e81, 0x6a6d98a4, 0x6c242960, 0x6dca0d14, 0x6f5f02b2, 0x70e2cbc6,
+  0x72552c85, 0x73b5ebd1,
+  0x7504d345, 0x7641af3d, 0x776c4edb, 0x78848414, 0x798a23b1, 0x7a7d055b,
+  0x7b5d039e, 0x7c29fbee,
+  0x7ce3ceb2, 0x7d8a5f40, 0x7e1d93ea, 0x7e9d55fc, 0x7f0991c4, 0x7f62368f,
+  0x7fa736b4, 0x7fd8878e,
+  0x7ff62182, 0x7fffffff, 0x7ff62182, 0x7fd8878e, 0x7fa736b4, 0x7f62368f,
+  0x7f0991c4, 0x7e9d55fc,
+  0x7e1d93ea, 0x7d8a5f40, 0x7ce3ceb2, 0x7c29fbee, 0x7b5d039e, 0x7a7d055b,
+  0x798a23b1, 0x78848414,
+  0x776c4edb, 0x7641af3d, 0x7504d345, 0x73b5ebd1, 0x72552c85, 0x70e2cbc6,
+  0x6f5f02b2, 0x6dca0d14,
+  0x6c242960, 0x6a6d98a4, 0x68a69e81, 0x66cf8120, 0x64e88926, 0x62f201ac,
+  0x60ec3830, 0x5ed77c8a,
+  0x5cb420e0, 0x5a82799a, 0x5842dd54, 0x55f5a4d2, 0x539b2af0, 0x5133cc94,
+  0x4ebfe8a5, 0x4c3fdff4,
+  0x49b41533, 0x471cece7, 0x447acd50, 0x41ce1e65, 0x3f1749b8, 0x3c56ba70,
+  0x398cdd32, 0x36ba2014,
+  0x33def287, 0x30fbc54d, 0x2e110a62, 0x2b1f34eb, 0x2826b928, 0x25280c5e,
+  0x2223a4c5, 0x1f19f97b,
+  0x1c0b826a, 0x18f8b83c, 0x15e21445, 0x12c8106f, 0xfab272b, 0xc8bd35e,
+  0x96a9049, 0x647d97c,
+  0x3242abf, 0x0, 0xfcdbd541, 0xf9b82684, 0xf6956fb7, 0xf3742ca2, 0xf054d8d5,
+  0xed37ef91,
+  0xea1debbb, 0xe70747c4, 0xe3f47d96, 0xe0e60685, 0xdddc5b3b, 0xdad7f3a2,
+  0xd7d946d8, 0xd4e0cb15,
+  0xd1eef59e, 0xcf043ab3, 0xcc210d79, 0xc945dfec, 0xc67322ce, 0xc3a94590,
+  0xc0e8b648, 0xbe31e19b,
+  0xbb8532b0, 0xb8e31319, 0xb64beacd, 0xb3c0200c, 0xb140175b, 0xaecc336c,
+  0xac64d510, 0xaa0a5b2e,
+  0xa7bd22ac, 0xa57d8666, 0xa34bdf20, 0xa1288376, 0x9f13c7d0, 0x9d0dfe54,
+  0x9b1776da, 0x99307ee0,
+  0x9759617f, 0x9592675c, 0x93dbd6a0, 0x9235f2ec, 0x90a0fd4e, 0x8f1d343a,
+  0x8daad37b, 0x8c4a142f,
+  0x8afb2cbb, 0x89be50c3, 0x8893b125, 0x877b7bec, 0x8675dc4f, 0x8582faa5,
+  0x84a2fc62, 0x83d60412,
+  0x831c314e, 0x8275a0c0, 0x81e26c16, 0x8162aa04, 0x80f66e3c, 0x809dc971,
+  0x8058c94c, 0x80277872,
+  0x8009de7e, 0x80000000, 0x8009de7e, 0x80277872, 0x8058c94c, 0x809dc971,
+  0x80f66e3c, 0x8162aa04,
+  0x81e26c16, 0x8275a0c0, 0x831c314e, 0x83d60412, 0x84a2fc62, 0x8582faa5,
+  0x8675dc4f, 0x877b7bec,
+  0x8893b125, 0x89be50c3, 0x8afb2cbb, 0x8c4a142f, 0x8daad37b, 0x8f1d343a,
+  0x90a0fd4e, 0x9235f2ec,
+  0x93dbd6a0, 0x9592675c, 0x9759617f, 0x99307ee0, 0x9b1776da, 0x9d0dfe54,
+  0x9f13c7d0, 0xa1288376,
+  0xa34bdf20, 0xa57d8666, 0xa7bd22ac, 0xaa0a5b2e, 0xac64d510, 0xaecc336c,
+  0xb140175b, 0xb3c0200c,
+  0xb64beacd, 0xb8e31319, 0xbb8532b0, 0xbe31e19b, 0xc0e8b648, 0xc3a94590,
+  0xc67322ce, 0xc945dfec,
+  0xcc210d79, 0xcf043ab3, 0xd1eef59e, 0xd4e0cb15, 0xd7d946d8, 0xdad7f3a2,
+  0xdddc5b3b, 0xe0e60685,
+  0xe3f47d96, 0xe70747c4, 0xea1debbb, 0xed37ef91, 0xf054d8d5, 0xf3742ca2,
+  0xf6956fb7, 0xf9b82684,
+  0xfcdbd541, 0x0, 0x3242abf
+};
+
+
+/**  
+ * @brief Fast approximation to the trigonometric sine function for Q31 data.  
+ * @param[in] x Scaled input value in radians.  
+ * @return  sin(x).  
+ *  
+ * The Q31 input value is in the range [0 +1) and is mapped to a radian value in the range [0 2*pi).  
+ */
+
+q31_t arm_sin_q31(
+  q31_t x)
+{
+  q31_t sinVal, in, in2;                         /* Temporary variables for input, output */
+  uint32_t index;                                /* Index variables */
+  q31_t wa, wb, wc, wd;                          /* Cubic interpolation coefficients */
+  q31_t a, b, c, d;                              /* Four nearest output values */
+  q31_t *tablePtr;                               /* Pointer to table */
+  q31_t fract, fractCube, fractSquare;           /* Temporary values for fractional values */
+  q31_t oneBy6 = 0x15555555;                     /* Fixed point value of 1/6 */
+  q31_t tableSpacing = TABLE_SPACING_Q31;        /* Table spacing */
+  q31_t temp;                                    /* Temporary variable for intermediate process */
+
+  in = x;
+
+  /* Calculate the nearest index */
+  index = (uint32_t) in / (uint32_t) tableSpacing;
+
+  /* Calculate the nearest value of input */
+  in2 = (q31_t) index *tableSpacing;
+
+  /* Calculation of fractional value */
+  fract = (in - in2) << 8;
+
+  /* fractSquare = fract * fract */
+  fractSquare = ((q31_t) (((q63_t) fract * fract) >> 32));
+  fractSquare = fractSquare << 1;
+
+  /* fractCube = fract * fract * fract */
+  fractCube = ((q31_t) (((q63_t) fractSquare * fract) >> 32));
+  fractCube = fractCube << 1;
+
+  /* Initialise table pointer */
+  tablePtr = (q31_t *) & sinTableQ31[index];
+
+  /* Cubic interpolation process */
+  /* Calculation of wa */
+  /* wa = -(oneBy6)*fractCube + (fractSquare >> 1u) - (0x2AAAAAAA)*fract; */
+  wa = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+  temp = 0x2AAAAAAA;
+  wa = (q31_t) ((((q63_t) wa << 32) + ((q63_t) temp * fract)) >> 32);
+  wa = -(wa << 1u);
+  wa += (fractSquare >> 1u);
+
+  /* Read first nearest value of output from the sin table */
+  a = *tablePtr++;
+
+  /* sinVal = a*wa */
+  sinVal = ((q31_t) (((q63_t) a * wa) >> 32));
+
+  /* q31(1.31) Fixed point value of 1 */
+  temp = 0x7FFFFFFF;
+
+  /* Calculation of wb */
+  wb = ((fractCube >> 1u) - (fractSquare + (fract >> 1u))) + temp;
+
+  /* Read second nearest value of output from the sin table */
+  b = *tablePtr++;
+
+  /*  sinVal += b*wb */
+  sinVal = (q31_t) ((((q63_t) sinVal << 32) + (q63_t) b * (wb)) >> 32);
+
+  /* Calculation of wc */
+  wc = -fractCube + fractSquare;
+  wc = (wc >> 1u) + fract;
+
+  /* Read third nearest value of output from the sin table */
+  c = *tablePtr++;
+
+  /*      sinVal += c*wc */
+  sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) c * wc)) >> 32);
+
+  /* Calculation of wd */
+  /* wd = (oneBy6) * fractCube - (oneBy6) * fract; */
+  fractCube = fractCube - fract;
+  wd = ((q31_t) (((q63_t) oneBy6 * fractCube) >> 32));
+  wd = (wd << 1u);
+
+  /* Read fourth nearest value of output from the sin table */
+  d = *tablePtr++;
+
+  /* sinVal += d*wd; */
+  sinVal = (q31_t) ((((q63_t) sinVal << 32) + ((q63_t) d * wd)) >> 32);
+
+  /* convert sinVal in 2.30 format to 1.31 format */
+  return (sinVal << 1u);
+
+}
+
+/**   
+ * @} end of sin group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c
new file mode 100644
index 0000000000..7e27baacbf
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c
@@ -0,0 +1,178 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_sqrt_q15.c   
+*   
+* Description:	Q15 square root function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+
+/**   
+ * @ingroup groupFastMath   
+ */
+
+/**   
+ * @addtogroup SQRT   
+ * @{   
+ */
+
+  /**  
+   * @brief  Q15 square root function.  
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.  
+   * @param[out]  *pOut  square root of input value.  
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if  
+   * in is negative value and returns zero output for negative values.  
+   */
+
+arm_status arm_sqrt_q15(
+  q15_t in,
+  q15_t * pOut)
+{
+  q31_t prevOut;
+  q15_t oneByOut;
+  uint32_t sign_bits;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t out;
+
+  if(in > 0)
+  {
+    /* run for ten iterations */
+
+    /* Take initial guess as half of the input and first iteration */
+    out = ((q31_t) in >> 1u) + 0x3FFF;
+
+    /* Calculation of reciprocal of out */
+    /* oneByOut contains reciprocal of out which is in 2.14 format   
+       and oneByOut should be upscaled by signBits */
+    sign_bits = arm_recip_q15((q15_t) out, &oneByOut, armRecipTableQ15);
+
+    /* 0.5 * (out) */
+    out = out >> 1u;
+    /* prevOut = 0.5 * out + (in * (oneByOut << signBits))) */
+    prevOut = out + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    /* Third iteration */
+    sign_bits = arm_recip_q15((q15_t) prevOut, &oneByOut, armRecipTableQ15);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    sign_bits = arm_recip_q15((q15_t) out, &oneByOut, armRecipTableQ15);
+    out = out >> 1u;
+    prevOut = out + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    /* Fifth iteration */
+    sign_bits = arm_recip_q15((q15_t) prevOut, &oneByOut, armRecipTableQ15);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    sign_bits = arm_recip_q15((q15_t) out, &oneByOut, armRecipTableQ15);
+    out = out >> 1u;
+    prevOut = out + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    /* Seventh iteration */
+    sign_bits = arm_recip_q15((q15_t) prevOut, &oneByOut, armRecipTableQ15);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    sign_bits = arm_recip_q15((q15_t) out, &oneByOut, armRecipTableQ15);
+    out = out >> 1u;
+    prevOut = out + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    sign_bits = arm_recip_q15((q15_t) prevOut, &oneByOut, armRecipTableQ15);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    /* tenth iteration */
+    sign_bits = arm_recip_q15((q15_t) out, &oneByOut, armRecipTableQ15);
+    out = out >> 1u;
+    *pOut = out + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    return (ARM_MATH_SUCCESS);
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t out, loopVar;                            /* Temporary variable for output, loop variable */
+  if(in > 0)
+  {
+    /* run for ten iterations */
+
+    /* Take initial guess as half of the input and first iteration */
+    out = ((q31_t) in >> 1u) + 0x3FFF;
+
+    /* Calculation of reciprocal of out */
+
+    /* oneByOut contains reciprocal of out which is in 2.14 format   
+       and oneByOut should be upscaled by sign bits */
+    sign_bits = arm_recip_q15((q15_t) out, &oneByOut, armRecipTableQ15);
+
+    /* 0.5 * (out) */
+    out = out >> 1u;
+    /* prevOut = 0.5 * out + (in * oneByOut) << signbits))) */
+    prevOut = out + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+
+    /* loop for third iteration to tenth iteration */
+
+    for (loopVar = 1; loopVar <= 8; loopVar++)
+    {
+
+      sign_bits = arm_recip_q15((q15_t) prevOut, &oneByOut, armRecipTableQ15);
+      /* 0.5 * (prevOut) */
+      prevOut = prevOut >> 1u;
+      /* prevOut = 0.5 * prevOut+ (in * oneByOut) << signbits))) */
+      out =
+        prevOut + (((q15_t) (((q31_t) in * oneByOut) >> 16)) << sign_bits);
+      /* prevOut      = out */
+      prevOut = out;
+
+    }
+    /* output is moved to pOut pointer */
+    *pOut = prevOut;
+
+    return (ARM_MATH_SUCCESS);
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  else
+  {
+
+    *pOut = 0;
+    return (ARM_MATH_ARGUMENT_ERROR);
+  }
+
+}
+
+/**   
+ * @} end of SQRT group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c
new file mode 100644
index 0000000000..ab2779e79a
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c
@@ -0,0 +1,199 @@
+/* ----------------------------------------------------------------------  
+* Copyright (C) 2010 ARM Limited. All rights reserved.  
+*  
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*  
+* Project: 	    CMSIS DSP Library  
+* Title:		arm_sqrt_q31.c  
+*  
+* Description:	Q31 square root function. 
+*  
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.2 2010/11/11  
+*    Documentation updated.   
+*  
+* Version 1.0.1 2010/10/05   
+*    Production release and review comments incorporated.  
+*  
+* Version 1.0.0 2010/09/20   
+*    Production release and review comments incorporated. 
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**  
+ * @ingroup groupFastMath  
+ */
+
+/**  
+ * @addtogroup SQRT  
+ * @{  
+ */
+
+/** 
+ * @brief Q31 square root function. 
+ * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF. 
+ * @param[out]  *pOut square root of input value. 
+ * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if 
+ * in is negative value and returns zero output for negative values. 
+ */
+
+arm_status arm_sqrt_q31(
+  q31_t in,
+  q31_t * pOut)
+{
+  q63_t prevOut;
+  q31_t oneByOut;
+  uint32_t signBits;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q63_t out;
+
+  if(in > 0)
+  {
+
+    /* run for ten iterations */
+
+    /* Take initial guess as half of the input and first iteration */
+    out = (in >> 1) + 0x3FFFFFFF;
+
+    /* Calculation of reciprocal of out */
+    /* oneByOut contains reciprocal of out which is in 2.30 format  
+       and oneByOut should be upscaled by signBits */
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+
+    /* 0.5 * (out) */
+    out = out >> 1u;
+
+    /* prevOut = 0.5 * out + (in * (oneByOut << signBits))) */
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    /* Third iteration */
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    /* Fifth iteration */
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    /* Seventh iteration */
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+    prevOut = prevOut >> 1u;
+    out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    /* tenth iteration */
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+    out = out >> 1u;
+    *pOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+    return (ARM_MATH_SUCCESS);
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t out, loopVar;                            /* Temporary variable for output, loop variable */
+  if(in > 0)
+  {
+
+    /* run for ten iterations */
+
+    /* Take initial guess as half of the input and first iteration */
+    out = (in >> 1) + 0x3FFFFFFF;
+
+    /* Calculation of reciprocal of out */
+    /* oneByOut contains reciprocal of out which is in 2.30 format   
+       and oneByOut should be upscaled by sign bits */
+    signBits = arm_recip_q31((q31_t) out, &oneByOut, armRecipTableQ31);
+
+    /* 0.5 * (out) */
+    out = out >> 1u;
+
+    /* prevOut = 0.5 * out + (in * (oneByOut) << signbits) */
+    prevOut = out + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+
+
+    /* loop for third iteration to tength iteration */
+
+    for (loopVar = 1; loopVar <= 14; loopVar++)
+    {
+
+      signBits = arm_recip_q31((q31_t) prevOut, &oneByOut, armRecipTableQ31);
+      /* 0.5 * (prevOut) */
+      prevOut = prevOut >> 1u;
+      /* out = 0.5 * prevOut + (in * oneByOut) << signbits))) */
+      out = prevOut + (((q31_t) (((q63_t) in * oneByOut) >> 32)) << signBits);
+      /* prevOut      = out */
+      prevOut = out;
+
+    }
+    /* output is moved to pOut pointer */
+    *pOut = prevOut;
+
+    return (ARM_MATH_SUCCESS);
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  else
+  {
+    *pOut = 0;
+    return (ARM_MATH_ARGUMENT_ERROR);
+  }
+}
+
+/**  
+ * @} end of SQRT group  
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
new file mode 100644
index 0000000000..ec4b058a96
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
@@ -0,0 +1,102 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_32x64_init_q31.c   
+*   
+* Description:	High precision Q31 Biquad cascade filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1_32x64   
+ * @{   
+ */
+
+/**   
+ * @details   
+ *   
+ * @param[in,out] *S           	points to an instance of the high precision Q31 Biquad cascade filter structure.   
+ * @param[in]     numStages     number of 2nd order stages in the filter.   
+ * @param[in]     *pCoeffs      points to the filter coefficients.   
+ * @param[in]     *pState       points to the state buffer.   
+ * @param[in]     postShift     Shift to be applied after the accumulator.  Varies according to the coefficients format.   
+ * @return        none   
+ *   
+ * Coefficient and State Ordering:   
+ *   
+ * \par   
+ * The coefficients are stored in the array pCoeffs in the following order:   
+ * 
       
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}   
+ * 
       
+ * where b1x and a1x are the coefficients for the first stage,   
+ * b2x and a2x are the coefficients for the second stage,   
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.   
+ *   
+ * \par   
+ * The pState points to state variables array and size of each state variable is 1.63 format.   
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].   
+ * The state variables are arranged in the state array as:   
+ * 
       
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ * 
       
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.   
+ * The state array has a total length of 4*numStages values.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ */
+
+void arm_biquad_cas_df1_32x64_init_q31(
+  arm_biquad_cas_df1_32x64_ins_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q63_t * pState,
+  uint8_t postShift)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign postShift to be applied to the output */
+  S->postShift = postShift;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q63_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**   
+ * @} end of BiquadCascadeDF1_32x64 group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
new file mode 100644
index 0000000000..35cfe856f6
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
@@ -0,0 +1,476 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_32x64_q31.c   
+*   
+* Description:	High precision Q31 Biquad cascade filter processing function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup BiquadCascadeDF1_32x64 High Precision Q31 Biquad Cascade Filter   
+ *   
+ * This function implements a high precision Biquad cascade filter which operates on   
+ * Q31 data values.  The filter coefficients are in 1.31 format and the state variables   
+ * are in 1.63 format.  The double precision state variables reduce quantization noise   
+ * in the filter and provide a cleaner output.   
+ * These filters are particularly useful when implementing filters in which the   
+ * singularities are close to the unit circle.  This is common for low pass or high   
+ * pass filters with very low cutoff frequencies.   
+ *   
+ * The function operates on blocks of input and output data   
+ * and each call to the function processes blockSize samples through   
+ * the filter. pSrc and pDst points to input and output arrays   
+ * containing blockSize Q31 values.   
+ *   
+ * \par Algorithm   
+ * Each Biquad stage implements a second order filter using the difference equation:   
+ * 
       
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+ * 
       
+ * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.   
+ * \image html Biquad.gif "Single Biquad filter stage"   
+ * Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.   
+ * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.   
+ * Pay careful attention to the sign of the feedback coefficients.   
+ * Some design tools use the difference equation   
+ * 
       
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]   
+ * 
       
+ * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.   
+ *   
+ * \par   
+ * Higher order filters are realized as a cascade of second order sections.   
+ * numStages refers to the number of second order stages used.   
+ * For example, an 8th order filter would be realized with numStages=4 second order stages.   
+ * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"   
+ * A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).   
+ *   
+ * \par   
+ * The pState points to state variables array .   
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2] and each state variable in 1.63 format to improve precision.   
+ * The state variables are arranged in the array as:   
+ * 
       
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ * 
       
+ *   
+ * \par   
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.   
+ * The state array has a total length of 4*numStages values of data in 1.63 format.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ *   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.   
+ *   
+ * \par Init Function   
+ * There is also an associated initialization function which performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros before static initialization.   
+ * For example, to statically initialize the filter instance structure use   
+ * 
       
+ *     arm_biquad_cas_df1_32x64_ins_q31 S1 = {numStages, pState, pCoeffs, postShift};   
+ * 
       
+ * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer;   
+ * pCoeffs is the address of the coefficient buffer; postShift shift to be applied which is described in detail below.   
+ * \par Fixed-Point Behavior   
+ * Care must be taken while using Biquad Cascade 32x64 filter function.   
+ * Following issues must be considered:   
+ * - Scaling of coefficients   
+ * - Filter gain   
+ * - Overflow and saturation   
+ *   
+ * \par   
+ * Filter coefficients are represented as fractional values and   
+ * restricted to lie in the range [-1 +1).   
+ * The processing function has an additional scaling parameter postShift   
+ * which allows the filter coefficients to exceed the range [+1 -1).   
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.   
+ * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"   
+ * This essentially scales the filter coefficients by 2^postShift.   
+ * For example, to realize the coefficients   
+ * 
       
+ *    {1.5, -0.8, 1.2, 1.6, -0.9}   
+ * 
       
+ * set the Coefficient array to:   
+ * 
       
+ *    {0.75, -0.4, 0.6, 0.8, -0.45}   
+ * 
       
+ * and set postShift=1   
+ *   
+ * \par   
+ * The second thing to keep in mind is the gain through the filter.   
+ * The frequency response of a Biquad filter is a function of its coefficients.   
+ * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.   
+ * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.   
+ * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.   
+ *   
+ * \par   
+ * The third item to consider is the overflow and saturation behavior of the fixed-point Q31 version.   
+ * This is described in the function specific documentation below.   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1_32x64   
+ * @{   
+ */
+
+/**   
+ * @details   
+   
+ * @param[in]  *S points to an instance of the high precision Q31 Biquad cascade filter.   
+ * @param[in]  *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in]  blockSize number of samples to process.   
+ * @return none.   
+ *   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around rather than clip.   
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).   
+ * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to   
+ * 1.31 format by discarding the low 32 bits.   
+ *   
+ * \par   
+ * Two related functions are provided in the CMSIS DSP library.   
+ * arm_biquad_cascade_df1_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q63 accumulator.   
+ * arm_biquad_cascade_df1_fast_q31() implements a Biquad cascade with 32-bit coefficients and state variables with a Q31 accumulator.   
+ */
+
+void arm_biquad_cas_df1_32x64_q31(
+  const arm_biquad_cas_df1_32x64_ins_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
+  q31_t *pOut = pDst;                            /*  output pointer initialization */
+  q63_t *pState = S->pState;                     /*  state pointer initialization  */
+  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
+  q63_t acc;                                     /*  accumulator                   */
+  q63_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q63_t Xn;                                      /*  temporary input               */
+  int32_t shift = (int32_t) S->postShift + 1;    /*  Shift to be applied to the output */
+  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /* The variable acc hold output value that is being computed and   
+     * stored in the destination buffer   
+     * acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     */
+
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling. Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* The value is shifted to the MSB to perform 32x64 multiplication */
+      Xn = Xn << 32;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = mult32x64(Xn, b0);
+      /* acc +=  b1 * x[n-1] */
+      acc += mult32x64(Xn1, b1);
+      /* acc +=  b[2] * x[n-2] */
+      acc += mult32x64(Xn2, b2);
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* The result is converted to 1.63 , Yn2 variable is reused */
+      Yn2 = acc << shift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = (q31_t) (acc >> (32 - shift));
+
+      /* Read the second input into Xn2, to reuse the value */
+      Xn2 = *pIn++;
+
+      /* The value is shifted to the MSB to perform 32x64 multiplication */
+      Xn2 = Xn2 << 32;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = mult32x64(Xn2, b0);
+      /* acc +=  b1 * x[n-1] */
+      acc += mult32x64(Xn, b1);
+      /* acc +=  b[2] * x[n-2] */
+      acc += mult32x64(Xn1, b2);
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn2, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn1, a2);
+
+      /* The result is converted to 1.63, Yn1 variable is reused */
+      Yn1 = acc << shift;
+
+      /* The result is converted to 1.31 */
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q31_t) (acc >> (32 - shift));
+
+      /* Read the third input into Xn1, to reuse the value */
+      Xn1 = *pIn++;
+
+      /* The value is shifted to the MSB to perform 32x64 multiplication */
+      Xn1 = Xn1 << 32;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = mult32x64(Xn1, b0);
+      /* acc +=  b1 * x[n-1] */
+      acc += mult32x64(Xn2, b1);
+      /* acc +=  b[2] * x[n-2] */
+      acc += mult32x64(Xn, b2);
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* The result is converted to 1.63, Yn2 variable is reused  */
+      Yn2 = acc << shift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = (q31_t) (acc >> (32 - shift));
+
+      /* Read the fourth input into Xn, to reuse the value */
+      Xn = *pIn++;
+
+      /* The value is shifted to the MSB to perform 32x64 multiplication */
+      Xn = Xn << 32;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = mult32x64(Xn, b0);
+      /* acc +=  b1 * x[n-1] */
+      acc += mult32x64(Xn1, b1);
+      /* acc +=  b[2] * x[n-2] */
+      acc += mult32x64(Xn2, b2);
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn2, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn1, a2);
+
+      /* The result is converted to 1.63, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = (q31_t) (acc >> (32 - shift));
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    sample = (blockSize & 0x3u);
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* The value is shifted to the MSB to perform 32x64 multiplication */
+      Xn = Xn << 32;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = mult32x64(Xn, b0);
+      /* acc +=  b1 * x[n-1] */
+      acc += mult32x64(Xn1, b1);
+      /* acc +=  b[2] * x[n-2] */
+      acc += mult32x64(Xn2, b2);
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc << shift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = (q31_t) (acc >> (32 - shift));
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage output is given as input to the second stage. */
+    pIn = pDst;
+
+    /* Reset to destination buffer working pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* The variable acc hold output value that is being computed and       
+     * stored in the destination buffer           
+     * acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]           
+     */
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* The value is shifted to the MSB to perform 32x64 multiplication */
+      Xn = Xn << 32;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = mult32x64(Xn, b0);
+      /* acc +=  b1 * x[n-1] */
+      acc += mult32x64(Xn1, b1);
+      /* acc +=  b[2] * x[n-2] */
+      acc += mult32x64(Xn2, b2);
+      /* acc +=  a1 * y[n-1] */
+      acc += mult32x64(Yn1, a1);
+      /* acc +=  a2 * y[n-2] */
+      acc += mult32x64(Yn2, a2);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc << shift;
+
+      /* Store the output in the destination buffer in 1.31 format. */
+      *pOut++ = (q31_t) (acc >> (32 - shift));
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage output is given as input to the second stage. */
+    pIn = pDst;
+
+    /* Reset to destination buffer working pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#endif /*    #ifndef ARM_MATH_CM0     */
+}
+
+  /**   
+   * @} end of BiquadCascadeDF1_32x64 group   
+   */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
new file mode 100644
index 0000000000..b5a744d0ff
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
@@ -0,0 +1,418 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_f32.c   
+*   
+* Description:	Processing function for the   
+*               floating-point Biquad cascade DirectFormI(DF1) filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup BiquadCascadeDF1 Biquad Cascade IIR Filters Using Direct Form I Structure   
+ *   
+ * This set of functions implements arbitrary order recursive (IIR) filters.   
+ * The filters are implemented as a cascade of second order Biquad sections.   
+ * The functions support Q15, Q31 and floating-point data types. 
+ * Fast version of Q15 and Q31 also supported on CortexM4 and Cortex-M3.   
+ *   
+ * The functions operate on blocks of input and output data and each call to the function   
+ * processes blockSize samples through the filter.   
+ * pSrc points to the array of input data and   
+ * pDst points to the array of output data.   
+ * Both arrays contain blockSize values.   
+ *   
+ * \par Algorithm   
+ * Each Biquad stage implements a second order filter using the difference equation:   
+ * 
       
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+ * 
       
+ * A Direct Form I algorithm is used with 5 coefficients and 4 state variables per stage.   
+ * \image html Biquad.gif "Single Biquad filter stage"   
+ * Coefficients b0, b1 and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.   
+ * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.   
+ * Pay careful attention to the sign of the feedback coefficients.   
+ * Some design tools use the difference equation   
+ * 
       
+ *     y[n] = b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] - a1 * y[n-1] - a2 * y[n-2]   
+ * 
       
+ * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.   
+ *   
+ * \par   
+ * Higher order filters are realized as a cascade of second order sections.   
+ * numStages refers to the number of second order stages used.   
+ * For example, an 8th order filter would be realized with numStages=4 second order stages.   
+ * \image html BiquadCascade.gif "8th order filter using a cascade of Biquad stages"   
+ * A 9th order filter would be realized with numStages=5 second order stages with the coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).   
+ *   
+ * \par   
+ * The pState points to state variables array.   
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].   
+ * The state variables are arranged in the pState array as:   
+ * 
       
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ * 
       
+ *   
+ * \par   
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.   
+ * The state array has a total length of 4*numStages values.   
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.   
+ *   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Init Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros before static initialization.   
+ * The code below statically initializes each of the 3 different data type filter instance structures   
+ * 
       
+ *     arm_biquad_casd_df1_inst_f32 S1 = {numStages, pState, pCoeffs};   
+ *     arm_biquad_casd_df1_inst_q15 S2 = {numStages, pState, pCoeffs, postShift};   
+ *     arm_biquad_casd_df1_inst_q31 S3 = {numStages, pState, pCoeffs, postShift};   
+ * 
       
+ * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer;   
+ * pCoeffs is the address of the coefficient buffer; postShift shift to be applied.   
+ *   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the Q15 and Q31 versions of the Biquad Cascade filter functions.   
+ * Following issues must be considered:   
+ * - Scaling of coefficients   
+ * - Filter gain   
+ * - Overflow and saturation   
+ *   
+ * \par   
+ * Scaling of coefficients:    
+ * Filter coefficients are represented as fractional values and   
+ * coefficients are restricted to lie in the range [-1 +1).   
+ * The fixed-point functions have an additional scaling parameter postShift   
+ * which allow the filter coefficients to exceed the range [+1 -1).   
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.   
+ * \image html BiquadPostshift.gif "Fixed-point Biquad with shift by postShift bits after accumulator"   
+ * This essentially scales the filter coefficients by 2^postShift.   
+ * For example, to realize the coefficients   
+ * 
       
+ *    {1.5, -0.8, 1.2, 1.6, -0.9}   
+ * 
       
+ * set the pCoeffs array to:   
+ * 
       
+ *    {0.75, -0.4, 0.6, 0.8, -0.45}   
+ * 
       
+ * and set postShift=1   
+ *   
+ * \par   
+ * Filter gain:    
+ * The frequency response of a Biquad filter is a function of its coefficients.   
+ * It is possible for the gain through the filter to exceed 1.0 meaning that the filter increases the amplitude of certain frequencies.   
+ * This means that an input signal with amplitude < 1.0 may result in an output > 1.0 and these are saturated or overflowed based on the implementation of the filter.   
+ * To avoid this behavior the filter needs to be scaled down such that its peak gain < 1.0 or the input signal must be scaled down so that the combination of input and filter are never overflowed.   
+ *   
+ * \par   
+ * Overflow and saturation:    
+ * For Q15 and Q31 versions, it is described separately as part of the function specific documentation below.   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.   
+ * @param[in]  *pSrc      points to the block of input data.   
+ * @param[out] *pDst      points to the block of output data.   
+ * @param[in]  blockSize  number of samples to process per call.   
+ * @return     none.   
+ *   
+ */
+
+void arm_biquad_cascade_df1_f32(
+  const arm_biquad_casd_df1_inst_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /*  source pointer            */
+  float32_t *pOut = pDst;                        /*  destination pointer       */
+  float32_t *pState = S->pState;                 /*  pState pointer            */
+  float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
+  float32_t acc;                                 /*  Simulates the accumulator */
+  float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
+  float32_t Xn1, Xn2, Yn1, Yn2;                  /*  Filter pState variables   */
+  float32_t Xn;                                  /*  temporary input           */
+  uint32_t sample, stage = S->numStages;         /*  loop counters             */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the pState values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:   
+     *   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]   
+     */
+
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the first input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn2 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+
+      /* Read the second input */
+      Xn2 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn1 = (b0 * Xn2) + (b1 * Xn) + (b2 * Xn1) + (a1 * Yn2) + (a2 * Yn1);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+
+      /* Read the third input */
+      Xn1 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn2 = (b0 * Xn1) + (b1 * Xn2) + (b2 * Xn) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as: */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+
+      /* Read the forth input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      Yn1 = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn2) + (a2 * Yn1);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    sample = blockSize & 0x3u;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:    */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc;
+
+      /* decrement the loop counter */
+      sample--;
+
+    }
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent numStages  occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /* decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the pState values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /*      The variables acc holds the output value that is computed:       
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1]   + a2 * y[n-2]       
+     */
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      acc = (b0 * Xn) + (b1 * Xn1) + (b2 * Xn2) + (a1 * Yn1) + (a2 * Yn2);
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:    */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent numStages  occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /* decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#endif /*   #ifndef ARM_MATH_CM0         */
+
+}
+
+
+  /**   
+   * @} end of BiquadCascadeDF1 group   
+   */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
new file mode 100644
index 0000000000..c2270fabdf
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
@@ -0,0 +1,283 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_fast_q15.c   
+*   
+* Description:	Fast processing function for the   
+*				Q15 Biquad cascade filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.9  2010/08/16    
+*    Initial version   
+*   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @details   
+ * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.   
+ * @param[in]  *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in]  blockSize number of samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * This fast version uses a 32-bit accumulator with 2.30 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.   
+ * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25).   
+ * The 2.30 accumulator is then shifted by postShift bits and the result truncated to 1.15 format by discarding the low 16 bits.   
+ *   
+ * \par   
+ * Refer to the function arm_biquad_cascade_df1_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.  Both the slow and the fast versions use the same instance structure.   
+ * Use the function arm_biquad_cascade_df1_init_q15() to initialize the filter structure.   
+ *   
+ */
+
+void arm_biquad_cascade_df1_fast_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /*  Source pointer                               */
+  q15_t *pOut = pDst;                            /*  Destination pointer                          */
+  q31_t in;                                      /*  Temporary variable to hold input value       */
+  q31_t out;                                     /*  Temporary variable to hold output value      */
+  q31_t b0;                                      /*  Temporary variable to hold bo value          */
+  q31_t b1, a1;                                  /*  Filter coefficients                          */
+  q31_t state_in, state_out;                     /*  Filter state variables                       */
+  q31_t acc0;                                    /*  Accumulator                                  */
+  int32_t shift = (int32_t) (15 - S->postShift); /*  Post shift                                   */
+  q15_t *pState = S->pState;                     /*  State pointer                                */
+  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
+  q31_t *pState_q31;                             /*  32-bit state pointer for SIMD implementation */
+  uint32_t sample, stage = S->numStages;         /*  Stage loop counter                           */
+
+
+
+  do
+  {
+    /* Initialize state pointer of type q31 */
+    pState_q31 = (q31_t *) (pState);
+
+    /* Read the b0 and 0 coefficients using SIMD  */
+    b0 = *__SIMD32(pCoeffs)++;
+
+    /* Read the b1 and b2 coefficients using SIMD */
+    b1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the a1 and a2 coefficients using SIMD */
+    a1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the input state values from the state buffer:  x[n-1], x[n-2] */
+    state_in = (q31_t) (*pState_q31++);
+
+    /* Read the output state values from the state buffer:  y[n-1], y[n-2] */
+    state_out = (q31_t) (*pState_q31);
+
+    /* Apply loop unrolling and compute 2 output values simultaneously. */
+    /*      The variables acc0 ... acc3 hold output values that are being computed:   
+     *   
+     *    acc0 =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     *    acc0 =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     */
+    sample = blockSize >> 1u;
+
+    /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.   
+     ** a second loop below computes the remaining 1 sample. */
+    while(sample > 0u)
+    {
+
+      /* Read the input */
+      in = *__SIMD32(pIn)++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUAD(b0, in);
+      /* acc0 =  b1 * x[n-1] + acc0 +=  b2 * x[n-2] + out */
+      acc0 = __SMLAD(b1, state_in, out);
+      /* acc0 +=  a1 * y[n-1] + acc0 +=  a2 * y[n-2] */
+      acc0 = __SMLAD(a1, state_out, acc0);
+
+      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+      out = __SSAT((acc0 >> shift), 16);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc0   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+      state_out = __PKHBT(state_out >> 16, (out), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUADX(b0, in);
+      /* acc0 =  b1 * x[n-1] + acc0 +=  b2 * x[n-2] + out */
+      acc0 = __SMLAD(b1, state_in, out);
+      /* acc0 +=  a1 * y[n-1] + acc0 +=  a2 * y[n-2] */
+      acc0 = __SMLAD(a1, state_out, acc0);
+
+      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+      out = __SSAT((acc0 >> shift), 16);
+
+
+      /* Store the output in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
+
+#else
+
+      *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc0   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in >> 16, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+
+      /* Decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 2, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+
+    if((blockSize & 0x1u) != 0u)
+    {
+      /* Read the input */
+      in = *pIn++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      out = __SMUAD(b0, in);
+
+#else
+
+      out = __SMUADX(b0, in);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* acc0 =  b1 * x[n-1] + acc0 +=  b2 * x[n-2] + out */
+      acc0 = __SMLAD(b1, state_in, out);
+      /* acc0 +=  a1 * y[n-1] + acc0 +=  a2 * y[n-2] */
+      acc0 = __SMLAD(a1, state_out, acc0);
+
+      /* The result is converted from 3.29 to 1.31 and then saturation is applied */
+      out = __SSAT((acc0 >> shift), 16);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q15_t) out;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc0   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer.  */
+    /*  Subsequent (numStages - 1) occur in-place in the output buffer  */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the state array */
+    *__SIMD32(pState)++ = state_in;
+    *__SIMD32(pState)++ = state_out;
+
+
+    /* Decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+}
+
+
+/**   
+ * @} end of BiquadCascadeDF1 group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
new file mode 100644
index 0000000000..5a86ee1bc5
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
@@ -0,0 +1,271 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_fast_q31.c   
+*   
+* Description:	Processing function for the   
+*				Q31 Fast Biquad cascade DirectFormI(DF1) filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.9  2010/08/27    
+*    Initial version   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @details   
+ *   
+ * @param[in]  *S        points to an instance of the Q31 Biquad cascade structure.   
+ * @param[in]  *pSrc     points to the block of input data.   
+ * @param[out] *pDst     points to the block of output data.   
+ * @param[in]  blockSize number of samples to process per call.   
+ * @return 	   none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.   
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.   
+ * These intermediate results are added to a 2.30 accumulator.   
+ * Finally, the accumulator is saturated and converted to a 1.31 result.   
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signal must be scaled down by two bits and lie in the range [-0.25 +0.25). Use the intialization function   
+ * arm_biquad_cascade_df1_init_q31() to initialize filter structure.   
+ *   
+ * \par   
+ * Refer to the function arm_biquad_cascade_df1_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.  Both the slow and the fast versions use the same instance structure.   
+ * Use the function arm_biquad_cascade_df1_init_q31() to initialize the filter structure.   
+ */
+
+void arm_biquad_cascade_df1_fast_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
+  q31_t *pOut = pDst;                            /*  output pointer initialization */
+  q31_t *pState = S->pState;                     /*  pState pointer initialization */
+  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
+  q31_t acc;                                     /*  accumulator                   */
+  q31_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q31_t Xn;                                      /*  temporary input               */
+  int32_t shift = (int32_t) S->postShift + 1;    /*  Shift to be applied to the output */
+  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
+
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /*      The variables acc ... acc3 hold output values that are being computed:   
+     *   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     */
+
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) (((q63_t) b0 * Xn) >> 32);
+      /* acc +=  b1 * x[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
+      /* acc +=  b[2] * x[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+      /* acc +=  a1 * y[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+      /* acc +=  a2 * y[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+
+      /* The result is converted to 1.31 , Yn2 variable is reused */
+      Yn2 = acc << shift;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Read the second input */
+      Xn2 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) (((q63_t) b0 * (Xn2)) >> 32);
+      /* acc +=  b1 * x[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn))) >> 32);
+      /* acc +=  b[2] * x[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn1))) >> 32);
+      /* acc +=  a1 * y[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
+      /* acc +=  a2 * y[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Read the third input  */
+      Xn1 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) (((q63_t) b0 * (Xn1)) >> 32);
+      /* acc +=  b1 * x[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn2))) >> 32);
+      /* acc +=  b[2] * x[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn))) >> 32);
+      /* acc +=  a1 * y[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+      /* acc +=  a2 * y[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+
+      /* The result is converted to 1.31, Yn2 variable is reused  */
+      Yn2 = acc << shift;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Read the forth input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
+      /* acc +=  b1 * x[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
+      /* acc +=  b[2] * x[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+      /* acc +=  a1 * y[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn2))) >> 32);
+      /* acc +=  a2 * y[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn1))) >> 32);
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      Yn1 = acc << shift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    sample = (blockSize & 0x3u);
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) (((q63_t) b0 * (Xn)) >> 32);
+      /* acc +=  b1 * x[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b1 * (Xn1))) >> 32);
+      /* acc +=  b[2] * x[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) b2 * (Xn2))) >> 32);
+      /* acc +=  a1 * y[n-1] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a1 * (Yn1))) >> 32);
+      /* acc +=  a2 * y[n-2] */
+      acc = (q31_t) ((((q63_t) acc << 32) + ((q63_t) a2 * (Yn2))) >> 32);
+      /* The result is converted to 1.31  */
+      acc = acc << shift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+}
+
+/**   
+  * @} end of BiquadCascadeDF1 group   
+  */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
new file mode 100644
index 0000000000..4ea93db8b5
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
@@ -0,0 +1,104 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_biquad_cascade_df1_init_f32.c   
+*   
+* Description:  floating-point Biquad cascade DirectFormI(DF1) filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @details   
+ * @brief  Initialization function for the floating-point Biquad cascade filter.   
+ * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.   
+ * @param[in]     numStages    number of 2nd order stages in the filter.   
+ * @param[in]     *pCoeffs     points to the filter coefficients array.   
+ * @param[in]     *pState      points to the state array.   
+ * @return        none   
+ *   
+ *   
+ * Coefficient and State Ordering:   
+ *   
+ * \par   
+ * The coefficients are stored in the array pCoeffs in the following order:   
+ * 
       
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}   
+ * 
       
+ *   
+ * \par   
+ * where b1x and a1x are the coefficients for the first stage,   
+ * b2x and a2x are the coefficients for the second stage,   
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.   
+ *   
+ * \par   
+ * The pState is a pointer to state array.   
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].   
+ * The state variables are arranged in the pState array as:   
+ * 
       
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ * 
       
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.   
+ * The state array has a total length of 4*numStages values.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ *   
+ */
+
+void arm_biquad_cascade_df1_init_f32(
+  arm_biquad_casd_df1_inst_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**   
+ * @} end of BiquadCascadeDF1 group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
new file mode 100644
index 0000000000..19ceb32a8a
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
@@ -0,0 +1,106 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_biquad_cascade_df1_init_q15.c   
+*   
+* Description:  Q15 Biquad cascade DirectFormI(DF1) filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @details   
+ *   
+ * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.   
+ * @param[in]     numStages    number of 2nd order stages in the filter.   
+ * @param[in]     *pCoeffs     points to the filter coefficients.   
+ * @param[in]     *pState      points to the state buffer.   
+ * @param[in]     postShift    Shift to be applied to the accumulator result. Varies according to the coefficients format   
+ * @return        none   
+ *   
+ * Coefficient and State Ordering:   
+ *   
+ * \par   
+ * The coefficients are stored in the array pCoeffs in the following order:   
+ * 
       
+ *     {b10, 0, b11, b12, a11, a12, b20, 0, b21, b22, a21, a22, ...}   
+ * 
       
+ * where b1x and a1x are the coefficients for the first stage,   
+ * b2x and a2x are the coefficients for the second stage,   
+ * and so on.  The pCoeffs array contains a total of 6*numStages values.   
+ * The zero coefficient between b1 and b2 facilities  use of 16-bit SIMD instructions on the Cortex-M4.   
+ *   
+ * \par   
+ * The state variables are stored in the array pState.   
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].   
+ * The state variables are arranged in the pState array as:   
+ * 
       
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ * 
       
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.   
+ * The state array has a total length of 4*numStages values.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ */
+
+void arm_biquad_cascade_df1_init_q15(
+  arm_biquad_casd_df1_inst_q15 * S,
+  uint8_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int8_t postShift)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign postShift to be applied to the output */
+  S->postShift = postShift;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**   
+ * @} end of BiquadCascadeDF1 group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
new file mode 100644
index 0000000000..a41e4daf74
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
@@ -0,0 +1,106 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_init_q31.c   
+*   
+* Description:	Q31 Biquad cascade DirectFormI(DF1) filter initialization function.   
+*   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @details   
+ *   
+ * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.   
+ * @param[in]     numStages    number of 2nd order stages in the filter.   
+ * @param[in]     *pCoeffs     points to the filter coefficients buffer.   
+ * @param[in]     *pState      points to the state buffer.   
+ * @param[in]     postShift    Shift to be applied after the accumulator.  Varies according to the coefficients format   
+ * @return        none   
+ *   
+ * Coefficient and State Ordering:   
+ *   
+ * \par   
+ * The coefficients are stored in the array pCoeffs in the following order:   
+ * 
       
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}   
+ * 
       
+ * where b1x and a1x are the coefficients for the first stage,   
+ * b2x and a2x are the coefficients for the second stage,   
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.   
+ *   
+ * \par   
+ * The pState points to state variables array.   
+ * Each Biquad stage has 4 state variables x[n-1], x[n-2], y[n-1], and y[n-2].   
+ * The state variables are arranged in the pState array as:   
+ * 
       
+ *     {x[n-1], x[n-2], y[n-1], y[n-2]}   
+ * 
       
+ * The 4 state variables for stage 1 are first, then the 4 state variables for stage 2, and so on.   
+ * The state array has a total length of 4*numStages values.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ */
+
+void arm_biquad_cascade_df1_init_q31(
+  arm_biquad_casd_df1_inst_q31 * S,
+  uint8_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int8_t postShift)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign postShift to be applied to the output */
+  S->postShift = postShift;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 4 * numStages */
+  memset(pState, 0, (4u * (uint32_t) numStages) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**   
+ * @} end of BiquadCascadeDF1 group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
new file mode 100644
index 0000000000..a9083f8f1b
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
@@ -0,0 +1,380 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_q15.c   
+*   
+* Description:	Processing function for the   
+*				Q15 Biquad cascade DirectFormI(DF1) filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 Biquad cascade filter.   
+ * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.   
+ * @param[in]  *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the location where the output result is written.   
+ * @param[in]  blockSize number of samples to process per call.   
+ * @return none.   
+ *   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * The accumulator is then shifted by postShift bits to truncate the result to 1.15 format by discarding the low 16 bits.   
+ * Finally, the result is saturated to 1.15 format.   
+ *   
+ * \par   
+ * Refer to the function arm_biquad_cascade_df1_fast_q15() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_biquad_cascade_df1_q15(
+  const arm_biquad_casd_df1_inst_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn = pSrc;                             /*  Source pointer                               */
+  q15_t *pOut = pDst;                            /*  Destination pointer                          */
+  q31_t in;                                      /*  Temporary variable to hold input value       */
+  q31_t out;                                     /*  Temporary variable to hold output value      */
+  q31_t b0;                                      /*  Temporary variable to hold bo value          */
+  q31_t b1, a1;                                  /*  Filter coefficients                          */
+  q31_t state_in, state_out;                     /*  Filter state variables                       */
+  q63_t acc;                                     /*  Accumulator                                  */
+  int32_t shift = (15 - (int32_t) S->postShift); /*  Post shift                                   */
+  q15_t *pState = S->pState;                     /*  State pointer                                */
+  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
+  q31_t *pState_q31;                             /*  32-bit state pointer for SIMD implementation */
+  uint32_t sample, stage = (uint32_t) S->numStages;     /*  Stage loop counter                           */
+
+  do
+  {
+    /* Initialize state pointer of type q31 */
+    pState_q31 = (q31_t *) (pState);
+
+    /* Read the b0 and 0 coefficients using SIMD  */
+    b0 = *__SIMD32(pCoeffs)++;
+
+    /* Read the b1 and b2 coefficients using SIMD */
+    b1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the a1 and a2 coefficients using SIMD */
+    a1 = *__SIMD32(pCoeffs)++;
+
+    /* Read the input state values from the state buffer:  x[n-1], x[n-2] */
+    state_in = (q31_t) (*pState_q31++);
+
+    /* Read the output state values from the state buffer:  y[n-1], y[n-2] */
+    state_out = (q31_t) (*pState_q31);
+
+    /* Apply loop unrolling and compute 2 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:   
+     *   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     */
+    sample = blockSize >> 1u;
+
+    /* First part of the processing with loop unrolling.  Compute 2 outputs at a time.   
+     ** a second loop below computes the remaining 1 sample. */
+    while(sample > 0u)
+    {
+
+      /* Read the input */
+      in = *__SIMD32(pIn)++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUAD(b0, in);
+
+      /* acc +=  b1 * x[n-1] +  b2 * x[n-2] + out */
+      acc = __SMLALD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] +  a2 * y[n-2] */
+      acc = __SMLALD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+      out = __SSAT((acc >> shift), 16);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, (in >> 16), 16);
+      state_out = __PKHBT(state_out >> 16, (out), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* out =  b0 * x[n] + 0 * 0 */
+      out = __SMUADX(b0, in);
+      /* acc +=  b1 * x[n-1] +  b2 * x[n-2] + out */
+      acc = __SMLALD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + a2 * y[n-2] */
+      acc = __SMLALD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+      out = __SSAT((acc >> shift), 16);
+
+      /* Store the output in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ = __PKHBT(state_out, out, 16);
+
+#else
+
+      *__SIMD32(pOut)++ = __PKHBT(out, state_out >> 16, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in >> 16, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+
+      /* Decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 2, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+
+    if((blockSize & 0x1u) != 0u)
+    {
+      /* Read the input */
+      in = *pIn++;
+
+      /* out =  b0 * x[n] + 0 * 0 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      out = __SMUAD(b0, in);
+
+#else
+
+      out = __SMUADX(b0, in);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* acc =  b1 * x[n-1] + b2 * x[n-2] + out */
+      acc = __SMLALD(b1, state_in, out);
+      /* acc +=  a1 * y[n-1] + a2 * y[n-2] */
+      acc = __SMLALD(a1, state_out, acc);
+
+      /* The result is converted from 3.29 to 1.31 if postShift = 1, and then saturation is applied */
+      out = __SSAT((acc >> shift), 16);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q15_t) out;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc   */
+      /* x[n-N], x[n-N-1] are packed together to make state_in of type q31 */
+      /* y[n-N], y[n-N-1] are packed together to make state_out of type q31 */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      state_in = __PKHBT(in, state_in, 16);
+      state_out = __PKHBT(out, state_out, 16);
+
+#else
+
+      state_in = __PKHBT(state_in >> 16, in, 16);
+      state_out = __PKHBT(state_out >> 16, out, 16);
+
+#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    }
+
+    /*  The first stage goes from the input wire to the output wire.  */
+    /*  Subsequent numStages occur in-place in the output wire  */
+    pIn = pDst;
+
+    /* Reset the output pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the state array */
+    *__SIMD32(pState)++ = state_in;
+    *__SIMD32(pState)++ = state_out;
+
+
+    /* Decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *pIn = pSrc;                             /*  Source pointer                               */
+  q15_t *pOut = pDst;                            /*  Destination pointer                          */
+  q15_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q15_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q15_t Xn;                                      /*  temporary input               */
+  q63_t acc;                                     /*  Accumulator                                  */
+  int32_t shift = (15 - (int32_t) S->postShift); /*  Post shift                                   */
+  q15_t *pState = S->pState;                     /*  State pointer                                */
+  q15_t *pCoeffs = S->pCoeffs;                   /*  Coefficient pointer                          */
+  uint32_t sample, stage = (uint32_t) S->numStages;     /*  Stage loop counter                           */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /*      The variables acc holds the output value that is computed:        
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]        
+     */
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q31_t) b0 *Xn;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q31_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q31_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q31_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q31_t) a2 *Yn2;
+
+      /* The result is converted to 1.31  */
+      acc = __SSAT((acc >> shift), 16);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = (q15_t) acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q15_t) acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#endif /*     #ifndef ARM_MATH_CM0 */
+
+}
+
+
+/**   
+ * @} end of BiquadCascadeDF1 group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
new file mode 100644
index 0000000000..66d65f8039
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
@@ -0,0 +1,362 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df1_q31.c   
+*   
+* Description:	Processing function for the   
+*				Q31 Biquad cascade filter   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF1   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 Biquad cascade filter.   
+ * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.   
+ * @param[in]  *pSrc      points to the block of input data.   
+ * @param[out] *pDst      points to the block of output data.   
+ * @param[in]  blockSize  number of samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around rather than clip.   
+ * In order to avoid overflows completely the input signal must be scaled down by 2 bits and lie in the range [-0.25 +0.25).   
+ * After all 5 multiply-accumulates are performed, the 2.62 accumulator is shifted by postShift bits and the result truncated to   
+ * 1.31 format by discarding the low 32 bits.   
+ *   
+ * \par   
+ * Refer to the function arm_biquad_cascade_df1_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_biquad_cascade_df1_q31(
+  const arm_biquad_casd_df1_inst_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /*  input pointer initialization  */
+  q31_t *pOut = pDst;                            /*  output pointer initialization */
+  q31_t *pState = S->pState;                     /*  pState pointer initialization */
+  q31_t *pCoeffs = S->pCoeffs;                   /*  coeff pointer initialization  */
+  q63_t acc;                                     /*  accumulator                   */
+  q31_t Xn1, Xn2, Yn1, Yn2;                      /*  Filter state variables        */
+  q31_t b0, b1, b2, a1, a2;                      /*  Filter coefficients           */
+  q31_t Xn;                                      /*  temporary input               */
+  uint32_t shift = 32u - ((uint32_t) S->postShift + 1u);        /*  Shift to be applied to the output */
+  uint32_t sample, stage = S->numStages;         /*  loop counters                     */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    /*      The variable acc hold output values that are being computed:   
+     *   
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]   
+     */
+
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31 , Yn2 variable is reused */
+      Yn2 = (q31_t) (acc >> shift);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Read the second input */
+      Xn2 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn2;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn1;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn2;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn1;
+
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      Yn1 = (q31_t) (acc >> shift);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* Read the third input  */
+      Xn1 = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn1;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn2;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31, Yn2 variable is reused  */
+      Yn2 = (q31_t) (acc >> shift);
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn2;
+
+      /* Read the forth input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn2;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn1;
+
+      /* The result is converted to 1.31, Yn1 variable is reused  */
+      Yn1 = (q31_t) (acc >> shift);
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = Yn1;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    sample = (blockSize & 0x3u);
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31  */
+      acc = acc >> shift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = (q31_t) acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q31_t) acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /* Reading the state values */
+    Xn1 = pState[0];
+    Xn2 = pState[1];
+    Yn1 = pState[2];
+    Yn2 = pState[3];
+
+    /*      The variables acc holds the output value that is computed:        
+     *    acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2]        
+     */
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* acc =  b0 * x[n] + b1 * x[n-1] + b2 * x[n-2] + a1 * y[n-1] + a2 * y[n-2] */
+      /* acc =  b0 * x[n] */
+      acc = (q63_t) b0 *Xn;
+
+      /* acc +=  b1 * x[n-1] */
+      acc += (q63_t) b1 *Xn1;
+      /* acc +=  b[2] * x[n-2] */
+      acc += (q63_t) b2 *Xn2;
+      /* acc +=  a1 * y[n-1] */
+      acc += (q63_t) a1 *Yn1;
+      /* acc +=  a2 * y[n-2] */
+      acc += (q63_t) a2 *Yn2;
+
+      /* The result is converted to 1.31  */
+      acc = acc >> shift;
+
+      /* Every time after the output is computed state should be updated. */
+      /* The states should be updated as:  */
+      /* Xn2 = Xn1    */
+      /* Xn1 = Xn     */
+      /* Yn2 = Yn1    */
+      /* Yn1 = acc    */
+      Xn2 = Xn1;
+      Xn1 = Xn;
+      Yn2 = Yn1;
+      Yn1 = (q31_t) acc;
+
+      /* Store the output in the destination buffer. */
+      *pOut++ = (q31_t) acc;
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /*  The first stage goes from the input buffer to the output buffer. */
+    /*  Subsequent stages occur in-place in the output buffer */
+    pIn = pDst;
+
+    /* Reset to destination pointer */
+    pOut = pDst;
+
+    /*  Store the updated state variables back into the pState array */
+    *pState++ = Xn1;
+    *pState++ = Xn2;
+    *pState++ = Yn1;
+    *pState++ = Yn2;
+
+  } while(--stage);
+
+#endif /*  #ifndef ARM_MATH_CM0 */
+}
+
+/**   
+  * @} end of BiquadCascadeDF1 group   
+  */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
new file mode 100644
index 0000000000..9c3e0a72fc
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
@@ -0,0 +1,359 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_biquad_cascade_df2T_f32.c   
+*   
+* Description:  Processing function for the floating-point transposed   
+*               direct form II Biquad cascade filter.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup BiquadCascadeDF2T Biquad Cascade IIR Filters Using a Direct Form II Transposed Structure   
+ *   
+ * This set of functions implements arbitrary order recursive (IIR) filters using a transposed direct form II structure.   
+ * The filters are implemented as a cascade of second order Biquad sections.   
+ * These functions provide a slight memory savings as compared to the direct form I Biquad filter functions.  
+ * Only floating-point data is supported.   
+ *   
+ * This function operate on blocks of input and output data and each call to the function   
+ * processes blockSize samples through the filter.   
+ * pSrc points to the array of input data and   
+ * pDst points to the array of output data.   
+ * Both arrays contain blockSize values.   
+ *   
+ * \par Algorithm   
+ * Each Biquad stage implements a second order filter using the difference equation:   
+ * 
       
+ *    y[n] = b0 * x[n] + d1   
+ *    d1 = b1 * x[n] + a1 * y[n] + d2   
+ *    d2 = b2 * x[n] + a2 * y[n]   
+ * 
       
+ * where d1 and d2 represent the two state values.   
+ *   
+ * \par   
+ * A Biquad filter using a transposed Direct Form II structure is shown below.   
+ * \image html BiquadDF2Transposed.gif "Single transposed Direct Form II Biquad"   
+ * Coefficients b0, b1, and b2  multiply the input signal x[n] and are referred to as the feedforward coefficients.   
+ * Coefficients a1 and a2 multiply the output signal y[n] and are referred to as the feedback coefficients.   
+ * Pay careful attention to the sign of the feedback coefficients.   
+ * Some design tools flip the sign of the feedback coefficients:   
+ * 
       
+ *    y[n] = b0 * x[n] + d1;   
+ *    d1 = b1 * x[n] - a1 * y[n] + d2;   
+ *    d2 = b2 * x[n] - a2 * y[n];   
+ * 
       
+ * In this case the feedback coefficients a1 and a2 must be negated when used with the CMSIS DSP Library.   
+ *   
+ * \par   
+ * Higher order filters are realized as a cascade of second order sections.   
+ * numStages refers to the number of second order stages used.   
+ * For example, an 8th order filter would be realized with numStages=4 second order stages.   
+ * A 9th order filter would be realized with numStages=5 second order stages with the   
+ * coefficients for one of the stages configured as a first order filter (b2=0 and a2=0).   
+ *   
+ * \par   
+ * pState points to the state variable array.   
+ * Each Biquad stage has 2 state variables d1 and d2.   
+ * The state variables are arranged in the pState array as:   
+ * 
       
+ *     {d11, d12, d21, d22, ...}   
+ * 
       
+ * where d1x refers to the state variables for the first Biquad and   
+ * d2x refers to the state variables for the second Biquad.   
+ * The state array has a total length of 2*numStages values.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ *   
+ * \par   
+ * The CMSIS library contains Biquad filters in both Direct Form I and transposed Direct Form II.   
+ * The advantage of the Direct Form I structure is that it is numerically more robust for fixed-point data types.   
+ * That is why the Direct Form I structure supports Q15 and Q31 data types.   
+ * The transposed Direct Form II structure, on the other hand, requires a wide dynamic range for the state variables d1 and d2.   
+ * Because of this, the CMSIS library only has a floating-point version of the Direct Form II Biquad.   
+ * The advantage of the Direct Form II Biquad is that it requires half the number of state variables, 2 rather than 4, per Biquad stage.   
+ *   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.   
+ *   
+ * \par Init Functions   
+ * There is also an associated initialization function.  
+ * The initialization function performs following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros before static initialization.   
+ * For example, to statically initialize the instance structure use   
+ * 
       
+ *     arm_biquad_cascade_df2T_instance_f32 S1 = {numStages, pState, pCoeffs};   
+ * 
       
+ * where numStages is the number of Biquad stages in the filter; pState is the address of the state buffer.   
+ * pCoeffs is the address of the coefficient buffer;    
+ *   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF2T   
+ * @{   
+ */
+
+/**  
+ * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.  
+ * @param[in]  *S        points to an instance of the filter data structure.  
+ * @param[in]  *pSrc     points to the block of input data.  
+ * @param[out] *pDst     points to the block of output data  
+ * @param[in]  blockSize number of samples to process.  
+ * @return none.  
+ */
+
+void arm_biquad_cascade_df2T_f32(
+  const arm_biquad_cascade_df2T_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+
+  float32_t *pIn = pSrc;                         /*  source pointer            */
+  float32_t *pOut = pDst;                        /*  destination pointer       */
+  float32_t *pState = S->pState;                 /*  State pointer            */
+  float32_t *pCoeffs = S->pCoeffs;               /*  coefficient pointer       */
+  float32_t acc0;                                /*  Simulates the accumulator */
+  float32_t b0, b1, b2, a1, a2;                  /*  Filter coefficients       */
+  float32_t Xn;                                  /*  temporary input           */
+  float32_t d1, d2;                              /*  state variables          */
+  uint32_t sample, stage = S->numStages;         /*  loop counters             */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /*Reading the state values */
+    d1 = pState[0];
+    d2 = pState[1];
+
+    /* Apply loop unrolling and compute 4 output values simultaneously. */
+    sample = blockSize >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(sample > 0u)
+    {
+      /* Read the first input */
+      Xn = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      /* Every time after the output is computed state should be updated. */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
+
+      /* d2 = b2 * x[n] + a2 * y[n] */
+      d2 = (b2 * Xn) + (a2 * acc0);
+
+      /* Read the second input */
+      Xn = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      /* Every time after the output is computed state should be updated. */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
+
+      /* d2 = b2 * x[n] + a2 * y[n] */
+      d2 = (b2 * Xn) + (a2 * acc0);
+
+      /* Read the third input */
+      Xn = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      /* Every time after the output is computed state should be updated. */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
+
+      /* d2 = b2 * x[n] + a2 * y[n] */
+      d2 = (b2 * Xn) + (a2 * acc0);
+
+      /* Read the fourth input */
+      Xn = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      /* Every time after the output is computed state should be updated. */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      d1 = (b1 * Xn) + (a1 * acc0) + d2;
+
+      /* d2 = b2 * x[n] + a2 * y[n] */
+      d2 = (b2 * Xn) + (a2 * acc0);
+
+      /* decrement the loop counter */
+      sample--;
+
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    sample = blockSize & 0x3u;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      /* Every time after the output is computed state should be updated. */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
+
+      /* d2 = b2 * x[n] + a2 * y[n] */
+      d2 = (b2 * Xn) + (a2 * acc0);
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* Store the updated state variables back into the state array */
+    *pState++ = d1;
+    *pState++ = d2;
+
+    /* The current stage input is given as the output to the next stage */
+    pIn = pDst;
+
+    /*Reset the output working pointer */
+    pOut = pDst;
+
+    /* decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  do
+  {
+    /* Reading the coefficients */
+    b0 = *pCoeffs++;
+    b1 = *pCoeffs++;
+    b2 = *pCoeffs++;
+    a1 = *pCoeffs++;
+    a2 = *pCoeffs++;
+
+    /*Reading the state values */
+    d1 = pState[0];
+    d2 = pState[1];
+
+
+    sample = blockSize;
+
+    while(sample > 0u)
+    {
+      /* Read the input */
+      Xn = *pIn++;
+
+      /* y[n] = b0 * x[n] + d1 */
+      acc0 = (b0 * Xn) + d1;
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+
+      /* Every time after the output is computed state should be updated. */
+      /* d1 = b1 * x[n] + a1 * y[n] + d2 */
+      d1 = ((b1 * Xn) + (a1 * acc0)) + d2;
+
+      /* d2 = b2 * x[n] + a2 * y[n] */
+      d2 = (b2 * Xn) + (a2 * acc0);
+
+      /* decrement the loop counter */
+      sample--;
+    }
+
+    /* Store the updated state variables back into the state array */
+    *pState++ = d1;
+    *pState++ = d2;
+
+    /* The current stage input is given as the output to the next stage */
+    pIn = pDst;
+
+    /*Reset the output working pointer */
+    pOut = pDst;
+
+    /* decrement the loop counter */
+    stage--;
+
+  } while(stage > 0u);
+
+#endif /*  #ifndef ARM_MATH_CM0         */
+
+}
+
+
+  /**   
+   * @} end of BiquadCascadeDF2T group   
+   */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
new file mode 100644
index 0000000000..eaf35d85b3
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
@@ -0,0 +1,94 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_biquad_cascade_df2T_init_f32.c   
+*   
+* Description:  Initialization function for the floating-point transposed  
+*               direct form II Biquad cascade filter.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup BiquadCascadeDF2T   
+ * @{   
+ */
+
+/**  
+ * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.  
+ * @param[in,out] *S           points to an instance of the filter data structure.  
+ * @param[in]     numStages    number of 2nd order stages in the filter.  
+ * @param[in]     *pCoeffs     points to the filter coefficients.  
+ * @param[in]     *pState      points to the state buffer.  
+ * @return        none  
+ *   
+ * Coefficient and State Ordering:   
+ * \par   
+ * The coefficients are stored in the array pCoeffs in the following order:   
+ * 
       
+ *     {b10, b11, b12, a11, a12, b20, b21, b22, a21, a22, ...}   
+ * 
       
+ *   
+ * \par   
+ * where b1x and a1x are the coefficients for the first stage,   
+ * b2x and a2x are the coefficients for the second stage,   
+ * and so on.  The pCoeffs array contains a total of 5*numStages values.   
+ *   
+ * \par   
+ * The pState is a pointer to state array.   
+ * Each Biquad stage has 2 state variables d1, and d2.   
+ * The 2 state variables for stage 1 are first, then the 2 state variables for stage 2, and so on.   
+ * The state array has a total length of 2*numStages values.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ */
+
+void arm_biquad_cascade_df2T_init_f32(
+  arm_biquad_cascade_df2T_instance_f32 * S,
+  uint8_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState)
+{
+  /* Assign filter stages */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always 2 * numStages */
+  memset(pState, 0, (2u * (uint32_t) numStages) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+}
+
+/**   
+ * @} end of BiquadCascadeDF2T group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c
new file mode 100644
index 0000000000..1c8a726e2d
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c
@@ -0,0 +1,623 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_f32.c   
+*   
+* Description:	Convolution of floating-point sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup Conv Convolution   
+ *   
+ * Convolution is a mathematical operation that operates on two finite length vectors to generate a finite length output vector.   
+ * Convolution is similar to correlation and is frequently used in filtering and data analysis.   
+ * The CMSIS DSP library contains functions for convolving Q7, Q15, Q31, and floating-point data types.   
+ * The library also provides fast versions of the Q15 and Q31 functions on Cortex-M4 and Cortex-M3.   
+ *   
+ * \par Algorithm   
+ * Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively.   
+ * Then the convolution   
+ *   
+ * 
       
+ *                   c[n] = a[n] * b[n]   
+ * 
       
+ *   
+ * \par   
+ * is defined as   
+ * \image html ConvolutionEquation.gif   
+ * \par   
+ * Note that c[n] is of length srcALen + srcBLen - 1 and is defined over the interval n=0, 1, 2, ..., srcALen + srcBLen - 2.   
+ * pSrcA points to the first input vector of length srcALen and   
+ * pSrcB points to the second input vector of length srcBLen.   
+ * The output result is written to pDst and the calling function must allocate srcALen+srcBLen-1 words for the result.   
+ *   
+ * \par   
+ * Conceptually, when two signals a[n] and b[n] are convolved,   
+ * the signal b[n] slides over a[n].   
+ * For each offset \c n, the overlapping portions of a[n] and b[n] are multiplied and summed together.   
+ *   
+ * \par   
+ * Note that convolution is a commutative operation:   
+ *   
+ * 
       
+ *                   a[n] * b[n] = b[n] * a[n].   
+ * 
       
+ *   
+ * \par   
+ * This means that switching the A and B arguments to the convolution functions has no effect.   
+ *   
+ * Fixed-Point Behavior   
+ *   
+ * \par   
+ * Convolution requires summing up a large number of intermediate products.   
+ * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.   
+ * Refer to the function specific documentation below for further details of the particular algorithm used.   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of floating-point sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ */
+
+void arm_conv_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t *pIn1;                               /* inputA pointer */
+  float32_t *pIn2;                               /* inputB pointer */
+  float32_t *pOut = pDst;                        /* output pointer */
+  float32_t *px;                                 /* Intermediate inputA pointer */
+  float32_t *py;                                 /* Intermediate inputB pointer */
+  float32_t *pSrc1, *pSrc2;                      /* Intermediate pointers */
+  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulator */
+  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counters */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 1] */
+      sum += *px++ * *py--;
+
+      /* x[1] * y[srcBLen - 2] */
+      sum += *px++ * *py--;
+
+      /* x[2] * y[srcBLen - 3] */
+      sum += *px++ * *py--;
+
+      /* x[3] * y[srcBLen - 4] */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0.0f;
+      acc1 = 0.0f;
+      acc2 = 0.0f;
+      acc3 = 0.0f;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[srcBLen - 1] */
+        acc0 += x0 * c0;
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] */
+        acc1 += x1 * c0;
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] */
+        acc2 += x2 * c0;
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] */
+        acc3 += x3 * c0;
+
+        /* Read y[srcBLen - 2] sample */
+        c0 = *(py--);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[srcBLen - 2] */
+        acc0 += x1 * c0;
+        /* acc1 +=  x[2] * y[srcBLen - 2] */
+        acc1 += x2 * c0;
+        /* acc2 +=  x[3] * y[srcBLen - 2] */
+        acc2 += x3 * c0;
+        /* acc3 +=  x[4] * y[srcBLen - 2] */
+        acc3 += x0 * c0;
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[srcBLen - 3] */
+        acc0 += x2 * c0;
+        /* acc1 +=  x[3] * y[srcBLen - 2] */
+        acc1 += x3 * c0;
+        /* acc2 +=  x[4] * y[srcBLen - 2] */
+        acc2 += x0 * c0;
+        /* acc3 +=  x[5] * y[srcBLen - 2] */
+        acc3 += x1 * c0;
+
+        /* Read y[srcBLen - 4] sample */
+        c0 = *(py--);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[srcBLen - 4] */
+        acc0 += x3 * c0;
+        /* acc1 +=  x[4] * y[srcBLen - 4] */
+        acc1 += x0 * c0;
+        /* acc2 +=  x[5] * y[srcBLen - 4] */
+        acc2 += x1 * c0;
+        /* acc3 +=  x[6] * y[srcBLen - 4] */
+        acc3 += x2 * c0;
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 += x0 * c0;
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 += x1 * c0;
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 += x2 * c0;
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 += x3 * c0;
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = acc0;
+      *pOut++ = acc1;
+      *pOut++ = acc2;
+      *pOut++ = acc3;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += *px++ * *py--;
+        sum += *px++ * *py--;
+        sum += *px++ * *py--;
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      sum += *px++ * *py--;
+
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum += *px++ * *py--;
+
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      sum += *px++ * *py--;
+
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+      sum += *px++ * *py--;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i < ((srcALen + srcBLen) - 1u); i++)
+  {
+    /* Initialize sum with zero to carry out MAC operations */
+    sum = 0.0f;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += pIn1[j] * pIn2[i - j];
+      }
+    }
+    /* Store the output in the destination buffer */
+    pDst[i] = sum;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0        */
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c
new file mode 100644
index 0000000000..e53dbac13d
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c
@@ -0,0 +1,677 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_fast_q15.c   
+*   
+* Description:	Fast Q15 Convolution.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * This fast version uses a 32-bit accumulator with 2.30 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results   
+ * but provides only a single guard bit. There is no saturation on intermediate additions.   
+ * Thus, if the accumulator overflows it wraps around and distorts the result.   
+ * The input signals should be scaled down to avoid intermediate overflows.   
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,   
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.   
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.   
+ *   
+ * \par   
+ * See arm_conv_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.   
+ */
+
+void arm_conv_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
+  q31_t *pb;                                     /* 32 bit pointer for inputB buffer */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations less than 4 */
+  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  while((count < 4u) && (blockSize1 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Loop over number of MAC operations between   
+     * inputA samples and inputB samples */
+    k = count;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* The second part of the stage starts here */
+  /* The internal loop, over count, is unrolled by 4 */
+  /* To, read the last two inputB samples using SIMD:   
+   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+  py = py - 1;
+
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD   
+     * So, py is incremented by 1 */
+    py = py + 1u;
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + (count - 1u);
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* Initialize inputB pointer of type q31 */
+  pb = (q31_t *) (py - 1u);
+
+  /* count is the index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+
+  /* --------------------   
+   * Stage2 process   
+   * -------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+
+      /* read x[0], x[1] samples */
+      x0 = *(q31_t *) (px++);
+      /* read x[1], x[2] samples */
+      x1 = *(q31_t *) (px++);
+
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:   
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+        c0 = *(pb--);
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLADX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLADX(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *(q31_t *) (px++);
+
+        /* Read x[3], x[4] */
+        x3 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLADX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLADX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+        c0 = *(pb--);
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLADX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLADX(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = *(q31_t *) (px++);
+
+        /* Read x[5], x[6] */
+        x1 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLADX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLADX(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+      py = (q15_t *) pb;
+      py = py + 1;
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+//          c0 = unallign_rev(p, c0); 
+        c0 = c0 << 16;
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = *(pb);
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = *pb--;
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x0, c0, acc0);
+        acc1 = __SMLADX(x1, c0, acc1);
+        acc2 = __SMLADX(x3, c0, acc2);
+        acc3 = __SMLADX(x2, c0, acc3);
+
+        /* Read y[srcBLen - 7] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = (*pb);
+//              c0 = (c0 & 0x0000FFFF)<<16;     
+        c0 = (c0) << 16;
+
+#else
+
+        c0 = (q15_t) (*pb >> 16);
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ = __PKHBT((acc0 >> 15), (acc1 >> 15), 16);
+      *__SIMD32(pOut)++ = __PKHBT((acc2 >> 15), (acc3 >> 15), 16);
+
+#else
+
+      *__SIMD32(pOut)++ = __PKHBT((acc1 >> 15), (acc0 >> 15), 16);
+      *__SIMD32(pOut)++ = __PKHBT((acc3 >> 15), (acc2 >> 15), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pSrc2;
+      pb = (q31_t *) (py - 1);
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  pIn2 = pSrc2 - 1u;
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations greater than 4 */
+  /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  j = blockSize3 >> 2u;
+
+  while((j > 0u) && (blockSize3 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
+       * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
+       * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD   
+     * So, py is incremented by 1 */
+    py = py + 1u;
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+
+    j--;
+  }
+
+  /* The second part of the stage starts here */
+  /* SIMD is not used for the next MAC operations,   
+   * so pointer py is updated to read only one sample at a time */
+  py = py + 1u;
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+      sum = __SMLAD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (sum >> 15);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c
new file mode 100644
index 0000000000..3bd92170f7
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c
@@ -0,0 +1,567 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_fast_q31.c   
+*   
+* Description:	Q31 Convolution (fast version).   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.   
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.   
+ * These intermediate results are accumulated in a 32-bit register in 2.30 format.   
+ * Finally, the accumulator is saturated and converted to a 1.31 result.   
+ *   
+ * \par   
+ * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signals must be scaled down.   
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,   
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.   
+ *   
+ * \par   
+ * See arm_conv_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.   
+ */
+
+void arm_conv_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+  q31_t *pIn1;                                   /* inputA pointer */
+  q31_t *pIn2;                                   /* inputB pointer */
+  q31_t *pOut = pDst;                            /* output pointer */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* x[1] * y[srcBLen - 2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* x[2] * y[srcBLen - 3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* x[3] * y[srcBLen - 4] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum << 1;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[0] * y[srcBLen - 1] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Read y[srcBLen - 2] sample */
+        c0 = *(py--);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[srcBLen - 2] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc1 +=  x[2] * y[srcBLen - 2] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc2 +=  x[3] * y[srcBLen - 2] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc3 +=  x[4] * y[srcBLen - 2] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[srcBLen - 3] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc1 +=  x[3] * y[srcBLen - 2] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc2 +=  x[4] * y[srcBLen - 2] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc3 +=  x[5] * y[srcBLen - 2] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+        /* Read y[srcBLen - 4] sample */
+        c0 = *(py--);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[srcBLen - 4] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc1 +=  x[4] * y[srcBLen - 4] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc2 +=  x[5] * y[srcBLen - 4] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc3 +=  x[6] * y[srcBLen - 4] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+      *pOut++ = (q31_t) (acc0 << 1);
+      *pOut++ = (q31_t) (acc1 << 1);
+      *pOut++ = (q31_t) (acc2 << 1);
+      *pOut++ = (q31_t) (acc3 << 1);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py--))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = sum << 1;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c
new file mode 100644
index 0000000000..914ee2b6c5
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c
@@ -0,0 +1,641 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_f32.c   
+*   
+* Description:	Partial convolution of floating-point sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup PartialConv Partial Convolution   
+ *   
+ * Partial Convolution is equivalent to Convolution except that a subset of the output samples is generated.   
+ * Each function has two additional arguments.   
+ * firstIndex specifies the starting index of the subset of output samples.   
+ * numPoints is the number of output samples to compute.   
+ * The function computes the output in the range   
+ * [firstIndex, ..., firstIndex+numPoints-1].   
+ * The output array pDst contains numPoints values.   
+ *   
+ * The allowable range of output indices is [0 srcALen+srcBLen-2].   
+ * If the requested subset does not fall in this range then the functions return ARM_MATH_ARGUMENT_ERROR.   
+ * Otherwise the functions return ARM_MATH_SUCCESS.   
+ * \note Refer arm_conv_f32() for details on fixed point behavior.  
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of floating-point sequences.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ */
+
+arm_status arm_conv_partial_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
+  float32_t *pOut = pDst;                        /* output pointer */
+  float32_t *px;                                 /* Intermediate inputA pointer */
+  float32_t *py;                                 /* Intermediate inputB pointer */
+  float32_t *pSrc1, *pSrc2;                      /* Intermediate pointers */
+  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulator */
+  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count = 0u, blkCnt, check;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = (int32_t) check - (int32_t) srcALen;
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = ((int32_t) srcBLen - 1) - (int32_t) firstIndex;
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = ((int32_t) check - blockSize3) -
+      (blockSize1 + (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc1 = pIn2 + firstIndex;
+    py = pSrc1;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* The first stage starts here */
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[0] * y[srcBLen - 1] */
+        sum += *px++ * *py--;
+
+        /* x[1] * y[srcBLen - 2] */
+        sum += *px++ * *py--;
+
+        /* x[2] * y[srcBLen - 3] */
+        sum += *px++ * *py--;
+
+        /* x[3] * y[srcBLen - 4] */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc1;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 1u;
+
+    /* -------------------   
+     * Stage2 process   
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0.0f;
+        acc1 = 0.0f;
+        acc2 = 0.0f;
+        acc3 = 0.0f;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[0] * y[srcBLen - 1] */
+          acc0 += x0 * c0;
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] */
+          acc1 += x1 * c0;
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] */
+          acc2 += x2 * c0;
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] */
+          acc3 += x3 * c0;
+
+          /* Read y[srcBLen - 2] sample */
+          c0 = *(py--);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[1] * y[srcBLen - 2] */
+          acc0 += x1 * c0;
+          /* acc1 +=  x[2] * y[srcBLen - 2] */
+          acc1 += x2 * c0;
+          /* acc2 +=  x[3] * y[srcBLen - 2] */
+          acc2 += x3 * c0;
+          /* acc3 +=  x[4] * y[srcBLen - 2] */
+          acc3 += x0 * c0;
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[2] * y[srcBLen - 3] */
+          acc0 += x2 * c0;
+          /* acc1 +=  x[3] * y[srcBLen - 2] */
+          acc1 += x3 * c0;
+          /* acc2 +=  x[4] * y[srcBLen - 2] */
+          acc2 += x0 * c0;
+          /* acc3 +=  x[5] * y[srcBLen - 2] */
+          acc3 += x1 * c0;
+
+          /* Read y[srcBLen - 4] sample */
+          c0 = *(py--);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[3] * y[srcBLen - 4] */
+          acc0 += x3 * c0;
+          /* acc1 +=  x[4] * y[srcBLen - 4] */
+          acc1 += x0 * c0;
+          /* acc2 +=  x[5] * y[srcBLen - 4] */
+          acc2 += x1 * c0;
+          /* acc3 +=  x[6] * y[srcBLen - 4] */
+          acc3 += x2 * c0;
+
+
+        } while(--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 += x0 * c0;
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 += x1 * c0;
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 += x2 * c0;
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 += x3 * c0;
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = acc0;
+        *pOut++ = acc1;
+        *pOut++ = acc2;
+        *pOut++ = acc3;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + (count * 4u);
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0.0f;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += *px++ * *py--;
+          sum += *px++ * *py--;
+          sum += *px++ * *py--;
+          sum += *px++ * *py--;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += *px++ * *py--;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0.0f;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += *px++ * *py--;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+        sum += *px++ * *py--;
+
+        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+        sum += *px++ * *py--;
+
+        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+        sum += *px++ * *py--;
+
+        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum += *px++ * *py--;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB;                       /* inputB pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0.0f;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0u; j <= i; j++)
+      {
+        /* Check the array limitations for inputs */
+        if((((i - j) < srcBLen) && (j < srcALen)))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += pIn1[j] * pIn2[i - j];
+        }
+      }
+      /* Store the output in the destination buffer */
+      pDst[i] = sum;
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
new file mode 100644
index 0000000000..af219a8ac9
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
@@ -0,0 +1,705 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_fast_q15.c   
+*   
+* Description:	Fast Q15 Partial convolution.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *   
+ * See arm_conv_partial_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.   
+ */
+
+
+arm_status arm_conv_partial_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
+  arm_status status;                             /* status of Partial convolution */
+  q31_t *pb;                                     /* 32 bit pointer for inputB buffer */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations less than 4 */
+    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    while((count < 4u) && (blockSize1 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over number of MAC operations between   
+       * inputA samples and inputB samples */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* The second part of the stage starts here */
+    /* The internal loop, over count, is unrolled by 4 */
+    /* To, read the last two inputB samples using SIMD:   
+     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+    py = py - 1;
+
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD   
+       * So, py is incremented by 1 */
+      py = py + 1u;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2 - 1u;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* Initialize inputB pointer of type q31 */
+    pb = (q31_t *) (py - 1u);
+
+    /* count is the index by which the pointer pIn1 to be incremented */
+    count = 1u;
+
+
+    /* --------------------   
+     * Stage2 process   
+     * -------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+
+        /* read x[0], x[1] samples */
+        x0 = *(q31_t *) (px++);
+        /* read x[1], x[2] samples */
+        x1 = *(q31_t *) (px++);
+
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read the last two inputB samples using SIMD:   
+           * y[srcBLen - 1] and y[srcBLen - 2] */
+          c0 = *(pb--);
+
+          /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+          acc0 = __SMLADX(x0, c0, acc0);
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+          acc1 = __SMLADX(x1, c0, acc1);
+
+          /* Read x[2], x[3] */
+          x2 = *(q31_t *) (px++);
+
+          /* Read x[3], x[4] */
+          x3 = *(q31_t *) (px++);
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+          acc2 = __SMLADX(x2, c0, acc2);
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+          acc3 = __SMLADX(x3, c0, acc3);
+
+          /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+          c0 = *(pb--);
+
+          /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+          acc0 = __SMLADX(x2, c0, acc0);
+
+          /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+          acc1 = __SMLADX(x3, c0, acc1);
+
+          /* Read x[4], x[5] */
+          x0 = *(q31_t *) (px++);
+
+          /* Read x[5], x[6] */
+          x1 = *(q31_t *) (px++);
+
+          /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+          acc2 = __SMLADX(x0, c0, acc2);
+
+          /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+          acc3 = __SMLADX(x1, c0, acc3);
+
+        } while(--k);
+
+        /* For the next MAC operations, SIMD is not used   
+         * So, the 16 bit pointer if inputB, py is updated */
+        py = (q15_t *) pb;
+        py = py + 1;
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        if(k == 1u)
+        {
+          /* Read y[srcBLen - 5] */
+          c0 = *(py);
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+          c0 = c0 << 16;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+          /* Read x[7] */
+          x3 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLAD(x0, c0, acc0);
+          acc1 = __SMLAD(x1, c0, acc1);
+          acc2 = __SMLADX(x1, c0, acc2);
+          acc3 = __SMLADX(x3, c0, acc3);
+        }
+
+        if(k == 2u)
+        {
+          /* Read y[srcBLen - 5], y[srcBLen - 6] */
+          c0 = *(pb);
+
+          /* Read x[7], x[8] */
+          x3 = *(q31_t *) px++;
+
+          /* Read x[9] */
+          x2 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLADX(x0, c0, acc0);
+          acc1 = __SMLADX(x1, c0, acc1);
+          acc2 = __SMLADX(x3, c0, acc2);
+          acc3 = __SMLADX(x2, c0, acc3);
+        }
+
+        if(k == 3u)
+        {
+          /* Read y[srcBLen - 5], y[srcBLen - 6] */
+          c0 = *pb--;
+
+          /* Read x[7], x[8] */
+          x3 = *(q31_t *) px++;
+
+          /* Read x[9] */
+          x2 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLADX(x0, c0, acc0);
+          acc1 = __SMLADX(x1, c0, acc1);
+          acc2 = __SMLADX(x3, c0, acc2);
+          acc3 = __SMLADX(x2, c0, acc3);
+
+          /* Read y[srcBLen - 7] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+          c0 = (*pb);
+          c0 = (c0) << 16;
+
+#else
+
+          c0 = (q15_t) (*pb >> 16);
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+          /* Read x[10] */
+          x3 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLADX(x1, c0, acc0);
+          acc1 = __SMLAD(x2, c0, acc1);
+          acc2 = __SMLADX(x2, c0, acc2);
+          acc3 = __SMLADX(x3, c0, acc3);
+        }
+
+        /* Store the results in the accumulators in the destination buffer. */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *__SIMD32(pOut)++ = __PKHBT(acc0 >> 15, acc1 >> 15, 16);
+        *__SIMD32(pOut)++ = __PKHBT(acc2 >> 15, acc3 >> 15, 16);
+
+#else
+
+        *__SIMD32(pOut)++ = __PKHBT(acc1 >> 15, acc0 >> 15, 16);
+        *__SIMD32(pOut)++ = __PKHBT(acc3 >> 15, acc2 >> 15, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + (count * 4u);
+        py = pSrc2;
+        pb = (q31_t *) (py - 1);
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (sum >> 15);
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (sum >> 15);
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    pIn2 = pSrc2 - 1u;
+    py = pIn2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations greater than 4 */
+    /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    j = count >> 2u;
+
+    while((j > 0u) && (blockSize3 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
+         * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
+         * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLADX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD   
+       * So, py is incremented by 1 */
+      py = py + 1u;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pIn2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+      j--;
+    }
+
+    /* The second part of the stage starts here */
+    /* SIMD is not used for the next MAC operations,   
+     * so pointer py is updated to read only one sample at a time */
+    py = py + 1u;
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum = __SMLAD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (sum >> 15);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
new file mode 100644
index 0000000000..4003e3af0c
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
@@ -0,0 +1,593 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_fast_q31.c   
+*   
+* Description:	Fast Q31 Partial convolution.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *   
+ * \par   
+ * See arm_conv_partial_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.   
+ */
+
+arm_status arm_conv_partial_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t x0, x1, x2, x3, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counters                 */
+  arm_status status;                             /* status of Partial convolution */
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* The first loop starts here */
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[0] * y[srcBLen - 1] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* x[1] * y[srcBLen - 2] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* x[2] * y[srcBLen - 3] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* x[3] * y[srcBLen - 4] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 1u;
+
+    /* -------------------   
+     * Stage2 process   
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[0] * y[srcBLen - 1] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+          /* Read y[srcBLen - 2] sample */
+          c0 = *(py--);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[1] * y[srcBLen - 2] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+          /* acc1 +=  x[2] * y[srcBLen - 2] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+          /* acc2 +=  x[3] * y[srcBLen - 2] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+          /* acc3 +=  x[4] * y[srcBLen - 2] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[2] * y[srcBLen - 3] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+          /* acc1 +=  x[3] * y[srcBLen - 2] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+          /* acc2 +=  x[4] * y[srcBLen - 2] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+          /* acc3 +=  x[5] * y[srcBLen - 2] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+          /* Read y[srcBLen - 4] sample */
+          c0 = *(py--);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[3] * y[srcBLen - 4] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+          /* acc1 +=  x[4] * y[srcBLen - 4] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+          /* acc2 +=  x[5] * y[srcBLen - 4] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+          /* acc3 +=  x[6] * y[srcBLen - 4] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+        } while(--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (acc0 << 1);
+        *pOut++ = (q31_t) (acc1 << 1);
+        *pOut++ = (q31_t) (acc2 << 1);
+        *pOut++ = (q31_t) (acc3 << 1);
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + (count * 4u);
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum << 1;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * px++ * (*py--))) >> 32);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = sum << 1;
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py--))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = sum << 1;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c
new file mode 100644
index 0000000000..de8d5065c9
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c
@@ -0,0 +1,765 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_q15.c   
+*   
+* Description:	Partial convolution of Q15 sequences.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q15 sequences.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *   
+ * Refer to arm_conv_partial_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+
+arm_status arm_conv_partial_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary input variables */
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter                 */
+  arm_status status;                             /* status of Partial convolution */
+  q31_t *pb;                                     /* 32 bit pointer for inputB buffer */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations less than 4 */
+    /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    while((count < 4u) && (blockSize1 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over number of MAC operations between   
+       * inputA samples and inputB samples */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* The second part of the stage starts here */
+    /* The internal loop, over count, is unrolled by 4 */
+    /* To, read the last two inputB samples using SIMD:   
+     * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+    py = py - 1;
+
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD   
+       * So, py is incremented by 1 */
+      py = py + 1u;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2 - 1u;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* Initialize inputB pointer of type q31 */
+    pb = (q31_t *) (py - 1u);
+
+    /* count is the index by which the pointer pIn1 to be incremented */
+    count = 1u;
+
+
+    /* --------------------   
+     * Stage2 process   
+     * -------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+
+        /* read x[0], x[1] samples */
+        x0 = *(q31_t *) (px++);
+        /* read x[1], x[2] samples */
+        x1 = *(q31_t *) (px++);
+
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read the last two inputB samples using SIMD:   
+           * y[srcBLen - 1] and y[srcBLen - 2] */
+          c0 = *(pb--);
+
+          /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+          acc0 = __SMLALDX(x0, c0, acc0);
+
+          /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+          acc1 = __SMLALDX(x1, c0, acc1);
+
+          /* Read x[2], x[3] */
+          x2 = *(q31_t *) (px++);
+
+          /* Read x[3], x[4] */
+          x3 = *(q31_t *) (px++);
+
+          /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+          acc2 = __SMLALDX(x2, c0, acc2);
+
+          /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+          acc3 = __SMLALDX(x3, c0, acc3);
+
+          /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+          c0 = *(pb--);
+
+          /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+          acc0 = __SMLALDX(x2, c0, acc0);
+
+          /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+          acc1 = __SMLALDX(x3, c0, acc1);
+
+          /* Read x[4], x[5] */
+          x0 = *(q31_t *) (px++);
+
+          /* Read x[5], x[6] */
+          x1 = *(q31_t *) (px++);
+
+          /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+          acc2 = __SMLALDX(x0, c0, acc2);
+
+          /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+          acc3 = __SMLALDX(x1, c0, acc3);
+
+        } while(--k);
+
+        /* For the next MAC operations, SIMD is not used   
+         * So, the 16 bit pointer if inputB, py is updated */
+        py = (q15_t *) pb;
+        py = py + 1;
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        if(k == 1u)
+        {
+          /* Read y[srcBLen - 5] */
+          c0 = *(py);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+          c0 = c0 << 16u;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+          /* Read x[7] */
+          x3 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLALD(x0, c0, acc0);
+          acc1 = __SMLALD(x1, c0, acc1);
+          acc2 = __SMLALDX(x1, c0, acc2);
+          acc3 = __SMLALDX(x3, c0, acc3);
+        }
+
+        if(k == 2u)
+        {
+          /* Read y[srcBLen - 5], y[srcBLen - 6] */
+          c0 = *(pb);
+
+          /* Read x[7], x[8] */
+          x3 = *(q31_t *) px++;
+
+          /* Read x[9] */
+          x2 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLALDX(x0, c0, acc0);
+          acc1 = __SMLALDX(x1, c0, acc1);
+          acc2 = __SMLALDX(x3, c0, acc2);
+          acc3 = __SMLALDX(x2, c0, acc3);
+        }
+
+        if(k == 3u)
+        {
+          /* Read y[srcBLen - 5], y[srcBLen - 6] */
+          c0 = *pb--;
+
+          /* Read x[7], x[8] */
+          x3 = *(q31_t *) px++;
+
+          /* Read x[9] */
+          x2 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLALDX(x0, c0, acc0);
+          acc1 = __SMLALDX(x1, c0, acc1);
+          acc2 = __SMLALDX(x3, c0, acc2);
+          acc3 = __SMLALDX(x2, c0, acc3);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+          /* Read y[srcBLen - 7] */
+          c0 = (*pb);
+          c0 = (c0) << 16;
+
+#else
+
+          /* Read y[srcBLen - 7] */
+          c0 = (q15_t) (*pb >> 16);
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+          /* Read x[10] */
+          x3 = *(q31_t *) px++;
+
+          /* Perform the multiply-accumulates */
+          acc0 = __SMLALDX(x1, c0, acc0);
+          acc1 = __SMLALD(x2, c0, acc1);
+          acc2 = __SMLALDX(x2, c0, acc2);
+          acc3 = __SMLALDX(x3, c0, acc3);
+        }
+
+        /* Store the results in the accumulators in the destination buffer. */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+        *__SIMD32(pOut)++ =
+          __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+        *__SIMD32(pOut)++ =
+          __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+        *__SIMD32(pOut)++ =
+          __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+        *__SIMD32(pOut)++ =
+          __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + (count * 4u);
+        py = pSrc2;
+        pb = (q31_t *) (py - 1);
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += (q63_t) ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    pIn2 = pSrc2 - 1u;
+    py = pIn2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    /* For loop unrolling by 4, this stage is divided into two. */
+    /* First part of this stage computes the MAC operations greater than 4 */
+    /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+    /* The first part of the stage starts here */
+    j = count >> 2u;
+
+    while((j > 0u) && (blockSize3 > 0))
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
+         * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+        /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
+         * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+        sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* For the next MAC operations, the pointer py is used without SIMD   
+       * So, py is incremented by 1 */
+      py = py + 1u;
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pIn2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+      j--;
+    }
+
+    /* The second part of the stage starts here */
+    /* SIMD is not used for the next MAC operations,   
+     * so pointer py is updated to read only one sample at a time */
+    py = py + 1u;
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum = __SMLALD(*px++, *py--, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA;                           /* inputA pointer */
+  q15_t *pIn2 = pSrcB;                           /* inputB pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0; j <= i; j++)
+      {
+        /* Check the array limitations */
+        if(((i - j) < srcBLen) && (j < srcALen))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += ((q31_t) pIn1[j] * (pIn2[i - j]));
+        }
+      }
+
+      /* Store the output in the destination buffer */
+      pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*     #ifndef ARM_MATH_CM0      */
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c
new file mode 100644
index 0000000000..ab7a4cc010
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c
@@ -0,0 +1,616 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_q31.c   
+*   
+* Description:	Partial convolution of Q31 sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q31 sequences.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *   
+ * See arm_conv_partial_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+arm_status arm_conv_partial_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers        */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator                  */
+  q31_t x0, x1, x2, x3, c0;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter                 */
+  arm_status status;                             /* status of Partial convolution */
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* The first loop starts here */
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[0] * y[srcBLen - 1] */
+        sum += (q63_t) * px++ * (*py--);
+        /* x[1] * y[srcBLen - 2] */
+        sum += (q63_t) * px++ * (*py--);
+        /* x[2] * y[srcBLen - 3] */
+        sum += (q63_t) * px++ * (*py--);
+        /* x[3] * y[srcBLen - 4] */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 1u;
+
+    /* -------------------   
+     * Stage2 process   
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[0] * y[srcBLen - 1] */
+          acc0 += (q63_t) x0 *c0;
+          /* acc1 +=  x[1] * y[srcBLen - 1] */
+          acc1 += (q63_t) x1 *c0;
+          /* acc2 +=  x[2] * y[srcBLen - 1] */
+          acc2 += (q63_t) x2 *c0;
+          /* acc3 +=  x[3] * y[srcBLen - 1] */
+          acc3 += (q63_t) x3 *c0;
+
+          /* Read y[srcBLen - 2] sample */
+          c0 = *(py--);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* Perform the multiply-accumulate */
+          /* acc0 +=  x[1] * y[srcBLen - 2] */
+          acc0 += (q63_t) x1 *c0;
+          /* acc1 +=  x[2] * y[srcBLen - 2] */
+          acc1 += (q63_t) x2 *c0;
+          /* acc2 +=  x[3] * y[srcBLen - 2] */
+          acc2 += (q63_t) x3 *c0;
+          /* acc3 +=  x[4] * y[srcBLen - 2] */
+          acc3 += (q63_t) x0 *c0;
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[2] * y[srcBLen - 3] */
+          acc0 += (q63_t) x2 *c0;
+          /* acc1 +=  x[3] * y[srcBLen - 2] */
+          acc1 += (q63_t) x3 *c0;
+          /* acc2 +=  x[4] * y[srcBLen - 2] */
+          acc2 += (q63_t) x0 *c0;
+          /* acc3 +=  x[5] * y[srcBLen - 2] */
+          acc3 += (q63_t) x1 *c0;
+
+          /* Read y[srcBLen - 4] sample */
+          c0 = *(py--);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[3] * y[srcBLen - 4] */
+          acc0 += (q63_t) x3 *c0;
+          /* acc1 +=  x[4] * y[srcBLen - 4] */
+          acc1 += (q63_t) x0 *c0;
+          /* acc2 +=  x[5] * y[srcBLen - 4] */
+          acc2 += (q63_t) x1 *c0;
+          /* acc3 +=  x[6] * y[srcBLen - 4] */
+          acc3 += (q63_t) x2 *c0;
+
+        } while(--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 += (q63_t) x0 *c0;
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 += (q63_t) x1 *c0;
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 += (q63_t) x2 *c0;
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 += (q63_t) x3 *c0;
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (acc0 >> 31);
+        *pOut++ = (q31_t) (acc1 >> 31);
+        *pOut++ = (q31_t) (acc2 >> 31);
+        *pOut++ = (q31_t) (acc3 >> 31);
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + (count * 4u);
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * px++ * (*py--);
+          sum += (q63_t) * px++ * (*py--);
+          sum += (q63_t) * px++ * (*py--);
+          sum += (q63_t) * px++ * (*py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += (q63_t) * px++ * (*py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (sum >> 31);
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += (q63_t) * px++ * (*py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q31_t) (sum >> 31);
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The blockSize3 variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pIn1 = pSrcA;                           /* inputA pointer */
+  q31_t *pIn2 = pSrcB;                           /* inputB pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0; j <= i; j++)
+      {
+        /* Check the array limitations */
+        if(((i - j) < srcBLen) && (j < srcALen))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
+        }
+      }
+
+      /* Store the output in the destination buffer */
+      pDst[i] = (q31_t) (sum >> 31u);
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*    #ifndef ARM_MATH_CM0      */
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c
new file mode 100644
index 0000000000..a6a0d5a000
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c
@@ -0,0 +1,723 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_partial_q7.c   
+*   
+* Description:	Partial convolution of Q7 sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup PartialConv   
+ * @{   
+ */
+
+/**   
+ * @brief Partial convolution of Q7 sequences.   
+ * @param[in]       *pSrcA points to the first input sequence.   
+ * @param[in]       srcALen length of the first input sequence.   
+ * @param[in]       *pSrcB points to the second input sequence.   
+ * @param[in]       srcBLen length of the second input sequence.   
+ * @param[out]      *pDst points to the location where the output result is written.   
+ * @param[in]       firstIndex is the first output sample to start with.   
+ * @param[in]       numPoints is the number of output points to be computed.   
+ * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].   
+ *   
+ */
+
+arm_status arm_conv_partial_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst,
+  uint32_t firstIndex,
+  uint32_t numPoints)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pIn1;                                    /* inputA pointer */
+  q7_t *pIn2;                                    /* inputB pointer */
+  q7_t *pOut = pDst;                             /* output pointer */
+  q7_t *px;                                      /* Intermediate inputA pointer */
+  q7_t *py;                                      /* Intermediate inputB pointer */
+  q7_t *pSrc1, *pSrc2;                           /* Intermediate pointers */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q31_t input1, input2;
+  q15_t in1, in2;
+  q7_t x0, x1, x2, x3, c0, c1;
+  uint32_t j, k, count, check, blkCnt;
+  int32_t blockSize1, blockSize2, blockSize3;    /* loop counter */
+  arm_status status;
+
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_MATH_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+
+    /* The algorithm implementation is based on the lengths of the inputs. */
+    /* srcB is always made to slide across srcA. */
+    /* So srcBLen is always considered as shorter or equal to srcALen */
+    if(srcALen >= srcBLen)
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcA;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcB;
+    }
+    else
+    {
+      /* Initialization of inputA pointer */
+      pIn1 = pSrcB;
+
+      /* Initialization of inputB pointer */
+      pIn2 = pSrcA;
+
+      /* srcBLen is always considered as shorter or equal to srcALen */
+      j = srcBLen;
+      srcBLen = srcALen;
+      srcALen = j;
+    }
+
+    /* Conditions to check which loopCounter holds   
+     * the first and last indices of the output samples to be calculated. */
+    check = firstIndex + numPoints;
+    blockSize3 = ((int32_t) check - (int32_t) srcALen);
+    blockSize3 = (blockSize3 > 0) ? blockSize3 : 0;
+    blockSize1 = (((int32_t) srcBLen - 1) - (int32_t) firstIndex);
+    blockSize1 = (blockSize1 > 0) ? ((check > (srcBLen - 1u)) ? blockSize1 :
+                                     (int32_t) numPoints) : 0;
+    blockSize2 = (int32_t) check - ((blockSize3 + blockSize1) +
+                                    (int32_t) firstIndex);
+    blockSize2 = (blockSize2 > 0) ? blockSize2 : 0;
+
+    /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+    /* The function is internally   
+     * divided into three stages according to the number of multiplications that has to be   
+     * taken place between inputA samples and inputB samples. In the first stage of the   
+     * algorithm, the multiplications increase by one for every iteration.   
+     * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+     * In the third stage of the algorithm, the multiplications decrease by one   
+     * for every iteration. */
+
+    /* Set the output pointer to point to the firstIndex   
+     * of the output sample to be calculated. */
+    pOut = pDst + firstIndex;
+
+    /* --------------------------   
+     * Initializations of stage1   
+     * -------------------------*/
+
+    /* sum = x[0] * y[0]   
+     * sum = x[0] * y[1] + x[1] * y[0]   
+     * ....   
+     * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+     */
+
+    /* In this stage the MAC operations are increased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed.   
+       Since the partial convolution starts from from firstIndex   
+       Number of Macs to be performed is firstIndex + 1 */
+    count = 1u + firstIndex;
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + firstIndex;
+    py = pSrc2;
+
+    /* ------------------------   
+     * Stage1 process   
+     * ----------------------*/
+
+    /* The first stage starts here */
+    while(blockSize1 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* x[0] , x[1] */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[srcBLen - 1] , y[srcBLen - 2] */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* x[0] * y[srcBLen - 1] */
+        /* x[1] * y[srcBLen - 2] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* x[2] , x[3] */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[srcBLen - 3] , y[srcBLen - 4] */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* x[2] * y[srcBLen - 3] */
+        /* x[3] * y[srcBLen - 4] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      py = ++pSrc2;
+      px = pIn1;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blockSize1--;
+    }
+
+    /* --------------------------   
+     * Initializations of stage2   
+     * ------------------------*/
+
+    /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+     * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+     * ....   
+     * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+     */
+
+    /* Working pointer of inputA */
+    px = pIn1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* count is index by which the pointer pIn1 to be incremented */
+    count = 1u;
+
+    /* -------------------   
+     * Stage2 process   
+     * ------------------*/
+
+    /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+     * So, to loop unroll over blockSize2,   
+     * srcBLen should be greater than or equal to 4 */
+    if(srcBLen >= 4u)
+    {
+      /* Loop unroll over blockSize2, by 4 */
+      blkCnt = ((uint32_t) blockSize2 >> 2u);
+
+      while(blkCnt > 0u)
+      {
+        /* Set all accumulators to zero */
+        acc0 = 0;
+        acc1 = 0;
+        acc2 = 0;
+        acc3 = 0;
+
+        /* read x[0], x[1], x[2] samples */
+        x0 = *(px++);
+        x1 = *(px++);
+        x2 = *(px++);
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        do
+        {
+          /* Read y[srcBLen - 1] sample */
+          c0 = *(py--);
+          /* Read y[srcBLen - 2] sample */
+          c1 = *(py--);
+
+          /* Read x[3] sample */
+          x3 = *(px++);
+
+          /* x[0] and x[1] are packed */
+          in1 = (q15_t) x0;
+          in2 = (q15_t) x1;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* y[srcBLen - 1]   and y[srcBLen - 2] are packed */
+          in1 = (q15_t) c0;
+          in2 = (q15_t) c1;
+
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2]  */
+          acc0 = __SMLAD(input1, input2, acc0);
+
+          /* x[1] and x[2] are packed */
+          in1 = (q15_t) x1;
+          in2 = (q15_t) x2;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2]  */
+          acc1 = __SMLAD(input1, input2, acc1);
+
+          /* x[2] and x[3] are packed */
+          in1 = (q15_t) x2;
+          in2 = (q15_t) x3;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2]  */
+          acc2 = __SMLAD(input1, input2, acc2);
+
+          /* Read x[4] sample */
+          x0 = *(px++);
+
+          /* x[3] and x[4] are packed */
+          in1 = (q15_t) x3;
+          in2 = (q15_t) x0;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2]  */
+          acc3 = __SMLAD(input1, input2, acc3);
+
+          /* Read y[srcBLen - 3] sample */
+          c0 = *(py--);
+          /* Read y[srcBLen - 4] sample */
+          c1 = *(py--);
+
+          /* Read x[5] sample */
+          x1 = *(px++);
+
+          /* x[2] and x[3] are packed */
+          in1 = (q15_t) x2;
+          in2 = (q15_t) x3;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+          in1 = (q15_t) c0;
+          in2 = (q15_t) c1;
+
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4]  */
+          acc0 = __SMLAD(input1, input2, acc0);
+
+          /* x[3] and x[4] are packed */
+          in1 = (q15_t) x3;
+          in2 = (q15_t) x0;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4]  */
+          acc1 = __SMLAD(input1, input2, acc1);
+
+          /* x[4] and x[5] are packed */
+          in1 = (q15_t) x0;
+          in2 = (q15_t) x1;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4]  */
+          acc2 = __SMLAD(input1, input2, acc2);
+
+          /* Read x[6] sample */
+          x2 = *(px++);
+
+          /* x[5] and x[6] are packed */
+          in1 = (q15_t) x1;
+          in2 = (q15_t) x2;
+
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4]  */
+          acc3 = __SMLAD(input1, input2, acc3);
+
+        } while(--k);
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Read y[srcBLen - 5] sample */
+          c0 = *(py--);
+
+          /* Read x[7] sample */
+          x3 = *(px++);
+
+          /* Perform the multiply-accumulates */
+          /* acc0 +=  x[4] * y[srcBLen - 5] */
+          acc0 += ((q31_t) x0 * c0);
+          /* acc1 +=  x[5] * y[srcBLen - 5] */
+          acc1 += ((q31_t) x1 * c0);
+          /* acc2 +=  x[6] * y[srcBLen - 5] */
+          acc2 += ((q31_t) x2 * c0);
+          /* acc3 +=  x[7] * y[srcBLen - 5] */
+          acc3 += ((q31_t) x3 * c0);
+
+          /* Reuse the present samples for the next MAC */
+          x0 = x1;
+          x1 = x2;
+          x2 = x3;
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q7_t) (__SSAT(acc0 >> 7, 8));
+        *pOut++ = (q7_t) (__SSAT(acc1 >> 7, 8));
+        *pOut++ = (q7_t) (__SSAT(acc2 >> 7, 8));
+        *pOut++ = (q7_t) (__SSAT(acc3 >> 7, 8));
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count * 4u;
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+
+      /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      blkCnt = (uint32_t) blockSize2 % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        k = srcBLen >> 2u;
+
+        /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+         ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+        while(k > 0u)
+        {
+
+          /* Reading two inputs of SrcA buffer and packing */
+          in1 = (q15_t) * px++;
+          in2 = (q15_t) * px++;
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Reading two inputs of SrcB buffer and packing */
+          in1 = (q15_t) * py--;
+          in2 = (q15_t) * py--;
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Perform the multiply-accumulates */
+          sum = __SMLAD(input1, input2, sum);
+
+          /* Reading two inputs of SrcA buffer and packing */
+          in1 = (q15_t) * px++;
+          in2 = (q15_t) * px++;
+          input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Reading two inputs of SrcB buffer and packing */
+          in1 = (q15_t) * py--;
+          in2 = (q15_t) * py--;
+          input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+          /* Perform the multiply-accumulates */
+          sum = __SMLAD(input1, input2, sum);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        k = srcBLen % 0x4u;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulates */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the pointer pIn1 index, count by 1 */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+    else
+    {
+      /* If the srcBLen is not a multiple of 4,   
+       * the blockSize2 loop cannot be unrolled by 4 */
+      blkCnt = (uint32_t) blockSize2;
+
+      while(blkCnt > 0u)
+      {
+        /* Accumulator is made zero for every iteration */
+        sum = 0;
+
+        /* srcBLen number of MACS should be performed */
+        k = srcBLen;
+
+        while(k > 0u)
+        {
+          /* Perform the multiply-accumulate */
+          sum += ((q31_t) * px++ * *py--);
+
+          /* Decrement the loop counter */
+          k--;
+        }
+
+        /* Store the result in the accumulator in the destination buffer. */
+        *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+        /* Update the inputA and inputB pointers for next MAC calculation */
+        px = pIn1 + count;
+        py = pSrc2;
+
+        /* Increment the MAC count */
+        count++;
+
+        /* Decrement the loop counter */
+        blkCnt--;
+      }
+    }
+
+
+    /* --------------------------   
+     * Initializations of stage3   
+     * -------------------------*/
+
+    /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+     * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+     * ....   
+     * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+     * sum +=  x[srcALen-1] * y[srcBLen-1]   
+     */
+
+    /* In this stage the MAC operations are decreased by 1 for every iteration.   
+       The count variable holds the number of MAC operations performed */
+    count = srcBLen - 1u;
+
+    /* Working pointer of inputA */
+    pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+    px = pSrc1;
+
+    /* Working pointer of inputB */
+    pSrc2 = pIn2 + (srcBLen - 1u);
+    py = pSrc2;
+
+    /* -------------------   
+     * Stage3 process   
+     * ------------------*/
+
+    while(blockSize3 > 0)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = count >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+        /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+        /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the count is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = count % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+        sum += ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = ++pSrc1;
+      py = pSrc2;
+
+      /* Decrement the MAC count */
+      count--;
+
+      /* Decrement the loop counter */
+      blockSize3--;
+
+    }
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t *pIn1 = pSrcA;                            /* inputA pointer */
+  q7_t *pIn2 = pSrcB;                            /* inputB pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counters */
+  arm_status status;                             /* status of Partial convolution */
+
+  /* Check for range of output samples to be calculated */
+  if((firstIndex + numPoints) > ((srcALen + (srcBLen - 1u))))
+  {
+    /* Set status as ARM_ARGUMENT_ERROR */
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Loop to calculate convolution for output length number of values */
+    for (i = firstIndex; i <= (firstIndex + numPoints - 1); i++)
+    {
+      /* Initialize sum with zero to carry on MAC operations */
+      sum = 0;
+
+      /* Loop to perform MAC operations according to convolution equation */
+      for (j = 0; j <= i; j++)
+      {
+        /* Check the array limitations */
+        if(((i - j) < srcBLen) && (j < srcALen))
+        {
+          /* z[i] += x[i-j] * y[j] */
+          sum += ((q15_t) pIn1[j] * (pIn2[i - j]));
+        }
+      }
+
+      /* Store the output in the destination buffer */
+      pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
+    }
+    /* set status as ARM_SUCCESS as there are no argument errors */
+    status = ARM_MATH_SUCCESS;
+  }
+  return (status);
+
+#endif /*  #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of PartialConv group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c
new file mode 100644
index 0000000000..71e15fd4cd
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c
@@ -0,0 +1,727 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_q15.c   
+*   
+* Description:	Convolution of Q15 sequences.     
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of Q15 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * This approach provides 33 guard bits and there is no risk of overflow.   
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.   
+ *   
+ * \par   
+ * Refer to arm_conv_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_conv_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn1;                                   /* inputA pointer */
+  q15_t *pIn2;                                   /* inputB pointer */
+  q15_t *pOut = pDst;                            /* output pointer */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t blockSize1, blockSize2, blockSize3, j, k, count, blkCnt;     /* loop counter */
+  q31_t *pb;                                     /* 32 bit pointer for inputB buffer */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations less than 4 */
+  /* Second part of this stage computes the MAC operations greater than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  while((count < 4u) && (blockSize1 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Loop over number of MAC operations between   
+     * inputA samples and inputB samples */
+    k = count;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* The second part of the stage starts here */
+  /* The internal loop, over count, is unrolled by 4 */
+  /* To, read the last two inputB samples using SIMD:   
+   * y[srcBLen] and y[srcBLen-1] coefficients, py is decremented by 1 */
+  py = py - 1;
+
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0], x[1] are multiplied with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[2], x[3] are multiplied with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD   
+     * So, py is incremented by 1 */
+    py = py + 1u;
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + (count - 1u);
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* Initialize inputB pointer of type q31 */
+  pb = (q31_t *) (py - 1u);
+
+  /* count is the index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+
+  /* --------------------   
+   * Stage2 process   
+   * -------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+
+      /* read x[0], x[1] samples */
+      x0 = *(q31_t *) (px++);
+      /* read x[1], x[2] samples */
+      x1 = *(q31_t *) (px++);
+
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the last two inputB samples using SIMD:   
+         * y[srcBLen - 1] and y[srcBLen - 2] */
+        c0 = *(pb--);
+
+        /* acc0 +=  x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2] */
+        acc0 = __SMLALDX(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2] */
+        acc1 = __SMLALDX(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *(q31_t *) (px++);
+
+        /* Read x[3], x[4] */
+        x3 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2] */
+        acc2 = __SMLALDX(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2] */
+        acc3 = __SMLALDX(x3, c0, acc3);
+
+        /* Read y[srcBLen - 3] and y[srcBLen - 4] */
+        c0 = *(pb--);
+
+        /* acc0 +=  x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4] */
+        acc0 = __SMLALDX(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4] */
+        acc1 = __SMLALDX(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = *(q31_t *) (px++);
+
+        /* Read x[5], x[6] */
+        x1 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4] */
+        acc2 = __SMLALDX(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4] */
+        acc3 = __SMLALDX(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+      py = (q15_t *) pb;
+      py = py + 1;
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[srcBLen - 5] */
+        c0 = *(py);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALDX(x1, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = *(pb);
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x0, c0, acc0);
+        acc1 = __SMLALDX(x1, c0, acc1);
+        acc2 = __SMLALDX(x3, c0, acc2);
+        acc3 = __SMLALDX(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[srcBLen - 5], y[srcBLen - 6] */
+        c0 = *pb--;
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x0, c0, acc0);
+        acc1 = __SMLALDX(x1, c0, acc1);
+        acc2 = __SMLALDX(x3, c0, acc2);
+        acc3 = __SMLALDX(x2, c0, acc3);
+
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        /* Read y[srcBLen - 7] */
+        c0 = (*pb);
+
+        //c0 = (c0 & 0x0000FFFF)<<16; 
+        c0 = (c0) << 16;
+
+#else
+
+        /* Read y[srcBLen - 7] */
+        c0 = (q15_t) (*pb >> 16);
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x1, c0, acc0);
+        acc1 = __SMLALD(x2, c0, acc1);
+        acc2 = __SMLALDX(x2, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+
+      /* Store the results in the accumulators in the destination buffer. */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+      *__SIMD32(pOut)++ =
+        __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pSrc2;
+      pb = (q31_t *) (py - 1);
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) ((q31_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q15_t) (__SSAT(sum >> 15, 16));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  blockSize3 = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  pIn2 = pSrc2 - 1u;
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  /* For loop unrolling by 4, this stage is divided into two. */
+  /* First part of this stage computes the MAC operations greater than 4 */
+  /* Second part of this stage computes the MAC operations less than or equal to 4 */
+
+  /* The first part of the stage starts here */
+  j = blockSize3 >> 2u;
+
+  while((j > 0u) && (blockSize3 > 0u))
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[srcALen - srcBLen + 1], x[srcALen - srcBLen + 2] are multiplied   
+       * with y[srcBLen - 1], y[srcBLen - 2] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+      /* x[srcALen - srcBLen + 3], x[srcALen - srcBLen + 4] are multiplied   
+       * with y[srcBLen - 3], y[srcBLen - 4] respectively */
+      sum = __SMLALDX(*__SIMD32(px)++, *__SIMD32(py)--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* For the next MAC operations, the pointer py is used without SIMD   
+     * So, py is incremented by 1 */
+    py = py + 1u;
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 5] * y[srcBLen - 5] */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+
+    j--;
+  }
+
+  /* The second part of the stage starts here */
+  /* SIMD is not used for the next MAC operations,   
+   * so pointer py is updated to read only one sample at a time */
+  py = py + 1u;
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum +=  x[srcALen-1] * y[srcBLen-1] */
+      sum = __SMLALD(*px++, *py--, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA;                           /* input pointer */
+  q15_t *pIn2 = pSrcB;                           /* coefficient pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counter */
+
+  /* Loop to calculate output of convolution for output length number of times */
+  for (i = 0; i < (srcALen + srcBLen - 1); i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if(((i - j) < srcBLen) && (j < srcALen))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += (q31_t) pIn1[j] * (pIn2[i - j]);
+      }
+    }
+
+    /* Store the output in the destination buffer */
+    pDst[i] = (q15_t) __SSAT((sum >> 15u), 16u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c
new file mode 100644
index 0000000000..b98bca0639
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c
@@ -0,0 +1,583 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_q31.c   
+*   
+* Description:	Convolution of Q31 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of Q31 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * There is no saturation on intermediate additions.   
+ * Thus, if the accumulator overflows it wraps around and distorts the result.   
+ * The input signals should be scaled down to avoid intermediate overflows.   
+ * Scale down the inputs by log2(min(srcALen, srcBLen)) (log2 is read as log to the base 2) times to avoid overflows,   
+ * as maximum of min(srcALen, srcBLen) number of additions are carried internally.   
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.   
+ *   
+ * \par   
+ * See arm_conv_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_conv_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1;                                   /* inputA pointer */
+  q31_t *pIn2;                                   /* inputB pointer */
+  q31_t *pOut = pDst;                            /* output pointer */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1, *pSrc2;                          /* Intermediate pointers */
+  q63_t sum;                                     /* Accumulator */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulator */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold state and coefficient values */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (q31_t *) pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = (q31_t *) pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py--);
+      /* x[1] * y[srcBLen - 2] */
+      sum += (q63_t) * px++ * (*py--);
+      /* x[2] * y[srcBLen - 3] */
+      sum += (q63_t) * px++ * (*py--);
+      /* x[3] * y[srcBLen - 4] */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q31_t) (sum >> 31);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[0] * y[srcBLen - 1] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[1] * y[srcBLen - 1] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[2] * y[srcBLen - 1] */
+        acc2 += ((q63_t) x2 * c0);
+        /* acc3 +=  x[3] * y[srcBLen - 1] */
+        acc3 += ((q63_t) x3 * c0);
+
+        /* Read y[srcBLen - 2] sample */
+        c0 = *(py--);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[srcBLen - 2] */
+        acc0 += ((q63_t) x1 * c0);
+        /* acc1 +=  x[2] * y[srcBLen - 2] */
+        acc1 += ((q63_t) x2 * c0);
+        /* acc2 +=  x[3] * y[srcBLen - 2] */
+        acc2 += ((q63_t) x3 * c0);
+        /* acc3 +=  x[4] * y[srcBLen - 2] */
+        acc3 += ((q63_t) x0 * c0);
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[srcBLen - 3] */
+        acc0 += ((q63_t) x2 * c0);
+        /* acc1 +=  x[3] * y[srcBLen - 2] */
+        acc1 += ((q63_t) x3 * c0);
+        /* acc2 +=  x[4] * y[srcBLen - 2] */
+        acc2 += ((q63_t) x0 * c0);
+        /* acc3 +=  x[5] * y[srcBLen - 2] */
+        acc3 += ((q63_t) x1 * c0);
+
+        /* Read y[srcBLen - 4] sample */
+        c0 = *(py--);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[srcBLen - 4] */
+        acc0 += ((q63_t) x3 * c0);
+        /* acc1 +=  x[4] * y[srcBLen - 4] */
+        acc1 += ((q63_t) x0 * c0);
+        /* acc2 +=  x[5] * y[srcBLen - 4] */
+        acc2 += ((q63_t) x1 * c0);
+        /* acc3 +=  x[6] * y[srcBLen - 4] */
+        acc3 += ((q63_t) x2 * c0);
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 += ((q63_t) x2 * c0);
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 += ((q63_t) x3 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the results in the accumulators in the destination buffer. */
+      *pOut++ = (q31_t) (acc0 >> 31);
+      *pOut++ = (q31_t) (acc1 >> 31);
+      *pOut++ = (q31_t) (acc2 >> 31);
+      *pOut++ = (q31_t) (acc3 >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q31_t) (sum >> 31);
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py--);
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum += (q63_t) * px++ * (*py--);
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      sum += (q63_t) * px++ * (*py--);
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (q63_t) * px++ * (*py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q31_t) (sum >> 31);
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pIn1 = pSrcA;                           /* input pointer */
+  q31_t *pIn2 = pSrcB;                           /* coefficient pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counter */
+
+  /* Loop to calculate output of convolution for output length number of times */
+  for (i = 0; i < (srcALen + srcBLen - 1); i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if(((i - j) < srcBLen) && (j < srcALen))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q63_t) pIn1[j] * (pIn2[i - j]));
+      }
+    }
+
+    /* Store the output in the destination buffer */
+    pDst[i] = (q31_t) (sum >> 31u);
+  }
+
+#endif /*     #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c
new file mode 100644
index 0000000000..cfdea705ea
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c
@@ -0,0 +1,680 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_conv_q7.c   
+*   
+* Description:	Convolution of Q7 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Conv   
+ * @{   
+ */
+
+/**   
+ * @brief Convolution of Q7 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.   
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.   
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   
+ * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.   
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and then saturated to 1.7 format.   
+ */
+
+void arm_conv_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pIn1;                                    /* inputA pointer */
+  q7_t *pIn2;                                    /* inputB pointer */
+  q7_t *pOut = pDst;                             /* output pointer */
+  q7_t *px;                                      /* Intermediate inputA pointer */
+  q7_t *py;                                      /* Intermediate inputB pointer */
+  q7_t *pSrc1, *pSrc2;                           /* Intermediate pointers */
+  q7_t x0, x1, x2, x3, c0, c1;                   /* Temporary variables to hold state and coefficient values */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulator */
+  q31_t input1, input2;                          /* Temporary input variables */
+  q15_t in1, in2;                                /* Temporary input variables */
+  uint32_t j, k, count, blkCnt, blockSize1, blockSize2, blockSize3;     /* loop counter */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+  }
+
+  /* conv(x,y) at n = x[n] * y[0] + x[n-1] * y[1] + x[n-2] * y[2] + ...+ x[n-N+1] * y[N -1] */
+  /* The function is internally   
+   * divided into three stages according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first stage of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second stage of the algorithm, srcBLen number of multiplications are done.   
+   * In the third stage of the algorithm, the multiplications decrease by one   
+   * for every iteration. */
+
+  /* The algorithm is implemented in three stages.   
+     The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = (srcALen - srcBLen) + 1u;
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[0]   
+   * sum = x[0] * y[1] + x[1] * y[0]   
+   * ....   
+   * sum = x[0] * y[srcBlen - 1] + x[1] * y[srcBlen - 2] +...+ x[srcBLen - 1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] , x[1] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* y[srcBLen - 1] , y[srcBLen - 2] */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* x[0] * y[srcBLen - 1] */
+      /* x[1] * y[srcBLen - 2] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* x[2] , x[3] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* y[srcBLen - 3] , y[srcBLen - 4] */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* x[2] * y[srcBLen - 3] */
+      /* x[3] * y[srcBLen - 4] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q15_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pIn2 + count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[srcBLen-1] + x[1] * y[srcBLen-2] +...+ x[srcBLen-1] * y[0]   
+   * sum = x[1] * y[srcBLen-1] + x[2] * y[srcBLen-2] +...+ x[srcBLen] * y[0]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[srcBLen-1] + x[srcALen] * y[srcBLen-2] +...+ x[srcALen-1] * y[0]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[srcBLen - 1] sample */
+        c0 = *(py--);
+        /* Read y[srcBLen - 2] sample */
+        c1 = *(py--);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* x[0] and x[1] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* y[srcBLen - 1]   and y[srcBLen - 2] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc0 += x[0] * y[srcBLen - 1] + x[1] * y[srcBLen - 2]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[1] and x[2] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc1 += x[1] * y[srcBLen - 1] + x[2] * y[srcBLen - 2]  */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc2 += x[2] * y[srcBLen - 1] + x[3] * y[srcBLen - 2]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc3 += x[3] * y[srcBLen - 1] + x[4] * y[srcBLen - 2]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+        /* Read y[srcBLen - 3] sample */
+        c0 = *(py--);
+        /* Read y[srcBLen - 4] sample */
+        c1 = *(py--);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* y[srcBLen - 3] and y[srcBLen - 4] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc0 += x[2] * y[srcBLen - 3] + x[3] * y[srcBLen - 4]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc1 += x[3] * y[srcBLen - 3] + x[4] * y[srcBLen - 4]  */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[4] and x[5] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc2 += x[4] * y[srcBLen - 3] + x[5] * y[srcBLen - 4]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* x[5] and x[6] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* acc3 += x[5] * y[srcBLen - 3] + x[6] * y[srcBLen - 4]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[srcBLen - 5] sample */
+        c0 = *(py--);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[srcBLen - 5] */
+        acc0 += ((q15_t) x0 * c0);
+        /* acc1 +=  x[5] * y[srcBLen - 5] */
+        acc1 += ((q15_t) x1 * c0);
+        /* acc2 +=  x[6] * y[srcBLen - 5] */
+        acc2 += ((q15_t) x2 * c0);
+        /* acc3 +=  x[7] * y[srcBLen - 5] */
+        acc3 += ((q15_t) x3 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(acc0 >> 7u, 8));
+      *pOut++ = (q7_t) (__SSAT(acc1 >> 7u, 8));
+      *pOut++ = (q7_t) (__SSAT(acc2 >> 7u, 8));
+      *pOut++ = (q7_t) (__SSAT(acc3 >> 7u, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py--;
+        in2 = (q15_t) * py--;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q15_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* srcBLen number of MACS should be performed */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q15_t) * px++ * *py--);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pSrc2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[srcBLen-1] + x[srcALen-srcBLen+2] * y[srcBLen-2] +...+ x[srcALen-1] * y[1]   
+   * sum += x[srcALen-srcBLen+2] * y[srcBLen-1] + x[srcALen-srcBLen+3] * y[srcBLen-2] +...+ x[srcALen-1] * y[2]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[srcBLen-1] + x[srcALen-1] * y[srcBLen-2]   
+   * sum +=  x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The blockSize3 variable holds the number of MAC operations performed */
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  pSrc2 = pIn2 + (srcBLen - 1u);
+  py = pSrc2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = blockSize3 >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Reading two inputs, x[srcALen - srcBLen + 1] and x[srcALen - srcBLen + 2] of SrcA buffer and packing */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* Reading two inputs, y[srcBLen - 1] and y[srcBLen - 2] of SrcB buffer and packing */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* sum += x[srcALen - srcBLen + 1] * y[srcBLen - 1] */
+      /* sum += x[srcALen - srcBLen + 2] * y[srcBLen - 2] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Reading two inputs, x[srcALen - srcBLen + 3] and x[srcALen - srcBLen + 4] of SrcA buffer and packing */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* Reading two inputs, y[srcBLen - 3] and y[srcBLen - 4] of SrcB buffer and packing */
+      in1 = (q15_t) * py--;
+      in2 = (q15_t) * py--;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16u);
+
+      /* sum += x[srcALen - srcBLen + 3] * y[srcBLen - 3] */
+      /* sum += x[srcALen - srcBLen + 4] * y[srcBLen - 4] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the blockSize3 is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = blockSize3 % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q15_t) * px++ * *py--);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut++ = (q7_t) (__SSAT(sum >> 7u, 8));
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pSrc2;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t *pIn1 = pSrcA;                            /* input pointer */
+  q7_t *pIn2 = pSrcB;                            /* coefficient pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint32_t i, j;                                 /* loop counter */
+
+  /* Loop to calculate output of convolution for output length number of times */
+  for (i = 0; i < (srcALen + srcBLen - 1); i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if(((i - j) < srcBLen) && (j < srcALen))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += (q15_t) pIn1[j] * (pIn2[i - j]);
+      }
+    }
+
+    /* Store the output in the destination buffer */
+    pDst[i] = (q7_t) __SSAT((sum >> 7u), 8u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0        */
+
+}
+
+/**   
+ * @} end of Conv group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c
new file mode 100644
index 0000000000..488046efda
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c
@@ -0,0 +1,718 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_f32.c   
+*   
+* Description:	 Correlation of floating-point sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup Corr Correlation   
+ *   
+ * Correlation is a mathematical operation that is similar to convolution.   
+ * As with convolution, correlation uses two signals to produce a third signal.   
+ * The underlying algorithms in correlation and convolution are identical except that one of the inputs is flipped in convolution.   
+ * Correlation is commonly used to measure the similarity between two signals.   
+ * It has applications in pattern recognition, cryptanalysis, and searching.   
+ * The CMSIS library provides correlation functions for Q7, Q15, Q31 and floating-point data types.   
+ * Fast versions of the Q15 and Q31 functions are also provided.   
+ *   
+ * \par Algorithm   
+ * Let a[n] and b[n] be sequences of length srcALen and srcBLen samples respectively.   
+ * The convolution of the two signals is denoted by   
+ * 
       
+ *                   c[n] = a[n] * b[n]   
+ * 
       
+ * In correlation, one of the signals is flipped in time   
+ * 
       
+ *                   c[n] = a[n] * b[-n]   
+ * 
       
+ *   
+ * \par   
+ * and this is mathematically defined as   
+ * \image html CorrelateEquation.gif   
+ * \par   
+ * The pSrcA points to the first input vector of length srcALen and pSrcB points to the second input vector of length srcBLen.   
+ * The result c[n] is of length 2 * max(srcALen, srcBLen) - 1 and is defined over the interval n=0, 1, 2, ..., (2 * max(srcALen, srcBLen) - 2).   
+ * The output result is written to pDst and the calling function must allocate 2 * max(srcALen, srcBLen) - 1 words for the result.   
+ *   
+ * Note  
+ * \par 
+ * The pDst should be initialized to all zeros before being used. 
+ * 
+ * Fixed-Point Behavior   
+ * \par   
+ * Correlation requires summing up a large number of intermediate products.   
+ * As such, the Q7, Q15, and Q31 functions run a risk of overflow and saturation.   
+ * Refer to the function specific documentation below for further details of the particular algorithm used.   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+/**   
+ * @brief Correlation of floating-point sequences.   
+ * @param[in]  *pSrcA points to the first input sequence.   
+ * @param[in]  srcALen length of the first input sequence.   
+ * @param[in]  *pSrcB points to the second input sequence.   
+ * @param[in]  srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ */
+
+void arm_correlate_f32(
+  float32_t * pSrcA,
+  uint32_t srcALen,
+  float32_t * pSrcB,
+  uint32_t srcBLen,
+  float32_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t *pIn1;                               /* inputA pointer */
+  float32_t *pIn2;                               /* inputB pointer */
+  float32_t *pOut = pDst;                        /* output pointer */
+  float32_t *px;                                 /* Intermediate inputA pointer */
+  float32_t *py;                                 /* Intermediate inputB pointer */
+  float32_t *pSrc1;                              /* Intermediate pointers */
+  float32_t sum, acc0, acc1, acc2, acc3;         /* Accumulators */
+  float32_t x0, x1, x2, x3, c0;                  /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counters */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcA;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcB;
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding has to be done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+    //while(j > 0u)  
+    //{  
+    //  /* Zero is stored in the destination buffer */  
+    //  *pOut++ = 0.0f;  
+
+    //  /* Decrement the loop counter */  
+    //  j--;  
+    //}  
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization of inputB pointer */
+    pIn2 = pSrcA;
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen-2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] */
+      sum += *px++ * *py++;
+      /* x[1] * y[srcBLen - 3] */
+      sum += *px++ * *py++;
+      /* x[2] * y[srcBLen - 2] */
+      sum += *px++ * *py++;
+      /* x[3] * y[srcBLen - 1] */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      /* x[0] * y[srcBLen - 1] */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0.0f;
+      acc1 = 0.0f;
+      acc2 = 0.0f;
+      acc3 = 0.0f;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *(py++);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[0] */
+        acc0 += x0 * c0;
+        /* acc1 +=  x[1] * y[0] */
+        acc1 += x1 * c0;
+        /* acc2 +=  x[2] * y[0] */
+        acc2 += x2 * c0;
+        /* acc3 +=  x[3] * y[0] */
+        acc3 += x3 * c0;
+
+        /* Read y[1] sample */
+        c0 = *(py++);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[1] * y[1] */
+        acc0 += x1 * c0;
+        /* acc1 +=  x[2] * y[1] */
+        acc1 += x2 * c0;
+        /* acc2 +=  x[3] * y[1] */
+        acc2 += x3 * c0;
+        /* acc3 +=  x[4] * y[1] */
+        acc3 += x0 * c0;
+
+        /* Read y[2] sample */
+        c0 = *(py++);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[2] */
+        acc0 += x2 * c0;
+        /* acc1 +=  x[3] * y[2] */
+        acc1 += x3 * c0;
+        /* acc2 +=  x[4] * y[2] */
+        acc2 += x0 * c0;
+        /* acc3 +=  x[5] * y[2] */
+        acc3 += x1 * c0;
+
+        /* Read y[3] sample */
+        c0 = *(py++);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[3] */
+        acc0 += x3 * c0;
+        /* acc1 +=  x[4] * y[3] */
+        acc1 += x0 * c0;
+        /* acc2 +=  x[5] * y[3] */
+        acc2 += x1 * c0;
+        /* acc3 +=  x[6] * y[3] */
+        acc3 += x2 * c0;
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[4] sample */
+        c0 = *(py++);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 += x0 * c0;
+        /* acc1 +=  x[5] * y[4] */
+        acc1 += x1 * c0;
+        /* acc2 +=  x[6] * y[4] */
+        acc2 += x2 * c0;
+        /* acc3 +=  x[7] * y[4] */
+        acc3 += x3 * c0;
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = acc0;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = acc1;
+      pOut += inc;
+
+      *pOut = acc2;
+      pOut += inc;
+
+      *pOut = acc3;
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += *px++ * *py++;
+        sum += *px++ * *py++;
+        sum += *px++ * *py++;
+        sum += *px++ * *py++;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py++;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0.0f;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *px++ * *py++;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0.0f;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum += *px++ * *py++;
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum += *px++ * *py++;
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum += *px++ * *py++;
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += *px++ * *py++;
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pIn1 = pSrcA;                       /* inputA pointer */
+  float32_t *pIn2 = pSrcB + (srcBLen - 1u);      /* inputB pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i = 0u, j;                            /* loop counters */
+  uint32_t inv = 0u;                             /* Reverse order flag */
+  uint32_t tot = 0u;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two   
+   * inputs of same length. But to improve the performance, we include zeroes   
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted  
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2u);
+
+  if(srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if(srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1u);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0.0f;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += pIn1[j] * pIn2[-((int32_t) i - j)];
+      }
+    }
+    /* Store the output in the destination buffer */
+    if(inv == 1)
+      *pDst-- = sum;
+    else
+      *pDst++ = sum;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c
new file mode 100644
index 0000000000..8c2dd0fb24
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c
@@ -0,0 +1,622 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_fast_q15.c   
+*   
+* Description:	Fast Q15 Correlation.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * This fast version uses a 32-bit accumulator with 2.30 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * There is no saturation on intermediate additions.   
+ * Thus, if the accumulator overflows it wraps around and distorts the result.   
+ * The input signals should be scaled down to avoid intermediate overflows.   
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen) to avoid overflow since a   
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.   
+ * The 2.30 accumulator is right shifted by 15 bits and then saturated to 1.15 format to yield the final result.   
+ *   
+ * \par   
+ * See arm_correlate_q15() for a slower implementation of this function which uses a 64-bit accumulator to avoid wrap around distortion.   
+ */
+
+void arm_correlate_fast_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+  q31_t *pb;                                     /* 32 bit pointer for inputB buffer */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first loop starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum = __SMLAD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (sum >> 15);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* Initialize inputB pointer of type q31 */
+  pb = (q31_t *) (py);
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1] samples */
+      x0 = *(q31_t *) (px++);
+      /* read x[1], x[2] samples */
+      x1 = *(q31_t *) (px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the first two inputB samples using SIMD:   
+         * y[0] and y[1] */
+        c0 = *(pb++);
+
+        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
+        acc0 = __SMLAD(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLAD(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *(q31_t *) (px++);
+
+        /* Read x[3], x[4] */
+        x3 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
+        acc2 = __SMLAD(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
+        acc3 = __SMLAD(x3, c0, acc3);
+
+        /* Read y[2] and y[3] */
+        c0 = *(pb++);
+
+        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
+        acc0 = __SMLAD(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
+        acc1 = __SMLAD(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = *(q31_t *) (px++);
+
+        /* Read x[5], x[6] */
+        x1 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
+        acc2 = __SMLAD(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
+        acc3 = __SMLAD(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+      py = (q15_t *) (pb);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[4] */
+        c0 = *py;
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[7] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLADX(x1, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[4], y[5] */
+        c0 = *(pb);
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLAD(x3, c0, acc2);
+        acc3 = __SMLAD(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[4], y[5] */
+        c0 = *pb++;
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLAD(x0, c0, acc0);
+        acc1 = __SMLAD(x1, c0, acc1);
+        acc2 = __SMLAD(x3, c0, acc2);
+        acc3 = __SMLAD(x2, c0, acc3);
+
+        /* Read y[6] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+        c0 = (*pb);
+        c0 = c0 & 0xFFFF0000;
+
+#else
+        c0 = (q15_t) (*pb);
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+
+        /* Read x[10] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLADX(x1, c0, acc0);
+        acc1 = __SMLAD(x2, c0, acc1);
+        acc2 = __SMLADX(x2, c0, acc2);
+        acc3 = __SMLADX(x3, c0, acc3);
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (acc0 >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q15_t) (acc1 >> 15);
+      pOut += inc;
+
+      *pOut = (q15_t) (acc2 >> 15);
+      pOut += inc;
+
+      *pOut = (q15_t) (acc3 >> 15);
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+      pb = (q31_t *) (py);
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (sum >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (sum >> 15);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum = __SMLAD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLAD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (sum >> 15);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c
new file mode 100644
index 0000000000..34cd3f4a49
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c
@@ -0,0 +1,599 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_fast_q31.c   
+*   
+* Description:	Fast Q31 Correlation.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.   
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.   
+ * These intermediate results are accumulated in a 32-bit register in 2.30 format.   
+ * Finally, the accumulator is saturated and converted to a 1.31 result.   
+ *   
+ * \par   
+ * The fast version has the same overflow behavior as the standard version but provides less precision since it discards the low 32 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signals must be scaled down.   
+ * The input signals should be scaled down to avoid intermediate overflows.   
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a   
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.   
+ *   
+ * \par   
+ * See arm_correlate_q31() for a slower implementation of this function which uses 64-bit accumulation to provide higher precision.   
+ */
+
+void arm_correlate_fast_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* x[1] * y[srcBLen - 3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* x[2] * y[srcBLen - 2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* x[3] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum << 1;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *(py++);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[0] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc1 +=  x[1] * y[0] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc2 +=  x[2] * y[0] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc3 +=  x[3] * y[0] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Read y[1] sample */
+        c0 = *(py++);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[1] * y[1] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc1 +=  x[2] * y[1] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc2 +=  x[3] * y[1] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc3 +=  x[4] * y[1] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x0 * c0)) >> 32);
+
+        /* Read y[2] sample */
+        c0 = *(py++);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[2] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc1 +=  x[3] * y[2] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc2 +=  x[4] * y[2] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc3 +=  x[5] * y[2] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x1 * c0)) >> 32);
+
+        /* Read y[3] sample */
+        c0 = *(py++);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[3] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x3 * c0)) >> 32);
+        /* acc1 +=  x[4] * y[3] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc2 +=  x[5] * y[3] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc3 +=  x[6] * y[3] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x2 * c0)) >> 32);
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[4] sample */
+        c0 = *(py++);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 = (q31_t) ((((q63_t) acc0 << 32) + ((q63_t) x0 * c0)) >> 32);
+        /* acc1 +=  x[5] * y[4] */
+        acc1 = (q31_t) ((((q63_t) acc1 << 32) + ((q63_t) x1 * c0)) >> 32);
+        /* acc2 +=  x[6] * y[4] */
+        acc2 = (q31_t) ((((q63_t) acc2 << 32) + ((q63_t) x2 * c0)) >> 32);
+        /* acc3 +=  x[7] * y[4] */
+        acc3 = (q31_t) ((((q63_t) acc3 << 32) + ((q63_t) x3 * c0)) >> 32);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (acc0 << 1);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q31_t) (acc1 << 1);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc2 << 1);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc3 << 1);
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum << 1;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum = (q31_t) ((((q63_t) sum << 32) +
+                        ((q63_t) * px++ * (*py++))) >> 32);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = sum << 1;
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = ((pIn1 + srcALen) - srcBLen) + 1u;
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = (q31_t) ((((q63_t) sum << 32) +
+                      ((q63_t) * px++ * (*py++))) >> 32);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = sum << 1;
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c
new file mode 100644
index 0000000000..a10c1bc51b
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c
@@ -0,0 +1,714 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_q15.c   
+*   
+* Description:	Correlation of Q15 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q15 sequences. 
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both inputs are in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * This approach provides 33 guard bits and there is no risk of overflow.   
+ * The 34.30 result is then truncated to 34.15 format by discarding the low 15 bits and then saturated to 1.15 format.   
+ *   
+ * \par   
+ * Refer to arm_correlate_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_correlate_q15(
+  q15_t * pSrcA,
+  uint32_t srcALen,
+  q15_t * pSrcB,
+  uint32_t srcBLen,
+  q15_t * pDst)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn1;                                   /* inputA pointer               */
+  q15_t *pIn2;                                   /* inputB pointer               */
+  q15_t *pOut = pDst;                            /* output pointer               */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q15_t *px;                                     /* Intermediate inputA pointer  */
+  q15_t *py;                                     /* Intermediate inputB pointer  */
+  q15_t *pSrc1;                                  /* Intermediate pointers        */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+  q31_t *pb;                                     /* 32 bit pointer for inputB buffer */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first loop starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] , x[1] * y[srcBLen - 3] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* x[3] * y[srcBLen - 1] , x[2] * y[srcBLen - 2] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum = __SMLALD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (__SSAT((sum >> 15), 16));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* Initialize inputB pointer of type q31 */
+  pb = (q31_t *) (py);
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 0u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4, to loop unroll the srcBLen loop */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1] samples */
+      x0 = *(q31_t *) (px++);
+      /* read x[1], x[2] samples */
+      x1 = *(q31_t *) (px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read the first two inputB samples using SIMD:   
+         * y[0] and y[1] */
+        c0 = *(pb++);
+
+        /* acc0 +=  x[0] * y[0] + x[1] * y[1] */
+        acc0 = __SMLALD(x0, c0, acc0);
+
+        /* acc1 +=  x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLALD(x1, c0, acc1);
+
+        /* Read x[2], x[3] */
+        x2 = *(q31_t *) (px++);
+
+        /* Read x[3], x[4] */
+        x3 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[2] * y[0] + x[3] * y[1] */
+        acc2 = __SMLALD(x2, c0, acc2);
+
+        /* acc3 +=  x[3] * y[0] + x[4] * y[1] */
+        acc3 = __SMLALD(x3, c0, acc3);
+
+        /* Read y[2] and y[3] */
+        c0 = *(pb++);
+
+        /* acc0 +=  x[2] * y[2] + x[3] * y[3] */
+        acc0 = __SMLALD(x2, c0, acc0);
+
+        /* acc1 +=  x[3] * y[2] + x[4] * y[3] */
+        acc1 = __SMLALD(x3, c0, acc1);
+
+        /* Read x[4], x[5] */
+        x0 = *(q31_t *) (px++);
+
+        /* Read x[5], x[6] */
+        x1 = *(q31_t *) (px++);
+
+        /* acc2 +=  x[4] * y[2] + x[5] * y[3] */
+        acc2 = __SMLALD(x0, c0, acc2);
+
+        /* acc3 +=  x[5] * y[2] + x[6] * y[3] */
+        acc3 = __SMLALD(x1, c0, acc3);
+
+      } while(--k);
+
+      /* For the next MAC operations, SIMD is not used   
+       * So, the 16 bit pointer if inputB, py is updated */
+      py = (q15_t *) (pb);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      if(k == 1u)
+      {
+        /* Read y[4] */
+        c0 = *py;
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = c0 << 16u;
+
+#else
+
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+        /* Read x[7] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALDX(x1, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      if(k == 2u)
+      {
+        /* Read y[4], y[5] */
+        c0 = *(pb);
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALD(x3, c0, acc2);
+        acc3 = __SMLALD(x2, c0, acc3);
+      }
+
+      if(k == 3u)
+      {
+        /* Read y[4], y[5] */
+        c0 = *pb++;
+
+        /* Read x[7], x[8] */
+        x3 = *(q31_t *) px++;
+
+        /* Read x[9] */
+        x2 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALD(x0, c0, acc0);
+        acc1 = __SMLALD(x1, c0, acc1);
+        acc2 = __SMLALD(x3, c0, acc2);
+        acc3 = __SMLALD(x2, c0, acc3);
+
+        /* Read y[6] */
+#ifdef  ARM_MATH_BIG_ENDIAN
+
+        c0 = (*pb);
+        c0 = c0 & 0xFFFF0000;
+
+#else
+
+        c0 = (q15_t) (*pb);
+        c0 = c0 & 0x0000FFFF;
+
+#endif /*      #ifdef  ARM_MATH_BIG_ENDIAN     */
+        /* Read x[10] */
+        x3 = *(q31_t *) px++;
+
+        /* Perform the multiply-accumulates */
+        acc0 = __SMLALDX(x1, c0, acc0);
+        acc1 = __SMLALD(x2, c0, acc1);
+        acc2 = __SMLALDX(x2, c0, acc2);
+        acc3 = __SMLALDX(x3, c0, acc3);
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (__SSAT(acc0 >> 15, 16));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q15_t) (__SSAT(acc1 >> 15, 16));
+      pOut += inc;
+
+      *pOut = (q15_t) (__SSAT(acc2 >> 15, 16));
+      pOut += inc;
+
+      *pOut = (q15_t) (__SSAT(acc3 >> 15, 16));
+      pOut += inc;
+
+      /* Increment the count by 4 as 4 output values are computed */
+      count += 4u;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+      pb = (q31_t *) (py);
+
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q63_t) * px++ * *py++);
+        sum += ((q63_t) * px++ * *py++);
+        sum += ((q63_t) * px++ * *py++);
+        sum += ((q63_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q63_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (__SSAT(sum >> 15, 16));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment count by 1, as one output value is computed */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q63_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q15_t) (__SSAT(sum >> 15, 16));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = (pIn1 + srcALen) - (srcBLen - 1u);
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] , sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] , sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum = __SMLALD(*__SIMD32(px)++, *__SIMD32(py)++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum = __SMLALD(*px++, *py++, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q15_t) (__SSAT((sum >> 15), 16));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA;                           /* inputA pointer               */
+  q15_t *pIn2 = pSrcB + (srcBLen - 1u);          /* inputB pointer               */
+  q63_t sum;                                     /* Accumulators                  */
+  uint32_t i = 0u, j;                            /* loop counters */
+  uint32_t inv = 0u;                             /* Reverse order flag */
+  uint32_t tot = 0u;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two   
+   * inputs of same length. But to improve the performance, we include zeroes   
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted  
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2u);
+
+  if(srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if(srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1u);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q31_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+      }
+    }
+    /* Store the output in the destination buffer */
+    if(inv == 1)
+      *pDst-- = (q15_t) __SSAT((sum >> 15u), 16u);
+    else
+      *pDst++ = (q15_t) __SSAT((sum >> 15u), 16u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c
new file mode 100644
index 0000000000..49de78702e
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c
@@ -0,0 +1,683 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_q31.c   
+*   
+* Description:	Correlation of Q31 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q31 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * There is no saturation on intermediate additions.   
+ * Thus, if the accumulator overflows it wraps around and distorts the result.   
+ * The input signals should be scaled down to avoid intermediate overflows.   
+ * Scale down one of the inputs by 1/min(srcALen, srcBLen)to avoid overflows since a   
+ * maximum of min(srcALen, srcBLen) number of additions is carried internally.   
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.   
+ *   
+ * \par   
+ * See arm_correlate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_correlate_q31(
+  q31_t * pSrcA,
+  uint32_t srcALen,
+  q31_t * pSrcB,
+  uint32_t srcBLen,
+  q31_t * pDst)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1;                                   /* inputA pointer               */
+  q31_t *pIn2;                                   /* inputB pointer               */
+  q31_t *pOut = pDst;                            /* output pointer               */
+  q31_t *px;                                     /* Intermediate inputA pointer  */
+  q31_t *py;                                     /* Intermediate inputB pointer  */
+  q31_t *pSrc1;                                  /* Intermediate pointers        */
+  q63_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t x0, x1, x2, x3, c0;                      /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;                               /* Destination address modifier */
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] * y[srcBLen - 4] */
+      sum += (q63_t) * px++ * (*py++);
+      /* x[1] * y[srcBLen - 3] */
+      sum += (q63_t) * px++ * (*py++);
+      /* x[2] * y[srcBLen - 2] */
+      sum += (q63_t) * px++ * (*py++);
+      /* x[3] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q31_t) (sum >> 31);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *(px++);
+      x1 = *(px++);
+      x2 = *(px++);
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *(py++);
+
+        /* Read x[3] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulate */
+        /* acc0 +=  x[0] * y[0] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[1] * y[0] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[2] * y[0] */
+        acc2 += ((q63_t) x2 * c0);
+        /* acc3 +=  x[3] * y[0] */
+        acc3 += ((q63_t) x3 * c0);
+
+        /* Read y[1] sample */
+        c0 = *(py++);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[1] * y[1] */
+        acc0 += ((q63_t) x1 * c0);
+        /* acc1 +=  x[2] * y[1] */
+        acc1 += ((q63_t) x2 * c0);
+        /* acc2 +=  x[3] * y[1] */
+        acc2 += ((q63_t) x3 * c0);
+        /* acc3 +=  x[4] * y[1] */
+        acc3 += ((q63_t) x0 * c0);
+        /* Read y[2] sample */
+        c0 = *(py++);
+
+        /* Read x[5] sample */
+        x1 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[2] * y[2] */
+        acc0 += ((q63_t) x2 * c0);
+        /* acc1 +=  x[3] * y[2] */
+        acc1 += ((q63_t) x3 * c0);
+        /* acc2 +=  x[4] * y[2] */
+        acc2 += ((q63_t) x0 * c0);
+        /* acc3 +=  x[5] * y[2] */
+        acc3 += ((q63_t) x1 * c0);
+
+        /* Read y[3] sample */
+        c0 = *(py++);
+
+        /* Read x[6] sample */
+        x2 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[3] * y[3] */
+        acc0 += ((q63_t) x3 * c0);
+        /* acc1 +=  x[4] * y[3] */
+        acc1 += ((q63_t) x0 * c0);
+        /* acc2 +=  x[5] * y[3] */
+        acc2 += ((q63_t) x1 * c0);
+        /* acc3 +=  x[6] * y[3] */
+        acc3 += ((q63_t) x2 * c0);
+
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[4] sample */
+        c0 = *(py++);
+
+        /* Read x[7] sample */
+        x3 = *(px++);
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 += ((q63_t) x0 * c0);
+        /* acc1 +=  x[5] * y[4] */
+        acc1 += ((q63_t) x1 * c0);
+        /* acc2 +=  x[6] * y[4] */
+        acc2 += ((q63_t) x2 * c0);
+        /* acc3 +=  x[7] * y[4] */
+        acc3 += ((q63_t) x3 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (acc0 >> 31);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q31_t) (acc1 >> 31);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc2 >> 31);
+      pOut += inc;
+
+      *pOut = (q31_t) (acc3 >> 31);
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += (q63_t) * px++ * (*py++);
+        sum += (q63_t) * px++ * (*py++);
+        sum += (q63_t) * px++ * (*py++);
+        sum += (q63_t) * px++ * (*py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (sum >> 31);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) * px++ * (*py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q31_t) (sum >> 31);
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum += (q63_t) * px++ * (*py++);
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      sum += (q63_t) * px++ * (*py++);
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum += (q63_t) * px++ * (*py++);
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += (q63_t) * px++ * (*py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q31_t) (sum >> 31);
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pIn1 = pSrcA;                           /* inputA pointer               */
+  q31_t *pIn2 = pSrcB + (srcBLen - 1u);          /* inputB pointer               */
+  q63_t sum;                                     /* Accumulators                  */
+  uint32_t i = 0u, j;                            /* loop counters */
+  uint32_t inv = 0u;                             /* Reverse order flag */
+  uint32_t tot = 0u;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two   
+   * inputs of same length. But to improve the performance, we include zeroes   
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted  
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2u);
+
+  if(srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if(srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1u);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q63_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+      }
+    }
+    /* Store the output in the destination buffer */
+    if(inv == 1)
+      *pDst-- = (q31_t) (sum >> 31u);
+    else
+      *pDst++ = (q31_t) (sum >> 31u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c
new file mode 100644
index 0000000000..873b5424f0
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c
@@ -0,0 +1,780 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_correlate_q7.c   
+*   
+* Description:	Correlation of Q7 sequences. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup Corr   
+ * @{   
+ */
+
+/**   
+ * @brief Correlation of Q7 sequences.   
+ * @param[in] *pSrcA points to the first input sequence.   
+ * @param[in] srcALen length of the first input sequence.   
+ * @param[in] *pSrcB points to the second input sequence.   
+ * @param[in] srcBLen length of the second input sequence.   
+ * @param[out] *pDst points to the location where the output result is written.  Length 2 * max(srcALen, srcBLen) - 1.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.   
+ * Both the inputs are represented in 1.7 format and multiplications yield a 2.14 result.   
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   
+ * This approach provides 17 guard bits and there is no risk of overflow as long as max(srcALen, srcBLen)<131072.   
+ * The 18.14 result is then truncated to 18.7 format by discarding the low 7 bits and saturated to 1.7 format.   
+ */
+
+void arm_correlate_q7(
+  q7_t * pSrcA,
+  uint32_t srcALen,
+  q7_t * pSrcB,
+  uint32_t srcBLen,
+  q7_t * pDst)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pIn1;                                    /* inputA pointer               */
+  q7_t *pIn2;                                    /* inputB pointer               */
+  q7_t *pOut = pDst;                             /* output pointer               */
+  q7_t *px;                                      /* Intermediate inputA pointer  */
+  q7_t *py;                                      /* Intermediate inputB pointer  */
+  q7_t *pSrc1;                                   /* Intermediate pointers        */
+  q31_t sum, acc0, acc1, acc2, acc3;             /* Accumulators                  */
+  q31_t input1, input2;                          /* temporary variables */
+  q15_t in1, in2;                                /* temporary variables */
+  q7_t x0, x1, x2, x3, c0, c1;                   /* temporary variables for holding input and coefficient values */
+  uint32_t j, k = 0u, count, blkCnt, outBlockSize, blockSize1, blockSize2, blockSize3;  /* loop counter                 */
+  int32_t inc = 1;
+
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and the destination pointer modifier, inc is set to -1 */
+  /* If srcALen > srcBLen, zero pad has to be done to srcB to make the two inputs of same length */
+  /* But to improve the performance,   
+   * we include zeroes in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the starting of the output buffer */
+  /* If srcALen < srcBLen,   
+   * (srcALen - srcBLen) zeroes has to included in the ending of the output buffer */
+  if(srcALen >= srcBLen)
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcA);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcB);
+
+    /* Number of output samples is calculated */
+    outBlockSize = (2u * srcALen) - 1u;
+
+    /* When srcALen > srcBLen, zero padding is done to srcB   
+     * to make their lengths equal.   
+     * Instead, (outBlockSize - (srcALen + srcBLen - 1))   
+     * number of output samples are made zero */
+    j = outBlockSize - (srcALen + (srcBLen - 1u));
+
+    /* Updating the pointer position to non zero value */
+    pOut += j;
+
+  }
+  else
+  {
+    /* Initialization of inputA pointer */
+    pIn1 = (pSrcB);
+
+    /* Initialization of inputB pointer */
+    pIn2 = (pSrcA);
+
+    /* srcBLen is always considered as shorter or equal to srcALen */
+    j = srcBLen;
+    srcBLen = srcALen;
+    srcALen = j;
+
+    /* CORR(x, y) = Reverse order(CORR(y, x)) */
+    /* Hence set the destination pointer to point to the last output sample */
+    pOut = pDst + ((srcALen + srcBLen) - 2u);
+
+    /* Destination address modifier is set to -1 */
+    inc = -1;
+
+  }
+
+  /* The function is internally   
+   * divided into three parts according to the number of multiplications that has to be   
+   * taken place between inputA samples and inputB samples. In the first part of the   
+   * algorithm, the multiplications increase by one for every iteration.   
+   * In the second part of the algorithm, srcBLen number of multiplications are done.   
+   * In the third part of the algorithm, the multiplications decrease by one   
+   * for every iteration.*/
+  /* The algorithm is implemented in three stages.   
+   * The loop counters of each stage is initiated here. */
+  blockSize1 = srcBLen - 1u;
+  blockSize2 = srcALen - (srcBLen - 1u);
+  blockSize3 = blockSize1;
+
+  /* --------------------------   
+   * Initializations of stage1   
+   * -------------------------*/
+
+  /* sum = x[0] * y[srcBlen - 1]   
+   * sum = x[0] * y[srcBlen - 2] + x[1] * y[srcBlen - 1]   
+   * ....   
+   * sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen - 1] * y[srcBLen - 1]   
+   */
+
+  /* In this stage the MAC operations are increased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = 1u;
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  pSrc1 = pIn2 + (srcBLen - 1u);
+  py = pSrc1;
+
+  /* ------------------------   
+   * Stage1 process   
+   * ----------------------*/
+
+  /* The first stage starts here */
+  while(blockSize1 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[0] , x[1] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[srcBLen - 4] , y[srcBLen - 3] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* x[0] * y[srcBLen - 4] */
+      /* x[1] * y[srcBLen - 3] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* x[2] , x[3] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[srcBLen - 2] , y[srcBLen - 1] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* x[2] * y[srcBLen - 2] */
+      /* x[3] * y[srcBLen - 1] */
+      sum = __SMLAD(input1, input2, sum);
+
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      /* x[0] * y[srcBLen - 1] */
+      sum += (q31_t) ((q15_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    py = pSrc1 - count;
+    px = pIn1;
+
+    /* Increment the MAC count */
+    count++;
+
+    /* Decrement the loop counter */
+    blockSize1--;
+  }
+
+  /* --------------------------   
+   * Initializations of stage2   
+   * ------------------------*/
+
+  /* sum = x[0] * y[0] + x[1] * y[1] +...+ x[srcBLen-1] * y[srcBLen-1]   
+   * sum = x[1] * y[0] + x[2] * y[1] +...+ x[srcBLen] * y[srcBLen-1]   
+   * ....   
+   * sum = x[srcALen-srcBLen-2] * y[0] + x[srcALen-srcBLen-1] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   */
+
+  /* Working pointer of inputA */
+  px = pIn1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* count is index by which the pointer pIn1 to be incremented */
+  count = 1u;
+
+  /* -------------------   
+   * Stage2 process   
+   * ------------------*/
+
+  /* Stage2 depends on srcBLen as in this stage srcBLen number of MACS are performed.   
+   * So, to loop unroll over blockSize2,   
+   * srcBLen should be greater than or equal to 4 */
+  if(srcBLen >= 4u)
+  {
+    /* Loop unroll over blockSize2, by 4 */
+    blkCnt = blockSize2 >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Set all accumulators to zero */
+      acc0 = 0;
+      acc1 = 0;
+      acc2 = 0;
+      acc3 = 0;
+
+      /* read x[0], x[1], x[2] samples */
+      x0 = *px++;
+      x1 = *px++;
+      x2 = *px++;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      do
+      {
+        /* Read y[0] sample */
+        c0 = *py++;
+        /* Read y[1] sample */
+        c1 = *py++;
+
+        /* Read x[3] sample */
+        x3 = *px++;
+
+        /* x[0] and x[1] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[0] and y[1] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc0 += x[0] * y[0] + x[1] * y[1]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[1] and x[2] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc1 += x[1] * y[0] + x[2] * y[1] */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc2 += x[2] * y[0] + x[3] * y[1]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[4] sample */
+        x0 = *(px++);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc3 += x[3] * y[0] + x[4] * y[1]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+        /* Read y[2] sample */
+        c0 = *py++;
+        /* Read y[3] sample */
+        c1 = *py++;
+
+        /* Read x[5] sample */
+        x1 = *px++;
+
+        /* x[2] and x[3] are packed */
+        in1 = (q15_t) x2;
+        in2 = (q15_t) x3;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* y[2] and y[3] are packed */
+        in1 = (q15_t) c0;
+        in2 = (q15_t) c1;
+
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc0 += x[2] * y[2] + x[3] * y[3]  */
+        acc0 = __SMLAD(input1, input2, acc0);
+
+        /* x[3] and x[4] are packed */
+        in1 = (q15_t) x3;
+        in2 = (q15_t) x0;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc1 += x[3] * y[2] + x[4] * y[3]  */
+        acc1 = __SMLAD(input1, input2, acc1);
+
+        /* x[4] and x[5] are packed */
+        in1 = (q15_t) x0;
+        in2 = (q15_t) x1;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc2 += x[4] * y[2] + x[5] * y[3]  */
+        acc2 = __SMLAD(input1, input2, acc2);
+
+        /* Read x[6] sample */
+        x2 = *px++;
+
+        /* x[5] and x[6] are packed */
+        in1 = (q15_t) x1;
+        in2 = (q15_t) x2;
+
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* acc3 += x[5] * y[2] + x[6] * y[3]  */
+        acc3 = __SMLAD(input1, input2, acc3);
+
+      } while(--k);
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Read y[4] sample */
+        c0 = *py++;
+
+        /* Read x[7] sample */
+        x3 = *px++;
+
+        /* Perform the multiply-accumulates */
+        /* acc0 +=  x[4] * y[4] */
+        acc0 += ((q15_t) x0 * c0);
+        /* acc1 +=  x[5] * y[4] */
+        acc1 += ((q15_t) x1 * c0);
+        /* acc2 +=  x[6] * y[4] */
+        acc2 += ((q15_t) x2 * c0);
+        /* acc3 +=  x[7] * y[4] */
+        acc3 += ((q15_t) x3 * c0);
+
+        /* Reuse the present samples for the next MAC */
+        x0 = x1;
+        x1 = x2;
+        x2 = x3;
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q7_t) (__SSAT(acc0 >> 7, 8));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      *pOut = (q7_t) (__SSAT(acc1 >> 7, 8));
+      pOut += inc;
+
+      *pOut = (q7_t) (__SSAT(acc2 >> 7, 8));
+      pOut += inc;
+
+      *pOut = (q7_t) (__SSAT(acc3 >> 7, 8));
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + (count * 4u);
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize2 is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = blockSize2 % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Apply loop unrolling and compute 4 MACs simultaneously. */
+      k = srcBLen >> 2u;
+
+      /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+       ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+      while(k > 0u)
+      {
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py++;
+        in2 = (q15_t) * py++;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Reading two inputs of SrcA buffer and packing */
+        in1 = (q15_t) * px++;
+        in2 = (q15_t) * px++;
+        input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Reading two inputs of SrcB buffer and packing */
+        in1 = (q15_t) * py++;
+        in2 = (q15_t) * py++;
+        input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+        /* Perform the multiply-accumulates */
+        sum = __SMLAD(input1, input2, sum);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* If the srcBLen is not a multiple of 4, compute any remaining MACs here.   
+       ** No loop unrolling is used. */
+      k = srcBLen % 0x4u;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulates */
+        sum += ((q15_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the pointer pIn1 index, count by 1 */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+  else
+  {
+    /* If the srcBLen is not a multiple of 4,   
+     * the blockSize2 loop cannot be unrolled by 4 */
+    blkCnt = blockSize2;
+
+    while(blkCnt > 0u)
+    {
+      /* Accumulator is made zero for every iteration */
+      sum = 0;
+
+      /* Loop over srcBLen */
+      k = srcBLen;
+
+      while(k > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += ((q15_t) * px++ * *py++);
+
+        /* Decrement the loop counter */
+        k--;
+      }
+
+      /* Store the result in the accumulator in the destination buffer. */
+      *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+      /* Destination pointer is updated according to the address modifier, inc */
+      pOut += inc;
+
+      /* Update the inputA and inputB pointers for next MAC calculation */
+      px = pIn1 + count;
+      py = pIn2;
+
+      /* Increment the MAC count */
+      count++;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+  }
+
+  /* --------------------------   
+   * Initializations of stage3   
+   * -------------------------*/
+
+  /* sum += x[srcALen-srcBLen+1] * y[0] + x[srcALen-srcBLen+2] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * sum += x[srcALen-srcBLen+2] * y[0] + x[srcALen-srcBLen+3] * y[1] +...+ x[srcALen-1] * y[srcBLen-1]   
+   * ....   
+   * sum +=  x[srcALen-2] * y[0] + x[srcALen-1] * y[1]   
+   * sum +=  x[srcALen-1] * y[0]   
+   */
+
+  /* In this stage the MAC operations are decreased by 1 for every iteration.   
+     The count variable holds the number of MAC operations performed */
+  count = srcBLen - 1u;
+
+  /* Working pointer of inputA */
+  pSrc1 = pIn1 + (srcALen - (srcBLen - 1u));
+  px = pSrc1;
+
+  /* Working pointer of inputB */
+  py = pIn2;
+
+  /* -------------------   
+   * Stage3 process   
+   * ------------------*/
+
+  while(blockSize3 > 0u)
+  {
+    /* Accumulator is made zero for every iteration */
+    sum = 0;
+
+    /* Apply loop unrolling and compute 4 MACs simultaneously. */
+    k = count >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 MACs at a time.   
+     ** a second loop below computes MACs for the remaining 1 to 3 samples. */
+    while(k > 0u)
+    {
+      /* x[srcALen - srcBLen + 1] , x[srcALen - srcBLen + 2]  */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[0] , y[1] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* sum += x[srcALen - srcBLen + 1] * y[0] */
+      /* sum += x[srcALen - srcBLen + 2] * y[1] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* x[srcALen - srcBLen + 3] , x[srcALen - srcBLen + 4] */
+      in1 = (q15_t) * px++;
+      in2 = (q15_t) * px++;
+      input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* y[2] , y[3] */
+      in1 = (q15_t) * py++;
+      in2 = (q15_t) * py++;
+      input2 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+      /* sum += x[srcALen - srcBLen + 3] * y[2] */
+      /* sum += x[srcALen - srcBLen + 4] * y[3] */
+      sum = __SMLAD(input1, input2, sum);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* If the count is not a multiple of 4, compute any remaining MACs here.   
+     ** No loop unrolling is used. */
+    k = count % 0x4u;
+
+    while(k > 0u)
+    {
+      /* Perform the multiply-accumulates */
+      sum += ((q15_t) * px++ * *py++);
+
+      /* Decrement the loop counter */
+      k--;
+    }
+
+    /* Store the result in the accumulator in the destination buffer. */
+    *pOut = (q7_t) (__SSAT(sum >> 7, 8));
+    /* Destination pointer is updated according to the address modifier, inc */
+    pOut += inc;
+
+    /* Update the inputA and inputB pointers for next MAC calculation */
+    px = ++pSrc1;
+    py = pIn2;
+
+    /* Decrement the MAC count */
+    count--;
+
+    /* Decrement the loop counter */
+    blockSize3--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q7_t *pIn1 = pSrcA;                            /* inputA pointer */
+  q7_t *pIn2 = pSrcB + (srcBLen - 1u);           /* inputB pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint32_t i = 0u, j;                            /* loop counters */
+  uint32_t inv = 0u;                             /* Reverse order flag */
+  uint32_t tot = 0u;                             /* Length */
+
+  /* The algorithm implementation is based on the lengths of the inputs. */
+  /* srcB is always made to slide across srcA. */
+  /* So srcBLen is always considered as shorter or equal to srcALen */
+  /* But CORR(x, y) is reverse of CORR(y, x) */
+  /* So, when srcBLen > srcALen, output pointer is made to point to the end of the output buffer */
+  /* and a varaible, inv is set to 1 */
+  /* If lengths are not equal then zero pad has to be done to  make the two   
+   * inputs of same length. But to improve the performance, we include zeroes   
+   * in the output instead of zero padding either of the the inputs*/
+  /* If srcALen > srcBLen, (srcALen - srcBLen) zeroes has to included in the   
+   * starting of the output buffer */
+  /* If srcALen < srcBLen, (srcALen - srcBLen) zeroes has to included in the  
+   * ending of the output buffer */
+  /* Once the zero padding is done the remaining of the output is calcualted  
+   * using convolution but with the shorter signal time shifted. */
+
+  /* Calculate the length of the remaining sequence */
+  tot = ((srcALen + srcBLen) - 2u);
+
+  if(srcALen > srcBLen)
+  {
+    /* Calculating the number of zeros to be padded to the output */
+    j = srcALen - srcBLen;
+
+    /* Initialise the pointer after zero padding */
+    pDst += j;
+  }
+
+  else if(srcALen < srcBLen)
+  {
+    /* Initialization to inputB pointer */
+    pIn1 = pSrcB;
+
+    /* Initialization to the end of inputA pointer */
+    pIn2 = pSrcA + (srcALen - 1u);
+
+    /* Initialisation of the pointer after zero padding */
+    pDst = pDst + tot;
+
+    /* Swapping the lengths */
+    j = srcALen;
+    srcALen = srcBLen;
+    srcBLen = j;
+
+    /* Setting the reverse flag */
+    inv = 1;
+
+  }
+
+  /* Loop to calculate convolution for output length number of times */
+  for (i = 0u; i <= tot; i++)
+  {
+    /* Initialize sum with zero to carry on MAC operations */
+    sum = 0;
+
+    /* Loop to perform MAC operations according to convolution equation */
+    for (j = 0u; j <= i; j++)
+    {
+      /* Check the array limitations */
+      if((((i - j) < srcBLen) && (j < srcALen)))
+      {
+        /* z[i] += x[i-j] * y[j] */
+        sum += ((q15_t) pIn1[j] * pIn2[-((int32_t) i - j)]);
+      }
+    }
+    /* Store the output in the destination buffer */
+    if(inv == 1)
+      *pDst-- = (q7_t) __SSAT((sum >> 7u), 8u);
+    else
+      *pDst++ = (q7_t) __SSAT((sum >> 7u), 8u);
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Corr group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c
new file mode 100644
index 0000000000..c66d3f4c16
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c
@@ -0,0 +1,370 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_decimate_f32.c   
+*   
+* Description:	FIR decimation for floating-point sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup FIR_decimate Finite Impulse Response (FIR) Decimator   
+ *   
+ * These functions combine an FIR filter together with a decimator.   
+ * They are used in multirate systems for reducing the sample rate of a signal without introducing aliasing distortion.   
+ * Conceptually, the functions are equivalent to the block diagram below:   
+ * \image html FIRDecimator.gif "Components included in the FIR Decimator functions"   
+ * When decimating by a factor of M, the signal should be prefiltered by a lowpass filter with a normalized   
+ * cutoff frequency of 1/M in order to prevent aliasing distortion.   
+ * The user of the function is responsible for providing the filter coefficients.   
+ *   
+ * The FIR decimator functions provided in the CMSIS DSP Library combine the FIR filter and the decimator in an efficient manner.   
+ * Instead of calculating all of the FIR filter outputs and discarding M-1 out of every M, only the   
+ * samples output by the decimator are computed.   
+ * The functions operate on blocks of input and output data.   
+ * pSrc points to an array of blockSize input values and   
+ * pDst points to an array of blockSize/M output values.   
+ * In order to have an integer number of output samples blockSize   
+ * must always be a multiple of the decimation factor M.   
+ *   
+ * The library provides separate functions for Q15, Q31 and floating-point data types.   
+ *   
+ * \par Algorithm:   
+ * The FIR portion of the algorithm uses the standard form filter:   
+ * 
       
+ *    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]   
+ * 
       
+ * where, b[n] are the filter coefficients.   
+ * \par  
+ * The pCoeffs points to a coefficient array of size numTaps.   
+ * Coefficients are stored in time reversed order.   
+ * \par   
+ * 
       
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
       
+ * \par   
+ * pState points to a state array of size numTaps + blockSize - 1.   
+ * Samples in the state buffer are stored in the order:   
+ * \par   
+ * 
       
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}   
+ * 
       
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.   
+ *   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ * - Checks to make sure that the size of the input is a multiple of the decimation factor.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * The code below statically initializes each of the 3 different data type filter instance structures   
+ * 
       
+ *arm_fir_decimate_instance_f32 S = {M, numTaps, pCoeffs, pState};   
+ *arm_fir_decimate_instance_q31 S = {M, numTaps, pCoeffs, pState};   
+ *arm_fir_decimate_instance_q15 S = {M, numTaps, pCoeffs, pState};   
+ * 
       
+ * where M is the decimation factor; numTaps is the number of filter coefficients in the filter;   
+ * pCoeffs is the address of the coefficient buffer;   
+ * pState is the address of the state buffer.   
+ * Be sure to set the values in the state buffer to zeros when doing static initialization.   
+ *   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the FIR decimate filter functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+  /**   
+   * @brief Processing function for the floating-point FIR decimator.   
+   * @param[in] *S        points to an instance of the floating-point FIR decimator structure.   
+   * @param[in] *pSrc     points to the block of input data.   
+   * @param[out] *pDst    points to the block of output data.   
+   * @param[in] blockSize number of input samples to process per call.   
+   * @return none.   
+   */
+
+void arm_fir_decimate_f32(
+  const arm_fir_decimate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  float32_t sum0;                                /* Accumulator */
+  float32_t x0, c0;                              /* Temporary variables to hold state and coefficient values */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor   
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = sum0;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += x0 * c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor          
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = sum0;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  i = (numTaps - 1u);
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0        */
+
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
new file mode 100644
index 0000000000..e9bc3c3d1f
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
@@ -0,0 +1,199 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_decimate_fast_q15.c   
+*   
+* Description:	Fast Q15 FIR Decimator.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.   
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * This fast version uses a 32-bit accumulator with 2.30 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.   
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (log2 is read as log to the base 2).   
+ * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.   
+ *   
+ * \par   
+ * Refer to the function arm_fir_decimate_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.   
+ * Both the slow and the fast versions use the same instance structure.   
+ * Use the function arm_fir_decimate_init_q15() to initialize the filter structure.   
+ */
+
+void arm_fir_decimate_fast_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q31_t sum0;                                    /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLAD(x0, c0, sum0);
+
+      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLAD(x0, c0, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLAD(x0, c0, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor   
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* Store filter output , smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) ((sum0 >> 15));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
new file mode 100644
index 0000000000..67d90587ef
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
@@ -0,0 +1,220 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_decimate_fast_q31.c   
+*   
+* Description:	Fast Q31 FIR Decimator.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.   
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none   
+ *   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.   
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.   
+ * These intermediate results are added to a 2.30 accumulator.   
+ * Finally, the accumulator is saturated and converted to a 1.31 result.   
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).   
+ *   
+ * \par   
+ * Refer to the function arm_fir_decimate_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.   
+ * Both the slow and the fast versions use the same instance structure.   
+ * Use the function arm_fir_decimate_init_q31() to initialize the filter structure.   
+ */
+
+void arm_fir_decimate_fast_q31(
+  arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q31_t *px;                                     /* Temporary pointers for state buffer */
+  q31_t *pb;                                     /* Temporary pointers for coefficient buffer */
+  q63_t sum0;                                    /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) x0 * c0) + (sum0 << 32)) >> 32);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) x0 * c0) + (sum0 << 32)) >> 32);
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) x0 * c0) + (sum0 << 32)) >> 32);
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) x0 * c0) + (sum0 << 32)) >> 32);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 = (q31_t) ((((q63_t) x0 * c0) + (sum0 << 32)) >> 32);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor   
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (sum0 << 1);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
new file mode 100644
index 0000000000..c30af4f359
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
@@ -0,0 +1,109 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_decimate_init_f32.c   
+*   
+* Description:  Floating-point FIR Decimator initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the floating-point FIR decimator.   
+ * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.   
+ * @param[in] numTaps  number of coefficients in the filter.   
+ * @param[in] M  decimation factor.   
+ * @param[in] *pCoeffs points to the filter coefficients.   
+ * @param[in] *pState points to the state buffer.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if   
+ * blockSize is not a multiple of M.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
       
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
       
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_f32().   
+ * M is the decimation factor.   
+ */
+
+arm_status arm_fir_decimate_init_f32(
+  arm_fir_decimate_instance_f32 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The size of the input block must be a multiple of the decimation factor */
+  if((blockSize % M) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear state buffer and size is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    /* Assign Decimation Factor */
+    S->M = M;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
new file mode 100644
index 0000000000..24b84c6ac0
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
@@ -0,0 +1,111 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_decimate_init_q15.c   
+*   
+* Description:  Initialization function for the Q15 FIR Decimator.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the Q15 FIR decimator.   
+ * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.   
+ * @param[in] numTaps  number of coefficients in the filter.   
+ * @param[in] M  decimation factor.   
+ * @param[in] *pCoeffs points to the filter coefficients.   
+ * @param[in] *pState points to the state buffer.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if   
+ * blockSize is not a multiple of M.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
       
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
       
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples   
+ * to the call arm_fir_decimate_q15().   
+ * M is the decimation factor.   
+ */
+
+arm_status arm_fir_decimate_init_q15(
+  arm_fir_decimate_instance_q15 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+
+  arm_status status;
+
+  /* The size of the input block must be a multiple of the decimation factor */
+  if((blockSize % M) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear the state buffer.  The size of buffer is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    /* Assign Decimation factor */
+    S->M = M;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
new file mode 100644
index 0000000000..55652126d2
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
@@ -0,0 +1,109 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_decimate_init_q31.c   
+*   
+* Description:  Initialization function for Q31 FIR Decimation filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the Q31 FIR decimator.   
+ * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.   
+ * @param[in] numTaps  number of coefficients in the filter.   
+ * @param[in] M  decimation factor.   
+ * @param[in] *pCoeffs points to the filter coefficients.   
+ * @param[in] *pState points to the state buffer.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return    The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if   
+ * blockSize is not a multiple of M.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
       
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
       
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1 words where blockSize is the number of input samples passed to arm_fir_decimate_q31().   
+ * M is the decimation factor.   
+ */
+
+arm_status arm_fir_decimate_init_q31(
+  arm_fir_decimate_instance_q31 * S,
+  uint16_t numTaps,
+  uint8_t M,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The size of the input block must be a multiple of the decimation factor */
+  if((blockSize % M) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(q31_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    /* Assign Decimation factor */
+    S->M = M;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c
new file mode 100644
index 0000000000..99e91c5b17
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c
@@ -0,0 +1,285 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_decimate_q15.c   
+*   
+* Description:	Q15 FIR Decimator.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 FIR decimator.   
+ * @param[in] *S points to an instance of the Q15 FIR decimator structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the location where the output result is written.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.   
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.   
+ *   
+ * \par   
+ * Refer to the function arm_fir_decimate_fast_q15() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_fir_decimate_q15(
+  const arm_fir_decimate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer coefficient buffer */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q63_t sum0;                                    /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, blkCnt, tapCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the Read b[numTaps-1] and b[numTaps-2]  coefficients */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-1] and x[n-numTaps-2]sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLALD(x0, c0, sum0);
+
+      /* Read the b[numTaps-3] and b[numTaps-4] coefficient */
+      c0 = *__SIMD32(pb)++;
+
+      /* Read x[n-numTaps-2] and x[n-numTaps-3] sample */
+      x0 = *__SIMD32(px)++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLALD(x0, c0, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 = __SMLALD(x0, c0, sum0);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor   
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* Store filter output, smlad returns the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /*Set sum to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q31_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor          
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /*Store filter output , smlad will return the values in 2.14 format */
+    /* so downsacle by 15 to get output in 1.15 */
+    *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = numTaps - 1u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c
new file mode 100644
index 0000000000..227a4ed76b
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c
@@ -0,0 +1,303 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_decimate_q31.c   
+*   
+* Description:	Q31 FIR Decimator.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_decimate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 FIR decimator.   
+ * @param[in] *S points to an instance of the Q31 FIR decimator structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around rather than clip.   
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits (where log2 is read as log to the base 2).   
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.   
+ *   
+ * \par   
+ * Refer to the function arm_fir_decimate_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_fir_decimate_q31(
+  const arm_fir_decimate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  q31_t *px;                                     /* Temporary pointers for state buffer */
+  q31_t *pb;                                     /* Temporary pointers for coefficient buffer */
+  q63_t sum0;                                    /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps */
+  uint32_t i, tapCnt, blkCnt, outBlockSize = blockSize / S->M;  /* Loop counters */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-1] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-2] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor   
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (sum0 >> 31);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = (numTaps - 1u) % 0x04u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Total number of output samples to be computed */
+  blkCnt = outBlockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy decimation factor number of new input samples into the state buffer */
+    i = S->M;
+
+    do
+    {
+      *pStateCurnt++ = *pSrc++;
+
+    } while(--i);
+
+    /* Set accumulator to zero */
+    sum0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *pb++;
+
+      /* Fetch 1 state variable */
+      x0 = *px++;
+
+      /* Perform the multiply-accumulate */
+      sum0 += (q63_t) x0 *c0;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by the decimation factor          
+     * to process the next group of decimation factor number samples */
+    pState = pState + S->M;
+
+    /* The result is in the accumulator, store in the destination buffer. */
+    *pDst++ = (q31_t) (sum0 >> 31);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the start of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = numTaps - 1u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_decimate group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c
new file mode 100644
index 0000000000..8ae71f7964
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c
@@ -0,0 +1,436 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_f32.c   
+*   
+* Description:	Floating-point FIR filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup FIR Finite Impulse Response (FIR) Filters   
+ *   
+ * This set of functions implements Finite Impulse Response (FIR) filters   
+ * for Q7, Q15, Q31, and floating-point data types.   
+ * Fast versions of Q15 and Q31 are also provided on Cortex-M4 and Cortex-M3.   
+ * The functions operate on blocks of input and output data and each call to the function processes   
+ * blockSize samples through the filter.  pSrc and   
+ * pDst points to input and output arrays containing blockSize values.   
+ *   
+ * \par Algorithm:   
+ * The FIR filter algorithm is based upon a sequence of multiply-accumulate (MAC) operations.   
+ * Each filter coefficient b[n] is multiplied by a state variable which equals a previous input sample x[n].   
+ * 
       
+ *    y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]   
+ * 
       
+ * \par   
+ * \image html FIR.gif "Finite Impulse Response filter"   
+ * \par   
+ * pCoeffs points to a coefficient array of size numTaps.   
+ * Coefficients are stored in time reversed order.   
+ * \par   
+ * 
       
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
       
+ * \par   
+ * pState points to a state array of size numTaps + blockSize - 1.   
+ * Samples in the state buffer are stored in the following order.   
+ * \par   
+ * 
       
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}   
+ * 
       
+ * \par   
+ * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1.   
+ * The increased state buffer length allows circular addressing, which is traditionally used in the FIR filters,   
+ * to be avoided and yields a significant speed improvement.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.   
+ * There are separate instance structure declarations for each of the 4 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros before static initialization.   
+ * The code below statically initializes each of the 4 different data type filter instance structures   
+ * 
       
+ *arm_fir_instance_f32 S = {numTaps, pState, pCoeffs};   
+ *arm_fir_instance_q31 S = {numTaps, pState, pCoeffs};   
+ *arm_fir_instance_q15 S = {numTaps, pState, pCoeffs};   
+ *arm_fir_instance_q7 S =  {numTaps, pState, pCoeffs};   
+ * 
       
+ *   
+ * where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;   
+ * pCoeffs is the address of the coefficient buffer.   
+ *   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the FIR filter functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ *   
+ * @param[in]  *S points to an instance of the floating-point FIR filter structure.   
+ * @param[in]  *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in]  blockSize number of samples to process per call.   
+ * @return     none.   
+ *   
+ */
+
+void arm_fir_f32(
+  const arm_fir_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t acc0, acc1, acc2, acc3;              /* Accumulators */
+  float32_t x0, x1, x2, x3, c0;                  /* Temporary variables to hold state and coefficient values */
+
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.   
+   * The variables acc0 ... acc3 hold output values that are being computed:   
+   *   
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]   
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]   
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]   
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]   
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0.0f;
+    acc1 = 0.0f;
+    acc2 = 0.0f;
+    acc3 = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the first three samples from the state buffer:  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+    x0 = *px++;
+    x1 = *px++;
+    x2 = *px++;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2u;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    while(tapCnt > 0u)
+    {
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x3 = *(px++);
+
+      /* acc0 +=  b[numTaps-1] * x[n-numTaps] */
+      acc0 += x0 * c0;
+
+      /* acc1 +=  b[numTaps-1] * x[n-numTaps-1] */
+      acc1 += x1 * c0;
+
+      /* acc2 +=  b[numTaps-1] * x[n-numTaps-2] */
+      acc2 += x2 * c0;
+
+      /* acc3 +=  b[numTaps-1] * x[n-numTaps-3] */
+      acc3 += x3 * c0;
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulate */
+      acc0 += x1 * c0;
+      acc1 += x2 * c0;
+      acc2 += x3 * c0;
+      acc3 += x0 * c0;
+
+      /* Read the b[numTaps-3] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-5] sample */
+      x1 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += x2 * c0;
+      acc1 += x3 * c0;
+      acc2 += x0 * c0;
+      acc3 += x1 * c0;
+
+      /* Read the b[numTaps-4] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-6] sample */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += x3 * c0;
+      acc1 += x0 * c0;
+      acc2 += x1 * c0;
+      acc3 += x2 * c0;
+
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x3 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += x0 * c0;
+      acc1 += x1 * c0;
+      acc2 += x2 * c0;
+      acc3 += x3 * c0;
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+      x2 = x3;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* The results in the 4 accumulators, store in the destination buffer. */
+    *pDst++ = acc0;
+    *pDst++ = acc1;
+    *pDst++ = acc2;
+    *pDst++ = acc3;
+
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      acc0 += *px++ * *pb++;
+      i--;
+
+    } while(i > 0u);
+
+    /* The result is store in the destination buffer. */
+    *pDst++ = acc0;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t acc;
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc = 0.0f;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = pCoeffs;
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += *px++ * *pb++;
+      i--;
+
+    } while(i > 0u);
+
+    /* The result is store in the destination buffer. */
+    *pDst++ = acc;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the starting of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  tapCnt = numTaps - 1u;
+
+  /* Copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c
new file mode 100644
index 0000000000..ed333a7cb2
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c
@@ -0,0 +1,279 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_fast_q15.c   
+*   
+* Description:  Q15 Fast FIR filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.9  2010/08/16    
+*    Initial version   
+*   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @param[in] *S points to an instance of the Q15 FIR filter structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in] blockSize number of samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * This fast version uses a 32-bit accumulator with 2.30 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around and distorts the result.   
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.   
+ * The 2.30 accumulator is then truncated to 2.15 format and saturated to yield the 1.15 result.   
+ *   
+ * \par   
+ * Refer to the function arm_fir_q15() for a slower implementation of this function which uses 64-bit accumulation to avoid wrap around distortion.  Both the slow and the fast versions use the same instance structure.   
+ * Use the function arm_fir_init_q15() to initialize the filter structure.   
+ */
+
+void arm_fir_fast_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px1;                                    /* Temporary q15 pointer for state buffer */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q31_t *px2;                                    /* Temporary q31 pointer for SIMD state buffer accesses */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold SIMD state and coefficient values */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.   
+   * The variables acc0 ... acc3 hold output values that are being computed:   
+   *   
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]   
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]   
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]   
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]   
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer.   
+     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer of type q15 */
+    px1 = pState;
+
+    /* Initialize coeff pointer of type q31 */
+    pb = (q31_t *) (pCoeffs);
+
+    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
+    x0 = *(q31_t *) (px1++);
+
+    /* Read the third and forth samples from the state buffer: x[n-N-1], x[n-N-2] */
+    x1 = *(q31_t *) (px1++);
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    tapCnt = numTaps >> 2;
+    do
+    {
+      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
+      c0 = *(pb++);
+
+      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      acc0 = __SMLAD(x0, c0, acc0);
+
+      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+      acc1 = __SMLAD(x1, c0, acc1);
+
+      /* Read state x[n-N-2], x[n-N-3] */
+      x2 = *(q31_t *) (px1++);
+
+      /* Read state x[n-N-3], x[n-N-4] */
+      x3 = *(q31_t *) (px1++);
+
+      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+      acc2 = __SMLAD(x2, c0, acc2);
+
+      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+      acc3 = __SMLAD(x3, c0, acc3);
+
+      /* Read coefficients b[N-2], b[N-3] */
+      c0 = *(pb++);
+
+      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+      acc0 = __SMLAD(x2, c0, acc0);
+
+      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+      acc1 = __SMLAD(x3, c0, acc1);
+
+      /* Read state x[n-N-4], x[n-N-5] */
+      x0 = *(q31_t *) (px1++);
+
+      /* Read state x[n-N-5], x[n-N-6] */
+      x1 = *(q31_t *) (px1++);
+
+      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+      acc2 = __SMLAD(x0, c0, acc2);
+
+      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+      acc3 = __SMLAD(x1, c0, acc3);
+      tapCnt--;
+
+    }
+    while(tapCnt > 0u);
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps.   
+     ** This is always 2 taps since the filter length is always even. */
+    if((numTaps & 0x3u) != 0u)
+    {
+      /* Read 2 coefficients */
+      c0 = *(pb++);
+      /* Fetch 4 state variables */
+      x2 = *(q31_t *) (px1++);
+      x3 = *(q31_t *) (px1++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = __SMLAD(x0, c0, acc0);
+      acc1 = __SMLAD(x1, c0, acc1);
+      acc2 = __SMLAD(x2, c0, acc2);
+      acc3 = __SMLAD(x3, c0, acc3);
+    }
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.   
+     ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ = __PKHBT((acc0 >> 15), (acc1 >> 15), 16u);
+    *__SIMD32(pDst)++ = __PKHBT((acc2 >> 15), (acc3 >> 15), 16u);
+
+#else
+
+    *__SIMD32(pDst)++ = __PKHBT((acc1 >> 15), (acc0 >> 15), 16u);
+    *__SIMD32(pDst)++ = __PKHBT((acc3 >> 15), (acc2 >> 15), 16u);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+  while(blkCnt > 0u)
+  {
+    /* Copy two samples into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Use SIMD to hold states and coefficients */
+    px2 = (q31_t *) pState;
+    pb = (q31_t *) (pCoeffs);
+    tapCnt = numTaps >> 1;
+
+    do
+    {
+      acc0 = __SMLAD(*px2++, *(pb++), acc0);
+      tapCnt--;
+    }
+    while(tapCnt > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.   
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) ((acc0 >> 15));
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    tapCnt--;
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy remaining data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c
new file mode 100644
index 0000000000..62449352c6
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c
@@ -0,0 +1,303 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_fast_q31.c   
+*   
+* Description:	Processing function for the Q31 Fast FIR filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.9  2010/08/27    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @param[in] *S points to an instance of the Q31 structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block output data.   
+ * @param[in] blockSize number of samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * This function is optimized for speed at the expense of fixed-point precision and overflow protection.   
+ * The result of each 1.31 x 1.31 multiplication is truncated to 2.30 format.   
+ * These intermediate results are added to a 2.30 accumulator.   
+ * Finally, the accumulator is saturated and converted to a 1.31 result.   
+ * The fast version has the same overflow behavior as the standard version and provides less precision since it discards the low 32 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.   
+ *   
+ * \par   
+ * Refer to the function arm_fir_q31() for a slower implementation of this function which uses a 64-bit accumulator to provide higher precision.  Both the slow and the fast versions use the same instance structure.   
+ * Use the function arm_fir_init_q31() to initialize the filter structure.   
+ */
+
+void arm_fir_fast_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t x0, x1, x2, x3;                          /* Temporary variables to hold state */
+  q31_t c0;                                      /* Temporary variable to hold coefficient value */
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.   
+   * The variables acc0 ... acc3 hold output values that are being computed:   
+   *   
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]   
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]   
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]   
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]   
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Read the first three samples from the state buffer:   
+     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+    x0 = *(px++);
+    x1 = *(px++);
+    x2 = *(px++);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+    i = tapCnt;
+
+    while(i > 0u)
+    {
+      /* Read the b[numTaps] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x3 = *(px++);
+
+      /* acc0 +=  b[numTaps] * x[n-numTaps] */
+      acc0 = (q31_t) ((((q63_t) x0 * c0) + (acc0 << 32)) >> 32);
+
+      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */
+      acc1 = (q31_t) ((((q63_t) x1 * c0) + (acc1 << 32)) >> 32);
+
+      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */
+      acc2 = (q31_t) ((((q63_t) x2 * c0) + (acc2 << 32)) >> 32);
+
+      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */
+      acc3 = (q31_t) ((((q63_t) x3 * c0) + (acc3 << 32)) >> 32);
+
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = (q31_t) ((((q63_t) x1 * c0) + (acc0 << 32)) >> 32);
+      acc1 = (q31_t) ((((q63_t) x2 * c0) + (acc1 << 32)) >> 32);
+      acc2 = (q31_t) ((((q63_t) x3 * c0) + (acc2 << 32)) >> 32);
+      acc3 = (q31_t) ((((q63_t) x0 * c0) + (acc3 << 32)) >> 32);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-5] sample */
+      x1 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = (q31_t) ((((q63_t) x2 * c0) + (acc0 << 32)) >> 32);
+      acc1 = (q31_t) ((((q63_t) x3 * c0) + (acc1 << 32)) >> 32);
+      acc2 = (q31_t) ((((q63_t) x0 * c0) + (acc2 << 32)) >> 32);
+      acc3 = (q31_t) ((((q63_t) x1 * c0) + (acc3 << 32)) >> 32);
+
+      /* Read the b[numTaps-3] coefficients */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-6] sample */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = (q31_t) ((((q63_t) x3 * c0) + (acc0 << 32)) >> 32);
+      acc1 = (q31_t) ((((q63_t) x0 * c0) + (acc1 << 32)) >> 32);
+      acc2 = (q31_t) ((((q63_t) x1 * c0) + (acc2 << 32)) >> 32);
+      acc3 = (q31_t) ((((q63_t) x2 * c0) + (acc3 << 32)) >> 32);
+      i--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+    i = numTaps - (tapCnt * 4u);
+    while(i > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x3 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = (q31_t) ((((q63_t) x0 * c0) + (acc0 << 32)) >> 32);
+      acc1 = (q31_t) ((((q63_t) x1 * c0) + (acc1 << 32)) >> 32);
+      acc2 = (q31_t) ((((q63_t) x2 * c0) + (acc2 << 32)) >> 32);
+      acc3 = (q31_t) ((((q63_t) x3 * c0) + (acc3 << 32)) >> 32);
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+      x2 = x3;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.31   
+     ** Then store the 4 outputs in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 << 1);
+    *pDst++ = (q31_t) (acc1 << 1);
+    *pDst++ = (q31_t) (acc2 << 1);
+    *pDst++ = (q31_t) (acc3 << 1);
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      acc0 = (q31_t) ((((q63_t) * (px++) * (*(pb++))) + (acc0 << 32)) >> 32);
+      i--;
+    } while(i > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.31   
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 << 1);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c
new file mode 100644
index 0000000000..a06ab0523f
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c
@@ -0,0 +1,91 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_init_f32.c   
+*   
+* Description:  Floating-point FIR filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @details   
+ *   
+ * @param[in,out] *S points to an instance of the floating-point FIR filter structure.   
+ * @param[in] 	  numTaps  Number of filter coefficients in the filter.   
+ * @param[in]     *pCoeffs points to the filter coefficients buffer.   
+ * @param[in]     *pState points to the state buffer.   
+ * @param[in] 	  blockSize number of samples that are processed per call.   
+ * @return 		  none.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
       
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
       
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_f32().   
+ */
+
+void arm_fir_init_f32(
+  arm_fir_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and the size of state buffer is (blockSize + numTaps - 1) */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c
new file mode 100644
index 0000000000..a160b83aa9
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c
@@ -0,0 +1,149 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_init_q15.c   
+*   
+* Description:  Q15 FIR filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @param[in,out]  *S points to an instance of the Q15 FIR filter structure.   
+ * @param[in] 	   numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.   
+ * @param[in]      *pCoeffs points to the filter coefficients buffer.   
+ * @param[in]      *pState points to the state buffer.   
+ * @param[in]      blockSize is number of samples processed per call.   
+ * @return The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if   
+ * numTaps is not greater than or equal to 4 and even.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
       
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
       
+ * Note that numTaps must be even and greater than or equal to 4.   
+ * To implement an odd length filter simply increase numTaps by 1 and set the last coefficient to zero.   
+ * For example, to implement a filter with numTaps=3 and coefficients   
+ * 
       
+ *     {0.3, -0.8, 0.3}   
+ * 
       
+ * set numTaps=4 and use the coefficients:   
+ * 
       
+ *     {0.3, -0.8, 0.3, 0}.   
+ * 
       
+ * Similarly, to implement a two point filter   
+ * 
       
+ *     {0.3, -0.3}   
+ * 
       
+ * set numTaps=4 and use the coefficients:   
+ * 
       
+ *     {0.3, -0.3, 0, 0}.   
+ * 
       
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1, where blockSize is the number of input samples processed by each call to arm_fir_q15().   
+ */
+
+arm_status arm_fir_init_q15(
+  arm_fir_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* The Number of filter coefficients in the filter must be even and at least 4 */
+  if((numTaps < 4u) || (numTaps & 0x1u))
+  {
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+  else
+  {
+    /* Assign filter taps */
+    S->numTaps = numTaps;
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+    memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  status = ARM_MATH_SUCCESS;
+
+  return (status);
+
+#endif /*  #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c
new file mode 100644
index 0000000000..c9204946b7
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c
@@ -0,0 +1,91 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_init_q31.c   
+*   
+* Description:	Q31 FIR filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @details   
+ *   
+ * @param[in,out] *S points to an instance of the Q31 FIR filter structure.   
+ * @param[in] 	  numTaps  Number of filter coefficients in the filter.   
+ * @param[in] 	  *pCoeffs points to the filter coefficients buffer.   
+ * @param[in] 	  *pState points to the state buffer.   
+ * @param[in] 	  blockSize number of samples that are processed per call.   
+ * @return        none.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
       
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
       
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q31().   
+ */
+
+void arm_fir_init_q31(
+  arm_fir_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and state array size is (blockSize + numTaps - 1) */
+  memset(pState, 0, (blockSize + ((uint32_t) numTaps - 1u)) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c
new file mode 100644
index 0000000000..e4db89fc1a
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c
@@ -0,0 +1,89 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_init_q7.c   
+*   
+* Description:  Q7 FIR filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* ------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+/**   
+ * @param[in,out] *S points to an instance of the Q7 FIR filter structure.   
+ * @param[in] 	  numTaps  Number of filter coefficients in the filter.   
+ * @param[in] 	  *pCoeffs points to the filter coefficients buffer.   
+ * @param[in]     *pState points to the state buffer.   
+ * @param[in]     blockSize number of samples that are processed per call.   
+ * @return     	  none   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
       
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
       
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_fir_q7().   
+ */
+
+void arm_fir_init_q7(
+  arm_fir_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  uint32_t blockSize)
+{
+
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear the state buffer.  The size is always (blockSize + numTaps - 1) */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q7_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c
new file mode 100644
index 0000000000..adcf4eec04
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c
@@ -0,0 +1,399 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_interpolate_f32.c   
+*   
+* Description:	FIR interpolation for floating-point sequences.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @defgroup FIR_Interpolate Finite Impulse Response (FIR) Interpolator   
+ *   
+ * These functions combine an upsampler (zero stuffer) and an FIR filter.   
+ * They are used in multirate systems for increasing the sample rate of a signal without introducing high frequency images.   
+ * Conceptually, the functions are equivalent to the block diagram below:   
+ * \image html FIRInterpolator.gif "Components included in the FIR Interpolator functions"   
+ * After upsampling by a factor of L, the signal should be filtered by a lowpass filter with a normalized   
+ * cutoff frequency of 1/L in order to eliminate high frequency copies of the spectrum.   
+ * The user of the function is responsible for providing the filter coefficients.   
+ *   
+ * The FIR interpolator functions provided in the CMSIS DSP Library combine the upsampler and FIR filter in an efficient manner.   
+ * The upsampler inserts L-1 zeros between each sample.   
+ * Instead of multiplying by these zero values, the FIR filter is designed to skip them.   
+ * This leads to an efficient implementation without any wasted effort.   
+ * The functions operate on blocks of input and output data.   
+ * pSrc points to an array of blockSize input values and   
+ * pDst points to an array of blockSize*L output values.   
+ *   
+ * The library provides separate functions for Q15, Q31, and floating-point data types.   
+ *   
+ * \par Algorithm:   
+ * The functions use a polyphase filter structure:   
+ * 
       
+ *    y[n] = b[0] * x[n] + b[L]   * x[n-1] + ... + b[L*(phaseLength-1)] * x[n-phaseLength+1]   
+ *    y[n+1] = b[1] * x[n] + b[L+1] * x[n-1] + ... + b[L*(phaseLength-1)+1] * x[n-phaseLength+1]   
+ *    ...   
+ *    y[n+(L-1)] = b[L-1] * x[n] + b[2*L-1] * x[n-1] + ....+ b[L*(phaseLength-1)+(L-1)] * x[n-phaseLength+1]   
+ * 
       
+ * This approach is more efficient than straightforward upsample-then-filter algorithms.   
+ * With this method the computation is reduced by a factor of 1/L when compared to using a standard FIR filter.   
+ * \par   
+ * pCoeffs points to a coefficient array of size numTaps.   
+ * numTaps must be a multiple of the interpolation factor L and this is checked by the   
+ * initialization functions.   
+ * Internally, the function divides the FIR filter's impulse response into shorter filters of length   
+ * phaseLength=numTaps/L.   
+ * Coefficients are stored in time reversed order.   
+ * \par   
+ * 
       
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
       
+ * \par   
+ * pState points to a state array of size blockSize + phaseLength - 1.   
+ * Samples in the state buffer are stored in the order:   
+ * \par   
+ * 
       
+ *    {x[n-phaseLength+1], x[n-phaseLength], x[n-phaseLength-1], x[n-phaseLength-2]....x[0], x[1], ..., x[blockSize-1]}   
+ * 
       
+ * The state variables are updated after each block of data is processed, the coefficients are untouched.   
+ *   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable array should be allocated separately.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ * - Checks to make sure that the length of the filter is a multiple of the interpolation factor.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * The code below statically initializes each of the 3 different data type filter instance structures   
+ * 
       
+ * arm_fir_interpolate_instance_f32 S = {L, phaseLength, pCoeffs, pState};   
+ * arm_fir_interpolate_instance_q31 S = {L, phaseLength, pCoeffs, pState};   
+ * arm_fir_interpolate_instance_q15 S = {L, phaseLength, pCoeffs, pState};   
+ * 
       
+ * where L is the interpolation factor; phaseLength=numTaps/L is the   
+ * length of each of the shorter FIR filters used internally,   
+ * pCoeffs is the address of the coefficient buffer;   
+ * pState is the address of the state buffer.   
+ * Be sure to set the values in the state buffer to zeros when doing static initialization.   
+ *   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the FIR interpolate filter functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/**   
+ * @addtogroup FIR_Interpolate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the floating-point FIR interpolator.   
+ * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.   
+ * @param[in] *pSrc     points to the block of input data.   
+ * @param[out] *pDst    points to the block of output data.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none.   
+ */
+
+void arm_fir_interpolate_f32(
+  const arm_fir_interpolate_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *ptr1, *ptr2;                        /* Temporary pointers for state and coefficient buffers */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t sum0;                                /* Accumulators */
+  float32_t x0, c0;                              /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, j;                         /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1u);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum0 = 0.0f;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.   
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2u;
+      while(tapCnt > 0u)
+      {
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.   
+         * So instead of multiplying zeros with coefficients,   
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += x0 * c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen % 0x4u;
+
+      while(tapCnt > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum0 += *(ptr1++) * (*ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = sum0;
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1   
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (phaseLen - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  tapCnt = (phaseLen - 1u) % 0x04u;
+
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t sum;                                 /* Accumulator */
+  uint32_t i, blkCnt;                            /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1u);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum = 0.0f;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (i - 1u);
+
+      /* Loop over the polyPhase length */
+      tapCnt = phaseLen;
+
+      while(tapCnt > 0u)
+      {
+        /* Perform the multiply-accumulate */
+        sum += *ptr1++ * *ptr2;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = sum;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1          
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last phaseLen - 1 samples to the start of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = phaseLen - 1u;
+
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+ /**   
+  * @} end of FIR_Interpolate group   
+  */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
new file mode 100644
index 0000000000..bfdc734bdc
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
@@ -0,0 +1,113 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_interpolate_init_f32.c   
+*   
+* Description:  Floating-point FIR interpolator initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Interpolate   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the floating-point FIR interpolator.   
+ * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.   
+ * @param[in]     L         upsample factor.   
+ * @param[in]     numTaps   number of filter coefficients in the filter.   
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.   
+ * @param[in]     *pState   points to the state buffer.   
+ * @param[in]     blockSize number of input samples to process per call.   
+ * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if   
+ * the filter length numTaps is not a multiple of the interpolation factor L.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
       
+ *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}   
+ * 
       
+ * The length of the filter numTaps must be a multiple of the interpolation factor L.   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length (numTaps/L)+blockSize-1 words   
+ * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_f32().   
+ */
+
+arm_status arm_fir_interpolate_init_f32(
+  arm_fir_interpolate_instance_f32 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The filter length must be a multiple of the interpolation factor */
+  if((numTaps % L) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Assign Interpolation factor */
+    S->L = L;
+
+    /* Assign polyPhaseLength */
+    S->phaseLength = numTaps / L;
+
+    /* Clear state buffer and size of state array is always phaseLength + blockSize - 1 */
+    memset(pState, 0,
+           (blockSize +
+            ((uint32_t) S->phaseLength - 1u)) * sizeof(float32_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+ /**   
+  * @} end of FIR_Interpolate group   
+  */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
new file mode 100644
index 0000000000..3995f73cd3
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
@@ -0,0 +1,112 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_interpolate_init_q15.c   
+*   
+* Description:  Q15 FIR interpolator initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Interpolate   
+ * @{   
+ */
+
+/**   
+ * @brief  Initialization function for the Q15 FIR interpolator.   
+ * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.   
+ * @param[in]     L         upsample factor.   
+ * @param[in]     numTaps   number of filter coefficients in the filter.   
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.   
+ * @param[in]     *pState   points to the state buffer.   
+ * @param[in]     blockSize number of input samples to process per call.   
+ * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if   
+ * the filter length numTaps is not a multiple of the interpolation factor L.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
       
+ *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}   
+ * 
       
+ * The length of the filter numTaps must be a multiple of the interpolation factor L.   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length (numTaps/L)+blockSize-1 words   
+ * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q15().   
+ */
+
+arm_status arm_fir_interpolate_init_q15(
+  arm_fir_interpolate_instance_q15 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The filter length must be a multiple of the interpolation factor */
+  if((numTaps % L) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Assign Interpolation factor */
+    S->L = L;
+
+    /* Assign polyPhaseLength */
+    S->phaseLength = numTaps / L;
+
+    /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+    memset(pState, 0,
+           (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q15_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+ /**   
+  * @} end of FIR_Interpolate group   
+  */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
new file mode 100644
index 0000000000..ade6b071c7
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
@@ -0,0 +1,113 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_interpolate_init_q31.c   
+*   
+* Description:  Q31 FIR interpolator initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Interpolate   
+ * @{   
+ */
+
+
+/**   
+ * @brief  Initialization function for the Q31 FIR interpolator.   
+ * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.   
+ * @param[in]     L         upsample factor.   
+ * @param[in]     numTaps   number of filter coefficients in the filter.   
+ * @param[in]     *pCoeffs  points to the filter coefficient buffer.   
+ * @param[in]     *pState   points to the state buffer.   
+ * @param[in]     blockSize number of input samples to process per call.   
+ * @return        The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_LENGTH_ERROR if   
+ * the filter length numTaps is not a multiple of the interpolation factor L.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
       
+ *    {b[numTaps-1], b[numTaps-2], b[numTaps-2], ..., b[1], b[0]}   
+ * 
       
+ * The length of the filter numTaps must be a multiple of the interpolation factor L.   
+ * \par   
+ * pState points to the array of state variables.   
+ * pState is of length (numTaps/L)+blockSize-1 words   
+ * where blockSize is the number of input samples processed by each call to arm_fir_interpolate_q31().   
+ */
+
+arm_status arm_fir_interpolate_init_q31(
+  arm_fir_interpolate_instance_q31 * S,
+  uint8_t L,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  arm_status status;
+
+  /* The filter length must be a multiple of the interpolation factor */
+  if((numTaps % L) != 0u)
+  {
+    /* Set status as ARM_MATH_LENGTH_ERROR */
+    status = ARM_MATH_LENGTH_ERROR;
+  }
+  else
+  {
+
+    /* Assign coefficient pointer */
+    S->pCoeffs = pCoeffs;
+
+    /* Assign Interpolation factor */
+    S->L = L;
+
+    /* Assign polyPhaseLength */
+    S->phaseLength = numTaps / L;
+
+    /* Clear state buffer and size of buffer is always phaseLength + blockSize - 1 */
+    memset(pState, 0,
+           (blockSize + ((uint32_t) S->phaseLength - 1u)) * sizeof(q31_t));
+
+    /* Assign state pointer */
+    S->pState = pState;
+
+    status = ARM_MATH_SUCCESS;
+  }
+
+  return (status);
+
+}
+
+ /**   
+  * @} end of FIR_Interpolate group   
+  */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c
new file mode 100644
index 0000000000..6403d7f398
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c
@@ -0,0 +1,349 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_fir_interpolate_q15.c   
+*   
+* Description:	Q15 FIR interpolation.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Interpolate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 FIR interpolator.   
+ * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.   
+ * @param[in] *pSrc     points to the block of input data.   
+ * @param[out] *pDst    points to the block of output data.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.   
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.   
+ */
+
+void arm_fir_interpolate_q15(
+  const arm_fir_interpolate_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer                                            */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer                                      */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state                */
+  q15_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers     */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q63_t sum0;                                    /* Accumulators                                             */
+  q15_t x0, c0, c1;                              /* Temporary variables to hold state and coefficient values */
+  q31_t c, x;
+  uint32_t i, blkCnt, j, tapCnt;                 /* Loop counters                                            */
+  uint16_t phaseLen = S->phaseLength;            /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1u);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum0 = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.   
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = (uint32_t) phaseLen >> 2u;
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.   
+         * So instead of multiplying zeros with coefficients,   
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the coefficient */
+        c1 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Pack the coefficients */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+        c = __PKHBT(c0, c1, 16);
+
+#else
+
+        c = __PKHBT(c1, c0, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+        /* Read twp consecutive input samples */
+        x = *__SIMD32(ptr1)++;
+
+        /* Perform the multiply-accumulate */
+        sum0 = __SMLALD(x, c, sum0);
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.   
+         * So insted of multiplying zeros with coefficients,   
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the coefficient */
+        c1 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Pack the coefficients */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+        c = __PKHBT(c0, c1, 16);
+
+#else
+
+        c = __PKHBT(c1, c0, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN            */
+
+        /* Read twp consecutive input samples */
+        x = *__SIMD32(ptr1)++;
+
+        /* Perform the multiply-accumulate */
+        sum0 = __SMLALD(x, c, sum0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = (uint32_t) phaseLen & 0x3u;
+
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 = __SMLALD(x0, c0, sum0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = (q15_t) (__SSAT((sum0 >> 15), 16));
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1   
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = ((uint32_t) phaseLen - 1u) >> 2u;
+
+  /* copy data */
+  while(i > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+  i = ((uint32_t) phaseLen - 1u) % 0x04u;
+
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sum;                                     /* Accumulator */
+  q15_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, tapCnt;                    /* Loop counters                                            */
+  uint16_t phaseLen = S->phaseLength;            /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (phaseLen - 1u);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (i - 1u);
+
+      /* Loop over the polyPhase length */
+      tapCnt = (uint32_t) phaseLen;
+
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *ptr2;
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *ptr1++;
+
+        /* Perform the multiply-accumulate */
+        sum += ((q31_t) x0 * c0);
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* Store the result after converting to 1.15 format in the destination buffer */
+      *pDst++ = (q15_t) (__SSAT((sum >> 15), 16));
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1          
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last phaseLen - 1 samples to the start of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  i = (uint32_t) phaseLen - 1u;
+
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+ /**   
+  * @} end of FIR_Interpolate group   
+  */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c
new file mode 100644
index 0000000000..466dccf1df
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c
@@ -0,0 +1,340 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_fir_interpolate_q31.c   
+*   
+* Description:	Q31 FIR interpolation.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Interpolate   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 FIR interpolator.   
+ * @param[in] *S        points to an instance of the Q31 FIR interpolator structure.   
+ * @param[in] *pSrc     points to the block of input data.   
+ * @param[out] *pDst    points to the block of output data.   
+ * @param[in] blockSize number of input samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around rather than clip.   
+ * In order to avoid overflows completely the input signal must be scaled down by 1/(numTaps/L).   
+ * since numTaps/L additions occur per output sample.   
+ * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format.   
+ */
+
+
+void arm_fir_interpolate_q31(
+  const arm_fir_interpolate_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t *ptr1, *ptr2;                            /* Temporary pointers for state and coefficient buffers */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q63_t sum0;                                    /* Accumulators */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt, j;                         /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Address modifier index of coefficient buffer */
+    j = 1u;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum0 = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (S->L - j);
+
+      /* Loop over the polyPhase length. Unroll by a factor of 4.   
+       ** Repeat until we've computed numTaps-(4*S->L) coefficients. */
+      tapCnt = phaseLen >> 2;
+      while(tapCnt > 0u)
+      {
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Upsampling is done by stuffing L-1 zeros between each sample.   
+         * So instead of multiplying zeros with coefficients,   
+         * Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* If the polyPhase length is not a multiple of 4, compute the remaining filter taps */
+      tapCnt = phaseLen & 0x3u;
+
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *(ptr1++);
+
+        /* Perform the multiply-accumulate */
+        sum0 += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = (q31_t) (sum0 >> 31);
+
+      /* Increment the address modifier index of coefficient buffer */
+      j++;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1   
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (phaseLen - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  tapCnt = (phaseLen - 1u) % 0x04u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sum;                                     /* Accumulator */
+  q31_t x0, c0;                                  /* Temporary variables to hold state and coefficient values */
+  uint32_t i, blkCnt;                            /* Loop counters */
+  uint16_t phaseLen = S->phaseLength, tapCnt;    /* Length of each polyphase filter component */
+
+
+  /* S->pState buffer contains previous frame (phaseLen - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + ((q31_t) phaseLen - 1);
+
+  /* Total number of intput samples */
+  blkCnt = blockSize;
+
+  /* Loop over the blockSize. */
+  while(blkCnt > 0u)
+  {
+    /* Copy new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Loop over the Interpolation factor. */
+    i = S->L;
+
+    while(i > 0u)
+    {
+      /* Set accumulator to zero */
+      sum = 0;
+
+      /* Initialize state pointer */
+      ptr1 = pState;
+
+      /* Initialize coefficient pointer */
+      ptr2 = pCoeffs + (i - 1u);
+
+      tapCnt = phaseLen;
+
+      while(tapCnt > 0u)
+      {
+        /* Read the coefficient */
+        c0 = *(ptr2);
+
+        /* Increment the coefficient pointer by interpolation factor times. */
+        ptr2 += S->L;
+
+        /* Read the input sample */
+        x0 = *ptr1++;
+
+        /* Perform the multiply-accumulate */
+        sum += (q63_t) x0 *c0;
+
+        /* Decrement the loop counter */
+        tapCnt--;
+      }
+
+      /* The result is in the accumulator, store in the destination buffer. */
+      *pDst++ = (q31_t) (sum >> 31);
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 1          
+     * to process the next group of interpolation factor number samples */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last phaseLen - 1 samples to the satrt of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = phaseLen - 1u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+ /**   
+  * @} end of FIR_Interpolate group   
+  */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c
new file mode 100644
index 0000000000..90486acb68
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c
@@ -0,0 +1,496 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_lattice_f32.c   
+*   
+* Description:	Processing function for the floating-point FIR Lattice filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup FIR_Lattice Finite Impulse Response (FIR) Lattice Filters   
+ *   
+ * This set of functions implements Finite Impulse Response (FIR) lattice filters   
+ * for Q15, Q31 and floating-point data types.  Lattice filters are used in a    
+ * variety of adaptive filter applications.  The filter structure is feedforward and   
+ * the net impulse response is finite length.   
+ * The functions operate on blocks   
+ * of input and output data and each call to the function processes   
+ * blockSize samples through the filter.  pSrc and   
+ * pDst point to input and output arrays containing blockSize values.   
+ *   
+ * \par Algorithm:   
+ * \image html FIRLattice.gif "Finite Impulse Response Lattice filter"   
+ * The following difference equation is implemented:   
+ * 
       
+ *    f0[n] = g0[n] = x[n]   
+ *    fm[n] = fm-1[n] + km * gm-1[n-1] for m = 1, 2, ...M   
+ *    gm[n] = km * fm-1[n] + gm-1[n-1] for m = 1, 2, ...M   
+ *    y[n] = fM[n]   
+ * 
       
+ * \par   
+ * pCoeffs points to tha array of reflection coefficients of size numStages.   
+ * Reflection Coefficients are stored in the following order.   
+ * \par   
+ * 
       
+ *    {k1, k2, ..., kM}   
+ * 
       
+ * where M is number of stages   
+ * \par   
+ * pState points to a state array of size numStages.   
+ * The state variables (g values) hold previous inputs and are stored in the following order.   
+ * 
       
+ *    {g0[n], g1[n], g2[n] ...gM-1[n]}   
+ * 
       
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:   
+ * 
       
+ *arm_fir_lattice_instance_f32 S = {numStages, pState, pCoeffs};   
+ *arm_fir_lattice_instance_q31 S = {numStages, pState, pCoeffs};   
+ *arm_fir_lattice_instance_q15 S = {numStages, pState, pCoeffs};   
+ * 
       
+ * \par   
+ * where numStages is the number of stages in the filter; pState is the address of the state buffer;   
+ * pCoeffs is the address of the coefficient buffer.   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the FIR Lattice filter functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/**   
+ * @addtogroup FIR_Lattice   
+ * @{   
+ */
+
+
+  /**   
+   * @brief Processing function for the floating-point FIR lattice filter.   
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.   
+   * @param[in]  *pSrc     points to the block of input data.   
+   * @param[out] *pDst     points to the block of output data   
+   * @param[in]  blockSize number of samples to process.   
+   * @return none.   
+   */
+
+void arm_fir_lattice_f32(
+  const arm_fir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pState;                             /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *px;                                 /* temporary state pointer */
+  float32_t *pk;                                 /* temporary coefficient pointer */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t fcurr1, fnext1, gcurr1, gnext1;      /* temporary variables for first sample in loop unrolling */
+  float32_t fcurr2, fnext2, gnext2;              /* temporary variables for second sample in loop unrolling */
+  float32_t fcurr3, fnext3, gnext3;              /* temporary variables for third sample in loop unrolling */
+  float32_t fcurr4, fnext4, gnext4;              /* temporary variables for fourth sample in loop unrolling */
+  uint32_t numStages = S->numStages;             /* Number of stages in the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  gcurr1 = 0.0f;
+  pState = &S->pState[0];
+
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* Read two samples from input buffer */
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+    fcurr2 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Read g0(n-1) from state */
+    gcurr1 = *px;
+
+    /* Process first sample for first tap */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = fcurr1 + ((*pk) * gcurr1);
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (fcurr1 * (*pk)) + gcurr1;
+
+    /* Process second sample for first tap */
+    /* for sample 2 processing */
+    fnext2 = fcurr2 + ((*pk) * fcurr1);
+    gnext2 = (fcurr2 * (*pk)) + fcurr1;
+
+    /* Read next two samples from input buffer */
+    /* f0(n+2) = x(n+2) */
+    fcurr3 = *pSrc++;
+    fcurr4 = *pSrc++;
+
+    /* Copy only last input samples into the state buffer   
+       which will be used for next four samples processing */
+    *px++ = fcurr4;
+
+    /* Process third sample for first tap */
+    fnext3 = fcurr3 + ((*pk) * fcurr2);
+    gnext3 = (fcurr3 * (*pk)) + fcurr2;
+
+    /* Process fourth sample for first tap */
+    fnext4 = fcurr4 + ((*pk) * fcurr3);
+    gnext4 = (fcurr4 * (*pk++)) + fcurr3;
+
+    /* Update of f values for next coefficient set processing */
+    fcurr1 = fnext1;
+    fcurr2 = fnext2;
+    fcurr3 = fnext3;
+    fcurr4 = fnext4;
+
+    /* Loop unrolling.  Process 4 taps at a time . */
+    stageCnt = (numStages - 1u) >> 2u;
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numStages-3 coefficients. */
+
+    /* Process 2nd, 3rd, 4th and 5th taps ... here */
+    while(stageCnt > 0u)
+    {
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Process first sample for 2nd, 6th .. tap */
+      /* Sample processing for K2, K6.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      /* Process second sample for 2nd, 6th .. tap */
+      /* for sample 2 processing */
+      fnext2 = fcurr2 + ((*pk) * gnext1);
+      /* Process third sample for 2nd, 6th .. tap */
+      fnext3 = fcurr3 + ((*pk) * gnext2);
+      /* Process fourth sample for 2nd, 6th .. tap */
+      fnext4 = fcurr4 + ((*pk) * gnext3);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (fcurr4 * (*pk)) + gnext3;
+      gnext3 = (fcurr3 * (*pk)) + gnext2;
+      gnext2 = (fcurr2 * (*pk)) + gnext1;
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g2(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Sample processing for K3, K7.... */
+      /* Process first sample for 3rd, 7th .. tap */
+      /* f3(n) = f2(n) +  K3 * g2(n-1) */
+      fcurr1 = fnext1 + ((*pk) * gcurr1);
+      /* Process second sample for 3rd, 7th .. tap */
+      fcurr2 = fnext2 + ((*pk) * gnext1);
+      /* Process third sample for 3rd, 7th .. tap */
+      fcurr3 = fnext3 + ((*pk) * gnext2);
+      /* Process fourth sample for 3rd, 7th .. tap */
+      fcurr4 = fnext4 + ((*pk) * gnext3);
+
+      /* Calculation of state values for next stage */
+      /* g3(n) = f2(n) * K3  +  g2(n-1) */
+      gnext4 = (fnext4 * (*pk)) + gnext3;
+      gnext3 = (fnext3 * (*pk)) + gnext2;
+      gnext2 = (fnext2 * (*pk)) + gnext1;
+      gnext1 = (fnext1 * (*pk++)) + gcurr1;
+
+
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g3(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Sample processing for K4, K8.... */
+      /* Process first sample for 4th, 8th .. tap */
+      /* f4(n) = f3(n) +  K4 * g3(n-1) */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      /* Process second sample for 4th, 8th .. tap */
+      /* for sample 2 processing */
+      fnext2 = fcurr2 + ((*pk) * gnext1);
+      /* Process third sample for 4th, 8th .. tap */
+      fnext3 = fcurr3 + ((*pk) * gnext2);
+      /* Process fourth sample for 4th, 8th .. tap */
+      fnext4 = fcurr4 + ((*pk) * gnext3);
+
+      /* g4(n) = f3(n) * K4  +  g3(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (fcurr4 * (*pk)) + gnext3;
+      gnext3 = (fcurr3 * (*pk)) + gnext2;
+      gnext2 = (fcurr2 * (*pk)) + gnext1;
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g4(n) in state buffer */
+      *px++ = gnext4;
+
+      /* Sample processing for K5, K9.... */
+      /* Process first sample for 5th, 9th .. tap */
+      /* f5(n) = f4(n) +  K5 * g4(n-1) */
+      fcurr1 = fnext1 + ((*pk) * gcurr1);
+      /* Process second sample for 5th, 9th .. tap */
+      fcurr2 = fnext2 + ((*pk) * gnext1);
+      /* Process third sample for 5th, 9th .. tap */
+      fcurr3 = fnext3 + ((*pk) * gnext2);
+      /* Process fourth sample for 5th, 9th .. tap */
+      fcurr4 = fnext4 + ((*pk) * gnext3);
+
+      /* Calculation of state values for next stage */
+      /* g5(n) = f4(n) * K5  +  g4(n-1) */
+      gnext4 = (fnext4 * (*pk)) + gnext3;
+      gnext3 = (fnext3 * (*pk)) + gnext2;
+      gnext2 = (fnext2 * (*pk)) + gnext1;
+      gnext1 = (fnext1 * (*pk++)) + gcurr1;
+
+      stageCnt--;
+    }
+
+    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+    stageCnt = (numStages - 1u) % 0x4u;
+
+    while(stageCnt > 0u)
+    {
+      gcurr1 = *px;
+
+      /* save g value in state buffer */
+      *px++ = gnext4;
+
+      /* Process four samples for last three taps here */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      fnext2 = fcurr2 + ((*pk) * gnext1);
+      fnext3 = fcurr3 + ((*pk) * gnext2);
+      fnext4 = fcurr4 + ((*pk) * gnext3);
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      gnext4 = (fcurr4 * (*pk)) + gnext3;
+      gnext3 = (fcurr3 * (*pk)) + gnext2;
+      gnext2 = (fcurr2 * (*pk)) + gnext1;
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+      /* Update of f values for next coefficient set processing */
+      fcurr1 = fnext1;
+      fcurr2 = fnext2;
+      fcurr3 = fnext3;
+      fcurr4 = fnext4;
+
+      stageCnt--;
+
+    }
+
+    /* The results in the 4 accumulators, store in the destination buffer. */
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+    *pDst++ = fcurr2;
+    *pDst++ = fcurr3;
+    *pDst++ = fcurr4;
+
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g2(n) from state buffer */
+    gcurr1 = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = fcurr1 + ((*pk) * gcurr1);
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+    /* save g1(n) in state buffer */
+    *px++ = fcurr1;
+
+    /* f1(n) is saved in fcurr1   
+       for next stage processing */
+    fcurr1 = fnext1;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext1;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = fcurr1 + ((*pk) * gcurr1);
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (fcurr1 * (*pk++)) + gcurr1;
+
+      /* f1(n) is saved in fcurr1   
+         for next stage processing */
+      fcurr1 = fnext1;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+
+    blkCnt--;
+
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t fcurr, fnext, gcurr, gnext;          /* temporary variables */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = pCoeffs;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n-1) from state buffer */
+    gcurr = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext = fcurr + ((*pk) * gcurr);
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext = (fcurr * (*pk++)) + gcurr;
+
+    /* save f0(n) in state buffer */
+    *px++ = fcurr;
+
+    /* f1(n) is saved in fcurr           
+       for next stage processing */
+    fcurr = fnext;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurr = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext = fcurr + ((*pk) * gcurr);
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext = (fcurr * (*pk++)) + gcurr;
+
+      /* f1(n) is saved in fcurr1           
+         for next stage processing */
+      fcurr = fnext;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr;
+
+    blkCnt--;
+
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_Lattice group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
new file mode 100644
index 0000000000..ab8da7fab4
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
@@ -0,0 +1,75 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_lattice_init_f32.c   
+*   
+* Description:  Floating-point FIR Lattice filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Lattice   
+ * @{   
+ */
+
+/**   
+ * @brief Initialization function for the floating-point FIR lattice filter.   
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.   
+ * @param[in] numStages  number of filter stages.   
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.   
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.   
+ * @return none.   
+ */
+
+void arm_fir_lattice_init_f32(
+  arm_fir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pCoeffs,
+  float32_t * pState)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always numStages */
+  memset(pState, 0, (numStages) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Lattice group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
new file mode 100644
index 0000000000..7e34c93ee0
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
@@ -0,0 +1,75 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_lattice_init_q15.c   
+*   
+* Description:  Q15 FIR Lattice filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Lattice   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for the Q15 FIR lattice filter.   
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.   
+   * @param[in] numStages  number of filter stages.   
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.    
+   * @param[in] *pState points to the state buffer.  The array is of length numStages.    
+   * @return none.   
+   */
+
+void arm_fir_lattice_init_q15(
+  arm_fir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pCoeffs,
+  q15_t * pState)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always numStages */
+  memset(pState, 0, (numStages) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Lattice group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
new file mode 100644
index 0000000000..31e32cf18e
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
@@ -0,0 +1,75 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_lattice_init_q31.c   
+*   
+* Description:  Q31 FIR lattice filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Lattice   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for the Q31 FIR lattice filter.   
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.   
+   * @param[in] numStages  number of filter stages.   
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.   
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.   
+   * @return none.   
+   */
+
+void arm_fir_lattice_init_q31(
+  arm_fir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pCoeffs,
+  q31_t * pState)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always numStages */
+  memset(pState, 0, (numStages) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Lattice group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c
new file mode 100644
index 0000000000..350f29d156
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c
@@ -0,0 +1,528 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_lattice_q15.c   
+*   
+* Description:	Q15 FIR lattice filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Lattice   
+ * @{   
+ */
+
+
+/**   
+ * @brief Processing function for the Q15 FIR lattice filter.   
+ * @param[in]  *S        points to an instance of the Q15 FIR lattice structure.   
+ * @param[in]  *pSrc     points to the block of input data.   
+ * @param[out] *pDst     points to the block of output data   
+ * @param[in]  blockSize number of samples to process.   
+ * @return none.   
+ */
+
+void arm_fir_lattice_q15(
+  const arm_fir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState;                                 /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *px;                                     /* temporary state pointer */
+  q15_t *pk;                                     /* temporary coefficient pointer */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t fcurnt1, fnext1, gcurnt1 = 0, gnext1;    /* temporary variables for first sample in loop unrolling */
+  q31_t fcurnt2, fnext2, gnext2;                 /* temporary variables for second sample in loop unrolling */
+  q31_t fcurnt3, fnext3, gnext3;                 /* temporary variables for third sample in loop unrolling */
+  q31_t fcurnt4, fnext4, gnext4;                 /* temporary variables for fourth sample in loop unrolling */
+  uint32_t numStages = S->numStages;             /* Number of stages in the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* Read two samples from input buffer */
+    /* f0(n) = x(n) */
+    fcurnt1 = *pSrc++;
+    fcurnt2 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Read g0(n-1) from state */
+    gcurnt1 = *px;
+
+    /* Process first sample for first tap */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+    fnext1 = __SSAT(fnext1, 16);
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + gcurnt1;
+    gnext1 = __SSAT(gnext1, 16);
+
+    /* Process second sample for first tap */
+    /* for sample 2 processing */
+    fnext2 = (q31_t) ((fcurnt1 * (*pk)) >> 15u) + fcurnt2;
+    fnext2 = __SSAT(fnext2, 16);
+
+    gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt1;
+    gnext2 = __SSAT(gnext2, 16);
+
+
+    /* Read next two samples from input buffer */
+    /* f0(n+2) = x(n+2) */
+    fcurnt3 = *pSrc++;
+    fcurnt4 = *pSrc++;
+
+    /* Copy only last input samples into the state buffer   
+       which is used for next four samples processing */
+    *px++ = (q15_t) fcurnt4;
+
+    /* Process third sample for first tap */
+    fnext3 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + fcurnt3;
+    fnext3 = __SSAT(fnext3, 16);
+    gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt2;
+    gnext3 = __SSAT(gnext3, 16);
+
+    /* Process fourth sample for first tap */
+    fnext4 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + fcurnt4;
+    fnext4 = __SSAT(fnext4, 16);
+    gnext4 = (q31_t) ((fcurnt4 * (*pk++)) >> 15u) + fcurnt3;
+    gnext4 = __SSAT(gnext4, 16);
+
+    /* Update of f values for next coefficient set processing */
+    fcurnt1 = fnext1;
+    fcurnt2 = fnext2;
+    fcurnt3 = fnext3;
+    fcurnt4 = fnext4;
+
+
+    /* Loop unrolling.  Process 4 taps at a time . */
+    stageCnt = (numStages - 1u) >> 2;
+
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numStages-3 coefficients. */
+
+    /* Process 2nd, 3rd, 4th and 5th taps ... here */
+    while(stageCnt > 0u)
+    {
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Process first sample for 2nd, 6th .. tap */
+      /* Sample processing for K2, K6.... */
+      /* f1(n) = f0(n) +  K1 * g0(n-1) */
+      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+
+
+      /* Process second sample for 2nd, 6th .. tap */
+      /* for sample 2 processing */
+      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+      fnext2 = __SSAT(fnext2, 16);
+      /* Process third sample for 2nd, 6th .. tap */
+      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+      fnext3 = __SSAT(fnext3, 16);
+      /* Process fourth sample for 2nd, 6th .. tap */
+      /* fnext4 = fcurnt4 + (*pk) * gnext3; */
+      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+      fnext4 = __SSAT(fnext4, 16);
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+
+      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+
+      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Sample processing for K3, K7.... */
+      /* Process first sample for 3rd, 7th .. tap */
+      /* f3(n) = f2(n) +  K3 * g2(n-1) */
+      fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
+      fcurnt1 = __SSAT(fcurnt1, 16);
+
+      /* Process second sample for 3rd, 7th .. tap */
+      fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
+      fcurnt2 = __SSAT(fcurnt2, 16);
+
+      /* Process third sample for 3rd, 7th .. tap */
+      fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
+      fcurnt3 = __SSAT(fcurnt3, 16);
+
+      /* Process fourth sample for 3rd, 7th .. tap */
+      fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
+      fcurnt4 = __SSAT(fcurnt4, 16);
+
+      /* Calculation of state values for next stage */
+      /* g3(n) = f2(n) * K3  +  g2(n-1) */
+      gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+
+      gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+
+      gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+
+      gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Sample processing for K4, K8.... */
+      /* Process first sample for 4th, 8th .. tap */
+      /* f4(n) = f3(n) +  K4 * g3(n-1) */
+      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+
+      /* Process second sample for 4th, 8th .. tap */
+      /* for sample 2 processing */
+      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+      fnext2 = __SSAT(fnext2, 16);
+
+      /* Process third sample for 4th, 8th .. tap */
+      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+      fnext3 = __SSAT(fnext3, 16);
+
+      /* Process fourth sample for 4th, 8th .. tap */
+      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+      fnext4 = __SSAT(fnext4, 16);
+
+      /* g4(n) = f3(n) * K4  +  g3(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+
+      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+
+      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurnt1 = *px;
+
+      /* save g4(n) in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Sample processing for K5, K9.... */
+      /* Process first sample for 5th, 9th .. tap */
+      /* f5(n) = f4(n) +  K5 * g4(n-1) */
+      fcurnt1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fnext1;
+      fcurnt1 = __SSAT(fcurnt1, 16);
+
+      /* Process second sample for 5th, 9th .. tap */
+      fcurnt2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fnext2;
+      fcurnt2 = __SSAT(fcurnt2, 16);
+
+      /* Process third sample for 5th, 9th .. tap */
+      fcurnt3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fnext3;
+      fcurnt3 = __SSAT(fcurnt3, 16);
+
+      /* Process fourth sample for 5th, 9th .. tap */
+      fcurnt4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fnext4;
+      fcurnt4 = __SSAT(fcurnt4, 16);
+
+      /* Calculation of state values for next stage */
+      /* g5(n) = f4(n) * K5  +  g4(n-1) */
+      gnext4 = (q31_t) ((fnext4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+      gnext3 = (q31_t) ((fnext3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+      gnext2 = (q31_t) ((fnext2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+      gnext1 = (q31_t) ((fnext1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+      stageCnt--;
+    }
+
+    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+    stageCnt = (numStages - 1u) % 0x4u;
+
+    while(stageCnt > 0u)
+    {
+      gcurnt1 = *px;
+
+      /* save g value in state buffer */
+      *px++ = (q15_t) gnext4;
+
+      /* Process four samples for last three taps here */
+      fnext1 = (q31_t) ((gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+      fnext2 = (q31_t) ((gnext1 * (*pk)) >> 15u) + fcurnt2;
+      fnext2 = __SSAT(fnext2, 16);
+
+      fnext3 = (q31_t) ((gnext2 * (*pk)) >> 15u) + fcurnt3;
+      fnext3 = __SSAT(fnext3, 16);
+
+      fnext4 = (q31_t) ((gnext3 * (*pk)) >> 15u) + fcurnt4;
+      fnext4 = __SSAT(fnext4, 16);
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      gnext4 = (q31_t) ((fcurnt4 * (*pk)) >> 15u) + gnext3;
+      gnext4 = __SSAT(gnext4, 16);
+      gnext3 = (q31_t) ((fcurnt3 * (*pk)) >> 15u) + gnext2;
+      gnext3 = __SSAT(gnext3, 16);
+      gnext2 = (q31_t) ((fcurnt2 * (*pk)) >> 15u) + gnext1;
+      gnext2 = __SSAT(gnext2, 16);
+      gnext1 = (q31_t) ((fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+      /* Update of f values for next coefficient set processing */
+      fcurnt1 = fnext1;
+      fcurnt2 = fnext2;
+      fcurnt3 = fnext3;
+      fcurnt4 = fnext4;
+
+      stageCnt--;
+
+    }
+
+    /* The results in the 4 accumulators, store in the destination buffer. */
+    /* y(n) = fN(n) */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt1, fcurnt2, 16);
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt3, fcurnt4, 16);
+
+#else
+
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt2, fcurnt1, 16);
+    *__SIMD32(pDst)++ = __PKHBT(fcurnt4, fcurnt3, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurnt1 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g2(n) from state buffer */
+    gcurnt1 = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+    fnext1 = __SSAT(fnext1, 16);
+
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+    gnext1 = __SSAT(gnext1, 16);
+
+    /* save g1(n) in state buffer */
+    *px++ = (q15_t) fcurnt1;
+
+    /* f1(n) is saved in fcurnt1   
+       for next stage processing */
+    fcurnt1 = fnext1;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurnt1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q15_t) gnext1;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = (((q31_t) gcurnt1 * (*pk)) >> 15u) + fcurnt1;
+      fnext1 = __SSAT(fnext1, 16);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (((q31_t) fcurnt1 * (*pk++)) >> 15u) + gcurnt1;
+      gnext1 = __SSAT(gnext1, 16);
+
+
+      /* f1(n) is saved in fcurnt1   
+         for next stage processing */
+      fcurnt1 = fnext1;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = __SSAT(fcurnt1, 16);
+
+
+    blkCnt--;
+
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t fcurnt, fnext, gcurnt, gnext;            /* temporary variables */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurnt = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n-1) from state buffer */
+    gcurnt = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
+    fnext = __SSAT(fnext, 16);
+
+
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
+    gnext = __SSAT(gnext, 16);
+
+    /* save f0(n) in state buffer */
+    *px++ = (q15_t) fcurnt;
+
+    /* f1(n) is saved in fcurnt           
+       for next stage processing */
+    fcurnt = fnext;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g1(n-1) from state buffer */
+      gcurnt = *px;
+
+      /* save g0(n-1) in state buffer */
+      *px++ = (q15_t) gnext;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext = ((gcurnt * (*pk)) >> 15u) + fcurnt;
+      fnext = __SSAT(fnext, 16);
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext = ((fcurnt * (*pk++)) >> 15u) + gcurnt;
+      gnext = __SSAT(gnext, 16);
+
+
+      /* f1(n) is saved in fcurnt           
+         for next stage processing */
+      fcurnt = fnext;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = __SSAT(fcurnt, 16);
+
+
+    blkCnt--;
+
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_Lattice group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c
new file mode 100644
index 0000000000..2f4c22a506
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c
@@ -0,0 +1,440 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_lattice_q31.c   
+*   
+* Description:	Q31 FIR lattice filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Lattice   
+ * @{   
+ */
+
+
+/**   
+ * @brief Processing function for the Q31 FIR lattice filter.   
+ * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.   
+ * @param[in]  *pSrc     points to the block of input data.   
+ * @param[out] *pDst     points to the block of output data   
+ * @param[in]  blockSize number of samples to process.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * In order to avoid overflows the input signal must be scaled down by 2*log2(numStages) bits.   
+ */
+
+void arm_fir_lattice_q31(
+  const arm_fir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState;                                 /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *px;                                     /* temporary state pointer */
+  q31_t *pk;                                     /* temporary coefficient pointer */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t fcurr1, fnext1, gcurr1 = 0, gnext1;      /* temporary variables for first sample in loop unrolling */
+  q63_t fcurr2, fnext2, gnext2;                  /* temporary variables for second sample in loop unrolling */
+  q63_t fcurr3, fnext3, gnext3;                  /* temporary variables for third sample in loop unrolling */
+  q63_t fcurr4, fnext4, gnext4;                  /* temporary variables for fourth sample in loop unrolling */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+    /* Read two samples from input buffer */
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+    /* f0(n) = x(n) */
+    fcurr2 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Read g0(n-1) from state */
+    gcurr1 = *px;
+
+    /* Process first sample for first tap */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fcurr1;
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 31) + gcurr1;
+
+    /* Process second sample for first tap */
+    /* for sample 2 processing */
+    fnext2 = (q31_t) (((q63_t) fcurr1 * (*pk)) >> 31) + fcurr2;
+    gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 31) + fcurr1;
+
+
+    /* Read next two samples from input buffer */
+    /* f0(n+2) = x(n+2) */
+    fcurr3 = *pSrc++;
+    fcurr4 = *pSrc++;
+
+    /* Copy only last input samples into the state buffer   
+       which will be used for next four samples processing */
+    *px++ = (q31_t) fcurr4;
+
+    /* Process third sample for first tap */
+    fnext3 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 31) + fcurr3;
+    gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 31) + fcurr2;
+
+    /* Process fourth sample for first tap */
+    fnext4 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 31) + fcurr4;
+    gnext4 = (q31_t) (((q63_t) fcurr4 * (*pk++)) >> 31) + fcurr3;
+
+    /* save g1(n) in state buffer for next sample processing */
+    /* *px++ = gnext4;       */
+
+    /* Update of f values for next coefficient set processing */
+    fcurr1 = fnext1;
+    fcurr2 = fnext2;
+    fcurr3 = fnext3;
+    fcurr4 = fnext4;
+
+
+    /* Loop unrolling.  Process 4 taps at a time . */
+    stageCnt = (numStages - 1u) >> 2u;
+
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numStages-3 coefficients. */
+
+    /* Process 2nd, 3rd, 4th and 5th taps ... here */
+    while(stageCnt > 0u)
+    {
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q31_t) gnext4;
+
+      /* Process first sample for 2nd, 6th .. tap */
+      /* Sample processing for K2, K6.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fcurr1;
+      /* Process second sample for 2nd, 6th .. tap */
+      /* for sample 2 processing */
+      fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 31) + fcurr2;
+      /* Process third sample for 2nd, 6th .. tap */
+      fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 31) + fcurr3;
+      /* Process fourth sample for 2nd, 6th .. tap */
+      fnext4 = (q31_t) (((q63_t) gnext3 * (*pk)) >> 31) + fcurr4;
+
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (q31_t) (((q63_t) fcurr4 * (*pk)) >> 31) + gnext3;
+      gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 31) + gnext2;
+      gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 31) + gnext1;
+      gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk++)) >> 31) + gcurr1;
+
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g2(n) in state buffer */
+      *px++ = (q31_t) gnext4;
+
+      /* Sample processing for K3, K7.... */
+      /* Process first sample for 3rd, 7th .. tap */
+      /* f3(n) = f2(n) +  K3 * g2(n-1) */
+      fcurr1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fnext1;
+      /* Process second sample for 3rd, 7th .. tap */
+      fcurr2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 31) + fnext2;
+      /* Process third sample for 3rd, 7th .. tap */
+      fcurr3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 31) + fnext3;
+      /* Process fourth sample for 3rd, 7th .. tap */
+      fcurr4 = (q31_t) (((q63_t) gnext3 * (*pk)) >> 31) + fnext4;
+
+      /* Calculation of state values for next stage */
+      /*  gnext4 = fnext4 * (*pk) +  gnext3; */
+      gnext4 = (q31_t) (((q63_t) fnext4 * (*pk)) >> 31) + gnext3;
+      gnext3 = (q31_t) (((q63_t) fnext3 * (*pk)) >> 31) + gnext2;
+      /*  gnext2 = fnext2 * (*pk) +  gnext1; */
+      gnext2 = (q31_t) (((q63_t) fnext2 * (*pk)) >> 31) + gnext1;
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      /*  gnext1 = fnext1 * (*pk++) +  gcurr1; */
+      gnext1 = (q31_t) (((q63_t) fnext1 * (*pk++)) >> 31) + gcurr1;
+
+      /* Read g1(n-1), g3(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = (q31_t) gnext4;
+
+      /* Sample processing for K4, K8.... */
+      /* Process first sample for 4th, 8th .. tap */
+      /* f4(n) = f3(n) +  K4 * g3(n-1) */
+      fnext1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fcurr1;
+      /* Process second sample for 4th, 8th .. tap */
+      /* for sample 2 processing */
+      fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 31) + fcurr2;
+      /* Process third sample for 4th, 8th .. tap */
+      fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 31) + fcurr3;
+      /* Process fourth sample for 4th, 8th .. tap */
+      fnext4 = (q31_t) (((q63_t) gnext3 * (*pk)) >> 31) + fcurr4;
+
+      /* g4(n) = f3(n) * K4  +  g3(n-1) */
+      /* Calculation of state values for next stage */
+      gnext4 = (q31_t) (((q63_t) fcurr4 * (*pk)) >> 31) + gnext3;
+      gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 31) + gnext2;
+      gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 31) + gnext1;
+      gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk++)) >> 31) + gcurr1;
+
+      /* Read g2(n-1), g4(n-1) .... from state */
+      gcurr1 = *px;
+
+      /* save g4(n) in state buffer */
+      *px++ = (q31_t) gnext4;
+
+      /* Sample processing for K5, K9.... */
+      /* Process first sample for 5th, 9th .. tap */
+      /* f5(n) = f4(n) +  K5 * g4(n-1) */
+      fcurr1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fnext1;
+      /* Process second sample for 5th, 9th .. tap */
+      fcurr2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 31) + fnext2;
+      /* Process third sample for 5th, 9th .. tap */
+      fcurr3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 31) + fnext3;
+      /* Process fourth sample for 5th, 9th .. tap */
+      fcurr4 = (q31_t) (((q63_t) gnext3 * (*pk)) >> 31) + fnext4;
+
+      /* Calculation of state values for next stage */
+      /* g5(n) = f4(n) * K5  +  g4(n-1) */
+      gnext4 = (q31_t) (((q63_t) fnext4 * (*pk)) >> 31) + gnext3;
+      gnext3 = (q31_t) (((q63_t) fnext3 * (*pk)) >> 31) + gnext2;
+      gnext2 = (q31_t) (((q63_t) fnext2 * (*pk)) >> 31) + gnext1;
+      gnext1 = (q31_t) (((q63_t) fnext1 * (*pk++)) >> 31) + gcurr1;
+
+      stageCnt--;
+    }
+
+    /* If the (filter length -1) is not a multiple of 4, compute the remaining filter taps */
+    stageCnt = (numStages - 1u) % 0x4u;
+
+    while(stageCnt > 0u)
+    {
+      gcurr1 = *px;
+
+      /* save g value in state buffer */
+      *px++ = (q31_t) gnext4;
+
+      /* Process four samples for last three taps here */
+      fnext1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fcurr1;
+      fnext2 = (q31_t) (((q63_t) gnext1 * (*pk)) >> 31) + fcurr2;
+      fnext3 = (q31_t) (((q63_t) gnext2 * (*pk)) >> 31) + fcurr3;
+      fnext4 = (q31_t) (((q63_t) gnext3 * (*pk)) >> 31) + fcurr4;
+
+      /* g1(n) = f0(n) * K1  +  g0(n-1) */
+      gnext4 = (q31_t) (((q63_t) fcurr4 * (*pk)) >> 31) + gnext3;
+      gnext3 = (q31_t) (((q63_t) fcurr3 * (*pk)) >> 31) + gnext2;
+      gnext2 = (q31_t) (((q63_t) fcurr2 * (*pk)) >> 31) + gnext1;
+      gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk++)) >> 31) + gcurr1;
+
+      /* Update of f values for next coefficient set processing */
+      fcurr1 = fnext1;
+      fcurr2 = fnext2;
+      fcurr3 = fnext3;
+      fcurr4 = fnext4;
+
+      stageCnt--;
+
+    }
+
+    /* The results in the 4 accumulators, store in the destination buffer. */
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+    *pDst++ = (q31_t) fcurr2;
+    *pDst++ = (q31_t) fcurr3;
+    *pDst++ = (q31_t) fcurr4;
+
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr1 = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g2(n) from state buffer */
+    gcurr1 = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fcurr1;
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk++)) >> 31) + gcurr1;
+    /* save g1(n) in state buffer */
+    *px++ = fcurr1;
+
+    /* f1(n) is saved in fcurr1   
+       for next stage processing */
+    fcurr1 = fnext1;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurr1 = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext1;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext1 = (q31_t) (((q63_t) gcurr1 * (*pk)) >> 31) + fcurr1;
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext1 = (q31_t) (((q63_t) fcurr1 * (*pk++)) >> 31) + gcurr1;
+
+      /* f1(n) is saved in fcurr1   
+         for next stage processing */
+      fcurr1 = fnext1;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr1;
+
+    blkCnt--;
+
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q31_t fcurr, fnext, gcurr, gnext;              /* temporary variables */
+  uint32_t numStages = S->numStages;             /* Length of the filter */
+  uint32_t blkCnt, stageCnt;                     /* temporary variables for counts */
+
+  pState = &S->pState[0];
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* f0(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize coeff pointer */
+    pk = (pCoeffs);
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* read g0(n-1) from state buffer */
+    gcurr = *px;
+
+    /* for sample 1 processing */
+    /* f1(n) = f0(n) +  K1 * g0(n-1) */
+    fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
+    /* g1(n) = f0(n) * K1  +  g0(n-1) */
+    gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
+    /* save g1(n) in state buffer */
+    *px++ = fcurr;
+
+    /* f1(n) is saved in fcurr1           
+       for next stage processing */
+    fcurr = fnext;
+
+    stageCnt = (numStages - 1u);
+
+    /* stage loop */
+    while(stageCnt > 0u)
+    {
+      /* read g2(n) from state buffer */
+      gcurr = *px;
+
+      /* save g1(n) in state buffer */
+      *px++ = gnext;
+
+      /* Sample processing for K2, K3.... */
+      /* f2(n) = f1(n) +  K2 * g1(n-1) */
+      fnext = (q31_t) (((q63_t) gcurr * (*pk)) >> 31) + fcurr;
+      /* g2(n) = f1(n) * K2  +  g1(n-1) */
+      gnext = (q31_t) (((q63_t) fcurr * (*pk++)) >> 31) + gcurr;
+
+      /* f1(n) is saved in fcurr1           
+         for next stage processing */
+      fcurr = fnext;
+
+      stageCnt--;
+
+    }
+
+    /* y(n) = fN(n) */
+    *pDst++ = fcurr;
+
+    blkCnt--;
+
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_Lattice group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c
new file mode 100644
index 0000000000..28214d11e5
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c
@@ -0,0 +1,368 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_q15.c   
+*   
+* Description:  Q15 FIR filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 FIR filter.   
+ * @param[in] *S points to an instance of the Q15 FIR structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in]  blockSize number of samples to process per call.   
+ * @return none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.   
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.   
+ *   
+ * \par   
+ * Refer to the function arm_fir_fast_q15() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_fir_q15(
+  const arm_fir_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *px1;                                    /* Temporary q15 pointer for state buffer */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q31_t *px2;                                    /* Temporary q31 pointer for SIMD state buffer accesses */
+  q31_t x0, x1, x2, x3, c0;                      /* Temporary variables to hold SIMD state and coefficient values */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.   
+   * The variables acc0 ... acc3 hold output values that are being computed:   
+   *   
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]   
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]   
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]   
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]   
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer.   
+     ** Use 32-bit SIMD to move the 16-bit data.  Only requires two copies. */
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pSrc)++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer of type q15 */
+    px1 = pState;
+
+    /* Initialize coeff pointer of type q31 */
+    pb = (q31_t *) (pCoeffs);
+
+    /* Read the first two samples from the state buffer:  x[n-N], x[n-N-1] */
+    x0 = *(q31_t *) (px1++);
+
+    /* Read the third and forth samples from the state buffer: x[n-N-1], x[n-N-2] */
+    x1 = *(q31_t *) (px1++);
+
+    /* Loop over the number of taps.  Unroll by a factor of 4.   
+     ** Repeat until we've computed numTaps-4 coefficients. */
+    tapCnt = numTaps >> 2;
+    do
+    {
+      /* Read the first two coefficients using SIMD:  b[N] and b[N-1] coefficients */
+      c0 = *(pb++);
+
+      /* acc0 +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      acc0 = __SMLALD(x0, c0, acc0);
+
+      /* acc1 +=  b[N] * x[n-N-1] + b[N-1] * x[n-N-2] */
+      acc1 = __SMLALD(x1, c0, acc1);
+
+      /* Read state x[n-N-2], x[n-N-3] */
+      x2 = *(q31_t *) (px1++);
+
+      /* Read state x[n-N-3], x[n-N-4] */
+      x3 = *(q31_t *) (px1++);
+
+      /* acc2 +=  b[N] * x[n-N-2] + b[N-1] * x[n-N-3] */
+      acc2 = __SMLALD(x2, c0, acc2);
+
+      /* acc3 +=  b[N] * x[n-N-3] + b[N-1] * x[n-N-4] */
+      acc3 = __SMLALD(x3, c0, acc3);
+
+      /* Read coefficients b[N-2], b[N-3] */
+      c0 = *(pb++);
+
+      /* acc0 +=  b[N-2] * x[n-N-2] + b[N-3] * x[n-N-3] */
+      acc0 = __SMLALD(x2, c0, acc0);
+
+      /* acc1 +=  b[N-2] * x[n-N-3] + b[N-3] * x[n-N-4] */
+      acc1 = __SMLALD(x3, c0, acc1);
+
+      /* Read state x[n-N-4], x[n-N-5] */
+      x0 = *(q31_t *) (px1++);
+
+      /* Read state x[n-N-5], x[n-N-6] */
+      x1 = *(q31_t *) (px1++);
+
+      /* acc2 +=  b[N-2] * x[n-N-4] + b[N-3] * x[n-N-5] */
+      acc2 = __SMLALD(x0, c0, acc2);
+
+      /* acc3 +=  b[N-2] * x[n-N-5] + b[N-3] * x[n-N-6] */
+      acc3 = __SMLALD(x1, c0, acc3);
+      tapCnt--;
+
+    }
+    while(tapCnt > 0u);
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps.   
+     ** This is always be 2 taps since the filter length is even. */
+    if((numTaps & 0x3u) != 0u)
+    {
+      /* Read 2 coefficients */
+      c0 = *(pb++);
+      /* Fetch 4 state variables */
+      x2 = *(q31_t *) (px1++);
+      x3 = *(q31_t *) (px1++);
+
+      /* Perform the multiply-accumulates */
+      acc0 = __SMLALD(x0, c0, acc0);
+      acc1 = __SMLALD(x1, c0, acc1);
+      acc2 = __SMLALD(x2, c0, acc2);
+      acc3 = __SMLALD(x3, c0, acc3);
+    }
+
+    /* The results in the 4 accumulators are in 2.30 format.  Convert to 1.15 with saturation.   
+     ** Then store the 4 outputs in the destination buffer. */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc0 >> 15), 16), __SSAT((acc1 >> 15), 16), 16);
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc2 >> 15), 16), __SSAT((acc3 >> 15), 16), 16);
+
+#else
+
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc1 >> 15), 16), __SSAT((acc0 >> 15), 16), 16);
+    *__SIMD32(pDst)++ =
+      __PKHBT(__SSAT((acc3 >> 15), 16), __SSAT((acc2 >> 15), 16), 16);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN       */
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+  while(blkCnt > 0u)
+  {
+    /* Copy two samples into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Use SIMD to hold states and coefficients */
+    px2 = (q31_t *) pState;
+    pb = (q31_t *) (pCoeffs);
+    tapCnt = numTaps >> 1;
+
+    do
+    {
+      acc0 = __SMLALD(*px2++, *(pb++), acc0);
+      tapCnt--;
+    }
+    while(tapCnt > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.15 with saturation.   
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) (__SSAT((acc0 >> 15), 16));
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy remaining data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *px;                                     /* Temporary pointer for state buffer */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc;                                     /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Number of nTaps in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = pCoeffs;
+
+    tapCnt = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += (q31_t) * px++ * *pb++;
+      tapCnt--;
+    } while(tapCnt > 0u);
+
+    /* The result is in 2.30 format.  Convert to 1.15        
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q15_t) __SSAT((acc >> 15u), 16);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  tapCnt = (numTaps - 1u);
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c
new file mode 100644
index 0000000000..adabf8458c
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c
@@ -0,0 +1,383 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_q31.c   
+*   
+* Description:	Q31 FIR filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @param[in] *S points to an instance of the Q31 FIR filter structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in] blockSize number of samples to process per call.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around rather than clip.   
+ * In order to avoid overflows completely the input signal must be scaled down by log2(numTaps) bits.   
+ * After all multiply-accumulates are performed, the 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result. 
+ *   
+ * \par   
+ * Refer to the function arm_fir_fast_q31() for a faster but less precise implementation of this filter for Cortex-M3 and Cortex-M4.   
+ */
+
+void arm_fir_q31(
+  const arm_fir_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t x0, x1, x2, x3;                          /* Temporary variables to hold state */
+  q31_t c0;                                      /* Temporary variable to hold coefficient value */
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.   
+   * The variables acc0 ... acc3 hold output values that are being computed:   
+   *   
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]   
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]   
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]   
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]   
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Read the first three samples from the state buffer:   
+     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+    x0 = *(px++);
+    x1 = *(px++);
+    x2 = *(px++);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+    i = tapCnt;
+
+    while(i > 0u)
+    {
+      /* Read the b[numTaps] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x3 = *(px++);
+
+      /* acc0 +=  b[numTaps] * x[n-numTaps] */
+      acc0 += ((q63_t) x0 * c0);
+
+      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */
+      acc1 += ((q63_t) x1 * c0);
+
+      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */
+      acc2 += ((q63_t) x2 * c0);
+
+      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */
+      acc3 += ((q63_t) x3 * c0);
+
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x1 * c0);
+      acc1 += ((q63_t) x2 * c0);
+      acc2 += ((q63_t) x3 * c0);
+      acc3 += ((q63_t) x0 * c0);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-5] sample */
+      x1 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x2 * c0);
+      acc1 += ((q63_t) x3 * c0);
+      acc2 += ((q63_t) x0 * c0);
+      acc3 += ((q63_t) x1 * c0);
+      /* Read the b[numTaps-3] coefficients */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-6] sample */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x3 * c0);
+      acc1 += ((q63_t) x0 * c0);
+      acc2 += ((q63_t) x1 * c0);
+      acc3 += ((q63_t) x2 * c0);
+      i--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+    i = numTaps - (tapCnt * 4u);
+    while(i > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x3 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q63_t) x0 * c0);
+      acc1 += ((q63_t) x1 * c0);
+      acc2 += ((q63_t) x2 * c0);
+      acc3 += ((q63_t) x3 * c0);
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+      x2 = x3;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* The results in the 4 accumulators are in 2.62 format.  Convert to 1.31   
+     ** Then store the 4 outputs in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 >> 31u);
+    *pDst++ = (q31_t) (acc1 >> 31u);
+    *pDst++ = (q31_t) (acc2 >> 31u);
+    *pDst++ = (q31_t) (acc3 >> 31u);
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      acc0 += (q63_t) * (px++) * (*(pb++));
+      i--;
+    } while(i > 0u);
+
+    /* The result is in 2.62 format.  Convert to 1.31   
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q31_t) (acc0 >> 31u);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  q63_t acc;                                     /* Accumulator */
+  uint32_t numTaps = S->numTaps;                 /* Length of the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState buffer contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = pCoeffs;
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += (q63_t) * px++ * *pb++;
+      i--;
+    } while(i > 0u);
+
+    /* The result is in 2.62 format.  Convert to 1.31        
+     ** Then store the output in the destination buffer. */
+    *pDst++ = (q31_t) (acc >> 31u);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the starting of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy numTaps number of values */
+  tapCnt = numTaps - 1u;
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+
+#endif /*  #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c
new file mode 100644
index 0000000000..c2d70c2909
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c
@@ -0,0 +1,385 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_q7.c   
+*   
+* Description:  Q7 FIR filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR   
+ * @{   
+ */
+
+/**   
+ * @param[in]   *S points to an instance of the Q7 FIR filter structure.   
+ * @param[in]   *pSrc points to the block of input data.   
+ * @param[out]  *pDst points to the block of output data.   
+ * @param[in]   blockSize number of samples to process per call.   
+ * @return 	none.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.   
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * The accumulator is converted to 18.7 format by discarding the low 7 bits.   
+ * Finally, the result is truncated to 1.7 format.   
+ */
+
+void arm_fir_q7(
+  const arm_fir_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t *pState = S->pState;                      /* State pointer */
+  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
+  q7_t *pStateCurnt;                             /* Points to the current sample of the state */
+  q7_t x0, x1, x2, x3;                           /* Temporary variables to hold state */
+  q7_t c0;                                       /* Temporary variable to hold coefficient value */
+  q7_t *px;                                      /* Temporary pointer for state */
+  q7_t *pb;                                      /* Temporary pointer for coefficient buffer */
+  q31_t acc0, acc1, acc2, acc3;                  /* Accumulators */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t i, tapCnt, blkCnt;                    /* Loop counters */
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Apply loop unrolling and compute 4 output values simultaneously.   
+   * The variables acc0 ... acc3 hold output values that are being computed:   
+   *   
+   *    acc0 =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0]   
+   *    acc1 =  b[numTaps-1] * x[n-numTaps] +   b[numTaps-2] * x[n-numTaps-1] + b[numTaps-3] * x[n-numTaps-2] +...+ b[0] * x[1]   
+   *    acc2 =  b[numTaps-1] * x[n-numTaps+1] + b[numTaps-2] * x[n-numTaps] +   b[numTaps-3] * x[n-numTaps-1] +...+ b[0] * x[2]   
+   *    acc3 =  b[numTaps-1] * x[n-numTaps+2] + b[numTaps-2] * x[n-numTaps+1] + b[numTaps-3] * x[n-numTaps]   +...+ b[0] * x[3]   
+   */
+  blkCnt = blockSize >> 2;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Copy four new input samples into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set all accumulators to zero */
+    acc0 = 0;
+    acc1 = 0;
+    acc2 = 0;
+    acc3 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Read the first three samples from the state buffer:   
+     *  x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2] */
+    x0 = *(px++);
+    x1 = *(px++);
+    x2 = *(px++);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+    i = tapCnt;
+
+    while(i > 0u)
+    {
+      /* Read the b[numTaps] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-3] sample */
+      x3 = *(px++);
+
+      /* acc0 +=  b[numTaps] * x[n-numTaps] */
+      acc0 += ((q15_t) x0 * c0);
+
+      /* acc1 +=  b[numTaps] * x[n-numTaps-1] */
+      acc1 += ((q15_t) x1 * c0);
+
+      /* acc2 +=  b[numTaps] * x[n-numTaps-2] */
+      acc2 += ((q15_t) x2 * c0);
+
+      /* acc3 +=  b[numTaps] * x[n-numTaps-3] */
+      acc3 += ((q15_t) x3 * c0);
+
+      /* Read the b[numTaps-1] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-4] sample */
+      x0 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x1 * c0);
+      acc1 += ((q15_t) x2 * c0);
+      acc2 += ((q15_t) x3 * c0);
+      acc3 += ((q15_t) x0 * c0);
+
+      /* Read the b[numTaps-2] coefficient */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-5] sample */
+      x1 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x2 * c0);
+      acc1 += ((q15_t) x3 * c0);
+      acc2 += ((q15_t) x0 * c0);
+      acc3 += ((q15_t) x1 * c0);
+      /* Read the b[numTaps-3] coefficients */
+      c0 = *(pb++);
+
+      /* Read x[n-numTaps-6] sample */
+      x2 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x3 * c0);
+      acc1 += ((q15_t) x0 * c0);
+      acc2 += ((q15_t) x1 * c0);
+      acc3 += ((q15_t) x2 * c0);
+      i--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+
+    i = numTaps - (tapCnt * 4u);
+    while(i > 0u)
+    {
+      /* Read coefficients */
+      c0 = *(pb++);
+
+      /* Fetch 1 state variable */
+      x3 = *(px++);
+
+      /* Perform the multiply-accumulates */
+      acc0 += ((q15_t) x0 * c0);
+      acc1 += ((q15_t) x1 * c0);
+      acc2 += ((q15_t) x2 * c0);
+      acc3 += ((q15_t) x3 * c0);
+
+      /* Reuse the present sample states for next sample */
+      x0 = x1;
+      x1 = x2;
+      x2 = x3;
+
+      /* Decrement the loop counter */
+      i--;
+    }
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 4;
+
+    /* The results in the 4 accumulators are in 2.62 format.  Convert to 1.31   
+     ** Then store the 4 outputs in the destination buffer. */
+    acc0 = __SSAT((acc0 >> 7u), 8);
+    *pDst++ = acc0;
+    acc1 = __SSAT((acc1 >> 7u), 8);
+    *pDst++ = acc1;
+    acc2 = __SSAT((acc2 >> 7u), 8);
+    *pDst++ = acc2;
+    acc3 = __SSAT((acc3 >> 7u), 8);
+    *pDst++ = acc3;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set the accumulator to zero */
+    acc0 = 0;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize Coefficient pointer */
+    pb = (pCoeffs);
+
+    i = numTaps;
+
+    /* Perform the multiply-accumulates */
+    do
+    {
+      acc0 += (q15_t) * (px++) * (*(pb++));
+      i--;
+    } while(i > 0u);
+
+    /* The result is in 2.14 format.  Convert to 1.7   
+     ** Then store the output in the destination buffer. */
+    *pDst++ = __SSAT((acc0 >> 7u), 8);
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the samples loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.   
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.   
+   ** This prepares the state buffer for the next function call. */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  uint32_t numTaps = S->numTaps;                 /* Number of taps in the filter */
+  uint32_t i, blkCnt;                            /* Loop counters */
+  q7_t *pState = S->pState;                      /* State pointer */
+  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
+  q7_t *px, *pb;                                 /* Temporary pointers to state and coeff */
+  q31_t acc = 0;                                 /* Accumlator */
+  q7_t *pStateCurnt;                             /* Points to the current sample of the state */
+
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = S->pState + (numTaps - 1u);
+
+  /* Initialize blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  /* Perform filtering upto BlockSize - BlockSize%4  */
+  while(blkCnt > 0u)
+  {
+    /* Copy one sample at a time into state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Set accumulator to zero */
+    acc = 0;
+
+    /* Initialize state pointer of type q7 */
+    px = pState;
+
+    /* Initialize coeff pointer of type q7 */
+    pb = pCoeffs;
+
+
+    i = numTaps;
+
+    while(i > 0u)
+    {
+      /* acc =  b[numTaps-1] * x[n-numTaps-1] + b[numTaps-2] * x[n-numTaps-2] + b[numTaps-3] * x[n-numTaps-3] +...+ b[0] * x[0] */
+      acc += (q15_t) * px++ * *pb++;
+      i--;
+    }
+
+    /* Store the 1.7 format filter output in destination buffer */
+    *pDst++ = (q7_t) __SSAT((acc >> 7), 8);
+
+    /* Advance the state pointer by 1 to process the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete.        
+   ** Now copy the last numTaps - 1 samples to the satrt of the state buffer.      
+   ** This prepares the state buffer for the next function call. */
+
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = S->pState;
+
+
+  /* Copy numTaps number of values */
+  i = (numTaps - 1u);
+
+  /* Copy q7_t data */
+  while(i > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    i--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c
new file mode 100644
index 0000000000..c83965b18b
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c
@@ -0,0 +1,362 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_sparse_f32.c   
+*   
+* Description:	Floating-point sparse FIR filter processing function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup FIR_Sparse Finite Impulse Response (FIR) Sparse Filters   
+ *   
+ * This group of functions implements sparse FIR filters.    
+ * Sparse FIR filters are equivalent to standard FIR filters except that most of the coefficients are equal to zero.  
+ * Sparse filters are used for simulating reflections in communications and audio applications.  
+ *  
+ * There are separate functions for Q7, Q15, Q31, and floating-point data types.   
+ * The functions operate on blocks  of input and output data and each call to the function processes   
+ * blockSize samples through the filter.  pSrc and   
+ * pDst points to input and output arrays respectively containing blockSize values.   
+ *   
+ * \par Algorithm:   
+ * The sparse filter instant structure contains an array of tap indices pTapDelay which specifies the locations of the non-zero coefficients.  
+ * This is in addition to the coefficient array b.  
+ * The implementation essentially skips the multiplications by zero and leads to an efficient realization.  
+ * 
      
+ *     y[n] = b[0] * x[n-pTapDelay[0]] + b[1] * x[n-pTapDelay[1]] + b[2] * x[n-pTapDelay[2]] + ...+ b[numTaps-1] * x[n-pTapDelay[numTaps-1]]   
+ * 
       
+ * \par   
+ * \image html FIRSparse.gif "Sparse FIR filter.  b[n] represents the filter coefficients"  
+ * \par   
+ * pCoeffs points to a coefficient array of size numTaps;   
+ * pTapDelay points to an array of nonzero indices and is also of size numTaps;  
+ * pState points to a state array of size maxDelay + blockSize, where  
+ * maxDelay is the largest offset value that is ever used in the pTapDelay array.  
+ * Some of the processing functions also require temporary working buffers.  
+ *  
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient and offset arrays may be shared among several instances while state variable arrays cannot be shared.   
+ * There are separate instance structure declarations for each of the 4 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros before static initialization.   
+ * The code below statically initializes each of the 4 different data type filter instance structures   
+ * 
       
+ *arm_fir_sparse_instance_f32 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};   
+ *arm_fir_sparse_instance_q31 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};   
+ *arm_fir_sparse_instance_q15 S = {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};   
+ *arm_fir_sparse_instance_q7 S =  {numTaps, 0, pState, pCoeffs, maxDelay, pTapDelay};   
+ * 
       
+ * \par   
+ *   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the sparse FIR filter functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief Processing function for the floating-point sparse FIR filter.  
+ * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.  
+ * @param[in]  *pSrc       points to the block of input data.  
+ * @param[out] *pDst       points to the block of output data  
+ * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.  
+ * @param[in]  blockSize   number of input samples to process per call.  
+ * @return none.  
+ */
+
+void arm_fir_sparse_f32(
+  arm_fir_sparse_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  float32_t * pScratchIn,
+  uint32_t blockSize)
+{
+
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *px;                                 /* Scratch buffer pointer */
+  float32_t *py = pState;                        /* Temporary pointers for state buffer */
+  float32_t *pb = pScratchIn;                    /* Temporary pointers for scratch buffer */
+  float32_t *pOut;                               /* Destination pointer */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter  */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  float32_t coeff = *pCoeffs++;                  /* Read the first coefficient value */
+
+
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+                        (int32_t *) pSrc, 1, blockSize);
+
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                       (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                       blockSize);
+
+  /* Working pointer for the scratch buffer */
+  px = pb;
+
+  /* Working pointer for destination buffer */
+  pOut = pDst;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Loop over the blockSize. Unroll by a factor of 4.   
+   * Compute 4 Multiplications at a time. */
+  blkCnt = blockSize >> 2u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in destination buffer */
+    *pOut++ = *px++ * coeff;
+    *pOut++ = *px++ * coeff;
+    *pOut++ = *px++ * coeff;
+    *pOut++ = *px++ * coeff;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in destination buffer */
+    *pOut++ = *px++ * coeff;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and   
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer */
+    px = pb;
+
+    /* Working pointer for destination buffer */
+    pOut = pDst;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.   
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pOut++ += *px++ * coeff;
+      *pOut++ += *px++ * coeff;
+      *pOut++ += *px++ * coeff;
+      *pOut++ += *px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,   
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pOut++ += *px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and   
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = ((int32_t) S->stateIndex -
+                 (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+#else
+
+/* Run the below code for Cortex-M0 */
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in destination buffer */
+    *pOut++ = *px++ * coeff;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and          
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer */
+    px = pb;
+
+    /* Working pointer for destination buffer */
+    pOut = pDst;
+
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pOut++ += *px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and          
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex =
+      ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0        */
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
new file mode 100644
index 0000000000..1ac9f71d71
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
@@ -0,0 +1,99 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_sparse_init_f32.c   
+*   
+* Description:	Floating-point sparse FIR filter initialization function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief  Initialization function for the floating-point sparse FIR filter.  
+ * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.  
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.  
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.  
+ * @param[in]     *pState    points to the state buffer.  
+ * @param[in]     *pTapDelay points to the array of offset times.  
+ * @param[in]     maxDelay   maximum offset time supported.  
+ * @param[in]     blockSize  number of samples that will be processed per block.  
+ * @return none  
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs holds the filter coefficients and has length numTaps.   
+ * pState holds the filter's state variables and must be of length   
+ * maxDelay + blockSize, where maxDelay   
+ * is the maximum number of delay line values.   
+ * blockSize is the   
+ * number of samples processed by the arm_fir_sparse_f32() function.   
+ */
+
+void arm_fir_sparse_init_f32(
+  arm_fir_sparse_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0u;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
new file mode 100644
index 0000000000..a74842dff6
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
@@ -0,0 +1,99 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_sparse_init_q15.c   
+*   
+* Description:	Q15 sparse FIR filter initialization function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief  Initialization function for the Q15 sparse FIR filter.  
+ * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.  
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.  
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.  
+ * @param[in]     *pState    points to the state buffer.  
+ * @param[in]     *pTapDelay points to the array of offset times.  
+ * @param[in]     maxDelay   maximum offset time supported.  
+ * @param[in]     blockSize  number of samples that will be processed per block.  
+ * @return none  
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs holds the filter coefficients and has length numTaps.   
+ * pState holds the filter's state variables and must be of length   
+ * maxDelay + blockSize, where maxDelay   
+ * is the maximum number of delay line values.   
+ * blockSize is the   
+ * number of words processed by arm_fir_sparse_q15() function.   
+ */
+
+void arm_fir_sparse_init_q15(
+  arm_fir_sparse_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0u;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
new file mode 100644
index 0000000000..fc71bc06e8
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
@@ -0,0 +1,98 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_sparse_init_q31.c   
+*   
+* Description:	Q31 sparse FIR filter initialization function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief  Initialization function for the Q31 sparse FIR filter.  
+ * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.  
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.  
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.  
+ * @param[in]     *pState    points to the state buffer.  
+ * @param[in]     *pTapDelay points to the array of offset times.  
+ * @param[in]     maxDelay   maximum offset time supported.  
+ * @param[in]     blockSize  number of samples that will be processed per block.  
+ * @return none  
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs holds the filter coefficients and has length numTaps.   
+ * pState holds the filter's state variables and must be of length   
+ * maxDelay + blockSize, where maxDelay   
+ * is the maximum number of delay line values.   
+ * blockSize is the number of words processed by arm_fir_sparse_q31() function.   
+ */
+
+void arm_fir_sparse_init_q31(
+  arm_fir_sparse_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0u;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
new file mode 100644
index 0000000000..f6223ac718
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
@@ -0,0 +1,99 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_fir_sparse_init_q7.c   
+*   
+* Description:	Q7 sparse FIR filter initialization function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief  Initialization function for the Q7 sparse FIR filter.  
+ * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.  
+ * @param[in]     numTaps    number of nonzero coefficients in the filter.  
+ * @param[in]     *pCoeffs   points to the array of filter coefficients.  
+ * @param[in]     *pState    points to the state buffer.  
+ * @param[in]     *pTapDelay points to the array of offset times.  
+ * @param[in]     maxDelay   maximum offset time supported.  
+ * @param[in]     blockSize  number of samples that will be processed per block.  
+ * @return none  
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs holds the filter coefficients and has length numTaps.   
+ * pState holds the filter's state variables and must be of length   
+ * maxDelay + blockSize, where maxDelay   
+ * is the maximum number of delay line values.   
+ * blockSize is the   
+ * number of samples processed by the arm_fir_sparse_q7() function.   
+ */
+
+void arm_fir_sparse_init_q7(
+  arm_fir_sparse_instance_q7 * S,
+  uint16_t numTaps,
+  q7_t * pCoeffs,
+  q7_t * pState,
+  int32_t * pTapDelay,
+  uint16_t maxDelay,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Assign TapDelay pointer */
+  S->pTapDelay = pTapDelay;
+
+  /* Assign MaxDelay */
+  S->maxDelay = maxDelay;
+
+  /* reset the stateIndex to 0 */
+  S->stateIndex = 0u;
+
+  /* Clear state buffer and size is always maxDelay + blockSize */
+  memset(pState, 0, (maxDelay + blockSize) * sizeof(q7_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c
new file mode 100644
index 0000000000..c71c1f8bc5
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c
@@ -0,0 +1,403 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_sparse_q15.c   
+*   
+* Description:	Q15 sparse FIR filter processing function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief Processing function for the Q15 sparse FIR filter.  
+ * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.  
+ * @param[in]  *pSrc        points to the block of input data.  
+ * @param[out] *pDst        points to the block of output data  
+ * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.  
+ * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.  
+ * @param[in]  blockSize    number of input samples to process per call.  
+ * @return none.  
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 32-bit accumulator.  
+ * The 1.15 x 1.15 multiplications yield a 2.30 result and these are added to a 2.30 accumulator.  
+ * Thus the full precision of the multiplications is maintained but there is only a single guard bit in the accumulator.  
+ * If the accumulator result overflows it will wrap around rather than saturate.  
+ * After all multiply-accumulates are performed, the 2.30 accumulator is truncated to 2.15 format and then saturated to 1.15 format.   
+ * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.  
+ */
+
+
+void arm_fir_sparse_q15(
+  arm_fir_sparse_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  q15_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize)
+{
+
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pIn = pSrc;                             /* Working pointer for input */
+  q15_t *pOut = pDst;                            /* Working pointer for output */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *px;                                     /* Temporary pointers for scratch buffer */
+  q15_t *pb = pScratchIn;                        /* Temporary pointers for scratch buffer */
+  q15_t *py = pState;                            /* Temporary pointers for state buffer */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Filter order */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  q15_t coeff = *pCoeffs++;                      /* Read the first coefficient value */
+  q31_t *pScr2 = pScratchOut;                    /* Working pointer for pScratchOut */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in1, in2;                                /* Temporary variables */
+
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                       pb, pb, blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  /* Loop over the blockSize. Unroll by a factor of 4.   
+   * Compute 4 multiplications at a time. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and   
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                         pb, pb, blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.   
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,   
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and   
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* All the output values are in pScratchOut buffer.   
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    in1 = *pScr2++;
+    in2 = *pScr2++;
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
+              16);
+
+#else
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
+              16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+    in1 = *pScr2++;
+
+    in2 = *pScr2++;
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in1 >> 15, 16), (q15_t) __SSAT(in2 >> 15, 16),
+              16);
+
+#else
+
+    *__SIMD32(pOut)++ =
+      __PKHBT((q15_t) __SSAT(in2 >> 15, 16), (q15_t) __SSAT(in1 >> 15, 16),
+              16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+
+    blkCnt--;
+
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+     remaining samples are processed in the below loop */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q15(py, delaySize, &S->stateIndex, 1, pIn, 1, blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                       pb, pb, blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and          
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q15(py, delaySize, &readIndex, 1,
+                         pb, pb, blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      *pScratchOut++ += (q31_t) * px++ * coeff;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and          
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* All the output values are in pScratchOut buffer.      
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    *pOut++ = (q15_t) __SSAT(*pScr2++ >> 15, 16);
+    blkCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c
new file mode 100644
index 0000000000..82808ecb07
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c
@@ -0,0 +1,367 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_sparse_q31.c   
+*   
+* Description:	Q31 sparse FIR filter processing function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+/**  
+ * @brief Processing function for the Q31 sparse FIR filter.  
+ * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.  
+ * @param[in]  *pSrc       points to the block of input data.  
+ * @param[out] *pDst       points to the block of output data  
+ * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.  
+ * @param[in]  blockSize   number of input samples to process per call.  
+ * @return none.  
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 32-bit accumulator.  
+ * The 1.31 x 1.31 multiplications are truncated to 2.30 format.  
+ * This leads to loss of precision on the intermediate multiplications and provides only a single guard bit.   
+ * If the accumulator result overflows, it wraps around rather than saturate.  
+ * In order to avoid overflows the input signal or coefficients must be scaled down by log2(numTaps) bits.  
+ */
+
+void arm_fir_sparse_q31(
+  arm_fir_sparse_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  q31_t * pScratchIn,
+  uint32_t blockSize)
+{
+
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *px;                                     /* Scratch buffer pointer */
+  q31_t *py = pState;                            /* Temporary pointers for state buffer */
+  q31_t *pb = pScratchIn;                        /* Temporary pointers for scratch buffer */
+  q31_t *pOut;                                   /* Destination pointer */
+  q63_t out;                                     /* Temporary output variable */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Filter order */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  q31_t coeff = *pCoeffs++;                      /* Read the first coefficient value */
+  q31_t in;
+
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_f32((int32_t *) py, delaySize, &S->stateIndex, 1,
+                        (int32_t *) pSrc, 1, blockSize);
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                       (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                       blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pOut = pDst;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Loop over the blockSize. Unroll by a factor of 4.   
+   * Compute 4 Multiplications at a time. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in the destination buffer */
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in the destination buffer */
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and   
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pOut = pDst;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.   
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2;
+
+    while(blkCnt > 0u)
+    {
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,   
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and   
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* Working output pointer is updated */
+  pOut = pDst;
+
+  /* Output is converted into 1.31 format. */
+  /* Loop over the blockSize. Unroll by a factor of 4.   
+   * process 4 output samples at a time. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    in = *pOut << 1;
+    *pOut++ = in;
+    in = *pOut << 1;
+    *pOut++ = in;
+    in = *pOut << 1;
+    *pOut++ = in;
+    in = *pOut << 1;
+    *pOut++ = in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+   * process the remaining output samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    in = *pOut << 1;
+    *pOut++ = in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform Multiplications and store in the destination buffer */
+    *pOut++ = (q31_t) (((q63_t) * px++ * coeff) >> 32);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and          
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_f32((int32_t *) py, delaySize, &readIndex, 1,
+                         (int32_t *) pb, (int32_t *) pb, blockSize, 1,
+                         blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pOut = pDst;
+
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      out = *pOut;
+      out += ((q63_t) * px++ * coeff) >> 32;
+      *pOut++ = (q31_t) (out);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and          
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = (int32_t) (S->stateIndex - blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* Working output pointer is updated */
+  pOut = pDst;
+
+  /* Output is converted into 1.31 format. */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    in = *pOut << 1;
+    *pOut++ = in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c
new file mode 100644
index 0000000000..a7dbdb60bc
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c
@@ -0,0 +1,395 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_fir_sparse_q7.c   
+*   
+* Description:	Q7 sparse FIR filter processing function.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ------------------------------------------------------------------- */
+#include "arm_math.h"
+
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup FIR_Sparse   
+ * @{   
+ */
+
+
+/**  
+ * @brief Processing function for the Q7 sparse FIR filter.  
+ * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.  
+ * @param[in]  *pSrc        points to the block of input data.  
+ * @param[out] *pDst        points to the block of output data  
+ * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.  
+ * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.  
+ * @param[in]  blockSize    number of input samples to process per call.  
+ * @return none.  
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.7 format and multiplications yield a 2.14 result.   
+ * The 2.14 intermediate results are accumulated in a 32-bit accumulator in 18.14 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * The accumulator is then converted to 18.7 format by discarding the low 7 bits.  
+ * Finally, the result is truncated to 1.7 format.  
+ */
+
+void arm_fir_sparse_q7(
+  arm_fir_sparse_instance_q7 * S,
+  q7_t * pSrc,
+  q7_t * pDst,
+  q7_t * pScratchIn,
+  q31_t * pScratchOut,
+  uint32_t blockSize)
+{
+
+  q7_t *pState = S->pState;                      /* State pointer */
+  q7_t *pCoeffs = S->pCoeffs;                    /* Coefficient pointer */
+  q7_t *px;                                      /* Scratch buffer pointer */
+  q7_t *py = pState;                             /* Temporary pointers for state buffer */
+  q7_t *pb = pScratchIn;                         /* Temporary pointers for scratch buffer */
+  q7_t *pOut = pDst;                             /* Destination pointer */
+  int32_t *pTapDelay = S->pTapDelay;             /* Pointer to the array containing offset of the non-zero tap values. */
+  uint32_t delaySize = S->maxDelay + blockSize;  /* state length */
+  uint16_t numTaps = S->numTaps;                 /* Filter order */
+  int32_t readIndex;                             /* Read index of the state buffer */
+  uint32_t tapCnt, blkCnt;                       /* loop counters */
+  q7_t coeff = *pCoeffs++;                       /* Read the coefficient value */
+  q31_t *pScr2 = pScratchOut;                    /* Working pointer for scratch buffer of output values */
+  q31_t in;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t in1, in2, in3, in4;
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
+                       blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                      (int32_t) blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  /* Loop over the blockSize. Unroll by a factor of 4.   
+   * Compute 4 multiplications at a time. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+   * compute the remaining samples */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and   
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                        (int32_t) blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    /* Loop over the blockSize. Unroll by a factor of 4.   
+     * Compute 4 MACS at a time. */
+    blkCnt = blockSize >> 2;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4,   
+     * compute the remaining samples */
+    blkCnt = blockSize % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and   
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex = ((int32_t) S->stateIndex -
+                 (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* All the output values are in pScratchOut buffer.   
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize >> 2;
+
+  while(blkCnt > 0u)
+  {
+    in1 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+    in2 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+    in3 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+    in4 = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+    *__SIMD32(pOut)++ = __PACKq7(in1, in2, in3, in4);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4,   
+     remaining samples are processed in the below loop */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* BlockSize of Input samples are copied into the state buffer */
+  /* StateIndex points to the starting position to write in the state buffer */
+  arm_circularWrite_q7(py, (int32_t) delaySize, &S->stateIndex, 1, pSrc, 1,
+                       blockSize);
+
+  /* Loop over the number of taps. */
+  tapCnt = numTaps;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Working pointer for state buffer is updated */
+  py = pState;
+
+  /* blockSize samples are read from the state buffer */
+  arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                      (int32_t) blockSize, 1, blockSize);
+
+  /* Working pointer for the scratch buffer of state values */
+  px = pb;
+
+  /* Working pointer for scratch buffer of output values */
+  pScratchOut = pScr2;
+
+  /* Loop over the blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Perform multiplication and store in the scratch buffer */
+    *pScratchOut++ = ((q31_t) * px++ * coeff);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Load the coefficient value and          
+   * increment the coefficient buffer for the next set of state values */
+  coeff = *pCoeffs++;
+
+  /* Read Index, from where the state buffer should be read, is calculated. */
+  readIndex = ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+  /* Wraparound of readIndex */
+  if(readIndex < 0)
+  {
+    readIndex += (int32_t) delaySize;
+  }
+
+  /* Loop over the number of taps. */
+  tapCnt = (uint32_t) numTaps - 1u;
+
+  while(tapCnt > 0u)
+  {
+    /* Working pointer for state buffer is updated */
+    py = pState;
+
+    /* blockSize samples are read from the state buffer */
+    arm_circularRead_q7(py, (int32_t) delaySize, &readIndex, 1, pb, pb,
+                        (int32_t) blockSize, 1, blockSize);
+
+    /* Working pointer for the scratch buffer of state values */
+    px = pb;
+
+    /* Working pointer for scratch buffer of output values */
+    pScratchOut = pScr2;
+
+    /* Loop over the blockSize */
+    blkCnt = blockSize;
+
+    while(blkCnt > 0u)
+    {
+      /* Perform Multiply-Accumulate */
+      in = *pScratchOut + ((q31_t) * px++ * coeff);
+      *pScratchOut++ = in;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* Load the coefficient value and          
+     * increment the coefficient buffer for the next set of state values */
+    coeff = *pCoeffs++;
+
+    /* Read Index, from where the state buffer should be read, is calculated. */
+    readIndex =
+      ((int32_t) S->stateIndex - (int32_t) blockSize) - *pTapDelay++;
+
+    /* Wraparound of readIndex */
+    if(readIndex < 0)
+    {
+      readIndex += (int32_t) delaySize;
+    }
+
+    /* Decrement the tap loop counter */
+    tapCnt--;
+  }
+
+  /* All the output values are in pScratchOut buffer.      
+     Convert them into 1.15 format, saturate and store in the destination buffer. */
+  /* Loop over the blockSize. */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    *pOut++ = (q7_t) __SSAT(*pScr2++ >> 7, 8);
+
+    /* Decrement the blockSize loop counter */
+    blkCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of FIR_Sparse group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c
new file mode 100644
index 0000000000..c140c0e733
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c
@@ -0,0 +1,402 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_iir_lattice_f32.c   
+*   
+* Description:	Floating-point IIR Lattice filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup IIR_Lattice Infinite Impulse Response (IIR) Lattice Filters   
+ *   
+ * This set of functions implements lattice filters   
+ * for Q15, Q31 and floating-point data types.  Lattice filters are used in a    
+ * variety of adaptive filter applications.  The filter structure has feedforward and   
+ * feedback components and the net impulse response is infinite length.   
+ * The functions operate on blocks   
+ * of input and output data and each call to the function processes   
+ * blockSize samples through the filter.  pSrc and   
+ * pDst point to input and output arrays containing blockSize values.   
+   
+ * \par Algorithm:   
+ * \image html IIRLattice.gif "Infinite Impulse Response Lattice filter"   
+ * 
       
+ *    fN(n)   =  x(n)   
+ *    fm-1(n) = fm(n) - km * gm-1(n-1)   for m = N, N-1, ...1   
+ *    gm(n)   = km * fm-1(n) + gm-1(n-1) for m = N, N-1, ...1   
+ *    y(n)    = vN * gN(n) + vN-1 * gN-1(n) + ...+ v0 * g0(n)   
+ * 
       
+ * \par   
+ * pkCoeffs points to array of reflection coefficients of size numStages.    
+ * Reflection coefficients are stored in time-reversed order.   
+ * \par   
+ * 
       
+ *    {kN, kN-1, ....k1}   
+ * 
       
+ * pvCoeffs points to the array of ladder coefficients of size (numStages+1).    
+ * Ladder coefficients are stored in time-reversed order.   
+ * \par   
+ * 
       
+ *    {vN, vN-1, ...v0}   
+ * 
       
+ * pState points to a state array of size numStages + blockSize.   
+ * The state variables shown in the figure above (the g values) are stored in the pState array.   
+ * The state variables are updated after each block of data is processed; the coefficients are untouched.   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter.   
+ * Coefficient arrays may be shared among several instances while state variable arrays cannot be shared.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+  *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ *   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros and then manually initialize the instance structure as follows:   
+ * 
       
+ *arm_iir_lattice_instance_f32 S = {numStages, pState, pkCoeffs, pvCoeffs};   
+ *arm_iir_lattice_instance_q31 S = {numStages, pState, pkCoeffs, pvCoeffs};   
+ *arm_iir_lattice_instance_q15 S = {numStages, pState, pkCoeffs, pvCoeffs};   
+ * 
       
+ * \par   
+ * where numStages is the number of stages in the filter; pState points to the state buffer array;   
+ * pkCoeffs points to array of the reflection coefficients; pvCoeffs points to the array of ladder coefficients.   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the IIR lattice filter functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/**   
+ * @addtogroup IIR_Lattice   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the floating-point IIR lattice filter.   
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in] blockSize number of samples to process.   
+ * @return none.   
+ */
+
+void arm_iir_lattice_f32(
+  const arm_iir_lattice_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t fcurr, fnext = 0, gcurr, gnext;      /* Temporary variables for lattice stages */
+  float32_t acc;                                 /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* temporary variables for counts */
+  float32_t *px1, *px2, *pk, *pv;                /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  float32_t *pState;                             /* State pointer */
+  float32_t *pStateCurnt;                        /* State current pointer */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  gcurr = 0.0f;
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0.0f;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for first tap */
+    gcurr = *px1++;
+    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+    fnext = fcurr - ((*pk) * gcurr);
+    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+    gnext = (fnext * (*pk++)) + gcurr;
+    /* write gN(n) into state for next sample processing */
+    *px2++ = gnext;
+    /* y(n) += gN(n) * vN  */
+    acc += (gnext * (*pv++));
+
+    /* Update f values for next coefficient processing */
+    fcurr = fnext;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = (numStages - 1u) >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Process sample for 2nd, 6th ...taps */
+      /* Read gN-2(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 2nd, 6th .. taps */
+      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+      fnext = fcurr - ((*pk) * gcurr);
+      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+      gnext = (fnext * (*pk++)) + gcurr;
+      /* y(n) += gN-1(n) * vN-1  */
+      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+      acc += (gnext * (*pv++));
+      /* write gN-1(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 3nd, 7th ...taps */
+      /* Read gN-3(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 3rd, 7th .. taps */
+      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+      fcurr = fnext - ((*pk) * gcurr);
+      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+      gnext = (fcurr * (*pk++)) + gcurr;
+      /* y(n) += gN-2(n) * vN-2  */
+      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+      acc += (gnext * (*pv++));
+      /* write gN-2(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 4th, 8th ...taps */
+      /* Read gN-4(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 4th, 8th .. taps */
+      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+      fnext = fcurr - ((*pk) * gcurr);
+      /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
+      gnext = (fnext * (*pk++)) + gcurr;
+      /* y(n) += gN-3(n) * vN-3  */
+      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+      acc += (gnext * (*pv++));
+      /* write gN-3(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 5th, 9th ...taps */
+      /* Read gN-5(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 5th, 9th .. taps */
+      /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */
+      fcurr = fnext - ((*pk) * gcurr);
+      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+      gnext = (fcurr * (*pk++)) + gcurr;
+      /* y(n) += gN-4(n) * vN-4  */
+      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+      acc += (gnext * (*pv++));
+      /* write gN-4(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      tapCnt--;
+
+    }
+
+    fnext = fcurr;
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = (numStages - 1u) % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = fcurr - ((*pk) * gcurr);
+      gnext = (fnext * (*pk++)) + gcurr;
+      /* Output samples for last taps */
+      acc += (gnext * (*pv++));
+      *px2++ = gnext;
+      fcurr = fnext;
+
+      tapCnt--;
+
+    }
+
+
+    /* y(n) += g0(n) * v0 */
+    acc += (fnext * (*pv));
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = acc;
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer   
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numStages) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0.0f;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for numStages */
+    tapCnt = numStages;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = fcurr - ((*pk) * gcurr);
+      gnext = (fnext * (*pk++)) + gcurr;
+
+      /* Output samples for last taps */
+      acc += (gnext * (*pv++));
+      *px2++ = gnext;
+      fcurr = fnext;
+
+      /* Decrementing loop counter */
+      tapCnt--;
+
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (fnext * (*pv));
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = acc;
+
+    /* Advance the state pointer by 1 to process the next group of samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer          
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages;
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+
+
+
+/**   
+ * @} end of IIR_Lattice group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
new file mode 100644
index 0000000000..5c78fc1347
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_iir_lattice_init_f32.c   
+*   
+* Description:  Floating-point IIR lattice filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup IIR_Lattice   
+ * @{   
+ */
+
+/**   
+ * @brief Initialization function for the floating-point IIR lattice filter.   
+ * @param[in] *S points to an instance of the floating-point IIR lattice structure.   
+ * @param[in] numStages number of stages in the filter.   
+ * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.   
+ * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.   
+ * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.   
+ * @param[in] blockSize number of samples to process.   
+ * @return none.   
+ */
+
+void arm_iir_lattice_init_f32(
+  arm_iir_lattice_instance_f32 * S,
+  uint16_t numStages,
+  float32_t * pkCoeffs,
+  float32_t * pvCoeffs,
+  float32_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign reflection coefficient pointer */
+  S->pkCoeffs = pkCoeffs;
+
+  /* Assign ladder coefficient pointer */
+  S->pvCoeffs = pvCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numStages */
+  memset(pState, 0, (numStages + blockSize) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+
+}
+
+  /**   
+   * @} end of IIR_Lattice group   
+   */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
new file mode 100644
index 0000000000..da4068cbeb
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_iir_lattice_init_q15.c   
+*   
+* Description:  Q15 IIR lattice filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup IIR_Lattice   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for the Q15 IIR lattice filter.   
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.   
+   * @param[in] numStages  number of stages in the filter.   
+   * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.   
+   * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.   
+   * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.   
+   * @param[in] blockSize number of samples to process per call.   
+   * @return none.   
+   */
+
+void arm_iir_lattice_init_q15(
+  arm_iir_lattice_instance_q15 * S,
+  uint16_t numStages,
+  q15_t * pkCoeffs,
+  q15_t * pvCoeffs,
+  q15_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign reflection coefficient pointer */
+  S->pkCoeffs = pkCoeffs;
+
+  /* Assign ladder coefficient pointer */
+  S->pvCoeffs = pvCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numStages */
+  memset(pState, 0, (numStages + blockSize) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+
+}
+
+/**   
+ * @} end of IIR_Lattice group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
new file mode 100644
index 0000000000..8bbc51902a
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
@@ -0,0 +1,83 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_iir_lattice_init_q31.c   
+*   
+* Description:  Initialization function for the Q31 IIR lattice filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup IIR_Lattice   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for the Q31 IIR lattice filter.   
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.   
+   * @param[in] numStages number of stages in the filter.   
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.   
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.   
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.   
+   * @param[in] blockSize number of samples to process.   
+   * @return none.   
+   */
+
+void arm_iir_lattice_init_q31(
+  arm_iir_lattice_instance_q31 * S,
+  uint16_t numStages,
+  q31_t * pkCoeffs,
+  q31_t * pvCoeffs,
+  q31_t * pState,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numStages = numStages;
+
+  /* Assign reflection coefficient pointer */
+  S->pkCoeffs = pkCoeffs;
+
+  /* Assign ladder coefficient pointer */
+  S->pvCoeffs = pvCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numStages */
+  memset(pState, 0, (numStages + blockSize) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+
+}
+
+/**   
+ * @} end of IIR_Lattice group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c
new file mode 100644
index 0000000000..e8bbc60b05
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c
@@ -0,0 +1,403 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_iir_lattice_q15.c   
+*   
+* Description:	Q15 IIR lattice filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup IIR_Lattice   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 IIR lattice filter.   
+ * @param[in] *S points to an instance of the Q15 IIR lattice structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in] blockSize number of samples to process.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.   
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.   
+ */
+
+void arm_iir_lattice_q15(
+  const arm_iir_lattice_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t fcurr, fnext, gcurr = 0, gnext;          /* Temporary variables for lattice stages */
+  q15_t gnext1, gnext2;                          /* Temporary variables for lattice stages */
+  uint32_t stgCnt;                               /* Temporary variables for counts */
+  q63_t acc;                                     /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
+  q15_t *px1, *px2, *pk, *pv;                    /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  q15_t *pState;                                 /* State pointer */
+  q15_t *pStateCurnt;                            /* State current pointer */
+  q15_t out;                                     /* Temporary variable for output */
+  q31_t v;                                       /* Temporary variable for ladder coefficient */
+
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for first tap */
+    gcurr = *px1++;
+    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+    fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+    fnext = __SSAT(fnext, 16);
+    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+    gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+    gnext = __SSAT(gnext, 16);
+    /* write gN(n) into state for next sample processing */
+    *px2++ = (q15_t) gnext;
+    /* y(n) += gN(n) * vN  */
+    acc += (q31_t) ((gnext * (*pv++)));
+
+
+    /* Update f values for next coefficient processing */
+    fcurr = fnext;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = (numStages - 1u) >> 2;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Process sample for 2nd, 6th ...taps */
+      /* Read gN-2(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 2nd, 6th .. taps */
+      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+      gnext1 = (q15_t) __SSAT(gnext, 16);
+      /* write gN-1(n) into state */
+      *px2++ = (q15_t) gnext1;
+
+
+      /* Process sample for 3nd, 7th ...taps */
+      /* Read gN-3(n-1) from state */
+      gcurr = *px1++;
+      /* Process sample for 3rd, 7th .. taps */
+      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+      fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
+      fcurr = __SSAT(fcurr, 16);
+      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+      gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
+      gnext2 = (q15_t) __SSAT(gnext, 16);
+      /* write gN-2(n) into state */
+      *px2++ = (q15_t) gnext2;
+
+      /* Read vN-1 and vN-2 at a time */
+      v = *__SIMD32(pv)++;
+
+
+      /* Pack gN-1(n) and gN-2(n) */
+
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      gnext = __PKHBT(gnext1, gnext2, 16);
+
+#else
+
+      gnext = __PKHBT(gnext2, gnext1, 16);
+
+#endif /*   #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* y(n) += gN-1(n) * vN-1  */
+      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+      /* y(n) += gN-2(n) * vN-2  */
+      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+      acc = __SMLALD(gnext, v, acc);
+
+
+      /* Process sample for 4th, 8th ...taps */
+      /* Read gN-4(n-1) from state */
+      gcurr = *px1++;
+      /* Process sample for 4th, 8th .. taps */
+      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      /* gN-3(n) = kN-3 * fN-1(n) + gN-1(n-1) */
+      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+      gnext1 = (q15_t) __SSAT(gnext, 16);
+      /* write  gN-3(n) for the next sample process */
+      *px2++ = (q15_t) gnext1;
+
+
+      /* Process sample for 5th, 9th ...taps */
+      /* Read gN-5(n-1) from state */
+      gcurr = *px1++;
+      /* Process sample for 5th, 9th .. taps */
+      /* fN-5(n) = fN-4(n) - kN-4 * gN-5(n-1) */
+      fcurr = fnext - (((q31_t) gcurr * (*pk)) >> 15);
+      fcurr = __SSAT(fcurr, 16);
+      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+      gnext = (((q31_t) fcurr * (*pk++)) >> 15) + gcurr;
+      gnext2 = (q15_t) __SSAT(gnext, 16);
+      /* write      gN-4(n) for the next sample process */
+      *px2++ = (q15_t) gnext2;
+
+      /* Read vN-3 and vN-4 at a time */
+      v = *__SIMD32(pv)++;
+
+      /* Pack gN-3(n) and gN-4(n) */
+#ifndef  ARM_MATH_BIG_ENDIAN
+
+      gnext = __PKHBT(gnext1, gnext2, 16);
+
+#else
+
+      gnext = __PKHBT(gnext2, gnext1, 16);
+
+#endif /*      #ifndef  ARM_MATH_BIG_ENDIAN    */
+
+      /* y(n) += gN-4(n) * vN-4  */
+      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+      /* y(n) += gN-3(n) * vN-3  */
+      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+      acc = __SMLALD(gnext, v, acc);
+
+      tapCnt--;
+
+    }
+
+    fnext = fcurr;
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = (numStages - 1u) % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = fcurr - (((q31_t) gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      gnext = (((q31_t) fnext * (*pk++)) >> 15) + gcurr;
+      gnext = __SSAT(gnext, 16);
+      /* Output samples for last taps */
+      acc += (q31_t) (((q31_t) gnext * (*pv++)));
+      *px2++ = (q15_t) gnext;
+      fcurr = fnext;
+
+      tapCnt--;
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q31_t) (((q31_t) fnext * (*pv++)));
+
+    out = (q15_t) __SSAT(acc >> 15, 16);
+    *px2++ = (q15_t) fnext;
+
+    /* write out into pDst */
+    *pDst++ = out;
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer   
+     for the preperation of next frame process */
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  stgCnt = (numStages >> 2u);
+
+  /* copy data */
+  while(stgCnt > 0u)
+  {
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    /* Decrement the loop counter */
+    stgCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  stgCnt = (numStages) % 0x4u;
+
+  /* copy data */
+  while(stgCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    stgCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t fcurr, fnext = 0, gcurr = 0, gnext;      /* Temporary variables for lattice stages */
+  uint32_t stgCnt;                               /* Temporary variables for counts */
+  q63_t acc;                                     /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
+  q15_t *px1, *px2, *pk, *pv;                    /* temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  q15_t *pState;                                 /* State pointer */
+  q15_t *pStateCurnt;                            /* State current pointer */
+  q15_t out;                                     /* Temporary variable for output */
+
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+    tapCnt = numStages;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample */
+      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+      fnext = fcurr - ((gcurr * (*pk)) >> 15);
+      fnext = __SSAT(fnext, 16);
+      /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+      gnext = ((fnext * (*pk++)) >> 15) + gcurr;
+      gnext = __SSAT(gnext, 16);
+      /* Output samples */
+      /* y(n) += gN(n) * vN */
+      acc += (q31_t) ((gnext * (*pv++)));
+      /* write gN(n) into state for next sample processing */
+      *px2++ = (q15_t) gnext;
+      /* Update f values for next coefficient processing */
+      fcurr = fnext;
+
+      tapCnt--;
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q31_t) ((fnext * (*pv++)));
+
+    out = (q15_t) __SSAT(acc >> 15, 16);
+    *px2++ = (q15_t) fnext;
+
+    /* write out into pDst */
+    *pDst++ = out;
+
+    /* Advance the state pointer by 1 to process the next group of samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer          
+     for the preperation of next frame process */
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  stgCnt = numStages;
+
+  /* copy data */
+  while(stgCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    stgCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+
+
+
+/**   
+ * @} end of IIR_Lattice group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c
new file mode 100644
index 0000000000..04e70386c6
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c
@@ -0,0 +1,342 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_iir_lattice_q31.c   
+*   
+* Description:	Q31 IIR lattice filter processing function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup IIR_Lattice   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 IIR lattice filter.   
+ * @param[in] *S points to an instance of the Q31 IIR lattice structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[out] *pDst points to the block of output data.   
+ * @param[in] blockSize number of samples to process.   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit.   
+ * Thus, if the accumulator result overflows it wraps around rather than clip.   
+ * In order to avoid overflows completely the input signal must be scaled down by 2*log2(numStages) bits.   
+ * After all multiply-accumulates are performed, the 2.62 accumulator is saturated to 1.32 format and then truncated to 1.31 format.   
+ */
+
+void arm_iir_lattice_q31(
+  const arm_iir_lattice_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t fcurr, fnext = 0, gcurr = 0, gnext;      /* Temporary variables for lattice stages */
+  q63_t acc;                                     /* Accumlator */
+  uint32_t blkCnt, tapCnt;                       /* Temporary variables for counts */
+  q31_t *px1, *px2, *pk, *pv;                    /* Temporary pointers for state and coef */
+  uint32_t numStages = S->numStages;             /* number of stages */
+  q31_t *pState;                                 /* State pointer */
+  q31_t *pStateCurnt;                            /* State current pointer */
+
+  blkCnt = blockSize;
+
+  pState = &S->pState[0];
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+
+    /* Process sample for first tap */
+    gcurr = *px1++;
+    /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+    fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+    /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+    gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+    /* write gN-1(n-1) into state for next sample processing */
+    *px2++ = gnext;
+    /* y(n) += gN(n) * vN  */
+    acc += ((q63_t) gnext * *pv++);
+
+    /* Update f values for next coefficient processing */
+    fcurr = fnext;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = (numStages - 1u) >> 2;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Process sample for 2nd, 6th .. taps */
+      /* Read gN-2(n-1) from state buffer */
+      gcurr = *px1++;
+      /* fN-2(n) = fN-1(n) - kN-1 * gN-2(n-1) */
+      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-1(n) = kN-1 * fN-2(n) + gN-2(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+      /* y(n) += gN-1(n) * vN-1  */
+      /* process for gN-5(n) * vN-5, gN-9(n) * vN-9 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-1(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      /* Process sample for 3nd, 7th ...taps */
+      /* Read gN-3(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 3rd, 7th .. taps */
+      /* fN-3(n) = fN-2(n) - kN-2 * gN-3(n-1) */
+      fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-2(n) = kN-2 * fN-3(n) + gN-3(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
+      /* y(n) += gN-2(n) * vN-2  */
+      /* process for gN-6(n) * vN-6, gN-10(n) * vN-10 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-2(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 4th, 8th ...taps */
+      /* Read gN-4(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 4th, 8th .. taps */
+      /* fN-4(n) = fN-3(n) - kN-3 * gN-4(n-1) */
+      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-3(n) = kN-3 * fN-4(n) + gN-4(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+      /* y(n) += gN-3(n) * vN-3  */
+      /* process for gN-7(n) * vN-7, gN-11(n) * vN-11 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-3(n) into state for next sample processing */
+      *px2++ = gnext;
+
+
+      /* Process sample for 5th, 9th ...taps */
+      /* Read gN-5(n-1) from state buffer */
+      gcurr = *px1++;
+      /* Process sample for 5th, 9th .. taps */
+      /* fN-5(n) = fN-4(n) - kN-4 * gN-1(n-1) */
+      fcurr = __QSUB(fnext, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      /* gN-4(n) = kN-4 * fN-5(n) + gN-5(n-1) */
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fcurr * (*pk++)) >> 31));
+      /* y(n) += gN-4(n) * vN-4  */
+      /* process for gN-8(n) * vN-8, gN-12(n) * vN-12 ... */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-4(n) into state for next sample processing */
+      *px2++ = gnext;
+
+      tapCnt--;
+
+    }
+
+    fnext = fcurr;
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = (numStages - 1u) % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample for last taps */
+      fnext = __QSUB(fcurr, (q31_t) (((q63_t) gcurr * (*pk)) >> 31));
+      gnext = __QADD(gcurr, (q31_t) (((q63_t) fnext * (*pk++)) >> 31));
+      /* Output samples for last taps */
+      acc += ((q63_t) gnext * *pv++);
+      *px2++ = gnext;
+      fcurr = fnext;
+
+      tapCnt--;
+
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q63_t) fnext *(
+  *pv++);
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = (q31_t) (acc >> 31u);
+
+    /* Advance the state pointer by 4 to process the next group of 4 samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer   
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numStages) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  };
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  /* Sample processing */
+  while(blkCnt > 0u)
+  {
+    /* Read Sample from input buffer */
+    /* fN(n) = x(n) */
+    fcurr = *pSrc++;
+
+    /* Initialize state read pointer */
+    px1 = pState;
+    /* Initialize state write pointer */
+    px2 = pState;
+    /* Set accumulator to zero */
+    acc = 0;
+    /* Initialize Ladder coeff pointer */
+    pv = &S->pvCoeffs[0];
+    /* Initialize Reflection coeff pointer */
+    pk = &S->pkCoeffs[0];
+
+    tapCnt = numStages;
+
+    while(tapCnt > 0u)
+    {
+      gcurr = *px1++;
+      /* Process sample */
+      /* fN-1(n) = fN(n) - kN * gN-1(n-1) */
+      fnext =
+        clip_q63_to_q31(((q63_t) fcurr -
+                         ((q31_t) (((q63_t) gcurr * (*pk)) >> 31))));
+      /* gN(n) = kN * fN-1(n) + gN-1(n-1) */
+      gnext =
+        clip_q63_to_q31(((q63_t) gcurr +
+                         ((q31_t) (((q63_t) fnext * (*pk++)) >> 31))));
+      /* Output samples */
+      /* y(n) += gN(n) * vN  */
+      acc += ((q63_t) gnext * *pv++);
+      /* write gN-1(n-1) into state for next sample processing */
+      *px2++ = gnext;
+      /* Update f values for next coefficient processing */
+      fcurr = fnext;
+
+      tapCnt--;
+    }
+
+    /* y(n) += g0(n) * v0 */
+    acc += (q63_t) fnext *(
+  *pv++);
+
+    *px2++ = fnext;
+
+    /* write out into pDst */
+    *pDst++ = (q31_t) (acc >> 31u);
+
+    /* Advance the state pointer by 1 to process the next group of samples */
+    pState = pState + 1u;
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy last S->numStages samples to start of the buffer          
+     for the preperation of next frame process */
+
+  /* Points to the start of the state buffer */
+  pStateCurnt = &S->pState[0];
+  pState = &S->pState[blockSize];
+
+  tapCnt = numStages;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+
+
+
+/**   
+ * @} end of IIR_Lattice group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c
new file mode 100644
index 0000000000..e3e1347a17
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c
@@ -0,0 +1,431 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_lms_f32.c   
+*   
+* Description:	Processing function for the floating-point LMS filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup LMS Least Mean Square (LMS) Filters   
+ *   
+ * LMS filters are a class of adaptive filters that are able to "learn" an unknown transfer functions.   
+ * LMS filters use a gradient descent method in which the filter coefficients are updated based on the instantaneous error signal.   
+ * Adaptive filters are often used in communication systems, equalizers, and noise removal.   
+ * The CMSIS DSP Library contains LMS filter functions that operate on Q15, Q31, and floating-point data types.   
+ * The library also contains normalized LMS filters in which the filter coefficient adaptation is indepedent of the level of the input signal.   
+ *   
+ * An LMS filter consists of two components as shown below.   
+ * The first component is a standard transversal or FIR filter.   
+ * The second component is a coefficient update mechanism.   
+ * The LMS filter has two input signals.   
+ * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.   
+ * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.   
+ * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.   
+ * This "error signal" tends towards zero as the filter adapts.   
+ * The LMS processing functions accept the input and reference input signals and generate the filter output and error signal.   
+ * \image html LMS.gif "Internal structure of the Least Mean Square filter"   
+ *   
+ * The functions operate on blocks of data and each call to the function processes   
+ * blockSize samples through the filter.   
+ * pSrc points to input signal, pRef points to reference signal,   
+ * pOut points to output signal and pErr points to error signal.   
+ * All arrays contain blockSize values.   
+ *   
+ * The functions operate on a block-by-block basis.   
+ * Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.   
+ * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.   
+ *   
+ * \par Algorithm:   
+ * The output signal y[n] is computed by a standard FIR filter:   
+ * 
       
+ *     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]   
+ * 
       
+ *   
+ * \par   
+ * The error signal equals the difference between the reference signal d[n] and the filter output:   
+ * 
       
+ *     e[n] = d[n] - y[n].   
+ * 
       
+ *   
+ * \par   
+ * After each sample of the error signal is computed, the filter coefficients b[k] are updated on a sample-by-sample basis:   
+ * 
       
+ *     b[k] = b[k] + e[n] * mu * x[n-k],  for k=0, 1, ..., numTaps-1   
+ * 
       
+ * where mu is the step size and controls the rate of coefficient convergence.   
+ *\par   
+ * In the APIs, pCoeffs points to a coefficient array of size numTaps.   
+ * Coefficients are stored in time reversed order.   
+ * \par   
+ * 
       
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
       
+ * \par   
+ * pState points to a state array of size numTaps + blockSize - 1.   
+ * Samples in the state buffer are stored in the order:   
+ * \par   
+ * 
       
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}   
+ * 
       
+ * \par   
+ * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.   
+ * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,   
+ * to be avoided and yields a significant speed improvement.   
+ * The state variables are updated after each block of data is processed.   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter and   
+ * coefficient and state arrays cannot be shared among instances.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Set the values in the state buffer to zeros before static initialization.   
+ * The code below statically initializes each of the 3 different data type filter instance structures   
+ * 
       
+ *    arm_lms_instance_f32 S = {numTaps, pState, pCoeffs, mu};   
+ *    arm_lms_instance_q31 S = {numTaps, pState, pCoeffs, mu, postShift};   
+ *    arm_lms_instance_q15 S = {numTaps, pState, pCoeffs, mu, postShift};   
+ * 
       
+ * where numTaps is the number of filter coefficients in the filter; pState is the address of the state buffer;   
+ * pCoeffs is the address of the coefficient buffer; mu is the step size parameter; and postShift is the shift applied to coefficients.   
+ *   
+ * \par Fixed-Point Behavior:   
+ * Care must be taken when using the Q15 and Q31 versions of the LMS filter.   
+ * The following issues must be considered:   
+ * - Scaling of coefficients   
+ * - Overflow and saturation   
+ *   
+ * \par Scaling of Coefficients:   
+ * Filter coefficients are represented as fractional values and   
+ * coefficients are restricted to lie in the range [-1 +1).   
+ * The fixed-point functions have an additional scaling parameter postShift.   
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.   
+ * This essentially scales the filter coefficients by 2^postShift and   
+ * allows the filter coefficients to exceed the range [+1 -1).   
+ * The value of postShift is set by the user based on the expected gain through the system being modeled.   
+ *   
+ * \par Overflow and Saturation:   
+ * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are   
+ * described separately as part of the function specific documentation below.   
+ */
+
+/**   
+ * @addtogroup LMS   
+ * @{   
+ */
+
+/**          
+ * @details          
+ * This function operates on floating-point data types.      
+ *   
+ * @brief Processing function for floating-point LMS filter.   
+ * @param[in]  *S points to an instance of the floating-point LMS filter structure.   
+ * @param[in]  *pSrc points to the block of input data.   
+ * @param[in]  *pRef points to the block of reference data.   
+ * @param[out] *pOut points to the block of output data.   
+ * @param[out] *pErr points to the block of error data.   
+ * @param[in]  blockSize number of samples to process.   
+ * @return     none.   
+ */
+
+void arm_lms_f32(
+  const arm_lms_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  float32_t mu = S->mu;                          /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  float32_t sum, e, d;                           /* accumulator, error, reference data sample */
+  float32_t w = 0.0f;                            /* weight factor */
+
+  e = 0.0f;
+  d = 0.0f;
+
+  /* S->pState points to state array which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result in the accumulator, store in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Calculation of Weighting factor for the updating filter coefficients */
+    w = e * mu;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the   
+     satrt of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1u) samples copy */
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result is stored in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Weighting factor for the LMS version */
+    w = e * mu;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb = *pb + (w * (*px++));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the       
+   * start of the state buffer. This prepares the state buffer for the       
+   * next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /*  Copy (numTaps - 1u) samples  */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of LMS group   
+   */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c
new file mode 100644
index 0000000000..9b08cdf727
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c
@@ -0,0 +1,87 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_lms_init_f32.c   
+*   
+* Description:  Floating-point LMS filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @addtogroup LMS   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for floating-point LMS filter.   
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.   
+   * @param[in] numTaps  number of filter coefficients.   
+   * @param[in] *pCoeffs points to the coefficient buffer.   
+   * @param[in] *pState points to state buffer.   
+   * @param[in] mu step size that controls filter coefficient updates.   
+   * @param[in] blockSize number of samples to process.   
+   * @return none.   
+   */
+
+/**   
+ * \par Description:   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
       
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
       
+ * The initial filter coefficients serve as a starting point for the adaptive filter.   
+ * pState points to an array of length numTaps+blockSize-1 samples, where blockSize is the number of input samples processed by each call to arm_lms_f32().   
+ */
+
+void arm_lms_init_f32(
+  arm_lms_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps */
+  memset(pState, 0, (numTaps + (blockSize - 1)) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+}
+
+/**   
+ * @} end of LMS group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c
new file mode 100644
index 0000000000..3a2a9948e6
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c
@@ -0,0 +1,97 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_lms_init_q15.c   
+*   
+* Description:  Q15 LMS filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS   
+ * @{   
+ */
+
+/**   
+* @brief Initialization function for the Q15 LMS filter.   
+* @param[in] *S points to an instance of the Q15 LMS filter structure.   
+* @param[in] numTaps  number of filter coefficients.   
+* @param[in] *pCoeffs points to the coefficient buffer.   
+* @param[in] *pState points to the state buffer.   
+* @param[in] mu step size that controls filter coefficient updates.   
+* @param[in] blockSize number of samples to process.   
+* @param[in] postShift bit shift applied to coefficients.   
+* @return    none.   
+*   
+* \par Description:   
+* pCoeffs points to the array of filter coefficients stored in time reversed order:   
+* 
       
+*    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+* 
       
+* The initial filter coefficients serve as a starting point for the adaptive filter.   
+* pState points to the array of state variables and size of array is   
+* numTaps+blockSize-1 samples, where blockSize is the number of   
+* input samples processed by each call to arm_lms_q15().   
+*/
+
+void arm_lms_init_q15(
+  arm_lms_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint32_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Assign postShift value to be applied */
+  S->postShift = postShift;
+
+}
+
+/**   
+ * @} end of LMS group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c
new file mode 100644
index 0000000000..b846be73a2
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c
@@ -0,0 +1,97 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_lms_init_q31.c   
+*   
+* Description:  Q31 LMS filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for Q31 LMS filter.   
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.   
+   * @param[in] numTaps  number of filter coefficients.   
+   * @param[in] *pCoeffs points to coefficient buffer.   
+   * @param[in] *pState points to state buffer.   
+   * @param[in] mu step size that controls filter coefficient updates.   
+   * @param[in] blockSize number of samples to process.   
+   * @param[in] postShift bit shift applied to coefficients.   
+   * @return none.   
+ *   
+ * \par Description:   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
       
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
       
+ * The initial filter coefficients serve as a starting point for the adaptive filter.   
+ * pState points to an array of length numTaps+blockSize-1 samples,   
+ * where blockSize is the number of input samples processed by each call to   
+ * arm_lms_q31().   
+ */
+
+void arm_lms_init_q31(
+  arm_lms_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint32_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, ((uint32_t) numTaps + (blockSize - 1u)) * sizeof(q31_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Assign postShift value to be applied */
+  S->postShift = postShift;
+
+}
+
+/**   
+ * @} end of LMS group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c
new file mode 100644
index 0000000000..2cc3047786
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c
@@ -0,0 +1,453 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_lms_norm_f32.c   
+*   
+* Description:	Processing function for the floating-point Normalised LMS.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @defgroup LMS_NORM Normalized LMS Filters   
+ *   
+ * This set of functions implements a commonly used adaptive filter.   
+ * It is related to the Least Mean Square (LMS) adaptive filter and includes an additional normalization   
+ * factor which increases the adaptation rate of the filter.   
+ * The CMSIS DSP Library contains normalized LMS filter functions that operate on Q15, Q31, and floating-point data types.   
+ *   
+ * A normalized least mean square (NLMS) filter consists of two components as shown below.   
+ * The first component is a standard transversal or FIR filter.   
+ * The second component is a coefficient update mechanism.   
+ * The NLMS filter has two input signals.   
+ * The "input" feeds the FIR filter while the "reference input" corresponds to the desired output of the FIR filter.   
+ * That is, the FIR filter coefficients are updated so that the output of the FIR filter matches the reference input.   
+ * The filter coefficient update mechanism is based on the difference between the FIR filter output and the reference input.   
+ * This "error signal" tends towards zero as the filter adapts.   
+ * The NLMS processing functions accept the input and reference input signals and generate the filter output and error signal.   
+ * \image html LMS.gif "Internal structure of the NLMS adaptive filter"   
+ *   
+ * The functions operate on blocks of data and each call to the function processes   
+ * blockSize samples through the filter.   
+ * pSrc points to input signal, pRef points to reference signal,   
+ * pOut points to output signal and pErr points to error signal.   
+ * All arrays contain blockSize values.   
+ *   
+ * The functions operate on a block-by-block basis.   
+ * Internally, the filter coefficients b[n] are updated on a sample-by-sample basis.   
+ * The convergence of the LMS filter is slower compared to the normalized LMS algorithm.   
+ *   
+ * \par Algorithm:   
+ * The output signal y[n] is computed by a standard FIR filter:   
+ * 
       
+ *     y[n] = b[0] * x[n] + b[1] * x[n-1] + b[2] * x[n-2] + ...+ b[numTaps-1] * x[n-numTaps+1]   
+ * 
       
+ *   
+ * \par   
+ * The error signal equals the difference between the reference signal d[n] and the filter output:   
+ * 
       
+ *     e[n] = d[n] - y[n].   
+ * 
       
+ *   
+ * \par   
+ * After each sample of the error signal is computed the instanteous energy of the filter state variables is calculated:   
+ * 
       
+ *    E = x[n]^2 + x[n-1]^2 + ... + x[n-numTaps+1]^2.   
+ * 
       
+ * The filter coefficients b[k] are then updated on a sample-by-sample basis:   
+ * 
       
+ *     b[k] = b[k] + e[n] * (mu/E) * x[n-k],  for k=0, 1, ..., numTaps-1   
+ * 
       
+ * where mu is the step size and controls the rate of coefficient convergence.   
+ *\par   
+ * In the APIs, pCoeffs points to a coefficient array of size numTaps.   
+ * Coefficients are stored in time reversed order.   
+ * \par   
+ * 
       
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
       
+ * \par   
+ * pState points to a state array of size numTaps + blockSize - 1.   
+ * Samples in the state buffer are stored in the order:   
+ * \par   
+ * 
       
+ *    {x[n-numTaps+1], x[n-numTaps], x[n-numTaps-1], x[n-numTaps-2]....x[0], x[1], ..., x[blockSize-1]}   
+ * 
       
+ * \par   
+ * Note that the length of the state buffer exceeds the length of the coefficient array by blockSize-1 samples.   
+ * The increased state buffer length allows circular addressing, which is traditionally used in FIR filters,   
+ * to be avoided and yields a significant speed improvement.   
+ * The state variables are updated after each block of data is processed.   
+ * \par Instance Structure   
+ * The coefficients and state variables for a filter are stored together in an instance data structure.   
+ * A separate instance structure must be defined for each filter and   
+ * coefficient and state arrays cannot be shared among instances.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Zeros out the values in the state buffer.   
+ * \par   
+ * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function.   
+ * \par Fixed-Point Behavior:   
+ * Care must be taken when using the Q15 and Q31 versions of the normalised LMS filter.   
+ * The following issues must be considered:   
+ * - Scaling of coefficients   
+ * - Overflow and saturation   
+ *   
+ * \par Scaling of Coefficients:   
+ * Filter coefficients are represented as fractional values and   
+ * coefficients are restricted to lie in the range [-1 +1).   
+ * The fixed-point functions have an additional scaling parameter postShift.   
+ * At the output of the filter's accumulator is a shift register which shifts the result by postShift bits.   
+ * This essentially scales the filter coefficients by 2^postShift and   
+ * allows the filter coefficients to exceed the range [+1 -1).   
+ * The value of postShift is set by the user based on the expected gain through the system being modeled.   
+ *   
+ * \par Overflow and Saturation:   
+ * Overflow and saturation behavior of the fixed-point Q15 and Q31 versions are   
+ * described separately as part of the function specific documentation below.   
+ */
+
+
+/**   
+ * @addtogroup LMS_NORM   
+ * @{   
+ */
+
+
+  /**   
+   * @brief Processing function for floating-point normalized LMS filter.   
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.   
+   * @param[in] *pSrc points to the block of input data.   
+   * @param[in] *pRef points to the block of reference data.   
+   * @param[out] *pOut points to the block of output data.   
+   * @param[out] *pErr points to the block of error data.   
+   * @param[in] blockSize number of samples to process.   
+   * @return none.   
+   */
+
+void arm_lms_norm_f32(
+  arm_lms_norm_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pRef,
+  float32_t * pOut,
+  float32_t * pErr,
+  uint32_t blockSize)
+{
+  float32_t *pState = S->pState;                 /* State pointer */
+  float32_t *pCoeffs = S->pCoeffs;               /* Coefficient pointer */
+  float32_t *pStateCurnt;                        /* Points to the current sample of the state */
+  float32_t *px, *pb;                            /* Temporary pointers for state and coefficient buffers */
+  float32_t mu = S->mu;                          /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  float32_t energy;                              /* Energy of the input */
+  float32_t sum, e, d;                           /* accumulator, error, reference data sample */
+  float32_t w, x0, in;                           /* weight factor, temporary variable to hold input sample and state */
+
+  /* Initializations of error,  difference, Coefficient update */
+  e = 0.0f;
+  d = 0.0f;
+  w = 0.0f;
+
+  energy = S->energy;
+  x0 = S->x0;
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= x0 * x0;
+    energy += in * in;
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result in the accumulator, store in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Calculation of Weighting factor for updating filter coefficients */
+    /* epsilon value 0.000000119209289f */
+    w = (e * mu) / (energy + 0.000000119209289f);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb += w * (*px++);
+      pb++;
+
+      *pb += w * (*px++);
+      pb++;
+
+      *pb += w * (*px++);
+      pb++;
+
+      *pb += w * (*px++);
+      pb++;
+
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb += w * (*px++);
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  S->energy = energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the   
+     satrt of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1u)/4 samples copy */
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= x0 * x0;
+    energy += in * in;
+
+    /* Set the accumulator to zero */
+    sum = 0.0f;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      sum += (*px++) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* The result in the accumulator is stored in the destination buffer. */
+    *pOut++ = sum;
+
+    /* Compute and store error */
+    d = (float32_t) (*pRef++);
+    e = d - sum;
+    *pErr++ = e;
+
+    /* Calculation of Weighting factor for updating filter coefficients */
+    /* epsilon value 0.000000119209289f */
+    w = (e * mu) / (energy + 0.000000119209289f);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCcoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb += w * (*px++);
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  S->energy = energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the       
+     satrt of the state buffer. This prepares the state buffer for the       
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Copy (numTaps - 1u) samples  */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of LMS_NORM group   
+   */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c
new file mode 100644
index 0000000000..8c2423c26d
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c
@@ -0,0 +1,97 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_lms_norm_init_f32.c   
+*   
+* Description:  Floating-point NLMS filter initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS_NORM   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for floating-point normalized LMS filter.   
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.   
+   * @param[in] numTaps  number of filter coefficients.   
+   * @param[in] *pCoeffs points to coefficient buffer.   
+   * @param[in] *pState points to state buffer.   
+   * @param[in] mu step size that controls filter coefficient updates.   
+   * @param[in] blockSize number of samples to process.   
+   * @return none.   
+   *   
+ * \par Description:   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
       
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
       
+ * The initial filter coefficients serve as a starting point for the adaptive filter.   
+ * pState points to an array of length numTaps+blockSize-1 samples,   
+ * where blockSize is the number of input samples processed by each call to arm_lms_norm_f32().   
+ */
+
+void arm_lms_norm_init_f32(
+  arm_lms_norm_instance_f32 * S,
+  uint16_t numTaps,
+  float32_t * pCoeffs,
+  float32_t * pState,
+  float32_t mu,
+  uint32_t blockSize)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(float32_t));
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Initialise Energy to zero */
+  S->energy = 0.0f;
+
+  /* Initialise x0 to zero */
+  S->x0 = 0.0f;
+
+}
+
+/**   
+ * @} end of LMS_NORM group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c
new file mode 100644
index 0000000000..a30419d9a5
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c
@@ -0,0 +1,104 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_lms_norm_init_q15.c   
+*   
+* Description:  Q15 NLMS initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**   
+ * @addtogroup LMS_NORM   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for Q15 normalized LMS filter.   
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.   
+   * @param[in] numTaps  number of filter coefficients.   
+   * @param[in] *pCoeffs points to coefficient buffer.   
+   * @param[in] *pState points to state buffer.   
+   * @param[in] mu step size that controls filter coefficient updates.   
+   * @param[in] blockSize number of samples to process.   
+   * @param[in] postShift bit shift applied to coefficients.   
+   * @return none.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
       
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
       
+ * The initial filter coefficients serve as a starting point for the adaptive filter.   
+ * pState points to the array of state variables and size of array is   
+ * numTaps+blockSize-1 samples, where blockSize is the number of input samples processed   
+ * by each call to arm_lms_norm_q15().   
+ */
+
+void arm_lms_norm_init_q15(
+  arm_lms_norm_instance_q15 * S,
+  uint16_t numTaps,
+  q15_t * pCoeffs,
+  q15_t * pState,
+  q15_t mu,
+  uint32_t blockSize,
+  uint8_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1 */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q15_t));
+
+  /* Assign post Shift value applied to coefficients */
+  S->postShift = postShift;
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Initialize reciprocal pointer table */
+  S->recipTable = armRecipTableQ15;
+
+  /* Initialise Energy to zero */
+  S->energy = 0;
+
+  /* Initialise x0 to zero */
+  S->x0 = 0;
+
+}
+
+/**   
+ * @} end of LMS_NORM group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c
new file mode 100644
index 0000000000..de28a767fd
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c
@@ -0,0 +1,103 @@
+/*-----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_lms_norm_init_q31.c   
+*   
+* Description:  Q31 NLMS initialization function.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------*/
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**   
+ * @addtogroup LMS_NORM   
+ * @{   
+ */
+
+  /**   
+   * @brief Initialization function for Q31 normalized LMS filter.   
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.   
+   * @param[in] numTaps  number of filter coefficients.   
+   * @param[in] *pCoeffs points to coefficient buffer.   
+   * @param[in] *pState points to state buffer.   
+   * @param[in] mu step size that controls filter coefficient updates.   
+   * @param[in] blockSize number of samples to process.   
+   * @param[in] postShift bit shift applied to coefficients.   
+   * @return none.   
+ *   
+ * Description:   
+ * \par   
+ * pCoeffs points to the array of filter coefficients stored in time reversed order:   
+ * 
       
+ *    {b[numTaps-1], b[numTaps-2], b[N-2], ..., b[1], b[0]}   
+ * 
       
+ * The initial filter coefficients serve as a starting point for the adaptive filter.   
+ * pState points to an array of length numTaps+blockSize-1 samples,   
+ * where blockSize is the number of input samples processed by each call to arm_lms_norm_q31().   
+ */
+
+void arm_lms_norm_init_q31(
+  arm_lms_norm_instance_q31 * S,
+  uint16_t numTaps,
+  q31_t * pCoeffs,
+  q31_t * pState,
+  q31_t mu,
+  uint32_t blockSize,
+  uint8_t postShift)
+{
+  /* Assign filter taps */
+  S->numTaps = numTaps;
+
+  /* Assign coefficient pointer */
+  S->pCoeffs = pCoeffs;
+
+  /* Clear state buffer and size is always blockSize + numTaps - 1  */
+  memset(pState, 0, (numTaps + (blockSize - 1u)) * sizeof(q31_t));
+
+  /* Assign post Shift value applied to coefficients */
+  S->postShift = postShift;
+
+  /* Assign state pointer */
+  S->pState = pState;
+
+  /* Assign Step size value */
+  S->mu = mu;
+
+  /* Initialize reciprocal pointer table */
+  S->recipTable = armRecipTableQ31;
+
+  /* Initialise Energy to zero */
+  S->energy = 0;
+
+  /* Initialise x0 to zero */
+  S->x0 = 0;
+
+}
+
+/**   
+ * @} end of LMS_NORM group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c
new file mode 100644
index 0000000000..98ea8a3d75
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c
@@ -0,0 +1,386 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_lms_norm_q15.c   
+*   
+* Description:	Q15 NLMS filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS_NORM   
+ * @{   
+ */
+
+/**   
+* @brief Processing function for Q15 normalized LMS filter.   
+* @param[in] *S points to an instance of the Q15 normalized LMS filter structure.   
+* @param[in] *pSrc points to the block of input data.   
+* @param[in] *pRef points to the block of reference data.   
+* @param[out] *pOut points to the block of output data.   
+* @param[out] *pErr points to the block of error data.   
+* @param[in] blockSize number of samples to process.   
+* @return none.   
+*   
+* Scaling and Overflow Behavior:    
+* \par    
+* The function is implemented using a 64-bit internal accumulator.    
+* Both coefficients and state variables are represented in 1.15 format and   
+* multiplications yield a 2.30 result. The 2.30 intermediate results are   
+* accumulated in a 64-bit accumulator in 34.30 format.    
+* There is no risk of internal overflow with this approach and the full   
+* precision of intermediate multiplications is preserved. After all additions   
+* have been performed, the accumulator is truncated to 34.15 format by   
+* discarding low 15 bits. Lastly, the accumulator is saturated to yield a   
+* result in 1.15 format.   
+*   
+* \par  
+* 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.   
+*   
+ */
+
+void arm_lms_norm_q15(
+  arm_lms_norm_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t *px, *pb;                                /* Temporary pointers for state and coefficient buffers */
+  q15_t mu = S->mu;                              /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q31_t energy;                                  /* Energy of the input */
+  q63_t acc;                                     /* Accumulator */
+  q15_t e = 0, d = 0;                            /* error, reference data sample */
+  q15_t w = 0, in;                               /* weight factor and state */
+  q15_t x0;                                      /* temporary variable to hold input sample */
+  uint32_t shift = (uint32_t) S->postShift + 1u; /* Shift to be applied to the output */
+  q15_t errorXmu, oneByEnergy;                   /* Temporary variables to store error and mu product and reciprocal of energy */
+  q15_t postShift;                               /* Post shift to be applied to weight after reciprocal calculation */
+  q31_t coef;                                    /* Teporary variable for coefficient */
+
+  energy = S->energy;
+  x0 = S->x0;
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= (((q31_t) x0 * (x0)) >> 15);
+    energy += (((q31_t) in * (in)) >> 15);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+
+      /* Perform the multiply-accumulate */
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (((q31_t) * px++ * (*pb++)));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.15 format */
+    acc = __SSAT((acc >> (16u - shift)), 16u);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q15_t) acc;
+    *pErr++ = e;
+
+    /* Calculation of 1/energy */
+    postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
+                              &oneByEnergy, S->recipTable);
+
+    /* Calculation of e * mu value */
+    errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
+
+    /* Calculation of (e * mu) * (1/energy) value */
+    acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
+
+    /* Weighting factor for the normalized version */
+    w = (q15_t) __SSAT((q31_t) acc, 16);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q15_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the   
+     satrt of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy -= (((q31_t) x0 * (x0)) >> 15);
+    energy += (((q31_t) in * (in)) >> 15);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (((q31_t) * px++ * (*pb++)));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.15 format */
+    acc = __SSAT((acc >> (16u - shift)), 16u);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q15_t) acc;
+    *pErr++ = e;
+
+    /* Calculation of 1/energy */
+    postShift = arm_recip_q15((q15_t) energy + DELTA_Q15,
+                              &oneByEnergy, S->recipTable);
+
+    /* Calculation of e * mu value */
+    errorXmu = (q15_t) (((q31_t) e * mu) >> 15);
+
+    /* Calculation of (e * mu) * (1/energy) value */
+    acc = (((q31_t) errorXmu * oneByEnergy) >> (15 - postShift));
+
+    /* Weighting factor for the normalized version */
+    w = (q15_t) __SSAT((q31_t) acc, 16);
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = *pb + (((q31_t) w * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q15_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the       
+     satrt of the state buffer. This prepares the state buffer for the       
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* copy (numTaps - 1u) data */
+  tapCnt = (numTaps - 1u);
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+
+/**   
+   * @} end of LMS_NORM group   
+   */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c
new file mode 100644
index 0000000000..c35a72f688
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c
@@ -0,0 +1,404 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_lms_norm_q31.c   
+*   
+* Description:	Processing function for the Q31 NLMS filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS_NORM   
+ * @{   
+ */
+
+/**   
+* @brief Processing function for Q31 normalized LMS filter.   
+* @param[in] *S points to an instance of the Q31 normalized LMS filter structure.   
+* @param[in] *pSrc points to the block of input data.   
+* @param[in] *pRef points to the block of reference data.   
+* @param[out] *pOut points to the block of output data.   
+* @param[out] *pErr points to the block of error data.   
+* @param[in] blockSize number of samples to process.   
+* @return none.   
+*   
+* Scaling and Overflow Behavior:    
+* \par    
+* The function is implemented using an internal 64-bit accumulator.    
+* The accumulator has a 2.62 format and maintains full precision of the intermediate  
+* multiplication results but provides only a single guard bit.    
+* Thus, if the accumulator result overflows it wraps around rather than clip.    
+* In order to avoid overflows completely the input signal must be scaled down by   
+* log2(numTaps) bits. The reference signal should not be scaled down.    
+* After all multiply-accumulates are performed, the 2.62 accumulator is shifted   
+* and saturated to 1.31 format to yield the final result.    
+* The output signal and error signal are in 1.31 format.    
+*   
+* \par   
+* 	In this filter, filter coefficients are updated for each sample and the   
+* updation of filter cofficients are saturted.   
+*    
+*/
+
+void arm_lms_norm_q31(
+  arm_lms_norm_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t *px, *pb;                                /* Temporary pointers for state and coefficient buffers */
+  q31_t mu = S->mu;                              /* Adaptive factor */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q63_t energy;                                  /* Energy of the input */
+  q63_t acc;                                     /* Accumulator */
+  q31_t e = 0, d = 0;                            /* error, reference data sample */
+  q31_t w = 0, in;                               /* weight factor and state */
+  q31_t x0;                                      /* temporary variable to hold input sample */
+  uint32_t shift = 32u - ((uint32_t) S->postShift + 1u);        /* Shift to be applied to the output */
+  q31_t errorXmu, oneByEnergy;                   /* Temporary variables to store error and mu product and reciprocal of energy */
+  q31_t postShift;                               /* Post shift to be applied to weight after reciprocal calculation */
+  q31_t coef;                                    /* Temporary variable for coef */
+
+  energy = S->energy;
+  x0 = S->x0;
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy = (q31_t) ((((q63_t) energy << 32) -
+                       (((q63_t) x0 * x0) << 1)) >> 32);
+    energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+      acc += ((q63_t) (*px++)) * (*pb++);
+      acc += ((q63_t) (*px++)) * (*pb++);
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    acc = (q31_t) (acc >> shift);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q31_t) acc;
+    *pErr++ = e;
+
+    /* Calculates the reciprocal of energy */
+    postShift = arm_recip_q31(energy + DELTA_Q31,
+                              &oneByEnergy, &S->recipTable[0]);
+
+    /* Calculation of product of (e * mu) */
+    errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Weighting factor for the normalized version */
+    w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+
+      /* coef is in 2.30 format */
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      /* get coef in 1.31 format by left shifting */
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      /* update coefficient buffer to next coefficient */
+      pb++;
+
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q31_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the   
+     satrt of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1u) samples copy */
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Read the sample from input buffer */
+    in = *pSrc++;
+
+    /* Update the energy calculation */
+    energy =
+      (q31_t) ((((q63_t) energy << 32) - (((q63_t) x0 * x0) << 1)) >> 32);
+    energy = (q31_t) (((((q63_t) in * in) << 1) + (energy << 32)) >> 32);
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    acc = (q31_t) (acc >> shift);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    d = *pRef++;
+    e = d - (q31_t) acc;
+    *pErr++ = e;
+
+    /* Calculates the reciprocal of energy */
+    postShift =
+      arm_recip_q31(energy + DELTA_Q31, &oneByEnergy, &S->recipTable[0]);
+
+    /* Calculation of product of (e * mu) */
+    errorXmu = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Weighting factor for the normalized version */
+    w = clip_q63_to_q31(((q63_t) errorXmu * oneByEnergy) >> (31 - postShift));
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize coeff pointer */
+    pb = (pCoeffs);
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      /* coef is in 2.30 format */
+      coef = (q31_t) (((q63_t) w * (*px++)) >> (32));
+      /* get coef in 1.31 format by left shifting */
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      /* update coefficient buffer to next coefficient */
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Read the sample from state buffer */
+    x0 = *pState;
+
+    /* Advance state pointer by 1 for the next sample */
+    pState = pState + 1;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Save energy and x0 values for the next frame */
+  S->energy = (q31_t) energy;
+  S->x0 = x0;
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
+     start of the state buffer. This prepares the state buffer for the       
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop for (numTaps - 1u) samples copy */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of LMS_NORM group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c
new file mode 100644
index 0000000000..7144248252
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c
@@ -0,0 +1,331 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_lms_q15.c   
+*   
+* Description:	Processing function for the Q15 LMS filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS   
+ * @{   
+ */
+
+ /**   
+ * @brief Processing function for Q15 LMS filter.   
+ * @param[in] *S points to an instance of the Q15 LMS filter structure.   
+ * @param[in] *pSrc points to the block of input data.   
+ * @param[in] *pRef points to the block of reference data.   
+ * @param[out] *pOut points to the block of output data.   
+ * @param[out] *pErr points to the block of error data.   
+ * @param[in] blockSize number of samples to process.   
+ * @return none.   
+ *   
+ * \par Scaling and Overflow Behavior:   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * Both coefficients and state variables are represented in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format.   
+ * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved.   
+ * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits.   
+ * Lastly, the accumulator is saturated to yield a result in 1.15 format.   
+ *  
+ * \par  
+ * 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.  
+ *   
+ */
+
+void arm_lms_q15(
+  const arm_lms_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pRef,
+  q15_t * pOut,
+  q15_t * pErr,
+  uint32_t blockSize)
+{
+  q15_t *pState = S->pState;                     /* State pointer */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  q15_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q15_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q15_t mu = S->mu;                              /* Adaptive factor */
+  q15_t *px;                                     /* Temporary pointer for state */
+  q15_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q63_t acc;                                     /* Accumulator */
+  q15_t e = 0;                                   /* error of data sample */
+  q15_t alpha;                                   /* Intermediate constant for taps update */
+  uint32_t shift = S->postShift + 1u;            /* Shift to be applied to the output */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t coef;                                    /* Teporary variable for coefficient */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initializing blkCnt with blockSize */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2u;
+
+    while(tapCnt > 0u)
+    {
+      /* acc +=  b[N] * x[n-N] + b[N-1] * x[n-N-1] */
+      /* Perform the multiply-accumulate */
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+      acc = __SMLALD(*__SIMD32(px)++, (*__SIMD32(pb)++), acc);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (q63_t) (((q31_t) (*px++) * (*pb++)));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.15 format and saturate the output */
+    acc = __SSAT((acc >> (16 - shift)), 16);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q15_t) acc;
+
+    *pErr++ = (q15_t) e;
+
+    /* Compute alpha i.e. intermediate constant for taps update */
+    alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
+
+    /* Initialize state pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2u;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) * pb + (((q31_t) alpha * (*px++)) >> 15);
+      *pb++ = (q15_t) __SSAT((coef), 16);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the   
+     satrt of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Calculation of count for copying integer writes */
+  tapCnt = (numTaps - 1u) >> 2;
+
+  while(tapCnt > 0u)
+  {
+
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+    *__SIMD32(pStateCurnt)++ = *__SIMD32(pState)++;
+
+    tapCnt--;
+
+  }
+
+  /* Calculation of count for remaining q15_t data */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += (q63_t) ((q31_t) (*px++) * (*pb++));
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.15 format and saturate the output */
+    acc = __SSAT((acc >> (16 - shift)), 16);
+
+    /* Store the result from accumulator into the destination buffer. */
+    *pOut++ = (q15_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q15_t) acc;
+
+    *pErr++ = (q15_t) e;
+
+    /* Compute alpha i.e. intermediate constant for taps update */
+    alpha = (q15_t) (((q31_t) e * (mu)) >> 15);
+
+    /* Initialize pState pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      *pb++ += (q15_t) (((q31_t) alpha * (*px++)) >> 15);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the       
+     start of the state buffer. This prepares the state buffer for the  
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /*  Copy (numTaps - 1u) samples  */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of LMS group   
+   */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c
new file mode 100644
index 0000000000..0c9ca3ef63
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c
@@ -0,0 +1,347 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_lms_q31.c   
+*   
+* Description:	Processing function for the Q31 LMS filter.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+/**   
+ * @ingroup groupFilters   
+ */
+
+/**   
+ * @addtogroup LMS   
+ * @{   
+ */
+
+ /**   
+ * @brief Processing function for Q31 LMS filter.   
+ * @param[in]  *S points to an instance of the Q15 LMS filter structure.   
+ * @param[in]  *pSrc points to the block of input data.   
+ * @param[in]  *pRef points to the block of reference data.   
+ * @param[out] *pOut points to the block of output data.   
+ * @param[out] *pErr points to the block of error data.   
+ * @param[in]  blockSize number of samples to process.   
+ * @return     none.   
+ *   
+ * \par Scaling and Overflow Behavior:    
+ * The function is implemented using an internal 64-bit accumulator.    
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate   
+ * multiplication results but provides only a single guard bit.    
+ * Thus, if the accumulator result overflows it wraps around rather than clips.    
+ * In order to avoid overflows completely the input signal must be scaled down by   
+ * log2(numTaps) bits.    
+ * The reference signal should not be scaled down.    
+ * After all multiply-accumulates are performed, the 2.62 accumulator is shifted   
+ * and saturated to 1.31 format to yield the final result.    
+ * The output signal and error signal are in 1.31 format.    
+ *   
+ * \par   
+ * 	In this filter, filter coefficients are updated for each sample and the updation of filter cofficients are saturted.   
+ */
+
+void arm_lms_q31(
+  const arm_lms_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pRef,
+  q31_t * pOut,
+  q31_t * pErr,
+  uint32_t blockSize)
+{
+  q31_t *pState = S->pState;                     /* State pointer */
+  uint32_t numTaps = S->numTaps;                 /* Number of filter coefficients in the filter */
+  q31_t *pCoeffs = S->pCoeffs;                   /* Coefficient pointer */
+  q31_t *pStateCurnt;                            /* Points to the current sample of the state */
+  q31_t mu = S->mu;                              /* Adaptive factor */
+  q31_t *px;                                     /* Temporary pointer for state */
+  q31_t *pb;                                     /* Temporary pointer for coefficient buffer */
+  uint32_t tapCnt, blkCnt;                       /* Loop counters */
+  q63_t acc;                                     /* Accumulator */
+  q31_t e = 0;                                   /* error of data sample */
+  q31_t alpha;                                   /* Intermediate constant for taps update */
+  uint8_t shift = (uint8_t) (32u - (S->postShift + 1u));        /* Shift to be applied to the output */
+  q31_t coef;                                    /* Temporary variable for coef */
+
+  /* S->pState points to buffer which contains previous frame (numTaps - 1) samples */
+  /* pStateCurnt points to the location where the new input data should be written */
+  pStateCurnt = &(S->pState[(numTaps - 1u)]);
+
+  /* Initializing blkCnt with blockSize */
+  blkCnt = blockSize;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize state pointer */
+    px = pState;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      /* acc +=  b[N] * x[n-N] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* acc +=  b[N-1] * x[n-N-1] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* acc +=  b[N-2] * x[n-N-2] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* acc +=  b[N-3] * x[n-N-3] */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    /* Store the result from accumulator into the destination buffer. */
+    acc = (q31_t) (acc >> shift);
+
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q31_t) acc;
+
+    *pErr++ = (q31_t) e;
+
+    /* Compute alpha i.e. intermediate constant for taps update */
+    alpha = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Initialize state pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize coefficient pointer */
+    pb = pCoeffs;
+
+    /* Loop unrolling.  Process 4 taps at a time. */
+    tapCnt = numTaps >> 2;
+
+    /* Update filter coefficients */
+    while(tapCnt > 0u)
+    {
+      /* coef is in 2.30 format */
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      /* get coef in 1.31 format by left shifting */
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      /* update coefficient buffer to next coefficient */
+      pb++;
+
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* If the filter length is not a multiple of 4, compute the remaining filter taps */
+    tapCnt = numTaps % 0x4u;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb = clip_q63_to_q31((q63_t) * pb + (coef << 1u));
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the   
+     satrt of the state buffer. This prepares the state buffer for the   
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /* Loop unrolling for (numTaps - 1u) samples copy */
+  tapCnt = (numTaps - 1u) >> 2u;
+
+  /* copy data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+  /* Calculate remaining number of copies */
+  tapCnt = (numTaps - 1u) % 0x4u;
+
+  /* Copy the remaining q31_t data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Copy the new input sample into the state buffer */
+    *pStateCurnt++ = *pSrc++;
+
+    /* Initialize pState pointer */
+    px = pState;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Set the accumulator to zero */
+    acc = 0;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      acc += ((q63_t) (*px++)) * (*pb++);
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Converting the result to 1.31 format */
+    /* Store the result from accumulator into the destination buffer. */
+    acc = (q31_t) (acc >> shift);
+
+    *pOut++ = (q31_t) acc;
+
+    /* Compute and store error */
+    e = *pRef++ - (q31_t) acc;
+
+    *pErr++ = (q31_t) e;
+
+    /* Weighting factor for the LMS version */
+    alpha = (q31_t) (((q63_t) e * mu) >> 31);
+
+    /* Initialize pState pointer */
+    /* Advance state pointer by 1 for the next sample */
+    px = pState++;
+
+    /* Initialize pCoeffs pointer */
+    pb = pCoeffs;
+
+    /* Loop over numTaps number of values */
+    tapCnt = numTaps;
+
+    while(tapCnt > 0u)
+    {
+      /* Perform the multiply-accumulate */
+      coef = (q31_t) (((q63_t) alpha * (*px++)) >> (32));
+      *pb += (coef << 1u);
+      pb++;
+
+      /* Decrement the loop counter */
+      tapCnt--;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Processing is complete. Now copy the last numTaps - 1 samples to the    
+     start of the state buffer. This prepares the state buffer for the  
+     next function call. */
+
+  /* Points to the start of the pState buffer */
+  pStateCurnt = S->pState;
+
+  /*  Copy (numTaps - 1u) samples  */
+  tapCnt = (numTaps - 1u);
+
+  /* Copy the data */
+  while(tapCnt > 0u)
+  {
+    *pStateCurnt++ = *pState++;
+
+    /* Decrement the loop counter */
+    tapCnt--;
+  }
+
+#endif /*   #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of LMS group   
+   */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c
new file mode 100644
index 0000000000..32eb69c41a
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c
@@ -0,0 +1,154 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_mat_add_f32.c   
+*   
+* Description:	Floating-point matrix addition   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixAdd Matrix Addition   
+ *   
+ * Adds two matrices.   
+ * \image html MatrixAddition.gif "Addition of two 3 x 3 matrices"   
+ *   
+ * The functions check to make sure that   
+ * pSrcA, pSrcB, and pDst have the same   
+ * number of rows and columns.   
+ */
+
+/**   
+ * @addtogroup MatrixAdd   
+ * @{   
+ */
+
+
+/**   
+ * @brief Floating-point matrix addition.   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ */
+
+arm_status arm_mat_add_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A  */
+  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B  */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer   */
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add and then store the results in the destination buffer. */
+      *pOut++ = (*pIn1++) + (*pIn2++);
+      *pOut++ = (*pIn1++) + (*pIn2++);
+      *pOut++ = (*pIn1++) + (*pIn2++);
+      *pOut++ = (*pIn1++) + (*pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add and then store the results in the destination buffer. */
+      *pOut++ = (*pIn1++) + (*pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixAdd group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c
new file mode 100644
index 0000000000..e16460061e
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c
@@ -0,0 +1,158 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_add_q15.c   
+*   
+* Description:	Q15 matrix addition   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixAdd   
+ * @{   
+ */
+
+/**   
+ * @brief Q15 matrix addition.   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.   
+ */
+
+arm_status arm_mat_add_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A  */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint16_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters  */
+  arm_status status;                             /* status of matrix addition  */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint16_t) (pSrcA->numRows * pSrcA->numCols);
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop unrolling */
+    blkCnt = (uint32_t) numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, Saturate and then store the results in the destination buffer. */
+      *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+      *__SIMD32(pOut)++ = __QADD16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = (uint32_t) numSamples % 0x4u;
+
+    /* q15 pointers of input and output are initialized */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, Saturate and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __QADD16(*pInA++, *pInB++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = (uint32_t) numSamples;
+
+
+    /* q15 pointers of input and output are initialized */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, Saturate and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ + *pInB++), 16);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixAdd group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c
new file mode 100644
index 0000000000..3d4563ca17
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c
@@ -0,0 +1,157 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_add_q31.c   
+*   
+* Description:	Q31 matrix addition   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixAdd   
+ * @{   
+ */
+
+/**   
+ * @brief Q31 matrix addition.   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.   
+ */
+
+arm_status arm_mat_add_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix addition */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2u;
+
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, saturate and then store the results in the destination buffer. */
+      *pOut++ = __QADD(*pIn1++, *pIn2++);
+      *pOut++ = __QADD(*pIn1++, *pIn2++);
+      *pOut++ = __QADD(*pIn1++, *pIn2++);
+      *pOut++ = __QADD(*pIn1++, *pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, saturate and then store the results in the destination buffer. */
+      *pOut++ = __QADD(*pIn1++, *pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) + B(m,n) */
+      /* Add, saturate and then store the results in the destination buffer. */
+      *pOut++ = clip_q63_to_q31(((q63_t) (*pIn1++)) + (*pIn2++));
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixAdd group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c
new file mode 100644
index 0000000000..96dbc53fd7
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c
@@ -0,0 +1,83 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_mat_init_f32.c   
+*   
+* Description:	Floating-point matrix initialization.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixInit Matrix Initialization   
+ *   
+ * Initializes the underlying matrix data structure.   
+ * The functions set the numRows,   
+ * numCols, and pData fields   
+ * of the matrix data structure.   
+ */
+
+/**   
+ * @addtogroup MatrixInit   
+ * @{   
+ */
+
+/**   
+   * @brief  Floating-point matrix initialization.   
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.   
+   * @param[in]     nRows          number of rows in the matrix.   
+   * @param[in]     nColumns       number of columns in the matrix.   
+   * @param[in]     *pData	   points to the matrix data array.   
+   * @return        none   
+   */
+
+void arm_mat_init_f32(
+  arm_matrix_instance_f32 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  float32_t * pData)
+{
+  /* Assign Number of Rows */
+  S->numRows = nRows;
+
+  /* Assign Number of Columns */
+  S->numCols = nColumns;
+
+  /* Assign Data pointer */
+  S->pData = pData;
+}
+
+/**   
+ * @} end of MatrixInit group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c
new file mode 100644
index 0000000000..8c7fb44df8
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c
@@ -0,0 +1,75 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_mat_init_q15.c   
+*   
+* Description:	Q15 matrix initialization.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixInit   
+ * @{   
+ */
+
+  /**   
+   * @brief  Q15 matrix initialization.   
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.   
+   * @param[in]     nRows          number of rows in the matrix.   
+   * @param[in]     nColumns       number of columns in the matrix.   
+   * @param[in]     *pData	   points to the matrix data array.   
+   * @return        none   
+   */
+
+void arm_mat_init_q15(
+  arm_matrix_instance_q15 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q15_t * pData)
+{
+  /* Assign Number of Rows */
+  S->numRows = nRows;
+
+  /* Assign Number of Columns */
+  S->numCols = nColumns;
+
+  /* Assign Data pointer */
+  S->pData = pData;
+}
+
+/**   
+ * @} end of MatrixInit group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c
new file mode 100644
index 0000000000..efe0bbd3c7
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c
@@ -0,0 +1,79 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_mat_init_q31.c   
+*   
+* Description:	Q31 matrix initialization.   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixInit Matrix Initialization   
+ *   
+ */
+
+/**   
+ * @addtogroup MatrixInit   
+ * @{   
+ */
+
+  /**   
+   * @brief  Q31 matrix initialization.   
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.   
+   * @param[in]     nRows          number of rows in the matrix.   
+   * @param[in]     nColumns       number of columns in the matrix.   
+   * @param[in]     *pData	   points to the matrix data array.   
+   * @return        none   
+   */
+
+void arm_mat_init_q31(
+  arm_matrix_instance_q31 * S,
+  uint16_t nRows,
+  uint16_t nColumns,
+  q31_t * pData)
+{
+  /* Assign Number of Rows */
+  S->numRows = nRows;
+
+  /* Assign Number of Columns */
+  S->numCols = nColumns;
+
+  /* Assign Data pointer */
+  S->pData = pData;
+}
+
+/**   
+ * @} end of MatrixInit group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c
new file mode 100644
index 0000000000..cd635c8cbd
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c
@@ -0,0 +1,665 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_inverse_f32.c   
+*   
+* Description:	Floating-point matrix inverse.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixInv Matrix Inverse   
+ *   
+ * Computes the inverse of a matrix.   
+ *   
+ * The inverse is defined only if the input matrix is square and non-singular (the determinant   
+ * is non-zero). The function checks that the input and output matrices are square and of the   
+ * same size.   
+ *   
+ * Matrix inversion is numerically sensitive and the CMSIS DSP library only supports matrix   
+ * inversion of floating-point matrices.   
+ *   
+ * \par Algorithm   
+ * The Gauss-Jordan method is used to find the inverse.   
+ * The algorithm performs a sequence of elementary row-operations till it   
+ * reduces the input matrix to an identity matrix. Applying the same sequence   
+ * of elementary row-operations to an identity matrix yields the inverse matrix.   
+ * If the input matrix is singular, then the algorithm terminates and returns error status   
+ * ARM_MATH_SINGULAR.   
+ * \image html MatrixInverse.gif "Matrix Inverse of a 3 x 3 matrix using Gauss-Jordan Method"   
+ */
+
+/**   
+ * @addtogroup MatrixInv   
+ * @{   
+ */
+
+/**   
+ * @brief Floating-point matrix inverse.   
+ * @param[in]       *pSrc points to input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns   
+ * ARM_MATH_SIZE_MISMATCH if the input matrix is not square or if the size   
+ * of the output matrix does not match the size of the input matrix.   
+ * If the input matrix is found to be singular (non-invertible), then the function returns   
+ * ARM_MATH_SINGULAR.  Otherwise, the function returns ARM_MATH_SUCCESS.   
+ */
+
+arm_status arm_mat_inverse_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float32_t *pInT1, *pInT2;                      /* Temporary input data matrix pointer */
+  float32_t *pInT3, *pInT4;                      /* Temporary output data matrix pointer */
+  float32_t *pPivotRowIn, *pPRT_in, *pPivotRowDst, *pPRT_pDst;  /* Temporary input and output data matrix pointer */
+  uint32_t numRows = pSrc->numRows;              /* Number of rows in the matrix  */
+  uint32_t numCols = pSrc->numCols;              /* Number of Cols in the matrix  */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t Xchg, in = 0.0f, in1;                /* Temporary input values  */
+  uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l;      /* loop counters */
+  arm_status status;                             /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+     || (pSrc->numRows != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+
+    /*--------------------------------------------------------------------------------------------------------------   
+	 * Matrix Inverse can be solved using elementary row operations.   
+	 *   
+	 *	Gauss-Jordan Method:   
+	 *   
+	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an   
+	 *        augmented matrix as follows:   
+	 *				        _ 	      	       _         _	       _   
+	 *					   |  a11  a12 | 1   0  |       |  X11 X12  |   
+	 *					   |           |        |   =   |           |   
+	 *					   |_ a21  a22 | 0   1 _|       |_ X21 X21 _|   
+	 *   
+	 *		2. In our implementation, pDst Matrix is used as identity matrix.   
+	 *   
+	 *		3. Begin with the first row. Let i = 1.   
+	 *   
+	 *	    4. Check to see if the pivot for row i is zero.   
+	 *		   The pivot is the element of the main diagonal that is on the current row.   
+	 *		   For instance, if working with row i, then the pivot element is aii.   
+	 *		   If the pivot is zero, exchange that row with a row below it that does not   
+	 *		   contain a zero in column i. If this is not possible, then an inverse   
+	 *		   to that matrix does not exist.   
+	 *   
+	 *	    5. Divide every element of row i by the pivot.   
+	 *   
+	 *	    6. For every row below and  row i, replace that row with the sum of that row and   
+	 *		   a multiple of row i so that each new element in column i below row i is zero.   
+	 *   
+	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros   
+	 *		   for every element below and above the main diagonal.   
+	 *   
+	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, pSrc).   
+	 *		   Therefore, the matrix to the right of the bar is our solution(pDst matrix, pDst).   
+	 *----------------------------------------------------------------------------------------------------------------*/
+
+    /* Working pointer for destination matrix */
+    pInT2 = pOut;
+
+    /* Loop over the number of rows */
+    rowCnt = numRows;
+
+    /* Making the destination matrix as identity matrix */
+    while(rowCnt > 0u)
+    {
+      /* Writing all zeroes in lower triangle of the destination matrix */
+      j = numRows - rowCnt;
+      while(j > 0u)
+      {
+        *pInT2++ = 0.0f;
+        j--;
+      }
+
+      /* Writing all ones in the diagonal of the destination matrix */
+      *pInT2++ = 1.0f;
+
+      /* Writing all zeroes in upper triangle of the destination matrix */
+      j = rowCnt - 1u;
+      while(j > 0u)
+      {
+        *pInT2++ = 0.0f;
+        j--;
+      }
+
+      /* Decrement the loop counter */
+      rowCnt--;
+    }
+
+    /* Loop over the number of columns of the input matrix.   
+       All the elements in each column are processed by the row operations */
+    loopCnt = numCols;
+
+    /* Index modifier to navigate through the columns */
+    l = 0u;
+
+    while(loopCnt > 0u)
+    {
+      /* Check if the pivot element is zero..   
+       * If it is zero then interchange the row with non zero row below.   
+       * If there is no non zero element to replace in the rows below,   
+       * then the matrix is Singular. */
+
+      /* Working pointer for the input matrix that points   
+       * to the pivot element of the particular row  */
+      pInT1 = pIn + (l * numCols);
+
+      /* Working pointer for the destination matrix that points   
+       * to the pivot element of the particular row  */
+      pInT3 = pOut + (l * numCols);
+
+      /* Temporary variable to hold the pivot value */
+      in = *pInT1;
+
+      /* Destination pointer modifier */
+      k = 1u;
+
+      /* Check if the pivot element is zero */
+      if(*pInT1 == 0.0f)
+      {
+        /* Loop over the number rows present below */
+        i = numRows - (l + 1u);
+
+        while(i > 0u)
+        {
+          /* Update the input and destination pointers */
+          pInT2 = pInT1 + (numCols * l);
+          pInT4 = pInT3 + (numCols * k);
+
+          /* Check if there is a non zero pivot element to   
+           * replace in the rows below */
+          if(*pInT2 != 0.0f)
+          {
+            /* Loop over number of columns   
+             * to the right of the pilot element */
+            j = numCols - l;
+
+            while(j > 0u)
+            {
+              /* Exchange the row elements of the input matrix */
+              Xchg = *pInT2;
+              *pInT2++ = *pInT1;
+              *pInT1++ = Xchg;
+
+              /* Decrement the loop counter */
+              j--;
+            }
+
+            /* Loop over number of columns of the destination matrix */
+            j = numCols;
+
+            while(j > 0u)
+            {
+              /* Exchange the row elements of the destination matrix */
+              Xchg = *pInT4;
+              *pInT4++ = *pInT3;
+              *pInT3++ = Xchg;
+
+              /* Decrement the loop counter */
+              j--;
+            }
+
+            /* Flag to indicate whether exchange is done or not */
+            flag = 1u;
+
+            /* Break after exchange is done */
+            break;
+          }
+
+          /* Update the destination pointer modifier */
+          k++;
+
+          /* Decrement the loop counter */
+          i--;
+        }
+      }
+
+      /* Update the status if the matrix is singular */
+      if((flag != 1u) && (in == 0.0f))
+      {
+        status = ARM_MATH_SINGULAR;
+
+        break;
+      }
+
+      /* Points to the pivot row of input and destination matrices */
+      pPivotRowIn = pIn + (l * numCols);
+      pPivotRowDst = pOut + (l * numCols);
+
+      /* Temporary pointers to the pivot row pointers */
+      pInT1 = pPivotRowIn;
+      pInT2 = pPivotRowDst;
+
+      /* Pivot element of the row */
+      in = *(pIn + (l * numCols));
+
+      /* Loop over number of columns   
+       * to the right of the pilot element */
+      j = (numCols - l);
+
+      while(j > 0u)
+      {
+        /* Divide each element of the row of the input matrix   
+         * by the pivot element */
+        in1 = *pInT1;
+        *pInT1++ = in1 / in;
+
+        /* Decrement the loop counter */
+        j--;
+      }
+
+      /* Loop over number of columns of the destination matrix */
+      j = numCols;
+
+      while(j > 0u)
+      {
+        /* Divide each element of the row of the destination matrix   
+         * by the pivot element */
+        in1 = *pInT2;
+        *pInT2++ = in1 / in;
+
+        /* Decrement the loop counter */
+        j--;
+      }
+
+      /* Replace the rows with the sum of that row and a multiple of row i   
+       * so that each new element in column i above row i is zero.*/
+
+      /* Temporary pointers for input and destination matrices */
+      pInT1 = pIn;
+      pInT2 = pOut;
+
+      /* index used to check for pivot element */
+      i = 0u;
+
+      /* Loop over number of rows */
+      /*  to be replaced by the sum of that row and a multiple of row i */
+      k = numRows;
+
+      while(k > 0u)
+      {
+        /* Check for the pivot element */
+        if(i == l)
+        {
+          /* If the processing element is the pivot element,   
+             only the columns to the right are to be processed */
+          pInT1 += numCols - l;
+
+          pInT2 += numCols;
+        }
+        else
+        {
+          /* Element of the reference row */
+          in = *pInT1;
+
+          /* Working pointers for input and destination pivot rows */
+          pPRT_in = pPivotRowIn;
+          pPRT_pDst = pPivotRowDst;
+
+          /* Loop over the number of columns to the right of the pivot element,   
+             to replace the elements in the input matrix */
+          j = (numCols - l);
+
+          while(j > 0u)
+          {
+            /* Replace the element by the sum of that row   
+               and a multiple of the reference row  */
+            in1 = *pInT1;
+            *pInT1++ = in1 - (in * *pPRT_in++);
+
+            /* Decrement the loop counter */
+            j--;
+          }
+
+          /* Loop over the number of columns to   
+             replace the elements in the destination matrix */
+          j = numCols;
+
+          while(j > 0u)
+          {
+            /* Replace the element by the sum of that row   
+               and a multiple of the reference row  */
+            in1 = *pInT2;
+            *pInT2++ = in1 - (in * *pPRT_pDst++);
+
+            /* Decrement the loop counter */
+            j--;
+          }
+
+        }
+
+        /* Increment the temporary input pointer */
+        pInT1 = pInT1 + l;
+
+        /* Decrement the loop counter */
+        k--;
+
+        /* Increment the pivot index */
+        i++;
+      }
+
+      /* Increment the input pointer */
+      pIn++;
+
+      /* Decrement the loop counter */
+      loopCnt--;
+
+      /* Increment the index modifier */
+      l++;
+    }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t Xchg, in = 0.0f;                     /* Temporary input values  */
+  uint32_t i, rowCnt, flag = 0u, j, loopCnt, k, l;      /* loop counters */
+  arm_status status;                             /* status of matrix inverse */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pSrc->numCols) || (pDst->numRows != pDst->numCols)
+     || (pSrc->numRows != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+  {
+
+    /*--------------------------------------------------------------------------------------------------------------      
+	 * Matrix Inverse can be solved using elementary row operations.       
+	 *       
+	 *	Gauss-Jordan Method:      
+	 *	 	      
+	 *	   1. First combine the identity matrix and the input matrix separated by a bar to form an       
+	 *        augmented matrix as follows:       
+	 *				        _  _	      _	    _	   _   _         _	       _      
+	 *					   |  |  a11  a12  | | | 1   0  |   |       |  X11 X12  |        
+	 *					   |  |            | | |        |   |   =   |           |       
+	 *					   |_ |_ a21  a22 _| | |_0   1 _|  _|       |_ X21 X21 _|      
+	 *					         
+	 *		2. In our implementation, pDst Matrix is used as identity matrix.   
+	 *      
+	 *		3. Begin with the first row. Let i = 1.      
+	 *      
+	 *	    4. Check to see if the pivot for row i is zero.      
+	 *		   The pivot is the element of the main diagonal that is on the current row.      
+	 *		   For instance, if working with row i, then the pivot element is aii.      
+	 *		   If the pivot is zero, exchange that row with a row below it that does not       
+	 *		   contain a zero in column i. If this is not possible, then an inverse       
+	 *		   to that matrix does not exist.      
+	 *	      
+	 *	    5. Divide every element of row i by the pivot.      
+	 *	      
+	 *	    6. For every row below and  row i, replace that row with the sum of that row and       
+	 *		   a multiple of row i so that each new element in column i below row i is zero.      
+	 *	      
+	 *	    7. Move to the next row and column and repeat steps 2 through 5 until you have zeros      
+	 *		   for every element below and above the main diagonal.       
+	 *		   		         
+	 *		8. Now an identical matrix is formed to the left of the bar(input matrix, src).      
+	 *		   Therefore, the matrix to the right of the bar is our solution(dst matrix, dst).        
+	 *----------------------------------------------------------------------------------------------------------------*/
+
+    /* Working pointer for destination matrix */
+    pInT2 = pOut;
+
+    /* Loop over the number of rows */
+    rowCnt = numRows;
+
+    /* Making the destination matrix as identity matrix */
+    while(rowCnt > 0u)
+    {
+      /* Writing all zeroes in lower triangle of the destination matrix */
+      j = numRows - rowCnt;
+      while(j > 0u)
+      {
+        *pInT2++ = 0.0f;
+        j--;
+      }
+
+      /* Writing all ones in the diagonal of the destination matrix */
+      *pInT2++ = 1.0f;
+
+      /* Writing all zeroes in upper triangle of the destination matrix */
+      j = rowCnt - 1u;
+      while(j > 0u)
+      {
+        *pInT2++ = 0.0f;
+        j--;
+      }
+
+      /* Decrement the loop counter */
+      rowCnt--;
+    }
+
+    /* Loop over the number of columns of the input matrix.    
+       All the elements in each column are processed by the row operations */
+    loopCnt = numCols;
+
+    /* Index modifier to navigate through the columns */
+    l = 0u;
+    //for(loopCnt = 0u; loopCnt < numCols; loopCnt++)  
+    while(loopCnt > 0u)
+    {
+      /* Check if the pivot element is zero..   
+       * If it is zero then interchange the row with non zero row below.  
+       * If there is no non zero element to replace in the rows below,  
+       * then the matrix is Singular. */
+
+      /* Working pointer for the input matrix that points    
+       * to the pivot element of the particular row  */
+      pInT1 = pIn + (l * numCols);
+
+      /* Working pointer for the destination matrix that points    
+       * to the pivot element of the particular row  */
+      pInT3 = pOut + (l * numCols);
+
+      /* Temporary variable to hold the pivot value */
+      in = *pInT1;
+
+      /* Destination pointer modifier */
+      k = 1u;
+
+      /* Check if the pivot element is zero */
+      if(*pInT1 == 0.0f)
+      {
+        /* Loop over the number rows present below */
+        for (i = (l + 1u); i < numRows; i++)
+        {
+          /* Update the input and destination pointers */
+          pInT2 = pInT1 + (numCols * l);
+          pInT4 = pInT3 + (numCols * k);
+
+          /* Check if there is a non zero pivot element to    
+           * replace in the rows below */
+          if(*pInT2 != 0.0f)
+          {
+            /* Loop over number of columns    
+             * to the right of the pilot element */
+            for (j = 0u; j < (numCols - l); j++)
+            {
+              /* Exchange the row elements of the input matrix */
+              Xchg = *pInT2;
+              *pInT2++ = *pInT1;
+              *pInT1++ = Xchg;
+            }
+
+            for (j = 0u; j < numCols; j++)
+            {
+              Xchg = *pInT4;
+              *pInT4++ = *pInT3;
+              *pInT3++ = Xchg;
+            }
+
+            /* Flag to indicate whether exchange is done or not */
+            flag = 1u;
+
+            /* Break after exchange is done */
+            break;
+          }
+
+          /* Update the destination pointer modifier */
+          k++;
+        }
+      }
+
+      /* Update the status if the matrix is singular */
+      if((flag != 1u) && (in == 0.0f))
+      {
+        status = ARM_MATH_SINGULAR;
+
+        break;
+      }
+
+      /* Points to the pivot row of input and destination matrices */
+      pPivotRowIn = pIn + (l * numCols);
+      pPivotRowDst = pOut + (l * numCols);
+
+      /* Temporary pointers to the pivot row pointers */
+      pInT1 = pPivotRowIn;
+      pInT2 = pPivotRowDst;
+
+      /* Pivot element of the row */
+      in = *(pIn + (l * numCols));
+
+      /* Loop over number of columns    
+       * to the right of the pilot element */
+      for (j = 0u; j < (numCols - l); j++)
+      {
+        /* Divide each element of the row of the input matrix    
+         * by the pivot element */
+        *pInT1++ = *pInT1 / in;
+      }
+      for (j = 0u; j < numCols; j++)
+      {
+        /* Divide each element of the row of the destination matrix    
+         * by the pivot element */
+        *pInT2++ = *pInT2 / in;
+      }
+
+      /* Replace the rows with the sum of that row and a multiple of row i    
+       * so that each new element in column i above row i is zero.*/
+
+      /* Temporary pointers for input and destination matrices */
+      pInT1 = pIn;
+      pInT2 = pOut;
+
+      for (i = 0u; i < numRows; i++)
+      {
+        /* Check for the pivot element */
+        if(i == l)
+        {
+          /* If the processing element is the pivot element,    
+             only the columns to the right are to be processed */
+          pInT1 += numCols - l;
+          pInT2 += numCols;
+        }
+        else
+        {
+          /* Element of the reference row */
+          in = *pInT1;
+
+          /* Working pointers for input and destination pivot rows */
+          pPRT_in = pPivotRowIn;
+          pPRT_pDst = pPivotRowDst;
+
+          /* Loop over the number of columns to the right of the pivot element,    
+             to replace the elements in the input matrix */
+          for (j = 0u; j < (numCols - l); j++)
+          {
+            /* Replace the element by the sum of that row    
+               and a multiple of the reference row  */
+            *pInT1++ = *pInT1 - (in * *pPRT_in++);
+          }
+          /* Loop over the number of columns to    
+             replace the elements in the destination matrix */
+          for (j = 0u; j < numCols; j++)
+          {
+            /* Replace the element by the sum of that row    
+               and a multiple of the reference row  */
+            *pInT2++ = *pInT2 - (in * *pPRT_pDst++);
+          }
+
+        }
+        /* Increment the temporary input pointer */
+        pInT1 = pInT1 + l;
+      }
+      /* Increment the input pointer */
+      pIn++;
+
+      /* Decrement the loop counter */
+      loopCnt--;
+      /* Increment the index modifier */
+      l++;
+    }
+
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+
+    if((flag != 1u) && (in == 0.0f))
+    {
+      status = ARM_MATH_SINGULAR;
+    }
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixInv group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c
new file mode 100644
index 0000000000..caa0200fa7
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c
@@ -0,0 +1,270 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_mult_f32.c   
+*   
+* Description:  Floating-point matrix multiplication.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixMult Matrix Multiplication   
+ *   
+ * Multiplies two matrices.   
+ *   
+ * \image html MatrixMultiplication.gif "Multiplication of two 3 x 3 matrices"   
+   
+ * Matrix multiplication is only defined if the number of columns of the   
+ * first matrix equals the number of rows of the second matrix.   
+ * Multiplying an M x N matrix with an N x P matrix results   
+ * in an M x P matrix.   
+ * When matrix size checking is enabled, the functions check: (1) that the inner dimensions of   
+ * pSrcA and pSrcB are equal; and (2) that the size of the output   
+ * matrix equals the outer dimensions of pSrcA and pSrcB.   
+ */
+
+
+/**   
+ * @addtogroup MatrixMult   
+ * @{   
+ */
+
+/**   
+ * @brief Floating-point matrix multiplication.   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ */
+
+arm_status arm_mat_mult_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */
+  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */
+  float32_t *pInA = pSrcA->pData;                /* input data matrix pointer A  */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float32_t *px;                                 /* Temporary output data matrix pointer */
+  float32_t sum;                                 /* Accumulator */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set   
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0u;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0.0f;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+        /* matrix multiplication        */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+
+          /* Decrement the loop count */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining MACs here.   
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Store the result in the destination buffer */
+        *px++ = sum;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = pSrcB->pData + j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t *pInB = pSrcB->pData;                /* input data matrix pointer B */
+  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pInA with each column in pInB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set    
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0.0f;
+
+        /* Initialize the pointer pIn1 to point to the starting address of the row being processed */
+        pIn1 = pInA;
+
+        /* Matrix A columns number of MAC operations are to be performed */
+        colCnt = numColsA;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += *pIn1++ * (*pIn2);
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Store the result in the destination buffer */
+        *px++ = sum;
+
+        /* Decrement the column loop counter */
+        col--;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        pIn2 = pInB + (numColsB - col);
+
+      } while(col > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixMult group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
new file mode 100644
index 0000000000..871719d968
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
@@ -0,0 +1,284 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_mult_fast_q15.c   
+*   
+* Description:	 Q15 matrix multiplication (fast variant)   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @param[in]		*pState points to the array for storing intermediate results   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The difference between the function arm_mat_mult_q15() and this fast variant is that   
+ * the fast variant use a 32-bit rather than a 64-bit accumulator.   
+ * The result of each 1.15 x 1.15 multiplication is truncated to   
+ * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30   
+ * format. Finally, the accumulator is saturated and converted to a 1.15 result.   
+ *   
+ * \par   
+ * The fast version has the same overflow behavior as the standard version but provides   
+ * less precision since it discards the low 16 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signals must be scaled down.   
+ * Scale down one of the input matrices by log2(numColsA) bits to   
+ * avoid overflows, as a total of numColsA additions are computed internally for each   
+ * output element.   
+ *   
+ * \par   
+ * See arm_mat_mult_q15() for a slower implementation of this function   
+ * which uses 64-bit accumulation to provide higher precision.   
+ */
+
+arm_status arm_mat_mult_fast_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState)
+{
+  q31_t sum;                                     /* accumulator */
+  q31_t in;                                      /* Temporary variable to hold the input value */
+  q15_t *pSrcBT = pState;                        /* input data matrix pointer for transpose */
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
+//  q15_t *pDst = pDst->pData;                   /* output data matrix pointer */   
+  q15_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */
+  uint16_t col, i = 0u, row = numRowsB, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      col = numColsB >> 2;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pSrcBT + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(col > 0u)
+      {
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      col = numColsB % 0x4u;
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pInB++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* Reset the variables for the usage in the following multiplication process */
+    row = numRowsA;
+    i = 0u;
+    px = pDst->pData;
+
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set   
+       ** to the starting address of the transposed pSrcB data */
+      pInB = pSrcBT;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 2 MACs simultaneously. */
+        colCnt = numColsA >> 1;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pInA = pSrcA->pData + i;
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum = __SMLAD(*__SIMD32(pInA)++, *__SIMD32(pInB)++, sum);
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* process odd column samples */
+        if((numColsA & 0x1u) > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += ((q31_t) * pInA * (*pInB++));
+        }
+
+        /* Saturate and store the result in the destination buffer */
+        *px = (q15_t) (sum >> 15);
+        px++;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+      i = i + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixMult group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
new file mode 100644
index 0000000000..44387b0e5c
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
@@ -0,0 +1,202 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_mult_fast_q31.c   
+*   
+* Description:	 Q31 matrix multiplication (fast variant).   
+*   
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixMult   
+ * @{   
+ */
+
+/**   
+ * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The difference between the function arm_mat_mult_q31() and this fast variant is that   
+ * the fast variant use a 32-bit rather than a 64-bit accumulator.   
+ * The result of each 1.31 x 1.31 multiplication is truncated to   
+ * 2.30 format. These intermediate results are accumulated in a 32-bit register in 2.30   
+ * format. Finally, the accumulator is saturated and converted to a 1.31 result.   
+ *   
+ * \par   
+ * The fast version has the same overflow behavior as the standard version but provides   
+ * less precision since it discards the low 32 bits of each multiplication result.   
+ * In order to avoid overflows completely the input signals must be scaled down.   
+ * Scale down one of the input matrices by log2(numColsA) bits to   
+ * avoid overflows, as a total of numColsA additions are computed internally for each   
+ * output element.   
+ *   
+ * \par   
+ * See arm_mat_mult_q31() for a slower implementation of this function   
+ * which uses 64-bit accumulation to provide higher precision.   
+ */
+
+arm_status arm_mat_mult_fast_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
+//  q31_t *pSrcB = pSrcB->pData;                    /* input data matrix pointer B */   
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q31_t *px;                                     /* Temporary output data matrix pointer */
+  q31_t sum;                                     /* Accumulator */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set   
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0u;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pInA */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * pIn1++ * (*pIn2))) >> 32);
+          pIn2 += numColsB;
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * pIn1++ * (*pIn2))) >> 32);
+          pIn2 += numColsB;
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * pIn1++ * (*pIn2))) >> 32);
+          pIn2 += numColsB;
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * pIn1++ * (*pIn2))) >> 32);
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.   
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum = (q31_t) ((((q63_t) sum << 32) +
+                          ((q63_t) * pIn1++ * (*pIn2))) >> 32);
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 2.30 to 1.31 format and store in destination buffer */
+        *px++ = sum << 1;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = pSrcB->pData + j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixMult group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c
new file mode 100644
index 0000000000..27dd13a224
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c
@@ -0,0 +1,378 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_mult_q15.c   
+*   
+* Description:	 Q15 matrix multiplication.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixMult   
+ * @{   
+ */
+
+
+/**   
+ * @brief Q15 matrix multiplication   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @param[in]		*pState points to the array for storing intermediate results  
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator. The inputs to the   
+ * multiplications are in 1.15 format and multiplications yield a 2.30 result.   
+ * The 2.30 intermediate   
+ * results are accumulated in a 64-bit accumulator in 34.30 format. This approach   
+ * provides 33 guard bits and there is no risk of overflow. The 34.30 result is then   
+ * truncated to 34.15 format by discarding the low 15 bits and then saturated to   
+ * 1.15 format.   
+ *   
+ * \par   
+ * Refer to arm_mat_mult_fast_q15() for a faster but less precise version of this function for Cortex-M3 and Cortex-M4.   
+ *   
+ */
+
+arm_status arm_mat_mult_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst,
+  q15_t * pState)
+{
+  q63_t sum;                                     /* accumulator */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;                                      /* Temporary variable to hold the input value */
+  q15_t *pSrcBT = pState;                        /* input data matrix pointer for transpose */
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
+  q15_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t numRowsB = pSrcB->numRows;            /* number of rows of input matrix A    */
+  uint16_t col, i = 0u, row = numRowsB, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      col = numColsB >> 2;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pSrcBT + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(col > 0u)
+      {
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Read two elements from the row */
+        in = *__SIMD32(pInB)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) in;
+
+#else
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *px = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *px = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* If the columns of pSrcB is not a multiple of 4, compute any remaining output samples here.   
+       ** No loop unrolling is used. */
+      col = numColsB % 0x4u;
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pInB++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += numRowsB;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* Reset the variables for the usage in the following multiplication process */
+    row = numRowsA;
+    i = 0u;
+    px = pDst->pData;
+
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set   
+       ** to the starting address of the transposed pSrcB data */
+      pInB = pSrcBT;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Apply loop unrolling and compute 2 MACs simultaneously. */
+        colCnt = numColsA >> 1;
+
+        /* Initiate the pointer pIn1 to point to the starting address of the column being processed */
+        pInA = pSrcA->pData + i;
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum = __SMLALD(*__SIMD32(pInA)++, *__SIMD32(pInB)++, sum);
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* process odd column samples */
+        if((numColsA & 0x1u) > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          sum += ((q31_t) * pInA * (*pInB++));
+        }
+
+        /* Saturate and store the result in the destination buffer */
+        *px = (q15_t) (__SSAT((sum >> 15), 16));
+        px++;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+      i = i + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q15_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A of Q15 type */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B of Q15 type */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q15_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set         
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pSrcA */
+        pIn1 = pInA;
+
+        /* Matrix A columns number of MAC operations are to be performed */
+        colCnt = numColsA;
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q31_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 34.30 to 1.15 format and store the saturated value in destination buffer */
+        /* Saturate and store the result in the destination buffer */
+        *px++ = (q15_t) __SSAT((sum >> 15), 16);
+
+        /* Decrement the column loop counter */
+        col--;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        pIn2 = pInB + (numColsB - col);
+
+      } while(col > 0u);
+
+      /* Update the pointer pSrcA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixMult group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c
new file mode 100644
index 0000000000..ad50365475
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c
@@ -0,0 +1,278 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_mult_q31.c   
+*   
+* Description:	 Q31 matrix multiplication.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixMult   
+ * @{   
+ */
+
+/**   
+ * @brief Q31 matrix multiplication   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The accumulator has a 2.62 format and maintains full precision of the intermediate   
+ * multiplication results but provides only a single guard bit. There is no saturation   
+ * on intermediate additions. Thus, if the accumulator overflows it wraps around and   
+ * distorts the result. The input signals should be scaled down to avoid intermediate   
+ * overflows. The input is thus scaled down by log2(numColsA) bits   
+ * to avoid overflows, as a total of numColsA additions are performed internally.   
+ * The 2.62 accumulator is right shifted by 31 bits and saturated to 1.31 format to yield the final result.   
+ *   
+ * \par   
+ * See arm_mat_mult_fast_q31() for a faster but less precise implementation of this function for Cortex-M3 and Cortex-M4.   
+ *   
+ */
+
+arm_status arm_mat_mult_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q31_t *px;                                     /* Temporary output data matrix pointer */
+  q63_t sum;                                     /* Accumulator */
+  uint16_t numRowsA = pSrcA->numRows;            /* number of rows of input matrix A    */
+  uint16_t numColsB = pSrcB->numCols;            /* number of columns of input matrix B */
+  uint16_t numColsA = pSrcA->numCols;            /* number of columns of input matrix A */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t col, i = 0u, j, row = numRowsA, colCnt;      /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set   
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      j = 0u;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pInA */
+        pIn1 = pInA;
+
+        /* Apply loop unrolling and compute 4 MACs simultaneously. */
+        colCnt = numColsA >> 2;
+
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* If the columns of pSrcA is not a multiple of 4, compute any remaining output samples here.   
+         ** No loop unrolling is used. */
+        colCnt = numColsA % 0x4u;
+
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
+        *px++ = (q31_t) (sum >> 31);
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        j++;
+        pIn2 = (pSrcB->pData) + j;
+
+        /* Decrement the column loop counter */
+        col--;
+
+      } while(col > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q31_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
+  uint16_t col, i = 0u, row = numRowsA, colCnt;  /* loop counters */
+  arm_status status;                             /* status of matrix multiplication */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numCols != pSrcB->numRows) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcB->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* The following loop performs the dot-product of each row in pSrcA with each column in pSrcB */
+    /* row loop */
+    do
+    {
+      /* Output pointer is set to starting address of the row being processed */
+      px = pOut + i;
+
+      /* For every row wise process, the column loop counter is to be initiated */
+      col = numColsB;
+
+      /* For every row wise process, the pIn2 pointer is set         
+       ** to the starting address of the pSrcB data */
+      pIn2 = pSrcB->pData;
+
+      /* column loop */
+      do
+      {
+        /* Set the variable sum, that acts as accumulator, to zero */
+        sum = 0;
+
+        /* Initiate the pointer pIn1 to point to the starting address of pInA */
+        pIn1 = pInA;
+
+        /* Matrix A columns number of MAC operations are to be performed */
+        colCnt = numColsA;
+
+        /* matrix multiplication */
+        while(colCnt > 0u)
+        {
+          /* c(m,n) = a(1,1)*b(1,1) + a(1,2) * b(2,1) + .... + a(m,p)*b(p,n) */
+          /* Perform the multiply-accumulates */
+          sum += (q63_t) * pIn1++ * *pIn2;
+          pIn2 += numColsB;
+
+          /* Decrement the loop counter */
+          colCnt--;
+        }
+
+        /* Convert the result from 2.62 to 1.31 format and store in destination buffer */
+        *px++ = (q31_t) (sum >> 31);
+
+        /* Decrement the column loop counter */
+        col--;
+
+        /* Update the pointer pIn2 to point to the  starting address of the next column */
+        pIn2 = pInB + (numColsB - col);
+
+      } while(col > 0u);
+
+#endif
+
+      /* Update the pointer pInA to point to the  starting address of the next row */
+      i = i + numColsB;
+      pInA = pInA + numColsA;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixMult group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c
new file mode 100644
index 0000000000..65d5cfd20f
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c
@@ -0,0 +1,156 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:        arm_mat_scale_f32.c   
+*   
+* Description:	Multiplies a floating-point matrix by a scalar.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixScale Matrix Scale   
+ *   
+ * Multiplies a matrix by a scalar.  This is accomplished by multiplying each element in the   
+ * matrix by the scalar.  For example:   
+ * \image html MatrixScale.gif "Matrix Scaling of a 3 x 3 matrix"   
+ *   
+ * The function checks to make sure that the input and output matrices are of the same size.   
+ *   
+ * In the fixed-point Q15 and Q31 functions, scale is represented by   
+ * a fractional multiplication scaleFract and an arithmetic shift shift.   
+ * The shift allows the gain of the scaling operation to exceed 1.0.   
+ * The overall scale factor applied to the fixed-point data is   
+ * 
       
+ *     scale = scaleFract * 2^shift.   
+ * 
       
+ */
+
+/**   
+ * @addtogroup MatrixScale   
+ * @{   
+ */
+
+/**   
+ * @brief Floating-point matrix scaling.   
+ * @param[in]       *pSrc points to input matrix structure   
+ * @param[in]       scale scale factor to be applied    
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either ARM_MATH_SIZE_MISMATCH    
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ */
+
+arm_status arm_mat_scale_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  float32_t scale,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix scaling     */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * scale */
+      /* Scaling and results are stored in the destination buffer. */
+      *pOut++ = (*pIn++) * scale;
+      *pOut++ = (*pIn++) * scale;
+      *pOut++ = (*pIn++) * scale;
+      *pOut++ = (*pIn++) * scale;
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * scale */
+      /* The results are stored in the destination buffer. */
+      *pOut++ = (*pIn++) * scale;
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixScale group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c
new file mode 100644
index 0000000000..fbdc511342
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_scale_q15.c   
+*   
+* Description:	Multiplies a Q15 matrix by a scalar.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixScale   
+ * @{   
+ */
+
+/**   
+ * @brief Q15 matrix scaling.   
+ * @param[in]       *pSrc points to input matrix   
+ * @param[in]       scaleFract fractional portion of the scale factor   
+ * @param[in]       shift number of bits to shift the result by   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The input data *pSrc and scaleFract are in 1.15 format.   
+ * These are multiplied to yield a 2.30 intermediate result and this is shifted with saturation to 1.15 format.   
+ */
+
+arm_status arm_mat_scale_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  q15_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pIn = pSrc->pData;                      /* input data matrix pointer */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  int32_t totShift = 15 - shift;                 /* total shift to apply after scaling */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix scaling     */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch */
+  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      *pOut++ =
+        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+      *pOut++ =
+        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+      *pOut++ =
+        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+      *pOut++ =
+        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      *pOut++ =
+        (q15_t) (__SSAT(((q31_t) (*pIn++) * scaleFract) >> totShift, 16));
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixScale group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c
new file mode 100644
index 0000000000..e94f9a5cb4
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c
@@ -0,0 +1,152 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_scale_q31.c   
+*   
+* Description:	Multiplies a Q31 matrix by a scalar.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixScale   
+ * @{   
+ */
+
+/**   
+ * @brief Q31 matrix scaling.   
+ * @param[in]       *pSrc points to input matrix   
+ * @param[in]       scaleFract fractional portion of the scale factor   
+ * @param[in]       shift number of bits to shift the result by   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The input data *pSrc and scaleFract are in 1.31 format.   
+ * These are multiplied to yield a 2.62 intermediate result and this is shifted with saturation to 1.31 format.   
+ */
+
+arm_status arm_mat_scale_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  q31_t scaleFract,
+  int32_t shift,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn = pSrc->pData;                      /* input data matrix pointer */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  q63_t out;                                     /* temporary variable to hold output value */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  int32_t totShift = 31 - shift;                 /* shift to apply after scaling */
+  uint32_t blkCnt;                               /* loop counters  */
+  arm_status status;                             /* status of matrix scaling      */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch  */
+  if((pSrc->numRows != pDst->numRows) || (pSrc->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrc->numRows * pSrc->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      out = ((q63_t) * pIn++ * scaleFract) >> totShift;
+      *pOut++ = clip_q63_to_q31(out);
+      out = ((q63_t) * pIn++ * scaleFract) >> totShift;
+      *pOut++ = clip_q63_to_q31(out);
+      out = ((q63_t) * pIn++ * scaleFract) >> totShift;
+      *pOut++ = clip_q63_to_q31(out);
+      out = ((q63_t) * pIn++ * scaleFract) >> totShift;
+      *pOut++ = clip_q63_to_q31(out);
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) * k */
+      /* Scale, saturate and then store the results in the destination buffer. */
+      out = ((q63_t) * pIn++ * scaleFract) >> totShift;
+      *pOut++ = clip_q63_to_q31(out);
+
+      /* Decrement the numSamples loop counter */
+      blkCnt--;
+    }
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixScale group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c
new file mode 100644
index 0000000000..4a5823e892
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c
@@ -0,0 +1,151 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_sub_f32.c   
+*   
+* Description:	Floating-point matrix subtraction.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @defgroup MatrixSub Matrix Subtraction   
+ *   
+ * Subtract two matrices.   
+ * \image html MatrixSubtraction.gif "Subraction of two 3 x 3 matrices"   
+ *   
+ * The functions check to make sure that   
+ * pSrcA, pSrcB, and pDst have the same   
+ * number of rows and columns.   
+ */
+
+/**   
+ * @addtogroup MatrixSub   
+ * @{   
+ */
+
+/**   
+ * @brief Floating-point matrix subtraction   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ */
+
+arm_status arm_mat_sub_f32(
+  const arm_matrix_instance_f32 * pSrcA,
+  const arm_matrix_instance_f32 * pSrcB,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn1 = pSrcA->pData;                /* input data matrix pointer A */
+  float32_t *pIn2 = pSrcB->pData;                /* input data matrix pointer B */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer  */
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix subtraction */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (*pIn1++) - (*pIn2++);
+      *pOut++ = (*pIn1++) - (*pIn2++);
+      *pOut++ = (*pIn1++) - (*pIn2++);
+      *pOut++ = (*pIn1++) - (*pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (*pIn1++) - (*pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixSub group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c
new file mode 100644
index 0000000000..d8acbd31c0
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c
@@ -0,0 +1,155 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_sub_q15.c   
+*   
+* Description:	Q15 Matrix subtraction   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixSub   
+ * @{   
+ */
+
+/**   
+ * @brief Q15 matrix subtraction.   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.   
+ */
+
+arm_status arm_mat_sub_q15(
+  const arm_matrix_instance_q15 * pSrcA,
+  const arm_matrix_instance_q15 * pSrcB,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pInA = pSrcA->pData;                    /* input data matrix pointer A */
+  q15_t *pInB = pSrcB->pData;                    /* input data matrix pointer B */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix */
+  uint32_t blkCnt;                               /* loop counters  */
+  arm_status status;                             /* status of matrix subtraction  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Apply loop unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, Saturate and then store the results in the destination buffer. */
+      *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+      *__SIMD32(pOut)++ = __QSUB16(*__SIMD32(pInA)++, *__SIMD32(pInB)++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __QSUB16(*pInA++, *pInB++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract and then store the results in the destination buffer. */
+      *pOut++ = (q15_t) __SSAT(((q31_t) * pInA++ - *pInB++), 16);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixSub group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c
new file mode 100644
index 0000000000..c5eac4e776
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c
@@ -0,0 +1,158 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_sub_q31.c   
+*   
+* Description:	Q31 matrix subtraction   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixSub   
+ * @{   
+ */
+
+/**   
+ * @brief Q31 matrix subtraction.   
+ * @param[in]       *pSrcA points to the first input matrix structure   
+ * @param[in]       *pSrcB points to the second input matrix structure   
+ * @param[out]      *pDst points to output matrix structure   
+ * @return     		The function returns either   
+ * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ *   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q31 range [0x80000000 0x7FFFFFFF] will be saturated.   
+ */
+
+
+arm_status arm_mat_sub_q31(
+  const arm_matrix_instance_q31 * pSrcA,
+  const arm_matrix_instance_q31 * pSrcB,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn1 = pSrcA->pData;                    /* input data matrix pointer A */
+  q31_t *pIn2 = pSrcB->pData;                    /* input data matrix pointer B */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint32_t numSamples;                           /* total number of elements in the matrix  */
+  uint32_t blkCnt;                               /* loop counters */
+  arm_status status;                             /* status of matrix subtraction */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition  */
+  if((pSrcA->numRows != pSrcB->numRows) ||
+     (pSrcA->numCols != pSrcB->numCols) ||
+     (pSrcA->numRows != pDst->numRows) || (pSrcA->numCols != pDst->numCols))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Total number of samples in the input matrix */
+    numSamples = (uint32_t) pSrcA->numRows * pSrcA->numCols;
+
+#ifndef ARM_MATH_CM0
+
+    /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+    /* Loop Unrolling */
+    blkCnt = numSamples >> 2u;
+
+    /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+     ** a second loop below computes the remaining 1 to 3 samples. */
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, saturate and then store the results in the destination buffer. */
+      *pOut++ = __QSUB(*pIn1++, *pIn2++);
+      *pOut++ = __QSUB(*pIn1++, *pIn2++);
+      *pOut++ = __QSUB(*pIn1++, *pIn2++);
+      *pOut++ = __QSUB(*pIn1++, *pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+    /* If the numSamples is not a multiple of 4, compute any remaining output samples here.   
+     ** No loop unrolling is used. */
+    blkCnt = numSamples % 0x4u;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, saturate and then store the results in the destination buffer. */
+      *pOut++ = __QSUB(*pIn1++, *pIn2++);
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#else
+
+    /* Run the below code for Cortex-M0 */
+
+    /* Initialize blkCnt with number of samples */
+    blkCnt = numSamples;
+
+    while(blkCnt > 0u)
+    {
+      /* C(m,n) = A(m,n) - B(m,n) */
+      /* Subtract, saturate and then store the results in the destination buffer. */
+      *pOut++ = clip_q63_to_q31(((q63_t) (*pIn1++)) - (*pIn2++));
+
+      /* Decrement the loop counter */
+      blkCnt--;
+    }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixSub group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c
new file mode 100644
index 0000000000..ada0c3914a
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c
@@ -0,0 +1,213 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_trans_f32.c   
+*   
+* Description:	Floating-point matrix transpose.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+/**   
+ * @defgroup MatrixTrans Matrix Transpose   
+ *   
+ * Tranposes a matrix.   
+ * Transposing an M x N matrix flips it around the center diagonal and results in an N x M matrix.   
+ * \image html MatrixTranspose.gif "Transpose of a 3 x 3 matrix"   
+ */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixTrans   
+ * @{   
+ */
+
+/**   
+  * @brief Floating-point matrix transpose.   
+  * @param[in]  *pSrc points to the input matrix   
+  * @param[out] *pDst points to the output matrix   
+  * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH   
+  * or ARM_MATH_SUCCESS based on the outcome of size checking.   
+  */
+
+
+arm_status arm_mat_trans_f32(
+  const arm_matrix_instance_f32 * pSrc,
+  arm_matrix_instance_f32 * pDst)
+{
+  float32_t *pIn = pSrc->pData;                  /* input data matrix pointer */
+  float32_t *pOut = pDst->pData;                 /* output data matrix pointer */
+  float32_t *px;                                 /* Temporary output data matrix pointer */
+  uint16_t nRows = pSrc->numRows;                /* number of rows */
+  uint16_t nColumns = pSrc->numCols;             /* number of columns */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t blkCnt, i = 0u, row = nRows;          /* loop counters */
+  arm_status status;                             /* status of matrix transpose  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* Loop Unrolling */
+      blkCnt = nColumns >> 2;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(blkCnt > 0u)        /* column loop */
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+      /* Perform matrix transpose for last 3 samples here. */
+      blkCnt = nColumns % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  uint16_t col, i = 0u, row = nRows;             /* loop counters */
+  arm_status status;                             /* status of matrix transpose  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* Initialize column loop counter */
+      col = nColumns;
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);          /* row loop end  */
+
+    /* Set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixTrans group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c
new file mode 100644
index 0000000000..c2f0ec388e
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c
@@ -0,0 +1,234 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_trans_q15.c   
+*   
+* Description:	Q15 matrix transpose.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixTrans   
+ * @{   
+ */
+
+/*   
+ * @brief Q15 matrix transpose.   
+ * @param[in]  *pSrc points to the input matrix   
+ * @param[out] *pDst points to the output matrix   
+ * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH   
+ * or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ */
+
+arm_status arm_mat_trans_q15(
+  const arm_matrix_instance_q15 * pSrc,
+  arm_matrix_instance_q15 * pDst)
+{
+  q15_t *pSrcA = pSrc->pData;                    /* input data matrix pointer */
+  q15_t *pOut = pDst->pData;                     /* output data matrix pointer */
+  uint16_t nRows = pSrc->numRows;                /* number of nRows */
+  uint16_t nColumns = pSrc->numCols;             /* number of nColumns */
+  uint16_t col, row = nRows, i = 0u;             /* row and column loop counters */
+  arm_status status;                             /* status of matrix transpose */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;                                      /* variable to hold temporary output  */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*      #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      col = nColumns >> 2u;
+
+      /* The pointer pOut is set to starting address of the column being processed */
+      pOut = pDst->pData + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(col > 0u)
+      {
+        /* Read two elements from the row */
+        in = *__SIMD32(pSrcA)++;
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) in;
+
+#else
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Unpack and store the second element in the destination */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *pOut = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Read two elements from the row */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        in = *__SIMD32(pSrcA)++;
+
+#else
+
+        in = *__SIMD32(pSrcA)++;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Unpack and store one element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) in;
+
+#else
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Unpack and store the second element in the destination */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        *pOut = (q15_t) ((in & (q31_t) 0xffff0000) >> 16);
+
+#else
+
+        *pOut = (q15_t) in;
+
+#endif /*    #ifndef ARM_MATH_BIG_ENDIAN    */
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      /* Perform matrix transpose for last 3 samples here. */
+      col = nColumns % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* The pointer pOut is set to starting address of the column being processed */
+      pOut = pDst->pData + i;
+
+      /* Initialize column loop counter */
+      col = nColumns;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *pOut = *pSrcA++;
+
+        /* Update the pointer pOut to point to the next row of the transposed matrix */
+        pOut += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    } while(row > 0u);
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixTrans group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c
new file mode 100644
index 0000000000..f96f1b3114
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c
@@ -0,0 +1,205 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_mat_trans_q31.c   
+*   
+* Description:	Q31 matrix transpose.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+*    incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupMatrix   
+ */
+
+/**   
+ * @addtogroup MatrixTrans   
+ * @{   
+ */
+
+/*   
+  * @brief Q31 matrix transpose.   
+  * @param[in]  *pSrc points to the input matrix   
+  * @param[out] *pDst points to the output matrix   
+  * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH   
+  * or ARM_MATH_SUCCESS based on the outcome of size checking.   
+ */
+
+arm_status arm_mat_trans_q31(
+  const arm_matrix_instance_q31 * pSrc,
+  arm_matrix_instance_q31 * pDst)
+{
+  q31_t *pIn = pSrc->pData;                      /* input data matrix pointer  */
+  q31_t *pOut = pDst->pData;                     /* output data matrix pointer  */
+  q31_t *px;                                     /* Temporary output data matrix pointer */
+  uint16_t nRows = pSrc->numRows;                /* number of nRows */
+  uint16_t nColumns = pSrc->numCols;             /* number of nColumns  */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  uint16_t blkCnt, i = 0u, row = nRows;          /* loop counters */
+  arm_status status;                             /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* Apply loop unrolling and exchange the columns with row elements */
+      blkCnt = nColumns >> 2u;
+
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+       ** a second loop below computes the remaining 1 to 3 samples. */
+      while(blkCnt > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+      /* Perform matrix transpose for last 3 samples here. */
+      blkCnt = nColumns % 0x4u;
+
+      while(blkCnt > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        blkCnt--;
+      }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  uint16_t col, i = 0u, row = nRows;             /* loop counters */
+  arm_status status;                             /* status of matrix transpose */
+
+
+#ifdef ARM_MATH_MATRIX_CHECK
+
+  /* Check for matrix mismatch condition */
+  if((pSrc->numRows != pDst->numCols) || (pSrc->numCols != pDst->numRows))
+  {
+    /* Set status as ARM_MATH_SIZE_MISMATCH */
+    status = ARM_MATH_SIZE_MISMATCH;
+  }
+  else
+#endif /*    #ifdef ARM_MATH_MATRIX_CHECK    */
+
+  {
+    /* Matrix transpose by exchanging the rows with columns */
+    /* row loop     */
+    do
+    {
+      /* The pointer px is set to starting address of the column being processed */
+      px = pOut + i;
+
+      /* Initialize column loop counter */
+      col = nColumns;
+
+      while(col > 0u)
+      {
+        /* Read and store the input element in the destination */
+        *px = *pIn++;
+
+        /* Update the pointer px to point to the next row of the transposed matrix */
+        px += nRows;
+
+        /* Decrement the column loop counter */
+        col--;
+      }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+      i++;
+
+      /* Decrement the row loop counter */
+      row--;
+
+    }
+    while(row > 0u);            /* row loop end */
+
+    /* set status as ARM_MATH_SUCCESS */
+    status = ARM_MATH_SUCCESS;
+  }
+
+  /* Return to application */
+  return (status);
+}
+
+/**   
+ * @} end of MatrixTrans group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c
new file mode 100644
index 0000000000..c63316f007
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c
@@ -0,0 +1,127 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_max_f32.c   
+*   
+* Description:	Maximum value of a floating-point vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup Max Maximum   
+ *   
+ * Computes the maximum value of an array of data.    
+ * The function returns both the maximum value and its position within the array.    
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.   
+ */
+
+/**   
+ * @addtogroup Max   
+ * @{   
+ */
+
+
+/**   
+ * @brief Maximum value of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult maximum value returned here   
+ * @param[out]      *pIndex index of maximum value returned here   
+ * @return none.   
+ */
+
+void arm_max_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex)
+{
+  float32_t maxVal, out;                         /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u);
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and it's index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  } while(blkCnt > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and it's index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  /* Store the maximum value and it's index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**   
+ * @} end of Max group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c
new file mode 100644
index 0000000000..27c995bb25
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_max_q15.c   
+*   
+* Description:	Maximum value of a Q15 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup Max   
+ * @{   
+ */
+
+
+/**   
+ * @brief Maximum value of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult maximum value returned here   
+ * @param[out]      *pIndex index of maximum value returned here   
+ * @return none.   
+ */
+
+void arm_max_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex)
+{
+  q15_t maxVal, out;                             /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u);
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    blkCnt--;
+
+  } while(blkCnt > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the maximum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**   
+ * @} end of Max group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c
new file mode 100644
index 0000000000..f78c4a3667
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_max_q31.c   
+*   
+* Description:	Maximum value of a Q31 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup Max   
+ * @{   
+ */
+
+
+/**   
+ * @brief Maximum value of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult maximum value returned here   
+ * @param[out]      *pIndex index of maximum value returned here   
+ * @return none.   
+ */
+
+void arm_max_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex)
+{
+  q31_t maxVal, out;                             /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u);
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  do
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  } while(blkCnt > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* Compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the maximum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**   
+ * @} end of Max group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c
new file mode 100644
index 0000000000..86309e53dc
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c
@@ -0,0 +1,206 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_max_q7.c   
+*   
+* Description:	Maximum value of a Q7 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup Max   
+ * @{   
+ */
+
+
+/**   
+ * @brief Maximum value of a Q7 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult maximum value returned here   
+ * @param[out]      *pIndex index of maximum value returned here   
+  * @return none.   
+ */
+
+void arm_max_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t res, maxVal, x0, x1, maxVal2, maxVal1;    /* Temporary variables to store the output value. */
+  uint32_t blkCnt, index1, index2, index3, indx, indxMod;       /* loop counter */
+
+  /* Initialise the index value to zero. */
+  indx = 0u;
+
+  /* Load first input value that act as reference value for comparision */
+  res = *pSrc++;
+
+  /* Loop unrolling */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.  
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    indxMod = blockSize - (blkCnt * 4u);
+
+    /* Load two input values for comparision */
+    x0 = *pSrc++;
+    x1 = *pSrc++;
+
+    if(x0 < x1)
+    {
+      /* Update the maximum value and its index */
+      maxVal1 = x1;
+      index1 = indxMod + 1u;
+    }
+    else
+    {
+      /* Update the maximum value and its index */
+      maxVal1 = x0;
+      index1 = indxMod;
+    }
+
+    /* Load two input values for comparision */
+    x0 = *pSrc++;
+    x1 = *pSrc++;
+
+    if(x0 < x1)
+    {
+      /* Update the maximum value and its index */
+      maxVal2 = x1;
+      index2 = indxMod + 3u;
+    }
+    else
+    {
+      /* Update the maximum value and its index */
+      maxVal2 = x0;
+      index2 = indxMod + 2u;
+    }
+
+    if(maxVal1 < maxVal2)
+    {
+      /* Update the maximum value and its index */
+      maxVal = maxVal2;
+      index3 = index2;
+    }
+    else
+    {
+      /* Update the maximum value and its index */
+      maxVal = maxVal1;
+      index3 = index1;
+    }
+
+    if(res < maxVal)
+    {
+      /* Update the maximum value and its index */
+      res = maxVal;
+      indx = index3;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* If the blockSize - 1 is not a multiple of 4, compute any remaining output samples here.  
+   ** No loop unrolling is used. */
+  blkCnt = (blockSize - 1u) % 0x04u;
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(res < maxVal)
+    {
+      /* Update the maximum value and its index */
+      res = maxVal;
+      indx = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the maximum value and its index into destination pointers */
+  *pResult = res;
+  *pIndex = indx;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t maxVal, out;                              /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop over blockSize - 1 number of values */
+  blkCnt = (blockSize - 1u);
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize maxVal to the next consecutive values one by one */
+    maxVal = *pSrc++;
+
+    /* compare for the maximum value */
+    if(out < maxVal)
+    {
+      /* Update the maximum value and its index */
+      out = maxVal;
+      outIndex = blockSize - blkCnt;
+    }
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  /* Store the maximum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Max group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c
new file mode 100644
index 0000000000..0024b485dd
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_mean_f32.c   
+*   
+* Description:	Mean value of a floating-point vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup mean Mean   
+ *   
+ * Calculates the mean of the input vector. Mean is defined as the average of the elements in the vector.   
+ * The underlying algorithm is used:   
+ *   
+ * 
       
+ * 	Result = (pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]) / blockSize;   
+ * 
       
+ *   
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.   
+ */
+
+/**   
+ * @addtogroup mean   
+ * @{   
+ */
+
+
+/**   
+ * @brief Mean value of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult mean value returned here   
+ * @return none.   
+ */
+
+
+void arm_mean_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = sum / (float32_t) blockSize;
+}
+
+/**   
+ * @} end of mean group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c
new file mode 100644
index 0000000000..fc49d125e8
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_mean_q15.c   
+*   
+* Description:	Mean value of a Q15 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup mean   
+ * @{   
+ */
+
+/**   
+ * @brief Mean value of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult mean value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.   
+ * The input is represented in 1.15 format and is accumulated in a 32-bit    
+ * accumulator in 17.15 format.    
+ * There is no risk of internal overflow with this approach, and the    
+ * full precision of intermediate result is preserved.    
+ * Finally, the accumulator is saturated and truncated to yield a result of 1.15 format.   
+ *   
+ */
+
+
+void arm_mean_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult)
+{
+  q31_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = (q15_t) (sum / blockSize);
+}
+
+/**   
+ * @} end of mean group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c
new file mode 100644
index 0000000000..5cc56bf5a6
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_mean_q31.c   
+*   
+* Description:	Mean value of a Q31 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup mean   
+ * @{   
+ */
+
+/**   
+ * @brief Mean value of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult mean value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *\par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * The input is represented in 1.31 format and is accumulated in a 64-bit   
+ * accumulator in 33.31 format.   
+ * There is no risk of internal overflow with this approach, and the    
+ * full precision of intermediate result is preserved.    
+ * Finally, the accumulator is truncated to yield a result of 1.31 format.   
+ *   
+ */
+
+
+void arm_mean_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = (q31_t) (sum / (int32_t) blockSize);
+}
+
+/**   
+ * @} end of mean group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c
new file mode 100644
index 0000000000..33ce695f3c
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_mean_q7.c   
+*   
+* Description:	Mean value of a Q7 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup mean   
+ * @{   
+ */
+
+/**   
+ * @brief Mean value of a Q7 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult mean value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.    
+ * The input is represented in 1.7 format and is accumulated in a 32-bit   
+ * accumulator in 25.7 format.   
+ * There is no risk of internal overflow with this approach, and the    
+ * full precision of intermediate result is preserved.    
+ * Finally, the accumulator is truncated to yield a result of 1.7 format.   
+ *   
+ */
+
+
+void arm_mean_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult)
+{
+  q31_t sum = 0;                                 /* Temporary result storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) / blockSize  */
+  /* Store the result to the destination */
+  *pResult = (q7_t) (sum / (int32_t) blockSize);
+}
+
+/**   
+ * @} end of mean group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c
new file mode 100644
index 0000000000..4319a46cb9
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c
@@ -0,0 +1,133 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_min_f32.c   
+*   
+* Description:	Minimum value of a floating-point vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup Min Minimum   
+ *   
+ * Computes the minimum value of an array of data.    
+ * The function returns both the minimum value and its position within the array.    
+ * There are separate functions for floating-point, Q31, Q15, and Q7 data types.   
+ */
+
+/**   
+ * @addtogroup Min   
+ * @{   
+ */
+
+
+/**   
+ * @brief Minimum value of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult minimum value returned here   
+ * @param[out]      *pIndex index of minimum value returned here   
+  * @return none.   
+ *   
+ */
+
+void arm_min_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult,
+  uint32_t * pIndex)
+{
+  float32_t minVal, out;                         /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u);
+
+  do
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and it's index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    blkCnt--;
+
+  } while(blkCnt > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize - 1 number of values */
+  blkCnt = (blockSize - 1u);
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and it's index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  /* Store the minimum value and it's index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**   
+ * @} end of Min group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c
new file mode 100644
index 0000000000..8763c4102c
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c
@@ -0,0 +1,127 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_min_q15.c   
+*   
+* Description:	Minimum value of a Q15 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+
+/**   
+ * @addtogroup Min   
+ * @{   
+ */
+
+
+/**   
+ * @brief Minimum value of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult minimum value returned here   
+ * @param[out]      *pIndex index of minimum value returned here   
+ * @return none.   
+ *   
+ */
+
+void arm_min_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult,
+  uint32_t * pIndex)
+{
+  q15_t minVal, out;                             /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u);
+
+  do
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and its index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    blkCnt--;
+
+  } while(blkCnt > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize - 1 number of values */
+  blkCnt = (blockSize - 1u);
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and its index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  /* Store the minimum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**   
+ * @} end of Min group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c
new file mode 100644
index 0000000000..6c7f94786b
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c
@@ -0,0 +1,125 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_min_q31.c   
+*   
+* Description:	Minimum value of a Q31 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+
+/**   
+ * @addtogroup Min   
+ * @{   
+ */
+
+
+/**   
+ * @brief Minimum value of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult minimum value returned here   
+ * @param[out]      *pIndex index of minimum value returned here   
+ * @return none.   
+ *   
+ */
+
+void arm_min_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult,
+  uint32_t * pIndex)
+{
+  q31_t minVal, out;                             /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u);
+
+  do
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and its index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    blkCnt--;
+
+  } while(blkCnt > 0u);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize -1 number of values */
+  blkCnt = (blockSize - 1u);
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and its index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the minimum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+}
+
+/**   
+ * @} end of Min group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c
new file mode 100644
index 0000000000..5f8250c222
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c
@@ -0,0 +1,204 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_min_q7.c   
+*   
+* Description:	Minimum value of a Q7 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup Min   
+ * @{   
+ */
+
+
+/**   
+ * @brief Minimum value of a Q7 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult minimum value returned here   
+ * @param[out]      *pIndex index of minimum value returned here   
+ * @return none.   
+ *   
+ */
+
+void arm_min_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q7_t * pResult,
+  uint32_t * pIndex)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q7_t minVal, minVal1, minVal2, res, x0, x1;    /* Temporary variables to store the output value. */
+  uint32_t blkCnt, indx, index1, index2, index3, indxMod;       /* loop counter */
+
+  /* Initialise the index value to zero. */
+  indx = 0u;
+
+  /* Load first input value that act as reference value for comparision */
+  res = *pSrc++;
+
+  /* Loop over blockSize number of values */
+  blkCnt = (blockSize - 1u) >> 2u;
+
+  while(blkCnt > 0u)
+  {
+    indxMod = blockSize - (blkCnt * 4u);
+
+    /* Load two input values for comparision */
+    x0 = *pSrc++;
+    x1 = *pSrc++;
+
+    if(x0 > x1)
+    {
+      /* Update the minimum value and its index */
+      minVal1 = x1;
+      index1 = indxMod + 1u;
+    }
+    else
+    {
+      /* Update the minimum value and its index */
+      minVal1 = x0;
+      index1 = indxMod;
+    }
+
+    /* Load two input values for comparision */
+    x0 = *pSrc++;
+    x1 = *pSrc++;
+
+    if(x0 > x1)
+    {
+      /* Update the minimum value and its index */
+      minVal2 = x1;
+      index2 = indxMod + 3u;
+    }
+    else
+    {
+      /* Update the minimum value and its index */
+      minVal2 = x0;
+      index2 = indxMod + 2u;
+    }
+
+    if(minVal1 > minVal2)
+    {
+      /* Update the minimum value and its index */
+      minVal = minVal2;
+      index3 = index2;
+    }
+    else
+    {
+      /* Update the minimum value and its index */
+      minVal = minVal1;
+      index3 = index1;
+    }
+
+    if(res > minVal)
+    {
+      /* Update the minimum value and its index */
+      res = minVal;
+      indx = index3;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+
+  }
+
+  blkCnt = (blockSize - 1u) % 0x04u;
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(res > minVal)
+    {
+      /* Update the minimum value and its index */
+      res = minVal;
+      indx = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the minimum value and its index into destination pointers */
+  *pResult = res;
+  *pIndex = indx;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q7_t minVal, out;                              /* Temporary variables to store the output value. */
+  uint32_t blkCnt, outIndex;                     /* loop counter */
+
+  /* Initialise the index value to zero. */
+  outIndex = 0u;
+
+  /* Load first input value that act as reference value for comparision */
+  out = *pSrc++;
+
+  /* Loop over blockSize - 1 number of values */
+  blkCnt = (blockSize - 1u);
+
+  while(blkCnt > 0u)
+  {
+    /* Initialize minVal to the next consecutive values one by one */
+    minVal = *pSrc++;
+
+    /* compare for the minimum value */
+    if(out > minVal)
+    {
+      /* Update the minimum value and its index */
+      out = minVal;
+      outIndex = blockSize - blkCnt;
+    }
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the minimum value and its index into destination pointers */
+  *pResult = out;
+  *pIndex = outIndex;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of Min group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c
new file mode 100644
index 0000000000..8139afd0e7
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c
@@ -0,0 +1,135 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_power_f32.c   
+*   
+* Description:	Sum of the squares of the elements of a floating-point vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup power Power   
+ *   
+ * Calculates the sum of the squares of the elements in the input vector.   
+ * The underlying algorithm is used:   
+ *   
+ * 
       
+ * 	Result = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + pSrc[2] * pSrc[2] + ... + pSrc[blockSize-1] * pSrc[blockSize-1];   
+ * 
       
+ *  
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.    
+ */
+
+/**   
+ * @addtogroup power   
+ * @{   
+ */
+
+
+/**   
+ * @brief Sum of the squares of the elements of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult sum of the squares value returned here   
+ * @return none.   
+ *   
+ */
+
+
+void arm_power_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* accumulator */
+  float32_t in;                                  /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* compute power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the result to the destination */
+  *pResult = sum;
+}
+
+/**   
+ * @} end of power group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c
new file mode 100644
index 0000000000..45d1c43cc5
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c
@@ -0,0 +1,141 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_power_q15.c   
+*   
+* Description:	Sum of the squares of the elements of a Q15 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup power   
+ * @{   
+ */
+
+/**   
+ * @brief Sum of the squares of the elements of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult sum of the squares value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.    
+ * The input is represented in 1.15 format.  
+ * Intermediate multiplication yields a 2.30 format, and this   
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.   
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the   
+ * full precision of the intermediate multiplication is preserved.   
+ * Finally, the return result is in 34.30 format.    
+ *   
+ */
+
+void arm_power_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in32;                                    /* Temporary variable to store input value */
+  q15_t in16;                                    /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in32 = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in32, in32, sum);
+    in32 = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in32, in32, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in16 = *pSrc++;
+    sum = __SMLALD(in16, in16, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t in;                                      /* Temporary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q31_t) in * in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Store the results in 34.30 format  */
+  *pResult = sum;
+}
+
+/**   
+ * @} end of power group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c
new file mode 100644
index 0000000000..b471955779
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c
@@ -0,0 +1,132 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_power_q31.c   
+*   
+* Description:	Sum of the squares of the elements of a Q31 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup power   
+ * @{   
+ */
+
+/**   
+ * @brief Sum of the squares of the elements of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult sum of the squares value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * The input is represented in 1.31 format.   
+ * Intermediate multiplication yields a 2.62 format, and this   
+ * result is truncated to 2.48 format by discarding the lower 14 bits.   
+ * The 2.48 result is then added without saturation to a 64-bit accumulator in 16.48 format.   
+ * With 15 guard bits in the accumulator, there is no risk of overflow, and the   
+ * full precision of the intermediate multiplication is preserved.   
+ * Finally, the return result is in 16.48 format.    
+ *   
+ */
+
+void arm_power_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult)
+{
+  q63_t sum = 0;                                 /* Temporary result storage */
+  q31_t in;
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power then shift intermediate results by 14 bits to maintain 16.48 format and then store the result in a temporary variable sum, providing 15 guard bits. */
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q63_t) in * in) >> 14u;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the results in 16.48 format  */
+  *pResult = sum;
+}
+
+/**   
+ * @} end of power group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c
new file mode 100644
index 0000000000..52159be2f7
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c
@@ -0,0 +1,137 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_power_q7.c   
+*   
+* Description:	Sum of the squares of the elements of a Q7 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup power   
+ * @{   
+ */
+
+/**   
+ * @brief Sum of the squares of the elements of a Q7 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult sum of the squares value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 32-bit internal accumulator.    
+ * The input is represented in 1.7 format.  
+ * Intermediate multiplication yields a 2.14 format, and this   
+ * result is added without saturation to an accumulator in 18.14 format.   
+ * With 17 guard bits in the accumulator, there is no risk of overflow, and the   
+ * full precision of the intermediate multiplication is preserved.   
+ * Finally, the return result is in 18.14 format.    
+ *   
+ */
+
+void arm_power_q7(
+  q7_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q31_t sum = 0;                                 /* Temporary result storage */
+  q7_t in;                                       /* Temporary variable to store input */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t input1;                                  /* Temporary variable to store packed input */
+  q15_t in1, in2;                                /* Temporary variables to store input */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* Reading two inputs of pSrc vector and packing */
+    in1 = (q15_t) * pSrc++;
+    in2 = (q15_t) * pSrc++;
+    input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    sum = __SMLAD(input1, input1, sum);
+
+    /* Reading two inputs of pSrc vector and packing */
+    in1 = (q15_t) * pSrc++;
+    in2 = (q15_t) * pSrc++;
+    input1 = ((q31_t) in1 & 0x0000FFFF) | ((q31_t) in2 << 16);
+
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    sum = __SMLAD(input1, input1, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute Power and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q15_t) in * in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Store the result in 18.14 format  */
+  *pResult = sum;
+}
+
+/**   
+ * @} end of power group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c
new file mode 100644
index 0000000000..4293a5280d
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c
@@ -0,0 +1,130 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_rms_f32.c   
+*   
+* Description:	Root mean square value of an array of F32 type   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup RMS Root mean square (RMS)   
+ *   
+ *    
+ * Calculates the Root Mean Sqaure of the elements in the input vector.   
+ * The underlying algorithm is used:   
+ *   
+ * 
       
+ * 	Result = sqrt(((pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]) / blockSize));   
+ * 
       
+ *  
+ * There are separate functions for floating point, Q31, and Q15 data types.    
+ */
+
+/**   
+ * @addtogroup RMS   
+ * @{   
+ */
+
+
+/**   
+ * @brief Root Mean Square of the elements of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult rms value returned here   
+ * @return none.   
+ *   
+ */
+
+void arm_rms_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* Accumulator */
+  float32_t in;                                  /* Tempoprary variable to store input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the result in a temporary variable, sum  */
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum  */
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Rms and store the result in the destination */
+  arm_sqrt_f32(sum / (float32_t) blockSize, pResult);
+}
+
+/**   
+ * @} end of RMS group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c
new file mode 100644
index 0000000000..d5548cc7f0
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c
@@ -0,0 +1,150 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_rms_q15.c   
+*   
+* Description:	Root Mean Square of the elements of a Q15 vector. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @addtogroup RMS   
+ * @{   
+ */
+
+/**   
+ * @brief Root Mean Square of the elements of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult rms value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * The input is represented in 1.15 format.   
+ * Intermediate multiplication yields a 2.30 format, and this   
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.   
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the   
+ * full precision of the intermediate multiplication is preserved.   
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower    
+ * 15 bits, and then saturated to yield a result in 1.15 format.   
+ *   
+ */
+
+void arm_rms_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult)
+{
+  q63_t sum = 0;                                 /* accumulator */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;                                      /* temporary variable to store the input value */
+  q15_t in1;                                     /* temporary variable to store the input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in1 = *pSrc++;
+    sum = __SMLALD(in1, in1, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Truncating and saturating the accumulator to 1.15 format */
+  sum = __SSAT((q31_t) (sum >> 15), 16);
+
+  in1 = (q15_t) (sum / blockSize);
+
+  /* Store the result in the destination */
+  arm_sqrt_q15(in1, pResult);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t in;                                      /* temporary variable to store the input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *pSrc++;
+    sum += ((q31_t) in * in);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Truncating and saturating the accumulator to 1.15 format */
+  sum = __SSAT((q31_t) (sum >> 15), 16);
+
+  in = (q15_t) (sum / blockSize);
+
+  /* Store the result in the destination */
+  arm_sqrt_q15(in, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of RMS group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c
new file mode 100644
index 0000000000..5d5805316e
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c
@@ -0,0 +1,143 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_rms_q31.c   
+*   
+* Description:	Root Mean Square of the elements of a Q31 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @addtogroup RMS   
+ * @{   
+ */
+
+
+/**   
+ * @brief Root Mean Square of the elements of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult rms value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ *\par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The input is represented in 1.31 format, and intermediate multiplication   
+ * yields a 2.62 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results,    
+ * but provides only a single guard bit.   
+ * There is no saturation on intermediate additions.   
+ * If the accumulator overflows, it wraps around and distorts the result.    
+ * In order to avoid overflows completely, the input signal must be scaled down by    
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.    
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.   
+ *   
+ */
+
+void arm_rms_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* accumulator */
+  q31_t in;                                      /* Temporary variable to store the input */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn1 = pSrc;                            /* SrcA pointer */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the result in a temporary variable, sum */
+    in = *pIn1++;
+    sum += (q63_t) in *in;
+    in = *pIn1++;
+    sum += (q63_t) in *in;
+    in = *pIn1++;
+    sum += (q63_t) in *in;
+    in = *pIn1++;
+    sum += (q63_t) in *in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *pIn1++;
+    sum += (q63_t) in *in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = A[0] * A[0] + A[1] * A[1] + A[2] * A[2] + ... + A[blockSize-1] * A[blockSize-1] */
+    /* Compute sum of the squares and then store the results in a temporary variable, sum */
+    in = *pSrc++;
+    sum += (q63_t) in *in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Convert data in 2.62 to 1.31 by 31 right shifts */
+  sum = sum >> 31;
+
+  /* Compute Rms and store the result in the destination vector */
+  arm_sqrt_q31((q31_t) (sum / (int32_t) blockSize), pResult);
+}
+
+/**   
+ * @} end of RMS group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c
new file mode 100644
index 0000000000..ea8c5b97dd
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c
@@ -0,0 +1,222 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_std_f32.c   
+*   
+* Description:	Standard deviation of the elements of a floating-point vector. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup STD Standard deviation   
+ *   
+ * Calculates the standard deviation of the elements in the input vector.    
+ * The underlying algorithm is used:   
+ *  
+ * 
       
+ * 	Result = sqrt((sumOfSquares - sum2 / blockSize) / (blockSize - 1))  
+ *  
+ *	   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]  
+ *  
+ *	                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]  
+ * 
      
+ *   
+ * There are separate functions for floating point, Q31, and Q15 data types.   
+ */
+
+/**   
+ * @addtogroup STD   
+ * @{   
+ */
+
+
+/**   
+ * @brief Standard deviation of the elements of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult standard deviation value returned here   
+ * @return none.   
+ *   
+ */
+
+
+void arm_std_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+  float32_t sum = 0.0f;                          /* Temporary result storage */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t meanOfSquares, mean, in, squareOfMean;
+  uint32_t blkCnt;                               /* loop counter */
+  float32_t *pIn;                                /* Temporary pointer */
+
+  pIn = pSrc;
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples   
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = sum / ((float32_t) blockSize - 1.0f);
+
+  /* Reset the accumulator */
+  sum = 0.0f;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Reset the input working pointer */
+  pSrc = pIn;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+  /* Compute mean of all input values */
+  mean = sum / (float32_t) blockSize;
+
+  /* Compute square of mean */
+  squareOfMean = (mean * mean) * (((float32_t) blockSize) /
+                                  ((float32_t) blockSize - 1.0f));
+
+  /* Compute standard deviation and then store the result to the destination */
+  arm_sqrt_f32((meanOfSquares - squareOfMean), pResult);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t sumOfSquares = 0.0f;                 /* Sum of squares */
+  float32_t squareOfSum;                         /* Square of Sum */
+  float32_t in;                                  /* input value */
+  float32_t var;                                 /* Temporary varaince storage */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += in * in;
+
+    /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
+    /* Compute Sum of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute the square of sum */
+  squareOfSum = ((sum * sum) / (float32_t) blockSize);
+
+  /* Compute the variance */
+  var = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
+
+  /* Compute standard deviation and then store the result to the destination */
+  arm_sqrt_f32(var, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of STD group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c
new file mode 100644
index 0000000000..371652dd24
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c
@@ -0,0 +1,229 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_std_q15.c   
+*   
+* Description:	Standard deviation of an array of Q15 type.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup STD   
+ * @{   
+ */
+
+/**   
+ * @brief Standard deviation of the elements of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult standard deviation value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * The input is represented in 1.15 format.  
+ * Intermediate multiplication yields a 2.30 format, and this   
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.   
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the   
+ * full precision of the intermediate multiplication is preserved.   
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower    
+ * 15 bits, and then saturated to yield a result in 1.15 format.   
+ */
+
+void arm_std_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q15_t * pResult)
+{
+  q63_t sum = 0;                                 /* Accumulator */
+  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
+  q15_t mean;                                    /* mean */
+  uint32_t blkCnt;                               /* loop counter */
+  q15_t t;                                       /* Temporary variable */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t *pIn;                                    /* Temporary pointer */
+  q31_t in;                                      /* input value */
+  q15_t in1;                                     /* input value */
+
+  pIn = pSrc;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in1 = *pSrc++;
+    sum = __SMLALD(in1, in1, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples   
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q15_t) ((1.0 / (blockSize - 1)) * 16384LL);
+  sum = __SSAT((sum >> 15u), 16u);
+
+  meanOfSquares = (q31_t) ((sum * t) >> 14u);
+
+  /* Reset the accumulator */
+  sum = 0;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Reset the input working pointer */
+  pSrc = pIn;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+  /* Compute mean of all input values */
+  t = (q15_t) ((1.0 / (blockSize * (blockSize - 1))) * 32768LL);
+  mean = (q15_t) __SSAT(sum, 16u);
+
+  /* Compute square of mean */
+  squareOfMean = ((q31_t) mean * mean) >> 15;
+  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
+
+  /* mean of the squares minus the square of the mean. */
+  in1 = (q15_t) (meanOfSquares - squareOfMean);
+
+  /* Compute standard deviation and store the result to the destination */
+  arm_sqrt_q15(in1, pResult);
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+  q15_t in;                                      /* input value */
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += (in * in);
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q15_t) ((1.0 / (blockSize - 1)) * 16384LL);
+  sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
+  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
+
+  /* Compute mean of all input values */
+  mean = (q15_t) __SSAT(sum, 16u);
+
+  /* Compute square of mean of the input samples  
+   * and then store the result in a temporary variable, squareOfMean.*/
+  t = (q15_t) ((1.0 / (blockSize * (blockSize - 1))) * 32768LL);
+  squareOfMean = ((q31_t) mean * mean) >> 15;
+  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
+
+  /* mean of the squares minus the square of the mean. */
+  in = (q15_t) (meanOfSquares - squareOfMean);
+
+  /* Compute standard deviation and store the result to the destination */
+  arm_sqrt_q15(in, pResult);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+}
+
+/**   
+ * @} end of STD group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c
new file mode 100644
index 0000000000..a33d51b4f6
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c
@@ -0,0 +1,219 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_std_q31.c   
+*   
+* Description:	Standard deviation of an array of Q31 type.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup STD   
+ * @{   
+ */
+
+
+/**   
+ * @brief Standard deviation of the elements of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult standard deviation value returned here   
+ * @return none.   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ *\par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The input is represented in 1.31 format, and intermediate multiplication   
+ * yields a 2.62 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results,    
+ * but provides only a single guard bit.   
+ * There is no saturation on intermediate additions.   
+ * If the accumulator overflows it wraps around and distorts the result.   
+ * In order to avoid overflows completely the input signal must be scaled down by    
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.    
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.   
+ *   
+ */
+
+
+void arm_std_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* Accumulator */
+  q31_t meanOfSquares, squareOfMean;             /* square of mean and mean of square */
+  q31_t mean;                                    /* mean */
+  q31_t in;                                      /* input value */
+  q31_t t;                                       /* Temporary variable */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn;                                    /* Temporary pointer */
+
+  pIn = pSrc;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);
+
+  /* Compute Mean of squares of the input samples   
+   * and then store the result in a temporary variable, meanOfSquares. */
+  sum = (sum >> 31);
+  meanOfSquares = (q31_t) ((sum * t) >> 30);
+
+  /* Reset the accumulator */
+  sum = 0;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Reset the input working pointer */
+  pSrc = pIn;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q31_t) ((1.0f / (float32_t) (blockSize - 1u)) * 1073741824.0f);
+  sumOfSquares = (sumOfSquares >> 31);
+  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 30);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Compute mean of all input values */
+  t = (q31_t) ((1.0f / (blockSize * (blockSize - 1u))) * 2147483648.0f);
+  mean = (q31_t) (sum);
+
+  /* Compute square of mean */
+  squareOfMean = (q31_t) (((q63_t) mean * mean) >> 31);
+  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 31);
+
+
+  /* Compute standard deviation and then store the result to the destination */
+  arm_sqrt_q31(meanOfSquares - squareOfMean, pResult);
+
+}
+
+/**   
+ * @} end of STD group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c
new file mode 100644
index 0000000000..89aca0e394
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c
@@ -0,0 +1,219 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_var_f32.c   
+*   
+* Description:	Variance of the elements of a floating-point vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @defgroup variance  Variance   
+ *   
+ * Calculates the variance of the elements in the input vector.   
+ * The underlying algorithm is used:   
+ *   
+ * 
       
+ * 	Result = (sumOfSquares - sum2 / blockSize) / (blockSize - 1)  
+ *  
+ *	   where, sumOfSquares = pSrc[0] * pSrc[0] + pSrc[1] * pSrc[1] + ... + pSrc[blockSize-1] * pSrc[blockSize-1]  
+ *  
+ *	                   sum = pSrc[0] + pSrc[1] + pSrc[2] + ... + pSrc[blockSize-1]  
+ * 
      
+ *   
+ * There are separate functions for floating point, Q31, and Q15 data types.   
+ */
+
+/**   
+ * @addtogroup variance   
+ * @{   
+ */
+
+
+/**   
+ * @brief Variance of the elements of a floating-point vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult variance value returned here   
+ * @return none.   
+ *   
+ */
+
+
+void arm_var_f32(
+  float32_t * pSrc,
+  uint32_t blockSize,
+  float32_t * pResult)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  float32_t sum = (float32_t) 0.0;               /* Accumulator */
+  float32_t meanOfSquares, mean, in, squareOfMean;      /* Temporary variables */
+  uint32_t blkCnt;                               /* loop counter */
+  float32_t *pIn;                                /* Temporary pointer */
+
+  /* updating temporary pointer */
+  pIn = pSrc;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += in * in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples   
+   * and then store the result in a temporary variable, meanOfSquares. */
+  meanOfSquares = sum / ((float32_t) blockSize - 1.0f);
+
+  /* Reset the accumulator */
+  sum = 0.0f;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Reset the input working pointer */
+  pSrc = pIn;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+  /* Compute mean of all input values */
+  mean = sum / (float32_t) blockSize;
+
+  /* Compute square of mean */
+  squareOfMean = (mean * mean) * (((float32_t) blockSize) /
+                                  ((float32_t) blockSize - 1.0f));
+
+  /* Compute variance and then store the result to the destination */
+  *pResult = meanOfSquares - squareOfMean;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  float32_t sum = 0.0f;                          /* Temporary result storage */
+  float32_t sumOfSquares = 0.0f;                 /* Sum of squares */
+  float32_t squareOfSum;                         /* Square of Sum */
+  float32_t in;                                  /* input value */
+  uint32_t blkCnt;                               /* loop counter */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += in * in;
+
+    /* C = (A[0] + A[1] + ... + A[blockSize-1]) */
+    /* Compute Sum of the input samples    
+     * and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute the square of sum */
+  squareOfSum = ((sum * sum) / (float32_t) blockSize);
+
+  /* Compute the variance */
+  *pResult = ((sumOfSquares - squareOfSum) / (float32_t) (blockSize - 1.0f));
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of variance group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c
new file mode 100644
index 0000000000..9721834227
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c
@@ -0,0 +1,214 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_var_q15.c   
+*   
+* Description:	Variance of an array of Q15 type.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup variance   
+ * @{   
+ */
+
+/**   
+ * @brief Variance of the elements of a Q15 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult variance value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ * \par   
+ * The function is implemented using a 64-bit internal accumulator.   
+ * The input is represented in 1.15 format.  
+ * Intermediate multiplication yields a 2.30 format, and this   
+ * result is added without saturation to a 64-bit accumulator in 34.30 format.   
+ * With 33 guard bits in the accumulator, there is no risk of overflow, and the   
+ * full precision of the intermediate multiplication is preserved.   
+ * Finally, the 34.30 result is truncated to 34.15 format by discarding the lower    
+ * 15 bits, and then saturated to yield a result in 1.15 format.   
+ *   
+ */
+
+
+void arm_var_q15(
+  q15_t * pSrc,
+  uint32_t blockSize,
+  q31_t * pResult)
+{
+  q63_t sum = 0;                                 /* Accumulator */
+  q31_t meanOfSquares, squareOfMean;             /* Mean of square and square of mean */
+  q15_t mean;                                    /* mean */
+  uint32_t blkCnt;                               /* loop counter */
+  q15_t t;                                       /* Temporary variable */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t in;                                      /* Input variable */
+  q15_t in1;                                     /* Temporary variable */
+  q15_t *pIn;                                    /* Temporary pointer */
+
+  pIn = pSrc;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+    in = *__SIMD32(pSrc)++;
+    sum = __SMLALD(in, in, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in1 = *pSrc++;
+    sum = __SMLALD(in1, in1, sum);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples   
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q15_t) ((1.0f / (float32_t) (blockSize - 1u)) * 16384);
+  sum = __SSAT((sum >> 15u), 16u);
+
+  meanOfSquares = (q31_t) ((sum * t) >> 14u);
+
+  /* Reset the accumulator */
+  sum = 0;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Reset the input working pointer */
+  pSrc = pIn;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+  q15_t in;                                      /* Temporary variable */
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += (in * in);
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q15_t) ((1.0f / (float32_t) (blockSize - 1u)) * 16384);
+  sumOfSquares = __SSAT((sumOfSquares >> 15u), 16u);
+  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 14u);
+
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Compute mean of all input values */
+  t = (q15_t) ((1.0f / (float32_t) (blockSize * (blockSize - 1u))) * 32768);
+  mean = __SSAT(sum, 16u);
+
+  /* Compute square of mean */
+  squareOfMean = ((q31_t) mean * mean) >> 15;
+  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 15);
+
+  /* Compute variance and then store the result to the destination */
+  *pResult = (meanOfSquares - squareOfMean);
+
+}
+
+/**   
+ * @} end of variance group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c
new file mode 100644
index 0000000000..94d3405db4
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c
@@ -0,0 +1,216 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_var_q31.c   
+*   
+* Description:	Variance of an array of Q31 type.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupStats   
+ */
+
+/**   
+ * @addtogroup variance   
+ * @{   
+ */
+
+/**   
+ * @brief Variance of the elements of a Q31 vector.   
+ * @param[in]       *pSrc points to the input vector   
+ * @param[in]       blockSize length of the input vector   
+ * @param[out]      *pResult variance value returned here   
+ * @return none.   
+ *   
+ * @details   
+ * Scaling and Overflow Behavior:   
+ *   
+ *\par   
+ * The function is implemented using an internal 64-bit accumulator.   
+ * The input is represented in 1.31 format, and intermediate multiplication   
+ * yields a 2.62 format.   
+ * The accumulator maintains full precision of the intermediate multiplication results,    
+ * but provides only a single guard bit.   
+ * There is no saturation on intermediate additions.   
+ * If the accumulator overflows it wraps around and distorts the result.   
+ * In order to avoid overflows completely the input signal must be scaled down by    
+ * log2(blockSize) bits, as a total of blockSize additions are performed internally.    
+ * Finally, the 2.62 accumulator is right shifted by 31 bits to yield a 1.31 format value.   
+ *   
+ */
+
+
+void arm_var_q31(
+  q31_t * pSrc,
+  uint32_t blockSize,
+  q63_t * pResult)
+{
+  q63_t sum = 0;                                 /* Accumulator */
+  q31_t meanOfSquares, squareOfMean;             /* Mean of square and square of mean */
+  q31_t mean;                                    /* Mean */
+  q31_t in;                                      /* Input variable */
+  q31_t t;                                       /* Temporary variable */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t *pIn;                                    /* Temporary pointer */
+
+  pIn = pSrc;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1]) */
+    /* Compute Sum of squares of the input samples   
+     * and then store the result in a temporary variable, sum. */
+    in = *pSrc++;
+    sum += ((q63_t) (in) * (in));
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples   
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q31_t) ((1.0 / (blockSize - 1)) * 1073741824LL);
+  sum = (sum >> 31);
+  meanOfSquares = (q31_t) ((sum * t) >> 30);
+
+  /* Reset the accumulator */
+  sum = 0;
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Reset the input working pointer */
+  pSrc = pIn;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q63_t sumOfSquares = 0;                        /* Accumulator */
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+    /* C = (A[0] * A[0] + A[1] * A[1] + ... + A[blockSize-1] * A[blockSize-1])  */
+    /* Compute Sum of squares of the input samples    
+     * and then store the result in a temporary variable, sumOfSquares. */
+    in = *pSrc++;
+    sumOfSquares += ((q63_t) (in) * (in));
+
+    /* C = (A[0] + A[1] + A[2] + ... + A[blockSize-1]) */
+    /* Compute sum of all input values and then store the result in a temporary variable, sum. */
+    sum += in;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* Compute Mean of squares of the input samples    
+   * and then store the result in a temporary variable, meanOfSquares. */
+  t = (q31_t) ((1.0 / (blockSize - 1)) * 1073741824LL);
+  sumOfSquares = (sumOfSquares >> 31);
+  meanOfSquares = (q31_t) ((sumOfSquares * t) >> 30);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  /* Compute mean of all input values */
+  t = (q31_t) ((1.0 / (blockSize * (blockSize - 1u))) * 2147483648LL);
+  mean = (q31_t) (sum);
+
+  /* Compute square of mean */
+  squareOfMean = (q31_t) (((q63_t) mean * mean) >> 31);
+  squareOfMean = (q31_t) (((q63_t) squareOfMean * t) >> 31);
+
+  /* Compute variance and then store the result to the destination */
+  *pResult = (q63_t) meanOfSquares - squareOfMean;
+
+}
+
+/**   
+ * @} end of variance group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c
new file mode 100644
index 0000000000..32ad4682fb
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c
@@ -0,0 +1,121 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_copy_f32.c   
+*   
+* Description:	Copies the elements of a floating-point vector. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @defgroup copy Vector Copy   
+ *   
+ * Copies sample by sample from source vector to destination vector.   
+ *   
+ * 
       
+ * 	pDst[n] = pSrc[n];   0 <= n < blockSize.   
+ * 
       
+ *  
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.    
+ */
+
+/**   
+ * @addtogroup copy   
+ * @{   
+ */
+
+/**   
+ * @brief Copies the elements of a floating-point vector.    
+ * @param[in]       *pSrc points to input vector   
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the input vector  
+ * @return none.   
+ *   
+ */
+
+
+void arm_copy_f32(
+  float32_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    *pDst++ = *pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of BasicCopy group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c
new file mode 100644
index 0000000000..80c31bbd6c
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c
@@ -0,0 +1,130 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_copy_q15.c   
+*   
+* Description:	Copies the elements of a Q15 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup copy   
+ * @{   
+ */
+/**   
+ * @brief Copies the elements of a Q15 vector.    
+ * @param[in]       *pSrc points to input vector   
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the input vector  
+ * @return none.   
+ *   
+ */
+
+void arm_copy_q15(
+  q15_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q15_t in1, in2;                                /* Temporary variables */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Read two inputs */
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* Store the values in the destination buffer by packing the two inputs */
+    *__SIMD32(pDst)++ = __PKHBT(in1, in2, 16);
+
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    *__SIMD32(pDst)++ = __PKHBT(in1, in2, 16);
+
+#else
+
+    /* Store the values in the destination buffer by packing the two inputs */
+    *__SIMD32(pDst)++ = __PKHBT(in2, in1, 16);
+
+    in1 = *pSrc++;
+    in2 = *pSrc++;
+    *__SIMD32(pDst)++ = __PKHBT(in2, in1, 16);
+
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the value in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of BasicCopy group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c
new file mode 100644
index 0000000000..ed482d4beb
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c
@@ -0,0 +1,109 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_copy_q31.c   
+*   
+* Description:	Copies the elements of a Q31 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup copy   
+ * @{   
+ */
+
+/**   
+ * @brief Copies the elements of a Q31 vector.    
+ * @param[in]       *pSrc points to input vector   
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the input vector  
+ * @return none.   
+ *   
+ */
+
+void arm_copy_q31(
+  q31_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the values in the destination buffer */
+    *pDst++ = *pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = *pSrc++;
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the value in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of BasicCopy group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c
new file mode 100644
index 0000000000..a8fc25c648
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c
@@ -0,0 +1,107 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_copy_q7.c   
+*   
+* Description:	Copies the elements of a Q7 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup copy   
+ * @{   
+ */
+
+/**   
+ * @brief Copies the elements of a Q7 vector.   
+ * @param[in]       *pSrc points to input vector   
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the input vector  
+ * @return none.   
+ *   
+ */
+
+void arm_copy_q7(
+  q7_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    /* 4 samples are copied and stored at a time using SIMD */
+    *__SIMD32(pDst)++ = *__SIMD32(pSrc)++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = A */
+    /* Copy and then store the results in the destination buffer */
+    *pDst++ = *pSrc++;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of BasicCopy group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c
new file mode 100644
index 0000000000..3e7cf934f6
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c
@@ -0,0 +1,122 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_fill_f32.c   
+*   
+* Description:	Fills a constant value into a floating-point vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @defgroup Fill Vector Fill   
+ *   
+ * Fills the destination vector with a constant value.   
+ *   
+ * 
       
+ * 	pDst[n] = value;   0 <= n < blockSize.   
+ * 
       
+ *  
+ * There are separate functions for floating point, Q31, Q15, and Q7 data types.    
+ */
+
+/**   
+ * @addtogroup Fill   
+ * @{   
+ */
+
+/**   
+ * @brief Fills a constant value into a floating-point vector.    
+ * @param[in]       value input value to be filled  
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the output vector  
+ * @return none.   
+ *   
+ */
+
+
+void arm_fill_f32(
+  float32_t value,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+    *pDst++ = value;
+    *pDst++ = value;
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of Fill group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c
new file mode 100644
index 0000000000..a5da51a7a5
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c
@@ -0,0 +1,112 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_fill_q15.c   
+*   
+* Description:	Fills a constant value into a Q15 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup Fill   
+ * @{   
+ */
+
+/**   
+ * @brief Fills a constant value into a Q15 vector.   
+ * @param[in]       value input value to be filled  
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the output vector  
+ * @return none.   
+ *   
+ */
+
+void arm_fill_q15(
+  q15_t value,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t packedValue;                             /* value packed to 32 bits */
+
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Packing two 16 bit values to 32 bit value in order to use SIMD */
+  packedValue = __PKHBT(value, value, 16u);
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *__SIMD32(pDst)++ = packedValue;
+    *__SIMD32(pDst)++ = packedValue;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of Fill group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c
new file mode 100644
index 0000000000..b571fdc9a6
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c
@@ -0,0 +1,109 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_fill_q31.c   
+*   
+* Description:	Fills a constant value into a Q31 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup Fill   
+ * @{   
+ */
+
+/**   
+ * @brief Fills a constant value into a Q31 vector.   
+ * @param[in]       value input value to be filled  
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the output vector  
+ * @return none.   
+ *   
+ */
+
+void arm_fill_q31(
+  q31_t value,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+    *pDst++ = value;
+    *pDst++ = value;
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of Fill group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c
new file mode 100644
index 0000000000..18bdf80070
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c
@@ -0,0 +1,110 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_fill_q7.c   
+*   
+* Description:	Fills a constant value into a Q7 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup Fill   
+ * @{   
+ */
+
+/**   
+ * @brief Fills a constant value into a Q7 vector.   
+ * @param[in]       value input value to be filled  
+ * @param[out]      *pDst points to output vector   
+ * @param[in]       blockSize length of the output vector  
+ * @return none.   
+ *   
+ */
+
+void arm_fill_q7(
+  q7_t value,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t packedValue;                             /* value packed to 32 bits */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* Packing four 8 bit values to 32 bit value in order to use SIMD */
+  packedValue = __PACKq7(value, value, value, value);
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *__SIMD32(pDst)++ = packedValue;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = value */
+    /* Fill the value in the destination buffer */
+    *pDst++ = value;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of Fill group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c
new file mode 100644
index 0000000000..85a740a429
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c
@@ -0,0 +1,193 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_float_to_q15.c   
+*   
+* Description:	Converts the elements of the floating-point vector to Q15 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup float_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the floating-point vector to Q15 vector.   
+ * @param[in]       *pSrc points to the floating-point input vector   
+ * @param[out]      *pDst points to the Q15 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ * \par  
+ * The equation used for the conversion process is:   
+ * 
       
+ * 	pDst[n] = (q15_t)(pSrc[n] * 32768);   0 <= n < blockSize.   
+ * 
       
+ * \par Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q15 range [0x8000 0x7FFF] will be saturated.   
+ * \note  
+ * In order to apply rounding, the library should be rebuilt with the ROUNDING macro    
+ * defined in the preprocessor section of project options.    
+ *   
+ */
+
+
+void arm_float_to_q15(
+  float32_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+  float32_t in;
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 32768.0f);
+    in += in > 0 ? 0.5f : -0.5f;
+    *pDst++ = (q15_t) (__SSAT((q31_t) (in), 16));
+
+#else
+
+    /* C = A * 32768 */
+    /* convert from float to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) __SSAT((q31_t) (*pIn++ * 32768.0f), 16);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of float_to_x group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c
new file mode 100644
index 0000000000..fa9a6e74f8
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c
@@ -0,0 +1,200 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_float_to_q31.c   
+*   
+* Description:	Converts the elements of the floating-point vector to Q31 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @defgroup float_to_x  Convert 32-bit floating point value   
+ */
+
+/**   
+ * @addtogroup float_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the floating-point vector to Q31 vector.   
+ * @param[in]       *pSrc points to the floating-point input vector   
+ * @param[out]      *pDst points to the Q31 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ *\par Description:   
+ * \par  
+ * The equation used for the conversion process is:   
+ *  
+ * 
       
+ * 	pDst[n] = (q31_t)(pSrc[n] * 2147483648);   0 <= n < blockSize.   
+ * 
       
+ * Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q31 range[0x80000000 0x7FFFFFFF] will be saturated.   
+ *  
+ * \note In order to apply rounding, the library should be rebuilt with the ROUNDING macro    
+ * defined in the preprocessor section of project options.    
+ */
+
+
+void arm_float_to_q31(
+  float32_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+  float32_t in;
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+
+    /* C = A * 32768 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 2147483648.0f);
+    in += in > 0 ? 0.5f : -0.5f;
+    *pDst++ = clip_q63_to_q31((q63_t) (in));
+
+#else
+
+    /* C = A * 2147483648 */
+    /* convert from float to Q31 and then store the results in the destination buffer */
+    *pDst++ = clip_q63_to_q31((q63_t) (*pIn++ * 2147483648.0f));
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of float_to_x group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c
new file mode 100644
index 0000000000..610ef3ae8e
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c
@@ -0,0 +1,192 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_float_to_q7.c   
+*   
+* Description:	Converts the elements of the floating-point vector to Q7 vector.  
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup float_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the floating-point vector to Q7 vector.   
+ * @param[in]       *pSrc points to the floating-point input vector   
+ * @param[out]      *pDst points to the Q7 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ *\par Description:   
+ * \par  
+ * The equation used for the conversion process is:   
+ * 
       
+ * 	pDst[n] = (q7_t)(pSrc[n] * 128);   0 <= n < blockSize.   
+ * 
       
+ * \par Scaling and Overflow Behavior:   
+ * \par   
+ * The function uses saturating arithmetic.   
+ * Results outside of the allowable Q7 range [0x80 0x7F] will be saturated.   
+ * \note  
+ * In order to apply rounding, the library should be rebuilt with the ROUNDING macro    
+ * defined in the preprocessor section of project options.    
+ */
+
+
+void arm_float_to_q7(
+  float32_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  float32_t *pIn = pSrc;                         /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifdef ARM_MATH_ROUNDING
+
+  float32_t in;
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+  while(blkCnt > 0u)
+  {
+
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 128);
+    in += in > 0 ? 0.5 : -0.5;
+    *pDst++ = (q7_t) (__SSAT((q15_t) (in), 8));
+
+#else
+
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    *pDst++ = __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+  while(blkCnt > 0u)
+  {
+#ifdef ARM_MATH_ROUNDING
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    in = *pIn++;
+    in = (in * 128.0f);
+    in += in > 0 ? 0.5f : -0.5f;
+    *pDst++ = (q7_t) (__SSAT((q31_t) (in), 8));
+
+#else
+
+    /* C = A * 128 */
+    /* convert from float to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) __SSAT((q31_t) (*pIn++ * 128.0f), 8);
+
+#endif /*      #ifdef ARM_MATH_ROUNDING        */
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+ * @} end of float_to_x group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c
new file mode 100644
index 0000000000..888379c2b9
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c
@@ -0,0 +1,123 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q15_to_float.c   
+*   
+* Description:	Converts the elements of the Q15 vector to floating-point vector.    
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @defgroup q15_to_x  Convert 16-bit Integer value   
+ */
+
+/**   
+ * @addtogroup q15_to_x   
+ * @{   
+ */
+
+
+
+
+/**   
+ * @brief  Converts the elements of the Q15 vector to floating-point vector.    
+ * @param[in]       *pSrc points to the Q15 input vector   
+ * @param[out]      *pDst points to the floating-point output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
       
+ * 	pDst[n] = (float32_t) pSrc[n] / 32768;   0 <= n < blockSize.   
+ * 
       
+ *  
+ */
+
+
+void arm_q15_to_float(
+  q15_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 32768 */
+    /* convert from q15 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 32768 */
+    /* convert from q15 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 32768.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of q15_to_x group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c
new file mode 100644
index 0000000000..c8902dec85
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c
@@ -0,0 +1,116 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q15_to_q31.c   
+*   
+* Description:	Converts the elements of the Q15 vector to Q31 vector. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup q15_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the Q15 vector to Q31 vector.    
+ * @param[in]       *pSrc points to the Q15 input vector   
+ * @param[out]      *pDst points to the Q31 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:  
+ *  
+ * 
       
+ * 	pDst[n] = (q31_t) pSrc[n] << 16;   0 <= n < blockSize.   
+ * 
       
+ *  
+ */
+
+
+void arm_q15_to_q31(
+  q15_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q31_t)A << 16 */
+    /* convert from q15 to q31 and then store the results in the destination buffer */
+    *pDst++ = (q31_t) * pIn++ << 16;
+    *pDst++ = (q31_t) * pIn++ << 16;
+    *pDst++ = (q31_t) * pIn++ << 16;
+    *pDst++ = (q31_t) * pIn++ << 16;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q31_t)A << 16 */
+    /* convert from q15 to q31 and then store the results in the destination buffer */
+    *pDst++ = (q31_t) * pIn++ << 16;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of q15_to_x group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c
new file mode 100644
index 0000000000..bfd8da8234
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c
@@ -0,0 +1,117 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q15_to_q7.c   
+*   
+* Description:	Converts the elements of the Q15 vector to Q7 vector. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup q15_to_x   
+ * @{   
+ */
+
+
+/**   
+ * @brief Converts the elements of the Q15 vector to Q7 vector.    
+ * @param[in]       *pSrc points to the Q15 input vector   
+ * @param[out]      *pDst points to the Q7 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
       
+ * 	pDst[n] = (q7_t) pSrc[n] >> 8;   0 <= n < blockSize.   
+ * 
      
+ *  
+ */
+
+
+void arm_q15_to_q7(
+  q15_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  q15_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q7_t) A >> 8 */
+    /* convert from q15 to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) (*pIn++ >> 8);
+    *pDst++ = (q7_t) (*pIn++ >> 8);
+    *pDst++ = (q7_t) (*pIn++ >> 8);
+    *pDst++ = (q7_t) (*pIn++ >> 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q7_t) A >> 8 */
+    /* convert from q15 to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) (*pIn++ >> 8);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of q15_to_x group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c
new file mode 100644
index 0000000000..3475044e82
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q31_to_float.c   
+*   
+* Description:	Converts the elements of the Q31 vector to floating-point vector.     
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @defgroup q31_to_x  Convert 32-bit Integer value   
+ */
+
+/**   
+ * @addtogroup q31_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the Q31 vector to floating-point vector.   
+ * @param[in]       *pSrc points to the Q31 input vector   
+ * @param[out]      *pDst points to the floating-point output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
       
+ * 	pDst[n] = (float32_t) pSrc[n] / 2147483648;   0 <= n < blockSize.   
+ * 
       
+ *  
+ */
+
+
+void arm_q31_to_float(
+  q31_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 2147483648 */
+    /* convert from q31 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 2147483648 */
+    /* convert from q31 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 2147483648.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of q31_to_x group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c
new file mode 100644
index 0000000000..54fc589e41
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c
@@ -0,0 +1,116 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q31_to_q15.c   
+*   
+* Description:	Converts the elements of the Q31 vector to Q15 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup q31_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the Q31 vector to Q15 vector.   
+ * @param[in]       *pSrc points to the Q31 input vector   
+ * @param[out]      *pDst points to the Q15 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *    
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
       
+ * 	pDst[n] = (q15_t) pSrc[n] >> 16;   0 <= n < blockSize.   
+ * 
       
+ *  
+ */
+
+
+void arm_q31_to_q15(
+  q31_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q15_t) A >> 16 */
+    /* convert from q31 to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) (*pIn++ >> 16);
+    *pDst++ = (q15_t) (*pIn++ >> 16);
+    *pDst++ = (q15_t) (*pIn++ >> 16);
+    *pDst++ = (q15_t) (*pIn++ >> 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q15_t) A >> 16 */
+    /* convert from q31 to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) (*pIn++ >> 16);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of q31_to_x group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c
new file mode 100644
index 0000000000..1e6bf47618
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c
@@ -0,0 +1,116 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q31_to_q7.c   
+*   
+* Description:	Converts the elements of the Q31 vector to Q7 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup q31_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the Q31 vector to Q7 vector.   
+ * @param[in]       *pSrc points to the Q31 input vector   
+ * @param[out]      *pDst points to the Q7 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
       
+ * 	pDst[n] = (q7_t) pSrc[n] >> 24;   0 <= n < blockSize.    
+ * 
       
+ *  
+ */
+
+
+void arm_q31_to_q7(
+  q31_t * pSrc,
+  q7_t * pDst,
+  uint32_t blockSize)
+{
+  q31_t *pIn = pSrc;                             /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q7_t) A >> 24 */
+    /* convert from q31 to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) (*pIn++ >> 24);
+    *pDst++ = (q7_t) (*pIn++ >> 24);
+    *pDst++ = (q7_t) (*pIn++ >> 24);
+    *pDst++ = (q7_t) (*pIn++ >> 24);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q7_t) A >> 24 */
+    /* convert from q31 to q7 and then store the results in the destination buffer */
+    *pDst++ = (q7_t) (*pIn++ >> 24);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of q31_to_x group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c
new file mode 100644
index 0000000000..7a2d61208c
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c
@@ -0,0 +1,120 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q7_to_float.c   
+*   
+* Description:	Converts the elements of the Q7 vector to floating-point vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @defgroup q7_to_x  Convert 8-bit Integer value   
+ */
+
+/**   
+ * @addtogroup q7_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the Q7 vector to floating-point vector.   
+ * @param[in]       *pSrc points to the Q7 input vector   
+ * @param[out]      *pDst points to the floating-point output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *		    
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
       
+ * 	pDst[n] = (float32_t) pSrc[n] / 128;   0 <= n < blockSize.   
+ * 
       
+ *  
+ */
+
+
+void arm_q7_to_float(
+  q7_t * pSrc,
+  float32_t * pDst,
+  uint32_t blockSize)
+{
+  q7_t *pIn = pSrc;                              /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 128 */
+    /* convert from q7 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (float32_t) A / 128 */
+    /* convert from q7 to float and then store the results in the destination buffer */
+    *pDst++ = ((float32_t) * pIn++ / 128.0f);
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+}
+
+/**   
+ * @} end of q7_to_x group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c
new file mode 100644
index 0000000000..4cba666fe6
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c
@@ -0,0 +1,119 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q7_to_q15.c   
+*   
+* Description:	Converts the elements of the Q7 vector to Q15 vector.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup q7_to_x   
+ * @{   
+ */
+
+
+
+
+/**   
+ * @brief Converts the elements of the Q7 vector to Q15 vector.   
+ * @param[in]       *pSrc points to the Q7 input vector   
+ * @param[out]      *pDst points to the Q15 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
       
+ * 	pDst[n] = (q15_t) pSrc[n] << 8;   0 <= n < blockSize.   
+ * 
       
+ *  
+ */
+
+
+void arm_q7_to_q15(
+  q7_t * pSrc,
+  q15_t * pDst,
+  uint32_t blockSize)
+{
+  q7_t *pIn = pSrc;                              /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q15_t) A << 8 */
+    /* convert from q7 to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) * pIn++ << 8;
+    *pDst++ = (q15_t) * pIn++ << 8;
+    *pDst++ = (q15_t) * pIn++ << 8;
+    *pDst++ = (q15_t) * pIn++ << 8;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q15_t) A << 8 */
+    /* convert from q7 to q15 and then store the results in the destination buffer */
+    *pDst++ = (q15_t) * pIn++ << 8;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of q7_to_x group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c
new file mode 100644
index 0000000000..6f425935ee
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c
@@ -0,0 +1,116 @@
+/* ----------------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:		arm_q7_to_q31.c   
+*   
+* Description:	Converts the elements of the Q7 vector to Q31 vector. 
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* ---------------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupSupport   
+ */
+
+/**   
+ * @addtogroup q7_to_x   
+ * @{   
+ */
+
+/**   
+ * @brief Converts the elements of the Q7 vector to Q31 vector.   
+ * @param[in]       *pSrc points to the Q7 input vector   
+ * @param[out]      *pDst points to the Q31 output vector  
+ * @param[in]       blockSize length of the input vector   
+ * @return none.   
+ *   
+ * \par Description:   
+ *   
+ * The equation used for the conversion process is:   
+ *  
+ * 
       
+ * 	pDst[n] = (q31_t) pSrc[n] << 24;   0 <= n < blockSize.  
+ * 
        
+ *  
+ */
+
+
+void arm_q7_to_q31(
+  q7_t * pSrc,
+  q31_t * pDst,
+  uint32_t blockSize)
+{
+  q7_t *pIn = pSrc;                              /* Src pointer */
+  uint32_t blkCnt;                               /* loop counter */
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*loop Unrolling */
+  blkCnt = blockSize >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  while(blkCnt > 0u)
+  {
+    /* C = (q31_t) A << 24 */
+    /* convert from q7 to q31 and then store the results in the destination buffer */
+    *pDst++ = (q31_t) * pIn++ << 24;
+    *pDst++ = (q31_t) * pIn++ << 24;
+    *pDst++ = (q31_t) * pIn++ << 24;
+    *pDst++ = (q31_t) * pIn++ << 24;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  blkCnt = blockSize % 0x4u;
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Loop over blockSize number of values */
+  blkCnt = blockSize;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+  while(blkCnt > 0u)
+  {
+    /* C = (q31_t) A << 24 */
+    /* convert from q7 to q31 and then store the results in the destination buffer */
+    *pDst++ = (q31_t) * pIn++ << 24;
+
+    /* Decrement the loop counter */
+    blkCnt--;
+  }
+
+}
+
+/**   
+ * @} end of q7_to_x group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c
new file mode 100644
index 0000000000..24099506da
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c
@@ -0,0 +1,1236 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix4_f32.c   
+*   
+* Description:	Radix-4 Decimation in Frequency CFFT & CIFFT Floating point processing function   
+*   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @defgroup CFFT_CIFFT Complex FFT Functions   
+ *   
+ * \par   
+ * Complex Fast Fourier Transform(CFFT) and Complex Inverse Fast Fourier Transform(CIFFT) is an efficient algorithm to compute Discrete Fourier Transform(DFT) and Inverse Discrete Fourier Transform(IDFT).   
+ * Computational complexity of CFFT reduces drastically when compared to DFT.   
+ * \par   
+ * This set of functions implements CFFT/CIFFT   
+ * for Q15, Q31, and floating-point data types.  The functions operates on in-place buffer which uses same buffer for input and output.   
+ * Complex input is stored in input buffer in an interleaved fashion.   
+ *   
+ * \par   
+ * The functions operate on blocks of input and output data and each call to the function processes   
+ * 2*fftLen samples through the transform.  pSrc  points to In-place arrays containing 2*fftLen values.   
+ * \par  
+ * The pSrc points to the array of in-place buffer of size 2*fftLen and inputs and outputs are stored in an interleaved fashion as shown below.   
+ * 
     {real[0], imag[0], real[1], imag[1],..} 
       
+ *   
+ * \par Lengths supported by the transform:  
+ * \par   
+ * Internally, the function utilize a radix-4 decimation in frequency(DIF) algorithm   
+ * and the size of the FFT supported are of the lengths [16, 64, 256, 1024].  
+ *    
+ *   
+ * \par Algorithm:   
+ *   
+ * Complex Fast Fourier Transform:   
+ * \par    
+ * Input real and imaginary data:   
+ * 
       
+ * x(n) = xa + j * ya   
+ * x(n+N/4 ) = xb + j * yb   
+ * x(n+N/2 ) = xc + j * yc   
+ * x(n+3N 4) = xd + j * yd   
+ * 
       
+ * where N is length of FFT   
+ * \par   
+ * Output real and imaginary data:   
+ * 
       
+ * X(4r) = xa'+ j * ya'   
+ * X(4r+1) = xb'+ j * yb'   
+ * X(4r+2) = xc'+ j * yc'   
+ * X(4r+3) = xd'+ j * yd'   
+ * 
       
+ * \par   
+ * Twiddle factors for radix-4 FFT:   
+ * 
       
+ * Wn = co1 + j * (- si1)   
+ * W2n = co2 + j * (- si2)   
+ * W3n = co3 + j * (- si3)   
+ * 
       
+ *   
+ * \par   
+ * \image html CFFT.gif "Radix-4 Decimation-in Frequency Complex Fast Fourier Transform"   
+ *   
+ * \par   
+ * Output from Radix-4 CFFT Results in Digit reversal order. Interchange middle two branches of every butterfly results in Bit reversed output.   
+ * \par   
+ *  Butterfly CFFT equations:   
+ * 
       
+ * xa' = xa + xb + xc + xd   
+ * ya' = ya + yb + yc + yd   
+ * xc' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)   
+ * yc' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)   
+ * xb' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)   
+ * yb' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)   
+ * xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)   
+ * yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)   
+ * 
       
+ *   
+ *   
+ * Complex Inverse Fast Fourier Transform:   
+ * \par   
+ * CIFFT uses same twiddle factor table as CFFT with modifications in the design equation as shown below.   
+ *   
+ * \par   
+ *  Modified Butterfly CIFFT equations:   
+ * 
       
+ * xa' = xa + xb + xc + xd   
+ * ya' = ya + yb + yc + yd   
+ * xc' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)   
+ * yc' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)   
+ * xb' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)   
+ * yb' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)   
+ * xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)   
+ * yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)   
+ * 
       
+ *   
+ * \par Instance Structure   
+ * A separate instance structure must be defined for each Instance but the twiddle factors and bit reversal tables can be reused.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Initializes twiddle factor table and bit reversal table pointers   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Manually initialize the instance structure as follows:   
+ * 
       
+ *arm_cfft_radix4_instance_f32 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor, onebyfftLen};   
+ *arm_cfft_radix4_instance_q31 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};   
+ *arm_cfft_radix4_instance_q15 S = {fftLen, ifftFlag, bitReverseFlag, pTwiddle, pBitRevTable, twidCoefModifier, bitRevFactor};   
+ * 
       
+ * \par   
+ * where fftLen length of CFFT/CIFFT; ifftFlag Flag for selection of CFFT or CIFFT(Set ifftFlag to calculate CIFFT otherwise calculates CFFT);   
+ * bitReverseFlag Flag for selection of output order(Set bitReverseFlag to output in normal order otherwise output in bit reversed order);    
+ * pTwiddlepoints to array of twiddle coefficients; pBitRevTable points to the array of bit reversal table.   
+ * twidCoefModifier modifier for twiddle factor table which supports all FFT lengths with same table;    
+ * pBitRevTable modifier for bit reversal table which supports all FFT lengths with same table.   
+ * onebyfftLen value of 1/fftLen to calculate CIFFT;   
+ *  
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the CFFT/CIFFT function.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+
+/**   
+ * @addtogroup CFFT_CIFFT   
+ * @{   
+ */
+
+/**   
+ * @details   
+ * @brief Processing function for the floating-point CFFT/CIFFT.  
+ * @param[in]      *S    points to an instance of the floating-point CFFT/CIFFT structure.  
+ * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.  
+ * @return none.  
+ */
+
+void arm_cfft_radix4_f32(
+  const arm_cfft_radix4_instance_f32 * S,
+  float32_t * pSrc)
+{
+
+  if(S->ifftFlag == 1u)
+  {
+    /*  Complex IFFT radix-4  */
+    arm_radix4_butterfly_inverse_f32(pSrc, S->fftLen, S->pTwiddle,
+                                     S->twidCoefModifier, S->onebyfftLen);
+  }
+  else
+  {
+    /*  Complex FFT radix-4  */
+    arm_radix4_butterfly_f32(pSrc, S->fftLen, S->pTwiddle,
+                             S->twidCoefModifier);
+  }
+
+  if(S->bitReverseFlag == 1u)
+  {
+    /*  Bit Reversal */
+    arm_bitreversal_f32(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+  }
+
+}
+
+
+/**   
+ * @} end of CFFT_CIFFT group   
+ */
+
+
+
+/* ----------------------------------------------------------------------   
+** Internal helper function used by the FFTs   
+** ------------------------------------------------------------------- */
+
+/*   
+ * @brief  Core function for the floating-point CFFT butterfly process.  
+ * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.  
+ * @param[in]      fftLen           length of the FFT.  
+ * @param[in]      *pCoef           points to the twiddle coefficient buffer.  
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.  
+ */
+
+void arm_radix4_butterfly_f32(
+  float32_t * pSrc,
+  uint16_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier)
+{
+
+  float32_t co1, co2, co3, si1, si2, si3;
+  float32_t t1, t2, r1, r2, s1, s2;
+  uint32_t ia1, ia2, ia3;
+  uint32_t i0, i1, i2, i3;
+  uint32_t n1, n2, j, k;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+  i0 = 0u;
+  ia1 = 0u;
+
+  j = n2;
+
+  /*  Calculation of first stage */
+  do
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+
+    /* xa + xc */
+    r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+    /* xa - xc */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xb + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = r1 + t1;
+
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = s1 + t2;
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+    /* xb - xd */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /*  index calculation for the coefficients */
+    ia2 = ia1 + ia1;
+    co2 = pCoef[ia2 * 2u];
+    si2 = pCoef[(ia2 * 2u) + 1u];
+
+    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = (r1 * co2) + (s1 * si2);
+
+    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = (s1 * co2) - (r1 * si2);
+
+    /* (xa - xc) + (yb - yd) */
+    r1 = r2 + t1;
+
+    /* (xa - xc) - (yb - yd) */
+    r2 = r2 - t1;
+
+    /* (ya - yc) - (xb - xd) */
+    s1 = s2 - t2;
+
+    /* (ya - yc) + (xb - xd) */
+    s2 = s2 + t2;
+
+    co1 = pCoef[ia1 * 2u];
+    si1 = pCoef[(ia1 * 2u) + 1u];
+
+    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = (r1 * co1) + (s1 * si1);
+
+    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = (s1 * co1) - (r1 * si1);
+
+    /*  index calculation for the coefficients */
+    ia3 = ia2 + ia1;
+    co3 = pCoef[ia3 * 2u];
+    si3 = pCoef[(ia3 * 2u) + 1u];
+
+
+    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = (r2 * co3) + (s2 * si3);
+
+    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = (s2 * co3) - (r2 * si3);
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  }
+  while(--j);
+
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of second stage to excluding last stage */
+  for (k = fftLen / 4; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  Calculation of first stage */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /* xa + xc */
+        r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+        /* xa - xc */
+        r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = r1 + t1;
+
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = s1 + t2;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (r1 * co2) + (s1 * si2);
+
+        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = (s1 * co2) - (r1 * si2);
+
+        /* (xa - xc) + (yb - yd) */
+        r1 = r2 + t1;
+
+        /* (xa - xc) - (yb - yd) */
+        r2 = r2 - t1;
+
+        /* (ya - yc) -  (xb - xd) */
+        s1 = s2 - t2;
+
+        /* (ya - yc) +  (xb - xd) */
+        s2 = s2 + t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (r1 * co1) + (s1 * si1);
+
+        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (s1 * co1) - (r1 * si1);
+
+        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = (r2 * co3) + (s2 * si3);
+
+        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (s2 * co3) - (r2 * si3);
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+
+  /*  Initializations of last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Calculations of last stage */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+
+    /* xa + xb */
+    r1 = pSrc[2u * i0] + pSrc[2u * i2];
+
+    /* xa - xb */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xc + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = r1 + t1;
+
+    /* (xa + xb) - (xc + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = s1 + t2;
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* (yb-yd) */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+    /* (xb-xd) */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = r1;
+
+    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = s1;
+
+    /* (xa+yb-xc-yd) */
+    r1 = r2 + t1;
+
+    /* (xa-yb-xc+yd) */
+    r2 = r2 - t1;
+
+    /* (ya-xb-yc+xd) */
+    s1 = s2 - t2;
+
+    /* (ya+xb-yc-xd) */
+    s2 = s2 + t2;
+
+    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = r1;
+
+    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = s1;
+
+    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = r2;
+
+    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = s2;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /*  Initializations for the fft calculation */
+  n2 = fftLen;
+  n1 = n2;
+  for (k = fftLen; k > 1u; k >>= 2u)
+  {
+    /*  Initializations for the fft calculation */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  FFT Calculation */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /* xa + xc */
+        r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+        /* xa - xc */
+        r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = r1 + t1;
+
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = s1 + t2;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (r1 * co2) + (s1 * si2);
+
+        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = (s1 * co2) - (r1 * si2);
+
+        /* (xa - xc) + (yb - yd) */
+        r1 = r2 + t1;
+
+        /* (xa - xc) - (yb - yd) */
+        r2 = r2 - t1;
+
+        /* (ya - yc) -  (xb - xd) */
+        s1 = s2 - t2;
+
+        /* (ya - yc) +  (xb - xd) */
+        s2 = s2 + t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (r1 * co1) + (s1 * si1);
+
+        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (s1 * co1) - (r1 * si1);
+
+        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = (r2 * co3) + (s2 * si3);
+
+        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (s2 * co3) - (r2 * si3);
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/*   
+ * @brief  Core function for the floating-point CIFFT butterfly process.  
+ * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.  
+ * @param[in]      fftLen           length of the FFT.  
+ * @param[in]      *pCoef           points to twiddle coefficient buffer.  
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @param[in]      onebyfftLen      value of 1/fftLen.  
+ * @return none.  
+ */
+
+void arm_radix4_butterfly_inverse_f32(
+  float32_t * pSrc,
+  uint16_t fftLen,
+  float32_t * pCoef,
+  uint16_t twidCoefModifier,
+  float32_t onebyfftLen)
+{
+  float32_t co1, co2, co3, si1, si2, si3;
+  float32_t t1, t2, r1, r2, s1, s2;
+  uint32_t ia1, ia2, ia3;
+  uint32_t i0, i1, i2, i3;
+  uint32_t n1, n2, j, k;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+  i0 = 0u;
+  ia1 = 0u;
+
+  j = n2;
+
+  /*  Calculation of first stage */
+  do
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+    /* xa - xc */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xb + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = r1 + t1;
+
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = s1 + t2;
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+    /* xb - xd */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /*  index calculation for the coefficients */
+    ia2 = ia1 + ia1;
+    co2 = pCoef[ia2 * 2u];
+    si2 = pCoef[(ia2 * 2u) + 1u];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = (r1 * co2) - (s1 * si2);
+
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = (s1 * co2) + (r1 * si2);
+
+    /* (xa - xc) - (yb - yd) */
+    r1 = r2 - t1;
+
+    /* (xa - xc) + (yb - yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb - xd) */
+    s1 = s2 + t2;
+
+    /* (ya - yc) - (xb - xd) */
+    s2 = s2 - t2;
+
+    co1 = pCoef[ia1 * 2u];
+    si1 = pCoef[(ia1 * 2u) + 1u];
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = (r1 * co1) - (s1 * si1);
+
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = (s1 * co1) + (r1 * si1);
+
+    /*  index calculation for the coefficients */
+    ia3 = ia2 + ia1;
+    co3 = pCoef[ia3 * 2u];
+    si3 = pCoef[(ia3 * 2u) + 1u];
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = (r2 * co3) - (s2 * si3);
+
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = (s2 * co3) + (r2 * si3);
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  }
+  while(--j);
+
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of second stage to excluding last stage */
+  for (k = fftLen / 4; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  Calculation of first stage */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /* xa + xc */
+        r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+        /* xa - xc */
+        r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = r1 + t1;
+
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = s1 + t2;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (r1 * co2) - (s1 * si2);
+
+        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = (s1 * co2) + (r1 * si2);
+
+        /* (xa - xc) - (yb - yd) */
+        r1 = r2 - t1;
+
+        /* (xa - xc) + (yb - yd) */
+        r2 = r2 + t1;
+
+        /* (ya - yc) +  (xb - xd) */
+        s1 = s2 + t2;
+
+        /* (ya - yc) -  (xb - xd) */
+        s2 = s2 - t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (r1 * co1) - (s1 * si1);
+
+        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (s1 * co1) + (r1 * si1);
+
+        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = (r2 * co3) - (s2 * si3);
+
+        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (s2 * co3) + (r2 * si3);
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+
+  /*  Initializations of last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Calculations of last stage */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = pSrc[2u * i0] + pSrc[2u * i2];
+
+    /* xa - xc */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xc + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1) * onebyfftLen;
+
+    /* (xa + xb) - (xc + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2) * onebyfftLen;
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* (yb-yd) */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+    /* (xb-xd) */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = r1 * onebyfftLen;
+
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = s1 * onebyfftLen;
+
+
+    /* (xa - xc) - (yb-yd) */
+    r1 = r2 - t1;
+
+    /* (xa - xc) + (yb-yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb-xd) */
+    s1 = s2 + t2;
+
+    /* (ya - yc) - (xb-xd) */
+    s2 = s2 - t2;
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = r1 * onebyfftLen;
+
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = s1 * onebyfftLen;
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = r2 * onebyfftLen;
+
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = s2 * onebyfftLen;
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /*  Calculation of first stage */
+  for (k = fftLen; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  Calculation of first stage */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /* xa + xc */
+        r1 = pSrc[(2u * i0)] + pSrc[(2u * i2)];
+
+        /* xa - xc */
+        r2 = pSrc[(2u * i0)] - pSrc[(2u * i2)];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = r1 + t1;
+
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = s1 + t2;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (r1 * co2) - (s1 * si2);
+
+        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = (s1 * co2) + (r1 * si2);
+
+        /* (xa - xc) - (yb - yd) */
+        r1 = r2 - t1;
+
+        /* (xa - xc) + (yb - yd) */
+        r2 = r2 + t1;
+
+        /* (ya - yc) +  (xb - xd) */
+        s1 = s2 + t2;
+
+        /* (ya - yc) -  (xb - xd) */
+        s2 = s2 - t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (r1 * co1) - (s1 * si1);
+
+        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (s1 * co1) + (r1 * si1);
+
+        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = (r2 * co3) - (s2 * si3);
+
+        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (s2 * co3) + (r2 * si3);
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+  /*  Initializations of last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Calculations of last stage */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = pSrc[2u * i0] + pSrc[2u * i2];
+
+    /* xa - xc */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xc + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1) * onebyfftLen;
+
+    /* (xa + xb) - (xc + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2) * onebyfftLen;
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* (yb-yd) */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+
+    /* (xb-xd) */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = r1 * onebyfftLen;
+
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = s1 * onebyfftLen;
+
+
+    /* (xa - xc) - (yb-yd) */
+    r1 = r2 - t1;
+
+    /* (xa - xc) + (yb-yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb-xd) */
+    s1 = s2 + t2;
+
+    /* (ya - yc) - (xb-xd) */
+    s2 = s2 - t2;
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = r1 * onebyfftLen;
+
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = s1 * onebyfftLen;
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = r2 * onebyfftLen;
+
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = s2 * onebyfftLen;
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/*   
+ * @brief  In-place bit reversal function.  
+ * @param[in, out] *pSrc        points to the in-place buffer of floating-point data type.  
+ * @param[in]      fftSize      length of the FFT.  
+ * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.  
+ * @param[in]      *pBitRevTab  points to the bit reversal table.  
+ * @return none.  
+ */
+
+void arm_bitreversal_f32(
+  float32_t * pSrc,
+  uint16_t fftSize,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTab)
+{
+  uint16_t fftLenBy2, fftLenBy2p1;
+  uint16_t i, j;
+  float32_t in;
+
+  /*  Initializations */
+  j = 0u;
+  fftLenBy2 = fftSize >> 1u;
+  fftLenBy2p1 = (fftSize >> 1u) + 1u;
+
+  /* Bit Reversal Implementation */
+  for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+  {
+    if(i < j)
+    {
+      /*  pSrc[i] <-> pSrc[j]; */
+      in = pSrc[2u * i];
+      pSrc[2u * i] = pSrc[2u * j];
+      pSrc[2u * j] = in;
+
+      /*  pSrc[i+1u] <-> pSrc[j+1u] */
+      in = pSrc[(2u * i) + 1u];
+      pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
+      pSrc[(2u * j) + 1u] = in;
+
+      /*  pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
+      in = pSrc[2u * (i + fftLenBy2p1)];
+      pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
+      pSrc[2u * (j + fftLenBy2p1)] = in;
+
+      /*  pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
+      in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
+      pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
+        pSrc[(2u * (j + fftLenBy2p1)) + 1u];
+      pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
+
+    }
+
+    /*  pSrc[i+1u] <-> pSrc[j+1u] */
+    in = pSrc[2u * (i + 1u)];
+    pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
+    pSrc[2u * (j + fftLenBy2)] = in;
+
+    /*  pSrc[i+2u] <-> pSrc[j+2u] */
+    in = pSrc[(2u * (i + 1u)) + 1u];
+    pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
+    pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
+
+    /*  Reading the index for the bit reversal */
+    j = *pBitRevTab;
+
+    /*  Updating the bit reversal index depending on the fft length  */
+    pBitRevTab += bitRevFactor;
+  }
+}
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
new file mode 100644
index 0000000000..07be8920b2
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
@@ -0,0 +1,1193 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix4_init_f32.c   
+*   
+* Description:	Radix-4 Decimation in Frequency Floating-point CFFT & CIFFT Initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup CFFT_CIFFT   
+ * @{   
+ */
+
+/*   
+* @brief  Floating-point Twiddle factors Table Generation   
+*/
+
+
+/**   
+* \par   
+* Example code for Floating-point Twiddle factors Generation:   
+* \par   
+* 
    for(i = 0; i< N; i++)   
+* {   
+*	twiddleCoef[2*i]= cos(i * 2*PI/(float)N);   
+*	twiddleCoef[2*i+1]= sin(i * 2*PI/(float)N);   
+* } 
       
+* \par   
+* where N = 1024	and PI = 3.14159265358979   
+* \par   
+* Cos and Sin values are in interleaved fashion   
+*    
+*/
+
+static const float32_t twiddleCoef[2048] = {
+  1.000000000000000000f, 0.000000000000000000f,
+  0.999981175282601110f, 0.006135884649154475f,
+  0.999924701839144500f, 0.012271538285719925f,
+  0.999830581795823400f, 0.018406729905804820f,
+  0.999698818696204250f, 0.024541228522912288f,
+  0.999529417501093140f, 0.030674803176636626f,
+  0.999322384588349540f, 0.036807222941358832f,
+  0.999077727752645360f, 0.042938256934940820f,
+  0.998795456205172410f, 0.049067674327418015f,
+  0.998475580573294770f, 0.055195244349689934f,
+  0.998118112900149180f, 0.061320736302208578f,
+  0.997723066644191640f, 0.067443919563664051f,
+  0.997290456678690210f, 0.073564563599667426f,
+  0.996820299291165670f, 0.079682437971430126f,
+  0.996312612182778000f, 0.085797312344439894f,
+  0.995767414467659820f, 0.091908956497132724f,
+  0.995184726672196930f, 0.098017140329560604f,
+  0.994564570734255420f, 0.104121633872054590f,
+  0.993906970002356060f, 0.110222207293883060f,
+  0.993211949234794500f, 0.116318630911904750f,
+  0.992479534598709970f, 0.122410675199216200f,
+  0.991709753669099530f, 0.128498110793793170f,
+  0.990902635427780010f, 0.134580708507126170f,
+  0.990058210262297120f, 0.140658239332849210f,
+  0.989176509964781010f, 0.146730474455361750f,
+  0.988257567730749460f, 0.152797185258443440f,
+  0.987301418157858430f, 0.158858143333861450f,
+  0.986308097244598670f, 0.164913120489969890f,
+  0.985277642388941220f, 0.170961888760301220f,
+  0.984210092386929030f, 0.177004220412148750f,
+  0.983105487431216290f, 0.183039887955140950f,
+  0.981963869109555240f, 0.189068664149806190f,
+  0.980785280403230430f, 0.195090322016128250f,
+  0.979569765685440520f, 0.201104634842091900f,
+  0.978317370719627650f, 0.207111376192218560f,
+  0.977028142657754390f, 0.213110319916091360f,
+  0.975702130038528570f, 0.219101240156869800f,
+  0.974339382785575860f, 0.225083911359792830f,
+  0.972939952205560180f, 0.231058108280671110f,
+  0.971503890986251780f, 0.237023605994367200f,
+  0.970031253194543970f, 0.242980179903263870f,
+  0.968522094274417380f, 0.248927605745720150f,
+  0.966976471044852070f, 0.254865659604514570f,
+  0.965394441697689400f, 0.260794117915275510f,
+  0.963776065795439840f, 0.266712757474898370f,
+  0.962121404269041580f, 0.272621355449948980f,
+  0.960430519415565790f, 0.278519689385053060f,
+  0.958703474895871600f, 0.284407537211271880f,
+  0.956940335732208820f, 0.290284677254462330f,
+  0.955141168305770780f, 0.296150888243623790f,
+  0.953306040354193860f, 0.302005949319228080f,
+  0.951435020969008340f, 0.307849640041534870f,
+  0.949528180593036670f, 0.313681740398891520f,
+  0.947585591017741090f, 0.319502030816015690f,
+  0.945607325380521280f, 0.325310292162262930f,
+  0.943593458161960390f, 0.331106305759876430f,
+  0.941544065183020810f, 0.336889853392220050f,
+  0.939459223602189920f, 0.342660717311994380f,
+  0.937339011912574960f, 0.348418680249434560f,
+  0.935183509938947610f, 0.354163525420490340f,
+  0.932992798834738960f, 0.359895036534988110f,
+  0.930766961078983710f, 0.365612997804773850f,
+  0.928506080473215590f, 0.371317193951837540f,
+  0.926210242138311380f, 0.377007410216418260f,
+  0.923879532511286740f, 0.382683432365089780f,
+  0.921514039342042010f, 0.388345046698826250f,
+  0.919113851690057770f, 0.393992040061048100f,
+  0.916679059921042700f, 0.399624199845646790f,
+  0.914209755703530690f, 0.405241314004989860f,
+  0.911706032005429880f, 0.410843171057903910f,
+  0.909167983090522380f, 0.416429560097637150f,
+  0.906595704514915330f, 0.422000270799799680f,
+  0.903989293123443340f, 0.427555093430282080f,
+  0.901348847046022030f, 0.433093818853151960f,
+  0.898674465693953820f, 0.438616238538527660f,
+  0.895966249756185220f, 0.444122144570429200f,
+  0.893224301195515320f, 0.449611329654606540f,
+  0.890448723244757880f, 0.455083587126343840f,
+  0.887639620402853930f, 0.460538710958240010f,
+  0.884797098430937790f, 0.465976495767966180f,
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+  0.854557988365400530f, -0.519355990165589530f,
+  0.857728610000272010f, -0.514102744193221880f,
+  0.860866938637767090f, -0.508830142543107430f,
+  0.863972856121586360f, -0.503538383725718130f,
+  0.867046245515692650f, -0.498227666972781870f,
+  0.870086991108711350f, -0.492898192229784260f,
+  0.873094978418289870f, -0.487550160148436380f,
+  0.876070094195406710f, -0.482183772079122610f,
+  0.879012226428633410f, -0.476799230063322200f,
+  0.881921264348354830f, -0.471396736825997920f,
+  0.884797098430937460f, -0.465976495767966680f,
+  0.887639620402853930f, -0.460538710958239950f,
+  0.890448723244757770f, -0.455083587126344000f,
+  0.893224301195515100f, -0.449611329654606980f,
+  0.895966249756184880f, -0.444122144570429810f,
+  0.898674465693953820f, -0.438616238538527660f,
+  0.901348847046021920f, -0.433093818853152180f,
+  0.903989293123443120f, -0.427555093430282530f,
+  0.906595704514915450f, -0.422000270799799570f,
+  0.909167983090522380f, -0.416429560097637260f,
+  0.911706032005429660f, -0.410843171057904240f,
+  0.914209755703530470f, -0.405241314004990420f,
+  0.916679059921042700f, -0.399624199845646790f,
+  0.919113851690057660f, -0.393992040061048270f,
+  0.921514039342041790f, -0.388345046698826690f,
+  0.923879532511286520f, -0.382683432365090390f,
+  0.926210242138311380f, -0.377007410216418260f,
+  0.928506080473215480f, -0.371317193951837820f,
+  0.930766961078983490f, -0.365612997804774350f,
+  0.932992798834738960f, -0.359895036534988000f,
+  0.935183509938947500f, -0.354163525420490510f,
+  0.937339011912574850f, -0.348418680249434900f,
+  0.939459223602189700f, -0.342660717311994930f,
+  0.941544065183020810f, -0.336889853392220000f,
+  0.943593458161960270f, -0.331106305759876600f,
+  0.945607325380521170f, -0.325310292162263370f,
+  0.947585591017741200f, -0.319502030816015470f,
+  0.949528180593036670f, -0.313681740398891520f,
+  0.951435020969008340f, -0.307849640041535140f,
+  0.953306040354193640f, -0.302005949319228580f,
+  0.955141168305770780f, -0.296150888243623730f,
+  0.956940335732208820f, -0.290284677254462500f,
+  0.958703474895871490f, -0.284407537211272210f,
+  0.960430519415565680f, -0.278519689385053670f,
+  0.962121404269041580f, -0.272621355449948980f,
+  0.963776065795439840f, -0.266712757474898590f,
+  0.965394441697689290f, -0.260794117915275960f,
+  0.966976471044852180f, -0.254865659604514410f,
+  0.968522094274417270f, -0.248927605745720200f,
+  0.970031253194543970f, -0.242980179903264180f,
+  0.971503890986251670f, -0.237023605994367730f,
+  0.972939952205560180f, -0.231058108280671000f,
+  0.974339382785575860f, -0.225083911359792970f,
+  0.975702130038528460f, -0.219101240156870160f,
+  0.977028142657754170f, -0.213110319916091970f,
+  0.978317370719627650f, -0.207111376192218530f,
+  0.979569765685440520f, -0.201104634842092120f,
+  0.980785280403230320f, -0.195090322016128720f,
+  0.981963869109555350f, -0.189068664149806030f,
+  0.983105487431216290f, -0.183039887955141010f,
+  0.984210092386929030f, -0.177004220412149050f,
+  0.985277642388941110f, -0.170961888760301770f,
+  0.986308097244598670f, -0.164913120489969810f,
+  0.987301418157858320f, -0.158858143333861580f,
+  0.988257567730749460f, -0.152797185258443800f,
+  0.989176509964780900f, -0.146730474455362390f,
+  0.990058210262297120f, -0.140658239332849210f,
+  0.990902635427780010f, -0.134580708507126420f,
+  0.991709753669099410f, -0.128498110793793640f,
+  0.992479534598709970f, -0.122410675199216030f,
+  0.993211949234794500f, -0.116318630911904840f,
+  0.993906970002356060f, -0.110222207293883360f,
+  0.994564570734255420f, -0.104121633872055130f,
+  0.995184726672196930f, -0.098017140329560506f,
+  0.995767414467659820f, -0.091908956497132877f,
+  0.996312612182778000f, -0.085797312344440282f,
+  0.996820299291165670f, -0.079682437971430750f,
+  0.997290456678690210f, -0.073564563599667412f,
+  0.997723066644191640f, -0.067443919563664287f,
+  0.998118112900149180f, -0.061320736302209057f,
+  0.998475580573294770f, -0.055195244349689775f,
+  0.998795456205172410f, -0.049067674327418091f,
+  0.999077727752645360f, -0.042938256934941139f,
+  0.999322384588349430f, -0.036807222941359394f,
+  0.999529417501093140f, -0.030674803176636543f,
+  0.999698818696204250f, -0.024541228522912448f,
+  0.999830581795823400f, -0.018406729905805226f,
+  0.999924701839144500f, -0.012271538285720572f,
+  0.999981175282601110f, -0.006135884649154477f
+};
+
+/**   
+* @brief  Initialization function for the floating-point CFFT/CIFFT.  
+* @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.  
+* @param[in]     fftLen         length of the FFT.  
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  
+*   
+* \par Description:  
+* \par   
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par   
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
+* \par   
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
+*/
+
+arm_status arm_cfft_radix4_init_f32(
+  arm_cfft_radix4_instance_f32 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (float32_t *) twiddleCoef;
+
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLen)
+  {
+
+  case 1024u:
+    /*  Initializations of structure parameters for 1024 point FFT */
+
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = armBitRevTable;
+    /*  Initialise the 1/fftLen Value */
+    S->onebyfftLen = 0.0009765625f;
+    break;
+
+
+  case 256u:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 4u;
+    S->bitRevFactor = 4u;
+    S->pBitRevTable = &armBitRevTable[3];
+    S->onebyfftLen = 0.00390625f;
+    break;
+
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = &armBitRevTable[15];
+    S->onebyfftLen = 0.015625f;
+    break;
+
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = &armBitRevTable[63];
+    S->onebyfftLen = 0.0625f;
+    break;
+
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**   
+ * @} end of CFFT_CIFFT group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
new file mode 100644
index 0000000000..3bb11df370
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
@@ -0,0 +1,415 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix4_init_q15.c   
+*   
+* Description:	Radix-4 Decimation in Frequency Q15 FFT & IFFT initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+
+/**   
+ * @addtogroup CFFT_CIFFT   
+ * @{   
+ */
+
+/*   
+* @brief  Twiddle factors Table   
+*/
+
+/**  
+* \par   
+* Example code for Q15 Twiddle factors Generation::   
+* \par   
+* 
    for(i = 0; i< N; i++)   
+* {   
+*	twiddleCoefQ15[2*i]= cos(i * 2*PI/(float)N);   
+*	twiddleCoefQ15[2*i+1]= sin(i * 2*PI/(float)N);   
+* } 
       
+* \par   
+* where N = 1024	and PI = 3.14159265358979   
+* \par   
+* Cos and Sin values are interleaved fashion   
+* \par   
+* Convert Floating point to Q15(Fixed point 1.15):   
+*	round(twiddleCoefQ15(i) * pow(2, 15))   
+*   
+*/
+
+static const q15_t twiddleCoefQ15[2048] = {
+  0x7fff, 0x0, 0x7fff, 0xc9, 0x7ffe, 0x192, 0x7ffa, 0x25b,
+  0x7ff6, 0x324, 0x7ff1, 0x3ed, 0x7fea, 0x4b6, 0x7fe2, 0x57f,
+  0x7fd9, 0x648, 0x7fce, 0x711, 0x7fc2, 0x7d9, 0x7fb5, 0x8a2,
+  0x7fa7, 0x96b, 0x7f98, 0xa33, 0x7f87, 0xafb, 0x7f75, 0xbc4,
+  0x7f62, 0xc8c, 0x7f4e, 0xd54, 0x7f38, 0xe1c, 0x7f22, 0xee4,
+  0x7f0a, 0xfab, 0x7ef0, 0x1073, 0x7ed6, 0x113a, 0x7eba, 0x1201,
+  0x7e9d, 0x12c8, 0x7e7f, 0x138f, 0x7e60, 0x1455, 0x7e3f, 0x151c,
+  0x7e1e, 0x15e2, 0x7dfb, 0x16a8, 0x7dd6, 0x176e, 0x7db1, 0x1833,
+  0x7d8a, 0x18f9, 0x7d63, 0x19be, 0x7d3a, 0x1a83, 0x7d0f, 0x1b47,
+  0x7ce4, 0x1c0c, 0x7cb7, 0x1cd0, 0x7c89, 0x1d93, 0x7c5a, 0x1e57,
+  0x7c2a, 0x1f1a, 0x7bf9, 0x1fdd, 0x7bc6, 0x209f, 0x7b92, 0x2162,
+  0x7b5d, 0x2224, 0x7b27, 0x22e5, 0x7aef, 0x23a7, 0x7ab7, 0x2467,
+  0x7a7d, 0x2528, 0x7a42, 0x25e8, 0x7a06, 0x26a8, 0x79c9, 0x2768,
+  0x798a, 0x2827, 0x794a, 0x28e5, 0x790a, 0x29a4, 0x78c8, 0x2a62,
+  0x7885, 0x2b1f, 0x7840, 0x2bdc, 0x77fb, 0x2c99, 0x77b4, 0x2d55,
+  0x776c, 0x2e11, 0x7723, 0x2ecc, 0x76d9, 0x2f87, 0x768e, 0x3042,
+  0x7642, 0x30fc, 0x75f4, 0x31b5, 0x75a6, 0x326e, 0x7556, 0x3327,
+  0x7505, 0x33df, 0x74b3, 0x3497, 0x7460, 0x354e, 0x740b, 0x3604,
+  0x73b6, 0x36ba, 0x735f, 0x3770, 0x7308, 0x3825, 0x72af, 0x38d9,
+  0x7255, 0x398d, 0x71fa, 0x3a40, 0x719e, 0x3af3, 0x7141, 0x3ba5,
+  0x70e3, 0x3c57, 0x7083, 0x3d08, 0x7023, 0x3db8, 0x6fc2, 0x3e68,
+  0x6f5f, 0x3f17, 0x6efb, 0x3fc6, 0x6e97, 0x4074, 0x6e31, 0x4121,
+  0x6dca, 0x41ce, 0x6d62, 0x427a, 0x6cf9, 0x4326, 0x6c8f, 0x43d1,
+  0x6c24, 0x447b, 0x6bb8, 0x4524, 0x6b4b, 0x45cd, 0x6add, 0x4675,
+  0x6a6e, 0x471d, 0x69fd, 0x47c4, 0x698c, 0x486a, 0x691a, 0x490f,
+  0x68a7, 0x49b4, 0x6832, 0x4a58, 0x67bd, 0x4afb, 0x6747, 0x4b9e,
+  0x66d0, 0x4c40, 0x6657, 0x4ce1, 0x65de, 0x4d81, 0x6564, 0x4e21,
+  0x64e9, 0x4ec0, 0x646c, 0x4f5e, 0x63ef, 0x4ffb, 0x6371, 0x5098,
+  0x62f2, 0x5134, 0x6272, 0x51cf, 0x61f1, 0x5269, 0x616f, 0x5303,
+  0x60ec, 0x539b, 0x6068, 0x5433, 0x5fe4, 0x54ca, 0x5f5e, 0x5560,
+  0x5ed7, 0x55f6, 0x5e50, 0x568a, 0x5dc8, 0x571e, 0x5d3e, 0x57b1,
+  0x5cb4, 0x5843, 0x5c29, 0x58d4, 0x5b9d, 0x5964, 0x5b10, 0x59f4,
+  0x5a82, 0x5a82, 0x59f4, 0x5b10, 0x5964, 0x5b9d, 0x58d4, 0x5c29,
+  0x5843, 0x5cb4, 0x57b1, 0x5d3e, 0x571e, 0x5dc8, 0x568a, 0x5e50,
+  0x55f6, 0x5ed7, 0x5560, 0x5f5e, 0x54ca, 0x5fe4, 0x5433, 0x6068,
+  0x539b, 0x60ec, 0x5303, 0x616f, 0x5269, 0x61f1, 0x51cf, 0x6272,
+  0x5134, 0x62f2, 0x5098, 0x6371, 0x4ffb, 0x63ef, 0x4f5e, 0x646c,
+  0x4ec0, 0x64e9, 0x4e21, 0x6564, 0x4d81, 0x65de, 0x4ce1, 0x6657,
+  0x4c40, 0x66d0, 0x4b9e, 0x6747, 0x4afb, 0x67bd, 0x4a58, 0x6832,
+  0x49b4, 0x68a7, 0x490f, 0x691a, 0x486a, 0x698c, 0x47c4, 0x69fd,
+  0x471d, 0x6a6e, 0x4675, 0x6add, 0x45cd, 0x6b4b, 0x4524, 0x6bb8,
+  0x447b, 0x6c24, 0x43d1, 0x6c8f, 0x4326, 0x6cf9, 0x427a, 0x6d62,
+  0x41ce, 0x6dca, 0x4121, 0x6e31, 0x4074, 0x6e97, 0x3fc6, 0x6efb,
+  0x3f17, 0x6f5f, 0x3e68, 0x6fc2, 0x3db8, 0x7023, 0x3d08, 0x7083,
+  0x3c57, 0x70e3, 0x3ba5, 0x7141, 0x3af3, 0x719e, 0x3a40, 0x71fa,
+  0x398d, 0x7255, 0x38d9, 0x72af, 0x3825, 0x7308, 0x3770, 0x735f,
+  0x36ba, 0x73b6, 0x3604, 0x740b, 0x354e, 0x7460, 0x3497, 0x74b3,
+  0x33df, 0x7505, 0x3327, 0x7556, 0x326e, 0x75a6, 0x31b5, 0x75f4,
+  0x30fc, 0x7642, 0x3042, 0x768e, 0x2f87, 0x76d9, 0x2ecc, 0x7723,
+  0x2e11, 0x776c, 0x2d55, 0x77b4, 0x2c99, 0x77fb, 0x2bdc, 0x7840,
+  0x2b1f, 0x7885, 0x2a62, 0x78c8, 0x29a4, 0x790a, 0x28e5, 0x794a,
+  0x2827, 0x798a, 0x2768, 0x79c9, 0x26a8, 0x7a06, 0x25e8, 0x7a42,
+  0x2528, 0x7a7d, 0x2467, 0x7ab7, 0x23a7, 0x7aef, 0x22e5, 0x7b27,
+  0x2224, 0x7b5d, 0x2162, 0x7b92, 0x209f, 0x7bc6, 0x1fdd, 0x7bf9,
+  0x1f1a, 0x7c2a, 0x1e57, 0x7c5a, 0x1d93, 0x7c89, 0x1cd0, 0x7cb7,
+  0x1c0c, 0x7ce4, 0x1b47, 0x7d0f, 0x1a83, 0x7d3a, 0x19be, 0x7d63,
+  0x18f9, 0x7d8a, 0x1833, 0x7db1, 0x176e, 0x7dd6, 0x16a8, 0x7dfb,
+  0x15e2, 0x7e1e, 0x151c, 0x7e3f, 0x1455, 0x7e60, 0x138f, 0x7e7f,
+  0x12c8, 0x7e9d, 0x1201, 0x7eba, 0x113a, 0x7ed6, 0x1073, 0x7ef0,
+  0xfab, 0x7f0a, 0xee4, 0x7f22, 0xe1c, 0x7f38, 0xd54, 0x7f4e,
+  0xc8c, 0x7f62, 0xbc4, 0x7f75, 0xafb, 0x7f87, 0xa33, 0x7f98,
+  0x96b, 0x7fa7, 0x8a2, 0x7fb5, 0x7d9, 0x7fc2, 0x711, 0x7fce,
+  0x648, 0x7fd9, 0x57f, 0x7fe2, 0x4b6, 0x7fea, 0x3ed, 0x7ff1,
+  0x324, 0x7ff6, 0x25b, 0x7ffa, 0x192, 0x7ffe, 0xc9, 0x7fff,
+  0x0, 0x7fff, 0xff37, 0x7fff, 0xfe6e, 0x7ffe, 0xfda5, 0x7ffa,
+  0xfcdc, 0x7ff6, 0xfc13, 0x7ff1, 0xfb4a, 0x7fea, 0xfa81, 0x7fe2,
+  0xf9b8, 0x7fd9, 0xf8ef, 0x7fce, 0xf827, 0x7fc2, 0xf75e, 0x7fb5,
+  0xf695, 0x7fa7, 0xf5cd, 0x7f98, 0xf505, 0x7f87, 0xf43c, 0x7f75,
+  0xf374, 0x7f62, 0xf2ac, 0x7f4e, 0xf1e4, 0x7f38, 0xf11c, 0x7f22,
+  0xf055, 0x7f0a, 0xef8d, 0x7ef0, 0xeec6, 0x7ed6, 0xedff, 0x7eba,
+  0xed38, 0x7e9d, 0xec71, 0x7e7f, 0xebab, 0x7e60, 0xeae4, 0x7e3f,
+  0xea1e, 0x7e1e, 0xe958, 0x7dfb, 0xe892, 0x7dd6, 0xe7cd, 0x7db1,
+  0xe707, 0x7d8a, 0xe642, 0x7d63, 0xe57d, 0x7d3a, 0xe4b9, 0x7d0f,
+  0xe3f4, 0x7ce4, 0xe330, 0x7cb7, 0xe26d, 0x7c89, 0xe1a9, 0x7c5a,
+  0xe0e6, 0x7c2a, 0xe023, 0x7bf9, 0xdf61, 0x7bc6, 0xde9e, 0x7b92,
+  0xdddc, 0x7b5d, 0xdd1b, 0x7b27, 0xdc59, 0x7aef, 0xdb99, 0x7ab7,
+  0xdad8, 0x7a7d, 0xda18, 0x7a42, 0xd958, 0x7a06, 0xd898, 0x79c9,
+  0xd7d9, 0x798a, 0xd71b, 0x794a, 0xd65c, 0x790a, 0xd59e, 0x78c8,
+  0xd4e1, 0x7885, 0xd424, 0x7840, 0xd367, 0x77fb, 0xd2ab, 0x77b4,
+  0xd1ef, 0x776c, 0xd134, 0x7723, 0xd079, 0x76d9, 0xcfbe, 0x768e,
+  0xcf04, 0x7642, 0xce4b, 0x75f4, 0xcd92, 0x75a6, 0xccd9, 0x7556,
+  0xcc21, 0x7505, 0xcb69, 0x74b3, 0xcab2, 0x7460, 0xc9fc, 0x740b,
+  0xc946, 0x73b6, 0xc890, 0x735f, 0xc7db, 0x7308, 0xc727, 0x72af,
+  0xc673, 0x7255, 0xc5c0, 0x71fa, 0xc50d, 0x719e, 0xc45b, 0x7141,
+  0xc3a9, 0x70e3, 0xc2f8, 0x7083, 0xc248, 0x7023, 0xc198, 0x6fc2,
+  0xc0e9, 0x6f5f, 0xc03a, 0x6efb, 0xbf8c, 0x6e97, 0xbedf, 0x6e31,
+  0xbe32, 0x6dca, 0xbd86, 0x6d62, 0xbcda, 0x6cf9, 0xbc2f, 0x6c8f,
+  0xbb85, 0x6c24, 0xbadc, 0x6bb8, 0xba33, 0x6b4b, 0xb98b, 0x6add,
+  0xb8e3, 0x6a6e, 0xb83c, 0x69fd, 0xb796, 0x698c, 0xb6f1, 0x691a,
+  0xb64c, 0x68a7, 0xb5a8, 0x6832, 0xb505, 0x67bd, 0xb462, 0x6747,
+  0xb3c0, 0x66d0, 0xb31f, 0x6657, 0xb27f, 0x65de, 0xb1df, 0x6564,
+  0xb140, 0x64e9, 0xb0a2, 0x646c, 0xb005, 0x63ef, 0xaf68, 0x6371,
+  0xaecc, 0x62f2, 0xae31, 0x6272, 0xad97, 0x61f1, 0xacfd, 0x616f,
+  0xac65, 0x60ec, 0xabcd, 0x6068, 0xab36, 0x5fe4, 0xaaa0, 0x5f5e,
+  0xaa0a, 0x5ed7, 0xa976, 0x5e50, 0xa8e2, 0x5dc8, 0xa84f, 0x5d3e,
+  0xa7bd, 0x5cb4, 0xa72c, 0x5c29, 0xa69c, 0x5b9d, 0xa60c, 0x5b10,
+  0xa57e, 0x5a82, 0xa4f0, 0x59f4, 0xa463, 0x5964, 0xa3d7, 0x58d4,
+  0xa34c, 0x5843, 0xa2c2, 0x57b1, 0xa238, 0x571e, 0xa1b0, 0x568a,
+  0xa129, 0x55f6, 0xa0a2, 0x5560, 0xa01c, 0x54ca, 0x9f98, 0x5433,
+  0x9f14, 0x539b, 0x9e91, 0x5303, 0x9e0f, 0x5269, 0x9d8e, 0x51cf,
+  0x9d0e, 0x5134, 0x9c8f, 0x5098, 0x9c11, 0x4ffb, 0x9b94, 0x4f5e,
+  0x9b17, 0x4ec0, 0x9a9c, 0x4e21, 0x9a22, 0x4d81, 0x99a9, 0x4ce1,
+  0x9930, 0x4c40, 0x98b9, 0x4b9e, 0x9843, 0x4afb, 0x97ce, 0x4a58,
+  0x9759, 0x49b4, 0x96e6, 0x490f, 0x9674, 0x486a, 0x9603, 0x47c4,
+  0x9592, 0x471d, 0x9523, 0x4675, 0x94b5, 0x45cd, 0x9448, 0x4524,
+  0x93dc, 0x447b, 0x9371, 0x43d1, 0x9307, 0x4326, 0x929e, 0x427a,
+  0x9236, 0x41ce, 0x91cf, 0x4121, 0x9169, 0x4074, 0x9105, 0x3fc6,
+  0x90a1, 0x3f17, 0x903e, 0x3e68, 0x8fdd, 0x3db8, 0x8f7d, 0x3d08,
+  0x8f1d, 0x3c57, 0x8ebf, 0x3ba5, 0x8e62, 0x3af3, 0x8e06, 0x3a40,
+  0x8dab, 0x398d, 0x8d51, 0x38d9, 0x8cf8, 0x3825, 0x8ca1, 0x3770,
+  0x8c4a, 0x36ba, 0x8bf5, 0x3604, 0x8ba0, 0x354e, 0x8b4d, 0x3497,
+  0x8afb, 0x33df, 0x8aaa, 0x3327, 0x8a5a, 0x326e, 0x8a0c, 0x31b5,
+  0x89be, 0x30fc, 0x8972, 0x3042, 0x8927, 0x2f87, 0x88dd, 0x2ecc,
+  0x8894, 0x2e11, 0x884c, 0x2d55, 0x8805, 0x2c99, 0x87c0, 0x2bdc,
+  0x877b, 0x2b1f, 0x8738, 0x2a62, 0x86f6, 0x29a4, 0x86b6, 0x28e5,
+  0x8676, 0x2827, 0x8637, 0x2768, 0x85fa, 0x26a8, 0x85be, 0x25e8,
+  0x8583, 0x2528, 0x8549, 0x2467, 0x8511, 0x23a7, 0x84d9, 0x22e5,
+  0x84a3, 0x2224, 0x846e, 0x2162, 0x843a, 0x209f, 0x8407, 0x1fdd,
+  0x83d6, 0x1f1a, 0x83a6, 0x1e57, 0x8377, 0x1d93, 0x8349, 0x1cd0,
+  0x831c, 0x1c0c, 0x82f1, 0x1b47, 0x82c6, 0x1a83, 0x829d, 0x19be,
+  0x8276, 0x18f9, 0x824f, 0x1833, 0x822a, 0x176e, 0x8205, 0x16a8,
+  0x81e2, 0x15e2, 0x81c1, 0x151c, 0x81a0, 0x1455, 0x8181, 0x138f,
+  0x8163, 0x12c8, 0x8146, 0x1201, 0x812a, 0x113a, 0x8110, 0x1073,
+  0x80f6, 0xfab, 0x80de, 0xee4, 0x80c8, 0xe1c, 0x80b2, 0xd54,
+  0x809e, 0xc8c, 0x808b, 0xbc4, 0x8079, 0xafb, 0x8068, 0xa33,
+  0x8059, 0x96b, 0x804b, 0x8a2, 0x803e, 0x7d9, 0x8032, 0x711,
+  0x8027, 0x648, 0x801e, 0x57f, 0x8016, 0x4b6, 0x800f, 0x3ed,
+  0x800a, 0x324, 0x8006, 0x25b, 0x8002, 0x192, 0x8001, 0xc9,
+  0x8000, 0x0, 0x8001, 0xff37, 0x8002, 0xfe6e, 0x8006, 0xfda5,
+  0x800a, 0xfcdc, 0x800f, 0xfc13, 0x8016, 0xfb4a, 0x801e, 0xfa81,
+  0x8027, 0xf9b8, 0x8032, 0xf8ef, 0x803e, 0xf827, 0x804b, 0xf75e,
+  0x8059, 0xf695, 0x8068, 0xf5cd, 0x8079, 0xf505, 0x808b, 0xf43c,
+  0x809e, 0xf374, 0x80b2, 0xf2ac, 0x80c8, 0xf1e4, 0x80de, 0xf11c,
+  0x80f6, 0xf055, 0x8110, 0xef8d, 0x812a, 0xeec6, 0x8146, 0xedff,
+  0x8163, 0xed38, 0x8181, 0xec71, 0x81a0, 0xebab, 0x81c1, 0xeae4,
+  0x81e2, 0xea1e, 0x8205, 0xe958, 0x822a, 0xe892, 0x824f, 0xe7cd,
+  0x8276, 0xe707, 0x829d, 0xe642, 0x82c6, 0xe57d, 0x82f1, 0xe4b9,
+  0x831c, 0xe3f4, 0x8349, 0xe330, 0x8377, 0xe26d, 0x83a6, 0xe1a9,
+  0x83d6, 0xe0e6, 0x8407, 0xe023, 0x843a, 0xdf61, 0x846e, 0xde9e,
+  0x84a3, 0xdddc, 0x84d9, 0xdd1b, 0x8511, 0xdc59, 0x8549, 0xdb99,
+  0x8583, 0xdad8, 0x85be, 0xda18, 0x85fa, 0xd958, 0x8637, 0xd898,
+  0x8676, 0xd7d9, 0x86b6, 0xd71b, 0x86f6, 0xd65c, 0x8738, 0xd59e,
+  0x877b, 0xd4e1, 0x87c0, 0xd424, 0x8805, 0xd367, 0x884c, 0xd2ab,
+  0x8894, 0xd1ef, 0x88dd, 0xd134, 0x8927, 0xd079, 0x8972, 0xcfbe,
+  0x89be, 0xcf04, 0x8a0c, 0xce4b, 0x8a5a, 0xcd92, 0x8aaa, 0xccd9,
+  0x8afb, 0xcc21, 0x8b4d, 0xcb69, 0x8ba0, 0xcab2, 0x8bf5, 0xc9fc,
+  0x8c4a, 0xc946, 0x8ca1, 0xc890, 0x8cf8, 0xc7db, 0x8d51, 0xc727,
+  0x8dab, 0xc673, 0x8e06, 0xc5c0, 0x8e62, 0xc50d, 0x8ebf, 0xc45b,
+  0x8f1d, 0xc3a9, 0x8f7d, 0xc2f8, 0x8fdd, 0xc248, 0x903e, 0xc198,
+  0x90a1, 0xc0e9, 0x9105, 0xc03a, 0x9169, 0xbf8c, 0x91cf, 0xbedf,
+  0x9236, 0xbe32, 0x929e, 0xbd86, 0x9307, 0xbcda, 0x9371, 0xbc2f,
+  0x93dc, 0xbb85, 0x9448, 0xbadc, 0x94b5, 0xba33, 0x9523, 0xb98b,
+  0x9592, 0xb8e3, 0x9603, 0xb83c, 0x9674, 0xb796, 0x96e6, 0xb6f1,
+  0x9759, 0xb64c, 0x97ce, 0xb5a8, 0x9843, 0xb505, 0x98b9, 0xb462,
+  0x9930, 0xb3c0, 0x99a9, 0xb31f, 0x9a22, 0xb27f, 0x9a9c, 0xb1df,
+  0x9b17, 0xb140, 0x9b94, 0xb0a2, 0x9c11, 0xb005, 0x9c8f, 0xaf68,
+  0x9d0e, 0xaecc, 0x9d8e, 0xae31, 0x9e0f, 0xad97, 0x9e91, 0xacfd,
+  0x9f14, 0xac65, 0x9f98, 0xabcd, 0xa01c, 0xab36, 0xa0a2, 0xaaa0,
+  0xa129, 0xaa0a, 0xa1b0, 0xa976, 0xa238, 0xa8e2, 0xa2c2, 0xa84f,
+  0xa34c, 0xa7bd, 0xa3d7, 0xa72c, 0xa463, 0xa69c, 0xa4f0, 0xa60c,
+  0xa57e, 0xa57e, 0xa60c, 0xa4f0, 0xa69c, 0xa463, 0xa72c, 0xa3d7,
+  0xa7bd, 0xa34c, 0xa84f, 0xa2c2, 0xa8e2, 0xa238, 0xa976, 0xa1b0,
+  0xaa0a, 0xa129, 0xaaa0, 0xa0a2, 0xab36, 0xa01c, 0xabcd, 0x9f98,
+  0xac65, 0x9f14, 0xacfd, 0x9e91, 0xad97, 0x9e0f, 0xae31, 0x9d8e,
+  0xaecc, 0x9d0e, 0xaf68, 0x9c8f, 0xb005, 0x9c11, 0xb0a2, 0x9b94,
+  0xb140, 0x9b17, 0xb1df, 0x9a9c, 0xb27f, 0x9a22, 0xb31f, 0x99a9,
+  0xb3c0, 0x9930, 0xb462, 0x98b9, 0xb505, 0x9843, 0xb5a8, 0x97ce,
+  0xb64c, 0x9759, 0xb6f1, 0x96e6, 0xb796, 0x9674, 0xb83c, 0x9603,
+  0xb8e3, 0x9592, 0xb98b, 0x9523, 0xba33, 0x94b5, 0xbadc, 0x9448,
+  0xbb85, 0x93dc, 0xbc2f, 0x9371, 0xbcda, 0x9307, 0xbd86, 0x929e,
+  0xbe32, 0x9236, 0xbedf, 0x91cf, 0xbf8c, 0x9169, 0xc03a, 0x9105,
+  0xc0e9, 0x90a1, 0xc198, 0x903e, 0xc248, 0x8fdd, 0xc2f8, 0x8f7d,
+  0xc3a9, 0x8f1d, 0xc45b, 0x8ebf, 0xc50d, 0x8e62, 0xc5c0, 0x8e06,
+  0xc673, 0x8dab, 0xc727, 0x8d51, 0xc7db, 0x8cf8, 0xc890, 0x8ca1,
+  0xc946, 0x8c4a, 0xc9fc, 0x8bf5, 0xcab2, 0x8ba0, 0xcb69, 0x8b4d,
+  0xcc21, 0x8afb, 0xccd9, 0x8aaa, 0xcd92, 0x8a5a, 0xce4b, 0x8a0c,
+  0xcf04, 0x89be, 0xcfbe, 0x8972, 0xd079, 0x8927, 0xd134, 0x88dd,
+  0xd1ef, 0x8894, 0xd2ab, 0x884c, 0xd367, 0x8805, 0xd424, 0x87c0,
+  0xd4e1, 0x877b, 0xd59e, 0x8738, 0xd65c, 0x86f6, 0xd71b, 0x86b6,
+  0xd7d9, 0x8676, 0xd898, 0x8637, 0xd958, 0x85fa, 0xda18, 0x85be,
+  0xdad8, 0x8583, 0xdb99, 0x8549, 0xdc59, 0x8511, 0xdd1b, 0x84d9,
+  0xdddc, 0x84a3, 0xde9e, 0x846e, 0xdf61, 0x843a, 0xe023, 0x8407,
+  0xe0e6, 0x83d6, 0xe1a9, 0x83a6, 0xe26d, 0x8377, 0xe330, 0x8349,
+  0xe3f4, 0x831c, 0xe4b9, 0x82f1, 0xe57d, 0x82c6, 0xe642, 0x829d,
+  0xe707, 0x8276, 0xe7cd, 0x824f, 0xe892, 0x822a, 0xe958, 0x8205,
+  0xea1e, 0x81e2, 0xeae4, 0x81c1, 0xebab, 0x81a0, 0xec71, 0x8181,
+  0xed38, 0x8163, 0xedff, 0x8146, 0xeec6, 0x812a, 0xef8d, 0x8110,
+  0xf055, 0x80f6, 0xf11c, 0x80de, 0xf1e4, 0x80c8, 0xf2ac, 0x80b2,
+  0xf374, 0x809e, 0xf43c, 0x808b, 0xf505, 0x8079, 0xf5cd, 0x8068,
+  0xf695, 0x8059, 0xf75e, 0x804b, 0xf827, 0x803e, 0xf8ef, 0x8032,
+  0xf9b8, 0x8027, 0xfa81, 0x801e, 0xfb4a, 0x8016, 0xfc13, 0x800f,
+  0xfcdc, 0x800a, 0xfda5, 0x8006, 0xfe6e, 0x8002, 0xff37, 0x8001,
+  0x0, 0x8000, 0xc9, 0x8001, 0x192, 0x8002, 0x25b, 0x8006,
+  0x324, 0x800a, 0x3ed, 0x800f, 0x4b6, 0x8016, 0x57f, 0x801e,
+  0x648, 0x8027, 0x711, 0x8032, 0x7d9, 0x803e, 0x8a2, 0x804b,
+  0x96b, 0x8059, 0xa33, 0x8068, 0xafb, 0x8079, 0xbc4, 0x808b,
+  0xc8c, 0x809e, 0xd54, 0x80b2, 0xe1c, 0x80c8, 0xee4, 0x80de,
+  0xfab, 0x80f6, 0x1073, 0x8110, 0x113a, 0x812a, 0x1201, 0x8146,
+  0x12c8, 0x8163, 0x138f, 0x8181, 0x1455, 0x81a0, 0x151c, 0x81c1,
+  0x15e2, 0x81e2, 0x16a8, 0x8205, 0x176e, 0x822a, 0x1833, 0x824f,
+  0x18f9, 0x8276, 0x19be, 0x829d, 0x1a83, 0x82c6, 0x1b47, 0x82f1,
+  0x1c0c, 0x831c, 0x1cd0, 0x8349, 0x1d93, 0x8377, 0x1e57, 0x83a6,
+  0x1f1a, 0x83d6, 0x1fdd, 0x8407, 0x209f, 0x843a, 0x2162, 0x846e,
+  0x2224, 0x84a3, 0x22e5, 0x84d9, 0x23a7, 0x8511, 0x2467, 0x8549,
+  0x2528, 0x8583, 0x25e8, 0x85be, 0x26a8, 0x85fa, 0x2768, 0x8637,
+  0x2827, 0x8676, 0x28e5, 0x86b6, 0x29a4, 0x86f6, 0x2a62, 0x8738,
+  0x2b1f, 0x877b, 0x2bdc, 0x87c0, 0x2c99, 0x8805, 0x2d55, 0x884c,
+  0x2e11, 0x8894, 0x2ecc, 0x88dd, 0x2f87, 0x8927, 0x3042, 0x8972,
+  0x30fc, 0x89be, 0x31b5, 0x8a0c, 0x326e, 0x8a5a, 0x3327, 0x8aaa,
+  0x33df, 0x8afb, 0x3497, 0x8b4d, 0x354e, 0x8ba0, 0x3604, 0x8bf5,
+  0x36ba, 0x8c4a, 0x3770, 0x8ca1, 0x3825, 0x8cf8, 0x38d9, 0x8d51,
+  0x398d, 0x8dab, 0x3a40, 0x8e06, 0x3af3, 0x8e62, 0x3ba5, 0x8ebf,
+  0x3c57, 0x8f1d, 0x3d08, 0x8f7d, 0x3db8, 0x8fdd, 0x3e68, 0x903e,
+  0x3f17, 0x90a1, 0x3fc6, 0x9105, 0x4074, 0x9169, 0x4121, 0x91cf,
+  0x41ce, 0x9236, 0x427a, 0x929e, 0x4326, 0x9307, 0x43d1, 0x9371,
+  0x447b, 0x93dc, 0x4524, 0x9448, 0x45cd, 0x94b5, 0x4675, 0x9523,
+  0x471d, 0x9592, 0x47c4, 0x9603, 0x486a, 0x9674, 0x490f, 0x96e6,
+  0x49b4, 0x9759, 0x4a58, 0x97ce, 0x4afb, 0x9843, 0x4b9e, 0x98b9,
+  0x4c40, 0x9930, 0x4ce1, 0x99a9, 0x4d81, 0x9a22, 0x4e21, 0x9a9c,
+  0x4ec0, 0x9b17, 0x4f5e, 0x9b94, 0x4ffb, 0x9c11, 0x5098, 0x9c8f,
+  0x5134, 0x9d0e, 0x51cf, 0x9d8e, 0x5269, 0x9e0f, 0x5303, 0x9e91,
+  0x539b, 0x9f14, 0x5433, 0x9f98, 0x54ca, 0xa01c, 0x5560, 0xa0a2,
+  0x55f6, 0xa129, 0x568a, 0xa1b0, 0x571e, 0xa238, 0x57b1, 0xa2c2,
+  0x5843, 0xa34c, 0x58d4, 0xa3d7, 0x5964, 0xa463, 0x59f4, 0xa4f0,
+  0x5a82, 0xa57e, 0x5b10, 0xa60c, 0x5b9d, 0xa69c, 0x5c29, 0xa72c,
+  0x5cb4, 0xa7bd, 0x5d3e, 0xa84f, 0x5dc8, 0xa8e2, 0x5e50, 0xa976,
+  0x5ed7, 0xaa0a, 0x5f5e, 0xaaa0, 0x5fe4, 0xab36, 0x6068, 0xabcd,
+  0x60ec, 0xac65, 0x616f, 0xacfd, 0x61f1, 0xad97, 0x6272, 0xae31,
+  0x62f2, 0xaecc, 0x6371, 0xaf68, 0x63ef, 0xb005, 0x646c, 0xb0a2,
+  0x64e9, 0xb140, 0x6564, 0xb1df, 0x65de, 0xb27f, 0x6657, 0xb31f,
+  0x66d0, 0xb3c0, 0x6747, 0xb462, 0x67bd, 0xb505, 0x6832, 0xb5a8,
+  0x68a7, 0xb64c, 0x691a, 0xb6f1, 0x698c, 0xb796, 0x69fd, 0xb83c,
+  0x6a6e, 0xb8e3, 0x6add, 0xb98b, 0x6b4b, 0xba33, 0x6bb8, 0xbadc,
+  0x6c24, 0xbb85, 0x6c8f, 0xbc2f, 0x6cf9, 0xbcda, 0x6d62, 0xbd86,
+  0x6dca, 0xbe32, 0x6e31, 0xbedf, 0x6e97, 0xbf8c, 0x6efb, 0xc03a,
+  0x6f5f, 0xc0e9, 0x6fc2, 0xc198, 0x7023, 0xc248, 0x7083, 0xc2f8,
+  0x70e3, 0xc3a9, 0x7141, 0xc45b, 0x719e, 0xc50d, 0x71fa, 0xc5c0,
+  0x7255, 0xc673, 0x72af, 0xc727, 0x7308, 0xc7db, 0x735f, 0xc890,
+  0x73b6, 0xc946, 0x740b, 0xc9fc, 0x7460, 0xcab2, 0x74b3, 0xcb69,
+  0x7505, 0xcc21, 0x7556, 0xccd9, 0x75a6, 0xcd92, 0x75f4, 0xce4b,
+  0x7642, 0xcf04, 0x768e, 0xcfbe, 0x76d9, 0xd079, 0x7723, 0xd134,
+  0x776c, 0xd1ef, 0x77b4, 0xd2ab, 0x77fb, 0xd367, 0x7840, 0xd424,
+  0x7885, 0xd4e1, 0x78c8, 0xd59e, 0x790a, 0xd65c, 0x794a, 0xd71b,
+  0x798a, 0xd7d9, 0x79c9, 0xd898, 0x7a06, 0xd958, 0x7a42, 0xda18,
+  0x7a7d, 0xdad8, 0x7ab7, 0xdb99, 0x7aef, 0xdc59, 0x7b27, 0xdd1b,
+  0x7b5d, 0xdddc, 0x7b92, 0xde9e, 0x7bc6, 0xdf61, 0x7bf9, 0xe023,
+  0x7c2a, 0xe0e6, 0x7c5a, 0xe1a9, 0x7c89, 0xe26d, 0x7cb7, 0xe330,
+  0x7ce4, 0xe3f4, 0x7d0f, 0xe4b9, 0x7d3a, 0xe57d, 0x7d63, 0xe642,
+  0x7d8a, 0xe707, 0x7db1, 0xe7cd, 0x7dd6, 0xe892, 0x7dfb, 0xe958,
+  0x7e1e, 0xea1e, 0x7e3f, 0xeae4, 0x7e60, 0xebab, 0x7e7f, 0xec71,
+  0x7e9d, 0xed38, 0x7eba, 0xedff, 0x7ed6, 0xeec6, 0x7ef0, 0xef8d,
+  0x7f0a, 0xf055, 0x7f22, 0xf11c, 0x7f38, 0xf1e4, 0x7f4e, 0xf2ac,
+  0x7f62, 0xf374, 0x7f75, 0xf43c, 0x7f87, 0xf505, 0x7f98, 0xf5cd,
+  0x7fa7, 0xf695, 0x7fb5, 0xf75e, 0x7fc2, 0xf827, 0x7fce, 0xf8ef,
+  0x7fd9, 0xf9b8, 0x7fe2, 0xfa81, 0x7fea, 0xfb4a, 0x7ff1, 0xfc13,
+  0x7ff6, 0xfcdc, 0x7ffa, 0xfda5, 0x7ffe, 0xfe6e, 0x7fff, 0xff37
+};
+
+
+/**   
+* @brief Initialization function for the Q15 CFFT/CIFFT.  
+* @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.  
+* @param[in]     fftLen         length of the FFT.  
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  
+*   
+* \par Description:  
+* \par   
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par   
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
+* \par   
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
+*/
+
+arm_status arm_cfft_radix4_init_q15(
+  arm_cfft_radix4_instance_q15 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (q15_t *) twiddleCoefQ15;
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLen)
+  {
+    /*  Initializations of structure parameters for 1024 point FFT */
+  case 1024u:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = armBitRevTable;
+
+    break;
+  case 256u:
+    /*  Initializations of structure parameters for 2566 point FFT */
+    S->twidCoefModifier = 4u;
+    S->bitRevFactor = 4u;
+    S->pBitRevTable = &armBitRevTable[3];
+
+    break;
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = &armBitRevTable[15];
+
+    break;
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = &armBitRevTable[63];
+
+    break;
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**   
+ * @} end of CFFT_CIFFT group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
new file mode 100644
index 0000000000..eba07ed548
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
@@ -0,0 +1,670 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix4_init_q31.c   
+*   
+* Description:	Radix-4 Decimation in Frequency Q31 FFT & IFFT initialization function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+#include "arm_common_tables.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup CFFT_CIFFT   
+ * @{   
+ */
+
+/*   
+* @brief  Twiddle factors Table   
+*/
+
+/**   
+* \par  
+* Example code for Q31 Twiddle factors Generation::   
+* \par   
+* 
    for(i = 0; i< N; i++)   
+* {   
+*    twiddleCoefQ31[2*i]= cos(i * 2*PI/(float)N);   
+*    twiddleCoefQ31[2*i+1]= sin(i * 2*PI/(float)N);   
+* } 
       
+* \par   
+* where N = 1024	and PI = 3.14159265358979   
+* \par   
+* Cos and Sin values are interleaved fashion   
+* \par   
+* Convert Floating point to Q31(Fixed point 1.31):   
+*	round(twiddleCoefQ31(i) * pow(2, 31))   
+*   
+*/
+
+static const q31_t twiddleCoefQ31[2048] = {
+  0x7fffffff, 0x0, 0x7fff6216, 0xc90f88, 0x7ffd885a, 0x1921d20, 0x7ffa72d1,
+  0x25b26d7,
+  0x7ff62182, 0x3242abf, 0x7ff09478, 0x3ed26e6, 0x7fe9cbc0, 0x4b6195d,
+  0x7fe1c76b, 0x57f0035,
+  0x7fd8878e, 0x647d97c, 0x7fce0c3e, 0x710a345, 0x7fc25596, 0x7d95b9e,
+  0x7fb563b3, 0x8a2009a,
+  0x7fa736b4, 0x96a9049, 0x7f97cebd, 0xa3308bd, 0x7f872bf3, 0xafb6805,
+  0x7f754e80, 0xbc3ac35,
+  0x7f62368f, 0xc8bd35e, 0x7f4de451, 0xd53db92, 0x7f3857f6, 0xe1bc2e4,
+  0x7f2191b4, 0xee38766,
+  0x7f0991c4, 0xfab272b, 0x7ef05860, 0x1072a048, 0x7ed5e5c6, 0x1139f0cf,
+  0x7eba3a39, 0x120116d5,
+  0x7e9d55fc, 0x12c8106f, 0x7e7f3957, 0x138edbb1, 0x7e5fe493, 0x145576b1,
+  0x7e3f57ff, 0x151bdf86,
+  0x7e1d93ea, 0x15e21445, 0x7dfa98a8, 0x16a81305, 0x7dd6668f, 0x176dd9de,
+  0x7db0fdf8, 0x183366e9,
+  0x7d8a5f40, 0x18f8b83c, 0x7d628ac6, 0x19bdcbf3, 0x7d3980ec, 0x1a82a026,
+  0x7d0f4218, 0x1b4732ef,
+  0x7ce3ceb2, 0x1c0b826a, 0x7cb72724, 0x1ccf8cb3, 0x7c894bde, 0x1d934fe5,
+  0x7c5a3d50, 0x1e56ca1e,
+  0x7c29fbee, 0x1f19f97b, 0x7bf88830, 0x1fdcdc1b, 0x7bc5e290, 0x209f701c,
+  0x7b920b89, 0x2161b3a0,
+  0x7b5d039e, 0x2223a4c5, 0x7b26cb4f, 0x22e541af, 0x7aef6323, 0x23a6887f,
+  0x7ab6cba4, 0x24677758,
+  0x7a7d055b, 0x25280c5e, 0x7a4210d8, 0x25e845b6, 0x7a05eead, 0x26a82186,
+  0x79c89f6e, 0x27679df4,
+  0x798a23b1, 0x2826b928, 0x794a7c12, 0x28e5714b, 0x7909a92d, 0x29a3c485,
+  0x78c7aba2, 0x2a61b101,
+  0x78848414, 0x2b1f34eb, 0x78403329, 0x2bdc4e6f, 0x77fab989, 0x2c98fbba,
+  0x77b417df, 0x2d553afc,
+  0x776c4edb, 0x2e110a62, 0x77235f2d, 0x2ecc681e, 0x76d94989, 0x2f875262,
+  0x768e0ea6, 0x3041c761,
+  0x7641af3d, 0x30fbc54d, 0x75f42c0b, 0x31b54a5e, 0x75a585cf, 0x326e54c7,
+  0x7555bd4c, 0x3326e2c3,
+  0x7504d345, 0x33def287, 0x74b2c884, 0x34968250, 0x745f9dd1, 0x354d9057,
+  0x740b53fb, 0x36041ad9,
+  0x73b5ebd1, 0x36ba2014, 0x735f6626, 0x376f9e46, 0x7307c3d0, 0x382493b0,
+  0x72af05a7, 0x38d8fe93,
+  0x72552c85, 0x398cdd32, 0x71fa3949, 0x3a402dd2, 0x719e2cd2, 0x3af2eeb7,
+  0x71410805, 0x3ba51e29,
+  0x70e2cbc6, 0x3c56ba70, 0x708378ff, 0x3d07c1d6, 0x7023109a, 0x3db832a6,
+  0x6fc19385, 0x3e680b2c,
+  0x6f5f02b2, 0x3f1749b8, 0x6efb5f12, 0x3fc5ec98, 0x6e96a99d, 0x4073f21d,
+  0x6e30e34a, 0x4121589b,
+  0x6dca0d14, 0x41ce1e65, 0x6d6227fa, 0x427a41d0, 0x6cf934fc, 0x4325c135,
+  0x6c8f351c, 0x43d09aed,
+  0x6c242960, 0x447acd50, 0x6bb812d1, 0x452456bd, 0x6b4af279, 0x45cd358f,
+  0x6adcc964, 0x46756828,
+  0x6a6d98a4, 0x471cece7, 0x69fd614a, 0x47c3c22f, 0x698c246c, 0x4869e665,
+  0x6919e320, 0x490f57ee,
+  0x68a69e81, 0x49b41533, 0x683257ab, 0x4a581c9e, 0x67bd0fbd, 0x4afb6c98,
+  0x6746c7d8, 0x4b9e0390,
+  0x66cf8120, 0x4c3fdff4, 0x66573cbb, 0x4ce10034, 0x65ddfbd3, 0x4d8162c4,
+  0x6563bf92, 0x4e210617,
+  0x64e88926, 0x4ebfe8a5, 0x646c59bf, 0x4f5e08e3, 0x63ef3290, 0x4ffb654d,
+  0x637114cc, 0x5097fc5e,
+  0x62f201ac, 0x5133cc94, 0x6271fa69, 0x51ced46e, 0x61f1003f, 0x5269126e,
+  0x616f146c, 0x53028518,
+  0x60ec3830, 0x539b2af0, 0x60686ccf, 0x5433027d, 0x5fe3b38d, 0x54ca0a4b,
+  0x5f5e0db3, 0x556040e2,
+  0x5ed77c8a, 0x55f5a4d2, 0x5e50015d, 0x568a34a9, 0x5dc79d7c, 0x571deefa,
+  0x5d3e5237, 0x57b0d256,
+  0x5cb420e0, 0x5842dd54, 0x5c290acc, 0x58d40e8c, 0x5b9d1154, 0x59646498,
+  0x5b1035cf, 0x59f3de12,
+  0x5a82799a, 0x5a82799a, 0x59f3de12, 0x5b1035cf, 0x59646498, 0x5b9d1154,
+  0x58d40e8c, 0x5c290acc,
+  0x5842dd54, 0x5cb420e0, 0x57b0d256, 0x5d3e5237, 0x571deefa, 0x5dc79d7c,
+  0x568a34a9, 0x5e50015d,
+  0x55f5a4d2, 0x5ed77c8a, 0x556040e2, 0x5f5e0db3, 0x54ca0a4b, 0x5fe3b38d,
+  0x5433027d, 0x60686ccf,
+  0x539b2af0, 0x60ec3830, 0x53028518, 0x616f146c, 0x5269126e, 0x61f1003f,
+  0x51ced46e, 0x6271fa69,
+  0x5133cc94, 0x62f201ac, 0x5097fc5e, 0x637114cc, 0x4ffb654d, 0x63ef3290,
+  0x4f5e08e3, 0x646c59bf,
+  0x4ebfe8a5, 0x64e88926, 0x4e210617, 0x6563bf92, 0x4d8162c4, 0x65ddfbd3,
+  0x4ce10034, 0x66573cbb,
+  0x4c3fdff4, 0x66cf8120, 0x4b9e0390, 0x6746c7d8, 0x4afb6c98, 0x67bd0fbd,
+  0x4a581c9e, 0x683257ab,
+  0x49b41533, 0x68a69e81, 0x490f57ee, 0x6919e320, 0x4869e665, 0x698c246c,
+  0x47c3c22f, 0x69fd614a,
+  0x471cece7, 0x6a6d98a4, 0x46756828, 0x6adcc964, 0x45cd358f, 0x6b4af279,
+  0x452456bd, 0x6bb812d1,
+  0x447acd50, 0x6c242960, 0x43d09aed, 0x6c8f351c, 0x4325c135, 0x6cf934fc,
+  0x427a41d0, 0x6d6227fa,
+  0x41ce1e65, 0x6dca0d14, 0x4121589b, 0x6e30e34a, 0x4073f21d, 0x6e96a99d,
+  0x3fc5ec98, 0x6efb5f12,
+  0x3f1749b8, 0x6f5f02b2, 0x3e680b2c, 0x6fc19385, 0x3db832a6, 0x7023109a,
+  0x3d07c1d6, 0x708378ff,
+  0x3c56ba70, 0x70e2cbc6, 0x3ba51e29, 0x71410805, 0x3af2eeb7, 0x719e2cd2,
+  0x3a402dd2, 0x71fa3949,
+  0x398cdd32, 0x72552c85, 0x38d8fe93, 0x72af05a7, 0x382493b0, 0x7307c3d0,
+  0x376f9e46, 0x735f6626,
+  0x36ba2014, 0x73b5ebd1, 0x36041ad9, 0x740b53fb, 0x354d9057, 0x745f9dd1,
+  0x34968250, 0x74b2c884,
+  0x33def287, 0x7504d345, 0x3326e2c3, 0x7555bd4c, 0x326e54c7, 0x75a585cf,
+  0x31b54a5e, 0x75f42c0b,
+  0x30fbc54d, 0x7641af3d, 0x3041c761, 0x768e0ea6, 0x2f875262, 0x76d94989,
+  0x2ecc681e, 0x77235f2d,
+  0x2e110a62, 0x776c4edb, 0x2d553afc, 0x77b417df, 0x2c98fbba, 0x77fab989,
+  0x2bdc4e6f, 0x78403329,
+  0x2b1f34eb, 0x78848414, 0x2a61b101, 0x78c7aba2, 0x29a3c485, 0x7909a92d,
+  0x28e5714b, 0x794a7c12,
+  0x2826b928, 0x798a23b1, 0x27679df4, 0x79c89f6e, 0x26a82186, 0x7a05eead,
+  0x25e845b6, 0x7a4210d8,
+  0x25280c5e, 0x7a7d055b, 0x24677758, 0x7ab6cba4, 0x23a6887f, 0x7aef6323,
+  0x22e541af, 0x7b26cb4f,
+  0x2223a4c5, 0x7b5d039e, 0x2161b3a0, 0x7b920b89, 0x209f701c, 0x7bc5e290,
+  0x1fdcdc1b, 0x7bf88830,
+  0x1f19f97b, 0x7c29fbee, 0x1e56ca1e, 0x7c5a3d50, 0x1d934fe5, 0x7c894bde,
+  0x1ccf8cb3, 0x7cb72724,
+  0x1c0b826a, 0x7ce3ceb2, 0x1b4732ef, 0x7d0f4218, 0x1a82a026, 0x7d3980ec,
+  0x19bdcbf3, 0x7d628ac6,
+  0x18f8b83c, 0x7d8a5f40, 0x183366e9, 0x7db0fdf8, 0x176dd9de, 0x7dd6668f,
+  0x16a81305, 0x7dfa98a8,
+  0x15e21445, 0x7e1d93ea, 0x151bdf86, 0x7e3f57ff, 0x145576b1, 0x7e5fe493,
+  0x138edbb1, 0x7e7f3957,
+  0x12c8106f, 0x7e9d55fc, 0x120116d5, 0x7eba3a39, 0x1139f0cf, 0x7ed5e5c6,
+  0x1072a048, 0x7ef05860,
+  0xfab272b, 0x7f0991c4, 0xee38766, 0x7f2191b4, 0xe1bc2e4, 0x7f3857f6,
+  0xd53db92, 0x7f4de451,
+  0xc8bd35e, 0x7f62368f, 0xbc3ac35, 0x7f754e80, 0xafb6805, 0x7f872bf3,
+  0xa3308bd, 0x7f97cebd,
+  0x96a9049, 0x7fa736b4, 0x8a2009a, 0x7fb563b3, 0x7d95b9e, 0x7fc25596,
+  0x710a345, 0x7fce0c3e,
+  0x647d97c, 0x7fd8878e, 0x57f0035, 0x7fe1c76b, 0x4b6195d, 0x7fe9cbc0,
+  0x3ed26e6, 0x7ff09478,
+  0x3242abf, 0x7ff62182, 0x25b26d7, 0x7ffa72d1, 0x1921d20, 0x7ffd885a,
+  0xc90f88, 0x7fff6216,
+  0x0, 0x7fffffff, 0xff36f078, 0x7fff6216, 0xfe6de2e0, 0x7ffd885a, 0xfda4d929,
+  0x7ffa72d1,
+  0xfcdbd541, 0x7ff62182, 0xfc12d91a, 0x7ff09478, 0xfb49e6a3, 0x7fe9cbc0,
+  0xfa80ffcb, 0x7fe1c76b,
+  0xf9b82684, 0x7fd8878e, 0xf8ef5cbb, 0x7fce0c3e, 0xf826a462, 0x7fc25596,
+  0xf75dff66, 0x7fb563b3,
+  0xf6956fb7, 0x7fa736b4, 0xf5ccf743, 0x7f97cebd, 0xf50497fb, 0x7f872bf3,
+  0xf43c53cb, 0x7f754e80,
+  0xf3742ca2, 0x7f62368f, 0xf2ac246e, 0x7f4de451, 0xf1e43d1c, 0x7f3857f6,
+  0xf11c789a, 0x7f2191b4,
+  0xf054d8d5, 0x7f0991c4, 0xef8d5fb8, 0x7ef05860, 0xeec60f31, 0x7ed5e5c6,
+  0xedfee92b, 0x7eba3a39,
+  0xed37ef91, 0x7e9d55fc, 0xec71244f, 0x7e7f3957, 0xebaa894f, 0x7e5fe493,
+  0xeae4207a, 0x7e3f57ff,
+  0xea1debbb, 0x7e1d93ea, 0xe957ecfb, 0x7dfa98a8, 0xe8922622, 0x7dd6668f,
+  0xe7cc9917, 0x7db0fdf8,
+  0xe70747c4, 0x7d8a5f40, 0xe642340d, 0x7d628ac6, 0xe57d5fda, 0x7d3980ec,
+  0xe4b8cd11, 0x7d0f4218,
+  0xe3f47d96, 0x7ce3ceb2, 0xe330734d, 0x7cb72724, 0xe26cb01b, 0x7c894bde,
+  0xe1a935e2, 0x7c5a3d50,
+  0xe0e60685, 0x7c29fbee, 0xe02323e5, 0x7bf88830, 0xdf608fe4, 0x7bc5e290,
+  0xde9e4c60, 0x7b920b89,
+  0xdddc5b3b, 0x7b5d039e, 0xdd1abe51, 0x7b26cb4f, 0xdc597781, 0x7aef6323,
+  0xdb9888a8, 0x7ab6cba4,
+  0xdad7f3a2, 0x7a7d055b, 0xda17ba4a, 0x7a4210d8, 0xd957de7a, 0x7a05eead,
+  0xd898620c, 0x79c89f6e,
+  0xd7d946d8, 0x798a23b1, 0xd71a8eb5, 0x794a7c12, 0xd65c3b7b, 0x7909a92d,
+  0xd59e4eff, 0x78c7aba2,
+  0xd4e0cb15, 0x78848414, 0xd423b191, 0x78403329, 0xd3670446, 0x77fab989,
+  0xd2aac504, 0x77b417df,
+  0xd1eef59e, 0x776c4edb, 0xd13397e2, 0x77235f2d, 0xd078ad9e, 0x76d94989,
+  0xcfbe389f, 0x768e0ea6,
+  0xcf043ab3, 0x7641af3d, 0xce4ab5a2, 0x75f42c0b, 0xcd91ab39, 0x75a585cf,
+  0xccd91d3d, 0x7555bd4c,
+  0xcc210d79, 0x7504d345, 0xcb697db0, 0x74b2c884, 0xcab26fa9, 0x745f9dd1,
+  0xc9fbe527, 0x740b53fb,
+  0xc945dfec, 0x73b5ebd1, 0xc89061ba, 0x735f6626, 0xc7db6c50, 0x7307c3d0,
+  0xc727016d, 0x72af05a7,
+  0xc67322ce, 0x72552c85, 0xc5bfd22e, 0x71fa3949, 0xc50d1149, 0x719e2cd2,
+  0xc45ae1d7, 0x71410805,
+  0xc3a94590, 0x70e2cbc6, 0xc2f83e2a, 0x708378ff, 0xc247cd5a, 0x7023109a,
+  0xc197f4d4, 0x6fc19385,
+  0xc0e8b648, 0x6f5f02b2, 0xc03a1368, 0x6efb5f12, 0xbf8c0de3, 0x6e96a99d,
+  0xbedea765, 0x6e30e34a,
+  0xbe31e19b, 0x6dca0d14, 0xbd85be30, 0x6d6227fa, 0xbcda3ecb, 0x6cf934fc,
+  0xbc2f6513, 0x6c8f351c,
+  0xbb8532b0, 0x6c242960, 0xbadba943, 0x6bb812d1, 0xba32ca71, 0x6b4af279,
+  0xb98a97d8, 0x6adcc964,
+  0xb8e31319, 0x6a6d98a4, 0xb83c3dd1, 0x69fd614a, 0xb796199b, 0x698c246c,
+  0xb6f0a812, 0x6919e320,
+  0xb64beacd, 0x68a69e81, 0xb5a7e362, 0x683257ab, 0xb5049368, 0x67bd0fbd,
+  0xb461fc70, 0x6746c7d8,
+  0xb3c0200c, 0x66cf8120, 0xb31effcc, 0x66573cbb, 0xb27e9d3c, 0x65ddfbd3,
+  0xb1def9e9, 0x6563bf92,
+  0xb140175b, 0x64e88926, 0xb0a1f71d, 0x646c59bf, 0xb0049ab3, 0x63ef3290,
+  0xaf6803a2, 0x637114cc,
+  0xaecc336c, 0x62f201ac, 0xae312b92, 0x6271fa69, 0xad96ed92, 0x61f1003f,
+  0xacfd7ae8, 0x616f146c,
+  0xac64d510, 0x60ec3830, 0xabccfd83, 0x60686ccf, 0xab35f5b5, 0x5fe3b38d,
+  0xaa9fbf1e, 0x5f5e0db3,
+  0xaa0a5b2e, 0x5ed77c8a, 0xa975cb57, 0x5e50015d, 0xa8e21106, 0x5dc79d7c,
+  0xa84f2daa, 0x5d3e5237,
+  0xa7bd22ac, 0x5cb420e0, 0xa72bf174, 0x5c290acc, 0xa69b9b68, 0x5b9d1154,
+  0xa60c21ee, 0x5b1035cf,
+  0xa57d8666, 0x5a82799a, 0xa4efca31, 0x59f3de12, 0xa462eeac, 0x59646498,
+  0xa3d6f534, 0x58d40e8c,
+  0xa34bdf20, 0x5842dd54, 0xa2c1adc9, 0x57b0d256, 0xa2386284, 0x571deefa,
+  0xa1affea3, 0x568a34a9,
+  0xa1288376, 0x55f5a4d2, 0xa0a1f24d, 0x556040e2, 0xa01c4c73, 0x54ca0a4b,
+  0x9f979331, 0x5433027d,
+  0x9f13c7d0, 0x539b2af0, 0x9e90eb94, 0x53028518, 0x9e0effc1, 0x5269126e,
+  0x9d8e0597, 0x51ced46e,
+  0x9d0dfe54, 0x5133cc94, 0x9c8eeb34, 0x5097fc5e, 0x9c10cd70, 0x4ffb654d,
+  0x9b93a641, 0x4f5e08e3,
+  0x9b1776da, 0x4ebfe8a5, 0x9a9c406e, 0x4e210617, 0x9a22042d, 0x4d8162c4,
+  0x99a8c345, 0x4ce10034,
+  0x99307ee0, 0x4c3fdff4, 0x98b93828, 0x4b9e0390, 0x9842f043, 0x4afb6c98,
+  0x97cda855, 0x4a581c9e,
+  0x9759617f, 0x49b41533, 0x96e61ce0, 0x490f57ee, 0x9673db94, 0x4869e665,
+  0x96029eb6, 0x47c3c22f,
+  0x9592675c, 0x471cece7, 0x9523369c, 0x46756828, 0x94b50d87, 0x45cd358f,
+  0x9447ed2f, 0x452456bd,
+  0x93dbd6a0, 0x447acd50, 0x9370cae4, 0x43d09aed, 0x9306cb04, 0x4325c135,
+  0x929dd806, 0x427a41d0,
+  0x9235f2ec, 0x41ce1e65, 0x91cf1cb6, 0x4121589b, 0x91695663, 0x4073f21d,
+  0x9104a0ee, 0x3fc5ec98,
+  0x90a0fd4e, 0x3f1749b8, 0x903e6c7b, 0x3e680b2c, 0x8fdcef66, 0x3db832a6,
+  0x8f7c8701, 0x3d07c1d6,
+  0x8f1d343a, 0x3c56ba70, 0x8ebef7fb, 0x3ba51e29, 0x8e61d32e, 0x3af2eeb7,
+  0x8e05c6b7, 0x3a402dd2,
+  0x8daad37b, 0x398cdd32, 0x8d50fa59, 0x38d8fe93, 0x8cf83c30, 0x382493b0,
+  0x8ca099da, 0x376f9e46,
+  0x8c4a142f, 0x36ba2014, 0x8bf4ac05, 0x36041ad9, 0x8ba0622f, 0x354d9057,
+  0x8b4d377c, 0x34968250,
+  0x8afb2cbb, 0x33def287, 0x8aaa42b4, 0x3326e2c3, 0x8a5a7a31, 0x326e54c7,
+  0x8a0bd3f5, 0x31b54a5e,
+  0x89be50c3, 0x30fbc54d, 0x8971f15a, 0x3041c761, 0x8926b677, 0x2f875262,
+  0x88dca0d3, 0x2ecc681e,
+  0x8893b125, 0x2e110a62, 0x884be821, 0x2d553afc, 0x88054677, 0x2c98fbba,
+  0x87bfccd7, 0x2bdc4e6f,
+  0x877b7bec, 0x2b1f34eb, 0x8738545e, 0x2a61b101, 0x86f656d3, 0x29a3c485,
+  0x86b583ee, 0x28e5714b,
+  0x8675dc4f, 0x2826b928, 0x86376092, 0x27679df4, 0x85fa1153, 0x26a82186,
+  0x85bdef28, 0x25e845b6,
+  0x8582faa5, 0x25280c5e, 0x8549345c, 0x24677758, 0x85109cdd, 0x23a6887f,
+  0x84d934b1, 0x22e541af,
+  0x84a2fc62, 0x2223a4c5, 0x846df477, 0x2161b3a0, 0x843a1d70, 0x209f701c,
+  0x840777d0, 0x1fdcdc1b,
+  0x83d60412, 0x1f19f97b, 0x83a5c2b0, 0x1e56ca1e, 0x8376b422, 0x1d934fe5,
+  0x8348d8dc, 0x1ccf8cb3,
+  0x831c314e, 0x1c0b826a, 0x82f0bde8, 0x1b4732ef, 0x82c67f14, 0x1a82a026,
+  0x829d753a, 0x19bdcbf3,
+  0x8275a0c0, 0x18f8b83c, 0x824f0208, 0x183366e9, 0x82299971, 0x176dd9de,
+  0x82056758, 0x16a81305,
+  0x81e26c16, 0x15e21445, 0x81c0a801, 0x151bdf86, 0x81a01b6d, 0x145576b1,
+  0x8180c6a9, 0x138edbb1,
+  0x8162aa04, 0x12c8106f, 0x8145c5c7, 0x120116d5, 0x812a1a3a, 0x1139f0cf,
+  0x810fa7a0, 0x1072a048,
+  0x80f66e3c, 0xfab272b, 0x80de6e4c, 0xee38766, 0x80c7a80a, 0xe1bc2e4,
+  0x80b21baf, 0xd53db92,
+  0x809dc971, 0xc8bd35e, 0x808ab180, 0xbc3ac35, 0x8078d40d, 0xafb6805,
+  0x80683143, 0xa3308bd,
+  0x8058c94c, 0x96a9049, 0x804a9c4d, 0x8a2009a, 0x803daa6a, 0x7d95b9e,
+  0x8031f3c2, 0x710a345,
+  0x80277872, 0x647d97c, 0x801e3895, 0x57f0035, 0x80163440, 0x4b6195d,
+  0x800f6b88, 0x3ed26e6,
+  0x8009de7e, 0x3242abf, 0x80058d2f, 0x25b26d7, 0x800277a6, 0x1921d20,
+  0x80009dea, 0xc90f88,
+  0x80000000, 0x0, 0x80009dea, 0xff36f078, 0x800277a6, 0xfe6de2e0, 0x80058d2f,
+  0xfda4d929,
+  0x8009de7e, 0xfcdbd541, 0x800f6b88, 0xfc12d91a, 0x80163440, 0xfb49e6a3,
+  0x801e3895, 0xfa80ffcb,
+  0x80277872, 0xf9b82684, 0x8031f3c2, 0xf8ef5cbb, 0x803daa6a, 0xf826a462,
+  0x804a9c4d, 0xf75dff66,
+  0x8058c94c, 0xf6956fb7, 0x80683143, 0xf5ccf743, 0x8078d40d, 0xf50497fb,
+  0x808ab180, 0xf43c53cb,
+  0x809dc971, 0xf3742ca2, 0x80b21baf, 0xf2ac246e, 0x80c7a80a, 0xf1e43d1c,
+  0x80de6e4c, 0xf11c789a,
+  0x80f66e3c, 0xf054d8d5, 0x810fa7a0, 0xef8d5fb8, 0x812a1a3a, 0xeec60f31,
+  0x8145c5c7, 0xedfee92b,
+  0x8162aa04, 0xed37ef91, 0x8180c6a9, 0xec71244f, 0x81a01b6d, 0xebaa894f,
+  0x81c0a801, 0xeae4207a,
+  0x81e26c16, 0xea1debbb, 0x82056758, 0xe957ecfb, 0x82299971, 0xe8922622,
+  0x824f0208, 0xe7cc9917,
+  0x8275a0c0, 0xe70747c4, 0x829d753a, 0xe642340d, 0x82c67f14, 0xe57d5fda,
+  0x82f0bde8, 0xe4b8cd11,
+  0x831c314e, 0xe3f47d96, 0x8348d8dc, 0xe330734d, 0x8376b422, 0xe26cb01b,
+  0x83a5c2b0, 0xe1a935e2,
+  0x83d60412, 0xe0e60685, 0x840777d0, 0xe02323e5, 0x843a1d70, 0xdf608fe4,
+  0x846df477, 0xde9e4c60,
+  0x84a2fc62, 0xdddc5b3b, 0x84d934b1, 0xdd1abe51, 0x85109cdd, 0xdc597781,
+  0x8549345c, 0xdb9888a8,
+  0x8582faa5, 0xdad7f3a2, 0x85bdef28, 0xda17ba4a, 0x85fa1153, 0xd957de7a,
+  0x86376092, 0xd898620c,
+  0x8675dc4f, 0xd7d946d8, 0x86b583ee, 0xd71a8eb5, 0x86f656d3, 0xd65c3b7b,
+  0x8738545e, 0xd59e4eff,
+  0x877b7bec, 0xd4e0cb15, 0x87bfccd7, 0xd423b191, 0x88054677, 0xd3670446,
+  0x884be821, 0xd2aac504,
+  0x8893b125, 0xd1eef59e, 0x88dca0d3, 0xd13397e2, 0x8926b677, 0xd078ad9e,
+  0x8971f15a, 0xcfbe389f,
+  0x89be50c3, 0xcf043ab3, 0x8a0bd3f5, 0xce4ab5a2, 0x8a5a7a31, 0xcd91ab39,
+  0x8aaa42b4, 0xccd91d3d,
+  0x8afb2cbb, 0xcc210d79, 0x8b4d377c, 0xcb697db0, 0x8ba0622f, 0xcab26fa9,
+  0x8bf4ac05, 0xc9fbe527,
+  0x8c4a142f, 0xc945dfec, 0x8ca099da, 0xc89061ba, 0x8cf83c30, 0xc7db6c50,
+  0x8d50fa59, 0xc727016d,
+  0x8daad37b, 0xc67322ce, 0x8e05c6b7, 0xc5bfd22e, 0x8e61d32e, 0xc50d1149,
+  0x8ebef7fb, 0xc45ae1d7,
+  0x8f1d343a, 0xc3a94590, 0x8f7c8701, 0xc2f83e2a, 0x8fdcef66, 0xc247cd5a,
+  0x903e6c7b, 0xc197f4d4,
+  0x90a0fd4e, 0xc0e8b648, 0x9104a0ee, 0xc03a1368, 0x91695663, 0xbf8c0de3,
+  0x91cf1cb6, 0xbedea765,
+  0x9235f2ec, 0xbe31e19b, 0x929dd806, 0xbd85be30, 0x9306cb04, 0xbcda3ecb,
+  0x9370cae4, 0xbc2f6513,
+  0x93dbd6a0, 0xbb8532b0, 0x9447ed2f, 0xbadba943, 0x94b50d87, 0xba32ca71,
+  0x9523369c, 0xb98a97d8,
+  0x9592675c, 0xb8e31319, 0x96029eb6, 0xb83c3dd1, 0x9673db94, 0xb796199b,
+  0x96e61ce0, 0xb6f0a812,
+  0x9759617f, 0xb64beacd, 0x97cda855, 0xb5a7e362, 0x9842f043, 0xb5049368,
+  0x98b93828, 0xb461fc70,
+  0x99307ee0, 0xb3c0200c, 0x99a8c345, 0xb31effcc, 0x9a22042d, 0xb27e9d3c,
+  0x9a9c406e, 0xb1def9e9,
+  0x9b1776da, 0xb140175b, 0x9b93a641, 0xb0a1f71d, 0x9c10cd70, 0xb0049ab3,
+  0x9c8eeb34, 0xaf6803a2,
+  0x9d0dfe54, 0xaecc336c, 0x9d8e0597, 0xae312b92, 0x9e0effc1, 0xad96ed92,
+  0x9e90eb94, 0xacfd7ae8,
+  0x9f13c7d0, 0xac64d510, 0x9f979331, 0xabccfd83, 0xa01c4c73, 0xab35f5b5,
+  0xa0a1f24d, 0xaa9fbf1e,
+  0xa1288376, 0xaa0a5b2e, 0xa1affea3, 0xa975cb57, 0xa2386284, 0xa8e21106,
+  0xa2c1adc9, 0xa84f2daa,
+  0xa34bdf20, 0xa7bd22ac, 0xa3d6f534, 0xa72bf174, 0xa462eeac, 0xa69b9b68,
+  0xa4efca31, 0xa60c21ee,
+  0xa57d8666, 0xa57d8666, 0xa60c21ee, 0xa4efca31, 0xa69b9b68, 0xa462eeac,
+  0xa72bf174, 0xa3d6f534,
+  0xa7bd22ac, 0xa34bdf20, 0xa84f2daa, 0xa2c1adc9, 0xa8e21106, 0xa2386284,
+  0xa975cb57, 0xa1affea3,
+  0xaa0a5b2e, 0xa1288376, 0xaa9fbf1e, 0xa0a1f24d, 0xab35f5b5, 0xa01c4c73,
+  0xabccfd83, 0x9f979331,
+  0xac64d510, 0x9f13c7d0, 0xacfd7ae8, 0x9e90eb94, 0xad96ed92, 0x9e0effc1,
+  0xae312b92, 0x9d8e0597,
+  0xaecc336c, 0x9d0dfe54, 0xaf6803a2, 0x9c8eeb34, 0xb0049ab3, 0x9c10cd70,
+  0xb0a1f71d, 0x9b93a641,
+  0xb140175b, 0x9b1776da, 0xb1def9e9, 0x9a9c406e, 0xb27e9d3c, 0x9a22042d,
+  0xb31effcc, 0x99a8c345,
+  0xb3c0200c, 0x99307ee0, 0xb461fc70, 0x98b93828, 0xb5049368, 0x9842f043,
+  0xb5a7e362, 0x97cda855,
+  0xb64beacd, 0x9759617f, 0xb6f0a812, 0x96e61ce0, 0xb796199b, 0x9673db94,
+  0xb83c3dd1, 0x96029eb6,
+  0xb8e31319, 0x9592675c, 0xb98a97d8, 0x9523369c, 0xba32ca71, 0x94b50d87,
+  0xbadba943, 0x9447ed2f,
+  0xbb8532b0, 0x93dbd6a0, 0xbc2f6513, 0x9370cae4, 0xbcda3ecb, 0x9306cb04,
+  0xbd85be30, 0x929dd806,
+  0xbe31e19b, 0x9235f2ec, 0xbedea765, 0x91cf1cb6, 0xbf8c0de3, 0x91695663,
+  0xc03a1368, 0x9104a0ee,
+  0xc0e8b648, 0x90a0fd4e, 0xc197f4d4, 0x903e6c7b, 0xc247cd5a, 0x8fdcef66,
+  0xc2f83e2a, 0x8f7c8701,
+  0xc3a94590, 0x8f1d343a, 0xc45ae1d7, 0x8ebef7fb, 0xc50d1149, 0x8e61d32e,
+  0xc5bfd22e, 0x8e05c6b7,
+  0xc67322ce, 0x8daad37b, 0xc727016d, 0x8d50fa59, 0xc7db6c50, 0x8cf83c30,
+  0xc89061ba, 0x8ca099da,
+  0xc945dfec, 0x8c4a142f, 0xc9fbe527, 0x8bf4ac05, 0xcab26fa9, 0x8ba0622f,
+  0xcb697db0, 0x8b4d377c,
+  0xcc210d79, 0x8afb2cbb, 0xccd91d3d, 0x8aaa42b4, 0xcd91ab39, 0x8a5a7a31,
+  0xce4ab5a2, 0x8a0bd3f5,
+  0xcf043ab3, 0x89be50c3, 0xcfbe389f, 0x8971f15a, 0xd078ad9e, 0x8926b677,
+  0xd13397e2, 0x88dca0d3,
+  0xd1eef59e, 0x8893b125, 0xd2aac504, 0x884be821, 0xd3670446, 0x88054677,
+  0xd423b191, 0x87bfccd7,
+  0xd4e0cb15, 0x877b7bec, 0xd59e4eff, 0x8738545e, 0xd65c3b7b, 0x86f656d3,
+  0xd71a8eb5, 0x86b583ee,
+  0xd7d946d8, 0x8675dc4f, 0xd898620c, 0x86376092, 0xd957de7a, 0x85fa1153,
+  0xda17ba4a, 0x85bdef28,
+  0xdad7f3a2, 0x8582faa5, 0xdb9888a8, 0x8549345c, 0xdc597781, 0x85109cdd,
+  0xdd1abe51, 0x84d934b1,
+  0xdddc5b3b, 0x84a2fc62, 0xde9e4c60, 0x846df477, 0xdf608fe4, 0x843a1d70,
+  0xe02323e5, 0x840777d0,
+  0xe0e60685, 0x83d60412, 0xe1a935e2, 0x83a5c2b0, 0xe26cb01b, 0x8376b422,
+  0xe330734d, 0x8348d8dc,
+  0xe3f47d96, 0x831c314e, 0xe4b8cd11, 0x82f0bde8, 0xe57d5fda, 0x82c67f14,
+  0xe642340d, 0x829d753a,
+  0xe70747c4, 0x8275a0c0, 0xe7cc9917, 0x824f0208, 0xe8922622, 0x82299971,
+  0xe957ecfb, 0x82056758,
+  0xea1debbb, 0x81e26c16, 0xeae4207a, 0x81c0a801, 0xebaa894f, 0x81a01b6d,
+  0xec71244f, 0x8180c6a9,
+  0xed37ef91, 0x8162aa04, 0xedfee92b, 0x8145c5c7, 0xeec60f31, 0x812a1a3a,
+  0xef8d5fb8, 0x810fa7a0,
+  0xf054d8d5, 0x80f66e3c, 0xf11c789a, 0x80de6e4c, 0xf1e43d1c, 0x80c7a80a,
+  0xf2ac246e, 0x80b21baf,
+  0xf3742ca2, 0x809dc971, 0xf43c53cb, 0x808ab180, 0xf50497fb, 0x8078d40d,
+  0xf5ccf743, 0x80683143,
+  0xf6956fb7, 0x8058c94c, 0xf75dff66, 0x804a9c4d, 0xf826a462, 0x803daa6a,
+  0xf8ef5cbb, 0x8031f3c2,
+  0xf9b82684, 0x80277872, 0xfa80ffcb, 0x801e3895, 0xfb49e6a3, 0x80163440,
+  0xfc12d91a, 0x800f6b88,
+  0xfcdbd541, 0x8009de7e, 0xfda4d929, 0x80058d2f, 0xfe6de2e0, 0x800277a6,
+  0xff36f078, 0x80009dea,
+  0x0, 0x80000000, 0xc90f88, 0x80009dea, 0x1921d20, 0x800277a6, 0x25b26d7,
+  0x80058d2f,
+  0x3242abf, 0x8009de7e, 0x3ed26e6, 0x800f6b88, 0x4b6195d, 0x80163440,
+  0x57f0035, 0x801e3895,
+  0x647d97c, 0x80277872, 0x710a345, 0x8031f3c2, 0x7d95b9e, 0x803daa6a,
+  0x8a2009a, 0x804a9c4d,
+  0x96a9049, 0x8058c94c, 0xa3308bd, 0x80683143, 0xafb6805, 0x8078d40d,
+  0xbc3ac35, 0x808ab180,
+  0xc8bd35e, 0x809dc971, 0xd53db92, 0x80b21baf, 0xe1bc2e4, 0x80c7a80a,
+  0xee38766, 0x80de6e4c,
+  0xfab272b, 0x80f66e3c, 0x1072a048, 0x810fa7a0, 0x1139f0cf, 0x812a1a3a,
+  0x120116d5, 0x8145c5c7,
+  0x12c8106f, 0x8162aa04, 0x138edbb1, 0x8180c6a9, 0x145576b1, 0x81a01b6d,
+  0x151bdf86, 0x81c0a801,
+  0x15e21445, 0x81e26c16, 0x16a81305, 0x82056758, 0x176dd9de, 0x82299971,
+  0x183366e9, 0x824f0208,
+  0x18f8b83c, 0x8275a0c0, 0x19bdcbf3, 0x829d753a, 0x1a82a026, 0x82c67f14,
+  0x1b4732ef, 0x82f0bde8,
+  0x1c0b826a, 0x831c314e, 0x1ccf8cb3, 0x8348d8dc, 0x1d934fe5, 0x8376b422,
+  0x1e56ca1e, 0x83a5c2b0,
+  0x1f19f97b, 0x83d60412, 0x1fdcdc1b, 0x840777d0, 0x209f701c, 0x843a1d70,
+  0x2161b3a0, 0x846df477,
+  0x2223a4c5, 0x84a2fc62, 0x22e541af, 0x84d934b1, 0x23a6887f, 0x85109cdd,
+  0x24677758, 0x8549345c,
+  0x25280c5e, 0x8582faa5, 0x25e845b6, 0x85bdef28, 0x26a82186, 0x85fa1153,
+  0x27679df4, 0x86376092,
+  0x2826b928, 0x8675dc4f, 0x28e5714b, 0x86b583ee, 0x29a3c485, 0x86f656d3,
+  0x2a61b101, 0x8738545e,
+  0x2b1f34eb, 0x877b7bec, 0x2bdc4e6f, 0x87bfccd7, 0x2c98fbba, 0x88054677,
+  0x2d553afc, 0x884be821,
+  0x2e110a62, 0x8893b125, 0x2ecc681e, 0x88dca0d3, 0x2f875262, 0x8926b677,
+  0x3041c761, 0x8971f15a,
+  0x30fbc54d, 0x89be50c3, 0x31b54a5e, 0x8a0bd3f5, 0x326e54c7, 0x8a5a7a31,
+  0x3326e2c3, 0x8aaa42b4,
+  0x33def287, 0x8afb2cbb, 0x34968250, 0x8b4d377c, 0x354d9057, 0x8ba0622f,
+  0x36041ad9, 0x8bf4ac05,
+  0x36ba2014, 0x8c4a142f, 0x376f9e46, 0x8ca099da, 0x382493b0, 0x8cf83c30,
+  0x38d8fe93, 0x8d50fa59,
+  0x398cdd32, 0x8daad37b, 0x3a402dd2, 0x8e05c6b7, 0x3af2eeb7, 0x8e61d32e,
+  0x3ba51e29, 0x8ebef7fb,
+  0x3c56ba70, 0x8f1d343a, 0x3d07c1d6, 0x8f7c8701, 0x3db832a6, 0x8fdcef66,
+  0x3e680b2c, 0x903e6c7b,
+  0x3f1749b8, 0x90a0fd4e, 0x3fc5ec98, 0x9104a0ee, 0x4073f21d, 0x91695663,
+  0x4121589b, 0x91cf1cb6,
+  0x41ce1e65, 0x9235f2ec, 0x427a41d0, 0x929dd806, 0x4325c135, 0x9306cb04,
+  0x43d09aed, 0x9370cae4,
+  0x447acd50, 0x93dbd6a0, 0x452456bd, 0x9447ed2f, 0x45cd358f, 0x94b50d87,
+  0x46756828, 0x9523369c,
+  0x471cece7, 0x9592675c, 0x47c3c22f, 0x96029eb6, 0x4869e665, 0x9673db94,
+  0x490f57ee, 0x96e61ce0,
+  0x49b41533, 0x9759617f, 0x4a581c9e, 0x97cda855, 0x4afb6c98, 0x9842f043,
+  0x4b9e0390, 0x98b93828,
+  0x4c3fdff4, 0x99307ee0, 0x4ce10034, 0x99a8c345, 0x4d8162c4, 0x9a22042d,
+  0x4e210617, 0x9a9c406e,
+  0x4ebfe8a5, 0x9b1776da, 0x4f5e08e3, 0x9b93a641, 0x4ffb654d, 0x9c10cd70,
+  0x5097fc5e, 0x9c8eeb34,
+  0x5133cc94, 0x9d0dfe54, 0x51ced46e, 0x9d8e0597, 0x5269126e, 0x9e0effc1,
+  0x53028518, 0x9e90eb94,
+  0x539b2af0, 0x9f13c7d0, 0x5433027d, 0x9f979331, 0x54ca0a4b, 0xa01c4c73,
+  0x556040e2, 0xa0a1f24d,
+  0x55f5a4d2, 0xa1288376, 0x568a34a9, 0xa1affea3, 0x571deefa, 0xa2386284,
+  0x57b0d256, 0xa2c1adc9,
+  0x5842dd54, 0xa34bdf20, 0x58d40e8c, 0xa3d6f534, 0x59646498, 0xa462eeac,
+  0x59f3de12, 0xa4efca31,
+  0x5a82799a, 0xa57d8666, 0x5b1035cf, 0xa60c21ee, 0x5b9d1154, 0xa69b9b68,
+  0x5c290acc, 0xa72bf174,
+  0x5cb420e0, 0xa7bd22ac, 0x5d3e5237, 0xa84f2daa, 0x5dc79d7c, 0xa8e21106,
+  0x5e50015d, 0xa975cb57,
+  0x5ed77c8a, 0xaa0a5b2e, 0x5f5e0db3, 0xaa9fbf1e, 0x5fe3b38d, 0xab35f5b5,
+  0x60686ccf, 0xabccfd83,
+  0x60ec3830, 0xac64d510, 0x616f146c, 0xacfd7ae8, 0x61f1003f, 0xad96ed92,
+  0x6271fa69, 0xae312b92,
+  0x62f201ac, 0xaecc336c, 0x637114cc, 0xaf6803a2, 0x63ef3290, 0xb0049ab3,
+  0x646c59bf, 0xb0a1f71d,
+  0x64e88926, 0xb140175b, 0x6563bf92, 0xb1def9e9, 0x65ddfbd3, 0xb27e9d3c,
+  0x66573cbb, 0xb31effcc,
+  0x66cf8120, 0xb3c0200c, 0x6746c7d8, 0xb461fc70, 0x67bd0fbd, 0xb5049368,
+  0x683257ab, 0xb5a7e362,
+  0x68a69e81, 0xb64beacd, 0x6919e320, 0xb6f0a812, 0x698c246c, 0xb796199b,
+  0x69fd614a, 0xb83c3dd1,
+  0x6a6d98a4, 0xb8e31319, 0x6adcc964, 0xb98a97d8, 0x6b4af279, 0xba32ca71,
+  0x6bb812d1, 0xbadba943,
+  0x6c242960, 0xbb8532b0, 0x6c8f351c, 0xbc2f6513, 0x6cf934fc, 0xbcda3ecb,
+  0x6d6227fa, 0xbd85be30,
+  0x6dca0d14, 0xbe31e19b, 0x6e30e34a, 0xbedea765, 0x6e96a99d, 0xbf8c0de3,
+  0x6efb5f12, 0xc03a1368,
+  0x6f5f02b2, 0xc0e8b648, 0x6fc19385, 0xc197f4d4, 0x7023109a, 0xc247cd5a,
+  0x708378ff, 0xc2f83e2a,
+  0x70e2cbc6, 0xc3a94590, 0x71410805, 0xc45ae1d7, 0x719e2cd2, 0xc50d1149,
+  0x71fa3949, 0xc5bfd22e,
+  0x72552c85, 0xc67322ce, 0x72af05a7, 0xc727016d, 0x7307c3d0, 0xc7db6c50,
+  0x735f6626, 0xc89061ba,
+  0x73b5ebd1, 0xc945dfec, 0x740b53fb, 0xc9fbe527, 0x745f9dd1, 0xcab26fa9,
+  0x74b2c884, 0xcb697db0,
+  0x7504d345, 0xcc210d79, 0x7555bd4c, 0xccd91d3d, 0x75a585cf, 0xcd91ab39,
+  0x75f42c0b, 0xce4ab5a2,
+  0x7641af3d, 0xcf043ab3, 0x768e0ea6, 0xcfbe389f, 0x76d94989, 0xd078ad9e,
+  0x77235f2d, 0xd13397e2,
+  0x776c4edb, 0xd1eef59e, 0x77b417df, 0xd2aac504, 0x77fab989, 0xd3670446,
+  0x78403329, 0xd423b191,
+  0x78848414, 0xd4e0cb15, 0x78c7aba2, 0xd59e4eff, 0x7909a92d, 0xd65c3b7b,
+  0x794a7c12, 0xd71a8eb5,
+  0x798a23b1, 0xd7d946d8, 0x79c89f6e, 0xd898620c, 0x7a05eead, 0xd957de7a,
+  0x7a4210d8, 0xda17ba4a,
+  0x7a7d055b, 0xdad7f3a2, 0x7ab6cba4, 0xdb9888a8, 0x7aef6323, 0xdc597781,
+  0x7b26cb4f, 0xdd1abe51,
+  0x7b5d039e, 0xdddc5b3b, 0x7b920b89, 0xde9e4c60, 0x7bc5e290, 0xdf608fe4,
+  0x7bf88830, 0xe02323e5,
+  0x7c29fbee, 0xe0e60685, 0x7c5a3d50, 0xe1a935e2, 0x7c894bde, 0xe26cb01b,
+  0x7cb72724, 0xe330734d,
+  0x7ce3ceb2, 0xe3f47d96, 0x7d0f4218, 0xe4b8cd11, 0x7d3980ec, 0xe57d5fda,
+  0x7d628ac6, 0xe642340d,
+  0x7d8a5f40, 0xe70747c4, 0x7db0fdf8, 0xe7cc9917, 0x7dd6668f, 0xe8922622,
+  0x7dfa98a8, 0xe957ecfb,
+  0x7e1d93ea, 0xea1debbb, 0x7e3f57ff, 0xeae4207a, 0x7e5fe493, 0xebaa894f,
+  0x7e7f3957, 0xec71244f,
+  0x7e9d55fc, 0xed37ef91, 0x7eba3a39, 0xedfee92b, 0x7ed5e5c6, 0xeec60f31,
+  0x7ef05860, 0xef8d5fb8,
+  0x7f0991c4, 0xf054d8d5, 0x7f2191b4, 0xf11c789a, 0x7f3857f6, 0xf1e43d1c,
+  0x7f4de451, 0xf2ac246e,
+  0x7f62368f, 0xf3742ca2, 0x7f754e80, 0xf43c53cb, 0x7f872bf3, 0xf50497fb,
+  0x7f97cebd, 0xf5ccf743,
+  0x7fa736b4, 0xf6956fb7, 0x7fb563b3, 0xf75dff66, 0x7fc25596, 0xf826a462,
+  0x7fce0c3e, 0xf8ef5cbb,
+  0x7fd8878e, 0xf9b82684, 0x7fe1c76b, 0xfa80ffcb, 0x7fe9cbc0, 0xfb49e6a3,
+  0x7ff09478, 0xfc12d91a,
+  0x7ff62182, 0xfcdbd541, 0x7ffa72d1, 0xfda4d929, 0x7ffd885a, 0xfe6de2e0,
+  0x7fff6216, 0xff36f078
+};
+
+/**   
+*   
+* @brief  Initialization function for the Q31 CFFT/CIFFT.  
+* @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.  
+* @param[in]     fftLen         length of the FFT.  
+* @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.  
+*   
+* \par Description:  
+* \par   
+* The parameter ifftFlag controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlag for calculation of CIFFT otherwise  CFFT is calculated  
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.   
+* \par   
+* The parameter fftLen	Specifies length of CFFT/CIFFT process. Supported FFT Lengths are 16, 64, 256, 1024.   
+* \par   
+* This Function also initializes Twiddle factor table pointer and Bit reversal table pointer.   
+*/
+
+arm_status arm_cfft_radix4_init_q31(
+  arm_cfft_radix4_instance_q31 * S,
+  uint16_t fftLen,
+  uint8_t ifftFlag,
+  uint8_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+  /*  Initialise the FFT length */
+  S->fftLen = fftLen;
+  /*  Initialise the Twiddle coefficient pointer */
+  S->pTwiddle = (q31_t *) twiddleCoefQ31;
+  /*  Initialise the Flag for selection of CFFT or CIFFT */
+  S->ifftFlag = ifftFlag;
+  /*  Initialise the Flag for calculation Bit reversal or not */
+  S->bitReverseFlag = bitReverseFlag;
+
+  /*  Initializations of Instance structure depending on the FFT length */
+  switch (S->fftLen)
+  {
+    /*  Initializations of structure parameters for 1024 point FFT */
+  case 1024u:
+    /*  Initialise the twiddle coef modifier value */
+    S->twidCoefModifier = 1u;
+    /*  Initialise the bit reversal table modifier */
+    S->bitRevFactor = 1u;
+    /*  Initialise the bit reversal table pointer */
+    S->pBitRevTable = armBitRevTable;
+    break;
+
+  case 256u:
+    /*  Initializations of structure parameters for 256 point FFT */
+    S->twidCoefModifier = 4u;
+    S->bitRevFactor = 4u;
+    S->pBitRevTable = (uint16_t *) & armBitRevTable[3];
+    break;
+
+  case 64u:
+    /*  Initializations of structure parameters for 64 point FFT */
+    S->twidCoefModifier = 16u;
+    S->bitRevFactor = 16u;
+    S->pBitRevTable = &armBitRevTable[15];
+    break;
+
+  case 16u:
+    /*  Initializations of structure parameters for 16 point FFT */
+    S->twidCoefModifier = 64u;
+    S->bitRevFactor = 64u;
+    S->pBitRevTable = &armBitRevTable[63];
+    break;
+
+  default:
+    /*  Reporting argument error if fftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  return (status);
+}
+
+/**   
+ * @} end of CFFT_CIFFT group   
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c
new file mode 100644
index 0000000000..0f45b52558
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c
@@ -0,0 +1,1952 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix4_q15.c   
+*   
+* Description:	This file has function definition of Radix-4 FFT & IFFT function and   
+*				In-place bit reversal using bit reversal table   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup CFFT_CIFFT   
+ * @{   
+ */
+
+
+/**   
+ * @details   
+ * @brief Processing function for the Q15 CFFT/CIFFT.  
+ * @param[in]      *S    points to an instance of the Q15 CFFT/CIFFT structure.  
+ * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.  
+ * @return none.  
+ *    
+ * \par Input and output formats:   
+ * \par   
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.  
+ * Hence the output format is different for different FFT sizes.   
+ * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:  
+ * \par  
+ * \image html CFFTQ15.gif "Input and Output Formats for Q15 CFFT"   
+ * \image html CIFFTQ15.gif "Input and Output Formats for Q15 CIFFT"   
+ */
+
+void arm_cfft_radix4_q15(
+  const arm_cfft_radix4_instance_q15 * S,
+  q15_t * pSrc)
+{
+  if(S->ifftFlag == 1u)
+  {
+    /*  Complex IFFT radix-4  */
+    arm_radix4_butterfly_inverse_q15(pSrc, S->fftLen, S->pTwiddle,
+                                     S->twidCoefModifier);
+  }
+  else
+  {
+    /*  Complex FFT radix-4  */
+    arm_radix4_butterfly_q15(pSrc, S->fftLen, S->pTwiddle,
+                             S->twidCoefModifier);
+  }
+
+  if(S->bitReverseFlag == 1u)
+  {
+    /*  Bit Reversal */
+    arm_bitreversal_q15(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+  }
+
+}
+
+/**   
+ * @} end of CFFT_CIFFT group   
+ */
+
+/*   
+* Radix-4 FFT algorithm used is :   
+*   
+* Input real and imaginary data:   
+* x(n) = xa + j * ya   
+* x(n+N/4 ) = xb + j * yb   
+* x(n+N/2 ) = xc + j * yc   
+* x(n+3N 4) = xd + j * yd   
+*   
+*   
+* Output real and imaginary data:   
+* x(4r) = xa'+ j * ya'   
+* x(4r+1) = xb'+ j * yb'   
+* x(4r+2) = xc'+ j * yc'   
+* x(4r+3) = xd'+ j * yd'   
+*   
+*   
+* Twiddle factors for radix-4 FFT:   
+* Wn = co1 + j * (- si1)   
+* W2n = co2 + j * (- si2)   
+* W3n = co3 + j * (- si3)   
+   
+* The real and imaginary output values for the radix-4 butterfly are   
+* xa' = xa + xb + xc + xd   
+* ya' = ya + yb + yc + yd   
+* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)   
+* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)   
+* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)   
+* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)   
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)   
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)   
+*   
+*/
+
+/**   
+ * @brief  Core function for the Q15 CFFT butterfly process.  
+ * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.  
+ * @param[in]      fftLen           length of the FFT.  
+ * @param[in]      *pCoef16         points to twiddle coefficient buffer.  
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.  
+ */
+
+void arm_radix4_butterfly_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  q15_t * pCoef16,
+  uint32_t twidCoefModifier)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t R, S, T, U;
+  q31_t C1, C2, C3, out1, out2;
+  q31_t *pSrc, *pCoeff;
+  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+  q15_t in;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  pointer initializations for SIMD calculations */
+  pSrc = (q31_t *) pSrc16;
+  pCoeff = (q31_t *) pCoef16;
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  /* Index for twiddle coefficient */
+  ic = 0u;
+
+  /* Index for input read and output write */
+  i0 = 0u;
+  j = n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T = pSrc[i0];
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* Read yc (real), xc(imag) input */
+    S = pSrc[i2];
+    in = ((int16_t) (S & 0xFFFF)) >> 2;
+    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* R = packed((ya + yc), (xa + xc) ) */
+    R = __QADD16(T, S);
+    /* S = packed((ya - yc), (xa - xc) ) */
+    S = __QSUB16(T, S);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T = pSrc[i1];
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* Read yd (real), xd(imag) input */
+    U = pSrc[i3];
+    in = ((int16_t) (U & 0xFFFF)) >> 2;
+    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* T = packed((yb + yd), (xb + xd) ) */
+    T = __QADD16(T, U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc[i0] = __SHADD16(R, T);
+
+    /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
+    R = __QSUB16(R, T);
+
+    /* co2 & si2 are read from SIMD Coefficient pointer */
+    C2 = pCoeff[2u * ic];
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out1 = __SMUAD(C2, R) >> 16u;
+    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out2 = __SMUSDX(C2, R);
+
+#else
+
+    /* xc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out1 = __SMUSDX(R, C2) >> 16u;
+    /* yc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out2 = __SMUAD(C2, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /*  Reading i0+fftLen/4 */
+    /* T = packed(yb, xb) */
+    T = pSrc[i1];
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    pSrc[i1] = (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    /*  Butterfly calculations */
+    /* U = packed(yd, xd) */
+    U = pSrc[i3];
+    in = ((int16_t) (U & 0xFFFF)) >> 2;
+    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* T = packed(yb-yd, xb-xd) */
+    T = __QSUB16(T, U);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+    R = __QASX(S, T);
+    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+    S = __QSAX(S, T);
+
+#else
+
+    /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+    R = __QSAX(S, T);
+    /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+    S = __QASX(S, T);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* co1 & si1 are read from SIMD Coefficient pointer */
+    C1 = pCoeff[ic];
+    /*  Butterfly process for the i0+fftLen/2 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out1 = __SMUAD(C1, S) >> 16u;
+    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out2 = __SMUSDX(C1, S);
+
+#else
+
+    /* xb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out1 = __SMUSDX(S, C1) >> 16u;
+    /* yb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out2 = __SMUAD(C1, S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xb', yb') in little endian format */
+    pSrc[i2] = ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
+
+
+    /* co3 & si3 are read from SIMD Coefficient pointer */
+    C3 = pCoeff[3u * ic];
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+    out1 = __SMUAD(C3, R) >> 16u;
+    /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+    out2 = __SMUSDX(C3, R);
+
+#else
+
+    /* xd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+    out1 = __SMUSDX(R, C3) >> 16u;
+    /* yd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+    out2 = __SMUAD(C3, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xd', yd') in little endian format */
+    pSrc[i3] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+  /* data is in 4.11(q11) format */
+
+  /* end of first stage process */
+
+
+  /* start of middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ic = 0u;
+
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      C1 = pCoeff[ic];
+      C2 = pCoeff[2u * ic];
+      C3 = pCoeff[3u * ic];
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T = pSrc[i0];
+
+        /* Read yc (real), xc(imag) input */
+        S = pSrc[i2];
+
+        /* R = packed( (ya + yc), (xa + xc)) */
+        R = __QADD16(T, S);
+
+        /* S = packed((ya - yc), (xa - xc)) */
+        S = __QSUB16(T, S);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T = pSrc[i1];
+
+        /* Read yd (real), xd(imag) input */
+        U = pSrc[i3];
+
+
+        /* T = packed( (yb + yd), (xb + xd)) */
+        T = __QADD16(T, U);
+
+
+        /*  writing the butterfly processed i0 sample */
+
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        out1 = __SHADD16(R, T);
+        in = ((int16_t) (out1 & 0xFFFF)) >> 1;
+        out1 = ((out1 >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+        pSrc[i0] = out1;
+
+        /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+        R = __SHSUB16(R, T);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out1 = __SMUAD(C2, R) >> 16u;
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out2 = __SMUSDX(C2, R);
+
+#else
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out1 = __SMUSDX(R, C2) >> 16u;
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out2 = __SMUAD(C2, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T = pSrc[i1];
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        pSrc[i1] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        /*  Butterfly calculations */
+
+        /* Read yd (real), xd(imag) input */
+        U = pSrc[i3];
+
+        /* T = packed(yb-yd, xb-xd) */
+        T = __QSUB16(T, U);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+        R = __SHASX(S, T);
+
+        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+        S = __SHSAX(S, T);
+
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUAD(C1, S) >> 16u;
+        out2 = __SMUSDX(C1, S);
+
+#else
+
+        /* R = packed((ya-yc) + (xb- xd) , (xa-xc) - (yb-yd)) */
+        R = __SHSAX(S, T);
+
+        /* S = packed((ya-yc) - (xb- xd),  (xa-xc) + (yb-yd)) */
+        S = __SHASX(S, T);
+
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUSDX(S, C1) >> 16u;
+        out2 = __SMUAD(C1, S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+        pSrc[i2] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUAD(C3, R) >> 16u;
+        out2 = __SMUSDX(C3, R);
+
+#else
+
+        out1 = __SMUSDX(R, C3) >> 16u;
+        out2 = __SMUAD(C3, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3) */
+        /* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3) */
+        pSrc[i3] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2u;
+  }
+  /* end of middle stage process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point */
+  /* data is in 6.10(q10) format for the 64 point */
+  /* data is in 4.12(q12) format for the 16 point */
+
+  /*  Initializations for the last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /* start of last stage process */
+
+  /*  Butterfly implementation */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T = pSrc[i0];
+    /* Read yc (real), xc(imag) input */
+    S = pSrc[i2];
+
+    /* R = packed((ya + yc), (xa + xc)) */
+    R = __QADD16(T, S);
+    /* S = packed((ya - yc), (xa - xc)) */
+    S = __QSUB16(T, S);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T = pSrc[i1];
+    /* Read yd (real), xd(imag) input */
+    U = pSrc[i3];
+
+    /* T = packed((yb + yd), (xb + xd)) */
+    T = __QADD16(T, U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc[i0] = __SHADD16(R, T);
+
+    /* R = packed((ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+    R = __SHSUB16(R, T);
+
+    /* Read yb (real), xb(imag) input */
+    T = pSrc[i1];
+
+    /*  writing the butterfly processed i0 + fftLen/4 sample */
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    pSrc[i1] = R;
+
+    /* Read yd (real), xd(imag) input */
+    U = pSrc[i3];
+    /* T = packed( (yb - yd), (xb - xd))  */
+    T = __QSUB16(T, U);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    pSrc[i2] = __SHSAX(S, T);
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    pSrc[i3] = __SHASX(S, T);
+
+#else
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    pSrc[i2] = __SHASX(S, T);
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    pSrc[i3] = __SHSAX(S, T);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+  }
+
+  /* end of last stage process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t R0, R1, S0, S1, T0, T1, U0, U1;
+  q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
+  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  /* Index for twiddle coefficient */
+  ic = 0u;
+
+  /* Index for input read and output write */
+  i0 = 0u;
+  j = n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+
+    /* input is down scale by 4 to avoid overflow */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2u] >> 2u;
+    T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
+
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2u] >> 2u;
+    S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
+
+    /* R0 = (ya + yc) */
+    R0 = __SSAT(T0 + S0, 16u);
+    /* R1 = (xa + xc) */
+    R1 = __SSAT(T1 + S1, 16u);
+
+    /* S0 = (ya - yc) */
+    S0 = __SSAT(T0 - S0, 16);
+    /* S1 = (xa - xc) */
+    S1 = __SSAT(T1 - S1, 16);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u] >> 2u;
+    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u] >> 2u;
+    U1 = pSrc16[(i3 * 2u) + 1] >> 2u;
+
+    /* T0 = (yb + yd) */
+    T0 = __SSAT(T0 + U0, 16u);
+    /* T1 = (xb + xd) */
+    T1 = __SSAT(T1 + U1, 16u);
+
+    /*  writing the butterfly processed i0 sample */
+    /* ya' = ya + yb + yc + yd */
+    /* xa' = xa + xb + xc + xd */
+    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+    /* R0 = (ya + yc) - (yb + yd) */
+    /* R1 = (xa + xc) - (xb + xd) */
+    R0 = __SSAT(R0 - T0, 16u);
+    R1 = __SSAT(R1 - T1, 16u);
+
+    /* co2 & si2 are read from Coefficient pointer */
+    Co2 = pCoef16[2u * ic * 2u];
+    Si2 = pCoef16[(2u * ic * 2u) + 1];
+
+    /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+    out1 = (short) ((Co2 * R0 + Si2 * R1) >> 16u);
+    /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+    out2 = (short) ((-Si2 * R0 + Co2 * R1) >> 16u);
+
+    /*  Reading i0+fftLen/4 */
+    /* input is down scale by 4 to avoid overflow */
+    /* T0 = yb, T1 =  xb */
+    T0 = pSrc16[i1 * 2u] >> 2;
+    T1 = pSrc16[(i1 * 2u) + 1] >> 2;
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    pSrc16[i1 * 2u] = out1;
+    pSrc16[(i1 * 2u) + 1] = out2;
+
+    /*  Butterfly calculations */
+    /* input is down scale by 4 to avoid overflow */
+    /* U0 = yd, U1 = xd */
+    U0 = pSrc16[i3 * 2u] >> 2;
+    U1 = pSrc16[(i3 * 2u) + 1] >> 2;
+    /* T0 = yb-yd */
+    T0 = __SSAT(T0 - U0, 16);
+    /* T1 = xb-xd */
+    T1 = __SSAT(T1 - U1, 16);
+
+    /* R1 = (ya-yc) + (xb- xd),  R0 = (xa-xc) - (yb-yd)) */
+    R0 = (short) __SSAT((q31_t) (S0 - T1), 16);
+    R1 = (short) __SSAT((q31_t) (S1 + T0), 16);
+
+    /* S1 = (ya-yc) - (xb- xd), S0 = (xa-xc) + (yb-yd)) */
+    S0 = (short) __SSAT(((q31_t) S0 + T1), 16u);
+    S1 = (short) __SSAT(((q31_t) S1 - T0), 16u);
+
+    /* co1 & si1 are read from Coefficient pointer */
+    Co1 = pCoef16[ic * 2u];
+    Si1 = pCoef16[(ic * 2u) + 1];
+    /*  Butterfly process for the i0+fftLen/2 sample */
+    /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+    out1 = (short) ((Si1 * S1 + Co1 * S0) >> 16);
+    /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+    out2 = (short) ((-Si1 * S0 + Co1 * S1) >> 16);
+
+    /* writing output(xb', yb') in little endian format */
+    pSrc16[i2 * 2u] = out1;
+    pSrc16[(i2 * 2u) + 1] = out2;
+
+    /* Co3 & si3 are read from Coefficient pointer */
+    Co3 = pCoef16[3u * (ic * 2u)];
+    Si3 = pCoef16[(3u * (ic * 2u)) + 1];
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+    /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
+    out1 = (short) ((Si3 * R1 + Co3 * R0) >> 16u);
+    /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
+    out2 = (short) ((-Si3 * R0 + Co3 * R1) >> 16u);
+    /* writing output(xd', yd') in little endian format */
+    pSrc16[i3 * 2u] = out1;
+    pSrc16[(i3 * 2u) + 1] = out2;
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+  /* data is in 4.11(q11) format */
+
+  /* end of first stage process */
+
+
+  /* start of middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ic = 0u;
+
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      Co1 = pCoef16[ic * 2u];
+      Si1 = pCoef16[(ic * 2u) + 1u];
+      Co2 = pCoef16[2u * (ic * 2u)];
+      Si2 = pCoef16[(2u * (ic * 2u)) + 1u];
+      Co3 = pCoef16[3u * (ic * 2u)];
+      Si3 = pCoef16[(3u * (ic * 2u)) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T0 = pSrc16[i0 * 2u];
+        T1 = pSrc16[(i0 * 2u) + 1u];
+
+        /* Read yc (real), xc(imag) input */
+        S0 = pSrc16[i2 * 2u];
+        S1 = pSrc16[(i2 * 2u) + 1u];
+
+        /* R0 = (ya + yc), R1 = (xa + xc) */
+        R0 = __SSAT(T0 + S0, 16);
+        R1 = __SSAT(T1 + S1, 16);
+
+        /* S0 = (ya - yc), S1 =(xa - xc) */
+        S0 = __SSAT(T0 - S0, 16);
+        S1 = __SSAT(T1 - S1, 16);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2u];
+        T1 = pSrc16[(i1 * 2u) + 1u];
+
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2u];
+        U1 = pSrc16[(i3 * 2u) + 1u];
+
+
+        /* T0 = (yb + yd), T1 = (xb + xd) */
+        T0 = __SSAT(T0 + U0, 16);
+        T1 = __SSAT(T1 + U1, 16);
+
+        /*  writing the butterfly processed i0 sample */
+
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        out1 = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
+        out2 = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
+
+        pSrc16[i0 * 2u] = out1;
+        pSrc16[(2u * i0) + 1u] = out2;
+
+        /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+        R0 = (R0 >> 1u) - (T0 >> 1u);
+        R1 = (R1 >> 1u) - (T1 >> 1u);
+
+        /* (ya-yb+yc-yd)* (si2) + (xa-xb+xc-xd)* co2 */
+        out1 = (short) ((Co2 * R0 + Si2 * R1) >> 16u);
+
+        /* (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        out2 = (short) ((-Si2 * R0 + Co2 * R1) >> 16u);
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2u];
+        T1 = pSrc16[(i1 * 2u) + 1u];
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2) */
+        pSrc16[i1 * 2u] = out1;
+        pSrc16[(i1 * 2u) + 1u] = out2;
+
+        /*  Butterfly calculations */
+
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2u];
+        U1 = pSrc16[(i3 * 2u) + 1u];
+
+        /* T0 = yb-yd, T1 = xb-xd */
+        T0 = __SSAT(T0 - U0, 16);
+        T1 = __SSAT(T1 - U1, 16);
+
+        /* R0 = (ya-yc) + (xb- xd), R1 = (xa-xc) - (yb-yd)) */
+        R0 = (S0 >> 1u) - (T1 >> 1u);
+        R1 = (S1 >> 1u) + (T0 >> 1u);
+
+        /* S0 = (ya-yc) - (xb- xd), S1 = (xa-xc) + (yb-yd)) */
+        S0 = (S0 >> 1u) + (T1 >> 1u);
+        S1 = (S1 >> 1u) - (T0 >> 1u);
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = (short) ((Co1 * S0 + Si1 * S1) >> 16u);
+
+        out2 = (short) ((-Si1 * S0 + Co1 * S1) >> 16u);
+
+        /* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1) */
+        /* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1) */
+        pSrc16[i2 * 2u] = out1;
+        pSrc16[(i2 * 2u) + 1u] = out2;
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+        out1 = (short) ((Si3 * R1 + Co3 * R0) >> 16u);
+
+        out2 = (short) ((-Si3 * R0 + Co3 * R1) >> 16u);
+        /* xd' = (xa-yb-xc+yd)* Co3 + (ya+xb-yc-xd)* (si3) */
+        /* yd' = (ya+xb-yc-xd)* Co3 - (xa-yb-xc+yd)* (si3) */
+        pSrc16[i3 * 2u] = out1;
+        pSrc16[(i3 * 2u) + 1u] = out2;
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2u;
+  }
+  /* end of middle stage process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point */
+  /* data is in 6.10(q10) format for the 64 point */
+  /* data is in 4.12(q12) format for the 16 point */
+
+  /*  Initializations for the last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /* start of last stage process */
+
+  /*  Butterfly implementation */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2u];
+    T1 = pSrc16[(i0 * 2u) + 1u];
+
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2u];
+    S1 = pSrc16[(i2 * 2u) + 1u];
+
+    /* R0 = (ya + yc), R1 = (xa + xc) */
+    R0 = __SSAT(T0 + S0, 16u);
+    R1 = __SSAT(T1 + S1, 16u);
+
+    /* S0 = (ya - yc), S1 = (xa - xc) */
+    S0 = __SSAT(T0 - S0, 16u);
+    S1 = __SSAT(T1 - S1, 16u);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u];
+    T1 = pSrc16[(i1 * 2u) + 1u];
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u];
+    U1 = pSrc16[(i3 * 2u) + 1u];
+
+    /* T0 = (yb + yd), T1 = (xb + xd)) */
+    T0 = __SSAT(T0 + U0, 16u);
+    T1 = __SSAT(T1 + U1, 16u);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+    R0 = (R0 >> 1u) - (T0 >> 1u);
+    R1 = (R1 >> 1u) - (T1 >> 1u);
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u];
+    T1 = pSrc16[(i1 * 2u) + 1u];
+
+    /*  writing the butterfly processed i0 + fftLen/4 sample */
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    pSrc16[i1 * 2u] = R0;
+    pSrc16[(i1 * 2u) + 1u] = R1;
+
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u];
+    U1 = pSrc16[(i3 * 2u) + 1u];
+    /* T0 = (yb - yd), T1 = (xb - xd)  */
+    T0 = __SSAT(T0 - U0, 16u);
+    T1 = __SSAT(T1 - U1, 16u);
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa+yb-xc-yd) */
+    /* yb' = (ya-xb-yc+xd) */
+    pSrc16[i2 * 2u] = (S0 >> 1u) + (T1 >> 1u);
+    pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa-yb-xc+yd) */
+    /* yd' = (ya+xb-yc-xd) */
+    pSrc16[i3 * 2u] = (S0 >> 1u) - (T1 >> 1u);
+    pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
+
+  }
+
+  /* end of last stage process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+
+/**   
+ * @brief  Core function for the Q15 CIFFT butterfly process.  
+ * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.  
+ * @param[in]      fftLen           length of the FFT.  
+ * @param[in]      *pCoef16         points to twiddle coefficient buffer.  
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.  
+ */
+
+/*   
+* Radix-4 IFFT algorithm used is :   
+*   
+* CIFFT uses same twiddle coefficients as CFFT function   
+*  x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]   
+*   
+*   
+* IFFT is implemented with following changes in equations from FFT   
+*   
+* Input real and imaginary data:   
+* x(n) = xa + j * ya   
+* x(n+N/4 ) = xb + j * yb   
+* x(n+N/2 ) = xc + j * yc   
+* x(n+3N 4) = xd + j * yd   
+*   
+*   
+* Output real and imaginary data:   
+* x(4r) = xa'+ j * ya'   
+* x(4r+1) = xb'+ j * yb'   
+* x(4r+2) = xc'+ j * yc'   
+* x(4r+3) = xd'+ j * yd'   
+*   
+*   
+* Twiddle factors for radix-4 IFFT:   
+* Wn = co1 + j * (si1)   
+* W2n = co2 + j * (si2)   
+* W3n = co3 + j * (si3)   
+   
+* The real and imaginary output values for the radix-4 butterfly are   
+* xa' = xa + xb + xc + xd   
+* ya' = ya + yb + yc + yd   
+* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)   
+* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)   
+* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)   
+* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)   
+* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)   
+* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)   
+*   
+*/
+
+void arm_radix4_butterfly_inverse_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  q15_t * pCoef16,
+  uint32_t twidCoefModifier)
+{
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  q31_t R, S, T, U;
+  q31_t C1, C2, C3, out1, out2;
+  q31_t *pSrc, *pCoeff;
+  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+  q15_t in;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  pointer initializations for SIMD calculations */
+  pSrc = (q31_t *) pSrc16;
+  pCoeff = (q31_t *) pCoef16;
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  /* Index for twiddle coefficient */
+  ic = 0u;
+
+  /* Index for input read and output write */
+  i0 = 0u;
+
+  j = n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  Start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T = pSrc[i0];
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* Read yc (real), xc(imag) input */
+    S = pSrc[i2];
+    in = ((int16_t) (S & 0xFFFF)) >> 2;
+    S = ((S >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* R = packed((ya + yc), (xa + xc) ) */
+    R = __QADD16(T, S);
+    /* S = packed((ya - yc), (xa - xc) ) */
+    S = __QSUB16(T, S);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T = pSrc[i1];
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+    /* Read yd (real), xd(imag) input */
+    U = pSrc[i3];
+    in = ((int16_t) (U & 0xFFFF)) >> 2;
+    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* T = packed((yb + yd), (xb + xd) ) */
+    T = __QADD16(T, U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc[i0] = __SHADD16(R, T);
+
+    /* R = packed((ya + yc) - (yb + yd), (xa + xc)- (xb + xd)) */
+    R = __QSUB16(R, T);
+    /* co2 & si2 are read from SIMD Coefficient pointer */
+    C2 = pCoeff[2u * ic];
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+    out1 = __SMUSD(C2, R) >> 16u;
+    /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+    out2 = __SMUADX(C2, R);
+
+#else
+
+    /* xc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+    out1 = __SMUADX(C2, R) >> 16u;
+    /* yc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+    out2 = __SMUSD(-C2, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /*  Reading i0+fftLen/4 */
+    /* T = packed(yb, xb) */
+    T = pSrc[i1];
+    in = ((int16_t) (T & 0xFFFF)) >> 2;
+    T = ((T >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    pSrc[i1] = (q31_t) ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    /*  Butterfly calculations */
+    /* U = packed(yd, xd) */
+    U = pSrc[i3];
+    in = ((int16_t) (U & 0xFFFF)) >> 2;
+    U = ((U >> 2) & 0xFFFF0000) | (in & 0xFFFF);
+
+    /* T = packed(yb-yd, xb-xd) */
+    T = __QSUB16(T, U);
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* R = packed((ya-yc) - (xb- xd) , (xa-xc) + (yb-yd)) */
+    R = __QSAX(S, T);
+    /* S = packed((ya-yc) + (xb- xd),  (xa-xc) - (yb-yd)) */
+    S = __QASX(S, T);
+
+#else
+
+    /* R = packed((ya-yc) - (xb- xd) , (xa-xc) + (yb-yd)) */
+    R = __QASX(S, T);
+    /* S = packed((ya-yc) + (xb- xd),  (xa-xc) - (yb-yd)) */
+    S = __QSAX(S, T);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* co1 & si1 are read from SIMD Coefficient pointer */
+    C1 = pCoeff[ic];
+    /*  Butterfly process for the i0+fftLen/2 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+    out1 = __SMUSD(C1, S) >> 16u;
+    /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+    out2 = __SMUADX(C1, S);
+
+#else
+
+    /* xb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+    out1 = __SMUADX(C1, S) >> 16u;
+    /* yb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+    out2 = __SMUSD(-C1, S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xb', yb') in little endian format */
+    pSrc[i2] = ((out2) & 0xFFFF0000) | ((out1) & 0x0000FFFF);
+
+    /* co3 & si3 are read from SIMD Coefficient pointer */
+    C3 = pCoeff[3u * ic];
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3) */
+    out1 = __SMUSD(C3, R) >> 16u;
+    /* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3) */
+    out2 = __SMUADX(C3, R);
+
+#else
+
+    /* xd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3) */
+    out1 = __SMUADX(C3, R) >> 16u;
+    /* yd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3) */
+    out2 = __SMUSD(-C3, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* writing output(xd', yd') in little endian format */
+    pSrc[i3] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+
+  /*  End of first stage process */
+
+  /* data is in 4.11(q11) format */
+
+
+  /*  Start of Middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ic = 0u;
+
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      C1 = pCoeff[ic];
+      C2 = pCoeff[2u * ic];
+      C3 = pCoeff[3u * ic];
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T = pSrc[i0];
+
+        /* Read yc (real), xc(imag) input */
+        S = pSrc[i2];
+
+
+        /* R = packed( (ya + yc), (xa + xc)) */
+        R = __QADD16(T, S);
+        /* S = packed((ya - yc), (xa - xc)) */
+        S = __QSUB16(T, S);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T = pSrc[i1];
+
+        /* Read yd (real), xd(imag) input */
+        U = pSrc[i3];
+
+
+        /* T = packed( (yb + yd), (xb + xd)) */
+        T = __QADD16(T, U);
+
+        /*  writing the butterfly processed i0 sample */
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        out1 = __SHADD16(R, T);
+        in = ((int16_t) (out1 & 0xFFFF)) >> 1;
+        out1 = ((out1 >> 1) & 0xFFFF0000) | (in & 0xFFFF);
+        pSrc[i0] = out1;
+
+
+
+        /* R = packed( (ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+        R = __SHSUB16(R, T);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */
+        out1 = __SMUSD(C2, R) >> 16u;
+        /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        out2 = __SMUADX(C2, R);
+
+#else
+
+        /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        out1 = __SMUADX(R, C2) >> 16u;
+        /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */
+        out2 = __SMUSD(-C2, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T = pSrc[i1];
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        pSrc[i1] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        /*  Butterfly calculations */
+        /* Read yd (real), xd(imag) input */
+        U = pSrc[i3];
+
+        /* T = packed(yb-yd, xb-xd) */
+        T = __QSUB16(T, U);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        /* R = packed((ya-yc) - (xb- xd) , (xa-xc) + (yb-yd)) */
+        R = __SHSAX(S, T);
+
+        /* S = packed((ya-yc) + (xb- xd),  (xa-xc) - (yb-yd)) */
+        S = __SHASX(S, T);
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUSD(C1, S) >> 16u;
+        out2 = __SMUADX(C1, S);
+
+#else
+
+        /* R = packed((ya-yc) - (xb- xd) , (xa-xc) + (yb-yd)) */
+        R = __SHASX(S, T);
+
+        /* S = packed((ya-yc) + (xb- xd),  (xa-xc) - (yb-yd)) */
+        S = __SHSAX(S, T);
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = __SMUADX(S, C1) >> 16u;
+        out2 = __SMUSD(-C1, S);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+        /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+        pSrc[i2] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+        out1 = __SMUSD(C3, R) >> 16u;
+        out2 = __SMUADX(C3, R);
+
+#else
+
+        out1 = __SMUADX(C3, R) >> 16u;
+        out2 = __SMUSD(-C3, R);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+        /* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3) */
+        /* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3) */
+        pSrc[i3] = ((out2) & 0xFFFF0000) | (out1 & 0x0000FFFF);
+
+
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2u;
+  }
+  /*  End of Middle stages process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point   */
+  /* data is in 6.10(q10) format for the 64 point  */
+  /* data is in 4.12(q12) format for the 16 point  */
+
+  /* start of last stage process */
+
+
+  /*  Initializations for the last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Butterfly implementation */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T = pSrc[i0];
+    /* Read yc (real), xc(imag) input */
+    S = pSrc[i2];
+
+    /* R = packed((ya + yc), (xa + xc)) */
+    R = __QADD16(T, S);
+    /* S = packed((ya - yc), (xa - xc)) */
+    S = __QSUB16(T, S);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T = pSrc[i1];
+    /* Read yd (real), xd(imag) input */
+    U = pSrc[i3];
+
+    /* T = packed((yb + yd), (xb + xd)) */
+    T = __QADD16(T, U);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc[i0] = __SHADD16(R, T);
+
+    /* R = packed((ya + yc) - (yb + yd), (xa + xc) - (xb + xd)) */
+    R = __SHSUB16(R, T);
+
+    /* Read yb (real), xb(imag) input */
+    T = pSrc[i1];
+
+    /*  writing the butterfly processed i0 + fftLen/4 sample */
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    pSrc[i1] = R;
+
+    /* Read yd (real), xd(imag) input */
+    U = pSrc[i3];
+    /* T = packed( (yb - yd), (xb - xd))  */
+    T = __QSUB16(T, U);
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa-yb-xc+yd) */
+    /* yb' = (ya+xb-yc-xd) */
+    pSrc[i2] = __SHASX(S, T);
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa+yb-xc-yd) */
+    /* yd' = (ya-xb-yc+xd) */
+    pSrc[i3] = __SHSAX(S, T);
+
+
+#else
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa-yb-xc+yd) */
+    /* yb' = (ya+xb-yc-xd) */
+    pSrc[i2] = __SHSAX(S, T);
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa+yb-xc-yd) */
+    /* yd' = (ya-xb-yc+xd) */
+    pSrc[i3] = __SHASX(S, T);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+  }
+  /* end of last stage  process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  q15_t R0, R1, S0, S1, T0, T1, U0, U1;
+  q15_t Co1, Si1, Co2, Si2, Co3, Si3, out1, out2;
+  uint32_t n1, n2, ic, i0, i1, i2, i3, j, k;
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+
+  /* Index for twiddle coefficient */
+  ic = 0u;
+
+  /* Index for input read and output write */
+  i0 = 0u;
+
+  j = n2;
+
+  /* Input is in 1.15(q15) format */
+
+  /*  Start of first stage process */
+  do
+  {
+    /*  Butterfly implementation */
+
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* input is down scale by 4 to avoid overflow */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2u] >> 2u;
+    T1 = pSrc16[(i0 * 2u) + 1u] >> 2u;
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2u] >> 2u;
+    S1 = pSrc16[(i2 * 2u) + 1u] >> 2u;
+
+    /* R0 = (ya + yc), R1 = (xa + xc) */
+    R0 = __SSAT(T0 + S0, 16u);
+    R1 = __SSAT(T1 + S1, 16u);
+    /* S0 = (ya - yc), S1 = (xa - xc) */
+    S0 = __SSAT(T0 - S0, 16u);
+    S1 = __SSAT(T1 - S1, 16u);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* input is down scale by 4 to avoid overflow */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u] >> 2u;
+    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+    /* Read yd (real), xd(imag) input */
+    /* input is down scale by 4 to avoid overflow */
+    U0 = pSrc16[i3 * 2u] >> 2u;
+    U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
+
+    /* T0 = (yb + yd), T1 = (xb + xd) */
+    T0 = __SSAT(T0 + U0, 16u);
+    T1 = __SSAT(T1 + U1, 16u);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc)- (xb + xd) */
+    R0 = __SSAT(R0 - T0, 16u);
+    R1 = __SSAT(R1 - T1, 16u);
+    /* co2 & si2 are read from Coefficient pointer */
+    Co2 = pCoef16[2u * ic * 2u];
+    Si2 = pCoef16[(2u * ic * 2u) + 1u];
+    /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+    out1 = (short) ((Co2 * R0 - Si2 * R1) >> 16u);
+    /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+    out2 = (short) ((Si2 * R0 + Co2 * R1) >> 16u);
+
+    /*  Reading i0+fftLen/4 */
+    /* input is down scale by 4 to avoid overflow */
+    /* T0 = yb, T1 = xb */
+    T0 = pSrc16[i1 * 2u] >> 2u;
+    T1 = pSrc16[(i1 * 2u) + 1u] >> 2u;
+
+    /* writing the butterfly processed i0 + fftLen/4 sample */
+    /* writing output(xc', yc') in little endian format */
+    pSrc16[i1 * 2u] = out1;
+    pSrc16[(i1 * 2u) + 1u] = out2;
+
+    /*  Butterfly calculations */
+    /* input is down scale by 4 to avoid overflow */
+    /* U0 = yd, U1 = xd) */
+    U0 = pSrc16[i3 * 2u] >> 2u;
+    U1 = pSrc16[(i3 * 2u) + 1u] >> 2u;
+
+    /* T0 = yb-yd, T1 = xb-xd) */
+    T0 = __SSAT(T0 - U0, 16u);
+    T1 = __SSAT(T1 - U1, 16u);
+    /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
+    R0 = (short) __SSAT((q31_t) (S0 + T1), 16);
+    R1 = (short) __SSAT((q31_t) (S1 - T0), 16);
+    /* S = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
+    S0 = (short) __SSAT((q31_t) (S0 - T1), 16);
+    S1 = (short) __SSAT((q31_t) (S1 + T0), 16);
+
+    /* co1 & si1 are read from Coefficient pointer */
+    Co1 = pCoef16[ic * 2u];
+    Si1 = pCoef16[(ic * 2u) + 1u];
+    /*  Butterfly process for the i0+fftLen/2 sample */
+    /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+    out1 = (short) ((Co1 * S0 - Si1 * S1) >> 16u);
+    /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+    out2 = (short) ((Si1 * S0 + Co1 * S1) >> 16u);
+    /* writing output(xb', yb') in little endian format */
+    pSrc16[i2 * 2u] = out1;
+    pSrc16[(i2 * 2u) + 1u] = out2;
+
+    /* Co3 & si3 are read from Coefficient pointer */
+    Co3 = pCoef16[3u * ic * 2u];
+    Si3 = pCoef16[(3u * ic * 2u) + 1u];
+    /*  Butterfly process for the i0+3fftLen/4 sample */
+    /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
+    out1 = (short) ((Co3 * R0 - Si3 * R1) >> 16u);
+    /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
+    out2 = (short) ((Si3 * R0 + Co3 * R1) >> 16u);
+    /* writing output(xd', yd') in little endian format */
+    pSrc16[i3 * 2u] = out1;
+    pSrc16[(i3 * 2u) + 1u] = out2;
+
+    /*  Twiddle coefficients index modifier */
+    ic = ic + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+
+  /*  End of first stage process */
+
+  /* data is in 4.11(q11) format */
+
+
+  /*  Start of Middle stage process */
+
+  /*  Twiddle coefficients index modifier */
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of Middle stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the middle stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ic = 0u;
+
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      Co1 = pCoef16[ic * 2u];
+      Si1 = pCoef16[(ic * 2u) + 1u];
+      Co2 = pCoef16[2u * ic * 2u];
+      Si2 = pCoef16[2u * ic * 2u + 1u];
+      Co3 = pCoef16[3u * ic * 2u];
+      Si3 = pCoef16[(3u * ic * 2u) + 1u];
+
+      /*  Twiddle coefficients index modifier */
+      ic = ic + twidCoefModifier;
+
+      /*  Butterfly implementation */
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Reading i0, i0+fftLen/2 inputs */
+        /* Read ya (real), xa(imag) input */
+        T0 = pSrc16[i0 * 2u];
+        T1 = pSrc16[(i0 * 2u) + 1u];
+
+        /* Read yc (real), xc(imag) input */
+        S0 = pSrc16[i2 * 2u];
+        S1 = pSrc16[(i2 * 2u) + 1u];
+
+
+        /* R0 = (ya + yc), R1 = (xa + xc) */
+        R0 = __SSAT(T0 + S0, 16u);
+        R1 = __SSAT(T1 + S1, 16u);
+        /* S0 = (ya - yc), S1 = (xa - xc) */
+        S0 = __SSAT(T0 - S0, 16u);
+        S1 = __SSAT(T1 - S1, 16u);
+
+        /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2u];
+        T1 = pSrc16[(i1 * 2u) + 1u];
+
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2u];
+        U1 = pSrc16[(i3 * 2u) + 1u];
+
+        /* T0 = (yb + yd), T1 = (xb + xd) */
+        T0 = __SSAT(T0 + U0, 16u);
+        T1 = __SSAT(T1 + U1, 16u);
+
+        /*  writing the butterfly processed i0 sample */
+        /* xa' = xa + xb + xc + xd */
+        /* ya' = ya + yb + yc + yd */
+        pSrc16[i0 * 2u] = ((R0 >> 1u) + (T0 >> 1u)) >> 1u;
+        pSrc16[(i0 * 2u) + 1u] = ((R1 >> 1u) + (T1 >> 1u)) >> 1u;
+
+        /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+        R0 = (R0 >> 1u) - (T0 >> 1u);
+        R1 = (R1 >> 1u) - (T1 >> 1u);
+
+        /* (ya-yb+yc-yd)* (si2) - (xa-xb+xc-xd)* co2 */
+        out1 = (short) ((Co2 * R0 - Si2 * R1) >> 16);
+        /* (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        out2 = (short) ((Si2 * R0 + Co2 * R1) >> 16);
+
+        /*  Reading i0+3fftLen/4 */
+        /* Read yb (real), xb(imag) input */
+        T0 = pSrc16[i1 * 2u];
+        T1 = pSrc16[(i1 * 2u) + 1u];
+
+        /*  writing the butterfly processed i0 + fftLen/4 sample */
+        /* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2) */
+        /* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2) */
+        pSrc16[i1 * 2u] = out1;
+        pSrc16[(i1 * 2u) + 1u] = out2;
+
+        /*  Butterfly calculations */
+        /* Read yd (real), xd(imag) input */
+        U0 = pSrc16[i3 * 2u];
+        U1 = pSrc16[(i3 * 2u) + 1u];
+
+        /* T0 = yb-yd, T1 = xb-xd) */
+        T0 = __SSAT(T0 - U0, 16u);
+        T1 = __SSAT(T1 - U1, 16u);
+
+        /* R0 = (ya-yc) - (xb- xd) , R1 = (xa-xc) + (yb-yd) */
+        R0 = (S0 >> 1u) + (T1 >> 1u);
+        R1 = (S1 >> 1u) - (T0 >> 1u);
+
+        /* S1 = (ya-yc) + (xb- xd), S1 = (xa-xc) - (yb-yd) */
+        S0 = (S0 >> 1u) - (T1 >> 1u);
+        S1 = (S1 >> 1u) + (T0 >> 1u);
+
+        /*  Butterfly process for the i0+fftLen/2 sample */
+        out1 = (short) ((Co1 * S0 - Si1 * S1) >> 16u);
+        out2 = (short) ((Si1 * S0 + Co1 * S1) >> 16u);
+        /* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1) */
+        /* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1) */
+        pSrc16[i2 * 2u] = out1;
+        pSrc16[(i2 * 2u) + 1u] = out2;
+
+        /*  Butterfly process for the i0+3fftLen/4 sample */
+        out1 = (short) ((Co3 * R0 - Si3 * R1) >> 16u);
+
+        out2 = (short) ((Si3 * R0 + Co3 * R1) >> 16u);
+        /* xd' = (xa+yb-xc-yd)* Co3 - (ya-xb-yc+xd)* (si3) */
+        /* yd' = (ya-xb-yc+xd)* Co3 + (xa+yb-xc-yd)* (si3) */
+        pSrc16[i3 * 2u] = out1;
+        pSrc16[(i3 * 2u) + 1u] = out2;
+
+
+      }
+    }
+    /*  Twiddle coefficients index modifier */
+    twidCoefModifier <<= 2u;
+  }
+  /*  End of Middle stages process */
+
+
+  /* data is in 10.6(q6) format for the 1024 point */
+  /* data is in 8.8(q8) format for the 256 point   */
+  /* data is in 6.10(q10) format for the 64 point  */
+  /* data is in 4.12(q12) format for the 16 point  */
+
+  /* start of last stage process */
+
+
+  /*  Initializations for the last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Butterfly implementation */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc16[i0 + 0], pSrc16[i0 + fftLen/4], pSrc16[i0 + fftLen/2], pSrc16[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Reading i0, i0+fftLen/2 inputs */
+    /* Read ya (real), xa(imag) input */
+    T0 = pSrc16[i0 * 2u];
+    T1 = pSrc16[(i0 * 2u) + 1u];
+    /* Read yc (real), xc(imag) input */
+    S0 = pSrc16[i2 * 2u];
+    S1 = pSrc16[(i2 * 2u) + 1u];
+
+    /* R0 = (ya + yc), R1 = (xa + xc) */
+    R0 = __SSAT(T0 + S0, 16u);
+    R1 = __SSAT(T1 + S1, 16u);
+    /* S0 = (ya - yc), S1 = (xa - xc) */
+    S0 = __SSAT(T0 - S0, 16u);
+    S1 = __SSAT(T1 - S1, 16u);
+
+    /*  Reading i0+fftLen/4 , i0+3fftLen/4 inputs */
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u];
+    T1 = pSrc16[(i1 * 2u) + 1u];
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u];
+    U1 = pSrc16[(i3 * 2u) + 1u];
+
+    /* T0 = (yb + yd), T1 = (xb + xd) */
+    T0 = __SSAT(T0 + U0, 16u);
+    T1 = __SSAT(T1 + U1, 16u);
+
+    /*  writing the butterfly processed i0 sample */
+    /* xa' = xa + xb + xc + xd */
+    /* ya' = ya + yb + yc + yd */
+    pSrc16[i0 * 2u] = (R0 >> 1u) + (T0 >> 1u);
+    pSrc16[(i0 * 2u) + 1u] = (R1 >> 1u) + (T1 >> 1u);
+
+    /* R0 = (ya + yc) - (yb + yd), R1 = (xa + xc) - (xb + xd) */
+    R0 = (R0 >> 1u) - (T0 >> 1u);
+    R1 = (R1 >> 1u) - (T1 >> 1u);
+
+    /* Read yb (real), xb(imag) input */
+    T0 = pSrc16[i1 * 2u];
+    T1 = pSrc16[(i1 * 2u) + 1u];
+
+    /*  writing the butterfly processed i0 + fftLen/4 sample */
+    /* xc' = (xa-xb+xc-xd) */
+    /* yc' = (ya-yb+yc-yd) */
+    pSrc16[i1 * 2u] = R0;
+    pSrc16[(i1 * 2u) + 1u] = R1;
+
+    /* Read yd (real), xd(imag) input */
+    U0 = pSrc16[i3 * 2u];
+    U1 = pSrc16[(i3 * 2u) + 1u];
+    /* T0 = (yb - yd), T1 = (xb - xd) */
+    T0 = __SSAT(T0 - U0, 16u);
+    T1 = __SSAT(T1 - U1, 16u);
+
+    /*  writing the butterfly processed i0 + fftLen/2 sample */
+    /* xb' = (xa-yb-xc+yd) */
+    /* yb' = (ya+xb-yc-xd) */
+    pSrc16[i2 * 2u] = (S0 >> 1u) - (T1 >> 1u);
+    pSrc16[(i2 * 2u) + 1u] = (S1 >> 1u) + (T0 >> 1u);
+
+
+    /*  writing the butterfly processed i0 + 3fftLen/4 sample */
+    /* xd' = (xa+yb-xc-yd) */
+    /* yd' = (ya-xb-yc+xd) */
+    pSrc16[i3 * 2u] = (S0 >> 1u) + (T1 >> 1u);
+    pSrc16[(i3 * 2u) + 1u] = (S1 >> 1u) - (T0 >> 1u);
+  }
+  /* end of last stage  process */
+
+  /* output is in 11.5(q5) format for the 1024 point */
+  /* output is in 9.7(q7) format for the 256 point   */
+  /* output is in 7.9(q9) format for the 64 point  */
+  /* output is in 5.11(q11) format for the 16 point  */
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+
+/*   
+   * @brief  In-place bit reversal function.  
+   * @param[in, out] *pSrc        points to the in-place buffer of Q15 data type.  
+   * @param[in]      fftLen       length of the FFT.  
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table  
+   * @param[in]      *pBitRevTab  points to bit reversal table.  
+   * @return none.  
+ */
+
+void arm_bitreversal_q15(
+  q15_t * pSrc16,
+  uint32_t fftLen,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTab)
+{
+  q31_t *pSrc = (q31_t *) pSrc16;
+  q31_t in;
+  uint32_t fftLenBy2, fftLenBy2p1;
+  uint32_t i, j;
+
+  /*  Initializations */
+  j = 0u;
+  fftLenBy2 = fftLen / 2u;
+  fftLenBy2p1 = (fftLen / 2u) + 1u;
+
+  /* Bit Reversal Implementation */
+  for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+  {
+    if(i < j)
+    {
+      /*  pSrc[i] <-> pSrc[j]; */
+      /*  pSrc[i+1u] <-> pSrc[j+1u] */
+      in = pSrc[i];
+      pSrc[i] = pSrc[j];
+      pSrc[j] = in;
+
+      /*  pSrc[i + fftLenBy2p1] <-> pSrc[j + fftLenBy2p1];  */
+      /*  pSrc[i + fftLenBy2p1+1u] <-> pSrc[j + fftLenBy2p1+1u] */
+      in = pSrc[i + fftLenBy2p1];
+      pSrc[i + fftLenBy2p1] = pSrc[j + fftLenBy2p1];
+      pSrc[j + fftLenBy2p1] = in;
+    }
+
+    /*  pSrc[i+1u] <-> pSrc[j+fftLenBy2];         */
+    /*  pSrc[i+2] <-> pSrc[j+fftLenBy2+1u]  */
+    in = pSrc[i + 1u];
+    pSrc[i + 1u] = pSrc[j + fftLenBy2];
+    pSrc[j + fftLenBy2] = in;
+
+    /*  Reading the index for the bit reversal */
+    j = *pBitRevTab;
+
+    /*  Updating the bit reversal index depending on the fft length  */
+    pBitRevTab += bitRevFactor;
+  }
+}
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c
new file mode 100644
index 0000000000..f61aa08926
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c
@@ -0,0 +1,906 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_cfft_radix4_q31.c   
+*   
+* Description:	This file has function definition of Radix-4 FFT & IFFT function and   
+*				In-place bit reversal using bit reversal table   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.5  2010/04/26    
+* 	 incorporated review comments and updated with latest CMSIS layer   
+*   
+* Version 0.0.3  2010/03/10    
+*    Initial version   
+* -------------------------------------------------------------------- */
+#include "arm_math.h"
+
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup CFFT_CIFFT   
+ * @{   
+ */
+
+/**   
+ * @details   
+ * @brief Processing function for the Q31 CFFT/CIFFT.   
+ * @param[in]      *S    points to an instance of the Q31 CFFT/CIFFT structure.  
+ * @param[in, out] *pSrc points to the complex data buffer of size 2*fftLen. Processing occurs in-place.  
+ * @return none.   
+ *    
+ * \par Input and output formats:   
+ * \par   
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.  
+ * Hence the output format is different for different FFT sizes.   
+ * The input and output formats for different FFT sizes and number of bits to upscale are mentioned in the tables below for CFFT and CIFFT:  
+ * \par  
+ * \image html CFFTQ31.gif "Input and Output Formats for Q31 CFFT"   
+ * \image html CIFFTQ31.gif "Input and Output Formats for Q31 CIFFT"   
+ *   
+ */
+
+void arm_cfft_radix4_q31(
+  const arm_cfft_radix4_instance_q31 * S,
+  q31_t * pSrc)
+{
+  if(S->ifftFlag == 1u)
+  {
+    /* Complex IFFT radix-4 */
+    arm_radix4_butterfly_inverse_q31(pSrc, S->fftLen, S->pTwiddle,
+                                     S->twidCoefModifier);
+  }
+  else
+  {
+    /* Complex FFT radix-4 */
+    arm_radix4_butterfly_q31(pSrc, S->fftLen, S->pTwiddle,
+                             S->twidCoefModifier);
+  }
+
+
+  if(S->bitReverseFlag == 1u)
+  {
+    /*  Bit Reversal */
+    arm_bitreversal_q31(pSrc, S->fftLen, S->bitRevFactor, S->pBitRevTable);
+  }
+
+}
+
+/**   
+ * @} end of CFFT_CIFFT group   
+ */
+
+/*   
+* Radix-4 FFT algorithm used is :   
+*   
+* Input real and imaginary data:   
+* x(n) = xa + j * ya   
+* x(n+N/4 ) = xb + j * yb   
+* x(n+N/2 ) = xc + j * yc   
+* x(n+3N 4) = xd + j * yd   
+*   
+*   
+* Output real and imaginary data:   
+* x(4r) = xa'+ j * ya'   
+* x(4r+1) = xb'+ j * yb'   
+* x(4r+2) = xc'+ j * yc'   
+* x(4r+3) = xd'+ j * yd'   
+*   
+*   
+* Twiddle factors for radix-4 FFT:   
+* Wn = co1 + j * (- si1)   
+* W2n = co2 + j * (- si2)   
+* W3n = co3 + j * (- si3)   
+*   
+*  Butterfly implementation:   
+* xa' = xa + xb + xc + xd   
+* ya' = ya + yb + yc + yd   
+* xb' = (xa+yb-xc-yd)* co1 + (ya-xb-yc+xd)* (si1)   
+* yb' = (ya-xb-yc+xd)* co1 - (xa+yb-xc-yd)* (si1)   
+* xc' = (xa-xb+xc-xd)* co2 + (ya-yb+yc-yd)* (si2)   
+* yc' = (ya-yb+yc-yd)* co2 - (xa-xb+xc-xd)* (si2)   
+* xd' = (xa-yb-xc+yd)* co3 + (ya+xb-yc-xd)* (si3)   
+* yd' = (ya+xb-yc-xd)* co3 - (xa-yb-xc+yd)* (si3)   
+*   
+*/
+
+/**   
+ * @brief  Core function for the Q31 CFFT butterfly process.  
+ * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.  
+ * @param[in]      fftLen           length of the FFT.  
+ * @param[in]      *pCoef           points to twiddle coefficient buffer.  
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.  
+ */
+
+void arm_radix4_butterfly_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint32_t twidCoefModifier)
+{
+  uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
+  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+
+
+  /* Total process is divided into three stages */
+
+  /* process first stage, middle stages, & last stage */
+
+
+  /* start of first stage process */
+
+  /*  Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+  i0 = 0u;
+  ia1 = 0u;
+
+  j = n2;
+
+  /*  Calculation of first stage */
+  do
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = (pSrc[(2u * i0)] >> 4u) + (pSrc[(2u * i2)] >> 4u);
+    /* xa - xc */
+    r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
+
+    /* ya + yc */
+    s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
+    /* ya - yc */
+    s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
+
+    /* xb + xd */
+    t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1);
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+    /* yb + yd */
+    t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2);
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
+    /* xb - xd */
+    t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
+
+    /*  index calculation for the coefficients */
+    ia2 = 2u * ia1;
+    co2 = pCoef[ia2 * 2u];
+    si2 = pCoef[(ia2 * 2u) + 1u];
+
+    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
+
+    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+                            ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
+
+    /* (xa - xc) + (yb - yd) */
+    r1 = r2 + t1;
+    /* (xa - xc) - (yb - yd) */
+    r2 = r2 - t1;
+
+    /* (ya - yc) - (xb - xd) */
+    s1 = s2 - t2;
+    /* (ya - yc) + (xb - xd) */
+    s2 = s2 + t2;
+
+    co1 = pCoef[ia1 * 2u];
+    si1 = pCoef[(ia1 * 2u) + 1u];
+
+    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
+
+    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
+
+    /*  index calculation for the coefficients */
+    ia3 = 3u * ia1;
+    co3 = pCoef[ia3 * 2u];
+    si3 = pCoef[(ia3 * 2u) + 1u];
+
+    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
+
+    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+
+  /* end of first stage process */
+
+  /* data is in 5.27(q27) format */
+
+
+  /* start of Middle stages process */
+
+
+  /* each stage in middle stages provides two down scaling of the input */
+
+  twidCoefModifier <<= 2u;
+
+
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    /*  Calculation of first stage */
+    for (j = 0u; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Butterfly implementation */
+        /* xa + xc */
+        r1 = pSrc[2u * i0] + pSrc[2u * i2];
+        /* xa - xc */
+        r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = (r1 + t1) >> 2u;
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) +
+                         ((int32_t) (((q63_t) s1 * si2) >> 32))) >> 1u;
+
+        /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) -
+                                ((int32_t) (((q63_t) r1 * si2) >> 32))) >> 1u;
+
+        /* (xa - xc) + (yb - yd) */
+        r1 = r2 + t1;
+        /* (xa - xc) - (yb - yd) */
+        r2 = r2 - t1;
+
+        /* (ya - yc) -  (xb - xd) */
+        s1 = s2 - t2;
+        /* (ya - yc) +  (xb - xd) */
+        s2 = s2 + t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) +
+                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
+
+        /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) -
+                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
+
+        /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+        pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) +
+                         ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
+
+        /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) -
+                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+
+  /* End of Middle stages process */
+
+  /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
+  /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
+  /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
+  /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
+
+
+  /* start of Last stage process */
+
+  /*  Initializations of last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Calculations of last stage */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xb */
+    r1 = pSrc[2u * i0] + pSrc[2u * i2];
+    /* xa - xb */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xc + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1);
+    /* (xa + xb) - (xc + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2);
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* (yb-yd) */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+    /* (xb-xd) */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /* xc' = (xa-xb+xc-xd)co2 + (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = r1;
+    /* yc' = (ya-yb+yc-yd)co2 - (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = s1;
+
+    /* (xa+yb-xc-yd) */
+    r1 = r2 + t1;
+    /* (xa-yb-xc+yd) */
+    r2 = r2 - t1;
+
+    /* (ya-xb-yc+xd) */
+    s1 = s2 - t2;
+    /* (ya+xb-yc-xd) */
+    s2 = s2 + t2;
+
+    /* xb' = (xa+yb-xc-yd)co1 + (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = r1;
+    /* yb' = (ya-xb-yc+xd)co1 - (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = s1;
+
+    /* xd' = (xa-yb-xc+yd)co3 + (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = r2;
+    /* yd' = (ya+xb-yc-xd)co3 - (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = s2;
+
+
+  }
+
+  /* output is in 11.21(q21) format for the 1024 point */
+  /* output is in 9.23(q23) format for the 256 point */
+  /* output is in 7.25(q25) format for the 64 point */
+  /* output is in 5.27(q27) format for the 16 point */
+
+  /* End of last stage process */
+
+}
+
+
+/**   
+ * @brief  Core function for the Q31 CIFFT butterfly process.  
+ * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.  
+ * @param[in]      fftLen           length of the FFT.  
+ * @param[in]      *pCoef           points to twiddle coefficient buffer.  
+ * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.  
+ */
+
+
+/*   
+* Radix-4 IFFT algorithm used is :   
+*   
+* CIFFT uses same twiddle coefficients as CFFT Function   
+*  x[k] = x[n] + (j)k * x[n + fftLen/4] + (-1)k * x[n+fftLen/2] + (-j)k * x[n+3*fftLen/4]   
+*   
+*   
+* IFFT is implemented with following changes in equations from FFT   
+*   
+* Input real and imaginary data:   
+* x(n) = xa + j * ya   
+* x(n+N/4 ) = xb + j * yb   
+* x(n+N/2 ) = xc + j * yc   
+* x(n+3N 4) = xd + j * yd   
+*   
+*   
+* Output real and imaginary data:   
+* x(4r) = xa'+ j * ya'   
+* x(4r+1) = xb'+ j * yb'   
+* x(4r+2) = xc'+ j * yc'   
+* x(4r+3) = xd'+ j * yd'   
+*   
+*   
+* Twiddle factors for radix-4 IFFT:   
+* Wn = co1 + j * (si1)   
+* W2n = co2 + j * (si2)   
+* W3n = co3 + j * (si3)   
+   
+* The real and imaginary output values for the radix-4 butterfly are   
+* xa' = xa + xb + xc + xd   
+* ya' = ya + yb + yc + yd   
+* xb' = (xa-yb-xc+yd)* co1 - (ya+xb-yc-xd)* (si1)   
+* yb' = (ya+xb-yc-xd)* co1 + (xa-yb-xc+yd)* (si1)   
+* xc' = (xa-xb+xc-xd)* co2 - (ya-yb+yc-yd)* (si2)   
+* yc' = (ya-yb+yc-yd)* co2 + (xa-xb+xc-xd)* (si2)   
+* xd' = (xa+yb-xc-yd)* co3 - (ya-xb-yc+xd)* (si3)   
+* yd' = (ya-xb-yc+xd)* co3 + (xa+yb-xc-yd)* (si3)   
+*   
+*/
+
+void arm_radix4_butterfly_inverse_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pCoef,
+  uint32_t twidCoefModifier)
+{
+  uint32_t n1, n2, ia1, ia2, ia3, i0, i1, i2, i3, j, k;
+  q31_t t1, t2, r1, r2, s1, s2, co1, co2, co3, si1, si2, si3;
+
+  /* input is be 1.31(q31) format for all FFT sizes */
+  /* Total process is divided into three stages */
+  /* process first stage, middle stages, & last stage */
+
+  /* Start of first stage process */
+
+  /* Initializations for the first stage */
+  n2 = fftLen;
+  n1 = n2;
+  /* n2 = fftLen/4 */
+  n2 >>= 2u;
+  i0 = 0u;
+  ia1 = 0u;
+
+  j = n2;
+
+  do
+  {
+
+    /* input is in 1.31(q31) format and provide 4 guard bits for the input */
+
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = (pSrc[2u * i0] >> 4u) + (pSrc[2u * i2] >> 4u);
+    /* xa - xc */
+    r2 = (pSrc[2u * i0] >> 4u) - (pSrc[2u * i2] >> 4u);
+
+    /* ya + yc */
+    s1 = (pSrc[(2u * i0) + 1u] >> 4u) + (pSrc[(2u * i2) + 1u] >> 4u);
+    /* ya - yc */
+    s2 = (pSrc[(2u * i0) + 1u] >> 4u) - (pSrc[(2u * i2) + 1u] >> 4u);
+
+    /* xb + xd */
+    t1 = (pSrc[2u * i1] >> 4u) + (pSrc[2u * i3] >> 4u);
+
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1);
+    /* (xa + xc) - (xb + xd) */
+    r1 = r1 - t1;
+    /* yb + yd */
+    t2 = (pSrc[(2u * i1) + 1u] >> 4u) + (pSrc[(2u * i3) + 1u] >> 4u);
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2);
+
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* yb - yd */
+    t1 = (pSrc[(2u * i1) + 1u] >> 4u) - (pSrc[(2u * i3) + 1u] >> 4u);
+    /* xb - xd */
+    t2 = (pSrc[2u * i1] >> 4u) - (pSrc[2u * i3] >> 4u);
+
+    /*  index calculation for the coefficients */
+    ia2 = 2u * ia1;
+    co2 = pCoef[ia2 * 2u];
+    si2 = pCoef[(ia2 * 2u) + 1u];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32)) -
+                     ((int32_t) (((q63_t) s1 * si2) >> 32))) << 1u;
+
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    pSrc[2u * i1 + 1u] = (((int32_t) (((q63_t) s1 * co2) >> 32)) +
+                          ((int32_t) (((q63_t) r1 * si2) >> 32))) << 1u;
+
+    /* (xa - xc) - (yb - yd) */
+    r1 = r2 - t1;
+    /* (xa - xc) + (yb - yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb - xd) */
+    s1 = s2 + t2;
+    /* (ya - yc) - (xb - xd) */
+    s2 = s2 - t2;
+
+    co1 = pCoef[ia1 * 2u];
+    si1 = pCoef[(ia1 * 2u) + 1u];
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+                     ((int32_t) (((q63_t) s1 * si1) >> 32))) << 1u;
+
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+                            ((int32_t) (((q63_t) r1 * si1) >> 32))) << 1u;
+
+    /*  index calculation for the coefficients */
+    ia3 = 3u * ia1;
+    co3 = pCoef[ia3 * 2u];
+    si3 = pCoef[(ia3 * 2u) + 1u];
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+                     ((int32_t) (((q63_t) s2 * si3) >> 32))) << 1u;
+
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+                            ((int32_t) (((q63_t) r2 * si3) >> 32))) << 1u;
+
+    /*  Twiddle coefficients index modifier */
+    ia1 = ia1 + twidCoefModifier;
+
+    /*  Updating input index */
+    i0 = i0 + 1u;
+
+  } while(--j);
+
+  /* data is in 5.27(q27) format */
+  /* each stage provides two down scaling of the input */
+
+
+  /* Start of Middle stages process */
+
+  twidCoefModifier <<= 2u;
+
+  /*  Calculation of second stage to excluding last stage */
+  for (k = fftLen / 4u; k > 4u; k >>= 2u)
+  {
+    /*  Initializations for the first stage */
+    n1 = n2;
+    n2 >>= 2u;
+    ia1 = 0u;
+
+    for (j = 0; j <= (n2 - 1u); j++)
+    {
+      /*  index calculation for the coefficients */
+      ia2 = ia1 + ia1;
+      ia3 = ia2 + ia1;
+      co1 = pCoef[ia1 * 2u];
+      si1 = pCoef[(ia1 * 2u) + 1u];
+      co2 = pCoef[ia2 * 2u];
+      si2 = pCoef[(ia2 * 2u) + 1u];
+      co3 = pCoef[ia3 * 2u];
+      si3 = pCoef[(ia3 * 2u) + 1u];
+      /*  Twiddle coefficients index modifier */
+      ia1 = ia1 + twidCoefModifier;
+
+      for (i0 = j; i0 < fftLen; i0 += n1)
+      {
+        /*  index calculation for the input as, */
+        /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+        i1 = i0 + n2;
+        i2 = i1 + n2;
+        i3 = i2 + n2;
+
+        /*  Butterfly implementation */
+        /* xa + xc */
+        r1 = pSrc[2u * i0] + pSrc[2u * i2];
+        /* xa - xc */
+        r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+        /* ya + yc */
+        s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+        /* ya - yc */
+        s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+        /* xb + xd */
+        t1 = pSrc[2u * i1] + pSrc[2u * i3];
+
+        /* xa' = xa + xb + xc + xd */
+        pSrc[2u * i0] = (r1 + t1) >> 2u;
+        /* xa + xc -(xb + xd) */
+        r1 = r1 - t1;
+        /* yb + yd */
+        t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+        /* ya' = ya + yb + yc + yd */
+        pSrc[(2u * i0) + 1u] = (s1 + t2) >> 2u;
+
+        /* (ya + yc) - (yb + yd) */
+        s1 = s1 - t2;
+
+        /* (yb - yd) */
+        t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+        /* (xb - xd) */
+        t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+        /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+        pSrc[2u * i1] = (((int32_t) (((q63_t) r1 * co2) >> 32u)) -
+                         ((int32_t) (((q63_t) s1 * si2) >> 32u))) >> 1u;
+
+        /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+        pSrc[(2u * i1) + 1u] =
+          (((int32_t) (((q63_t) s1 * co2) >> 32u)) +
+           ((int32_t) (((q63_t) r1 * si2) >> 32u))) >> 1u;
+
+        /* (xa - xc) - (yb - yd) */
+        r1 = r2 - t1;
+        /* (xa - xc) + (yb - yd) */
+        r2 = r2 + t1;
+
+        /* (ya - yc) +  (xb - xd) */
+        s1 = s2 + t2;
+        /* (ya - yc) -  (xb - xd) */
+        s2 = s2 - t2;
+
+        /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+        pSrc[2u * i2] = (((int32_t) (((q63_t) r1 * co1) >> 32)) -
+                         ((int32_t) (((q63_t) s1 * si1) >> 32))) >> 1u;
+
+        /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+        pSrc[(2u * i2) + 1u] = (((int32_t) (((q63_t) s1 * co1) >> 32)) +
+                                ((int32_t) (((q63_t) r1 * si1) >> 32))) >> 1u;
+
+        /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+        pSrc[(2u * i3)] = (((int32_t) (((q63_t) r2 * co3) >> 32)) -
+                           ((int32_t) (((q63_t) s2 * si3) >> 32))) >> 1u;
+
+        /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+        pSrc[(2u * i3) + 1u] = (((int32_t) (((q63_t) s2 * co3) >> 32)) +
+                                ((int32_t) (((q63_t) r2 * si3) >> 32))) >> 1u;
+      }
+    }
+    twidCoefModifier <<= 2u;
+  }
+
+  /* End of Middle stages process */
+
+  /* data is in 11.21(q21) format for the 1024 point as there are 3 middle stages */
+  /* data is in 9.23(q23) format for the 256 point as there are 2 middle stages */
+  /* data is in 7.25(q25) format for the 64 point as there are 1 middle stage */
+  /* data is in 5.27(q27) format for the 16 point as there are no middle stages */
+
+
+  /* Start of last stage process */
+
+
+  /*  Initializations of last stage */
+  n1 = n2;
+  n2 >>= 2u;
+
+  /*  Calculations of last stage */
+  for (i0 = 0u; i0 <= (fftLen - n1); i0 += n1)
+  {
+    /*  index calculation for the input as, */
+    /*  pSrc[i0 + 0], pSrc[i0 + fftLen/4], pSrc[i0 + fftLen/2u], pSrc[i0 + 3fftLen/4] */
+    i1 = i0 + n2;
+    i2 = i1 + n2;
+    i3 = i2 + n2;
+
+    /*  Butterfly implementation */
+    /* xa + xc */
+    r1 = pSrc[2u * i0] + pSrc[2u * i2];
+    /* xa - xc */
+    r2 = pSrc[2u * i0] - pSrc[2u * i2];
+
+    /* ya + yc */
+    s1 = pSrc[(2u * i0) + 1u] + pSrc[(2u * i2) + 1u];
+    /* ya - yc */
+    s2 = pSrc[(2u * i0) + 1u] - pSrc[(2u * i2) + 1u];
+
+    /* xc + xd */
+    t1 = pSrc[2u * i1] + pSrc[2u * i3];
+    /* xa' = xa + xb + xc + xd */
+    pSrc[2u * i0] = (r1 + t1);
+    /* (xa + xb) - (xc + xd) */
+    r1 = r1 - t1;
+
+    /* yb + yd */
+    t2 = pSrc[(2u * i1) + 1u] + pSrc[(2u * i3) + 1u];
+    /* ya' = ya + yb + yc + yd */
+    pSrc[(2u * i0) + 1u] = (s1 + t2);
+    /* (ya + yc) - (yb + yd) */
+    s1 = s1 - t2;
+
+    /* (yb-yd) */
+    t1 = pSrc[(2u * i1) + 1u] - pSrc[(2u * i3) + 1u];
+    /* (xb-xd) */
+    t2 = pSrc[2u * i1] - pSrc[2u * i3];
+
+    /* xc' = (xa-xb+xc-xd)co2 - (ya-yb+yc-yd)(si2) */
+    pSrc[2u * i1] = r1;
+    /* yc' = (ya-yb+yc-yd)co2 + (xa-xb+xc-xd)(si2) */
+    pSrc[(2u * i1) + 1u] = s1;
+
+    /* (xa - xc) - (yb-yd) */
+    r1 = r2 - t1;
+
+    /* (xa - xc) + (yb-yd) */
+    r2 = r2 + t1;
+
+    /* (ya - yc) + (xb-xd) */
+    s1 = s2 + t2;
+
+    /* (ya - yc) - (xb-xd) */
+    s2 = s2 - t2;
+
+    /* xb' = (xa+yb-xc-yd)co1 - (ya-xb-yc+xd)(si1) */
+    pSrc[2u * i2] = r1;
+    /* yb' = (ya-xb-yc+xd)co1 + (xa+yb-xc-yd)(si1) */
+    pSrc[(2u * i2) + 1u] = s1;
+
+    /* xd' = (xa-yb-xc+yd)co3 - (ya+xb-yc-xd)(si3) */
+    pSrc[2u * i3] = r2;
+    /* yd' = (ya+xb-yc-xd)co3 + (xa-yb-xc+yd)(si3) */
+    pSrc[(2u * i3) + 1u] = s2;
+
+  }
+
+  /* output is in 11.21(q21) format for the 1024 point */
+  /* output is in 9.23(q23) format for the 256 point */
+  /* output is in 7.25(q25) format for the 64 point */
+  /* output is in 5.27(q27) format for the 16 point */
+
+  /* End of last stage process */
+}
+
+
+/*   
+ * @brief  In-place bit reversal function.  
+ * @param[in, out] *pSrc        points to the in-place buffer of Q31 data type.  
+ * @param[in]      fftLen       length of the FFT.  
+ * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table  
+ * @param[in]      *pBitRevTab  points to bit reversal table.  
+ * @return none.  
+ */
+
+void arm_bitreversal_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  uint16_t bitRevFactor,
+  uint16_t * pBitRevTable)
+{
+  uint32_t fftLenBy2, fftLenBy2p1, i, j;
+  q31_t in;
+
+  /*  Initializations      */
+  j = 0u;
+  fftLenBy2 = fftLen / 2u;
+  fftLenBy2p1 = (fftLen / 2u) + 1u;
+
+  /* Bit Reversal Implementation */
+  for (i = 0u; i <= (fftLenBy2 - 2u); i += 2u)
+  {
+    if(i < j)
+    {
+      /*  pSrc[i] <-> pSrc[j]; */
+      in = pSrc[2u * i];
+      pSrc[2u * i] = pSrc[2u * j];
+      pSrc[2u * j] = in;
+
+      /*  pSrc[i+1u] <-> pSrc[j+1u] */
+      in = pSrc[(2u * i) + 1u];
+      pSrc[(2u * i) + 1u] = pSrc[(2u * j) + 1u];
+      pSrc[(2u * j) + 1u] = in;
+
+      /*  pSrc[i+fftLenBy2p1] <-> pSrc[j+fftLenBy2p1] */
+      in = pSrc[2u * (i + fftLenBy2p1)];
+      pSrc[2u * (i + fftLenBy2p1)] = pSrc[2u * (j + fftLenBy2p1)];
+      pSrc[2u * (j + fftLenBy2p1)] = in;
+
+      /*  pSrc[i+fftLenBy2p1+1u] <-> pSrc[j+fftLenBy2p1+1u] */
+      in = pSrc[(2u * (i + fftLenBy2p1)) + 1u];
+      pSrc[(2u * (i + fftLenBy2p1)) + 1u] =
+        pSrc[(2u * (j + fftLenBy2p1)) + 1u];
+      pSrc[(2u * (j + fftLenBy2p1)) + 1u] = in;
+
+    }
+
+    /*  pSrc[i+1u] <-> pSrc[j+1u] */
+    in = pSrc[2u * (i + 1u)];
+    pSrc[2u * (i + 1u)] = pSrc[2u * (j + fftLenBy2)];
+    pSrc[2u * (j + fftLenBy2)] = in;
+
+    /*  pSrc[i+2u] <-> pSrc[j+2u] */
+    in = pSrc[(2u * (i + 1u)) + 1u];
+    pSrc[(2u * (i + 1u)) + 1u] = pSrc[(2u * (j + fftLenBy2)) + 1u];
+    pSrc[(2u * (j + fftLenBy2)) + 1u] = in;
+
+    /*  Reading the index for the bit reversal */
+    j = *pBitRevTable;
+
+    /*  Updating the bit reversal index depending on the fft length */
+    pBitRevTable += bitRevFactor;
+  }
+}
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c
new file mode 100644
index 0000000000..2e94a19ab3
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c
@@ -0,0 +1,450 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_dct4_f32.c   
+*   
+* Description:	Processing function of DCT4 & IDCT4 F32.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @defgroup DCT4_IDCT4 DCT Type IV Functions   
+ * Representation of signals by minimum number of values is important for storage and transmission.   
+ * The possibility of large discontinuity between the beginning and end of a period of a signal   
+ * in DFT can be avoided by extending the signal so that it is even-symmetric.   
+ * Discrete Cosine Transform (DCT) is constructed such that its energy is heavily concentrated in the lower part of the   
+ * spectrum and is very widely used in signal and image coding applications.   
+ * The family of DCTs (DCT type- 1,2,3,4) is the outcome of different combinations of homogeneous boundary conditions.   
+ * DCT has an excellent energy-packing capability, hence has many applications and in data compression in particular.   
+ *   
+ * DCT is essentially the Discrete Fourier Transform(DFT) of an even-extended real signal.   
+ * Reordering of the input data makes the computation of DCT just a problem of   
+ * computing the DFT of a real signal with a few additional operations.   
+ * This approach provides regular, simple, and very efficient DCT algorithms for practical hardware and software implementations.   
+ *    
+ * DCT type-II can be implemented using Fast fourier transform (FFT) internally, as the transform is applied on real values, Real FFT can be used.   
+ * DCT4 is implemented using DCT2 as their implementations are similar except with some added pre-processing and post-processing.   
+ * DCT2 implementation can be described in the following steps:   
+ * - Re-ordering input   
+ * - Calculating Real FFT   
+ * - Multiplication of weights and Real FFT output and getting real part from the product.   
+ *   
+ * This process is explained by the block diagram below:   
+ * \image html DCT4.gif "Discrete Cosine Transform - type-IV"   
+ *   
+ * \par Algorithm:   
+ * The N-point type-IV DCT is defined as a real, linear transformation by the formula:   
+ * \image html DCT4Equation.gif   
+ * where k = 0,1,2,.....N-1   
+ *\par   
+ * Its inverse is defined as follows:   
+ * \image html IDCT4Equation.gif   
+ * where n = 0,1,2,.....N-1   
+ *\par   
+ * The DCT4 matrices become involutory (i.e. they are self-inverse) by multiplying with an overall scale factor of sqrt(2/N).   
+ * The symmetry of the transform matrix indicates that the fast algorithms for the forward   
+ * and inverse transform computation are identical.   
+ * Note that the implementation of Inverse DCT4 and DCT4 is same, hence same process function can be used for both.   
+ *   
+ * \par Lengths supported by the transform:   
+ *  As DCT4 internally uses Real FFT, it supports all the lengths supported by arm_rfft_f32().   
+ * The library provides separate functions for Q15, Q31, and floating-point data types.   
+ * \par Instance Structure   
+ * The instances for Real FFT and FFT, cosine values table and twiddle factor table are stored in an instance data structure.   
+ * A separate instance structure must be defined for each transform.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Initializes Real FFT as its process function is used internally in DCT4, by calling arm_rfft_init_f32().   
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Manually initialize the instance structure as follows:   
+ * 
       
+ *arm_dct4_instance_f32 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};   
+ *arm_dct4_instance_q31 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};  
+ *arm_dct4_instance_q15 S = {N, Nby2, normalize, pTwiddle, pCosFactor, pRfft, pCfft};  
+ * 
      
+ * where \c N is the length of the DCT4; \c Nby2 is half of the length of the DCT4;  
+ * \c normalize is normalizing factor used and is equal to sqrt(2/N);   
+ * \c pTwiddle points to the twiddle factor table;  
+ * \c pCosFactor points to the cosFactor table;  
+ * \c pRfft points to the real FFT instance;  
+ * \c pCfft points to the complex FFT instance;  
+ * The CFFT and RFFT structures also needs to be initialized, refer to arm_cfft_radix4_f32()  
+ * and arm_rfft_f32() respectively for details regarding static initialization.  
+ *  
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the DCT4 transform functions.   
+ * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+ /**   
+ * @addtogroup DCT4_IDCT4   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the floating-point DCT4/IDCT4.  
+ * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.  
+ * @param[in]       *pState        points to state buffer.  
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.  
+ * @return none.  
+ */
+
+void arm_dct4_f32(
+  const arm_dct4_instance_f32 * S,
+  float32_t * pState,
+  float32_t * pInlineBuffer)
+{
+  uint32_t i;                                    /* Loop counter */
+  float32_t *weights = S->pTwiddle;              /* Pointer to the Weights table */
+  float32_t *cosFact = S->pCosFactor;            /* Pointer to the cos factors table */
+  float32_t *pS1, *pS2, *pbuff;                  /* Temporary pointers for input buffer and pState buffer */
+  float32_t in;                                  /* Temporary variable */
+
+
+  /* DCT4 computation involves DCT2 (which is calculated using RFFT)   
+   * along with some pre-processing and post-processing.   
+   * Computational procedure is explained as follows:   
+   * (a) Pre-processing involves multiplying input with cos factor,   
+   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))   
+   *              where,   
+   *                 r(n) -- output of preprocessing   
+   *                 u(n) -- input to preprocessing(actual Source buffer)   
+   * (b) Calculation of DCT2 using FFT is divided into three steps:   
+   *                  Step1: Re-ordering of even and odd elements of input.   
+   *                  Step2: Calculating FFT of the re-ordered input.   
+   *                  Step3: Taking the real part of the product of FFT output and weights.   
+   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:   
+   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *                        where,   
+   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output   
+   * (d) Multiplying the output with the normalizing factor sqrt(2/N).   
+   */
+
+        /*-------- Pre-processing ------------*/
+  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+  arm_scale_f32(pInlineBuffer, 2.0f, pInlineBuffer, S->N);
+  arm_mult_f32(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+
+  /* ----------------------------------------------------------------   
+   * Step1: Re-ordering of even and odd elements as,   
+   *             pState[i] =  pInlineBuffer[2*i] and   
+   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2   
+   ---------------------------------------------------------------------*/
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+  pS2 = pState + (S->N - 1u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+  i = (uint32_t) S->Nby2 >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2u;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.   
+   * Compute 4 outputs at a time */
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------   
+   *     Step2: Calculate RFFT for N-point input   
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
+
+        /*----------------------------------------------------------------------   
+	 *  Step3: Multiply the FFT output with the weights.   
+	 *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,   
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+  i = ((uint32_t) S->N - 1u) >> 2u;
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ * (float32_t) 0.5;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  i = ((uint32_t) S->N - 1u) % 0x4u;
+
+  while(i > 0u)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2u;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initializing the loop counter to N/2 */
+  i = (uint32_t) S->Nby2;
+
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------   
+   *     Step2: Calculate RFFT for N-point input   
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_f32(S->pRfft, pInlineBuffer, pState);
+
+        /*----------------------------------------------------------------------   
+	 *  Step3: Multiply the FFT output with the weights.   
+	 *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_f32(pState, weights, pState, S->N);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,   
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ * (float32_t) 0.5;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* Initializing the loop counter */
+  i = ((uint32_t) S->N - 1u);
+
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = in * S->normalize;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of DCT4_IDCT4 group   
+   */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c
new file mode 100644
index 0000000000..5c55d35796
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c
@@ -0,0 +1,4208 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_dct4_init_f32.c   
+*   
+* Description:	Initialization function of DCT-4 & IDCT4 F32   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup DCT4_IDCT4   
+ * @{   
+ */
+
+/*   
+* @brief  Weights Table   
+*/
+
+/**   
+* \par   
+* Weights tables are generated using the formula : 
    weights[n] = e^(-j*n*pi/(2*N))
       
+* \par   
+* C command to generate the table   
+* 
       
+* for(i = 0; i< N; i++)   
+* {   
+*    weights[2*i]= cos(i*c);   
+*    weights[(2*i)+1]= -sin(i * c);   
+* } 
       
+* \par   
+* Where N is the Number of weights to be calculated and c is pi/(2*N)   
+* \par   
+* In the tables below the real and imaginary values are placed alternatively, hence the   
+* array length is 2*N.   
+*/
+
+static const float32_t Weights_128[256] = {
+  1.000000000000000000f, 0.000000000000000000f, 0.999924701839144500f,
+  -0.012271538285719925f,
+  0.999698818696204250f, -0.024541228522912288f, 0.999322384588349540f,
+  -0.036807222941358832f,
+  0.998795456205172410f, -0.049067674327418015f, 0.998118112900149180f,
+  -0.061320736302208578f,
+  0.997290456678690210f, -0.073564563599667426f, 0.996312612182778000f,
+  -0.085797312344439894f,
+  0.995184726672196930f, -0.098017140329560604f, 0.993906970002356060f,
+  -0.110222207293883060f,
+  0.992479534598709970f, -0.122410675199216200f, 0.990902635427780010f,
+  -0.134580708507126170f,
+  0.989176509964781010f, -0.146730474455361750f, 0.987301418157858430f,
+  -0.158858143333861450f,
+  0.985277642388941220f, -0.170961888760301220f, 0.983105487431216290f,
+  -0.183039887955140950f,
+  0.980785280403230430f, -0.195090322016128250f, 0.978317370719627650f,
+  -0.207111376192218560f,
+  0.975702130038528570f, -0.219101240156869800f, 0.972939952205560180f,
+  -0.231058108280671110f,
+  0.970031253194543970f, -0.242980179903263870f, 0.966976471044852070f,
+  -0.254865659604514570f,
+  0.963776065795439840f, -0.266712757474898370f, 0.960430519415565790f,
+  -0.278519689385053060f,
+  0.956940335732208820f, -0.290284677254462330f, 0.953306040354193860f,
+  -0.302005949319228080f,
+  0.949528180593036670f, -0.313681740398891520f, 0.945607325380521280f,
+  -0.325310292162262930f,
+  0.941544065183020810f, -0.336889853392220050f, 0.937339011912574960f,
+  -0.348418680249434560f,
+  0.932992798834738960f, -0.359895036534988110f, 0.928506080473215590f,
+  -0.371317193951837540f,
+  0.923879532511286740f, -0.382683432365089780f, 0.919113851690057770f,
+  -0.393992040061048100f,
+  0.914209755703530690f, -0.405241314004989860f, 0.909167983090522380f,
+  -0.416429560097637150f,
+  0.903989293123443340f, -0.427555093430282080f, 0.898674465693953820f,
+  -0.438616238538527660f,
+  0.893224301195515320f, -0.449611329654606540f, 0.887639620402853930f,
+  -0.460538710958240010f,
+  0.881921264348355050f, -0.471396736825997640f, 0.876070094195406600f,
+  -0.482183772079122720f,
+  0.870086991108711460f, -0.492898192229784040f, 0.863972856121586810f,
+  -0.503538383725717580f,
+  0.857728610000272120f, -0.514102744193221660f, 0.851355193105265200f,
+  -0.524589682678468950f,
+  0.844853565249707120f, -0.534997619887097150f, 0.838224705554838080f,
+  -0.545324988422046460f,
+  0.831469612302545240f, -0.555570233019602180f, 0.824589302785025290f,
+  -0.565731810783613120f,
+  0.817584813151583710f, -0.575808191417845340f, 0.810457198252594770f,
+  -0.585797857456438860f,
+  0.803207531480644940f, -0.595699304492433360f, 0.795836904608883570f,
+  -0.605511041404325550f,
+  0.788346427626606340f, -0.615231590580626820f, 0.780737228572094490f,
+  -0.624859488142386340f,
+  0.773010453362736990f, -0.634393284163645490f, 0.765167265622458960f,
+  -0.643831542889791390f,
+  0.757208846506484570f, -0.653172842953776760f, 0.749136394523459370f,
+  -0.662415777590171780f,
+  0.740951125354959110f, -0.671558954847018330f, 0.732654271672412820f,
+  -0.680600997795453020f,
+  0.724247082951467000f, -0.689540544737066830f, 0.715730825283818590f,
+  -0.698376249408972920f,
+  0.707106781186547570f, -0.707106781186547460f, 0.698376249408972920f,
+  -0.715730825283818590f,
+  0.689540544737066940f, -0.724247082951466890f, 0.680600997795453130f,
+  -0.732654271672412820f,
+  0.671558954847018330f, -0.740951125354959110f, 0.662415777590171780f,
+  -0.749136394523459260f,
+  0.653172842953776760f, -0.757208846506484460f, 0.643831542889791500f,
+  -0.765167265622458960f,
+  0.634393284163645490f, -0.773010453362736990f, 0.624859488142386450f,
+  -0.780737228572094380f,
+  0.615231590580626820f, -0.788346427626606230f, 0.605511041404325550f,
+  -0.795836904608883460f,
+  0.595699304492433470f, -0.803207531480644830f, 0.585797857456438860f,
+  -0.810457198252594770f,
+  0.575808191417845340f, -0.817584813151583710f, 0.565731810783613230f,
+  -0.824589302785025290f,
+  0.555570233019602290f, -0.831469612302545240f, 0.545324988422046460f,
+  -0.838224705554837970f,
+  0.534997619887097260f, -0.844853565249707010f, 0.524589682678468840f,
+  -0.851355193105265200f,
+  0.514102744193221660f, -0.857728610000272120f, 0.503538383725717580f,
+  -0.863972856121586700f,
+  0.492898192229784090f, -0.870086991108711350f, 0.482183772079122830f,
+  -0.876070094195406600f,
+  0.471396736825997810f, -0.881921264348354940f, 0.460538710958240010f,
+  -0.887639620402853930f,
+  0.449611329654606600f, -0.893224301195515320f, 0.438616238538527710f,
+  -0.898674465693953820f,
+  0.427555093430282200f, -0.903989293123443340f, 0.416429560097637320f,
+  -0.909167983090522270f,
+  0.405241314004989860f, -0.914209755703530690f, 0.393992040061048100f,
+  -0.919113851690057770f,
+  0.382683432365089840f, -0.923879532511286740f, 0.371317193951837600f,
+  -0.928506080473215480f,
+  0.359895036534988280f, -0.932992798834738850f, 0.348418680249434510f,
+  -0.937339011912574960f,
+  0.336889853392220050f, -0.941544065183020810f, 0.325310292162262980f,
+  -0.945607325380521280f,
+  0.313681740398891570f, -0.949528180593036670f, 0.302005949319228200f,
+  -0.953306040354193750f,
+  0.290284677254462330f, -0.956940335732208940f, 0.278519689385053060f,
+  -0.960430519415565790f,
+  0.266712757474898420f, -0.963776065795439840f, 0.254865659604514630f,
+  -0.966976471044852070f,
+  0.242980179903263980f, -0.970031253194543970f, 0.231058108280671280f,
+  -0.972939952205560070f,
+  0.219101240156869770f, -0.975702130038528570f, 0.207111376192218560f,
+  -0.978317370719627650f,
+  0.195090322016128330f, -0.980785280403230430f, 0.183039887955141060f,
+  -0.983105487431216290f,
+  0.170961888760301360f, -0.985277642388941220f, 0.158858143333861390f,
+  -0.987301418157858430f,
+  0.146730474455361750f, -0.989176509964781010f, 0.134580708507126220f,
+  -0.990902635427780010f,
+  0.122410675199216280f, -0.992479534598709970f, 0.110222207293883180f,
+  -0.993906970002356060f,
+  0.098017140329560770f, -0.995184726672196820f, 0.085797312344439880f,
+  -0.996312612182778000f,
+  0.073564563599667454f, -0.997290456678690210f, 0.061320736302208648f,
+  -0.998118112900149180f,
+  0.049067674327418126f, -0.998795456205172410f, 0.036807222941358991f,
+  -0.999322384588349540f,
+  0.024541228522912264f, -0.999698818696204250f, 0.012271538285719944f,
+  -0.999924701839144500f
+};
+
+static const float32_t Weights_512[1024] = {
+  1.000000000000000000f, 0.000000000000000000f, 0.999995293809576190f,
+  -0.003067956762965976f,
+  0.999981175282601110f, -0.006135884649154475f, 0.999957644551963900f,
+  -0.009203754782059819f,
+  0.999924701839144500f, -0.012271538285719925f, 0.999882347454212560f,
+  -0.015339206284988100f,
+  0.999830581795823400f, -0.018406729905804820f, 0.999769405351215280f,
+  -0.021474080275469508f,
+  0.999698818696204250f, -0.024541228522912288f, 0.999618822495178640f,
+  -0.027608145778965740f,
+  0.999529417501093140f, -0.030674803176636626f, 0.999430604555461730f,
+  -0.033741171851377580f,
+  0.999322384588349540f, -0.036807222941358832f, 0.999204758618363890f,
+  -0.039872927587739811f,
+  0.999077727752645360f, -0.042938256934940820f, 0.998941293186856870f,
+  -0.046003182130914623f,
+  0.998795456205172410f, -0.049067674327418015f, 0.998640218180265270f,
+  -0.052131704680283324f,
+  0.998475580573294770f, -0.055195244349689934f, 0.998301544933892890f,
+  -0.058258264500435752f,
+  0.998118112900149180f, -0.061320736302208578f, 0.997925286198596000f,
+  -0.064382630929857465f,
+  0.997723066644191640f, -0.067443919563664051f, 0.997511456140303450f,
+  -0.070504573389613856f,
+  0.997290456678690210f, -0.073564563599667426f, 0.997060070339482960f,
+  -0.076623861392031492f,
+  0.996820299291165670f, -0.079682437971430126f, 0.996571145790554840f,
+  -0.082740264549375692f,
+  0.996312612182778000f, -0.085797312344439894f, 0.996044700901251970f,
+  -0.088853552582524600f,
+  0.995767414467659820f, -0.091908956497132724f, 0.995480755491926940f,
+  -0.094963495329638992f,
+  0.995184726672196930f, -0.098017140329560604f, 0.994879330794805620f,
+  -0.101069862754827820f,
+  0.994564570734255420f, -0.104121633872054590f, 0.994240449453187900f,
+  -0.107172424956808840f,
+  0.993906970002356060f, -0.110222207293883060f, 0.993564135520595300f,
+  -0.113270952177564350f,
+  0.993211949234794500f, -0.116318630911904750f, 0.992850414459865100f,
+  -0.119365214810991350f,
+  0.992479534598709970f, -0.122410675199216200f, 0.992099313142191800f,
+  -0.125454983411546230f,
+  0.991709753669099530f, -0.128498110793793170f, 0.991310859846115440f,
+  -0.131540028702883120f,
+  0.990902635427780010f, -0.134580708507126170f, 0.990485084256457090f,
+  -0.137620121586486040f,
+  0.990058210262297120f, -0.140658239332849210f, 0.989622017463200890f,
+  -0.143695033150294470f,
+  0.989176509964781010f, -0.146730474455361750f, 0.988721691960323780f,
+  -0.149764534677321510f,
+  0.988257567730749460f, -0.152797185258443440f, 0.987784141644572180f,
+  -0.155828397654265230f,
+  0.987301418157858430f, -0.158858143333861450f, 0.986809401814185530f,
+  -0.161886393780111830f,
+  0.986308097244598670f, -0.164913120489969890f, 0.985797509167567480f,
+  -0.167938294974731170f,
+  0.985277642388941220f, -0.170961888760301220f, 0.984748501801904210f,
+  -0.173983873387463820f,
+  0.984210092386929030f, -0.177004220412148750f, 0.983662419211730250f,
+  -0.180022901405699510f,
+  0.983105487431216290f, -0.183039887955140950f, 0.982539302287441240f,
+  -0.186055151663446630f,
+  0.981963869109555240f, -0.189068664149806190f, 0.981379193313754560f,
+  -0.192080397049892440f,
+  0.980785280403230430f, -0.195090322016128250f, 0.980182135968117430f,
+  -0.198098410717953560f,
+  0.979569765685440520f, -0.201104634842091900f, 0.978948175319062200f,
+  -0.204108966092816870f,
+  0.978317370719627650f, -0.207111376192218560f, 0.977677357824509930f,
+  -0.210111836880469610f,
+  0.977028142657754390f, -0.213110319916091360f, 0.976369731330021140f,
+  -0.216106797076219520f,
+  0.975702130038528570f, -0.219101240156869800f, 0.975025345066994120f,
+  -0.222093620973203510f,
+  0.974339382785575860f, -0.225083911359792830f, 0.973644249650811980f,
+  -0.228072083170885730f,
+  0.972939952205560180f, -0.231058108280671110f, 0.972226497078936270f,
+  -0.234041958583543430f,
+  0.971503890986251780f, -0.237023605994367200f, 0.970772140728950350f,
+  -0.240003022448741500f,
+  0.970031253194543970f, -0.242980179903263870f, 0.969281235356548530f,
+  -0.245955050335794590f,
+  0.968522094274417380f, -0.248927605745720150f, 0.967753837093475510f,
+  -0.251897818154216970f,
+  0.966976471044852070f, -0.254865659604514570f, 0.966190003445412500f,
+  -0.257831102162158990f,
+  0.965394441697689400f, -0.260794117915275510f, 0.964589793289812760f,
+  -0.263754678974831350f,
+  0.963776065795439840f, -0.266712757474898370f, 0.962953266873683880f,
+  -0.269668325572915090f,
+  0.962121404269041580f, -0.272621355449948980f, 0.961280485811320640f,
+  -0.275571819310958140f,
+  0.960430519415565790f, -0.278519689385053060f, 0.959571513081984520f,
+  -0.281464937925757940f,
+  0.958703474895871600f, -0.284407537211271880f, 0.957826413027532910f,
+  -0.287347459544729510f,
+  0.956940335732208820f, -0.290284677254462330f, 0.956045251349996410f,
+  -0.293219162694258630f,
+  0.955141168305770780f, -0.296150888243623790f, 0.954228095109105670f,
+  -0.299079826308040480f,
+  0.953306040354193860f, -0.302005949319228080f, 0.952375012719765880f,
+  -0.304929229735402370f,
+  0.951435020969008340f, -0.307849640041534870f, 0.950486073949481700f,
+  -0.310767152749611470f,
+  0.949528180593036670f, -0.313681740398891520f, 0.948561349915730270f,
+  -0.316593375556165850f,
+  0.947585591017741090f, -0.319502030816015690f, 0.946600913083283530f,
+  -0.322407678801069850f,
+  0.945607325380521280f, -0.325310292162262930f, 0.944604837261480260f,
+  -0.328209843579092500f,
+  0.943593458161960390f, -0.331106305759876430f, 0.942573197601446870f,
+  -0.333999651442009380f,
+  0.941544065183020810f, -0.336889853392220050f, 0.940506070593268300f,
+  -0.339776884406826850f,
+  0.939459223602189920f, -0.342660717311994380f, 0.938403534063108060f,
+  -0.345541324963989090f,
+  0.937339011912574960f, -0.348418680249434560f, 0.936265667170278260f,
+  -0.351292756085567090f,
+  0.935183509938947610f, -0.354163525420490340f, 0.934092550404258980f,
+  -0.357030961233429980f,
+  0.932992798834738960f, -0.359895036534988110f, 0.931884265581668150f,
+  -0.362755724367397230f,
+  0.930766961078983710f, -0.365612997804773850f, 0.929640895843181330f,
+  -0.368466829953372320f,
+  0.928506080473215590f, -0.371317193951837540f, 0.927362525650401110f,
+  -0.374164062971457930f,
+  0.926210242138311380f, -0.377007410216418260f, 0.925049240782677580f,
+  -0.379847208924051160f,
+  0.923879532511286740f, -0.382683432365089780f, 0.922701128333878630f,
+  -0.385516053843918850f,
+  0.921514039342042010f, -0.388345046698826250f, 0.920318276709110590f,
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+  -0.996571145790554840f,
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+  -0.997060070339482960f,
+  0.073564563599667454f, -0.997290456678690210f, 0.070504573389614009f,
+  -0.997511456140303450f,
+  0.067443919563664106f, -0.997723066644191640f, 0.064382630929857410f,
+  -0.997925286198596000f,
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+  -0.998640218180265270f,
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+  -0.998941293186856870f,
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+  -0.999204758618363890f,
+  0.036807222941358991f, -0.999322384588349540f, 0.033741171851377642f,
+  -0.999430604555461730f,
+  0.030674803176636581f, -0.999529417501093140f, 0.027608145778965820f,
+  -0.999618822495178640f,
+  0.024541228522912264f, -0.999698818696204250f, 0.021474080275469605f,
+  -0.999769405351215280f,
+  0.018406729905804820f, -0.999830581795823400f, 0.015339206284988220f,
+  -0.999882347454212560f,
+  0.012271538285719944f, -0.999924701839144500f, 0.009203754782059960f,
+  -0.999957644551963900f,
+  0.006135884649154515f, -0.999981175282601110f, 0.003067956762966138f,
+  -0.999995293809576190f
+};
+
+static const float32_t Weights_2048[4096] = {
+  1.000000000000000000f, 0.000000000000000000f, 0.999999705862882230f,
+  -0.000766990318742704f,
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+  -0.002300969151425805f,
+  0.999995293809576190f, -0.003067956762965976f, 0.999992646580707190f,
+  -0.003834942569706228f,
+  0.999989411081928400f, -0.004601926120448571f, 0.999985587315143200f,
+  -0.005368906963996343f,
+  0.999981175282601110f, -0.006135884649154475f, 0.999976174986897610f,
+  -0.006902858724729756f,
+  0.999970586430974140f, -0.007669828739531097f, 0.999964409618118280f,
+  -0.008436794242369799f,
+  0.999957644551963900f, -0.009203754782059819f, 0.999950291236490480f,
+  -0.009970709907418031f,
+  0.999942349676023910f, -0.010737659167264491f, 0.999933819875236000f,
+  -0.011504602110422714f,
+  0.999924701839144500f, -0.012271538285719925f, 0.999914995573113470f,
+  -0.013038467241987334f,
+  0.999904701082852900f, -0.013805388528060391f, 0.999893818374418490f,
+  -0.014572301692779064f,
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+  -0.016106101853537287f,
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+  -0.017639864115082053f,
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+  -0.019173584868322623f,
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+  -0.020707260504265895f,
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+  -0.022240887414024961f,
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+  -0.023774461988827555f,
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+  -0.025307980620024571f,
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+  -0.046769346900537863f,
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+  -0.052897636725665324f,
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+  -0.054429407010919133f,
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+  -0.055961049218520569f,
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+  -0.992941674389860470f,
+  0.117842061508325020f, -0.993032350197851410f, 0.117080380647800550f,
+  -0.993122441830495580f,
+  0.116318630911904880f, -0.993211949234794500f, 0.115556812748755290f,
+  -0.993300872358093280f,
+  0.114794926606510250f, -0.993389211148080650f, 0.114032972933367300f,
+  -0.993476965552789190f,
+  0.113270952177564360f, -0.993564135520595300f, 0.112508864787378830f,
+  -0.993650721000219120f,
+  0.111746711211126660f, -0.993736721940724600f, 0.110984491897163380f,
+  -0.993822138291519660f,
+  0.110222207293883180f, -0.993906970002356060f, 0.109459857849718030f,
+  -0.993991217023329380f,
+  0.108697444013138670f, -0.994074879304879370f, 0.107934966232653760f,
+  -0.994157956797789730f,
+  0.107172424956808870f, -0.994240449453187900f, 0.106409820634187840f,
+  -0.994322357222545810f,
+  0.105647153713410700f, -0.994403680057679100f, 0.104884424643134970f,
+  -0.994484417910747600f,
+  0.104121633872054730f, -0.994564570734255420f, 0.103358781848899700f,
+  -0.994644138481050710f,
+  0.102595869022436280f, -0.994723121104325700f, 0.101832895841466670f,
+  -0.994801518557617110f,
+  0.101069862754827880f, -0.994879330794805620f, 0.100306770211392820f,
+  -0.994956557770116380f,
+  0.099543618660069444f, -0.995033199438118630f, 0.098780408549799664f,
+  -0.995109255753726110f,
+  0.098017140329560770f, -0.995184726672196820f, 0.097253814448363354f,
+  -0.995259612149133390f,
+  0.096490431355252607f, -0.995333912140482280f, 0.095726991499307315f,
+  -0.995407626602534900f,
+  0.094963495329639061f, -0.995480755491926940f, 0.094199943295393190f,
+  -0.995553298765638470f,
+  0.093436335845747912f, -0.995625256380994310f, 0.092672673429913366f,
+  -0.995696628295663520f,
+  0.091908956497132696f, -0.995767414467659820f, 0.091145185496681130f,
+  -0.995837614855341610f,
+  0.090381360877865011f, -0.995907229417411720f, 0.089617483090022917f,
+  -0.995976258112917790f,
+  0.088853552582524684f, -0.996044700901251970f, 0.088089569804770507f,
+  -0.996112557742151130f,
+  0.087325535206192226f, -0.996179828595696870f, 0.086561449236251239f,
+  -0.996246513422315520f,
+  0.085797312344439880f, -0.996312612182778000f, 0.085033124980280414f,
+  -0.996378124838200210f,
+  0.084268887593324127f, -0.996443051350042630f, 0.083504600633152404f,
+  -0.996507391680110820f,
+  0.082740264549375803f, -0.996571145790554840f, 0.081975879791633108f,
+  -0.996634313643869900f,
+  0.081211446809592386f, -0.996696895202896060f, 0.080446966052950097f,
+  -0.996758890430818000f,
+  0.079682437971430126f, -0.996820299291165670f, 0.078917863014785095f,
+  -0.996881121747813850f,
+  0.078153241632794315f, -0.996941357764982160f, 0.077388574275265049f,
+  -0.997001007307235290f,
+  0.076623861392031617f, -0.997060070339482960f, 0.075859103432954503f,
+  -0.997118546826979980f,
+  0.075094300847921291f, -0.997176436735326190f, 0.074329454086845867f,
+  -0.997233740030466160f,
+  0.073564563599667454f, -0.997290456678690210f, 0.072799629836351618f,
+  -0.997346586646633230f,
+  0.072034653246889416f, -0.997402129901275300f, 0.071269634281296415f,
+  -0.997457086409941910f,
+  0.070504573389614009f, -0.997511456140303450f, 0.069739471021907376f,
+  -0.997565239060375750f,
+  0.068974327628266732f, -0.997618435138519550f, 0.068209143658806454f,
+  -0.997671044343441000f,
+  0.067443919563664106f, -0.997723066644191640f, 0.066678655793001543f,
+  -0.997774502010167820f,
+  0.065913352797003930f, -0.997825350411111640f, 0.065148011025878860f,
+  -0.997875611817110150f,
+  0.064382630929857410f, -0.997925286198596000f, 0.063617212959193190f,
+  -0.997974373526346990f,
+  0.062851757564161420f, -0.998022873771486240f, 0.062086265195060247f,
+  -0.998070786905482340f,
+  0.061320736302208648f, -0.998118112900149180f, 0.060555171335947781f,
+  -0.998164851727646240f,
+  0.059789570746640007f, -0.998211003360478190f, 0.059023934984667986f,
+  -0.998256567771495180f,
+  0.058258264500435732f, -0.998301544933892890f, 0.057492559744367684f,
+  -0.998345934821212370f,
+  0.056726821166907783f, -0.998389737407340160f, 0.055961049218520520f,
+  -0.998432952666508440f,
+  0.055195244349690031f, -0.998475580573294770f, 0.054429407010919147f,
+  -0.998517621102622210f,
+  0.053663537652730679f, -0.998559074229759310f, 0.052897636725665401f,
+  -0.998599939930320370f,
+  0.052131704680283317f, -0.998640218180265270f, 0.051365741967162731f,
+  -0.998679908955899090f,
+  0.050599749036899337f, -0.998719012233872940f, 0.049833726340107257f,
+  -0.998757527991183340f,
+  0.049067674327418126f, -0.998795456205172410f, 0.048301593449480172f,
+  -0.998832796853527990f,
+  0.047535484156959261f, -0.998869549914283560f, 0.046769346900537960f,
+  -0.998905715365818290f,
+  0.046003182130914644f, -0.998941293186856870f, 0.045236990298804750f,
+  -0.998976283356469820f,
+  0.044470771854938744f, -0.999010685854073380f, 0.043704527250063421f,
+  -0.999044500659429290f,
+  0.042938256934940959f, -0.999077727752645360f, 0.042171961360348002f,
+  -0.999110367114174890f,
+  0.041405640977076712f, -0.999142418724816910f, 0.040639296235933854f,
+  -0.999173882565716380f,
+  0.039872927587739845f, -0.999204758618363890f, 0.039106535483329839f,
+  -0.999235046864595850f,
+  0.038340120373552791f, -0.999264747286594420f, 0.037573682709270514f,
+  -0.999293859866887790f,
+  0.036807222941358991f, -0.999322384588349540f, 0.036040741520706299f,
+  -0.999350321434199440f,
+  0.035274238898213947f, -0.999377670388002850f, 0.034507715524795889f,
+  -0.999404431433671300f,
+  0.033741171851377642f, -0.999430604555461730f, 0.032974608328897315f,
+  -0.999456189737977340f,
+  0.032208025408304704f, -0.999481186966166950f, 0.031441423540560343f,
+  -0.999505596225325310f,
+  0.030674803176636581f, -0.999529417501093140f, 0.029908164767516655f,
+  -0.999552650779456990f,
+  0.029141508764193740f, -0.999575296046749220f, 0.028374835617672258f,
+  -0.999597353289648380f,
+  0.027608145778965820f, -0.999618822495178640f, 0.026841439699098527f,
+  -0.999639703650710200f,
+  0.026074717829104040f, -0.999659996743959220f, 0.025307980620024630f,
+  -0.999679701762987930f,
+  0.024541228522912264f, -0.999698818696204250f, 0.023774461988827676f,
+  -0.999717347532362190f,
+  0.023007681468839410f, -0.999735288260561680f, 0.022240887414024919f,
+  -0.999752640870248840f,
+  0.021474080275469605f, -0.999769405351215280f, 0.020707260504265912f,
+  -0.999785581693599210f,
+  0.019940428551514598f, -0.999801169887884260f, 0.019173584868322699f,
+  -0.999816169924900410f,
+  0.018406729905804820f, -0.999830581795823400f, 0.017639864115082195f,
+  -0.999844405492175240f,
+  0.016872987947281773f, -0.999857641005823860f, 0.016106101853537263f,
+  -0.999870288328982950f,
+  0.015339206284988220f, -0.999882347454212560f, 0.014572301692779104f,
+  -0.999893818374418490f,
+  0.013805388528060349f, -0.999904701082852900f, 0.013038467241987433f,
+  -0.999914995573113470f,
+  0.012271538285719944f, -0.999924701839144500f, 0.011504602110422875f,
+  -0.999933819875236000f,
+  0.010737659167264572f, -0.999942349676023910f, 0.009970709907418029f,
+  -0.999950291236490480f,
+  0.009203754782059960f, -0.999957644551963900f, 0.008436794242369860f,
+  -0.999964409618118280f,
+  0.007669828739531077f, -0.999970586430974140f, 0.006902858724729877f,
+  -0.999976174986897610f,
+  0.006135884649154515f, -0.999981175282601110f, 0.005368906963996303f,
+  -0.999985587315143200f,
+  0.004601926120448672f, -0.999989411081928400f, 0.003834942569706248f,
+  -0.999992646580707190f,
+  0.003067956762966138f, -0.999995293809576190f, 0.002300969151425887f,
+  -0.999997352766978210f,
+  0.001533980186284766f, -0.999998823451701880f, 0.000766990318742846f,
+  -0.999999705862882230f
+};
+
+/**   
+* \par   
+* cosFactor tables are generated using the formula : 
    cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
       
+* \par   
+* C command to generate the table   
+* \par   
+* 
     for(i = 0; i< N; i++)   
+* {   
+*    cos_factors[i]= 2 * cos((2*i+1)*c/2);   
+* } 
       
+* \par   
+* where N is the number of factors to generate and c is pi/(2*N)   
+*/
+static const float32_t cos_factors_128[128] = {
+  0.999981175282601110f, 0.999830581795823400f, 0.999529417501093140f,
+  0.999077727752645360f,
+  0.998475580573294770f, 0.997723066644191640f, 0.996820299291165670f,
+  0.995767414467659820f,
+  0.994564570734255420f, 0.993211949234794500f, 0.991709753669099530f,
+  0.990058210262297120f,
+  0.988257567730749460f, 0.986308097244598670f, 0.984210092386929030f,
+  0.981963869109555240f,
+  0.979569765685440520f, 0.977028142657754390f, 0.974339382785575860f,
+  0.971503890986251780f,
+  0.968522094274417380f, 0.965394441697689400f, 0.962121404269041580f,
+  0.958703474895871600f,
+  0.955141168305770780f, 0.951435020969008340f, 0.947585591017741090f,
+  0.943593458161960390f,
+  0.939459223602189920f, 0.935183509938947610f, 0.930766961078983710f,
+  0.926210242138311380f,
+  0.921514039342042010f, 0.916679059921042700f, 0.911706032005429880f,
+  0.906595704514915330f,
+  0.901348847046022030f, 0.895966249756185220f, 0.890448723244757880f,
+  0.884797098430937790f,
+  0.879012226428633530f, 0.873094978418290090f, 0.867046245515692650f,
+  0.860866938637767310f,
+  0.854557988365400530f, 0.848120344803297230f, 0.841554977436898440f,
+  0.834862874986380010f,
+  0.828045045257755800f, 0.821102514991104650f, 0.814036329705948410f,
+  0.806847553543799330f,
+  0.799537269107905010f, 0.792106577300212390f, 0.784556597155575240f,
+  0.776888465673232440f,
+  0.769103337645579700f, 0.761202385484261780f, 0.753186799043612520f,
+  0.745057785441466060f,
+  0.736816568877369900f, 0.728464390448225200f, 0.720002507961381650f,
+  0.711432195745216430f,
+  0.702754744457225300f, 0.693971460889654000f, 0.685083667772700360f,
+  0.676092703575316030f,
+  0.666999922303637470f, 0.657806693297078640f, 0.648514401022112550f,
+  0.639124444863775730f,
+  0.629638238914927100f, 0.620057211763289210f, 0.610382806276309480f,
+  0.600616479383868970f,
+  0.590759701858874280f, 0.580813958095764530f, 0.570780745886967370f,
+  0.560661576197336030f,
+  0.550457972936604810f, 0.540171472729892970f, 0.529803624686294830f,
+  0.519355990165589530f,
+  0.508830142543106990f, 0.498227666972781870f, 0.487550160148436050f,
+  0.476799230063322250f,
+  0.465976495767966130f, 0.455083587126343840f, 0.444122144570429260f,
+  0.433093818853152010f,
+  0.422000270799799790f, 0.410843171057903910f, 0.399624199845646790f,
+  0.388345046698826300f,
+  0.377007410216418310f, 0.365612997804773960f, 0.354163525420490510f,
+  0.342660717311994380f,
+  0.331106305759876430f, 0.319502030816015750f, 0.307849640041534980f,
+  0.296150888243623960f,
+  0.284407537211271820f, 0.272621355449948980f, 0.260794117915275570f,
+  0.248927605745720260f,
+  0.237023605994367340f, 0.225083911359792780f, 0.213110319916091360f,
+  0.201104634842091960f,
+  0.189068664149806280f, 0.177004220412148860f, 0.164913120489970090f,
+  0.152797185258443410f,
+  0.140658239332849240f, 0.128498110793793220f, 0.116318630911904880f,
+  0.104121633872054730f,
+  0.091908956497132696f, 0.079682437971430126f, 0.067443919563664106f,
+  0.055195244349690031f,
+  0.042938256934940959f, 0.030674803176636581f, 0.018406729905804820f,
+  0.006135884649154515f
+};
+
+static const float32_t cos_factors_512[512] = {
+  0.999998823451701880f, 0.999989411081928400f, 0.999970586430974140f,
+  0.999942349676023910f,
+  0.999904701082852900f, 0.999857641005823860f, 0.999801169887884260f,
+  0.999735288260561680f,
+  0.999659996743959220f, 0.999575296046749220f, 0.999481186966166950f,
+  0.999377670388002850f,
+  0.999264747286594420f, 0.999142418724816910f, 0.999010685854073380f,
+  0.998869549914283560f,
+  0.998719012233872940f, 0.998559074229759310f, 0.998389737407340160f,
+  0.998211003360478190f,
+  0.998022873771486240f, 0.997825350411111640f, 0.997618435138519550f,
+  0.997402129901275300f,
+  0.997176436735326190f, 0.996941357764982160f, 0.996696895202896060f,
+  0.996443051350042630f,
+  0.996179828595696980f, 0.995907229417411720f, 0.995625256380994310f,
+  0.995333912140482280f,
+  0.995033199438118630f, 0.994723121104325700f, 0.994403680057679100f,
+  0.994074879304879370f,
+  0.993736721940724600f, 0.993389211148080650f, 0.993032350197851410f,
+  0.992666142448948020f,
+  0.992290591348257370f, 0.991905700430609330f, 0.991511473318743900f,
+  0.991107913723276890f,
+  0.990695025442664630f, 0.990272812363169110f, 0.989841278458820530f,
+  0.989400427791380380f,
+  0.988950264510302990f, 0.988490792852696590f, 0.988022017143283530f,
+  0.987543941794359230f,
+  0.987056571305750970f, 0.986559910264775410f, 0.986053963346195440f,
+  0.985538735312176060f,
+  0.985014231012239840f, 0.984480455383220930f, 0.983937413449218920f,
+  0.983385110321551180f,
+  0.982823551198705240f, 0.982252741366289370f, 0.981672686196983110f,
+  0.981083391150486710f,
+  0.980484861773469380f, 0.979877103699517640f, 0.979260122649082020f,
+  0.978633924429423210f,
+  0.977998514934557140f, 0.977353900145199960f, 0.976700086128711840f,
+  0.976037079039039020f,
+  0.975364885116656980f, 0.974683510688510670f, 0.973992962167955830f,
+  0.973293246054698250f,
+  0.972584368934732210f, 0.971866337480279400f, 0.971139158449725090f,
+  0.970402838687555500f,
+  0.969657385124292450f, 0.968902804776428870f, 0.968139104746362440f,
+  0.967366292222328510f,
+  0.966584374478333120f, 0.965793358874083680f, 0.964993252854920320f,
+  0.964184063951745830f,
+  0.963365799780954050f, 0.962538468044359160f, 0.961702076529122540f,
+  0.960856633107679660f,
+  0.960002145737665960f, 0.959138622461841890f, 0.958266071408017670f,
+  0.957384500788975860f,
+  0.956493918902395100f, 0.955594334130771110f, 0.954685754941338340f,
+  0.953768189885990330f,
+  0.952841647601198720f, 0.951906136807932350f, 0.950961666311575080f,
+  0.950008245001843000f,
+  0.949045881852700560f, 0.948074585922276230f, 0.947094366352777220f,
+  0.946105232370403450f,
+  0.945107193285260610f, 0.944100258491272660f, 0.943084437466093490f,
+  0.942059739771017310f,
+  0.941026175050889260f, 0.939983753034014050f, 0.938932483532064600f,
+  0.937872376439989890f,
+  0.936803441735921560f, 0.935725689481080370f, 0.934639129819680780f,
+  0.933543772978836170f,
+  0.932439629268462360f, 0.931326709081180430f, 0.930205022892219070f,
+  0.929074581259315860f,
+  0.927935394822617890f, 0.926787474304581750f, 0.925630830509872720f,
+  0.924465474325262600f,
+  0.923291416719527640f, 0.922108668743345180f, 0.920917241529189520f,
+  0.919717146291227360f,
+  0.918508394325212250f, 0.917290997008377910f, 0.916064965799331720f,
+  0.914830312237946200f,
+  0.913587047945250810f, 0.912335184623322750f, 0.911074734055176360f,
+  0.909805708104652220f,
+  0.908528118716306120f, 0.907241977915295820f, 0.905947297807268460f,
+  0.904644090578246240f,
+  0.903332368494511820f, 0.902012143902493180f, 0.900683429228646970f,
+  0.899346236979341570f,
+  0.898000579740739880f, 0.896646470178680150f, 0.895283921038557580f,
+  0.893912945145203250f,
+  0.892533555402764580f, 0.891145764794583180f, 0.889749586383072780f,
+  0.888345033309596350f,
+  0.886932118794342190f, 0.885510856136199950f, 0.884081258712634990f,
+  0.882643339979562790f,
+  0.881197113471222090f, 0.879742592800047410f, 0.878279791656541580f,
+  0.876808723809145650f,
+  0.875329403104110890f, 0.873841843465366860f, 0.872346058894391540f,
+  0.870842063470078980f,
+  0.869329871348606840f, 0.867809496763303320f, 0.866280954024512990f,
+  0.864744257519462380f,
+  0.863199421712124160f, 0.861646461143081300f, 0.860085390429390140f,
+  0.858516224264442740f,
+  0.856938977417828760f, 0.855353664735196030f, 0.853760301138111410f,
+  0.852158901623919830f,
+  0.850549481265603480f, 0.848932055211639610f, 0.847306638685858320f,
+  0.845673246987299070f,
+  0.844031895490066410f, 0.842382599643185850f, 0.840725374970458070f,
+  0.839060237070312740f,
+  0.837387201615661940f, 0.835706284353752600f, 0.834017501106018130f,
+  0.832320867767929680f,
+  0.830616400308846310f, 0.828904114771864870f, 0.827184027273669130f,
+  0.825456154004377550f,
+  0.823720511227391430f, 0.821977115279241550f, 0.820225982569434690f,
+  0.818467129580298660f,
+  0.816700572866827850f, 0.814926329056526620f, 0.813144414849253590f,
+  0.811354847017063730f,
+  0.809557642404051260f, 0.807752817926190360f, 0.805940390571176280f,
+  0.804120377398265810f,
+  0.802292795538115720f, 0.800457662192622820f, 0.798614994634760820f,
+  0.796764810208418830f,
+  0.794907126328237010f, 0.793041960479443640f, 0.791169330217690200f,
+  0.789289253168885650f,
+  0.787401747029031430f, 0.785506829564053930f, 0.783604518609638200f,
+  0.781694832071059390f,
+  0.779777787923014550f, 0.777853404209453150f, 0.775921699043407690f,
+  0.773982690606822900f,
+  0.772036397150384520f, 0.770082836993347900f, 0.768122028523365420f,
+  0.766153990196312920f,
+  0.764178740536116670f, 0.762196298134578900f, 0.760206681651202420f,
+  0.758209909813015280f,
+  0.756206001414394540f, 0.754194975316889170f, 0.752176850449042810f,
+  0.750151645806215070f,
+  0.748119380450403600f, 0.746080073510063780f, 0.744033744179929290f,
+  0.741980411720831070f,
+  0.739920095459516200f, 0.737852814788465980f, 0.735778589165713590f,
+  0.733697438114660370f,
+  0.731609381223892630f, 0.729514438146997010f, 0.727412628602375770f,
+  0.725303972373060770f,
+  0.723188489306527460f, 0.721066199314508110f, 0.718937122372804490f,
+  0.716801278521099540f,
+  0.714658687862769090f, 0.712509370564692320f, 0.710353346857062420f,
+  0.708190637033195400f,
+  0.706021261449339740f, 0.703845240524484940f, 0.701662594740168570f,
+  0.699473344640283770f,
+  0.697277510830886630f, 0.695075113980000880f, 0.692866174817424740f,
+  0.690650714134534720f,
+  0.688428752784090550f, 0.686200311680038700f, 0.683965411797315510f,
+  0.681724074171649820f,
+  0.679476319899365080f, 0.677222170137180450f, 0.674961646102012040f,
+  0.672694769070772970f,
+  0.670421560380173090f, 0.668142041426518560f, 0.665856233665509720f,
+  0.663564158612039880f,
+  0.661265837839992270f, 0.658961292982037320f, 0.656650545729429050f,
+  0.654333617831800550f,
+  0.652010531096959500f, 0.649681307390683190f, 0.647345968636512060f,
+  0.645004536815544040f,
+  0.642657033966226860f, 0.640303482184151670f, 0.637943903621844170f,
+  0.635578320488556230f,
+  0.633206755050057190f, 0.630829229628424470f, 0.628445766601832710f,
+  0.626056388404343520f,
+  0.623661117525694640f, 0.621259976511087660f, 0.618852987960976320f,
+  0.616440174530853650f,
+  0.614021558931038490f, 0.611597163926462020f, 0.609167012336453210f,
+  0.606731127034524480f,
+  0.604289530948156070f, 0.601842247058580030f, 0.599389298400564540f,
+  0.596930708062196500f,
+  0.594466499184664540f, 0.591996694962040990f, 0.589521318641063940f,
+  0.587040393520918080f,
+  0.584553942953015330f, 0.582061990340775550f, 0.579564559139405740f,
+  0.577061672855679550f,
+  0.574553355047715760f, 0.572039629324757050f, 0.569520519346947250f,
+  0.566996048825108680f,
+  0.564466241520519500f, 0.561931121244689470f, 0.559390711859136140f,
+  0.556845037275160100f,
+  0.554294121453620110f, 0.551737988404707450f, 0.549176662187719770f,
+  0.546610166910834860f,
+  0.544038526730883930f, 0.541461765853123560f, 0.538879908531008420f,
+  0.536292979065963180f,
+  0.533701001807152960f, 0.531104001151255000f, 0.528502001542228480f,
+  0.525895027471084740f,
+  0.523283103475656430f, 0.520666254140367270f, 0.518044504095999340f,
+  0.515417878019463150f,
+  0.512786400633563070f, 0.510150096706766700f, 0.507508991052970870f,
+  0.504863108531267480f,
+  0.502212474045710900f, 0.499557112545081890f, 0.496897049022654640f,
+  0.494232308515959730f,
+  0.491562916106550060f, 0.488888896919763230f, 0.486210276124486530f,
+  0.483527078932918740f,
+  0.480839330600333900f, 0.478147056424843120f, 0.475450281747155870f,
+  0.472749031950342900f,
+  0.470043332459595620f, 0.467333208741988530f, 0.464618686306237820f,
+  0.461899790702462840f,
+  0.459176547521944150f, 0.456448982396883860f, 0.453717121000163930f,
+  0.450980989045103810f,
+  0.448240612285220000f, 0.445496016513981740f, 0.442747227564570130f,
+  0.439994271309633260f,
+  0.437237173661044200f, 0.434475960569655710f, 0.431710658025057370f,
+  0.428941292055329550f,
+  0.426167888726799620f, 0.423390474143796100f, 0.420609074448402510f,
+  0.417823715820212380f,
+  0.415034424476081630f, 0.412241226669883000f, 0.409444148692257590f,
+  0.406643216870369140f,
+  0.403838457567654130f, 0.401029897183575790f, 0.398217562153373620f,
+  0.395401478947816300f,
+  0.392581674072951530f, 0.389758174069856410f, 0.386931005514388690f,
+  0.384100195016935040f,
+  0.381265769222162490f, 0.378427754808765620f, 0.375586178489217330f,
+  0.372741067009515810f,
+  0.369892447148934270f, 0.367040345719767240f, 0.364184789567079840f,
+  0.361325805568454340f,
+  0.358463420633736540f, 0.355597661704783960f, 0.352728555755210730f,
+  0.349856129790135030f,
+  0.346980410845923680f, 0.344101425989938980f, 0.341219202320282410f,
+  0.338333766965541290f,
+  0.335445147084531660f, 0.332553369866044220f, 0.329658462528587550f,
+  0.326760452320131790f,
+  0.323859366517852960f, 0.320955232427875210f, 0.318048077385015060f,
+  0.315137928752522440f,
+  0.312224813921825050f, 0.309308760312268780f, 0.306389795370861080f,
+  0.303467946572011370f,
+  0.300543241417273400f, 0.297615707435086310f, 0.294685372180514330f,
+  0.291752263234989370f,
+  0.288816408206049480f, 0.285877834727080730f, 0.282936570457055390f,
+  0.279992643080273380f,
+  0.277046080306099950f, 0.274096909868706330f, 0.271145159526808070f,
+  0.268190857063403180f,
+  0.265234030285511900f, 0.262274707023913590f, 0.259312915132886350f,
+  0.256348682489942910f,
+  0.253382036995570270f, 0.250413006572965280f, 0.247441619167773440f,
+  0.244467902747824210f,
+  0.241491885302869300f, 0.238513594844318500f, 0.235533059404975460f,
+  0.232550307038775330f,
+  0.229565365820518870f, 0.226578263845610110f, 0.223589029229790020f,
+  0.220597690108873650f,
+  0.217604274638483670f, 0.214608810993786920f, 0.211611327369227610f,
+  0.208611851978263460f,
+  0.205610413053099320f, 0.202607038844421110f, 0.199601757621131050f,
+  0.196594597670080220f,
+  0.193585587295803750f, 0.190574754820252800f, 0.187562128582529740f,
+  0.184547736938619640f,
+  0.181531608261125130f, 0.178513770938997590f, 0.175494253377271400f,
+  0.172473083996796030f,
+  0.169450291233967930f, 0.166425903540464220f, 0.163399949382973230f,
+  0.160372457242928400f,
+  0.157343455616238280f, 0.154312973013020240f, 0.151281037957330250f,
+  0.148247678986896200f,
+  0.145212924652847520f, 0.142176803519448000f, 0.139139344163826280f,
+  0.136100575175706200f,
+  0.133060525157139180f, 0.130019222722233350f, 0.126976696496885980f,
+  0.123932975118512200f,
+  0.120888087235777220f, 0.117842061508325020f, 0.114794926606510250f,
+  0.111746711211126660f,
+  0.108697444013138670f, 0.105647153713410700f, 0.102595869022436280f,
+  0.099543618660069444f,
+  0.096490431355252607f, 0.093436335845747912f, 0.090381360877865011f,
+  0.087325535206192226f,
+  0.084268887593324127f, 0.081211446809592386f, 0.078153241632794315f,
+  0.075094300847921291f,
+  0.072034653246889416f, 0.068974327628266732f, 0.065913352797003930f,
+  0.062851757564161420f,
+  0.059789570746640007f, 0.056726821166907783f, 0.053663537652730679f,
+  0.050599749036899337f,
+  0.047535484156959261f, 0.044470771854938744f, 0.041405640977076712f,
+  0.038340120373552791f,
+  0.035274238898213947f, 0.032208025408304704f, 0.029141508764193740f,
+  0.026074717829104040f,
+  0.023007681468839410f, 0.019940428551514598f, 0.016872987947281773f,
+  0.013805388528060349f,
+  0.010737659167264572f, 0.007669828739531077f, 0.004601926120448672f,
+  0.001533980186284766f
+};
+
+static const float32_t cos_factors_2048[2048] = {
+  0.999999926465717890f, 0.999999338191525530f, 0.999998161643486980f,
+  0.999996396822294350f,
+  0.999994043728985820f, 0.999991102364945590f, 0.999987572731904080f,
+  0.999983454831937730f,
+  0.999978748667468830f, 0.999973454241265940f, 0.999967571556443780f,
+  0.999961100616462820f,
+  0.999954041425129780f, 0.999946393986597460f, 0.999938158305364590f,
+  0.999929334386276070f,
+  0.999919922234522750f, 0.999909921855641540f, 0.999899333255515390f,
+  0.999888156440373320f,
+  0.999876391416790410f, 0.999864038191687680f, 0.999851096772332190f,
+  0.999837567166337090f,
+  0.999823449381661570f, 0.999808743426610520f, 0.999793449309835270f,
+  0.999777567040332940f,
+  0.999761096627446610f, 0.999744038080865430f, 0.999726391410624470f,
+  0.999708156627104880f,
+  0.999689333741033640f, 0.999669922763483760f, 0.999649923705874240f,
+  0.999629336579970110f,
+  0.999608161397882110f, 0.999586398172067070f, 0.999564046915327740f,
+  0.999541107640812940f,
+  0.999517580362016990f, 0.999493465092780590f, 0.999468761847290050f,
+  0.999443470640077770f,
+  0.999417591486021720f, 0.999391124400346050f, 0.999364069398620550f,
+  0.999336426496761240f,
+  0.999308195711029470f, 0.999279377058032710f, 0.999249970554724420f,
+  0.999219976218403530f,
+  0.999189394066714920f, 0.999158224117649430f, 0.999126466389543390f,
+  0.999094120901079070f,
+  0.999061187671284600f, 0.999027666719533690f, 0.998993558065545680f,
+  0.998958861729386080f,
+  0.998923577731465780f, 0.998887706092541290f, 0.998851246833715180f,
+  0.998814199976435390f,
+  0.998776565542495610f, 0.998738343554035230f, 0.998699534033539280f,
+  0.998660137003838490f,
+  0.998620152488108870f, 0.998579580509872500f, 0.998538421092996730f,
+  0.998496674261694640f,
+  0.998454340040524800f, 0.998411418454391300f, 0.998367909528543820f,
+  0.998323813288577560f,
+  0.998279129760433200f, 0.998233858970396850f, 0.998188000945100300f,
+  0.998141555711520520f,
+  0.998094523296980010f, 0.998046903729146840f, 0.997998697036034390f,
+  0.997949903246001190f,
+  0.997900522387751620f, 0.997850554490335110f, 0.997799999583146470f,
+  0.997748857695925690f,
+  0.997697128858758500f, 0.997644813102075420f, 0.997591910456652630f,
+  0.997538420953611340f,
+  0.997484344624417930f, 0.997429681500884180f, 0.997374431615167150f,
+  0.997318594999768600f,
+  0.997262171687536170f, 0.997205161711661850f, 0.997147565105683480f,
+  0.997089381903483400f,
+  0.997030612139289450f, 0.996971255847674320f, 0.996911313063555740f,
+  0.996850783822196610f,
+  0.996789668159204560f, 0.996727966110532490f, 0.996665677712478160f,
+  0.996602803001684130f,
+  0.996539342015137940f, 0.996475294790172160f, 0.996410661364464100f,
+  0.996345441776035900f,
+  0.996279636063254650f, 0.996213244264832040f, 0.996146266419824620f,
+  0.996078702567633980f,
+  0.996010552748005870f, 0.995941817001031350f, 0.995872495367145730f,
+  0.995802587887129160f,
+  0.995732094602106430f, 0.995661015553546910f, 0.995589350783264600f,
+  0.995517100333418110f,
+  0.995444264246510340f, 0.995370842565388990f, 0.995296835333246090f,
+  0.995222242593618360f,
+  0.995147064390386470f, 0.995071300767776170f, 0.994994951770357020f,
+  0.994918017443043200f,
+  0.994840497831093180f, 0.994762392980109930f, 0.994683702936040250f,
+  0.994604427745175660f,
+  0.994524567454151740f, 0.994444122109948040f, 0.994363091759888570f,
+  0.994281476451641550f,
+  0.994199276233218910f, 0.994116491152977070f, 0.994033121259616400f,
+  0.993949166602181130f,
+  0.993864627230059750f, 0.993779503192984580f, 0.993693794541031790f,
+  0.993607501324621610f,
+  0.993520623594518090f, 0.993433161401829360f, 0.993345114798006910f,
+  0.993256483834846440f,
+  0.993167268564487230f, 0.993077469039412300f, 0.992987085312448390f,
+  0.992896117436765980f,
+  0.992804565465879140f, 0.992712429453645460f, 0.992619709454266140f,
+  0.992526405522286100f,
+  0.992432517712593660f, 0.992338046080420420f, 0.992242990681341700f,
+  0.992147351571276090f,
+  0.992051128806485720f, 0.991954322443575950f, 0.991856932539495470f,
+  0.991758959151536110f,
+  0.991660402337333210f, 0.991561262154865290f, 0.991461538662453790f,
+  0.991361231918763460f,
+  0.991260341982802440f, 0.991158868913921350f, 0.991056812771814340f,
+  0.990954173616518500f,
+  0.990850951508413620f, 0.990747146508222710f, 0.990642758677011570f,
+  0.990537788076188750f,
+  0.990432234767505970f, 0.990326098813057330f, 0.990219380275280000f,
+  0.990112079216953770f,
+  0.990004195701200910f, 0.989895729791486660f, 0.989786681551618640f,
+  0.989677051045747210f,
+  0.989566838338365120f, 0.989456043494307710f, 0.989344666578752640f,
+  0.989232707657220050f,
+  0.989120166795572690f, 0.989007044060015270f, 0.988893339517095130f,
+  0.988779053233701520f,
+  0.988664185277066230f, 0.988548735714763200f, 0.988432704614708340f,
+  0.988316092045159690f,
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+  0.060937958300107238f, 0.060172375466026218f, 0.059406757234087247f,
+  0.058641104054683348f,
+  0.057875416378229017f, 0.057109694655158132f, 0.056343939335925283f,
+  0.055578150871004817f,
+  0.054812329710889909f, 0.054046476306093640f, 0.053280591107148056f,
+  0.052514674564603257f,
+  0.051748727129028414f, 0.050982749251010900f, 0.050216741381155325f,
+  0.049450703970084824f,
+  0.048684637468439020f, 0.047918542326875327f, 0.047152418996068000f,
+  0.046386267926707213f,
+  0.045620089569500123f, 0.044853884375169933f, 0.044087652794454979f,
+  0.043321395278109784f,
+  0.042555112276904117f, 0.041788804241622082f, 0.041022471623063397f,
+  0.040256114872041358f,
+  0.039489734439384118f, 0.038723330775933762f, 0.037956904332545366f,
+  0.037190455560088091f,
+  0.036423984909444228f, 0.035657492831508264f, 0.034890979777187955f,
+  0.034124446197403423f,
+  0.033357892543086159f, 0.032591319265180385f, 0.031824726814640963f,
+  0.031058115642434700f,
+  0.030291486199539423f, 0.029524838936943035f, 0.028758174305644590f,
+  0.027991492756653365f,
+  0.027224794740987910f, 0.026458080709677145f, 0.025691351113759395f,
+  0.024924606404281485f,
+  0.024157847032300020f, 0.023391073448879338f, 0.022624286105092803f,
+  0.021857485452021874f,
+  0.021090671940755180f, 0.020323846022389572f, 0.019557008148029204f,
+  0.018790158768784596f,
+  0.018023298335773701f, 0.017256427300120978f, 0.016489546112956454f,
+  0.015722655225417017f,
+  0.014955755088644378f, 0.014188846153786343f, 0.013421928871995907f,
+  0.012655003694430301f,
+  0.011888071072252072f, 0.011121131456628141f, 0.010354185298728884f,
+  0.009587233049729183f,
+  0.008820275160807512f, 0.008053312083144991f, 0.007286344267926684f,
+  0.006519372166339549f,
+  0.005752396229573737f, 0.004985416908821652f, 0.004218434655277024f,
+  0.003451449920135975f,
+  0.002684463154596083f, 0.001917474809855460f, 0.001150485337113809f,
+  0.000383495187571497f
+};
+
+/**   
+ * @brief  Initialization function for the floating-point DCT4/IDCT4.  
+ * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.  
+ * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.  
+ * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.  
+ * @param[in]     N			 length of the DCT4.  
+ * @param[in]     Nby2       half of the length of the DCT4.  
+ * @param[in]     normalize  normalizing factor.  
+ * @return        arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.  
+ * \par Normalizing factor:   
+ * The normalizing factor is sqrt(2/N), which depends on the size of transform N.   
+ * Floating-point normalizing factors are mentioned in the table below for different DCT sizes:   
+ * \image html dct4NormalizingF32Table.gif   
+ */
+
+arm_status arm_dct4_init_f32(
+  arm_dct4_instance_f32 * S,
+  arm_rfft_instance_f32 * S_RFFT,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  float32_t normalize)
+{
+  /*  Initialize the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /* Initializing the pointer array with the weight table base addresses of different lengths */
+  float32_t *twiddlePtr[3] =
+    { (float32_t *) Weights_128, (float32_t *) Weights_512,
+    (float32_t *) Weights_2048
+  };
+
+  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+  float32_t *pCosFactor[3] =
+    { (float32_t *) cos_factors_128, (float32_t *) cos_factors_512,
+    (float32_t *) cos_factors_2048
+  };
+
+  /* Initialize the DCT4 length */
+  S->N = N;
+
+  /* Initialize the half of DCT4 length */
+  S->Nby2 = Nby2;
+
+  /* Initialize the DCT4 Normalizing factor */
+  S->normalize = normalize;
+
+  /* Initialize Real FFT Instance */
+  S->pRfft = S_RFFT;
+
+  /* Initialize Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  switch (N)
+  {
+    /* Initialize the table modifier values */
+  case 2048u:
+    S->pTwiddle = twiddlePtr[2];
+    S->pCosFactor = pCosFactor[2];
+    break;
+  case 512u:
+    S->pTwiddle = twiddlePtr[1];
+    S->pCosFactor = pCosFactor[1];
+    break;
+  case 128u:
+    S->pTwiddle = twiddlePtr[0];
+    S->pCosFactor = pCosFactor[0];
+    break;
+  default:
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+
+  /* Initialize the RFFT/RIFFT */
+  arm_rfft_init_f32(S->pRfft, S->pCfft, S->N, 0u, 1u);
+
+  /* return the status of DCT4 Init function */
+  return (status);
+}
+
+/**   
+   * @} end of DCT4_IDCT4 group   
+   */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c
new file mode 100644
index 0000000000..25ed1e8ed5
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c
@@ -0,0 +1,1190 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_dct4_init_q15.c   
+*   
+* Description:	Initialization function of DCT-4 & IDCT4 Q15   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup DCT4_IDCT4   
+ * @{   
+ */
+
+/*   
+* @brief  Weights Table   
+*/
+
+/**   
+* \par   
+* Weights tables are generated using the formula : 
    weights[n] = e^(-j*n*pi/(2*N))
       
+* \par   
+* C command to generate the table   
+* 
       
+* for(i = 0; i< N; i++)   
+* {   
+*   weights[2*i]= cos(i*c);   
+*   weights[(2*i)+1]= -sin(i * c);   
+* } 
       
+* \par   
+* where N is the Number of weights to be calculated and c is pi/(2*N)   
+* \par   
+* Converted the output to q15 format by multiplying with 2^31 and saturated if required.   
+* \par   
+* In the tables below the real and imaginary values are placed alternatively, hence the   
+* array length is 2*N.   
+*/
+
+static const q15_t WeightsQ15_128[256] = {
+  0x7fff, 0x0, 0x7ffd, 0xfe6e, 0x7ff6, 0xfcdc, 0x7fe9, 0xfb4a,
+  0x7fd8, 0xf9b9, 0x7fc2, 0xf827, 0x7fa7, 0xf696, 0x7f87, 0xf505,
+  0x7f62, 0xf375, 0x7f38, 0xf1e5, 0x7f09, 0xf055, 0x7ed5, 0xeec7,
+  0x7e9d, 0xed38, 0x7e5f, 0xebab, 0x7e1d, 0xea1e, 0x7dd6, 0xe893,
+  0x7d8a, 0xe708, 0x7d39, 0xe57e, 0x7ce3, 0xe3f5, 0x7c89, 0xe26d,
+  0x7c29, 0xe0e7, 0x7bc5, 0xdf61, 0x7b5d, 0xdddd, 0x7aef, 0xdc5a,
+  0x7a7d, 0xdad8, 0x7a05, 0xd958, 0x798a, 0xd7da, 0x7909, 0xd65d,
+  0x7884, 0xd4e1, 0x77fa, 0xd368, 0x776c, 0xd1ef, 0x76d9, 0xd079,
+  0x7641, 0xcf05, 0x75a5, 0xcd92, 0x7504, 0xcc22, 0x745f, 0xcab3,
+  0x73b5, 0xc946, 0x7307, 0xc7dc, 0x7255, 0xc674, 0x719e, 0xc50e,
+  0x70e2, 0xc3aa, 0x7023, 0xc248, 0x6f5f, 0xc0e9, 0x6e96, 0xbf8d,
+  0x6dca, 0xbe32, 0x6cf9, 0xbcdb, 0x6c24, 0xbb86, 0x6b4a, 0xba33,
+  0x6a6d, 0xb8e4, 0x698c, 0xb797, 0x68a6, 0xb64c, 0x67bd, 0xb505,
+  0x66cf, 0xb3c1, 0x65dd, 0xb27f, 0x64e8, 0xb141, 0x63ef, 0xb005,
+  0x62f2, 0xaecd, 0x61f1, 0xad97, 0x60ec, 0xac65, 0x5fe3, 0xab36,
+  0x5ed7, 0xaa0b, 0x5dc7, 0xa8e3, 0x5cb4, 0xa7be, 0x5b9d, 0xa69c,
+  0x5a82, 0xa57e, 0x5964, 0xa463, 0x5842, 0xa34c, 0x571d, 0xa239,
+  0x55f5, 0xa129, 0x54ca, 0xa01d, 0x539b, 0x9f14, 0x5269, 0x9e0f,
+  0x5133, 0x9d0e, 0x4ffb, 0x9c11, 0x4ebf, 0x9b18, 0x4d81, 0x9a23,
+  0x4c3f, 0x9931, 0x4afb, 0x9843, 0x49b4, 0x975a, 0x4869, 0x9674,
+  0x471c, 0x9593, 0x45cd, 0x94b6, 0x447a, 0x93dc, 0x4325, 0x9307,
+  0x41ce, 0x9236, 0x4073, 0x916a, 0x3f17, 0x90a1, 0x3db8, 0x8fdd,
+  0x3c56, 0x8f1e, 0x3af2, 0x8e62, 0x398c, 0x8dab, 0x3824, 0x8cf9,
+  0x36ba, 0x8c4b, 0x354d, 0x8ba1, 0x33de, 0x8afc, 0x326e, 0x8a5b,
+  0x30fb, 0x89bf, 0x2f87, 0x8927, 0x2e11, 0x8894, 0x2c98, 0x8806,
+  0x2b1f, 0x877c, 0x29a3, 0x86f7, 0x2826, 0x8676, 0x26a8, 0x85fb,
+  0x2528, 0x8583, 0x23a6, 0x8511, 0x2223, 0x84a3, 0x209f, 0x843b,
+  0x1f19, 0x83d7, 0x1d93, 0x8377, 0x1c0b, 0x831d, 0x1a82, 0x82c7,
+  0x18f8, 0x8276, 0x176d, 0x822a, 0x15e2, 0x81e3, 0x1455, 0x81a1,
+  0x12c8, 0x8163, 0x1139, 0x812b, 0xfab, 0x80f7, 0xe1b, 0x80c8,
+  0xc8b, 0x809e, 0xafb, 0x8079, 0x96a, 0x8059, 0x7d9, 0x803e,
+  0x647, 0x8028, 0x4b6, 0x8017, 0x324, 0x800a, 0x192, 0x8003,
+};
+
+static const q15_t WeightsQ15_512[1024] = {
+  0x7fff, 0x0, 0x7fff, 0xff9c, 0x7fff, 0xff37, 0x7ffe, 0xfed3,
+  0x7ffd, 0xfe6e, 0x7ffc, 0xfe0a, 0x7ffa, 0xfda5, 0x7ff8, 0xfd41,
+  0x7ff6, 0xfcdc, 0x7ff3, 0xfc78, 0x7ff0, 0xfc13, 0x7fed, 0xfbaf,
+  0x7fe9, 0xfb4a, 0x7fe5, 0xfae6, 0x7fe1, 0xfa81, 0x7fdd, 0xfa1d,
+  0x7fd8, 0xf9b9, 0x7fd3, 0xf954, 0x7fce, 0xf8f0, 0x7fc8, 0xf88b,
+  0x7fc2, 0xf827, 0x7fbc, 0xf7c3, 0x7fb5, 0xf75e, 0x7fae, 0xf6fa,
+  0x7fa7, 0xf696, 0x7f9f, 0xf632, 0x7f97, 0xf5cd, 0x7f8f, 0xf569,
+  0x7f87, 0xf505, 0x7f7e, 0xf4a1, 0x7f75, 0xf43d, 0x7f6b, 0xf3d9,
+  0x7f62, 0xf375, 0x7f58, 0xf311, 0x7f4d, 0xf2ad, 0x7f43, 0xf249,
+  0x7f38, 0xf1e5, 0x7f2d, 0xf181, 0x7f21, 0xf11d, 0x7f15, 0xf0b9,
+  0x7f09, 0xf055, 0x7efd, 0xeff2, 0x7ef0, 0xef8e, 0x7ee3, 0xef2a,
+  0x7ed5, 0xeec7, 0x7ec8, 0xee63, 0x7eba, 0xedff, 0x7eab, 0xed9c,
+  0x7e9d, 0xed38, 0x7e8e, 0xecd5, 0x7e7f, 0xec72, 0x7e6f, 0xec0e,
+  0x7e5f, 0xebab, 0x7e4f, 0xeb48, 0x7e3f, 0xeae5, 0x7e2e, 0xea81,
+  0x7e1d, 0xea1e, 0x7e0c, 0xe9bb, 0x7dfa, 0xe958, 0x7de8, 0xe8f6,
+  0x7dd6, 0xe893, 0x7dc3, 0xe830, 0x7db0, 0xe7cd, 0x7d9d, 0xe76a,
+  0x7d8a, 0xe708, 0x7d76, 0xe6a5, 0x7d62, 0xe643, 0x7d4e, 0xe5e0,
+  0x7d39, 0xe57e, 0x7d24, 0xe51c, 0x7d0f, 0xe4b9, 0x7cf9, 0xe457,
+  0x7ce3, 0xe3f5, 0x7ccd, 0xe393, 0x7cb7, 0xe331, 0x7ca0, 0xe2cf,
+  0x7c89, 0xe26d, 0x7c71, 0xe20b, 0x7c5a, 0xe1aa, 0x7c42, 0xe148,
+  0x7c29, 0xe0e7, 0x7c11, 0xe085, 0x7bf8, 0xe024, 0x7bdf, 0xdfc2,
+  0x7bc5, 0xdf61, 0x7bac, 0xdf00, 0x7b92, 0xde9f, 0x7b77, 0xde3e,
+  0x7b5d, 0xdddd, 0x7b42, 0xdd7c, 0x7b26, 0xdd1b, 0x7b0b, 0xdcbb,
+  0x7aef, 0xdc5a, 0x7ad3, 0xdbf9, 0x7ab6, 0xdb99, 0x7a9a, 0xdb39,
+  0x7a7d, 0xdad8, 0x7a5f, 0xda78, 0x7a42, 0xda18, 0x7a24, 0xd9b8,
+  0x7a05, 0xd958, 0x79e7, 0xd8f9, 0x79c8, 0xd899, 0x79a9, 0xd839,
+  0x798a, 0xd7da, 0x796a, 0xd77a, 0x794a, 0xd71b, 0x792a, 0xd6bc,
+  0x7909, 0xd65d, 0x78e8, 0xd5fe, 0x78c7, 0xd59f, 0x78a6, 0xd540,
+  0x7884, 0xd4e1, 0x7862, 0xd483, 0x7840, 0xd424, 0x781d, 0xd3c6,
+  0x77fa, 0xd368, 0x77d7, 0xd309, 0x77b4, 0xd2ab, 0x7790, 0xd24d,
+  0x776c, 0xd1ef, 0x7747, 0xd192, 0x7723, 0xd134, 0x76fe, 0xd0d7,
+  0x76d9, 0xd079, 0x76b3, 0xd01c, 0x768e, 0xcfbf, 0x7668, 0xcf62,
+  0x7641, 0xcf05, 0x761b, 0xcea8, 0x75f4, 0xce4b, 0x75cc, 0xcdef,
+  0x75a5, 0xcd92, 0x757d, 0xcd36, 0x7555, 0xccda, 0x752d, 0xcc7e,
+  0x7504, 0xcc22, 0x74db, 0xcbc6, 0x74b2, 0xcb6a, 0x7489, 0xcb0e,
+  0x745f, 0xcab3, 0x7435, 0xca58, 0x740b, 0xc9fc, 0x73e0, 0xc9a1,
+  0x73b5, 0xc946, 0x738a, 0xc8ec, 0x735f, 0xc891, 0x7333, 0xc836,
+  0x7307, 0xc7dc, 0x72db, 0xc782, 0x72af, 0xc728, 0x7282, 0xc6ce,
+  0x7255, 0xc674, 0x7227, 0xc61a, 0x71fa, 0xc5c0, 0x71cc, 0xc567,
+  0x719e, 0xc50e, 0x716f, 0xc4b4, 0x7141, 0xc45b, 0x7112, 0xc403,
+  0x70e2, 0xc3aa, 0x70b3, 0xc351, 0x7083, 0xc2f9, 0x7053, 0xc2a0,
+  0x7023, 0xc248, 0x6ff2, 0xc1f0, 0x6fc1, 0xc198, 0x6f90, 0xc141,
+  0x6f5f, 0xc0e9, 0x6f2d, 0xc092, 0x6efb, 0xc03b, 0x6ec9, 0xbfe3,
+  0x6e96, 0xbf8d, 0x6e63, 0xbf36, 0x6e30, 0xbedf, 0x6dfd, 0xbe89,
+  0x6dca, 0xbe32, 0x6d96, 0xbddc, 0x6d62, 0xbd86, 0x6d2d, 0xbd30,
+  0x6cf9, 0xbcdb, 0x6cc4, 0xbc85, 0x6c8f, 0xbc30, 0x6c59, 0xbbdb,
+  0x6c24, 0xbb86, 0x6bee, 0xbb31, 0x6bb8, 0xbadc, 0x6b81, 0xba88,
+  0x6b4a, 0xba33, 0x6b13, 0xb9df, 0x6adc, 0xb98b, 0x6aa5, 0xb937,
+  0x6a6d, 0xb8e4, 0x6a35, 0xb890, 0x69fd, 0xb83d, 0x69c4, 0xb7ea,
+  0x698c, 0xb797, 0x6953, 0xb744, 0x6919, 0xb6f1, 0x68e0, 0xb69f,
+  0x68a6, 0xb64c, 0x686c, 0xb5fa, 0x6832, 0xb5a8, 0x67f7, 0xb557,
+  0x67bd, 0xb505, 0x6782, 0xb4b4, 0x6746, 0xb462, 0x670b, 0xb411,
+  0x66cf, 0xb3c1, 0x6693, 0xb370, 0x6657, 0xb31f, 0x661a, 0xb2cf,
+  0x65dd, 0xb27f, 0x65a0, 0xb22f, 0x6563, 0xb1df, 0x6526, 0xb190,
+  0x64e8, 0xb141, 0x64aa, 0xb0f1, 0x646c, 0xb0a2, 0x642d, 0xb054,
+  0x63ef, 0xb005, 0x63b0, 0xafb7, 0x6371, 0xaf69, 0x6331, 0xaf1b,
+  0x62f2, 0xaecd, 0x62b2, 0xae7f, 0x6271, 0xae32, 0x6231, 0xade4,
+  0x61f1, 0xad97, 0x61b0, 0xad4b, 0x616f, 0xacfe, 0x612d, 0xacb2,
+  0x60ec, 0xac65, 0x60aa, 0xac19, 0x6068, 0xabcd, 0x6026, 0xab82,
+  0x5fe3, 0xab36, 0x5fa0, 0xaaeb, 0x5f5e, 0xaaa0, 0x5f1a, 0xaa55,
+  0x5ed7, 0xaa0b, 0x5e93, 0xa9c0, 0x5e50, 0xa976, 0x5e0b, 0xa92c,
+  0x5dc7, 0xa8e3, 0x5d83, 0xa899, 0x5d3e, 0xa850, 0x5cf9, 0xa807,
+  0x5cb4, 0xa7be, 0x5c6e, 0xa775, 0x5c29, 0xa72c, 0x5be3, 0xa6e4,
+  0x5b9d, 0xa69c, 0x5b56, 0xa654, 0x5b10, 0xa60d, 0x5ac9, 0xa5c5,
+  0x5a82, 0xa57e, 0x5a3b, 0xa537, 0x59f3, 0xa4f0, 0x59ac, 0xa4aa,
+  0x5964, 0xa463, 0x591c, 0xa41d, 0x58d4, 0xa3d7, 0x588b, 0xa392,
+  0x5842, 0xa34c, 0x57f9, 0xa307, 0x57b0, 0xa2c2, 0x5767, 0xa27d,
+  0x571d, 0xa239, 0x56d4, 0xa1f5, 0x568a, 0xa1b0, 0x5640, 0xa16d,
+  0x55f5, 0xa129, 0x55ab, 0xa0e6, 0x5560, 0xa0a2, 0x5515, 0xa060,
+  0x54ca, 0xa01d, 0x547e, 0x9fda, 0x5433, 0x9f98, 0x53e7, 0x9f56,
+  0x539b, 0x9f14, 0x534e, 0x9ed3, 0x5302, 0x9e91, 0x52b5, 0x9e50,
+  0x5269, 0x9e0f, 0x521c, 0x9dcf, 0x51ce, 0x9d8f, 0x5181, 0x9d4e,
+  0x5133, 0x9d0e, 0x50e5, 0x9ccf, 0x5097, 0x9c8f, 0x5049, 0x9c50,
+  0x4ffb, 0x9c11, 0x4fac, 0x9bd3, 0x4f5e, 0x9b94, 0x4f0f, 0x9b56,
+  0x4ebf, 0x9b18, 0x4e70, 0x9ada, 0x4e21, 0x9a9d, 0x4dd1, 0x9a60,
+  0x4d81, 0x9a23, 0x4d31, 0x99e6, 0x4ce1, 0x99a9, 0x4c90, 0x996d,
+  0x4c3f, 0x9931, 0x4bef, 0x98f5, 0x4b9e, 0x98ba, 0x4b4c, 0x987e,
+  0x4afb, 0x9843, 0x4aa9, 0x9809, 0x4a58, 0x97ce, 0x4a06, 0x9794,
+  0x49b4, 0x975a, 0x4961, 0x9720, 0x490f, 0x96e7, 0x48bc, 0x96ad,
+  0x4869, 0x9674, 0x4816, 0x963c, 0x47c3, 0x9603, 0x4770, 0x95cb,
+  0x471c, 0x9593, 0x46c9, 0x955b, 0x4675, 0x9524, 0x4621, 0x94ed,
+  0x45cd, 0x94b6, 0x4578, 0x947f, 0x4524, 0x9448, 0x44cf, 0x9412,
+  0x447a, 0x93dc, 0x4425, 0x93a7, 0x43d0, 0x9371, 0x437b, 0x933c,
+  0x4325, 0x9307, 0x42d0, 0x92d3, 0x427a, 0x929e, 0x4224, 0x926a,
+  0x41ce, 0x9236, 0x4177, 0x9203, 0x4121, 0x91d0, 0x40ca, 0x919d,
+  0x4073, 0x916a, 0x401d, 0x9137, 0x3fc5, 0x9105, 0x3f6e, 0x90d3,
+  0x3f17, 0x90a1, 0x3ebf, 0x9070, 0x3e68, 0x903f, 0x3e10, 0x900e,
+  0x3db8, 0x8fdd, 0x3d60, 0x8fad, 0x3d07, 0x8f7d, 0x3caf, 0x8f4d,
+  0x3c56, 0x8f1e, 0x3bfd, 0x8eee, 0x3ba5, 0x8ebf, 0x3b4c, 0x8e91,
+  0x3af2, 0x8e62, 0x3a99, 0x8e34, 0x3a40, 0x8e06, 0x39e6, 0x8dd9,
+  0x398c, 0x8dab, 0x3932, 0x8d7e, 0x38d8, 0x8d51, 0x387e, 0x8d25,
+  0x3824, 0x8cf9, 0x37ca, 0x8ccd, 0x376f, 0x8ca1, 0x3714, 0x8c76,
+  0x36ba, 0x8c4b, 0x365f, 0x8c20, 0x3604, 0x8bf5, 0x35a8, 0x8bcb,
+  0x354d, 0x8ba1, 0x34f2, 0x8b77, 0x3496, 0x8b4e, 0x343a, 0x8b25,
+  0x33de, 0x8afc, 0x3382, 0x8ad3, 0x3326, 0x8aab, 0x32ca, 0x8a83,
+  0x326e, 0x8a5b, 0x3211, 0x8a34, 0x31b5, 0x8a0c, 0x3158, 0x89e5,
+  0x30fb, 0x89bf, 0x309e, 0x8998, 0x3041, 0x8972, 0x2fe4, 0x894d,
+  0x2f87, 0x8927, 0x2f29, 0x8902, 0x2ecc, 0x88dd, 0x2e6e, 0x88b9,
+  0x2e11, 0x8894, 0x2db3, 0x8870, 0x2d55, 0x884c, 0x2cf7, 0x8829,
+  0x2c98, 0x8806, 0x2c3a, 0x87e3, 0x2bdc, 0x87c0, 0x2b7d, 0x879e,
+  0x2b1f, 0x877c, 0x2ac0, 0x875a, 0x2a61, 0x8739, 0x2a02, 0x8718,
+  0x29a3, 0x86f7, 0x2944, 0x86d6, 0x28e5, 0x86b6, 0x2886, 0x8696,
+  0x2826, 0x8676, 0x27c7, 0x8657, 0x2767, 0x8638, 0x2707, 0x8619,
+  0x26a8, 0x85fb, 0x2648, 0x85dc, 0x25e8, 0x85be, 0x2588, 0x85a1,
+  0x2528, 0x8583, 0x24c7, 0x8566, 0x2467, 0x854a, 0x2407, 0x852d,
+  0x23a6, 0x8511, 0x2345, 0x84f5, 0x22e5, 0x84da, 0x2284, 0x84be,
+  0x2223, 0x84a3, 0x21c2, 0x8489, 0x2161, 0x846e, 0x2100, 0x8454,
+  0x209f, 0x843b, 0x203e, 0x8421, 0x1fdc, 0x8408, 0x1f7b, 0x83ef,
+  0x1f19, 0x83d7, 0x1eb8, 0x83be, 0x1e56, 0x83a6, 0x1df5, 0x838f,
+  0x1d93, 0x8377, 0x1d31, 0x8360, 0x1ccf, 0x8349, 0x1c6d, 0x8333,
+  0x1c0b, 0x831d, 0x1ba9, 0x8307, 0x1b47, 0x82f1, 0x1ae4, 0x82dc,
+  0x1a82, 0x82c7, 0x1a20, 0x82b2, 0x19bd, 0x829e, 0x195b, 0x828a,
+  0x18f8, 0x8276, 0x1896, 0x8263, 0x1833, 0x8250, 0x17d0, 0x823d,
+  0x176d, 0x822a, 0x170a, 0x8218, 0x16a8, 0x8206, 0x1645, 0x81f4,
+  0x15e2, 0x81e3, 0x157f, 0x81d2, 0x151b, 0x81c1, 0x14b8, 0x81b1,
+  0x1455, 0x81a1, 0x13f2, 0x8191, 0x138e, 0x8181, 0x132b, 0x8172,
+  0x12c8, 0x8163, 0x1264, 0x8155, 0x1201, 0x8146, 0x119d, 0x8138,
+  0x1139, 0x812b, 0x10d6, 0x811d, 0x1072, 0x8110, 0x100e, 0x8103,
+  0xfab, 0x80f7, 0xf47, 0x80eb, 0xee3, 0x80df, 0xe7f, 0x80d3,
+  0xe1b, 0x80c8, 0xdb7, 0x80bd, 0xd53, 0x80b3, 0xcef, 0x80a8,
+  0xc8b, 0x809e, 0xc27, 0x8095, 0xbc3, 0x808b, 0xb5f, 0x8082,
+  0xafb, 0x8079, 0xa97, 0x8071, 0xa33, 0x8069, 0x9ce, 0x8061,
+  0x96a, 0x8059, 0x906, 0x8052, 0x8a2, 0x804b, 0x83d, 0x8044,
+  0x7d9, 0x803e, 0x775, 0x8038, 0x710, 0x8032, 0x6ac, 0x802d,
+  0x647, 0x8028, 0x5e3, 0x8023, 0x57f, 0x801f, 0x51a, 0x801b,
+  0x4b6, 0x8017, 0x451, 0x8013, 0x3ed, 0x8010, 0x388, 0x800d,
+  0x324, 0x800a, 0x2bf, 0x8008, 0x25b, 0x8006, 0x1f6, 0x8004,
+  0x192, 0x8003, 0x12d, 0x8002, 0xc9, 0x8001, 0x64, 0x8001,
+};
+
+static const q15_t WeightsQ15_2048[4096] = {
+  0x7fff, 0x0, 0x7fff, 0xffe7, 0x7fff, 0xffce, 0x7fff, 0xffb5,
+  0x7fff, 0xff9c, 0x7fff, 0xff83, 0x7fff, 0xff6a, 0x7fff, 0xff51,
+  0x7fff, 0xff37, 0x7fff, 0xff1e, 0x7fff, 0xff05, 0x7ffe, 0xfeec,
+  0x7ffe, 0xfed3, 0x7ffe, 0xfeba, 0x7ffe, 0xfea1, 0x7ffd, 0xfe88,
+  0x7ffd, 0xfe6e, 0x7ffd, 0xfe55, 0x7ffc, 0xfe3c, 0x7ffc, 0xfe23,
+  0x7ffc, 0xfe0a, 0x7ffb, 0xfdf1, 0x7ffb, 0xfdd8, 0x7ffa, 0xfdbe,
+  0x7ffa, 0xfda5, 0x7ff9, 0xfd8c, 0x7ff9, 0xfd73, 0x7ff8, 0xfd5a,
+  0x7ff8, 0xfd41, 0x7ff7, 0xfd28, 0x7ff7, 0xfd0f, 0x7ff6, 0xfcf5,
+  0x7ff6, 0xfcdc, 0x7ff5, 0xfcc3, 0x7ff4, 0xfcaa, 0x7ff4, 0xfc91,
+  0x7ff3, 0xfc78, 0x7ff2, 0xfc5f, 0x7ff2, 0xfc46, 0x7ff1, 0xfc2c,
+  0x7ff0, 0xfc13, 0x7fef, 0xfbfa, 0x7fee, 0xfbe1, 0x7fee, 0xfbc8,
+  0x7fed, 0xfbaf, 0x7fec, 0xfb96, 0x7feb, 0xfb7d, 0x7fea, 0xfb64,
+  0x7fe9, 0xfb4a, 0x7fe8, 0xfb31, 0x7fe7, 0xfb18, 0x7fe6, 0xfaff,
+  0x7fe5, 0xfae6, 0x7fe4, 0xfacd, 0x7fe3, 0xfab4, 0x7fe2, 0xfa9b,
+  0x7fe1, 0xfa81, 0x7fe0, 0xfa68, 0x7fdf, 0xfa4f, 0x7fde, 0xfa36,
+  0x7fdd, 0xfa1d, 0x7fdc, 0xfa04, 0x7fda, 0xf9eb, 0x7fd9, 0xf9d2,
+  0x7fd8, 0xf9b9, 0x7fd7, 0xf9a0, 0x7fd6, 0xf986, 0x7fd4, 0xf96d,
+  0x7fd3, 0xf954, 0x7fd2, 0xf93b, 0x7fd0, 0xf922, 0x7fcf, 0xf909,
+  0x7fce, 0xf8f0, 0x7fcc, 0xf8d7, 0x7fcb, 0xf8be, 0x7fc9, 0xf8a5,
+  0x7fc8, 0xf88b, 0x7fc6, 0xf872, 0x7fc5, 0xf859, 0x7fc3, 0xf840,
+  0x7fc2, 0xf827, 0x7fc0, 0xf80e, 0x7fbf, 0xf7f5, 0x7fbd, 0xf7dc,
+  0x7fbc, 0xf7c3, 0x7fba, 0xf7aa, 0x7fb8, 0xf791, 0x7fb7, 0xf778,
+  0x7fb5, 0xf75e, 0x7fb3, 0xf745, 0x7fb1, 0xf72c, 0x7fb0, 0xf713,
+  0x7fae, 0xf6fa, 0x7fac, 0xf6e1, 0x7faa, 0xf6c8, 0x7fa9, 0xf6af,
+  0x7fa7, 0xf696, 0x7fa5, 0xf67d, 0x7fa3, 0xf664, 0x7fa1, 0xf64b,
+  0x7f9f, 0xf632, 0x7f9d, 0xf619, 0x7f9b, 0xf600, 0x7f99, 0xf5e7,
+  0x7f97, 0xf5cd, 0x7f95, 0xf5b4, 0x7f93, 0xf59b, 0x7f91, 0xf582,
+  0x7f8f, 0xf569, 0x7f8d, 0xf550, 0x7f8b, 0xf537, 0x7f89, 0xf51e,
+  0x7f87, 0xf505, 0x7f85, 0xf4ec, 0x7f82, 0xf4d3, 0x7f80, 0xf4ba,
+  0x7f7e, 0xf4a1, 0x7f7c, 0xf488, 0x7f79, 0xf46f, 0x7f77, 0xf456,
+  0x7f75, 0xf43d, 0x7f72, 0xf424, 0x7f70, 0xf40b, 0x7f6e, 0xf3f2,
+  0x7f6b, 0xf3d9, 0x7f69, 0xf3c0, 0x7f67, 0xf3a7, 0x7f64, 0xf38e,
+  0x7f62, 0xf375, 0x7f5f, 0xf35c, 0x7f5d, 0xf343, 0x7f5a, 0xf32a,
+  0x7f58, 0xf311, 0x7f55, 0xf2f8, 0x7f53, 0xf2df, 0x7f50, 0xf2c6,
+  0x7f4d, 0xf2ad, 0x7f4b, 0xf294, 0x7f48, 0xf27b, 0x7f45, 0xf262,
+  0x7f43, 0xf249, 0x7f40, 0xf230, 0x7f3d, 0xf217, 0x7f3b, 0xf1fe,
+  0x7f38, 0xf1e5, 0x7f35, 0xf1cc, 0x7f32, 0xf1b3, 0x7f2f, 0xf19a,
+  0x7f2d, 0xf181, 0x7f2a, 0xf168, 0x7f27, 0xf14f, 0x7f24, 0xf136,
+  0x7f21, 0xf11d, 0x7f1e, 0xf104, 0x7f1b, 0xf0eb, 0x7f18, 0xf0d2,
+  0x7f15, 0xf0b9, 0x7f12, 0xf0a0, 0x7f0f, 0xf087, 0x7f0c, 0xf06e,
+  0x7f09, 0xf055, 0x7f06, 0xf03c, 0x7f03, 0xf023, 0x7f00, 0xf00b,
+  0x7efd, 0xeff2, 0x7ef9, 0xefd9, 0x7ef6, 0xefc0, 0x7ef3, 0xefa7,
+  0x7ef0, 0xef8e, 0x7eed, 0xef75, 0x7ee9, 0xef5c, 0x7ee6, 0xef43,
+  0x7ee3, 0xef2a, 0x7edf, 0xef11, 0x7edc, 0xeef8, 0x7ed9, 0xeedf,
+  0x7ed5, 0xeec7, 0x7ed2, 0xeeae, 0x7ecf, 0xee95, 0x7ecb, 0xee7c,
+  0x7ec8, 0xee63, 0x7ec4, 0xee4a, 0x7ec1, 0xee31, 0x7ebd, 0xee18,
+  0x7eba, 0xedff, 0x7eb6, 0xede7, 0x7eb3, 0xedce, 0x7eaf, 0xedb5,
+  0x7eab, 0xed9c, 0x7ea8, 0xed83, 0x7ea4, 0xed6a, 0x7ea1, 0xed51,
+  0x7e9d, 0xed38, 0x7e99, 0xed20, 0x7e95, 0xed07, 0x7e92, 0xecee,
+  0x7e8e, 0xecd5, 0x7e8a, 0xecbc, 0x7e86, 0xeca3, 0x7e83, 0xec8a,
+  0x7e7f, 0xec72, 0x7e7b, 0xec59, 0x7e77, 0xec40, 0x7e73, 0xec27,
+  0x7e6f, 0xec0e, 0x7e6b, 0xebf5, 0x7e67, 0xebdd, 0x7e63, 0xebc4,
+  0x7e5f, 0xebab, 0x7e5b, 0xeb92, 0x7e57, 0xeb79, 0x7e53, 0xeb61,
+  0x7e4f, 0xeb48, 0x7e4b, 0xeb2f, 0x7e47, 0xeb16, 0x7e43, 0xeafd,
+  0x7e3f, 0xeae5, 0x7e3b, 0xeacc, 0x7e37, 0xeab3, 0x7e32, 0xea9a,
+  0x7e2e, 0xea81, 0x7e2a, 0xea69, 0x7e26, 0xea50, 0x7e21, 0xea37,
+  0x7e1d, 0xea1e, 0x7e19, 0xea06, 0x7e14, 0xe9ed, 0x7e10, 0xe9d4,
+  0x7e0c, 0xe9bb, 0x7e07, 0xe9a3, 0x7e03, 0xe98a, 0x7dff, 0xe971,
+  0x7dfa, 0xe958, 0x7df6, 0xe940, 0x7df1, 0xe927, 0x7ded, 0xe90e,
+  0x7de8, 0xe8f6, 0x7de4, 0xe8dd, 0x7ddf, 0xe8c4, 0x7dda, 0xe8ab,
+  0x7dd6, 0xe893, 0x7dd1, 0xe87a, 0x7dcd, 0xe861, 0x7dc8, 0xe849,
+  0x7dc3, 0xe830, 0x7dbf, 0xe817, 0x7dba, 0xe7fe, 0x7db5, 0xe7e6,
+  0x7db0, 0xe7cd, 0x7dac, 0xe7b4, 0x7da7, 0xe79c, 0x7da2, 0xe783,
+  0x7d9d, 0xe76a, 0x7d98, 0xe752, 0x7d94, 0xe739, 0x7d8f, 0xe720,
+  0x7d8a, 0xe708, 0x7d85, 0xe6ef, 0x7d80, 0xe6d6, 0x7d7b, 0xe6be,
+  0x7d76, 0xe6a5, 0x7d71, 0xe68d, 0x7d6c, 0xe674, 0x7d67, 0xe65b,
+  0x7d62, 0xe643, 0x7d5d, 0xe62a, 0x7d58, 0xe611, 0x7d53, 0xe5f9,
+  0x7d4e, 0xe5e0, 0x7d49, 0xe5c8, 0x7d43, 0xe5af, 0x7d3e, 0xe596,
+  0x7d39, 0xe57e, 0x7d34, 0xe565, 0x7d2f, 0xe54d, 0x7d29, 0xe534,
+  0x7d24, 0xe51c, 0x7d1f, 0xe503, 0x7d19, 0xe4ea, 0x7d14, 0xe4d2,
+  0x7d0f, 0xe4b9, 0x7d09, 0xe4a1, 0x7d04, 0xe488, 0x7cff, 0xe470,
+  0x7cf9, 0xe457, 0x7cf4, 0xe43f, 0x7cee, 0xe426, 0x7ce9, 0xe40e,
+  0x7ce3, 0xe3f5, 0x7cde, 0xe3dc, 0x7cd8, 0xe3c4, 0x7cd3, 0xe3ab,
+  0x7ccd, 0xe393, 0x7cc8, 0xe37a, 0x7cc2, 0xe362, 0x7cbc, 0xe349,
+  0x7cb7, 0xe331, 0x7cb1, 0xe318, 0x7cab, 0xe300, 0x7ca6, 0xe2e8,
+  0x7ca0, 0xe2cf, 0x7c9a, 0xe2b7, 0x7c94, 0xe29e, 0x7c8f, 0xe286,
+  0x7c89, 0xe26d, 0x7c83, 0xe255, 0x7c7d, 0xe23c, 0x7c77, 0xe224,
+  0x7c71, 0xe20b, 0x7c6c, 0xe1f3, 0x7c66, 0xe1db, 0x7c60, 0xe1c2,
+  0x7c5a, 0xe1aa, 0x7c54, 0xe191, 0x7c4e, 0xe179, 0x7c48, 0xe160,
+  0x7c42, 0xe148, 0x7c3c, 0xe130, 0x7c36, 0xe117, 0x7c30, 0xe0ff,
+  0x7c29, 0xe0e7, 0x7c23, 0xe0ce, 0x7c1d, 0xe0b6, 0x7c17, 0xe09d,
+  0x7c11, 0xe085, 0x7c0b, 0xe06d, 0x7c05, 0xe054, 0x7bfe, 0xe03c,
+  0x7bf8, 0xe024, 0x7bf2, 0xe00b, 0x7beb, 0xdff3, 0x7be5, 0xdfdb,
+  0x7bdf, 0xdfc2, 0x7bd9, 0xdfaa, 0x7bd2, 0xdf92, 0x7bcc, 0xdf79,
+  0x7bc5, 0xdf61, 0x7bbf, 0xdf49, 0x7bb9, 0xdf30, 0x7bb2, 0xdf18,
+  0x7bac, 0xdf00, 0x7ba5, 0xdee8, 0x7b9f, 0xdecf, 0x7b98, 0xdeb7,
+  0x7b92, 0xde9f, 0x7b8b, 0xde87, 0x7b84, 0xde6e, 0x7b7e, 0xde56,
+  0x7b77, 0xde3e, 0x7b71, 0xde26, 0x7b6a, 0xde0d, 0x7b63, 0xddf5,
+  0x7b5d, 0xdddd, 0x7b56, 0xddc5, 0x7b4f, 0xddac, 0x7b48, 0xdd94,
+  0x7b42, 0xdd7c, 0x7b3b, 0xdd64, 0x7b34, 0xdd4c, 0x7b2d, 0xdd33,
+  0x7b26, 0xdd1b, 0x7b1f, 0xdd03, 0x7b19, 0xdceb, 0x7b12, 0xdcd3,
+  0x7b0b, 0xdcbb, 0x7b04, 0xdca2, 0x7afd, 0xdc8a, 0x7af6, 0xdc72,
+  0x7aef, 0xdc5a, 0x7ae8, 0xdc42, 0x7ae1, 0xdc2a, 0x7ada, 0xdc12,
+  0x7ad3, 0xdbf9, 0x7acc, 0xdbe1, 0x7ac5, 0xdbc9, 0x7abd, 0xdbb1,
+  0x7ab6, 0xdb99, 0x7aaf, 0xdb81, 0x7aa8, 0xdb69, 0x7aa1, 0xdb51,
+  0x7a9a, 0xdb39, 0x7a92, 0xdb21, 0x7a8b, 0xdb09, 0x7a84, 0xdaf1,
+  0x7a7d, 0xdad8, 0x7a75, 0xdac0, 0x7a6e, 0xdaa8, 0x7a67, 0xda90,
+  0x7a5f, 0xda78, 0x7a58, 0xda60, 0x7a50, 0xda48, 0x7a49, 0xda30,
+  0x7a42, 0xda18, 0x7a3a, 0xda00, 0x7a33, 0xd9e8, 0x7a2b, 0xd9d0,
+  0x7a24, 0xd9b8, 0x7a1c, 0xd9a0, 0x7a15, 0xd988, 0x7a0d, 0xd970,
+  0x7a05, 0xd958, 0x79fe, 0xd940, 0x79f6, 0xd928, 0x79ef, 0xd911,
+  0x79e7, 0xd8f9, 0x79df, 0xd8e1, 0x79d8, 0xd8c9, 0x79d0, 0xd8b1,
+  0x79c8, 0xd899, 0x79c0, 0xd881, 0x79b9, 0xd869, 0x79b1, 0xd851,
+  0x79a9, 0xd839, 0x79a1, 0xd821, 0x7999, 0xd80a, 0x7992, 0xd7f2,
+  0x798a, 0xd7da, 0x7982, 0xd7c2, 0x797a, 0xd7aa, 0x7972, 0xd792,
+  0x796a, 0xd77a, 0x7962, 0xd763, 0x795a, 0xd74b, 0x7952, 0xd733,
+  0x794a, 0xd71b, 0x7942, 0xd703, 0x793a, 0xd6eb, 0x7932, 0xd6d4,
+  0x792a, 0xd6bc, 0x7922, 0xd6a4, 0x7919, 0xd68c, 0x7911, 0xd675,
+  0x7909, 0xd65d, 0x7901, 0xd645, 0x78f9, 0xd62d, 0x78f1, 0xd615,
+  0x78e8, 0xd5fe, 0x78e0, 0xd5e6, 0x78d8, 0xd5ce, 0x78cf, 0xd5b7,
+  0x78c7, 0xd59f, 0x78bf, 0xd587, 0x78b6, 0xd56f, 0x78ae, 0xd558,
+  0x78a6, 0xd540, 0x789d, 0xd528, 0x7895, 0xd511, 0x788c, 0xd4f9,
+  0x7884, 0xd4e1, 0x787c, 0xd4ca, 0x7873, 0xd4b2, 0x786b, 0xd49a,
+  0x7862, 0xd483, 0x7859, 0xd46b, 0x7851, 0xd453, 0x7848, 0xd43c,
+  0x7840, 0xd424, 0x7837, 0xd40d, 0x782e, 0xd3f5, 0x7826, 0xd3dd,
+  0x781d, 0xd3c6, 0x7814, 0xd3ae, 0x780c, 0xd397, 0x7803, 0xd37f,
+  0x77fa, 0xd368, 0x77f1, 0xd350, 0x77e9, 0xd338, 0x77e0, 0xd321,
+  0x77d7, 0xd309, 0x77ce, 0xd2f2, 0x77c5, 0xd2da, 0x77bc, 0xd2c3,
+  0x77b4, 0xd2ab, 0x77ab, 0xd294, 0x77a2, 0xd27c, 0x7799, 0xd265,
+  0x7790, 0xd24d, 0x7787, 0xd236, 0x777e, 0xd21e, 0x7775, 0xd207,
+  0x776c, 0xd1ef, 0x7763, 0xd1d8, 0x775a, 0xd1c1, 0x7751, 0xd1a9,
+  0x7747, 0xd192, 0x773e, 0xd17a, 0x7735, 0xd163, 0x772c, 0xd14b,
+  0x7723, 0xd134, 0x771a, 0xd11d, 0x7710, 0xd105, 0x7707, 0xd0ee,
+  0x76fe, 0xd0d7, 0x76f5, 0xd0bf, 0x76eb, 0xd0a8, 0x76e2, 0xd091,
+  0x76d9, 0xd079, 0x76cf, 0xd062, 0x76c6, 0xd04b, 0x76bd, 0xd033,
+  0x76b3, 0xd01c, 0x76aa, 0xd005, 0x76a0, 0xcfed, 0x7697, 0xcfd6,
+  0x768e, 0xcfbf, 0x7684, 0xcfa7, 0x767b, 0xcf90, 0x7671, 0xcf79,
+  0x7668, 0xcf62, 0x765e, 0xcf4a, 0x7654, 0xcf33, 0x764b, 0xcf1c,
+  0x7641, 0xcf05, 0x7638, 0xceee, 0x762e, 0xced6, 0x7624, 0xcebf,
+  0x761b, 0xcea8, 0x7611, 0xce91, 0x7607, 0xce7a, 0x75fd, 0xce62,
+  0x75f4, 0xce4b, 0x75ea, 0xce34, 0x75e0, 0xce1d, 0x75d6, 0xce06,
+  0x75cc, 0xcdef, 0x75c3, 0xcdd8, 0x75b9, 0xcdc0, 0x75af, 0xcda9,
+  0x75a5, 0xcd92, 0x759b, 0xcd7b, 0x7591, 0xcd64, 0x7587, 0xcd4d,
+  0x757d, 0xcd36, 0x7573, 0xcd1f, 0x7569, 0xcd08, 0x755f, 0xccf1,
+  0x7555, 0xccda, 0x754b, 0xccc3, 0x7541, 0xccac, 0x7537, 0xcc95,
+  0x752d, 0xcc7e, 0x7523, 0xcc67, 0x7519, 0xcc50, 0x750f, 0xcc39,
+  0x7504, 0xcc22, 0x74fa, 0xcc0b, 0x74f0, 0xcbf4, 0x74e6, 0xcbdd,
+  0x74db, 0xcbc6, 0x74d1, 0xcbaf, 0x74c7, 0xcb98, 0x74bd, 0xcb81,
+  0x74b2, 0xcb6a, 0x74a8, 0xcb53, 0x749e, 0xcb3c, 0x7493, 0xcb25,
+  0x7489, 0xcb0e, 0x747e, 0xcaf8, 0x7474, 0xcae1, 0x746a, 0xcaca,
+  0x745f, 0xcab3, 0x7455, 0xca9c, 0x744a, 0xca85, 0x7440, 0xca6e,
+  0x7435, 0xca58, 0x742b, 0xca41, 0x7420, 0xca2a, 0x7415, 0xca13,
+  0x740b, 0xc9fc, 0x7400, 0xc9e6, 0x73f6, 0xc9cf, 0x73eb, 0xc9b8,
+  0x73e0, 0xc9a1, 0x73d6, 0xc98b, 0x73cb, 0xc974, 0x73c0, 0xc95d,
+  0x73b5, 0xc946, 0x73ab, 0xc930, 0x73a0, 0xc919, 0x7395, 0xc902,
+  0x738a, 0xc8ec, 0x737f, 0xc8d5, 0x7375, 0xc8be, 0x736a, 0xc8a8,
+  0x735f, 0xc891, 0x7354, 0xc87a, 0x7349, 0xc864, 0x733e, 0xc84d,
+  0x7333, 0xc836, 0x7328, 0xc820, 0x731d, 0xc809, 0x7312, 0xc7f3,
+  0x7307, 0xc7dc, 0x72fc, 0xc7c5, 0x72f1, 0xc7af, 0x72e6, 0xc798,
+  0x72db, 0xc782, 0x72d0, 0xc76b, 0x72c5, 0xc755, 0x72ba, 0xc73e,
+  0x72af, 0xc728, 0x72a3, 0xc711, 0x7298, 0xc6fa, 0x728d, 0xc6e4,
+  0x7282, 0xc6ce, 0x7276, 0xc6b7, 0x726b, 0xc6a1, 0x7260, 0xc68a,
+  0x7255, 0xc674, 0x7249, 0xc65d, 0x723e, 0xc647, 0x7233, 0xc630,
+  0x7227, 0xc61a, 0x721c, 0xc603, 0x7211, 0xc5ed, 0x7205, 0xc5d7,
+  0x71fa, 0xc5c0, 0x71ee, 0xc5aa, 0x71e3, 0xc594, 0x71d7, 0xc57d,
+  0x71cc, 0xc567, 0x71c0, 0xc551, 0x71b5, 0xc53a, 0x71a9, 0xc524,
+  0x719e, 0xc50e, 0x7192, 0xc4f7, 0x7186, 0xc4e1, 0x717b, 0xc4cb,
+  0x716f, 0xc4b4, 0x7164, 0xc49e, 0x7158, 0xc488, 0x714c, 0xc472,
+  0x7141, 0xc45b, 0x7135, 0xc445, 0x7129, 0xc42f, 0x711d, 0xc419,
+  0x7112, 0xc403, 0x7106, 0xc3ec, 0x70fa, 0xc3d6, 0x70ee, 0xc3c0,
+  0x70e2, 0xc3aa, 0x70d6, 0xc394, 0x70cb, 0xc37d, 0x70bf, 0xc367,
+  0x70b3, 0xc351, 0x70a7, 0xc33b, 0x709b, 0xc325, 0x708f, 0xc30f,
+  0x7083, 0xc2f9, 0x7077, 0xc2e3, 0x706b, 0xc2cd, 0x705f, 0xc2b7,
+  0x7053, 0xc2a0, 0x7047, 0xc28a, 0x703b, 0xc274, 0x702f, 0xc25e,
+  0x7023, 0xc248, 0x7016, 0xc232, 0x700a, 0xc21c, 0x6ffe, 0xc206,
+  0x6ff2, 0xc1f0, 0x6fe6, 0xc1da, 0x6fda, 0xc1c4, 0x6fcd, 0xc1ae,
+  0x6fc1, 0xc198, 0x6fb5, 0xc183, 0x6fa9, 0xc16d, 0x6f9c, 0xc157,
+  0x6f90, 0xc141, 0x6f84, 0xc12b, 0x6f77, 0xc115, 0x6f6b, 0xc0ff,
+  0x6f5f, 0xc0e9, 0x6f52, 0xc0d3, 0x6f46, 0xc0bd, 0x6f39, 0xc0a8,
+  0x6f2d, 0xc092, 0x6f20, 0xc07c, 0x6f14, 0xc066, 0x6f07, 0xc050,
+  0x6efb, 0xc03b, 0x6eee, 0xc025, 0x6ee2, 0xc00f, 0x6ed5, 0xbff9,
+  0x6ec9, 0xbfe3, 0x6ebc, 0xbfce, 0x6eaf, 0xbfb8, 0x6ea3, 0xbfa2,
+  0x6e96, 0xbf8d, 0x6e89, 0xbf77, 0x6e7d, 0xbf61, 0x6e70, 0xbf4b,
+  0x6e63, 0xbf36, 0x6e57, 0xbf20, 0x6e4a, 0xbf0a, 0x6e3d, 0xbef5,
+  0x6e30, 0xbedf, 0x6e24, 0xbeca, 0x6e17, 0xbeb4, 0x6e0a, 0xbe9e,
+  0x6dfd, 0xbe89, 0x6df0, 0xbe73, 0x6de3, 0xbe5e, 0x6dd6, 0xbe48,
+  0x6dca, 0xbe32, 0x6dbd, 0xbe1d, 0x6db0, 0xbe07, 0x6da3, 0xbdf2,
+  0x6d96, 0xbddc, 0x6d89, 0xbdc7, 0x6d7c, 0xbdb1, 0x6d6f, 0xbd9c,
+  0x6d62, 0xbd86, 0x6d55, 0xbd71, 0x6d48, 0xbd5b, 0x6d3a, 0xbd46,
+  0x6d2d, 0xbd30, 0x6d20, 0xbd1b, 0x6d13, 0xbd06, 0x6d06, 0xbcf0,
+  0x6cf9, 0xbcdb, 0x6cec, 0xbcc5, 0x6cde, 0xbcb0, 0x6cd1, 0xbc9b,
+  0x6cc4, 0xbc85, 0x6cb7, 0xbc70, 0x6ca9, 0xbc5b, 0x6c9c, 0xbc45,
+  0x6c8f, 0xbc30, 0x6c81, 0xbc1b, 0x6c74, 0xbc05, 0x6c67, 0xbbf0,
+  0x6c59, 0xbbdb, 0x6c4c, 0xbbc5, 0x6c3f, 0xbbb0, 0x6c31, 0xbb9b,
+  0x6c24, 0xbb86, 0x6c16, 0xbb70, 0x6c09, 0xbb5b, 0x6bfb, 0xbb46,
+  0x6bee, 0xbb31, 0x6be0, 0xbb1c, 0x6bd3, 0xbb06, 0x6bc5, 0xbaf1,
+  0x6bb8, 0xbadc, 0x6baa, 0xbac7, 0x6b9c, 0xbab2, 0x6b8f, 0xba9d,
+  0x6b81, 0xba88, 0x6b73, 0xba73, 0x6b66, 0xba5d, 0x6b58, 0xba48,
+  0x6b4a, 0xba33, 0x6b3d, 0xba1e, 0x6b2f, 0xba09, 0x6b21, 0xb9f4,
+  0x6b13, 0xb9df, 0x6b06, 0xb9ca, 0x6af8, 0xb9b5, 0x6aea, 0xb9a0,
+  0x6adc, 0xb98b, 0x6ace, 0xb976, 0x6ac1, 0xb961, 0x6ab3, 0xb94c,
+  0x6aa5, 0xb937, 0x6a97, 0xb922, 0x6a89, 0xb90d, 0x6a7b, 0xb8f8,
+  0x6a6d, 0xb8e4, 0x6a5f, 0xb8cf, 0x6a51, 0xb8ba, 0x6a43, 0xb8a5,
+  0x6a35, 0xb890, 0x6a27, 0xb87b, 0x6a19, 0xb866, 0x6a0b, 0xb852,
+  0x69fd, 0xb83d, 0x69ef, 0xb828, 0x69e1, 0xb813, 0x69d3, 0xb7fe,
+  0x69c4, 0xb7ea, 0x69b6, 0xb7d5, 0x69a8, 0xb7c0, 0x699a, 0xb7ab,
+  0x698c, 0xb797, 0x697d, 0xb782, 0x696f, 0xb76d, 0x6961, 0xb758,
+  0x6953, 0xb744, 0x6944, 0xb72f, 0x6936, 0xb71a, 0x6928, 0xb706,
+  0x6919, 0xb6f1, 0x690b, 0xb6dd, 0x68fd, 0xb6c8, 0x68ee, 0xb6b3,
+  0x68e0, 0xb69f, 0x68d1, 0xb68a, 0x68c3, 0xb676, 0x68b5, 0xb661,
+  0x68a6, 0xb64c, 0x6898, 0xb638, 0x6889, 0xb623, 0x687b, 0xb60f,
+  0x686c, 0xb5fa, 0x685e, 0xb5e6, 0x684f, 0xb5d1, 0x6840, 0xb5bd,
+  0x6832, 0xb5a8, 0x6823, 0xb594, 0x6815, 0xb57f, 0x6806, 0xb56b,
+  0x67f7, 0xb557, 0x67e9, 0xb542, 0x67da, 0xb52e, 0x67cb, 0xb519,
+  0x67bd, 0xb505, 0x67ae, 0xb4f1, 0x679f, 0xb4dc, 0x6790, 0xb4c8,
+  0x6782, 0xb4b4, 0x6773, 0xb49f, 0x6764, 0xb48b, 0x6755, 0xb477,
+  0x6746, 0xb462, 0x6737, 0xb44e, 0x6729, 0xb43a, 0x671a, 0xb426,
+  0x670b, 0xb411, 0x66fc, 0xb3fd, 0x66ed, 0xb3e9, 0x66de, 0xb3d5,
+  0x66cf, 0xb3c1, 0x66c0, 0xb3ac, 0x66b1, 0xb398, 0x66a2, 0xb384,
+  0x6693, 0xb370, 0x6684, 0xb35c, 0x6675, 0xb348, 0x6666, 0xb334,
+  0x6657, 0xb31f, 0x6648, 0xb30b, 0x6639, 0xb2f7, 0x6629, 0xb2e3,
+  0x661a, 0xb2cf, 0x660b, 0xb2bb, 0x65fc, 0xb2a7, 0x65ed, 0xb293,
+  0x65dd, 0xb27f, 0x65ce, 0xb26b, 0x65bf, 0xb257, 0x65b0, 0xb243,
+  0x65a0, 0xb22f, 0x6591, 0xb21b, 0x6582, 0xb207, 0x6573, 0xb1f3,
+  0x6563, 0xb1df, 0x6554, 0xb1cc, 0x6545, 0xb1b8, 0x6535, 0xb1a4,
+  0x6526, 0xb190, 0x6516, 0xb17c, 0x6507, 0xb168, 0x64f7, 0xb154,
+  0x64e8, 0xb141, 0x64d9, 0xb12d, 0x64c9, 0xb119, 0x64ba, 0xb105,
+  0x64aa, 0xb0f1, 0x649b, 0xb0de, 0x648b, 0xb0ca, 0x647b, 0xb0b6,
+  0x646c, 0xb0a2, 0x645c, 0xb08f, 0x644d, 0xb07b, 0x643d, 0xb067,
+  0x642d, 0xb054, 0x641e, 0xb040, 0x640e, 0xb02c, 0x63fe, 0xb019,
+  0x63ef, 0xb005, 0x63df, 0xaff1, 0x63cf, 0xafde, 0x63c0, 0xafca,
+  0x63b0, 0xafb7, 0x63a0, 0xafa3, 0x6390, 0xaf90, 0x6380, 0xaf7c,
+  0x6371, 0xaf69, 0x6361, 0xaf55, 0x6351, 0xaf41, 0x6341, 0xaf2e,
+  0x6331, 0xaf1b, 0x6321, 0xaf07, 0x6311, 0xaef4, 0x6301, 0xaee0,
+  0x62f2, 0xaecd, 0x62e2, 0xaeb9, 0x62d2, 0xaea6, 0x62c2, 0xae92,
+  0x62b2, 0xae7f, 0x62a2, 0xae6c, 0x6292, 0xae58, 0x6282, 0xae45,
+  0x6271, 0xae32, 0x6261, 0xae1e, 0x6251, 0xae0b, 0x6241, 0xadf8,
+  0x6231, 0xade4, 0x6221, 0xadd1, 0x6211, 0xadbe, 0x6201, 0xadab,
+  0x61f1, 0xad97, 0x61e0, 0xad84, 0x61d0, 0xad71, 0x61c0, 0xad5e,
+  0x61b0, 0xad4b, 0x619f, 0xad37, 0x618f, 0xad24, 0x617f, 0xad11,
+  0x616f, 0xacfe, 0x615e, 0xaceb, 0x614e, 0xacd8, 0x613e, 0xacc5,
+  0x612d, 0xacb2, 0x611d, 0xac9e, 0x610d, 0xac8b, 0x60fc, 0xac78,
+  0x60ec, 0xac65, 0x60db, 0xac52, 0x60cb, 0xac3f, 0x60ba, 0xac2c,
+  0x60aa, 0xac19, 0x6099, 0xac06, 0x6089, 0xabf3, 0x6078, 0xabe0,
+  0x6068, 0xabcd, 0x6057, 0xabbb, 0x6047, 0xaba8, 0x6036, 0xab95,
+  0x6026, 0xab82, 0x6015, 0xab6f, 0x6004, 0xab5c, 0x5ff4, 0xab49,
+  0x5fe3, 0xab36, 0x5fd3, 0xab24, 0x5fc2, 0xab11, 0x5fb1, 0xaafe,
+  0x5fa0, 0xaaeb, 0x5f90, 0xaad8, 0x5f7f, 0xaac6, 0x5f6e, 0xaab3,
+  0x5f5e, 0xaaa0, 0x5f4d, 0xaa8e, 0x5f3c, 0xaa7b, 0x5f2b, 0xaa68,
+  0x5f1a, 0xaa55, 0x5f0a, 0xaa43, 0x5ef9, 0xaa30, 0x5ee8, 0xaa1d,
+  0x5ed7, 0xaa0b, 0x5ec6, 0xa9f8, 0x5eb5, 0xa9e6, 0x5ea4, 0xa9d3,
+  0x5e93, 0xa9c0, 0x5e82, 0xa9ae, 0x5e71, 0xa99b, 0x5e60, 0xa989,
+  0x5e50, 0xa976, 0x5e3f, 0xa964, 0x5e2d, 0xa951, 0x5e1c, 0xa93f,
+  0x5e0b, 0xa92c, 0x5dfa, 0xa91a, 0x5de9, 0xa907, 0x5dd8, 0xa8f5,
+  0x5dc7, 0xa8e3, 0x5db6, 0xa8d0, 0x5da5, 0xa8be, 0x5d94, 0xa8ab,
+  0x5d83, 0xa899, 0x5d71, 0xa887, 0x5d60, 0xa874, 0x5d4f, 0xa862,
+  0x5d3e, 0xa850, 0x5d2d, 0xa83d, 0x5d1b, 0xa82b, 0x5d0a, 0xa819,
+  0x5cf9, 0xa807, 0x5ce8, 0xa7f4, 0x5cd6, 0xa7e2, 0x5cc5, 0xa7d0,
+  0x5cb4, 0xa7be, 0x5ca2, 0xa7ab, 0x5c91, 0xa799, 0x5c80, 0xa787,
+  0x5c6e, 0xa775, 0x5c5d, 0xa763, 0x5c4b, 0xa751, 0x5c3a, 0xa73f,
+  0x5c29, 0xa72c, 0x5c17, 0xa71a, 0x5c06, 0xa708, 0x5bf4, 0xa6f6,
+  0x5be3, 0xa6e4, 0x5bd1, 0xa6d2, 0x5bc0, 0xa6c0, 0x5bae, 0xa6ae,
+  0x5b9d, 0xa69c, 0x5b8b, 0xa68a, 0x5b79, 0xa678, 0x5b68, 0xa666,
+  0x5b56, 0xa654, 0x5b45, 0xa642, 0x5b33, 0xa630, 0x5b21, 0xa61f,
+  0x5b10, 0xa60d, 0x5afe, 0xa5fb, 0x5aec, 0xa5e9, 0x5adb, 0xa5d7,
+  0x5ac9, 0xa5c5, 0x5ab7, 0xa5b3, 0x5aa5, 0xa5a2, 0x5a94, 0xa590,
+  0x5a82, 0xa57e, 0x5a70, 0xa56c, 0x5a5e, 0xa55b, 0x5a4d, 0xa549,
+  0x5a3b, 0xa537, 0x5a29, 0xa525, 0x5a17, 0xa514, 0x5a05, 0xa502,
+  0x59f3, 0xa4f0, 0x59e1, 0xa4df, 0x59d0, 0xa4cd, 0x59be, 0xa4bb,
+  0x59ac, 0xa4aa, 0x599a, 0xa498, 0x5988, 0xa487, 0x5976, 0xa475,
+  0x5964, 0xa463, 0x5952, 0xa452, 0x5940, 0xa440, 0x592e, 0xa42f,
+  0x591c, 0xa41d, 0x590a, 0xa40c, 0x58f8, 0xa3fa, 0x58e6, 0xa3e9,
+  0x58d4, 0xa3d7, 0x58c1, 0xa3c6, 0x58af, 0xa3b5, 0x589d, 0xa3a3,
+  0x588b, 0xa392, 0x5879, 0xa380, 0x5867, 0xa36f, 0x5855, 0xa35e,
+  0x5842, 0xa34c, 0x5830, 0xa33b, 0x581e, 0xa32a, 0x580c, 0xa318,
+  0x57f9, 0xa307, 0x57e7, 0xa2f6, 0x57d5, 0xa2e5, 0x57c3, 0xa2d3,
+  0x57b0, 0xa2c2, 0x579e, 0xa2b1, 0x578c, 0xa2a0, 0x5779, 0xa28f,
+  0x5767, 0xa27d, 0x5755, 0xa26c, 0x5742, 0xa25b, 0x5730, 0xa24a,
+  0x571d, 0xa239, 0x570b, 0xa228, 0x56f9, 0xa217, 0x56e6, 0xa206,
+  0x56d4, 0xa1f5, 0x56c1, 0xa1e4, 0x56af, 0xa1d3, 0x569c, 0xa1c1,
+  0x568a, 0xa1b0, 0x5677, 0xa1a0, 0x5665, 0xa18f, 0x5652, 0xa17e,
+  0x5640, 0xa16d, 0x562d, 0xa15c, 0x561a, 0xa14b, 0x5608, 0xa13a,
+  0x55f5, 0xa129, 0x55e3, 0xa118, 0x55d0, 0xa107, 0x55bd, 0xa0f6,
+  0x55ab, 0xa0e6, 0x5598, 0xa0d5, 0x5585, 0xa0c4, 0x5572, 0xa0b3,
+  0x5560, 0xa0a2, 0x554d, 0xa092, 0x553a, 0xa081, 0x5528, 0xa070,
+  0x5515, 0xa060, 0x5502, 0xa04f, 0x54ef, 0xa03e, 0x54dc, 0xa02d,
+  0x54ca, 0xa01d, 0x54b7, 0xa00c, 0x54a4, 0x9ffc, 0x5491, 0x9feb,
+  0x547e, 0x9fda, 0x546b, 0x9fca, 0x5458, 0x9fb9, 0x5445, 0x9fa9,
+  0x5433, 0x9f98, 0x5420, 0x9f88, 0x540d, 0x9f77, 0x53fa, 0x9f67,
+  0x53e7, 0x9f56, 0x53d4, 0x9f46, 0x53c1, 0x9f35, 0x53ae, 0x9f25,
+  0x539b, 0x9f14, 0x5388, 0x9f04, 0x5375, 0x9ef3, 0x5362, 0x9ee3,
+  0x534e, 0x9ed3, 0x533b, 0x9ec2, 0x5328, 0x9eb2, 0x5315, 0x9ea2,
+  0x5302, 0x9e91, 0x52ef, 0x9e81, 0x52dc, 0x9e71, 0x52c9, 0x9e61,
+  0x52b5, 0x9e50, 0x52a2, 0x9e40, 0x528f, 0x9e30, 0x527c, 0x9e20,
+  0x5269, 0x9e0f, 0x5255, 0x9dff, 0x5242, 0x9def, 0x522f, 0x9ddf,
+  0x521c, 0x9dcf, 0x5208, 0x9dbf, 0x51f5, 0x9daf, 0x51e2, 0x9d9f,
+  0x51ce, 0x9d8f, 0x51bb, 0x9d7e, 0x51a8, 0x9d6e, 0x5194, 0x9d5e,
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+  0x2223, 0x84a3, 0x220b, 0x849d, 0x21f3, 0x8496, 0x21da, 0x848f,
+  0x21c2, 0x8489, 0x21aa, 0x8482, 0x2192, 0x847c, 0x2179, 0x8475,
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+  0x1fdc, 0x8408, 0x1fc4, 0x8402, 0x1fac, 0x83fb, 0x1f93, 0x83f5,
+  0x1f7b, 0x83ef, 0x1f63, 0x83e9, 0x1f4a, 0x83e3, 0x1f32, 0x83dd,
+  0x1f19, 0x83d7, 0x1f01, 0x83d0, 0x1ee9, 0x83ca, 0x1ed0, 0x83c4,
+  0x1eb8, 0x83be, 0x1ea0, 0x83b8, 0x1e87, 0x83b2, 0x1e6f, 0x83ac,
+  0x1e56, 0x83a6, 0x1e3e, 0x83a0, 0x1e25, 0x839a, 0x1e0d, 0x8394,
+  0x1df5, 0x838f, 0x1ddc, 0x8389, 0x1dc4, 0x8383, 0x1dab, 0x837d,
+  0x1d93, 0x8377, 0x1d7a, 0x8371, 0x1d62, 0x836c, 0x1d49, 0x8366,
+  0x1d31, 0x8360, 0x1d18, 0x835a, 0x1d00, 0x8355, 0x1ce8, 0x834f,
+  0x1ccf, 0x8349, 0x1cb7, 0x8344, 0x1c9e, 0x833e, 0x1c86, 0x8338,
+  0x1c6d, 0x8333, 0x1c55, 0x832d, 0x1c3c, 0x8328, 0x1c24, 0x8322,
+  0x1c0b, 0x831d, 0x1bf2, 0x8317, 0x1bda, 0x8312, 0x1bc1, 0x830c,
+  0x1ba9, 0x8307, 0x1b90, 0x8301, 0x1b78, 0x82fc, 0x1b5f, 0x82f7,
+  0x1b47, 0x82f1, 0x1b2e, 0x82ec, 0x1b16, 0x82e7, 0x1afd, 0x82e1,
+  0x1ae4, 0x82dc, 0x1acc, 0x82d7, 0x1ab3, 0x82d1, 0x1a9b, 0x82cc,
+  0x1a82, 0x82c7, 0x1a6a, 0x82c2, 0x1a51, 0x82bd, 0x1a38, 0x82b7,
+  0x1a20, 0x82b2, 0x1a07, 0x82ad, 0x19ef, 0x82a8, 0x19d6, 0x82a3,
+  0x19bd, 0x829e, 0x19a5, 0x8299, 0x198c, 0x8294, 0x1973, 0x828f,
+  0x195b, 0x828a, 0x1942, 0x8285, 0x192a, 0x8280, 0x1911, 0x827b,
+  0x18f8, 0x8276, 0x18e0, 0x8271, 0x18c7, 0x826c, 0x18ae, 0x8268,
+  0x1896, 0x8263, 0x187d, 0x825e, 0x1864, 0x8259, 0x184c, 0x8254,
+  0x1833, 0x8250, 0x181a, 0x824b, 0x1802, 0x8246, 0x17e9, 0x8241,
+  0x17d0, 0x823d, 0x17b7, 0x8238, 0x179f, 0x8233, 0x1786, 0x822f,
+  0x176d, 0x822a, 0x1755, 0x8226, 0x173c, 0x8221, 0x1723, 0x821c,
+  0x170a, 0x8218, 0x16f2, 0x8213, 0x16d9, 0x820f, 0x16c0, 0x820a,
+  0x16a8, 0x8206, 0x168f, 0x8201, 0x1676, 0x81fd, 0x165d, 0x81f9,
+  0x1645, 0x81f4, 0x162c, 0x81f0, 0x1613, 0x81ec, 0x15fa, 0x81e7,
+  0x15e2, 0x81e3, 0x15c9, 0x81df, 0x15b0, 0x81da, 0x1597, 0x81d6,
+  0x157f, 0x81d2, 0x1566, 0x81ce, 0x154d, 0x81c9, 0x1534, 0x81c5,
+  0x151b, 0x81c1, 0x1503, 0x81bd, 0x14ea, 0x81b9, 0x14d1, 0x81b5,
+  0x14b8, 0x81b1, 0x149f, 0x81ad, 0x1487, 0x81a9, 0x146e, 0x81a5,
+  0x1455, 0x81a1, 0x143c, 0x819d, 0x1423, 0x8199, 0x140b, 0x8195,
+  0x13f2, 0x8191, 0x13d9, 0x818d, 0x13c0, 0x8189, 0x13a7, 0x8185,
+  0x138e, 0x8181, 0x1376, 0x817d, 0x135d, 0x817a, 0x1344, 0x8176,
+  0x132b, 0x8172, 0x1312, 0x816e, 0x12f9, 0x816b, 0x12e0, 0x8167,
+  0x12c8, 0x8163, 0x12af, 0x815f, 0x1296, 0x815c, 0x127d, 0x8158,
+  0x1264, 0x8155, 0x124b, 0x8151, 0x1232, 0x814d, 0x1219, 0x814a,
+  0x1201, 0x8146, 0x11e8, 0x8143, 0x11cf, 0x813f, 0x11b6, 0x813c,
+  0x119d, 0x8138, 0x1184, 0x8135, 0x116b, 0x8131, 0x1152, 0x812e,
+  0x1139, 0x812b, 0x1121, 0x8127, 0x1108, 0x8124, 0x10ef, 0x8121,
+  0x10d6, 0x811d, 0x10bd, 0x811a, 0x10a4, 0x8117, 0x108b, 0x8113,
+  0x1072, 0x8110, 0x1059, 0x810d, 0x1040, 0x810a, 0x1027, 0x8107,
+  0x100e, 0x8103, 0xff5, 0x8100, 0xfdd, 0x80fd, 0xfc4, 0x80fa,
+  0xfab, 0x80f7, 0xf92, 0x80f4, 0xf79, 0x80f1, 0xf60, 0x80ee,
+  0xf47, 0x80eb, 0xf2e, 0x80e8, 0xf15, 0x80e5, 0xefc, 0x80e2,
+  0xee3, 0x80df, 0xeca, 0x80dc, 0xeb1, 0x80d9, 0xe98, 0x80d6,
+  0xe7f, 0x80d3, 0xe66, 0x80d1, 0xe4d, 0x80ce, 0xe34, 0x80cb,
+  0xe1b, 0x80c8, 0xe02, 0x80c5, 0xde9, 0x80c3, 0xdd0, 0x80c0,
+  0xdb7, 0x80bd, 0xd9e, 0x80bb, 0xd85, 0x80b8, 0xd6c, 0x80b5,
+  0xd53, 0x80b3, 0xd3a, 0x80b0, 0xd21, 0x80ad, 0xd08, 0x80ab,
+  0xcef, 0x80a8, 0xcd6, 0x80a6, 0xcbd, 0x80a3, 0xca4, 0x80a1,
+  0xc8b, 0x809e, 0xc72, 0x809c, 0xc59, 0x8099, 0xc40, 0x8097,
+  0xc27, 0x8095, 0xc0e, 0x8092, 0xbf5, 0x8090, 0xbdc, 0x808e,
+  0xbc3, 0x808b, 0xbaa, 0x8089, 0xb91, 0x8087, 0xb78, 0x8084,
+  0xb5f, 0x8082, 0xb46, 0x8080, 0xb2d, 0x807e, 0xb14, 0x807b,
+  0xafb, 0x8079, 0xae2, 0x8077, 0xac9, 0x8075, 0xab0, 0x8073,
+  0xa97, 0x8071, 0xa7e, 0x806f, 0xa65, 0x806d, 0xa4c, 0x806b,
+  0xa33, 0x8069, 0xa19, 0x8067, 0xa00, 0x8065, 0x9e7, 0x8063,
+  0x9ce, 0x8061, 0x9b5, 0x805f, 0x99c, 0x805d, 0x983, 0x805b,
+  0x96a, 0x8059, 0x951, 0x8057, 0x938, 0x8056, 0x91f, 0x8054,
+  0x906, 0x8052, 0x8ed, 0x8050, 0x8d4, 0x804f, 0x8bb, 0x804d,
+  0x8a2, 0x804b, 0x888, 0x8049, 0x86f, 0x8048, 0x856, 0x8046,
+  0x83d, 0x8044, 0x824, 0x8043, 0x80b, 0x8041, 0x7f2, 0x8040,
+  0x7d9, 0x803e, 0x7c0, 0x803d, 0x7a7, 0x803b, 0x78e, 0x803a,
+  0x775, 0x8038, 0x75b, 0x8037, 0x742, 0x8035, 0x729, 0x8034,
+  0x710, 0x8032, 0x6f7, 0x8031, 0x6de, 0x8030, 0x6c5, 0x802e,
+  0x6ac, 0x802d, 0x693, 0x802c, 0x67a, 0x802a, 0x660, 0x8029,
+  0x647, 0x8028, 0x62e, 0x8027, 0x615, 0x8026, 0x5fc, 0x8024,
+  0x5e3, 0x8023, 0x5ca, 0x8022, 0x5b1, 0x8021, 0x598, 0x8020,
+  0x57f, 0x801f, 0x565, 0x801e, 0x54c, 0x801d, 0x533, 0x801c,
+  0x51a, 0x801b, 0x501, 0x801a, 0x4e8, 0x8019, 0x4cf, 0x8018,
+  0x4b6, 0x8017, 0x49c, 0x8016, 0x483, 0x8015, 0x46a, 0x8014,
+  0x451, 0x8013, 0x438, 0x8012, 0x41f, 0x8012, 0x406, 0x8011,
+  0x3ed, 0x8010, 0x3d4, 0x800f, 0x3ba, 0x800e, 0x3a1, 0x800e,
+  0x388, 0x800d, 0x36f, 0x800c, 0x356, 0x800c, 0x33d, 0x800b,
+  0x324, 0x800a, 0x30b, 0x800a, 0x2f1, 0x8009, 0x2d8, 0x8009,
+  0x2bf, 0x8008, 0x2a6, 0x8008, 0x28d, 0x8007, 0x274, 0x8007,
+  0x25b, 0x8006, 0x242, 0x8006, 0x228, 0x8005, 0x20f, 0x8005,
+  0x1f6, 0x8004, 0x1dd, 0x8004, 0x1c4, 0x8004, 0x1ab, 0x8003,
+  0x192, 0x8003, 0x178, 0x8003, 0x15f, 0x8002, 0x146, 0x8002,
+  0x12d, 0x8002, 0x114, 0x8002, 0xfb, 0x8001, 0xe2, 0x8001,
+  0xc9, 0x8001, 0xaf, 0x8001, 0x96, 0x8001, 0x7d, 0x8001,
+  0x64, 0x8001, 0x4b, 0x8001, 0x32, 0x8001, 0x19, 0x8001,
+};
+
+/**   
+* \par   
+* cosFactor tables are generated using the formula : 
     cos_factors[n] = 2 * cos((2n+1)*pi/(4*N)) 
       
+* \par   
+* C command to generate the table   
+* 
       
+* for(i = 0; i< N; i++)   
+* {   
+*   cos_factors[i]= 2 * cos((2*i+1)*c/2);   
+* } 
       
+* \par   
+* where N is the number of factors to generate and c is pi/(2*N)   
+* \par   
+* Then converted to q15 format by multiplying with 2^31 and saturated if required.   
+   
+*/
+
+static const q15_t cos_factorsQ15_128[128] = {
+  0x7fff, 0x7ffa, 0x7ff0, 0x7fe1, 0x7fce, 0x7fb5, 0x7f97, 0x7f75,
+  0x7f4d, 0x7f21, 0x7ef0, 0x7eba, 0x7e7f, 0x7e3f, 0x7dfa, 0x7db0,
+  0x7d62, 0x7d0f, 0x7cb7, 0x7c5a, 0x7bf8, 0x7b92, 0x7b26, 0x7ab6,
+  0x7a42, 0x79c8, 0x794a, 0x78c7, 0x7840, 0x77b4, 0x7723, 0x768e,
+  0x75f4, 0x7555, 0x74b2, 0x740b, 0x735f, 0x72af, 0x71fa, 0x7141,
+  0x7083, 0x6fc1, 0x6efb, 0x6e30, 0x6d62, 0x6c8f, 0x6bb8, 0x6adc,
+  0x69fd, 0x6919, 0x6832, 0x6746, 0x6657, 0x6563, 0x646c, 0x6371,
+  0x6271, 0x616f, 0x6068, 0x5f5e, 0x5e50, 0x5d3e, 0x5c29, 0x5b10,
+  0x59f3, 0x58d4, 0x57b0, 0x568a, 0x5560, 0x5433, 0x5302, 0x51ce,
+  0x5097, 0x4f5e, 0x4e21, 0x4ce1, 0x4b9e, 0x4a58, 0x490f, 0x47c3,
+  0x4675, 0x4524, 0x43d0, 0x427a, 0x4121, 0x3fc5, 0x3e68, 0x3d07,
+  0x3ba5, 0x3a40, 0x38d8, 0x376f, 0x3604, 0x3496, 0x3326, 0x31b5,
+  0x3041, 0x2ecc, 0x2d55, 0x2bdc, 0x2a61, 0x28e5, 0x2767, 0x25e8,
+  0x2467, 0x22e5, 0x2161, 0x1fdc, 0x1e56, 0x1ccf, 0x1b47, 0x19bd,
+  0x1833, 0x16a8, 0x151b, 0x138e, 0x1201, 0x1072, 0xee3, 0xd53,
+  0xbc3, 0xa33, 0x8a2, 0x710, 0x57f, 0x3ed, 0x25b, 0xc9
+};
+
+static const q15_t cos_factorsQ15_512[512] = {
+  0x7fff, 0x7fff, 0x7fff, 0x7ffe, 0x7ffc, 0x7ffb, 0x7ff9, 0x7ff7,
+  0x7ff4, 0x7ff2, 0x7fee, 0x7feb, 0x7fe7, 0x7fe3, 0x7fdf, 0x7fda,
+  0x7fd6, 0x7fd0, 0x7fcb, 0x7fc5, 0x7fbf, 0x7fb8, 0x7fb1, 0x7faa,
+  0x7fa3, 0x7f9b, 0x7f93, 0x7f8b, 0x7f82, 0x7f79, 0x7f70, 0x7f67,
+  0x7f5d, 0x7f53, 0x7f48, 0x7f3d, 0x7f32, 0x7f27, 0x7f1b, 0x7f0f,
+  0x7f03, 0x7ef6, 0x7ee9, 0x7edc, 0x7ecf, 0x7ec1, 0x7eb3, 0x7ea4,
+  0x7e95, 0x7e86, 0x7e77, 0x7e67, 0x7e57, 0x7e47, 0x7e37, 0x7e26,
+  0x7e14, 0x7e03, 0x7df1, 0x7ddf, 0x7dcd, 0x7dba, 0x7da7, 0x7d94,
+  0x7d80, 0x7d6c, 0x7d58, 0x7d43, 0x7d2f, 0x7d19, 0x7d04, 0x7cee,
+  0x7cd8, 0x7cc2, 0x7cab, 0x7c94, 0x7c7d, 0x7c66, 0x7c4e, 0x7c36,
+  0x7c1d, 0x7c05, 0x7beb, 0x7bd2, 0x7bb9, 0x7b9f, 0x7b84, 0x7b6a,
+  0x7b4f, 0x7b34, 0x7b19, 0x7afd, 0x7ae1, 0x7ac5, 0x7aa8, 0x7a8b,
+  0x7a6e, 0x7a50, 0x7a33, 0x7a15, 0x79f6, 0x79d8, 0x79b9, 0x7999,
+  0x797a, 0x795a, 0x793a, 0x7919, 0x78f9, 0x78d8, 0x78b6, 0x7895,
+  0x7873, 0x7851, 0x782e, 0x780c, 0x77e9, 0x77c5, 0x77a2, 0x777e,
+  0x775a, 0x7735, 0x7710, 0x76eb, 0x76c6, 0x76a0, 0x767b, 0x7654,
+  0x762e, 0x7607, 0x75e0, 0x75b9, 0x7591, 0x7569, 0x7541, 0x7519,
+  0x74f0, 0x74c7, 0x749e, 0x7474, 0x744a, 0x7420, 0x73f6, 0x73cb,
+  0x73a0, 0x7375, 0x7349, 0x731d, 0x72f1, 0x72c5, 0x7298, 0x726b,
+  0x723e, 0x7211, 0x71e3, 0x71b5, 0x7186, 0x7158, 0x7129, 0x70fa,
+  0x70cb, 0x709b, 0x706b, 0x703b, 0x700a, 0x6fda, 0x6fa9, 0x6f77,
+  0x6f46, 0x6f14, 0x6ee2, 0x6eaf, 0x6e7d, 0x6e4a, 0x6e17, 0x6de3,
+  0x6db0, 0x6d7c, 0x6d48, 0x6d13, 0x6cde, 0x6ca9, 0x6c74, 0x6c3f,
+  0x6c09, 0x6bd3, 0x6b9c, 0x6b66, 0x6b2f, 0x6af8, 0x6ac1, 0x6a89,
+  0x6a51, 0x6a19, 0x69e1, 0x69a8, 0x696f, 0x6936, 0x68fd, 0x68c3,
+  0x6889, 0x684f, 0x6815, 0x67da, 0x679f, 0x6764, 0x6729, 0x66ed,
+  0x66b1, 0x6675, 0x6639, 0x65fc, 0x65bf, 0x6582, 0x6545, 0x6507,
+  0x64c9, 0x648b, 0x644d, 0x640e, 0x63cf, 0x6390, 0x6351, 0x6311,
+  0x62d2, 0x6292, 0x6251, 0x6211, 0x61d0, 0x618f, 0x614e, 0x610d,
+  0x60cb, 0x6089, 0x6047, 0x6004, 0x5fc2, 0x5f7f, 0x5f3c, 0x5ef9,
+  0x5eb5, 0x5e71, 0x5e2d, 0x5de9, 0x5da5, 0x5d60, 0x5d1b, 0x5cd6,
+  0x5c91, 0x5c4b, 0x5c06, 0x5bc0, 0x5b79, 0x5b33, 0x5aec, 0x5aa5,
+  0x5a5e, 0x5a17, 0x59d0, 0x5988, 0x5940, 0x58f8, 0x58af, 0x5867,
+  0x581e, 0x57d5, 0x578c, 0x5742, 0x56f9, 0x56af, 0x5665, 0x561a,
+  0x55d0, 0x5585, 0x553a, 0x54ef, 0x54a4, 0x5458, 0x540d, 0x53c1,
+  0x5375, 0x5328, 0x52dc, 0x528f, 0x5242, 0x51f5, 0x51a8, 0x515a,
+  0x510c, 0x50bf, 0x5070, 0x5022, 0x4fd4, 0x4f85, 0x4f36, 0x4ee7,
+  0x4e98, 0x4e48, 0x4df9, 0x4da9, 0x4d59, 0x4d09, 0x4cb8, 0x4c68,
+  0x4c17, 0x4bc6, 0x4b75, 0x4b24, 0x4ad2, 0x4a81, 0x4a2f, 0x49dd,
+  0x498a, 0x4938, 0x48e6, 0x4893, 0x4840, 0x47ed, 0x479a, 0x4746,
+  0x46f3, 0x469f, 0x464b, 0x45f7, 0x45a3, 0x454e, 0x44fa, 0x44a5,
+  0x4450, 0x43fb, 0x43a5, 0x4350, 0x42fa, 0x42a5, 0x424f, 0x41f9,
+  0x41a2, 0x414c, 0x40f6, 0x409f, 0x4048, 0x3ff1, 0x3f9a, 0x3f43,
+  0x3eeb, 0x3e93, 0x3e3c, 0x3de4, 0x3d8c, 0x3d33, 0x3cdb, 0x3c83,
+  0x3c2a, 0x3bd1, 0x3b78, 0x3b1f, 0x3ac6, 0x3a6c, 0x3a13, 0x39b9,
+  0x395f, 0x3906, 0x38ab, 0x3851, 0x37f7, 0x379c, 0x3742, 0x36e7,
+  0x368c, 0x3631, 0x35d6, 0x357b, 0x351f, 0x34c4, 0x3468, 0x340c,
+  0x33b0, 0x3354, 0x32f8, 0x329c, 0x3240, 0x31e3, 0x3186, 0x312a,
+  0x30cd, 0x3070, 0x3013, 0x2fb5, 0x2f58, 0x2efb, 0x2e9d, 0x2e3f,
+  0x2de2, 0x2d84, 0x2d26, 0x2cc8, 0x2c69, 0x2c0b, 0x2bad, 0x2b4e,
+  0x2aef, 0x2a91, 0x2a32, 0x29d3, 0x2974, 0x2915, 0x28b5, 0x2856,
+  0x27f6, 0x2797, 0x2737, 0x26d8, 0x2678, 0x2618, 0x25b8, 0x2558,
+  0x24f7, 0x2497, 0x2437, 0x23d6, 0x2376, 0x2315, 0x22b4, 0x2254,
+  0x21f3, 0x2192, 0x2131, 0x20d0, 0x206e, 0x200d, 0x1fac, 0x1f4a,
+  0x1ee9, 0x1e87, 0x1e25, 0x1dc4, 0x1d62, 0x1d00, 0x1c9e, 0x1c3c,
+  0x1bda, 0x1b78, 0x1b16, 0x1ab3, 0x1a51, 0x19ef, 0x198c, 0x192a,
+  0x18c7, 0x1864, 0x1802, 0x179f, 0x173c, 0x16d9, 0x1676, 0x1613,
+  0x15b0, 0x154d, 0x14ea, 0x1487, 0x1423, 0x13c0, 0x135d, 0x12f9,
+  0x1296, 0x1232, 0x11cf, 0x116b, 0x1108, 0x10a4, 0x1040, 0xfdd,
+  0xf79, 0xf15, 0xeb1, 0xe4d, 0xde9, 0xd85, 0xd21, 0xcbd,
+  0xc59, 0xbf5, 0xb91, 0xb2d, 0xac9, 0xa65, 0xa00, 0x99c,
+  0x938, 0x8d4, 0x86f, 0x80b, 0x7a7, 0x742, 0x6de, 0x67a,
+  0x615, 0x5b1, 0x54c, 0x4e8, 0x483, 0x41f, 0x3ba, 0x356,
+  0x2f1, 0x28d, 0x228, 0x1c4, 0x15f, 0xfb, 0x96, 0x32,
+};
+
+static const q15_t cos_factorsQ15_2048[2048] = {
+  0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff, 0x7fff,
+  0x7fff, 0x7fff, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffe, 0x7ffd, 0x7ffd,
+  0x7ffd, 0x7ffd, 0x7ffc, 0x7ffc, 0x7ffb, 0x7ffb, 0x7ffb, 0x7ffa,
+  0x7ffa, 0x7ff9, 0x7ff9, 0x7ff8, 0x7ff8, 0x7ff7, 0x7ff7, 0x7ff6,
+  0x7ff5, 0x7ff5, 0x7ff4, 0x7ff3, 0x7ff3, 0x7ff2, 0x7ff1, 0x7ff0,
+  0x7ff0, 0x7fef, 0x7fee, 0x7fed, 0x7fec, 0x7fec, 0x7feb, 0x7fea,
+  0x7fe9, 0x7fe8, 0x7fe7, 0x7fe6, 0x7fe5, 0x7fe4, 0x7fe3, 0x7fe2,
+  0x7fe1, 0x7fe0, 0x7fdf, 0x7fdd, 0x7fdc, 0x7fdb, 0x7fda, 0x7fd9,
+  0x7fd7, 0x7fd6, 0x7fd5, 0x7fd4, 0x7fd2, 0x7fd1, 0x7fd0, 0x7fce,
+  0x7fcd, 0x7fcb, 0x7fca, 0x7fc9, 0x7fc7, 0x7fc6, 0x7fc4, 0x7fc3,
+  0x7fc1, 0x7fc0, 0x7fbe, 0x7fbc, 0x7fbb, 0x7fb9, 0x7fb7, 0x7fb6,
+  0x7fb4, 0x7fb2, 0x7fb1, 0x7faf, 0x7fad, 0x7fab, 0x7fa9, 0x7fa8,
+  0x7fa6, 0x7fa4, 0x7fa2, 0x7fa0, 0x7f9e, 0x7f9c, 0x7f9a, 0x7f98,
+  0x7f96, 0x7f94, 0x7f92, 0x7f90, 0x7f8e, 0x7f8c, 0x7f8a, 0x7f88,
+  0x7f86, 0x7f83, 0x7f81, 0x7f7f, 0x7f7d, 0x7f7b, 0x7f78, 0x7f76,
+  0x7f74, 0x7f71, 0x7f6f, 0x7f6d, 0x7f6a, 0x7f68, 0x7f65, 0x7f63,
+  0x7f60, 0x7f5e, 0x7f5b, 0x7f59, 0x7f56, 0x7f54, 0x7f51, 0x7f4f,
+  0x7f4c, 0x7f49, 0x7f47, 0x7f44, 0x7f41, 0x7f3f, 0x7f3c, 0x7f39,
+  0x7f36, 0x7f34, 0x7f31, 0x7f2e, 0x7f2b, 0x7f28, 0x7f25, 0x7f23,
+  0x7f20, 0x7f1d, 0x7f1a, 0x7f17, 0x7f14, 0x7f11, 0x7f0e, 0x7f0b,
+  0x7f08, 0x7f04, 0x7f01, 0x7efe, 0x7efb, 0x7ef8, 0x7ef5, 0x7ef1,
+  0x7eee, 0x7eeb, 0x7ee8, 0x7ee4, 0x7ee1, 0x7ede, 0x7eda, 0x7ed7,
+  0x7ed4, 0x7ed0, 0x7ecd, 0x7ec9, 0x7ec6, 0x7ec3, 0x7ebf, 0x7ebb,
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+  0x5b94, 0x5b82, 0x5b71, 0x5b5f, 0x5b4d, 0x5b3c, 0x5b2a, 0x5b19,
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+  0x5680, 0x566e, 0x565b, 0x5649, 0x5636, 0x5624, 0x5611, 0x55fe,
+  0x55ec, 0x55d9, 0x55c7, 0x55b4, 0x55a1, 0x558f, 0x557c, 0x5569,
+  0x5556, 0x5544, 0x5531, 0x551e, 0x550b, 0x54f9, 0x54e6, 0x54d3,
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+  0x5391, 0x537e, 0x536b, 0x5358, 0x5345, 0x5332, 0x531f, 0x530c,
+  0x52f8, 0x52e5, 0x52d2, 0x52bf, 0x52ac, 0x5299, 0x5285, 0x5272,
+  0x525f, 0x524c, 0x5238, 0x5225, 0x5212, 0x51ff, 0x51eb, 0x51d8,
+  0x51c5, 0x51b1, 0x519e, 0x518b, 0x5177, 0x5164, 0x5150, 0x513d,
+  0x512a, 0x5116, 0x5103, 0x50ef, 0x50dc, 0x50c8, 0x50b5, 0x50a1,
+  0x508e, 0x507a, 0x5067, 0x5053, 0x503f, 0x502c, 0x5018, 0x5005,
+  0x4ff1, 0x4fdd, 0x4fca, 0x4fb6, 0x4fa2, 0x4f8f, 0x4f7b, 0x4f67,
+  0x4f54, 0x4f40, 0x4f2c, 0x4f18, 0x4f05, 0x4ef1, 0x4edd, 0x4ec9,
+  0x4eb6, 0x4ea2, 0x4e8e, 0x4e7a, 0x4e66, 0x4e52, 0x4e3e, 0x4e2a,
+  0x4e17, 0x4e03, 0x4def, 0x4ddb, 0x4dc7, 0x4db3, 0x4d9f, 0x4d8b,
+  0x4d77, 0x4d63, 0x4d4f, 0x4d3b, 0x4d27, 0x4d13, 0x4cff, 0x4ceb,
+  0x4cd6, 0x4cc2, 0x4cae, 0x4c9a, 0x4c86, 0x4c72, 0x4c5e, 0x4c49,
+  0x4c35, 0x4c21, 0x4c0d, 0x4bf9, 0x4be4, 0x4bd0, 0x4bbc, 0x4ba8,
+  0x4b93, 0x4b7f, 0x4b6b, 0x4b56, 0x4b42, 0x4b2e, 0x4b19, 0x4b05,
+  0x4af1, 0x4adc, 0x4ac8, 0x4ab4, 0x4a9f, 0x4a8b, 0x4a76, 0x4a62,
+  0x4a4d, 0x4a39, 0x4a24, 0x4a10, 0x49fb, 0x49e7, 0x49d2, 0x49be,
+  0x49a9, 0x4995, 0x4980, 0x496c, 0x4957, 0x4942, 0x492e, 0x4919,
+  0x4905, 0x48f0, 0x48db, 0x48c7, 0x48b2, 0x489d, 0x4888, 0x4874,
+  0x485f, 0x484a, 0x4836, 0x4821, 0x480c, 0x47f7, 0x47e2, 0x47ce,
+  0x47b9, 0x47a4, 0x478f, 0x477a, 0x4765, 0x4751, 0x473c, 0x4727,
+  0x4712, 0x46fd, 0x46e8, 0x46d3, 0x46be, 0x46a9, 0x4694, 0x467f,
+  0x466a, 0x4655, 0x4640, 0x462b, 0x4616, 0x4601, 0x45ec, 0x45d7,
+  0x45c2, 0x45ad, 0x4598, 0x4583, 0x456e, 0x4559, 0x4544, 0x452e,
+  0x4519, 0x4504, 0x44ef, 0x44da, 0x44c5, 0x44af, 0x449a, 0x4485,
+  0x4470, 0x445a, 0x4445, 0x4430, 0x441b, 0x4405, 0x43f0, 0x43db,
+  0x43c5, 0x43b0, 0x439b, 0x4385, 0x4370, 0x435b, 0x4345, 0x4330,
+  0x431b, 0x4305, 0x42f0, 0x42da, 0x42c5, 0x42af, 0x429a, 0x4284,
+  0x426f, 0x425a, 0x4244, 0x422f, 0x4219, 0x4203, 0x41ee, 0x41d8,
+  0x41c3, 0x41ad, 0x4198, 0x4182, 0x416d, 0x4157, 0x4141, 0x412c,
+  0x4116, 0x4100, 0x40eb, 0x40d5, 0x40bf, 0x40aa, 0x4094, 0x407e,
+  0x4069, 0x4053, 0x403d, 0x4027, 0x4012, 0x3ffc, 0x3fe6, 0x3fd0,
+  0x3fbb, 0x3fa5, 0x3f8f, 0x3f79, 0x3f63, 0x3f4d, 0x3f38, 0x3f22,
+  0x3f0c, 0x3ef6, 0x3ee0, 0x3eca, 0x3eb4, 0x3e9e, 0x3e88, 0x3e73,
+  0x3e5d, 0x3e47, 0x3e31, 0x3e1b, 0x3e05, 0x3def, 0x3dd9, 0x3dc3,
+  0x3dad, 0x3d97, 0x3d81, 0x3d6b, 0x3d55, 0x3d3e, 0x3d28, 0x3d12,
+  0x3cfc, 0x3ce6, 0x3cd0, 0x3cba, 0x3ca4, 0x3c8e, 0x3c77, 0x3c61,
+  0x3c4b, 0x3c35, 0x3c1f, 0x3c09, 0x3bf2, 0x3bdc, 0x3bc6, 0x3bb0,
+  0x3b99, 0x3b83, 0x3b6d, 0x3b57, 0x3b40, 0x3b2a, 0x3b14, 0x3afe,
+  0x3ae7, 0x3ad1, 0x3abb, 0x3aa4, 0x3a8e, 0x3a78, 0x3a61, 0x3a4b,
+  0x3a34, 0x3a1e, 0x3a08, 0x39f1, 0x39db, 0x39c4, 0x39ae, 0x3998,
+  0x3981, 0x396b, 0x3954, 0x393e, 0x3927, 0x3911, 0x38fa, 0x38e4,
+  0x38cd, 0x38b7, 0x38a0, 0x388a, 0x3873, 0x385d, 0x3846, 0x382f,
+  0x3819, 0x3802, 0x37ec, 0x37d5, 0x37be, 0x37a8, 0x3791, 0x377a,
+  0x3764, 0x374d, 0x3736, 0x3720, 0x3709, 0x36f2, 0x36dc, 0x36c5,
+  0x36ae, 0x3698, 0x3681, 0x366a, 0x3653, 0x363d, 0x3626, 0x360f,
+  0x35f8, 0x35e1, 0x35cb, 0x35b4, 0x359d, 0x3586, 0x356f, 0x3558,
+  0x3542, 0x352b, 0x3514, 0x34fd, 0x34e6, 0x34cf, 0x34b8, 0x34a1,
+  0x348b, 0x3474, 0x345d, 0x3446, 0x342f, 0x3418, 0x3401, 0x33ea,
+  0x33d3, 0x33bc, 0x33a5, 0x338e, 0x3377, 0x3360, 0x3349, 0x3332,
+  0x331b, 0x3304, 0x32ed, 0x32d6, 0x32bf, 0x32a8, 0x3290, 0x3279,
+  0x3262, 0x324b, 0x3234, 0x321d, 0x3206, 0x31ef, 0x31d8, 0x31c0,
+  0x31a9, 0x3192, 0x317b, 0x3164, 0x314c, 0x3135, 0x311e, 0x3107,
+  0x30f0, 0x30d8, 0x30c1, 0x30aa, 0x3093, 0x307b, 0x3064, 0x304d,
+  0x3036, 0x301e, 0x3007, 0x2ff0, 0x2fd8, 0x2fc1, 0x2faa, 0x2f92,
+  0x2f7b, 0x2f64, 0x2f4c, 0x2f35, 0x2f1e, 0x2f06, 0x2eef, 0x2ed8,
+  0x2ec0, 0x2ea9, 0x2e91, 0x2e7a, 0x2e63, 0x2e4b, 0x2e34, 0x2e1c,
+  0x2e05, 0x2ded, 0x2dd6, 0x2dbe, 0x2da7, 0x2d8f, 0x2d78, 0x2d60,
+  0x2d49, 0x2d31, 0x2d1a, 0x2d02, 0x2ceb, 0x2cd3, 0x2cbc, 0x2ca4,
+  0x2c8d, 0x2c75, 0x2c5e, 0x2c46, 0x2c2e, 0x2c17, 0x2bff, 0x2be8,
+  0x2bd0, 0x2bb8, 0x2ba1, 0x2b89, 0x2b71, 0x2b5a, 0x2b42, 0x2b2b,
+  0x2b13, 0x2afb, 0x2ae4, 0x2acc, 0x2ab4, 0x2a9c, 0x2a85, 0x2a6d,
+  0x2a55, 0x2a3e, 0x2a26, 0x2a0e, 0x29f6, 0x29df, 0x29c7, 0x29af,
+  0x2997, 0x2980, 0x2968, 0x2950, 0x2938, 0x2920, 0x2909, 0x28f1,
+  0x28d9, 0x28c1, 0x28a9, 0x2892, 0x287a, 0x2862, 0x284a, 0x2832,
+  0x281a, 0x2802, 0x27eb, 0x27d3, 0x27bb, 0x27a3, 0x278b, 0x2773,
+  0x275b, 0x2743, 0x272b, 0x2713, 0x26fb, 0x26e4, 0x26cc, 0x26b4,
+  0x269c, 0x2684, 0x266c, 0x2654, 0x263c, 0x2624, 0x260c, 0x25f4,
+  0x25dc, 0x25c4, 0x25ac, 0x2594, 0x257c, 0x2564, 0x254c, 0x2534,
+  0x251c, 0x2503, 0x24eb, 0x24d3, 0x24bb, 0x24a3, 0x248b, 0x2473,
+  0x245b, 0x2443, 0x242b, 0x2413, 0x23fa, 0x23e2, 0x23ca, 0x23b2,
+  0x239a, 0x2382, 0x236a, 0x2352, 0x2339, 0x2321, 0x2309, 0x22f1,
+  0x22d9, 0x22c0, 0x22a8, 0x2290, 0x2278, 0x2260, 0x2247, 0x222f,
+  0x2217, 0x21ff, 0x21e7, 0x21ce, 0x21b6, 0x219e, 0x2186, 0x216d,
+  0x2155, 0x213d, 0x2125, 0x210c, 0x20f4, 0x20dc, 0x20c3, 0x20ab,
+  0x2093, 0x207a, 0x2062, 0x204a, 0x2032, 0x2019, 0x2001, 0x1fe9,
+  0x1fd0, 0x1fb8, 0x1f9f, 0x1f87, 0x1f6f, 0x1f56, 0x1f3e, 0x1f26,
+  0x1f0d, 0x1ef5, 0x1edd, 0x1ec4, 0x1eac, 0x1e93, 0x1e7b, 0x1e62,
+  0x1e4a, 0x1e32, 0x1e19, 0x1e01, 0x1de8, 0x1dd0, 0x1db7, 0x1d9f,
+  0x1d87, 0x1d6e, 0x1d56, 0x1d3d, 0x1d25, 0x1d0c, 0x1cf4, 0x1cdb,
+  0x1cc3, 0x1caa, 0x1c92, 0x1c79, 0x1c61, 0x1c48, 0x1c30, 0x1c17,
+  0x1bff, 0x1be6, 0x1bce, 0x1bb5, 0x1b9d, 0x1b84, 0x1b6c, 0x1b53,
+  0x1b3a, 0x1b22, 0x1b09, 0x1af1, 0x1ad8, 0x1ac0, 0x1aa7, 0x1a8e,
+  0x1a76, 0x1a5d, 0x1a45, 0x1a2c, 0x1a13, 0x19fb, 0x19e2, 0x19ca,
+  0x19b1, 0x1998, 0x1980, 0x1967, 0x194e, 0x1936, 0x191d, 0x1905,
+  0x18ec, 0x18d3, 0x18bb, 0x18a2, 0x1889, 0x1871, 0x1858, 0x183f,
+  0x1827, 0x180e, 0x17f5, 0x17dd, 0x17c4, 0x17ab, 0x1792, 0x177a,
+  0x1761, 0x1748, 0x1730, 0x1717, 0x16fe, 0x16e5, 0x16cd, 0x16b4,
+  0x169b, 0x1682, 0x166a, 0x1651, 0x1638, 0x161f, 0x1607, 0x15ee,
+  0x15d5, 0x15bc, 0x15a4, 0x158b, 0x1572, 0x1559, 0x1541, 0x1528,
+  0x150f, 0x14f6, 0x14dd, 0x14c5, 0x14ac, 0x1493, 0x147a, 0x1461,
+  0x1449, 0x1430, 0x1417, 0x13fe, 0x13e5, 0x13cc, 0x13b4, 0x139b,
+  0x1382, 0x1369, 0x1350, 0x1337, 0x131f, 0x1306, 0x12ed, 0x12d4,
+  0x12bb, 0x12a2, 0x1289, 0x1271, 0x1258, 0x123f, 0x1226, 0x120d,
+  0x11f4, 0x11db, 0x11c2, 0x11a9, 0x1191, 0x1178, 0x115f, 0x1146,
+  0x112d, 0x1114, 0x10fb, 0x10e2, 0x10c9, 0x10b0, 0x1098, 0x107f,
+  0x1066, 0x104d, 0x1034, 0x101b, 0x1002, 0xfe9, 0xfd0, 0xfb7,
+  0xf9e, 0xf85, 0xf6c, 0xf53, 0xf3a, 0xf21, 0xf08, 0xef0,
+  0xed7, 0xebe, 0xea5, 0xe8c, 0xe73, 0xe5a, 0xe41, 0xe28,
+  0xe0f, 0xdf6, 0xddd, 0xdc4, 0xdab, 0xd92, 0xd79, 0xd60,
+  0xd47, 0xd2e, 0xd15, 0xcfc, 0xce3, 0xcca, 0xcb1, 0xc98,
+  0xc7f, 0xc66, 0xc4d, 0xc34, 0xc1b, 0xc02, 0xbe9, 0xbd0,
+  0xbb7, 0xb9e, 0xb85, 0xb6c, 0xb53, 0xb3a, 0xb20, 0xb07,
+  0xaee, 0xad5, 0xabc, 0xaa3, 0xa8a, 0xa71, 0xa58, 0xa3f,
+  0xa26, 0xa0d, 0x9f4, 0x9db, 0x9c2, 0x9a9, 0x990, 0x977,
+  0x95e, 0x944, 0x92b, 0x912, 0x8f9, 0x8e0, 0x8c7, 0x8ae,
+  0x895, 0x87c, 0x863, 0x84a, 0x831, 0x818, 0x7fe, 0x7e5,
+  0x7cc, 0x7b3, 0x79a, 0x781, 0x768, 0x74f, 0x736, 0x71d,
+  0x704, 0x6ea, 0x6d1, 0x6b8, 0x69f, 0x686, 0x66d, 0x654,
+  0x63b, 0x622, 0x609, 0x5ef, 0x5d6, 0x5bd, 0x5a4, 0x58b,
+  0x572, 0x559, 0x540, 0x527, 0x50d, 0x4f4, 0x4db, 0x4c2,
+  0x4a9, 0x490, 0x477, 0x45e, 0x445, 0x42b, 0x412, 0x3f9,
+  0x3e0, 0x3c7, 0x3ae, 0x395, 0x37c, 0x362, 0x349, 0x330,
+  0x317, 0x2fe, 0x2e5, 0x2cc, 0x2b3, 0x299, 0x280, 0x267,
+  0x24e, 0x235, 0x21c, 0x203, 0x1ea, 0x1d0, 0x1b7, 0x19e,
+  0x185, 0x16c, 0x153, 0x13a, 0x121, 0x107, 0xee, 0xd5,
+  0xbc, 0xa3, 0x8a, 0x71, 0x57, 0x3e, 0x25, 0xc,
+
+};
+
+/**   
+ * @brief  Initialization function for the Q15 DCT4/IDCT4.  
+ * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.  
+ * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.  
+ * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.  
+ * @param[in]     N          length of the DCT4.  
+ * @param[in]     Nby2       half of the length of the DCT4.  
+ * @param[in]     normalize  normalizing factor.  
+ * @return  	  arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.  
+ * \par Normalizing factor:   
+ * The normalizing factor is sqrt(2/N), which depends on the size of transform N.   
+ * Normalizing factors in 1.15 format are mentioned in the table below for different DCT sizes:   
+ * \image html dct4NormalizingQ15Table.gif   
+ */
+
+arm_status arm_dct4_init_q15(
+  arm_dct4_instance_q15 * S,
+  arm_rfft_instance_q15 * S_RFFT,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q15_t normalize)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /* Initializing the pointer array with the weight table base addresses of different lengths */
+  q15_t *twiddlePtr[3] = { (q15_t *) WeightsQ15_128, (q15_t *) WeightsQ15_512,
+    (q15_t *) WeightsQ15_2048
+  };
+
+  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+  q15_t *pCosFactor[3] =
+    { (q15_t *) cos_factorsQ15_128, (q15_t *) cos_factorsQ15_512,
+    (q15_t *) cos_factorsQ15_2048
+  };
+
+  /* Initialize the DCT4 length */
+  S->N = N;
+
+  /* Initialize the half of DCT4 length */
+  S->Nby2 = Nby2;
+
+  /* Initialize the DCT4 Normalizing factor */
+  S->normalize = normalize;
+
+  /* Initialize Real FFT Instance */
+  S->pRfft = S_RFFT;
+
+  /* Initialize Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  switch (N)
+  {
+    /* Initialize the table modifier values */
+  case 2048u:
+    S->pTwiddle = twiddlePtr[2];
+    S->pCosFactor = pCosFactor[2];
+    break;
+  case 512u:
+    S->pTwiddle = twiddlePtr[1];
+    S->pCosFactor = pCosFactor[1];
+    break;
+  case 128u:
+    S->pTwiddle = twiddlePtr[0];
+    S->pCosFactor = pCosFactor[0];
+    break;
+  default:
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+
+  /* Initialize the RFFT/RIFFT */
+  arm_rfft_init_q15(S->pRfft, S->pCfft, S->N, 0u, 1u);
+
+  /* return the status of DCT4 Init function */
+  return (status);
+}
+
+/**   
+   * @} end of DCT4_IDCT4 group   
+   */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c
new file mode 100644
index 0000000000..78bce4ac63
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c
@@ -0,0 +1,2198 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_dct4_init_q31.c   
+*   
+* Description:	Initialization function of DCT-4 & IDCT4 Q31   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup DCT4_IDCT4   
+ * @{   
+ */
+
+/*   
+* @brief  Weights Table   
+*/
+
+/**   
+* \par   
+* Weights tables are generated using the formula : 
    weights[n] = e^(-j*n*pi/(2*N))
       
+* \par   
+* C command to generate the table   
+* 
       
+* for(i = 0; i< N; i++)   
+* {   
+*   weights[2*i]= cos(i*c);   
+*   weights[(2*i)+1]= -sin(i * c);   
+* } 
       
+* \par   
+* where N is the Number of weights to be calculated and c is pi/(2*N)   
+* \par   
+* Convert the output to q31 format by multiplying with 2^31 and saturated if required.   
+* \par   
+* In the tables below the real and imaginary values are placed alternatively, hence the   
+* array length is 2*N.   
+*/
+
+static const q31_t WeightsQ31_128[256] = {
+  0x7fffffff, 0x0, 0x7ffd885a, 0xfe6de2e0, 0x7ff62182, 0xfcdbd541, 0x7fe9cbc0,
+  0xfb49e6a3,
+  0x7fd8878e, 0xf9b82684, 0x7fc25596, 0xf826a462, 0x7fa736b4, 0xf6956fb7,
+  0x7f872bf3, 0xf50497fb,
+  0x7f62368f, 0xf3742ca2, 0x7f3857f6, 0xf1e43d1c, 0x7f0991c4, 0xf054d8d5,
+  0x7ed5e5c6, 0xeec60f31,
+  0x7e9d55fc, 0xed37ef91, 0x7e5fe493, 0xebaa894f, 0x7e1d93ea, 0xea1debbb,
+  0x7dd6668f, 0xe8922622,
+  0x7d8a5f40, 0xe70747c4, 0x7d3980ec, 0xe57d5fda, 0x7ce3ceb2, 0xe3f47d96,
+  0x7c894bde, 0xe26cb01b,
+  0x7c29fbee, 0xe0e60685, 0x7bc5e290, 0xdf608fe4, 0x7b5d039e, 0xdddc5b3b,
+  0x7aef6323, 0xdc597781,
+  0x7a7d055b, 0xdad7f3a2, 0x7a05eead, 0xd957de7a, 0x798a23b1, 0xd7d946d8,
+  0x7909a92d, 0xd65c3b7b,
+  0x78848414, 0xd4e0cb15, 0x77fab989, 0xd3670446, 0x776c4edb, 0xd1eef59e,
+  0x76d94989, 0xd078ad9e,
+  0x7641af3d, 0xcf043ab3, 0x75a585cf, 0xcd91ab39, 0x7504d345, 0xcc210d79,
+  0x745f9dd1, 0xcab26fa9,
+  0x73b5ebd1, 0xc945dfec, 0x7307c3d0, 0xc7db6c50, 0x72552c85, 0xc67322ce,
+  0x719e2cd2, 0xc50d1149,
+  0x70e2cbc6, 0xc3a94590, 0x7023109a, 0xc247cd5a, 0x6f5f02b2, 0xc0e8b648,
+  0x6e96a99d, 0xbf8c0de3,
+  0x6dca0d14, 0xbe31e19b, 0x6cf934fc, 0xbcda3ecb, 0x6c242960, 0xbb8532b0,
+  0x6b4af279, 0xba32ca71,
+  0x6a6d98a4, 0xb8e31319, 0x698c246c, 0xb796199b, 0x68a69e81, 0xb64beacd,
+  0x67bd0fbd, 0xb5049368,
+  0x66cf8120, 0xb3c0200c, 0x65ddfbd3, 0xb27e9d3c, 0x64e88926, 0xb140175b,
+  0x63ef3290, 0xb0049ab3,
+  0x62f201ac, 0xaecc336c, 0x61f1003f, 0xad96ed92, 0x60ec3830, 0xac64d510,
+  0x5fe3b38d, 0xab35f5b5,
+  0x5ed77c8a, 0xaa0a5b2e, 0x5dc79d7c, 0xa8e21106, 0x5cb420e0, 0xa7bd22ac,
+  0x5b9d1154, 0xa69b9b68,
+  0x5a82799a, 0xa57d8666, 0x59646498, 0xa462eeac, 0x5842dd54, 0xa34bdf20,
+  0x571deefa, 0xa2386284,
+  0x55f5a4d2, 0xa1288376, 0x54ca0a4b, 0xa01c4c73, 0x539b2af0, 0x9f13c7d0,
+  0x5269126e, 0x9e0effc1,
+  0x5133cc94, 0x9d0dfe54, 0x4ffb654d, 0x9c10cd70, 0x4ebfe8a5, 0x9b1776da,
+  0x4d8162c4, 0x9a22042d,
+  0x4c3fdff4, 0x99307ee0, 0x4afb6c98, 0x9842f043, 0x49b41533, 0x9759617f,
+  0x4869e665, 0x9673db94,
+  0x471cece7, 0x9592675c, 0x45cd358f, 0x94b50d87, 0x447acd50, 0x93dbd6a0,
+  0x4325c135, 0x9306cb04,
+  0x41ce1e65, 0x9235f2ec, 0x4073f21d, 0x91695663, 0x3f1749b8, 0x90a0fd4e,
+  0x3db832a6, 0x8fdcef66,
+  0x3c56ba70, 0x8f1d343a, 0x3af2eeb7, 0x8e61d32e, 0x398cdd32, 0x8daad37b,
+  0x382493b0, 0x8cf83c30,
+  0x36ba2014, 0x8c4a142f, 0x354d9057, 0x8ba0622f, 0x33def287, 0x8afb2cbb,
+  0x326e54c7, 0x8a5a7a31,
+  0x30fbc54d, 0x89be50c3, 0x2f875262, 0x8926b677, 0x2e110a62, 0x8893b125,
+  0x2c98fbba, 0x88054677,
+  0x2b1f34eb, 0x877b7bec, 0x29a3c485, 0x86f656d3, 0x2826b928, 0x8675dc4f,
+  0x26a82186, 0x85fa1153,
+  0x25280c5e, 0x8582faa5, 0x23a6887f, 0x85109cdd, 0x2223a4c5, 0x84a2fc62,
+  0x209f701c, 0x843a1d70,
+  0x1f19f97b, 0x83d60412, 0x1d934fe5, 0x8376b422, 0x1c0b826a, 0x831c314e,
+  0x1a82a026, 0x82c67f14,
+  0x18f8b83c, 0x8275a0c0, 0x176dd9de, 0x82299971, 0x15e21445, 0x81e26c16,
+  0x145576b1, 0x81a01b6d,
+  0x12c8106f, 0x8162aa04, 0x1139f0cf, 0x812a1a3a, 0xfab272b, 0x80f66e3c,
+  0xe1bc2e4, 0x80c7a80a,
+  0xc8bd35e, 0x809dc971, 0xafb6805, 0x8078d40d, 0x96a9049, 0x8058c94c,
+  0x7d95b9e, 0x803daa6a,
+  0x647d97c, 0x80277872, 0x4b6195d, 0x80163440, 0x3242abf, 0x8009de7e,
+  0x1921d20, 0x800277a6,
+};
+
+static const q31_t WeightsQ31_512[1024] = {
+  0x7fffffff, 0x0, 0x7fffd886, 0xff9b781d, 0x7fff6216, 0xff36f078, 0x7ffe9cb2,
+  0xfed2694f,
+  0x7ffd885a, 0xfe6de2e0, 0x7ffc250f, 0xfe095d69, 0x7ffa72d1, 0xfda4d929,
+  0x7ff871a2, 0xfd40565c,
+  0x7ff62182, 0xfcdbd541, 0x7ff38274, 0xfc775616, 0x7ff09478, 0xfc12d91a,
+  0x7fed5791, 0xfbae5e89,
+  0x7fe9cbc0, 0xfb49e6a3, 0x7fe5f108, 0xfae571a4, 0x7fe1c76b, 0xfa80ffcb,
+  0x7fdd4eec, 0xfa1c9157,
+  0x7fd8878e, 0xf9b82684, 0x7fd37153, 0xf953bf91, 0x7fce0c3e, 0xf8ef5cbb,
+  0x7fc85854, 0xf88afe42,
+  0x7fc25596, 0xf826a462, 0x7fbc040a, 0xf7c24f59, 0x7fb563b3, 0xf75dff66,
+  0x7fae7495, 0xf6f9b4c6,
+  0x7fa736b4, 0xf6956fb7, 0x7f9faa15, 0xf6313077, 0x7f97cebd, 0xf5ccf743,
+  0x7f8fa4b0, 0xf568c45b,
+  0x7f872bf3, 0xf50497fb, 0x7f7e648c, 0xf4a07261, 0x7f754e80, 0xf43c53cb,
+  0x7f6be9d4, 0xf3d83c77,
+  0x7f62368f, 0xf3742ca2, 0x7f5834b7, 0xf310248a, 0x7f4de451, 0xf2ac246e,
+  0x7f434563, 0xf2482c8a,
+  0x7f3857f6, 0xf1e43d1c, 0x7f2d1c0e, 0xf1805662, 0x7f2191b4, 0xf11c789a,
+  0x7f15b8ee, 0xf0b8a401,
+  0x7f0991c4, 0xf054d8d5, 0x7efd1c3c, 0xeff11753, 0x7ef05860, 0xef8d5fb8,
+  0x7ee34636, 0xef29b243,
+  0x7ed5e5c6, 0xeec60f31, 0x7ec8371a, 0xee6276bf, 0x7eba3a39, 0xedfee92b,
+  0x7eabef2c, 0xed9b66b2,
+  0x7e9d55fc, 0xed37ef91, 0x7e8e6eb2, 0xecd48407, 0x7e7f3957, 0xec71244f,
+  0x7e6fb5f4, 0xec0dd0a8,
+  0x7e5fe493, 0xebaa894f, 0x7e4fc53e, 0xeb474e81, 0x7e3f57ff, 0xeae4207a,
+  0x7e2e9cdf, 0xea80ff7a,
+  0x7e1d93ea, 0xea1debbb, 0x7e0c3d29, 0xe9bae57d, 0x7dfa98a8, 0xe957ecfb,
+  0x7de8a670, 0xe8f50273,
+  0x7dd6668f, 0xe8922622, 0x7dc3d90d, 0xe82f5844, 0x7db0fdf8, 0xe7cc9917,
+  0x7d9dd55a, 0xe769e8d8,
+  0x7d8a5f40, 0xe70747c4, 0x7d769bb5, 0xe6a4b616, 0x7d628ac6, 0xe642340d,
+  0x7d4e2c7f, 0xe5dfc1e5,
+  0x7d3980ec, 0xe57d5fda, 0x7d24881b, 0xe51b0e2a, 0x7d0f4218, 0xe4b8cd11,
+  0x7cf9aef0, 0xe4569ccb,
+  0x7ce3ceb2, 0xe3f47d96, 0x7ccda169, 0xe3926fad, 0x7cb72724, 0xe330734d,
+  0x7ca05ff1, 0xe2ce88b3,
+  0x7c894bde, 0xe26cb01b, 0x7c71eaf9, 0xe20ae9c1, 0x7c5a3d50, 0xe1a935e2,
+  0x7c4242f2, 0xe14794ba,
+  0x7c29fbee, 0xe0e60685, 0x7c116853, 0xe0848b7f, 0x7bf88830, 0xe02323e5,
+  0x7bdf5b94, 0xdfc1cff3,
+  0x7bc5e290, 0xdf608fe4, 0x7bac1d31, 0xdeff63f4, 0x7b920b89, 0xde9e4c60,
+  0x7b77ada8, 0xde3d4964,
+  0x7b5d039e, 0xdddc5b3b, 0x7b420d7a, 0xdd7b8220, 0x7b26cb4f, 0xdd1abe51,
+  0x7b0b3d2c, 0xdcba1008,
+  0x7aef6323, 0xdc597781, 0x7ad33d45, 0xdbf8f4f8, 0x7ab6cba4, 0xdb9888a8,
+  0x7a9a0e50, 0xdb3832cd,
+  0x7a7d055b, 0xdad7f3a2, 0x7a5fb0d8, 0xda77cb63, 0x7a4210d8, 0xda17ba4a,
+  0x7a24256f, 0xd9b7c094,
+  0x7a05eead, 0xd957de7a, 0x79e76ca7, 0xd8f81439, 0x79c89f6e, 0xd898620c,
+  0x79a98715, 0xd838c82d,
+  0x798a23b1, 0xd7d946d8, 0x796a7554, 0xd779de47, 0x794a7c12, 0xd71a8eb5,
+  0x792a37fe, 0xd6bb585e,
+  0x7909a92d, 0xd65c3b7b, 0x78e8cfb2, 0xd5fd3848, 0x78c7aba2, 0xd59e4eff,
+  0x78a63d11, 0xd53f7fda,
+  0x78848414, 0xd4e0cb15, 0x786280bf, 0xd48230e9, 0x78403329, 0xd423b191,
+  0x781d9b65, 0xd3c54d47,
+  0x77fab989, 0xd3670446, 0x77d78daa, 0xd308d6c7, 0x77b417df, 0xd2aac504,
+  0x7790583e, 0xd24ccf39,
+  0x776c4edb, 0xd1eef59e, 0x7747fbce, 0xd191386e, 0x77235f2d, 0xd13397e2,
+  0x76fe790e, 0xd0d61434,
+  0x76d94989, 0xd078ad9e, 0x76b3d0b4, 0xd01b6459, 0x768e0ea6, 0xcfbe389f,
+  0x76680376, 0xcf612aaa,
+  0x7641af3d, 0xcf043ab3, 0x761b1211, 0xcea768f2, 0x75f42c0b, 0xce4ab5a2,
+  0x75ccfd42, 0xcdee20fc,
+  0x75a585cf, 0xcd91ab39, 0x757dc5ca, 0xcd355491, 0x7555bd4c, 0xccd91d3d,
+  0x752d6c6c, 0xcc7d0578,
+  0x7504d345, 0xcc210d79, 0x74dbf1ef, 0xcbc53579, 0x74b2c884, 0xcb697db0,
+  0x7489571c, 0xcb0de658,
+  0x745f9dd1, 0xcab26fa9, 0x74359cbd, 0xca5719db, 0x740b53fb, 0xc9fbe527,
+  0x73e0c3a3, 0xc9a0d1c5,
+  0x73b5ebd1, 0xc945dfec, 0x738acc9e, 0xc8eb0fd6, 0x735f6626, 0xc89061ba,
+  0x7333b883, 0xc835d5d0,
+  0x7307c3d0, 0xc7db6c50, 0x72db8828, 0xc7812572, 0x72af05a7, 0xc727016d,
+  0x72823c67, 0xc6cd0079,
+  0x72552c85, 0xc67322ce, 0x7227d61c, 0xc61968a2, 0x71fa3949, 0xc5bfd22e,
+  0x71cc5626, 0xc5665fa9,
+  0x719e2cd2, 0xc50d1149, 0x716fbd68, 0xc4b3e746, 0x71410805, 0xc45ae1d7,
+  0x71120cc5, 0xc4020133,
+  0x70e2cbc6, 0xc3a94590, 0x70b34525, 0xc350af26, 0x708378ff, 0xc2f83e2a,
+  0x70536771, 0xc29ff2d4,
+  0x7023109a, 0xc247cd5a, 0x6ff27497, 0xc1efcdf3, 0x6fc19385, 0xc197f4d4,
+  0x6f906d84, 0xc1404233,
+  0x6f5f02b2, 0xc0e8b648, 0x6f2d532c, 0xc0915148, 0x6efb5f12, 0xc03a1368,
+  0x6ec92683, 0xbfe2fcdf,
+  0x6e96a99d, 0xbf8c0de3, 0x6e63e87f, 0xbf3546a8, 0x6e30e34a, 0xbedea765,
+  0x6dfd9a1c, 0xbe88304f,
+  0x6dca0d14, 0xbe31e19b, 0x6d963c54, 0xbddbbb7f, 0x6d6227fa, 0xbd85be30,
+  0x6d2dd027, 0xbd2fe9e2,
+  0x6cf934fc, 0xbcda3ecb, 0x6cc45698, 0xbc84bd1f, 0x6c8f351c, 0xbc2f6513,
+  0x6c59d0a9, 0xbbda36dd,
+  0x6c242960, 0xbb8532b0, 0x6bee3f62, 0xbb3058c0, 0x6bb812d1, 0xbadba943,
+  0x6b81a3cd, 0xba87246d,
+  0x6b4af279, 0xba32ca71, 0x6b13fef5, 0xb9de9b83, 0x6adcc964, 0xb98a97d8,
+  0x6aa551e9, 0xb936bfa4,
+  0x6a6d98a4, 0xb8e31319, 0x6a359db9, 0xb88f926d, 0x69fd614a, 0xb83c3dd1,
+  0x69c4e37a, 0xb7e9157a,
+  0x698c246c, 0xb796199b, 0x69532442, 0xb7434a67, 0x6919e320, 0xb6f0a812,
+  0x68e06129, 0xb69e32cd,
+  0x68a69e81, 0xb64beacd, 0x686c9b4b, 0xb5f9d043, 0x683257ab, 0xb5a7e362,
+  0x67f7d3c5, 0xb556245e,
+  0x67bd0fbd, 0xb5049368, 0x67820bb7, 0xb4b330b3, 0x6746c7d8, 0xb461fc70,
+  0x670b4444, 0xb410f6d3,
+  0x66cf8120, 0xb3c0200c, 0x66937e91, 0xb36f784f, 0x66573cbb, 0xb31effcc,
+  0x661abbc5, 0xb2ceb6b5,
+  0x65ddfbd3, 0xb27e9d3c, 0x65a0fd0b, 0xb22eb392, 0x6563bf92, 0xb1def9e9,
+  0x6526438f, 0xb18f7071,
+  0x64e88926, 0xb140175b, 0x64aa907f, 0xb0f0eeda, 0x646c59bf, 0xb0a1f71d,
+  0x642de50d, 0xb0533055,
+  0x63ef3290, 0xb0049ab3, 0x63b0426d, 0xafb63667, 0x637114cc, 0xaf6803a2,
+  0x6331a9d4, 0xaf1a0293,
+  0x62f201ac, 0xaecc336c, 0x62b21c7b, 0xae7e965b, 0x6271fa69, 0xae312b92,
+  0x62319b9d, 0xade3f33e,
+  0x61f1003f, 0xad96ed92, 0x61b02876, 0xad4a1aba, 0x616f146c, 0xacfd7ae8,
+  0x612dc447, 0xacb10e4b,
+  0x60ec3830, 0xac64d510, 0x60aa7050, 0xac18cf69, 0x60686ccf, 0xabccfd83,
+  0x60262dd6, 0xab815f8d,
+  0x5fe3b38d, 0xab35f5b5, 0x5fa0fe1f, 0xaaeac02c, 0x5f5e0db3, 0xaa9fbf1e,
+  0x5f1ae274, 0xaa54f2ba,
+  0x5ed77c8a, 0xaa0a5b2e, 0x5e93dc1f, 0xa9bff8a8, 0x5e50015d, 0xa975cb57,
+  0x5e0bec6e, 0xa92bd367,
+  0x5dc79d7c, 0xa8e21106, 0x5d8314b1, 0xa8988463, 0x5d3e5237, 0xa84f2daa,
+  0x5cf95638, 0xa8060d08,
+  0x5cb420e0, 0xa7bd22ac, 0x5c6eb258, 0xa7746ec0, 0x5c290acc, 0xa72bf174,
+  0x5be32a67, 0xa6e3aaf2,
+  0x5b9d1154, 0xa69b9b68, 0x5b56bfbd, 0xa653c303, 0x5b1035cf, 0xa60c21ee,
+  0x5ac973b5, 0xa5c4b855,
+  0x5a82799a, 0xa57d8666, 0x5a3b47ab, 0xa5368c4b, 0x59f3de12, 0xa4efca31,
+  0x59ac3cfd, 0xa4a94043,
+  0x59646498, 0xa462eeac, 0x591c550e, 0xa41cd599, 0x58d40e8c, 0xa3d6f534,
+  0x588b9140, 0xa3914da8,
+  0x5842dd54, 0xa34bdf20, 0x57f9f2f8, 0xa306a9c8, 0x57b0d256, 0xa2c1adc9,
+  0x57677b9d, 0xa27ceb4f,
+  0x571deefa, 0xa2386284, 0x56d42c99, 0xa1f41392, 0x568a34a9, 0xa1affea3,
+  0x56400758, 0xa16c23e1,
+  0x55f5a4d2, 0xa1288376, 0x55ab0d46, 0xa0e51d8c, 0x556040e2, 0xa0a1f24d,
+  0x55153fd4, 0xa05f01e1,
+  0x54ca0a4b, 0xa01c4c73, 0x547ea073, 0x9fd9d22a, 0x5433027d, 0x9f979331,
+  0x53e73097, 0x9f558fb0,
+  0x539b2af0, 0x9f13c7d0, 0x534ef1b5, 0x9ed23bb9, 0x53028518, 0x9e90eb94,
+  0x52b5e546, 0x9e4fd78a,
+  0x5269126e, 0x9e0effc1, 0x521c0cc2, 0x9dce6463, 0x51ced46e, 0x9d8e0597,
+  0x518169a5, 0x9d4de385,
+  0x5133cc94, 0x9d0dfe54, 0x50e5fd6d, 0x9cce562c, 0x5097fc5e, 0x9c8eeb34,
+  0x5049c999, 0x9c4fbd93,
+  0x4ffb654d, 0x9c10cd70, 0x4faccfab, 0x9bd21af3, 0x4f5e08e3, 0x9b93a641,
+  0x4f0f1126, 0x9b556f81,
+  0x4ebfe8a5, 0x9b1776da, 0x4e708f8f, 0x9ad9bc71, 0x4e210617, 0x9a9c406e,
+  0x4dd14c6e, 0x9a5f02f5,
+  0x4d8162c4, 0x9a22042d, 0x4d31494b, 0x99e5443b, 0x4ce10034, 0x99a8c345,
+  0x4c9087b1, 0x996c816f,
+  0x4c3fdff4, 0x99307ee0, 0x4bef092d, 0x98f4bbbc, 0x4b9e0390, 0x98b93828,
+  0x4b4ccf4d, 0x987df449,
+  0x4afb6c98, 0x9842f043, 0x4aa9dba2, 0x98082c3b, 0x4a581c9e, 0x97cda855,
+  0x4a062fbd, 0x979364b5,
+  0x49b41533, 0x9759617f, 0x4961cd33, 0x971f9ed7, 0x490f57ee, 0x96e61ce0,
+  0x48bcb599, 0x96acdbbe,
+  0x4869e665, 0x9673db94, 0x4816ea86, 0x963b1c86, 0x47c3c22f, 0x96029eb6,
+  0x47706d93, 0x95ca6247,
+  0x471cece7, 0x9592675c, 0x46c9405c, 0x955aae17, 0x46756828, 0x9523369c,
+  0x4621647d, 0x94ec010b,
+  0x45cd358f, 0x94b50d87, 0x4578db93, 0x947e5c33, 0x452456bd, 0x9447ed2f,
+  0x44cfa740, 0x9411c09e,
+  0x447acd50, 0x93dbd6a0, 0x4425c923, 0x93a62f57, 0x43d09aed, 0x9370cae4,
+  0x437b42e1, 0x933ba968,
+  0x4325c135, 0x9306cb04, 0x42d0161e, 0x92d22fd9, 0x427a41d0, 0x929dd806,
+  0x42244481, 0x9269c3ac,
+  0x41ce1e65, 0x9235f2ec, 0x4177cfb1, 0x920265e4, 0x4121589b, 0x91cf1cb6,
+  0x40cab958, 0x919c1781,
+  0x4073f21d, 0x91695663, 0x401d0321, 0x9136d97d, 0x3fc5ec98, 0x9104a0ee,
+  0x3f6eaeb8, 0x90d2acd4,
+  0x3f1749b8, 0x90a0fd4e, 0x3ebfbdcd, 0x906f927c, 0x3e680b2c, 0x903e6c7b,
+  0x3e10320d, 0x900d8b69,
+  0x3db832a6, 0x8fdcef66, 0x3d600d2c, 0x8fac988f, 0x3d07c1d6, 0x8f7c8701,
+  0x3caf50da, 0x8f4cbadb,
+  0x3c56ba70, 0x8f1d343a, 0x3bfdfecd, 0x8eedf33b, 0x3ba51e29, 0x8ebef7fb,
+  0x3b4c18ba, 0x8e904298,
+  0x3af2eeb7, 0x8e61d32e, 0x3a99a057, 0x8e33a9da, 0x3a402dd2, 0x8e05c6b7,
+  0x39e6975e, 0x8dd829e4,
+  0x398cdd32, 0x8daad37b, 0x3932ff87, 0x8d7dc399, 0x38d8fe93, 0x8d50fa59,
+  0x387eda8e, 0x8d2477d8,
+  0x382493b0, 0x8cf83c30, 0x37ca2a30, 0x8ccc477d, 0x376f9e46, 0x8ca099da,
+  0x3714f02a, 0x8c753362,
+  0x36ba2014, 0x8c4a142f, 0x365f2e3b, 0x8c1f3c5d, 0x36041ad9, 0x8bf4ac05,
+  0x35a8e625, 0x8bca6343,
+  0x354d9057, 0x8ba0622f, 0x34f219a8, 0x8b76a8e4, 0x34968250, 0x8b4d377c,
+  0x343aca87, 0x8b240e11,
+  0x33def287, 0x8afb2cbb, 0x3382fa88, 0x8ad29394, 0x3326e2c3, 0x8aaa42b4,
+  0x32caab6f, 0x8a823a36,
+  0x326e54c7, 0x8a5a7a31, 0x3211df04, 0x8a3302be, 0x31b54a5e, 0x8a0bd3f5,
+  0x3158970e, 0x89e4edef,
+  0x30fbc54d, 0x89be50c3, 0x309ed556, 0x8997fc8a, 0x3041c761, 0x8971f15a,
+  0x2fe49ba7, 0x894c2f4c,
+  0x2f875262, 0x8926b677, 0x2f29ebcc, 0x890186f2, 0x2ecc681e, 0x88dca0d3,
+  0x2e6ec792, 0x88b80432,
+  0x2e110a62, 0x8893b125, 0x2db330c7, 0x886fa7c2, 0x2d553afc, 0x884be821,
+  0x2cf72939, 0x88287256,
+  0x2c98fbba, 0x88054677, 0x2c3ab2b9, 0x87e2649b, 0x2bdc4e6f, 0x87bfccd7,
+  0x2b7dcf17, 0x879d7f41,
+  0x2b1f34eb, 0x877b7bec, 0x2ac08026, 0x8759c2ef, 0x2a61b101, 0x8738545e,
+  0x2a02c7b8, 0x8717304e,
+  0x29a3c485, 0x86f656d3, 0x2944a7a2, 0x86d5c802, 0x28e5714b, 0x86b583ee,
+  0x288621b9, 0x86958aac,
+  0x2826b928, 0x8675dc4f, 0x27c737d3, 0x865678eb, 0x27679df4, 0x86376092,
+  0x2707ebc7, 0x86189359,
+  0x26a82186, 0x85fa1153, 0x26483f6c, 0x85dbda91, 0x25e845b6, 0x85bdef28,
+  0x2588349d, 0x85a04f28,
+  0x25280c5e, 0x8582faa5, 0x24c7cd33, 0x8565f1b0, 0x24677758, 0x8549345c,
+  0x24070b08, 0x852cc2bb,
+  0x23a6887f, 0x85109cdd, 0x2345eff8, 0x84f4c2d4, 0x22e541af, 0x84d934b1,
+  0x22847de0, 0x84bdf286,
+  0x2223a4c5, 0x84a2fc62, 0x21c2b69c, 0x84885258, 0x2161b3a0, 0x846df477,
+  0x21009c0c, 0x8453e2cf,
+  0x209f701c, 0x843a1d70, 0x203e300d, 0x8420a46c, 0x1fdcdc1b, 0x840777d0,
+  0x1f7b7481, 0x83ee97ad,
+  0x1f19f97b, 0x83d60412, 0x1eb86b46, 0x83bdbd0e, 0x1e56ca1e, 0x83a5c2b0,
+  0x1df5163f, 0x838e1507,
+  0x1d934fe5, 0x8376b422, 0x1d31774d, 0x835fa00f, 0x1ccf8cb3, 0x8348d8dc,
+  0x1c6d9053, 0x83325e97,
+  0x1c0b826a, 0x831c314e, 0x1ba96335, 0x83065110, 0x1b4732ef, 0x82f0bde8,
+  0x1ae4f1d6, 0x82db77e5,
+  0x1a82a026, 0x82c67f14, 0x1a203e1b, 0x82b1d381, 0x19bdcbf3, 0x829d753a,
+  0x195b49ea, 0x8289644b,
+  0x18f8b83c, 0x8275a0c0, 0x18961728, 0x82622aa6, 0x183366e9, 0x824f0208,
+  0x17d0a7bc, 0x823c26f3,
+  0x176dd9de, 0x82299971, 0x170afd8d, 0x82175990, 0x16a81305, 0x82056758,
+  0x16451a83, 0x81f3c2d7,
+  0x15e21445, 0x81e26c16, 0x157f0086, 0x81d16321, 0x151bdf86, 0x81c0a801,
+  0x14b8b17f, 0x81b03ac2,
+  0x145576b1, 0x81a01b6d, 0x13f22f58, 0x81904a0c, 0x138edbb1, 0x8180c6a9,
+  0x132b7bf9, 0x8171914e,
+  0x12c8106f, 0x8162aa04, 0x1264994e, 0x815410d4, 0x120116d5, 0x8145c5c7,
+  0x119d8941, 0x8137c8e6,
+  0x1139f0cf, 0x812a1a3a, 0x10d64dbd, 0x811cb9ca, 0x1072a048, 0x810fa7a0,
+  0x100ee8ad, 0x8102e3c4,
+  0xfab272b, 0x80f66e3c, 0xf475bff, 0x80ea4712, 0xee38766, 0x80de6e4c,
+  0xe7fa99e, 0x80d2e3f2,
+  0xe1bc2e4, 0x80c7a80a, 0xdb7d376, 0x80bcba9d, 0xd53db92, 0x80b21baf,
+  0xcefdb76, 0x80a7cb49,
+  0xc8bd35e, 0x809dc971, 0xc27c389, 0x8094162c, 0xbc3ac35, 0x808ab180,
+  0xb5f8d9f, 0x80819b74,
+  0xafb6805, 0x8078d40d, 0xa973ba5, 0x80705b50, 0xa3308bd, 0x80683143,
+  0x9cecf89, 0x806055eb,
+  0x96a9049, 0x8058c94c, 0x9064b3a, 0x80518b6b, 0x8a2009a, 0x804a9c4d,
+  0x83db0a7, 0x8043fbf6,
+  0x7d95b9e, 0x803daa6a, 0x77501be, 0x8037a7ac, 0x710a345, 0x8031f3c2,
+  0x6ac406f, 0x802c8ead,
+  0x647d97c, 0x80277872, 0x5e36ea9, 0x8022b114, 0x57f0035, 0x801e3895,
+  0x51a8e5c, 0x801a0ef8,
+  0x4b6195d, 0x80163440, 0x451a177, 0x8012a86f, 0x3ed26e6, 0x800f6b88,
+  0x388a9ea, 0x800c7d8c,
+  0x3242abf, 0x8009de7e, 0x2bfa9a4, 0x80078e5e, 0x25b26d7, 0x80058d2f,
+  0x1f6a297, 0x8003daf1,
+  0x1921d20, 0x800277a6, 0x12d96b1, 0x8001634e, 0xc90f88, 0x80009dea,
+  0x6487e3, 0x8000277a,
+};
+
+static const q31_t WeightsQ31_2048[4096] = {
+  0x7fffffff, 0x0, 0x7ffffd88, 0xffe6de05, 0x7ffff621, 0xffcdbc0b, 0x7fffe9cb,
+  0xffb49a12,
+  0x7fffd886, 0xff9b781d, 0x7fffc251, 0xff82562c, 0x7fffa72c, 0xff69343f,
+  0x7fff8719, 0xff501258,
+  0x7fff6216, 0xff36f078, 0x7fff3824, 0xff1dcea0, 0x7fff0943, 0xff04acd0,
+  0x7ffed572, 0xfeeb8b0a,
+  0x7ffe9cb2, 0xfed2694f, 0x7ffe5f03, 0xfeb947a0, 0x7ffe1c65, 0xfea025fd,
+  0x7ffdd4d7, 0xfe870467,
+  0x7ffd885a, 0xfe6de2e0, 0x7ffd36ee, 0xfe54c169, 0x7ffce093, 0xfe3ba002,
+  0x7ffc8549, 0xfe227eac,
+  0x7ffc250f, 0xfe095d69, 0x7ffbbfe6, 0xfdf03c3a, 0x7ffb55ce, 0xfdd71b1e,
+  0x7ffae6c7, 0xfdbdfa18,
+  0x7ffa72d1, 0xfda4d929, 0x7ff9f9ec, 0xfd8bb850, 0x7ff97c18, 0xfd729790,
+  0x7ff8f954, 0xfd5976e9,
+  0x7ff871a2, 0xfd40565c, 0x7ff7e500, 0xfd2735ea, 0x7ff75370, 0xfd0e1594,
+  0x7ff6bcf0, 0xfcf4f55c,
+  0x7ff62182, 0xfcdbd541, 0x7ff58125, 0xfcc2b545, 0x7ff4dbd9, 0xfca9956a,
+  0x7ff4319d, 0xfc9075af,
+  0x7ff38274, 0xfc775616, 0x7ff2ce5b, 0xfc5e36a0, 0x7ff21553, 0xfc45174e,
+  0x7ff1575d, 0xfc2bf821,
+  0x7ff09478, 0xfc12d91a, 0x7fefcca4, 0xfbf9ba39, 0x7feeffe1, 0xfbe09b80,
+  0x7fee2e30, 0xfbc77cf0,
+  0x7fed5791, 0xfbae5e89, 0x7fec7c02, 0xfb95404d, 0x7feb9b85, 0xfb7c223d,
+  0x7feab61a, 0xfb630459,
+  0x7fe9cbc0, 0xfb49e6a3, 0x7fe8dc78, 0xfb30c91b, 0x7fe7e841, 0xfb17abc2,
+  0x7fe6ef1c, 0xfafe8e9b,
+  0x7fe5f108, 0xfae571a4, 0x7fe4ee06, 0xfacc54e0, 0x7fe3e616, 0xfab3384f,
+  0x7fe2d938, 0xfa9a1bf3,
+  0x7fe1c76b, 0xfa80ffcb, 0x7fe0b0b1, 0xfa67e3da, 0x7fdf9508, 0xfa4ec821,
+  0x7fde7471, 0xfa35ac9f,
+  0x7fdd4eec, 0xfa1c9157, 0x7fdc247a, 0xfa037648, 0x7fdaf519, 0xf9ea5b75,
+  0x7fd9c0ca, 0xf9d140de,
+  0x7fd8878e, 0xf9b82684, 0x7fd74964, 0xf99f0c68, 0x7fd6064c, 0xf985f28a,
+  0x7fd4be46, 0xf96cd8ed,
+  0x7fd37153, 0xf953bf91, 0x7fd21f72, 0xf93aa676, 0x7fd0c8a3, 0xf9218d9e,
+  0x7fcf6ce8, 0xf908750a,
+  0x7fce0c3e, 0xf8ef5cbb, 0x7fcca6a7, 0xf8d644b2, 0x7fcb3c23, 0xf8bd2cef,
+  0x7fc9ccb2, 0xf8a41574,
+  0x7fc85854, 0xf88afe42, 0x7fc6df08, 0xf871e759, 0x7fc560cf, 0xf858d0bb,
+  0x7fc3dda9, 0xf83fba68,
+  0x7fc25596, 0xf826a462, 0x7fc0c896, 0xf80d8ea9, 0x7fbf36aa, 0xf7f4793e,
+  0x7fbd9fd0, 0xf7db6423,
+  0x7fbc040a, 0xf7c24f59, 0x7fba6357, 0xf7a93ae0, 0x7fb8bdb8, 0xf79026b9,
+  0x7fb7132b, 0xf77712e5,
+  0x7fb563b3, 0xf75dff66, 0x7fb3af4e, 0xf744ec3b, 0x7fb1f5fc, 0xf72bd967,
+  0x7fb037bf, 0xf712c6ea,
+  0x7fae7495, 0xf6f9b4c6, 0x7facac7f, 0xf6e0a2fa, 0x7faadf7c, 0xf6c79188,
+  0x7fa90d8e, 0xf6ae8071,
+  0x7fa736b4, 0xf6956fb7, 0x7fa55aee, 0xf67c5f59, 0x7fa37a3c, 0xf6634f59,
+  0x7fa1949e, 0xf64a3fb8,
+  0x7f9faa15, 0xf6313077, 0x7f9dbaa0, 0xf6182196, 0x7f9bc640, 0xf5ff1318,
+  0x7f99ccf4, 0xf5e604fc,
+  0x7f97cebd, 0xf5ccf743, 0x7f95cb9a, 0xf5b3e9f0, 0x7f93c38c, 0xf59add02,
+  0x7f91b694, 0xf581d07b,
+  0x7f8fa4b0, 0xf568c45b, 0x7f8d8de1, 0xf54fb8a4, 0x7f8b7227, 0xf536ad56,
+  0x7f895182, 0xf51da273,
+  0x7f872bf3, 0xf50497fb, 0x7f850179, 0xf4eb8def, 0x7f82d214, 0xf4d28451,
+  0x7f809dc5, 0xf4b97b21,
+  0x7f7e648c, 0xf4a07261, 0x7f7c2668, 0xf4876a10, 0x7f79e35a, 0xf46e6231,
+  0x7f779b62, 0xf4555ac5,
+  0x7f754e80, 0xf43c53cb, 0x7f72fcb4, 0xf4234d45, 0x7f70a5fe, 0xf40a4735,
+  0x7f6e4a5e, 0xf3f1419a,
+  0x7f6be9d4, 0xf3d83c77, 0x7f698461, 0xf3bf37cb, 0x7f671a05, 0xf3a63398,
+  0x7f64aabf, 0xf38d2fe0,
+  0x7f62368f, 0xf3742ca2, 0x7f5fbd77, 0xf35b29e0, 0x7f5d3f75, 0xf342279b,
+  0x7f5abc8a, 0xf32925d3,
+  0x7f5834b7, 0xf310248a, 0x7f55a7fa, 0xf2f723c1, 0x7f531655, 0xf2de2379,
+  0x7f507fc7, 0xf2c523b2,
+  0x7f4de451, 0xf2ac246e, 0x7f4b43f2, 0xf29325ad, 0x7f489eaa, 0xf27a2771,
+  0x7f45f47b, 0xf26129ba,
+  0x7f434563, 0xf2482c8a, 0x7f409164, 0xf22f2fe1, 0x7f3dd87c, 0xf21633c0,
+  0x7f3b1aad, 0xf1fd3829,
+  0x7f3857f6, 0xf1e43d1c, 0x7f359057, 0xf1cb429a, 0x7f32c3d1, 0xf1b248a5,
+  0x7f2ff263, 0xf1994f3d,
+  0x7f2d1c0e, 0xf1805662, 0x7f2a40d2, 0xf1675e17, 0x7f2760af, 0xf14e665c,
+  0x7f247ba5, 0xf1356f32,
+  0x7f2191b4, 0xf11c789a, 0x7f1ea2dc, 0xf1038295, 0x7f1baf1e, 0xf0ea8d24,
+  0x7f18b679, 0xf0d19848,
+  0x7f15b8ee, 0xf0b8a401, 0x7f12b67c, 0xf09fb051, 0x7f0faf25, 0xf086bd39,
+  0x7f0ca2e7, 0xf06dcaba,
+  0x7f0991c4, 0xf054d8d5, 0x7f067bba, 0xf03be78a, 0x7f0360cb, 0xf022f6da,
+  0x7f0040f6, 0xf00a06c8,
+  0x7efd1c3c, 0xeff11753, 0x7ef9f29d, 0xefd8287c, 0x7ef6c418, 0xefbf3a45,
+  0x7ef390ae, 0xefa64cae,
+  0x7ef05860, 0xef8d5fb8, 0x7eed1b2c, 0xef747365, 0x7ee9d914, 0xef5b87b5,
+  0x7ee69217, 0xef429caa,
+  0x7ee34636, 0xef29b243, 0x7edff570, 0xef10c883, 0x7edc9fc6, 0xeef7df6a,
+  0x7ed94538, 0xeedef6f9,
+  0x7ed5e5c6, 0xeec60f31, 0x7ed28171, 0xeead2813, 0x7ecf1837, 0xee9441a0,
+  0x7ecbaa1a, 0xee7b5bd9,
+  0x7ec8371a, 0xee6276bf, 0x7ec4bf36, 0xee499253, 0x7ec14270, 0xee30ae96,
+  0x7ebdc0c6, 0xee17cb88,
+  0x7eba3a39, 0xedfee92b, 0x7eb6aeca, 0xede60780, 0x7eb31e78, 0xedcd2687,
+  0x7eaf8943, 0xedb44642,
+  0x7eabef2c, 0xed9b66b2, 0x7ea85033, 0xed8287d7, 0x7ea4ac58, 0xed69a9b3,
+  0x7ea1039b, 0xed50cc46,
+  0x7e9d55fc, 0xed37ef91, 0x7e99a37c, 0xed1f1396, 0x7e95ec1a, 0xed063856,
+  0x7e922fd6, 0xeced5dd0,
+  0x7e8e6eb2, 0xecd48407, 0x7e8aa8ac, 0xecbbaafb, 0x7e86ddc6, 0xeca2d2ad,
+  0x7e830dff, 0xec89fb1e,
+  0x7e7f3957, 0xec71244f, 0x7e7b5fce, 0xec584e41, 0x7e778166, 0xec3f78f6,
+  0x7e739e1d, 0xec26a46d,
+  0x7e6fb5f4, 0xec0dd0a8, 0x7e6bc8eb, 0xebf4fda8, 0x7e67d703, 0xebdc2b6e,
+  0x7e63e03b, 0xebc359fb,
+  0x7e5fe493, 0xebaa894f, 0x7e5be40c, 0xeb91b96c, 0x7e57dea7, 0xeb78ea52,
+  0x7e53d462, 0xeb601c04,
+  0x7e4fc53e, 0xeb474e81, 0x7e4bb13c, 0xeb2e81ca, 0x7e47985b, 0xeb15b5e1,
+  0x7e437a9c, 0xeafceac6,
+  0x7e3f57ff, 0xeae4207a, 0x7e3b3083, 0xeacb56ff, 0x7e37042a, 0xeab28e56,
+  0x7e32d2f4, 0xea99c67e,
+  0x7e2e9cdf, 0xea80ff7a, 0x7e2a61ed, 0xea683949, 0x7e26221f, 0xea4f73ee,
+  0x7e21dd73, 0xea36af69,
+  0x7e1d93ea, 0xea1debbb, 0x7e194584, 0xea0528e5, 0x7e14f242, 0xe9ec66e8,
+  0x7e109a24, 0xe9d3a5c5,
+  0x7e0c3d29, 0xe9bae57d, 0x7e07db52, 0xe9a22610, 0x7e0374a0, 0xe9896781,
+  0x7dff0911, 0xe970a9ce,
+  0x7dfa98a8, 0xe957ecfb, 0x7df62362, 0xe93f3107, 0x7df1a942, 0xe92675f4,
+  0x7ded2a47, 0xe90dbbc2,
+  0x7de8a670, 0xe8f50273, 0x7de41dc0, 0xe8dc4a07, 0x7ddf9034, 0xe8c39280,
+  0x7ddafdce, 0xe8aadbde,
+  0x7dd6668f, 0xe8922622, 0x7dd1ca75, 0xe879714d, 0x7dcd2981, 0xe860bd61,
+  0x7dc883b4, 0xe8480a5d,
+  0x7dc3d90d, 0xe82f5844, 0x7dbf298d, 0xe816a716, 0x7dba7534, 0xe7fdf6d4,
+  0x7db5bc02, 0xe7e5477f,
+  0x7db0fdf8, 0xe7cc9917, 0x7dac3b15, 0xe7b3eb9f, 0x7da77359, 0xe79b3f16,
+  0x7da2a6c6, 0xe782937e,
+  0x7d9dd55a, 0xe769e8d8, 0x7d98ff17, 0xe7513f25, 0x7d9423fc, 0xe7389665,
+  0x7d8f4409, 0xe71fee99,
+  0x7d8a5f40, 0xe70747c4, 0x7d85759f, 0xe6eea1e4, 0x7d808728, 0xe6d5fcfc,
+  0x7d7b93da, 0xe6bd590d,
+  0x7d769bb5, 0xe6a4b616, 0x7d719eba, 0xe68c141a, 0x7d6c9ce9, 0xe6737319,
+  0x7d679642, 0xe65ad315,
+  0x7d628ac6, 0xe642340d, 0x7d5d7a74, 0xe6299604, 0x7d58654d, 0xe610f8f9,
+  0x7d534b50, 0xe5f85cef,
+  0x7d4e2c7f, 0xe5dfc1e5, 0x7d4908d9, 0xe5c727dd, 0x7d43e05e, 0xe5ae8ed8,
+  0x7d3eb30f, 0xe595f6d7,
+  0x7d3980ec, 0xe57d5fda, 0x7d3449f5, 0xe564c9e3, 0x7d2f0e2b, 0xe54c34f3,
+  0x7d29cd8c, 0xe533a10a,
+  0x7d24881b, 0xe51b0e2a, 0x7d1f3dd6, 0xe5027c53, 0x7d19eebf, 0xe4e9eb87,
+  0x7d149ad5, 0xe4d15bc6,
+  0x7d0f4218, 0xe4b8cd11, 0x7d09e489, 0xe4a03f69, 0x7d048228, 0xe487b2d0,
+  0x7cff1af5, 0xe46f2745,
+  0x7cf9aef0, 0xe4569ccb, 0x7cf43e1a, 0xe43e1362, 0x7ceec873, 0xe4258b0a,
+  0x7ce94dfb, 0xe40d03c6,
+  0x7ce3ceb2, 0xe3f47d96, 0x7cde4a98, 0xe3dbf87a, 0x7cd8c1ae, 0xe3c37474,
+  0x7cd333f3, 0xe3aaf184,
+  0x7ccda169, 0xe3926fad, 0x7cc80a0f, 0xe379eeed, 0x7cc26de5, 0xe3616f48,
+  0x7cbcccec, 0xe348f0bd,
+  0x7cb72724, 0xe330734d, 0x7cb17c8d, 0xe317f6fa, 0x7cabcd28, 0xe2ff7bc3,
+  0x7ca618f3, 0xe2e701ac,
+  0x7ca05ff1, 0xe2ce88b3, 0x7c9aa221, 0xe2b610da, 0x7c94df83, 0xe29d9a23,
+  0x7c8f1817, 0xe285248d,
+  0x7c894bde, 0xe26cb01b, 0x7c837ad8, 0xe2543ccc, 0x7c7da505, 0xe23bcaa2,
+  0x7c77ca65, 0xe223599e,
+  0x7c71eaf9, 0xe20ae9c1, 0x7c6c06c0, 0xe1f27b0b, 0x7c661dbc, 0xe1da0d7e,
+  0x7c602fec, 0xe1c1a11b,
+  0x7c5a3d50, 0xe1a935e2, 0x7c5445e9, 0xe190cbd4, 0x7c4e49b7, 0xe17862f3,
+  0x7c4848ba, 0xe15ffb3f,
+  0x7c4242f2, 0xe14794ba, 0x7c3c3860, 0xe12f2f63, 0x7c362904, 0xe116cb3d,
+  0x7c3014de, 0xe0fe6848,
+  0x7c29fbee, 0xe0e60685, 0x7c23de35, 0xe0cda5f5, 0x7c1dbbb3, 0xe0b54698,
+  0x7c179467, 0xe09ce871,
+  0x7c116853, 0xe0848b7f, 0x7c0b3777, 0xe06c2fc4, 0x7c0501d2, 0xe053d541,
+  0x7bfec765, 0xe03b7bf6,
+  0x7bf88830, 0xe02323e5, 0x7bf24434, 0xe00acd0e, 0x7bebfb70, 0xdff27773,
+  0x7be5ade6, 0xdfda2314,
+  0x7bdf5b94, 0xdfc1cff3, 0x7bd9047c, 0xdfa97e0f, 0x7bd2a89e, 0xdf912d6b,
+  0x7bcc47fa, 0xdf78de07,
+  0x7bc5e290, 0xdf608fe4, 0x7bbf7860, 0xdf484302, 0x7bb9096b, 0xdf2ff764,
+  0x7bb295b0, 0xdf17ad0a,
+  0x7bac1d31, 0xdeff63f4, 0x7ba59fee, 0xdee71c24, 0x7b9f1de6, 0xdeced59b,
+  0x7b989719, 0xdeb69059,
+  0x7b920b89, 0xde9e4c60, 0x7b8b7b36, 0xde8609b1, 0x7b84e61f, 0xde6dc84b,
+  0x7b7e4c45, 0xde558831,
+  0x7b77ada8, 0xde3d4964, 0x7b710a49, 0xde250be3, 0x7b6a6227, 0xde0ccfb1,
+  0x7b63b543, 0xddf494ce,
+  0x7b5d039e, 0xdddc5b3b, 0x7b564d36, 0xddc422f8, 0x7b4f920e, 0xddabec08,
+  0x7b48d225, 0xdd93b66a,
+  0x7b420d7a, 0xdd7b8220, 0x7b3b4410, 0xdd634f2b, 0x7b3475e5, 0xdd4b1d8c,
+  0x7b2da2fa, 0xdd32ed43,
+  0x7b26cb4f, 0xdd1abe51, 0x7b1feee5, 0xdd0290b8, 0x7b190dbc, 0xdcea6478,
+  0x7b1227d3, 0xdcd23993,
+  0x7b0b3d2c, 0xdcba1008, 0x7b044dc7, 0xdca1e7da, 0x7afd59a4, 0xdc89c109,
+  0x7af660c2, 0xdc719b96,
+  0x7aef6323, 0xdc597781, 0x7ae860c7, 0xdc4154cd, 0x7ae159ae, 0xdc293379,
+  0x7ada4dd8, 0xdc111388,
+  0x7ad33d45, 0xdbf8f4f8, 0x7acc27f7, 0xdbe0d7cd, 0x7ac50dec, 0xdbc8bc06,
+  0x7abdef25, 0xdbb0a1a4,
+  0x7ab6cba4, 0xdb9888a8, 0x7aafa367, 0xdb807114, 0x7aa8766f, 0xdb685ae9,
+  0x7aa144bc, 0xdb504626,
+  0x7a9a0e50, 0xdb3832cd, 0x7a92d329, 0xdb2020e0, 0x7a8b9348, 0xdb08105e,
+  0x7a844eae, 0xdaf00149,
+  0x7a7d055b, 0xdad7f3a2, 0x7a75b74f, 0xdabfe76a, 0x7a6e648a, 0xdaa7dca1,
+  0x7a670d0d, 0xda8fd349,
+  0x7a5fb0d8, 0xda77cb63, 0x7a584feb, 0xda5fc4ef, 0x7a50ea47, 0xda47bfee,
+  0x7a497feb, 0xda2fbc61,
+  0x7a4210d8, 0xda17ba4a, 0x7a3a9d0f, 0xd9ffb9a9, 0x7a332490, 0xd9e7ba7f,
+  0x7a2ba75a, 0xd9cfbccd,
+  0x7a24256f, 0xd9b7c094, 0x7a1c9ece, 0xd99fc5d4, 0x7a151378, 0xd987cc90,
+  0x7a0d836d, 0xd96fd4c7,
+  0x7a05eead, 0xd957de7a, 0x79fe5539, 0xd93fe9ab, 0x79f6b711, 0xd927f65b,
+  0x79ef1436, 0xd910048a,
+  0x79e76ca7, 0xd8f81439, 0x79dfc064, 0xd8e0256a, 0x79d80f6f, 0xd8c8381d,
+  0x79d059c8, 0xd8b04c52,
+  0x79c89f6e, 0xd898620c, 0x79c0e062, 0xd880794b, 0x79b91ca4, 0xd868920f,
+  0x79b15435, 0xd850ac5a,
+  0x79a98715, 0xd838c82d, 0x79a1b545, 0xd820e589, 0x7999dec4, 0xd809046e,
+  0x79920392, 0xd7f124dd,
+  0x798a23b1, 0xd7d946d8, 0x79823f20, 0xd7c16a5f, 0x797a55e0, 0xd7a98f73,
+  0x797267f2, 0xd791b616,
+  0x796a7554, 0xd779de47, 0x79627e08, 0xd7620808, 0x795a820e, 0xd74a335b,
+  0x79528167, 0xd732603f,
+  0x794a7c12, 0xd71a8eb5, 0x79427210, 0xd702bec0, 0x793a6361, 0xd6eaf05f,
+  0x79325006, 0xd6d32393,
+  0x792a37fe, 0xd6bb585e, 0x79221b4b, 0xd6a38ec0, 0x7919f9ec, 0xd68bc6ba,
+  0x7911d3e2, 0xd674004e,
+  0x7909a92d, 0xd65c3b7b, 0x790179cd, 0xd6447844, 0x78f945c3, 0xd62cb6a8,
+  0x78f10d0f, 0xd614f6a9,
+  0x78e8cfb2, 0xd5fd3848, 0x78e08dab, 0xd5e57b85, 0x78d846fb, 0xd5cdc062,
+  0x78cffba3, 0xd5b606e0,
+  0x78c7aba2, 0xd59e4eff, 0x78bf56f9, 0xd58698c0, 0x78b6fda8, 0xd56ee424,
+  0x78ae9fb0, 0xd557312d,
+  0x78a63d11, 0xd53f7fda, 0x789dd5cb, 0xd527d02e, 0x789569df, 0xd5102228,
+  0x788cf94c, 0xd4f875ca,
+  0x78848414, 0xd4e0cb15, 0x787c0a36, 0xd4c92209, 0x78738bb3, 0xd4b17aa8,
+  0x786b088c, 0xd499d4f2,
+  0x786280bf, 0xd48230e9, 0x7859f44f, 0xd46a8e8d, 0x7851633b, 0xd452eddf,
+  0x7848cd83, 0xd43b4ee0,
+  0x78403329, 0xd423b191, 0x7837942b, 0xd40c15f3, 0x782ef08b, 0xd3f47c06,
+  0x78264849, 0xd3dce3cd,
+  0x781d9b65, 0xd3c54d47, 0x7814e9df, 0xd3adb876, 0x780c33b8, 0xd396255a,
+  0x780378f1, 0xd37e93f4,
+  0x77fab989, 0xd3670446, 0x77f1f581, 0xd34f764f, 0x77e92cd9, 0xd337ea12,
+  0x77e05f91, 0xd3205f8f,
+  0x77d78daa, 0xd308d6c7, 0x77ceb725, 0xd2f14fba, 0x77c5dc01, 0xd2d9ca6a,
+  0x77bcfc3f, 0xd2c246d8,
+  0x77b417df, 0xd2aac504, 0x77ab2ee2, 0xd29344f0, 0x77a24148, 0xd27bc69c,
+  0x77994f11, 0xd2644a0a,
+  0x7790583e, 0xd24ccf39, 0x77875cce, 0xd235562b, 0x777e5cc3, 0xd21ddee2,
+  0x7775581d, 0xd206695d,
+  0x776c4edb, 0xd1eef59e, 0x776340ff, 0xd1d783a6, 0x775a2e89, 0xd1c01375,
+  0x77511778, 0xd1a8a50d,
+  0x7747fbce, 0xd191386e, 0x773edb8b, 0xd179cd99, 0x7735b6af, 0xd1626490,
+  0x772c8d3a, 0xd14afd52,
+  0x77235f2d, 0xd13397e2, 0x771a2c88, 0xd11c343f, 0x7710f54c, 0xd104d26b,
+  0x7707b979, 0xd0ed7267,
+  0x76fe790e, 0xd0d61434, 0x76f5340e, 0xd0beb7d2, 0x76ebea77, 0xd0a75d42,
+  0x76e29c4b, 0xd0900486,
+  0x76d94989, 0xd078ad9e, 0x76cff232, 0xd061588b, 0x76c69647, 0xd04a054e,
+  0x76bd35c7, 0xd032b3e7,
+  0x76b3d0b4, 0xd01b6459, 0x76aa670d, 0xd00416a3, 0x76a0f8d2, 0xcfeccac7,
+  0x76978605, 0xcfd580c6,
+  0x768e0ea6, 0xcfbe389f, 0x768492b4, 0xcfa6f255, 0x767b1231, 0xcf8fade9,
+  0x76718d1c, 0xcf786b5a,
+  0x76680376, 0xcf612aaa, 0x765e7540, 0xcf49ebda, 0x7654e279, 0xcf32aeeb,
+  0x764b4b23, 0xcf1b73de,
+  0x7641af3d, 0xcf043ab3, 0x76380ec8, 0xceed036b, 0x762e69c4, 0xced5ce08,
+  0x7624c031, 0xcebe9a8a,
+  0x761b1211, 0xcea768f2, 0x76115f63, 0xce903942, 0x7607a828, 0xce790b79,
+  0x75fdec60, 0xce61df99,
+  0x75f42c0b, 0xce4ab5a2, 0x75ea672a, 0xce338d97, 0x75e09dbd, 0xce1c6777,
+  0x75d6cfc5, 0xce054343,
+  0x75ccfd42, 0xcdee20fc, 0x75c32634, 0xcdd700a4, 0x75b94a9c, 0xcdbfe23a,
+  0x75af6a7b, 0xcda8c5c1,
+  0x75a585cf, 0xcd91ab39, 0x759b9c9b, 0xcd7a92a2, 0x7591aedd, 0xcd637bfe,
+  0x7587bc98, 0xcd4c674d,
+  0x757dc5ca, 0xcd355491, 0x7573ca75, 0xcd1e43ca, 0x7569ca99, 0xcd0734f9,
+  0x755fc635, 0xccf0281f,
+  0x7555bd4c, 0xccd91d3d, 0x754bafdc, 0xccc21455, 0x75419de7, 0xccab0d65,
+  0x7537876c, 0xcc940871,
+  0x752d6c6c, 0xcc7d0578, 0x75234ce8, 0xcc66047b, 0x751928e0, 0xcc4f057c,
+  0x750f0054, 0xcc38087b,
+  0x7504d345, 0xcc210d79, 0x74faa1b3, 0xcc0a1477, 0x74f06b9e, 0xcbf31d75,
+  0x74e63108, 0xcbdc2876,
+  0x74dbf1ef, 0xcbc53579, 0x74d1ae55, 0xcbae447f, 0x74c7663a, 0xcb97558a,
+  0x74bd199f, 0xcb80689a,
+  0x74b2c884, 0xcb697db0, 0x74a872e8, 0xcb5294ce, 0x749e18cd, 0xcb3badf3,
+  0x7493ba34, 0xcb24c921,
+  0x7489571c, 0xcb0de658, 0x747eef85, 0xcaf7059a, 0x74748371, 0xcae026e8,
+  0x746a12df, 0xcac94a42,
+  0x745f9dd1, 0xcab26fa9, 0x74552446, 0xca9b971e, 0x744aa63f, 0xca84c0a3,
+  0x744023bc, 0xca6dec37,
+  0x74359cbd, 0xca5719db, 0x742b1144, 0xca404992, 0x74208150, 0xca297b5a,
+  0x7415ece2, 0xca12af37,
+  0x740b53fb, 0xc9fbe527, 0x7400b69a, 0xc9e51d2d, 0x73f614c0, 0xc9ce5748,
+  0x73eb6e6e, 0xc9b7937a,
+  0x73e0c3a3, 0xc9a0d1c5, 0x73d61461, 0xc98a1227, 0x73cb60a8, 0xc97354a4,
+  0x73c0a878, 0xc95c993a,
+  0x73b5ebd1, 0xc945dfec, 0x73ab2ab4, 0xc92f28ba, 0x73a06522, 0xc91873a5,
+  0x73959b1b, 0xc901c0ae,
+  0x738acc9e, 0xc8eb0fd6, 0x737ff9ae, 0xc8d4611d, 0x73752249, 0xc8bdb485,
+  0x736a4671, 0xc8a70a0e,
+  0x735f6626, 0xc89061ba, 0x73548168, 0xc879bb89, 0x73499838, 0xc863177b,
+  0x733eaa96, 0xc84c7593,
+  0x7333b883, 0xc835d5d0, 0x7328c1ff, 0xc81f3834, 0x731dc70a, 0xc8089cbf,
+  0x7312c7a5, 0xc7f20373,
+  0x7307c3d0, 0xc7db6c50, 0x72fcbb8c, 0xc7c4d757, 0x72f1aed9, 0xc7ae4489,
+  0x72e69db7, 0xc797b3e7,
+  0x72db8828, 0xc7812572, 0x72d06e2b, 0xc76a992a, 0x72c54fc1, 0xc7540f11,
+  0x72ba2cea, 0xc73d8727,
+  0x72af05a7, 0xc727016d, 0x72a3d9f7, 0xc7107de4, 0x7298a9dd, 0xc6f9fc8d,
+  0x728d7557, 0xc6e37d69,
+  0x72823c67, 0xc6cd0079, 0x7276ff0d, 0xc6b685bd, 0x726bbd48, 0xc6a00d37,
+  0x7260771b, 0xc68996e7,
+  0x72552c85, 0xc67322ce, 0x7249dd86, 0xc65cb0ed, 0x723e8a20, 0xc6464144,
+  0x72333251, 0xc62fd3d6,
+  0x7227d61c, 0xc61968a2, 0x721c7580, 0xc602ffaa, 0x7211107e, 0xc5ec98ee,
+  0x7205a716, 0xc5d6346f,
+  0x71fa3949, 0xc5bfd22e, 0x71eec716, 0xc5a9722c, 0x71e35080, 0xc593146a,
+  0x71d7d585, 0xc57cb8e9,
+  0x71cc5626, 0xc5665fa9, 0x71c0d265, 0xc55008ab, 0x71b54a41, 0xc539b3f1,
+  0x71a9bdba, 0xc523617a,
+  0x719e2cd2, 0xc50d1149, 0x71929789, 0xc4f6c35d, 0x7186fdde, 0xc4e077b8,
+  0x717b5fd3, 0xc4ca2e5b,
+  0x716fbd68, 0xc4b3e746, 0x7164169d, 0xc49da27a, 0x71586b74, 0xc4875ff9,
+  0x714cbbeb, 0xc4711fc2,
+  0x71410805, 0xc45ae1d7, 0x71354fc0, 0xc444a639, 0x7129931f, 0xc42e6ce8,
+  0x711dd220, 0xc41835e6,
+  0x71120cc5, 0xc4020133, 0x7106430e, 0xc3ebced0, 0x70fa74fc, 0xc3d59ebe,
+  0x70eea28e, 0xc3bf70fd,
+  0x70e2cbc6, 0xc3a94590, 0x70d6f0a4, 0xc3931c76, 0x70cb1128, 0xc37cf5b0,
+  0x70bf2d53, 0xc366d140,
+  0x70b34525, 0xc350af26, 0x70a7589f, 0xc33a8f62, 0x709b67c0, 0xc32471f7,
+  0x708f728b, 0xc30e56e4,
+  0x708378ff, 0xc2f83e2a, 0x70777b1c, 0xc2e227cb, 0x706b78e3, 0xc2cc13c7,
+  0x705f7255, 0xc2b6021f,
+  0x70536771, 0xc29ff2d4, 0x70475839, 0xc289e5e7, 0x703b44ad, 0xc273db58,
+  0x702f2ccd, 0xc25dd329,
+  0x7023109a, 0xc247cd5a, 0x7016f014, 0xc231c9ec, 0x700acb3c, 0xc21bc8e1,
+  0x6ffea212, 0xc205ca38,
+  0x6ff27497, 0xc1efcdf3, 0x6fe642ca, 0xc1d9d412, 0x6fda0cae, 0xc1c3dc97,
+  0x6fcdd241, 0xc1ade781,
+  0x6fc19385, 0xc197f4d4, 0x6fb5507a, 0xc182048d, 0x6fa90921, 0xc16c16b0,
+  0x6f9cbd79, 0xc1562b3d,
+  0x6f906d84, 0xc1404233, 0x6f841942, 0xc12a5b95, 0x6f77c0b3, 0xc1147764,
+  0x6f6b63d8, 0xc0fe959f,
+  0x6f5f02b2, 0xc0e8b648, 0x6f529d40, 0xc0d2d960, 0x6f463383, 0xc0bcfee7,
+  0x6f39c57d, 0xc0a726df,
+  0x6f2d532c, 0xc0915148, 0x6f20dc92, 0xc07b7e23, 0x6f1461b0, 0xc065ad70,
+  0x6f07e285, 0xc04fdf32,
+  0x6efb5f12, 0xc03a1368, 0x6eeed758, 0xc0244a14, 0x6ee24b57, 0xc00e8336,
+  0x6ed5bb10, 0xbff8bece,
+  0x6ec92683, 0xbfe2fcdf, 0x6ebc8db0, 0xbfcd3d69, 0x6eaff099, 0xbfb7806c,
+  0x6ea34f3d, 0xbfa1c5ea,
+  0x6e96a99d, 0xbf8c0de3, 0x6e89ffb9, 0xbf765858, 0x6e7d5193, 0xbf60a54a,
+  0x6e709f2a, 0xbf4af4ba,
+  0x6e63e87f, 0xbf3546a8, 0x6e572d93, 0xbf1f9b16, 0x6e4a6e66, 0xbf09f205,
+  0x6e3daaf8, 0xbef44b74,
+  0x6e30e34a, 0xbedea765, 0x6e24175c, 0xbec905d9, 0x6e174730, 0xbeb366d1,
+  0x6e0a72c5, 0xbe9dca4e,
+  0x6dfd9a1c, 0xbe88304f, 0x6df0bd35, 0xbe7298d7, 0x6de3dc11, 0xbe5d03e6,
+  0x6dd6f6b1, 0xbe47717c,
+  0x6dca0d14, 0xbe31e19b, 0x6dbd1f3c, 0xbe1c5444, 0x6db02d29, 0xbe06c977,
+  0x6da336dc, 0xbdf14135,
+  0x6d963c54, 0xbddbbb7f, 0x6d893d93, 0xbdc63856, 0x6d7c3a98, 0xbdb0b7bb,
+  0x6d6f3365, 0xbd9b39ad,
+  0x6d6227fa, 0xbd85be30, 0x6d551858, 0xbd704542, 0x6d48047e, 0xbd5acee5,
+  0x6d3aec6e, 0xbd455b1a,
+  0x6d2dd027, 0xbd2fe9e2, 0x6d20afac, 0xbd1a7b3d, 0x6d138afb, 0xbd050f2c,
+  0x6d066215, 0xbcefa5b0,
+  0x6cf934fc, 0xbcda3ecb, 0x6cec03af, 0xbcc4da7b, 0x6cdece2f, 0xbcaf78c4,
+  0x6cd1947c, 0xbc9a19a5,
+  0x6cc45698, 0xbc84bd1f, 0x6cb71482, 0xbc6f6333, 0x6ca9ce3b, 0xbc5a0be2,
+  0x6c9c83c3, 0xbc44b72c,
+  0x6c8f351c, 0xbc2f6513, 0x6c81e245, 0xbc1a1598, 0x6c748b3f, 0xbc04c8ba,
+  0x6c67300b, 0xbbef7e7c,
+  0x6c59d0a9, 0xbbda36dd, 0x6c4c6d1a, 0xbbc4f1df, 0x6c3f055d, 0xbbafaf82,
+  0x6c319975, 0xbb9a6fc7,
+  0x6c242960, 0xbb8532b0, 0x6c16b521, 0xbb6ff83c, 0x6c093cb6, 0xbb5ac06d,
+  0x6bfbc021, 0xbb458b43,
+  0x6bee3f62, 0xbb3058c0, 0x6be0ba7b, 0xbb1b28e4, 0x6bd3316a, 0xbb05fbb0,
+  0x6bc5a431, 0xbaf0d125,
+  0x6bb812d1, 0xbadba943, 0x6baa7d49, 0xbac6840c, 0x6b9ce39b, 0xbab16180,
+  0x6b8f45c7, 0xba9c41a0,
+  0x6b81a3cd, 0xba87246d, 0x6b73fdae, 0xba7209e7, 0x6b66536b, 0xba5cf210,
+  0x6b58a503, 0xba47dce8,
+  0x6b4af279, 0xba32ca71, 0x6b3d3bcb, 0xba1dbaaa, 0x6b2f80fb, 0xba08ad95,
+  0x6b21c208, 0xb9f3a332,
+  0x6b13fef5, 0xb9de9b83, 0x6b0637c1, 0xb9c99688, 0x6af86c6c, 0xb9b49442,
+  0x6aea9cf8, 0xb99f94b2,
+  0x6adcc964, 0xb98a97d8, 0x6acef1b2, 0xb9759db6, 0x6ac115e2, 0xb960a64c,
+  0x6ab335f4, 0xb94bb19b,
+  0x6aa551e9, 0xb936bfa4, 0x6a9769c1, 0xb921d067, 0x6a897d7d, 0xb90ce3e6,
+  0x6a7b8d1e, 0xb8f7fa21,
+  0x6a6d98a4, 0xb8e31319, 0x6a5fa010, 0xb8ce2ecf, 0x6a51a361, 0xb8b94d44,
+  0x6a43a29a, 0xb8a46e78,
+  0x6a359db9, 0xb88f926d, 0x6a2794c1, 0xb87ab922, 0x6a1987b0, 0xb865e299,
+  0x6a0b7689, 0xb8510ed4,
+  0x69fd614a, 0xb83c3dd1, 0x69ef47f6, 0xb8276f93, 0x69e12a8c, 0xb812a41a,
+  0x69d3090e, 0xb7fddb67,
+  0x69c4e37a, 0xb7e9157a, 0x69b6b9d3, 0xb7d45255, 0x69a88c19, 0xb7bf91f8,
+  0x699a5a4c, 0xb7aad465,
+  0x698c246c, 0xb796199b, 0x697dea7b, 0xb781619c, 0x696fac78, 0xb76cac69,
+  0x69616a65, 0xb757fa01,
+  0x69532442, 0xb7434a67, 0x6944da10, 0xb72e9d9b, 0x69368bce, 0xb719f39e,
+  0x6928397e, 0xb7054c6f,
+  0x6919e320, 0xb6f0a812, 0x690b88b5, 0xb6dc0685, 0x68fd2a3d, 0xb6c767ca,
+  0x68eec7b9, 0xb6b2cbe2,
+  0x68e06129, 0xb69e32cd, 0x68d1f68f, 0xb6899c8d, 0x68c387e9, 0xb6750921,
+  0x68b5153a, 0xb660788c,
+  0x68a69e81, 0xb64beacd, 0x689823bf, 0xb6375fe5, 0x6889a4f6, 0xb622d7d6,
+  0x687b2224, 0xb60e529f,
+  0x686c9b4b, 0xb5f9d043, 0x685e106c, 0xb5e550c1, 0x684f8186, 0xb5d0d41a,
+  0x6840ee9b, 0xb5bc5a50,
+  0x683257ab, 0xb5a7e362, 0x6823bcb7, 0xb5936f53, 0x68151dbe, 0xb57efe22,
+  0x68067ac3, 0xb56a8fd0,
+  0x67f7d3c5, 0xb556245e, 0x67e928c5, 0xb541bbcd, 0x67da79c3, 0xb52d561e,
+  0x67cbc6c0, 0xb518f351,
+  0x67bd0fbd, 0xb5049368, 0x67ae54ba, 0xb4f03663, 0x679f95b7, 0xb4dbdc42,
+  0x6790d2b6, 0xb4c78507,
+  0x67820bb7, 0xb4b330b3, 0x677340ba, 0xb49edf45, 0x676471c0, 0xb48a90c0,
+  0x67559eca, 0xb4764523,
+  0x6746c7d8, 0xb461fc70, 0x6737ecea, 0xb44db6a8, 0x67290e02, 0xb43973ca,
+  0x671a2b20, 0xb42533d8,
+  0x670b4444, 0xb410f6d3, 0x66fc596f, 0xb3fcbcbb, 0x66ed6aa1, 0xb3e88592,
+  0x66de77dc, 0xb3d45157,
+  0x66cf8120, 0xb3c0200c, 0x66c0866d, 0xb3abf1b2, 0x66b187c3, 0xb397c649,
+  0x66a28524, 0xb3839dd3,
+  0x66937e91, 0xb36f784f, 0x66847408, 0xb35b55bf, 0x6675658c, 0xb3473623,
+  0x6666531d, 0xb333197c,
+  0x66573cbb, 0xb31effcc, 0x66482267, 0xb30ae912, 0x66390422, 0xb2f6d550,
+  0x6629e1ec, 0xb2e2c486,
+  0x661abbc5, 0xb2ceb6b5, 0x660b91af, 0xb2baabde, 0x65fc63a9, 0xb2a6a402,
+  0x65ed31b5, 0xb2929f21,
+  0x65ddfbd3, 0xb27e9d3c, 0x65cec204, 0xb26a9e54, 0x65bf8447, 0xb256a26a,
+  0x65b0429f, 0xb242a97e,
+  0x65a0fd0b, 0xb22eb392, 0x6591b38c, 0xb21ac0a6, 0x65826622, 0xb206d0ba,
+  0x657314cf, 0xb1f2e3d0,
+  0x6563bf92, 0xb1def9e9, 0x6554666d, 0xb1cb1304, 0x6545095f, 0xb1b72f23,
+  0x6535a86b, 0xb1a34e47,
+  0x6526438f, 0xb18f7071, 0x6516dacd, 0xb17b95a0, 0x65076e25, 0xb167bdd7,
+  0x64f7fd98, 0xb153e915,
+  0x64e88926, 0xb140175b, 0x64d910d1, 0xb12c48ab, 0x64c99498, 0xb1187d05,
+  0x64ba147d, 0xb104b46a,
+  0x64aa907f, 0xb0f0eeda, 0x649b08a0, 0xb0dd2c56, 0x648b7ce0, 0xb0c96ce0,
+  0x647bed3f, 0xb0b5b077,
+  0x646c59bf, 0xb0a1f71d, 0x645cc260, 0xb08e40d2, 0x644d2722, 0xb07a8d97,
+  0x643d8806, 0xb066dd6d,
+  0x642de50d, 0xb0533055, 0x641e3e38, 0xb03f864f, 0x640e9386, 0xb02bdf5c,
+  0x63fee4f8, 0xb0183b7d,
+  0x63ef3290, 0xb0049ab3, 0x63df7c4d, 0xaff0fcfe, 0x63cfc231, 0xafdd625f,
+  0x63c0043b, 0xafc9cad7,
+  0x63b0426d, 0xafb63667, 0x63a07cc7, 0xafa2a50f, 0x6390b34a, 0xaf8f16d1,
+  0x6380e5f6, 0xaf7b8bac,
+  0x637114cc, 0xaf6803a2, 0x63613fcd, 0xaf547eb3, 0x635166f9, 0xaf40fce1,
+  0x63418a50, 0xaf2d7e2b,
+  0x6331a9d4, 0xaf1a0293, 0x6321c585, 0xaf068a1a, 0x6311dd64, 0xaef314c0,
+  0x6301f171, 0xaedfa285,
+  0x62f201ac, 0xaecc336c, 0x62e20e17, 0xaeb8c774, 0x62d216b3, 0xaea55e9e,
+  0x62c21b7e, 0xae91f8eb,
+  0x62b21c7b, 0xae7e965b, 0x62a219aa, 0xae6b36f0, 0x6292130c, 0xae57daab,
+  0x628208a1, 0xae44818b,
+  0x6271fa69, 0xae312b92, 0x6261e866, 0xae1dd8c0, 0x6251d298, 0xae0a8916,
+  0x6241b8ff, 0xadf73c96,
+  0x62319b9d, 0xade3f33e, 0x62217a72, 0xadd0ad12, 0x6211557e, 0xadbd6a10,
+  0x62012cc2, 0xadaa2a3b,
+  0x61f1003f, 0xad96ed92, 0x61e0cff5, 0xad83b416, 0x61d09be5, 0xad707dc8,
+  0x61c06410, 0xad5d4aaa,
+  0x61b02876, 0xad4a1aba, 0x619fe918, 0xad36edfc, 0x618fa5f7, 0xad23c46e,
+  0x617f5f12, 0xad109e12,
+  0x616f146c, 0xacfd7ae8, 0x615ec603, 0xacea5af2, 0x614e73da, 0xacd73e30,
+  0x613e1df0, 0xacc424a3,
+  0x612dc447, 0xacb10e4b, 0x611d66de, 0xac9dfb29, 0x610d05b7, 0xac8aeb3e,
+  0x60fca0d2, 0xac77de8b,
+  0x60ec3830, 0xac64d510, 0x60dbcbd1, 0xac51cecf, 0x60cb5bb7, 0xac3ecbc7,
+  0x60bae7e1, 0xac2bcbfa,
+  0x60aa7050, 0xac18cf69, 0x6099f505, 0xac05d613, 0x60897601, 0xabf2dffb,
+  0x6078f344, 0xabdfed1f,
+  0x60686ccf, 0xabccfd83, 0x6057e2a2, 0xabba1125, 0x604754bf, 0xaba72807,
+  0x6036c325, 0xab944229,
+  0x60262dd6, 0xab815f8d, 0x601594d1, 0xab6e8032, 0x6004f819, 0xab5ba41a,
+  0x5ff457ad, 0xab48cb46,
+  0x5fe3b38d, 0xab35f5b5, 0x5fd30bbc, 0xab23236a, 0x5fc26038, 0xab105464,
+  0x5fb1b104, 0xaafd88a4,
+  0x5fa0fe1f, 0xaaeac02c, 0x5f90478a, 0xaad7fafb, 0x5f7f8d46, 0xaac53912,
+  0x5f6ecf53, 0xaab27a73,
+  0x5f5e0db3, 0xaa9fbf1e, 0x5f4d4865, 0xaa8d0713, 0x5f3c7f6b, 0xaa7a5253,
+  0x5f2bb2c5, 0xaa67a0e0,
+  0x5f1ae274, 0xaa54f2ba, 0x5f0a0e77, 0xaa4247e1, 0x5ef936d1, 0xaa2fa056,
+  0x5ee85b82, 0xaa1cfc1a,
+  0x5ed77c8a, 0xaa0a5b2e, 0x5ec699e9, 0xa9f7bd92, 0x5eb5b3a2, 0xa9e52347,
+  0x5ea4c9b3, 0xa9d28c4e,
+  0x5e93dc1f, 0xa9bff8a8, 0x5e82eae5, 0xa9ad6855, 0x5e71f606, 0xa99adb56,
+  0x5e60fd84, 0xa98851ac,
+  0x5e50015d, 0xa975cb57, 0x5e3f0194, 0xa9634858, 0x5e2dfe29, 0xa950c8b0,
+  0x5e1cf71c, 0xa93e4c5f,
+  0x5e0bec6e, 0xa92bd367, 0x5dfade20, 0xa9195dc7, 0x5de9cc33, 0xa906eb82,
+  0x5dd8b6a7, 0xa8f47c97,
+  0x5dc79d7c, 0xa8e21106, 0x5db680b4, 0xa8cfa8d2, 0x5da5604f, 0xa8bd43fa,
+  0x5d943c4e, 0xa8aae280,
+  0x5d8314b1, 0xa8988463, 0x5d71e979, 0xa88629a5, 0x5d60baa7, 0xa873d246,
+  0x5d4f883b, 0xa8617e48,
+  0x5d3e5237, 0xa84f2daa, 0x5d2d189a, 0xa83ce06e, 0x5d1bdb65, 0xa82a9693,
+  0x5d0a9a9a, 0xa818501c,
+  0x5cf95638, 0xa8060d08, 0x5ce80e41, 0xa7f3cd59, 0x5cd6c2b5, 0xa7e1910f,
+  0x5cc57394, 0xa7cf582a,
+  0x5cb420e0, 0xa7bd22ac, 0x5ca2ca99, 0xa7aaf094, 0x5c9170bf, 0xa798c1e5,
+  0x5c801354, 0xa786969e,
+  0x5c6eb258, 0xa7746ec0, 0x5c5d4dcc, 0xa7624a4d, 0x5c4be5b0, 0xa7502943,
+  0x5c3a7a05, 0xa73e0ba5,
+  0x5c290acc, 0xa72bf174, 0x5c179806, 0xa719daae, 0x5c0621b2, 0xa707c757,
+  0x5bf4a7d2, 0xa6f5b76d,
+  0x5be32a67, 0xa6e3aaf2, 0x5bd1a971, 0xa6d1a1e7, 0x5bc024f0, 0xa6bf9c4b,
+  0x5bae9ce7, 0xa6ad9a21,
+  0x5b9d1154, 0xa69b9b68, 0x5b8b8239, 0xa689a022, 0x5b79ef96, 0xa677a84e,
+  0x5b68596d, 0xa665b3ee,
+  0x5b56bfbd, 0xa653c303, 0x5b452288, 0xa641d58c, 0x5b3381ce, 0xa62feb8b,
+  0x5b21dd90, 0xa61e0501,
+  0x5b1035cf, 0xa60c21ee, 0x5afe8a8b, 0xa5fa4252, 0x5aecdbc5, 0xa5e8662f,
+  0x5adb297d, 0xa5d68d85,
+  0x5ac973b5, 0xa5c4b855, 0x5ab7ba6c, 0xa5b2e6a0, 0x5aa5fda5, 0xa5a11866,
+  0x5a943d5e, 0xa58f4da8,
+  0x5a82799a, 0xa57d8666, 0x5a70b258, 0xa56bc2a2, 0x5a5ee79a, 0xa55a025b,
+  0x5a4d1960, 0xa5484594,
+  0x5a3b47ab, 0xa5368c4b, 0x5a29727b, 0xa524d683, 0x5a1799d1, 0xa513243b,
+  0x5a05bdae, 0xa5017575,
+  0x59f3de12, 0xa4efca31, 0x59e1faff, 0xa4de2270, 0x59d01475, 0xa4cc7e32,
+  0x59be2a74, 0xa4badd78,
+  0x59ac3cfd, 0xa4a94043, 0x599a4c12, 0xa497a693, 0x598857b2, 0xa486106a,
+  0x59765fde, 0xa4747dc7,
+  0x59646498, 0xa462eeac, 0x595265df, 0xa4516319, 0x594063b5, 0xa43fdb10,
+  0x592e5e19, 0xa42e568f,
+  0x591c550e, 0xa41cd599, 0x590a4893, 0xa40b582e, 0x58f838a9, 0xa3f9de4e,
+  0x58e62552, 0xa3e867fa,
+  0x58d40e8c, 0xa3d6f534, 0x58c1f45b, 0xa3c585fb, 0x58afd6bd, 0xa3b41a50,
+  0x589db5b3, 0xa3a2b234,
+  0x588b9140, 0xa3914da8, 0x58796962, 0xa37fecac, 0x58673e1b, 0xa36e8f41,
+  0x58550f6c, 0xa35d3567,
+  0x5842dd54, 0xa34bdf20, 0x5830a7d6, 0xa33a8c6c, 0x581e6ef1, 0xa3293d4b,
+  0x580c32a7, 0xa317f1bf,
+  0x57f9f2f8, 0xa306a9c8, 0x57e7afe4, 0xa2f56566, 0x57d5696d, 0xa2e4249b,
+  0x57c31f92, 0xa2d2e766,
+  0x57b0d256, 0xa2c1adc9, 0x579e81b8, 0xa2b077c5, 0x578c2dba, 0xa29f4559,
+  0x5779d65b, 0xa28e1687,
+  0x57677b9d, 0xa27ceb4f, 0x57551d80, 0xa26bc3b2, 0x5742bc06, 0xa25a9fb1,
+  0x5730572e, 0xa2497f4c,
+  0x571deefa, 0xa2386284, 0x570b8369, 0xa2274959, 0x56f9147e, 0xa21633cd,
+  0x56e6a239, 0xa20521e0,
+  0x56d42c99, 0xa1f41392, 0x56c1b3a1, 0xa1e308e4, 0x56af3750, 0xa1d201d7,
+  0x569cb7a8, 0xa1c0fe6c,
+  0x568a34a9, 0xa1affea3, 0x5677ae54, 0xa19f027c, 0x566524aa, 0xa18e09fa,
+  0x565297ab, 0xa17d151b,
+  0x56400758, 0xa16c23e1, 0x562d73b2, 0xa15b364d, 0x561adcb9, 0xa14a4c5e,
+  0x5608426e, 0xa1396617,
+  0x55f5a4d2, 0xa1288376, 0x55e303e6, 0xa117a47e, 0x55d05faa, 0xa106c92f,
+  0x55bdb81f, 0xa0f5f189,
+  0x55ab0d46, 0xa0e51d8c, 0x55985f20, 0xa0d44d3b, 0x5585adad, 0xa0c38095,
+  0x5572f8ed, 0xa0b2b79b,
+  0x556040e2, 0xa0a1f24d, 0x554d858d, 0xa09130ad, 0x553ac6ee, 0xa08072ba,
+  0x55280505, 0xa06fb876,
+  0x55153fd4, 0xa05f01e1, 0x5502775c, 0xa04e4efc, 0x54efab9c, 0xa03d9fc8,
+  0x54dcdc96, 0xa02cf444,
+  0x54ca0a4b, 0xa01c4c73, 0x54b734ba, 0xa00ba853, 0x54a45be6, 0x9ffb07e7,
+  0x54917fce, 0x9fea6b2f,
+  0x547ea073, 0x9fd9d22a, 0x546bbdd7, 0x9fc93cdb, 0x5458d7f9, 0x9fb8ab41,
+  0x5445eedb, 0x9fa81d5e,
+  0x5433027d, 0x9f979331, 0x542012e1, 0x9f870cbc, 0x540d2005, 0x9f7689ff,
+  0x53fa29ed, 0x9f660afb,
+  0x53e73097, 0x9f558fb0, 0x53d43406, 0x9f45181f, 0x53c13439, 0x9f34a449,
+  0x53ae3131, 0x9f24342f,
+  0x539b2af0, 0x9f13c7d0, 0x53882175, 0x9f035f2e, 0x537514c2, 0x9ef2fa49,
+  0x536204d7, 0x9ee29922,
+  0x534ef1b5, 0x9ed23bb9, 0x533bdb5d, 0x9ec1e210, 0x5328c1d0, 0x9eb18c26,
+  0x5315a50e, 0x9ea139fd,
+  0x53028518, 0x9e90eb94, 0x52ef61ee, 0x9e80a0ee, 0x52dc3b92, 0x9e705a09,
+  0x52c91204, 0x9e6016e8,
+  0x52b5e546, 0x9e4fd78a, 0x52a2b556, 0x9e3f9bf0, 0x528f8238, 0x9e2f641b,
+  0x527c4bea, 0x9e1f300b,
+  0x5269126e, 0x9e0effc1, 0x5255d5c5, 0x9dfed33e, 0x524295f0, 0x9deeaa82,
+  0x522f52ee, 0x9dde858e,
+  0x521c0cc2, 0x9dce6463, 0x5208c36a, 0x9dbe4701, 0x51f576ea, 0x9dae2d68,
+  0x51e22740, 0x9d9e179a,
+  0x51ced46e, 0x9d8e0597, 0x51bb7e75, 0x9d7df75f, 0x51a82555, 0x9d6decf4,
+  0x5194c910, 0x9d5de656,
+  0x518169a5, 0x9d4de385, 0x516e0715, 0x9d3de482, 0x515aa162, 0x9d2de94d,
+  0x5147388c, 0x9d1df1e9,
+  0x5133cc94, 0x9d0dfe54, 0x51205d7b, 0x9cfe0e8f, 0x510ceb40, 0x9cee229c,
+  0x50f975e6, 0x9cde3a7b,
+  0x50e5fd6d, 0x9cce562c, 0x50d281d5, 0x9cbe75b0, 0x50bf031f, 0x9cae9907,
+  0x50ab814d, 0x9c9ec033,
+  0x5097fc5e, 0x9c8eeb34, 0x50847454, 0x9c7f1a0a, 0x5070e92f, 0x9c6f4cb6,
+  0x505d5af1, 0x9c5f8339,
+  0x5049c999, 0x9c4fbd93, 0x50363529, 0x9c3ffbc5, 0x50229da1, 0x9c303dcf,
+  0x500f0302, 0x9c2083b3,
+  0x4ffb654d, 0x9c10cd70, 0x4fe7c483, 0x9c011b08, 0x4fd420a4, 0x9bf16c7a,
+  0x4fc079b1, 0x9be1c1c8,
+  0x4faccfab, 0x9bd21af3, 0x4f992293, 0x9bc277fa, 0x4f857269, 0x9bb2d8de,
+  0x4f71bf2e, 0x9ba33da0,
+  0x4f5e08e3, 0x9b93a641, 0x4f4a4f89, 0x9b8412c1, 0x4f369320, 0x9b748320,
+  0x4f22d3aa, 0x9b64f760,
+  0x4f0f1126, 0x9b556f81, 0x4efb4b96, 0x9b45eb83, 0x4ee782fb, 0x9b366b68,
+  0x4ed3b755, 0x9b26ef2f,
+  0x4ebfe8a5, 0x9b1776da, 0x4eac16eb, 0x9b080268, 0x4e984229, 0x9af891db,
+  0x4e846a60, 0x9ae92533,
+  0x4e708f8f, 0x9ad9bc71, 0x4e5cb1b9, 0x9aca5795, 0x4e48d0dd, 0x9abaf6a1,
+  0x4e34ecfc, 0x9aab9993,
+  0x4e210617, 0x9a9c406e, 0x4e0d1c30, 0x9a8ceb31, 0x4df92f46, 0x9a7d99de,
+  0x4de53f5a, 0x9a6e4c74,
+  0x4dd14c6e, 0x9a5f02f5, 0x4dbd5682, 0x9a4fbd61, 0x4da95d96, 0x9a407bb9,
+  0x4d9561ac, 0x9a313dfc,
+  0x4d8162c4, 0x9a22042d, 0x4d6d60df, 0x9a12ce4b, 0x4d595bfe, 0x9a039c57,
+  0x4d455422, 0x99f46e51,
+  0x4d31494b, 0x99e5443b, 0x4d1d3b7a, 0x99d61e14, 0x4d092ab0, 0x99c6fbde,
+  0x4cf516ee, 0x99b7dd99,
+  0x4ce10034, 0x99a8c345, 0x4ccce684, 0x9999ace3, 0x4cb8c9dd, 0x998a9a74,
+  0x4ca4aa41, 0x997b8bf8,
+  0x4c9087b1, 0x996c816f, 0x4c7c622d, 0x995d7adc, 0x4c6839b7, 0x994e783d,
+  0x4c540e4e, 0x993f7993,
+  0x4c3fdff4, 0x99307ee0, 0x4c2baea9, 0x99218824, 0x4c177a6e, 0x9912955f,
+  0x4c034345, 0x9903a691,
+  0x4bef092d, 0x98f4bbbc, 0x4bdacc28, 0x98e5d4e0, 0x4bc68c36, 0x98d6f1fe,
+  0x4bb24958, 0x98c81316,
+  0x4b9e0390, 0x98b93828, 0x4b89badd, 0x98aa6136, 0x4b756f40, 0x989b8e40,
+  0x4b6120bb, 0x988cbf46,
+  0x4b4ccf4d, 0x987df449, 0x4b387af9, 0x986f2d4a, 0x4b2423be, 0x98606a49,
+  0x4b0fc99d, 0x9851ab46,
+  0x4afb6c98, 0x9842f043, 0x4ae70caf, 0x98343940, 0x4ad2a9e2, 0x9825863d,
+  0x4abe4433, 0x9816d73b,
+  0x4aa9dba2, 0x98082c3b, 0x4a957030, 0x97f9853d, 0x4a8101de, 0x97eae242,
+  0x4a6c90ad, 0x97dc4349,
+  0x4a581c9e, 0x97cda855, 0x4a43a5b0, 0x97bf1165, 0x4a2f2be6, 0x97b07e7a,
+  0x4a1aaf3f, 0x97a1ef94,
+  0x4a062fbd, 0x979364b5, 0x49f1ad61, 0x9784dddc, 0x49dd282a, 0x97765b0a,
+  0x49c8a01b, 0x9767dc41,
+  0x49b41533, 0x9759617f, 0x499f8774, 0x974aeac6, 0x498af6df, 0x973c7817,
+  0x49766373, 0x972e0971,
+  0x4961cd33, 0x971f9ed7, 0x494d341e, 0x97113847, 0x49389836, 0x9702d5c3,
+  0x4923f97b, 0x96f4774b,
+  0x490f57ee, 0x96e61ce0, 0x48fab391, 0x96d7c682, 0x48e60c62, 0x96c97432,
+  0x48d16265, 0x96bb25f0,
+  0x48bcb599, 0x96acdbbe, 0x48a805ff, 0x969e959b, 0x48935397, 0x96905388,
+  0x487e9e64, 0x96821585,
+  0x4869e665, 0x9673db94, 0x48552b9b, 0x9665a5b4, 0x48406e08, 0x965773e7,
+  0x482badab, 0x9649462d,
+  0x4816ea86, 0x963b1c86, 0x48022499, 0x962cf6f2, 0x47ed5be6, 0x961ed574,
+  0x47d8906d, 0x9610b80a,
+  0x47c3c22f, 0x96029eb6, 0x47aef12c, 0x95f48977, 0x479a1d67, 0x95e67850,
+  0x478546de, 0x95d86b3f,
+  0x47706d93, 0x95ca6247, 0x475b9188, 0x95bc5d66, 0x4746b2bc, 0x95ae5c9f,
+  0x4731d131, 0x95a05ff0,
+  0x471cece7, 0x9592675c, 0x470805df, 0x958472e2, 0x46f31c1a, 0x95768283,
+  0x46de2f99, 0x9568963f,
+  0x46c9405c, 0x955aae17, 0x46b44e65, 0x954cca0c, 0x469f59b4, 0x953eea1e,
+  0x468a624a, 0x95310e4e,
+  0x46756828, 0x9523369c, 0x46606b4e, 0x95156308, 0x464b6bbe, 0x95079394,
+  0x46366978, 0x94f9c83f,
+  0x4621647d, 0x94ec010b, 0x460c5cce, 0x94de3df8, 0x45f7526b, 0x94d07f05,
+  0x45e24556, 0x94c2c435,
+  0x45cd358f, 0x94b50d87, 0x45b82318, 0x94a75afd, 0x45a30df0, 0x9499ac95,
+  0x458df619, 0x948c0252,
+  0x4578db93, 0x947e5c33, 0x4563be60, 0x9470ba39, 0x454e9e80, 0x94631c65,
+  0x45397bf4, 0x945582b7,
+  0x452456bd, 0x9447ed2f, 0x450f2edb, 0x943a5bcf, 0x44fa0450, 0x942cce96,
+  0x44e4d71c, 0x941f4585,
+  0x44cfa740, 0x9411c09e, 0x44ba74bd, 0x94043fdf, 0x44a53f93, 0x93f6c34a,
+  0x449007c4, 0x93e94adf,
+  0x447acd50, 0x93dbd6a0, 0x44659039, 0x93ce668b, 0x4450507e, 0x93c0faa3,
+  0x443b0e21, 0x93b392e6,
+  0x4425c923, 0x93a62f57, 0x44108184, 0x9398cff5, 0x43fb3746, 0x938b74c1,
+  0x43e5ea68, 0x937e1dbb,
+  0x43d09aed, 0x9370cae4, 0x43bb48d4, 0x93637c3d, 0x43a5f41e, 0x935631c5,
+  0x43909ccd, 0x9348eb7e,
+  0x437b42e1, 0x933ba968, 0x4365e65b, 0x932e6b84, 0x4350873c, 0x932131d1,
+  0x433b2585, 0x9313fc51,
+  0x4325c135, 0x9306cb04, 0x43105a50, 0x92f99deb, 0x42faf0d4, 0x92ec7505,
+  0x42e584c3, 0x92df5054,
+  0x42d0161e, 0x92d22fd9, 0x42baa4e6, 0x92c51392, 0x42a5311b, 0x92b7fb82,
+  0x428fbabe, 0x92aae7a8,
+  0x427a41d0, 0x929dd806, 0x4264c653, 0x9290cc9b, 0x424f4845, 0x9283c568,
+  0x4239c7aa, 0x9276c26d,
+  0x42244481, 0x9269c3ac, 0x420ebecb, 0x925cc924, 0x41f93689, 0x924fd2d7,
+  0x41e3abbc, 0x9242e0c4,
+  0x41ce1e65, 0x9235f2ec, 0x41b88e84, 0x9229094f, 0x41a2fc1a, 0x921c23ef,
+  0x418d6729, 0x920f42cb,
+  0x4177cfb1, 0x920265e4, 0x416235b2, 0x91f58d3b, 0x414c992f, 0x91e8b8d0,
+  0x4136fa27, 0x91dbe8a4,
+  0x4121589b, 0x91cf1cb6, 0x410bb48c, 0x91c25508, 0x40f60dfb, 0x91b5919a,
+  0x40e064ea, 0x91a8d26d,
+  0x40cab958, 0x919c1781, 0x40b50b46, 0x918f60d6, 0x409f5ab6, 0x9182ae6d,
+  0x4089a7a8, 0x91760047,
+  0x4073f21d, 0x91695663, 0x405e3a16, 0x915cb0c3, 0x40487f94, 0x91500f67,
+  0x4032c297, 0x91437250,
+  0x401d0321, 0x9136d97d, 0x40074132, 0x912a44f0, 0x3ff17cca, 0x911db4a9,
+  0x3fdbb5ec, 0x911128a8,
+  0x3fc5ec98, 0x9104a0ee, 0x3fb020ce, 0x90f81d7b, 0x3f9a5290, 0x90eb9e50,
+  0x3f8481dd, 0x90df236e,
+  0x3f6eaeb8, 0x90d2acd4, 0x3f58d921, 0x90c63a83, 0x3f430119, 0x90b9cc7d,
+  0x3f2d26a0, 0x90ad62c0,
+  0x3f1749b8, 0x90a0fd4e, 0x3f016a61, 0x90949c28, 0x3eeb889c, 0x90883f4d,
+  0x3ed5a46b, 0x907be6be,
+  0x3ebfbdcd, 0x906f927c, 0x3ea9d4c3, 0x90634287, 0x3e93e950, 0x9056f6df,
+  0x3e7dfb73, 0x904aaf86,
+  0x3e680b2c, 0x903e6c7b, 0x3e52187f, 0x90322dbf, 0x3e3c2369, 0x9025f352,
+  0x3e262bee, 0x9019bd36,
+  0x3e10320d, 0x900d8b69, 0x3dfa35c8, 0x90015dee, 0x3de4371f, 0x8ff534c4,
+  0x3dce3614, 0x8fe90fec,
+  0x3db832a6, 0x8fdcef66, 0x3da22cd7, 0x8fd0d333, 0x3d8c24a8, 0x8fc4bb53,
+  0x3d761a19, 0x8fb8a7c7,
+  0x3d600d2c, 0x8fac988f, 0x3d49fde1, 0x8fa08dab, 0x3d33ec39, 0x8f94871d,
+  0x3d1dd835, 0x8f8884e4,
+  0x3d07c1d6, 0x8f7c8701, 0x3cf1a91c, 0x8f708d75, 0x3cdb8e09, 0x8f649840,
+  0x3cc5709e, 0x8f58a761,
+  0x3caf50da, 0x8f4cbadb, 0x3c992ec0, 0x8f40d2ad, 0x3c830a50, 0x8f34eed8,
+  0x3c6ce38a, 0x8f290f5c,
+  0x3c56ba70, 0x8f1d343a, 0x3c408f03, 0x8f115d72, 0x3c2a6142, 0x8f058b04,
+  0x3c143130, 0x8ef9bcf2,
+  0x3bfdfecd, 0x8eedf33b, 0x3be7ca1a, 0x8ee22de0, 0x3bd19318, 0x8ed66ce1,
+  0x3bbb59c7, 0x8ecab040,
+  0x3ba51e29, 0x8ebef7fb, 0x3b8ee03e, 0x8eb34415, 0x3b78a007, 0x8ea7948c,
+  0x3b625d86, 0x8e9be963,
+  0x3b4c18ba, 0x8e904298, 0x3b35d1a5, 0x8e84a02d, 0x3b1f8848, 0x8e790222,
+  0x3b093ca3, 0x8e6d6877,
+  0x3af2eeb7, 0x8e61d32e, 0x3adc9e86, 0x8e564246, 0x3ac64c0f, 0x8e4ab5bf,
+  0x3aaff755, 0x8e3f2d9b,
+  0x3a99a057, 0x8e33a9da, 0x3a834717, 0x8e282a7b, 0x3a6ceb96, 0x8e1caf80,
+  0x3a568dd4, 0x8e1138ea,
+  0x3a402dd2, 0x8e05c6b7, 0x3a29cb91, 0x8dfa58ea, 0x3a136712, 0x8deeef82,
+  0x39fd0056, 0x8de38a80,
+  0x39e6975e, 0x8dd829e4, 0x39d02c2a, 0x8dcccdaf, 0x39b9bebc, 0x8dc175e0,
+  0x39a34f13, 0x8db6227a,
+  0x398cdd32, 0x8daad37b, 0x39766919, 0x8d9f88e5, 0x395ff2c9, 0x8d9442b8,
+  0x39497a43, 0x8d8900f3,
+  0x3932ff87, 0x8d7dc399, 0x391c8297, 0x8d728aa9, 0x39060373, 0x8d675623,
+  0x38ef821c, 0x8d5c2609,
+  0x38d8fe93, 0x8d50fa59, 0x38c278d9, 0x8d45d316, 0x38abf0ef, 0x8d3ab03f,
+  0x389566d6, 0x8d2f91d5,
+  0x387eda8e, 0x8d2477d8, 0x38684c19, 0x8d196249, 0x3851bb77, 0x8d0e5127,
+  0x383b28a9, 0x8d034474,
+  0x382493b0, 0x8cf83c30, 0x380dfc8d, 0x8ced385b, 0x37f76341, 0x8ce238f6,
+  0x37e0c7cc, 0x8cd73e01,
+  0x37ca2a30, 0x8ccc477d, 0x37b38a6d, 0x8cc1556a, 0x379ce885, 0x8cb667c8,
+  0x37864477, 0x8cab7e98,
+  0x376f9e46, 0x8ca099da, 0x3758f5f2, 0x8c95b98f, 0x37424b7b, 0x8c8addb7,
+  0x372b9ee3, 0x8c800652,
+  0x3714f02a, 0x8c753362, 0x36fe3f52, 0x8c6a64e5, 0x36e78c5b, 0x8c5f9ade,
+  0x36d0d746, 0x8c54d54c,
+  0x36ba2014, 0x8c4a142f, 0x36a366c6, 0x8c3f5788, 0x368cab5c, 0x8c349f58,
+  0x3675edd9, 0x8c29eb9f,
+  0x365f2e3b, 0x8c1f3c5d, 0x36486c86, 0x8c149192, 0x3631a8b8, 0x8c09eb40,
+  0x361ae2d3, 0x8bff4966,
+  0x36041ad9, 0x8bf4ac05, 0x35ed50c9, 0x8bea131e, 0x35d684a6, 0x8bdf7eb0,
+  0x35bfb66e, 0x8bd4eebc,
+  0x35a8e625, 0x8bca6343, 0x359213c9, 0x8bbfdc44, 0x357b3f5d, 0x8bb559c1,
+  0x356468e2, 0x8baadbba,
+  0x354d9057, 0x8ba0622f, 0x3536b5be, 0x8b95ed21, 0x351fd918, 0x8b8b7c8f,
+  0x3508fa66, 0x8b81107b,
+  0x34f219a8, 0x8b76a8e4, 0x34db36df, 0x8b6c45cc, 0x34c4520d, 0x8b61e733,
+  0x34ad6b32, 0x8b578d18,
+  0x34968250, 0x8b4d377c, 0x347f9766, 0x8b42e661, 0x3468aa76, 0x8b3899c6,
+  0x3451bb81, 0x8b2e51ab,
+  0x343aca87, 0x8b240e11, 0x3423d78a, 0x8b19cef8, 0x340ce28b, 0x8b0f9462,
+  0x33f5eb89, 0x8b055e4d,
+  0x33def287, 0x8afb2cbb, 0x33c7f785, 0x8af0ffac, 0x33b0fa84, 0x8ae6d720,
+  0x3399fb85, 0x8adcb318,
+  0x3382fa88, 0x8ad29394, 0x336bf78f, 0x8ac87894, 0x3354f29b, 0x8abe6219,
+  0x333debab, 0x8ab45024,
+  0x3326e2c3, 0x8aaa42b4, 0x330fd7e1, 0x8aa039cb, 0x32f8cb07, 0x8a963567,
+  0x32e1bc36, 0x8a8c358b,
+  0x32caab6f, 0x8a823a36, 0x32b398b3, 0x8a784368, 0x329c8402, 0x8a6e5123,
+  0x32856d5e, 0x8a646365,
+  0x326e54c7, 0x8a5a7a31, 0x32573a3f, 0x8a509585, 0x32401dc6, 0x8a46b564,
+  0x3228ff5c, 0x8a3cd9cc,
+  0x3211df04, 0x8a3302be, 0x31fabcbd, 0x8a29303b, 0x31e39889, 0x8a1f6243,
+  0x31cc7269, 0x8a1598d6,
+  0x31b54a5e, 0x8a0bd3f5, 0x319e2067, 0x8a0213a0, 0x3186f487, 0x89f857d8,
+  0x316fc6be, 0x89eea09d,
+  0x3158970e, 0x89e4edef, 0x31416576, 0x89db3fcf, 0x312a31f8, 0x89d1963c,
+  0x3112fc95, 0x89c7f138,
+  0x30fbc54d, 0x89be50c3, 0x30e48c22, 0x89b4b4dd, 0x30cd5115, 0x89ab1d87,
+  0x30b61426, 0x89a18ac0,
+  0x309ed556, 0x8997fc8a, 0x308794a6, 0x898e72e4, 0x30705217, 0x8984edcf,
+  0x30590dab, 0x897b6d4c,
+  0x3041c761, 0x8971f15a, 0x302a7f3a, 0x896879fb, 0x30133539, 0x895f072e,
+  0x2ffbe95d, 0x895598f3,
+  0x2fe49ba7, 0x894c2f4c, 0x2fcd4c19, 0x8942ca39, 0x2fb5fab2, 0x893969b9,
+  0x2f9ea775, 0x89300dce,
+  0x2f875262, 0x8926b677, 0x2f6ffb7a, 0x891d63b5, 0x2f58a2be, 0x89141589,
+  0x2f41482e, 0x890acbf2,
+  0x2f29ebcc, 0x890186f2, 0x2f128d99, 0x88f84687, 0x2efb2d95, 0x88ef0ab4,
+  0x2ee3cbc1, 0x88e5d378,
+  0x2ecc681e, 0x88dca0d3, 0x2eb502ae, 0x88d372c6, 0x2e9d9b70, 0x88ca4951,
+  0x2e863267, 0x88c12475,
+  0x2e6ec792, 0x88b80432, 0x2e575af3, 0x88aee888, 0x2e3fec8b, 0x88a5d177,
+  0x2e287c5a, 0x889cbf01,
+  0x2e110a62, 0x8893b125, 0x2df996a3, 0x888aa7e3, 0x2de2211e, 0x8881a33d,
+  0x2dcaa9d5, 0x8878a332,
+  0x2db330c7, 0x886fa7c2, 0x2d9bb5f6, 0x8866b0ef, 0x2d843964, 0x885dbeb8,
+  0x2d6cbb10, 0x8854d11e,
+  0x2d553afc, 0x884be821, 0x2d3db928, 0x884303c1, 0x2d263596, 0x883a23ff,
+  0x2d0eb046, 0x883148db,
+  0x2cf72939, 0x88287256, 0x2cdfa071, 0x881fa06f, 0x2cc815ee, 0x8816d327,
+  0x2cb089b1, 0x880e0a7f,
+  0x2c98fbba, 0x88054677, 0x2c816c0c, 0x87fc870f, 0x2c69daa6, 0x87f3cc48,
+  0x2c52478a, 0x87eb1621,
+  0x2c3ab2b9, 0x87e2649b, 0x2c231c33, 0x87d9b7b7, 0x2c0b83fa, 0x87d10f75,
+  0x2bf3ea0d, 0x87c86bd5,
+  0x2bdc4e6f, 0x87bfccd7, 0x2bc4b120, 0x87b7327d, 0x2bad1221, 0x87ae9cc5,
+  0x2b957173, 0x87a60bb1,
+  0x2b7dcf17, 0x879d7f41, 0x2b662b0e, 0x8794f774, 0x2b4e8558, 0x878c744d,
+  0x2b36ddf7, 0x8783f5ca,
+  0x2b1f34eb, 0x877b7bec, 0x2b078a36, 0x877306b4, 0x2aefddd8, 0x876a9621,
+  0x2ad82fd2, 0x87622a35,
+  0x2ac08026, 0x8759c2ef, 0x2aa8ced3, 0x87516050, 0x2a911bdc, 0x87490258,
+  0x2a796740, 0x8740a907,
+  0x2a61b101, 0x8738545e, 0x2a49f920, 0x8730045d, 0x2a323f9e, 0x8727b905,
+  0x2a1a847b, 0x871f7255,
+  0x2a02c7b8, 0x8717304e, 0x29eb0957, 0x870ef2f1, 0x29d34958, 0x8706ba3d,
+  0x29bb87bc, 0x86fe8633,
+  0x29a3c485, 0x86f656d3, 0x298bffb2, 0x86ee2c1e, 0x29743946, 0x86e60614,
+  0x295c7140, 0x86dde4b5,
+  0x2944a7a2, 0x86d5c802, 0x292cdc6d, 0x86cdaffa, 0x29150fa1, 0x86c59c9f,
+  0x28fd4140, 0x86bd8df0,
+  0x28e5714b, 0x86b583ee, 0x28cd9fc1, 0x86ad7e99, 0x28b5cca5, 0x86a57df2,
+  0x289df7f8, 0x869d81f8,
+  0x288621b9, 0x86958aac, 0x286e49ea, 0x868d980e, 0x2856708d, 0x8685aa20,
+  0x283e95a1, 0x867dc0e0,
+  0x2826b928, 0x8675dc4f, 0x280edb23, 0x866dfc6e, 0x27f6fb92, 0x8666213c,
+  0x27df1a77, 0x865e4abb,
+  0x27c737d3, 0x865678eb, 0x27af53a6, 0x864eabcb, 0x27976df1, 0x8646e35c,
+  0x277f86b5, 0x863f1f9e,
+  0x27679df4, 0x86376092, 0x274fb3ae, 0x862fa638, 0x2737c7e3, 0x8627f091,
+  0x271fda96, 0x86203f9c,
+  0x2707ebc7, 0x86189359, 0x26effb76, 0x8610ebca, 0x26d809a5, 0x860948ef,
+  0x26c01655, 0x8601aac7,
+  0x26a82186, 0x85fa1153, 0x26902b39, 0x85f27c93, 0x26783370, 0x85eaec88,
+  0x26603a2c, 0x85e36132,
+  0x26483f6c, 0x85dbda91, 0x26304333, 0x85d458a6, 0x26184581, 0x85ccdb70,
+  0x26004657, 0x85c562f1,
+  0x25e845b6, 0x85bdef28, 0x25d0439f, 0x85b68015, 0x25b84012, 0x85af15b9,
+  0x25a03b11, 0x85a7b015,
+  0x2588349d, 0x85a04f28, 0x25702cb7, 0x8598f2f3, 0x2558235f, 0x85919b76,
+  0x25401896, 0x858a48b1,
+  0x25280c5e, 0x8582faa5, 0x250ffeb7, 0x857bb152, 0x24f7efa2, 0x85746cb8,
+  0x24dfdf20, 0x856d2cd7,
+  0x24c7cd33, 0x8565f1b0, 0x24afb9da, 0x855ebb44, 0x2497a517, 0x85578991,
+  0x247f8eec, 0x85505c99,
+  0x24677758, 0x8549345c, 0x244f5e5c, 0x854210db, 0x243743fa, 0x853af214,
+  0x241f2833, 0x8533d809,
+  0x24070b08, 0x852cc2bb, 0x23eeec78, 0x8525b228, 0x23d6cc87, 0x851ea652,
+  0x23beab33, 0x85179f39,
+  0x23a6887f, 0x85109cdd, 0x238e646a, 0x85099f3e, 0x23763ef7, 0x8502a65c,
+  0x235e1826, 0x84fbb239,
+  0x2345eff8, 0x84f4c2d4, 0x232dc66d, 0x84edd82d, 0x23159b88, 0x84e6f244,
+  0x22fd6f48, 0x84e0111b,
+  0x22e541af, 0x84d934b1, 0x22cd12bd, 0x84d25d06, 0x22b4e274, 0x84cb8a1b,
+  0x229cb0d5, 0x84c4bbf0,
+  0x22847de0, 0x84bdf286, 0x226c4996, 0x84b72ddb, 0x225413f8, 0x84b06df2,
+  0x223bdd08, 0x84a9b2ca,
+  0x2223a4c5, 0x84a2fc62, 0x220b6b32, 0x849c4abd, 0x21f3304f, 0x84959dd9,
+  0x21daf41d, 0x848ef5b7,
+  0x21c2b69c, 0x84885258, 0x21aa77cf, 0x8481b3bb, 0x219237b5, 0x847b19e1,
+  0x2179f64f, 0x847484ca,
+  0x2161b3a0, 0x846df477, 0x21496fa7, 0x846768e7, 0x21312a65, 0x8460e21a,
+  0x2118e3dc, 0x845a6012,
+  0x21009c0c, 0x8453e2cf, 0x20e852f6, 0x844d6a50, 0x20d0089c, 0x8446f695,
+  0x20b7bcfe, 0x844087a0,
+  0x209f701c, 0x843a1d70, 0x208721f9, 0x8433b806, 0x206ed295, 0x842d5762,
+  0x205681f1, 0x8426fb84,
+  0x203e300d, 0x8420a46c, 0x2025dcec, 0x841a521a, 0x200d888d, 0x84140490,
+  0x1ff532f2, 0x840dbbcc,
+  0x1fdcdc1b, 0x840777d0, 0x1fc4840a, 0x8401389b, 0x1fac2abf, 0x83fafe2e,
+  0x1f93d03c, 0x83f4c889,
+  0x1f7b7481, 0x83ee97ad, 0x1f63178f, 0x83e86b99, 0x1f4ab968, 0x83e2444d,
+  0x1f325a0b, 0x83dc21cb,
+  0x1f19f97b, 0x83d60412, 0x1f0197b8, 0x83cfeb22, 0x1ee934c3, 0x83c9d6fc,
+  0x1ed0d09d, 0x83c3c7a0,
+  0x1eb86b46, 0x83bdbd0e, 0x1ea004c1, 0x83b7b746, 0x1e879d0d, 0x83b1b649,
+  0x1e6f342c, 0x83abba17,
+  0x1e56ca1e, 0x83a5c2b0, 0x1e3e5ee5, 0x839fd014, 0x1e25f282, 0x8399e244,
+  0x1e0d84f5, 0x8393f940,
+  0x1df5163f, 0x838e1507, 0x1ddca662, 0x8388359b, 0x1dc4355e, 0x83825afb,
+  0x1dabc334, 0x837c8528,
+  0x1d934fe5, 0x8376b422, 0x1d7adb73, 0x8370e7e9, 0x1d6265dd, 0x836b207d,
+  0x1d49ef26, 0x83655ddf,
+  0x1d31774d, 0x835fa00f, 0x1d18fe54, 0x8359e70d, 0x1d00843d, 0x835432d8,
+  0x1ce80906, 0x834e8373,
+  0x1ccf8cb3, 0x8348d8dc, 0x1cb70f43, 0x83433314, 0x1c9e90b8, 0x833d921b,
+  0x1c861113, 0x8337f5f1,
+  0x1c6d9053, 0x83325e97, 0x1c550e7c, 0x832ccc0d, 0x1c3c8b8c, 0x83273e52,
+  0x1c240786, 0x8321b568,
+  0x1c0b826a, 0x831c314e, 0x1bf2fc3a, 0x8316b205, 0x1bda74f6, 0x8311378d,
+  0x1bc1ec9e, 0x830bc1e6,
+  0x1ba96335, 0x83065110, 0x1b90d8bb, 0x8300e50b, 0x1b784d30, 0x82fb7dd8,
+  0x1b5fc097, 0x82f61b77,
+  0x1b4732ef, 0x82f0bde8, 0x1b2ea43a, 0x82eb652b, 0x1b161479, 0x82e61141,
+  0x1afd83ad, 0x82e0c22a,
+  0x1ae4f1d6, 0x82db77e5, 0x1acc5ef6, 0x82d63274, 0x1ab3cb0d, 0x82d0f1d5,
+  0x1a9b361d, 0x82cbb60b,
+  0x1a82a026, 0x82c67f14, 0x1a6a0929, 0x82c14cf1, 0x1a517128, 0x82bc1fa2,
+  0x1a38d823, 0x82b6f727,
+  0x1a203e1b, 0x82b1d381, 0x1a07a311, 0x82acb4b0, 0x19ef0707, 0x82a79ab3,
+  0x19d669fc, 0x82a2858c,
+  0x19bdcbf3, 0x829d753a, 0x19a52ceb, 0x829869be, 0x198c8ce7, 0x82936317,
+  0x1973ebe6, 0x828e6146,
+  0x195b49ea, 0x8289644b, 0x1942a6f3, 0x82846c26, 0x192a0304, 0x827f78d8,
+  0x19115e1c, 0x827a8a61,
+  0x18f8b83c, 0x8275a0c0, 0x18e01167, 0x8270bbf7, 0x18c7699b, 0x826bdc04,
+  0x18aec0db, 0x826700e9,
+  0x18961728, 0x82622aa6, 0x187d6c82, 0x825d593a, 0x1864c0ea, 0x82588ca7,
+  0x184c1461, 0x8253c4eb,
+  0x183366e9, 0x824f0208, 0x181ab881, 0x824a43fe, 0x1802092c, 0x82458acc,
+  0x17e958ea, 0x8240d673,
+  0x17d0a7bc, 0x823c26f3, 0x17b7f5a3, 0x82377c4c, 0x179f429f, 0x8232d67f,
+  0x17868eb3, 0x822e358b,
+  0x176dd9de, 0x82299971, 0x17552422, 0x82250232, 0x173c6d80, 0x82206fcc,
+  0x1723b5f9, 0x821be240,
+  0x170afd8d, 0x82175990, 0x16f2443e, 0x8212d5b9, 0x16d98a0c, 0x820e56be,
+  0x16c0cef9, 0x8209dc9e,
+  0x16a81305, 0x82056758, 0x168f5632, 0x8200f6ef, 0x1676987f, 0x81fc8b60,
+  0x165dd9f0, 0x81f824ae,
+  0x16451a83, 0x81f3c2d7, 0x162c5a3b, 0x81ef65dc, 0x16139918, 0x81eb0dbe,
+  0x15fad71b, 0x81e6ba7c,
+  0x15e21445, 0x81e26c16, 0x15c95097, 0x81de228d, 0x15b08c12, 0x81d9dde1,
+  0x1597c6b7, 0x81d59e13,
+  0x157f0086, 0x81d16321, 0x15663982, 0x81cd2d0c, 0x154d71aa, 0x81c8fbd6,
+  0x1534a901, 0x81c4cf7d,
+  0x151bdf86, 0x81c0a801, 0x1503153a, 0x81bc8564, 0x14ea4a1f, 0x81b867a5,
+  0x14d17e36, 0x81b44ec4,
+  0x14b8b17f, 0x81b03ac2, 0x149fe3fc, 0x81ac2b9e, 0x148715ae, 0x81a82159,
+  0x146e4694, 0x81a41bf4,
+  0x145576b1, 0x81a01b6d, 0x143ca605, 0x819c1fc5, 0x1423d492, 0x819828fd,
+  0x140b0258, 0x81943715,
+  0x13f22f58, 0x81904a0c, 0x13d95b93, 0x818c61e3, 0x13c0870a, 0x81887e9a,
+  0x13a7b1bf, 0x8184a032,
+  0x138edbb1, 0x8180c6a9, 0x137604e2, 0x817cf201, 0x135d2d53, 0x8179223a,
+  0x13445505, 0x81755754,
+  0x132b7bf9, 0x8171914e, 0x1312a230, 0x816dd02a, 0x12f9c7aa, 0x816a13e6,
+  0x12e0ec6a, 0x81665c84,
+  0x12c8106f, 0x8162aa04, 0x12af33ba, 0x815efc65, 0x1296564d, 0x815b53a8,
+  0x127d7829, 0x8157afcd,
+  0x1264994e, 0x815410d4, 0x124bb9be, 0x815076bd, 0x1232d979, 0x814ce188,
+  0x1219f880, 0x81495136,
+  0x120116d5, 0x8145c5c7, 0x11e83478, 0x81423f3a, 0x11cf516a, 0x813ebd90,
+  0x11b66dad, 0x813b40ca,
+  0x119d8941, 0x8137c8e6, 0x1184a427, 0x813455e6, 0x116bbe60, 0x8130e7c9,
+  0x1152d7ed, 0x812d7e8f,
+  0x1139f0cf, 0x812a1a3a, 0x11210907, 0x8126bac8, 0x11082096, 0x8123603a,
+  0x10ef377d, 0x81200a90,
+  0x10d64dbd, 0x811cb9ca, 0x10bd6356, 0x81196de9, 0x10a4784b, 0x811626ec,
+  0x108b8c9b, 0x8112e4d4,
+  0x1072a048, 0x810fa7a0, 0x1059b352, 0x810c6f52, 0x1040c5bb, 0x81093be8,
+  0x1027d784, 0x81060d63,
+  0x100ee8ad, 0x8102e3c4, 0xff5f938, 0x80ffbf0a, 0xfdd0926, 0x80fc9f35,
+  0xfc41876, 0x80f98446,
+  0xfab272b, 0x80f66e3c, 0xf923546, 0x80f35d19, 0xf7942c7, 0x80f050db,
+  0xf604faf, 0x80ed4984,
+  0xf475bff, 0x80ea4712, 0xf2e67b8, 0x80e74987, 0xf1572dc, 0x80e450e2,
+  0xefc7d6b, 0x80e15d24,
+  0xee38766, 0x80de6e4c, 0xeca90ce, 0x80db845b, 0xeb199a4, 0x80d89f51,
+  0xe98a1e9, 0x80d5bf2e,
+  0xe7fa99e, 0x80d2e3f2, 0xe66b0c3, 0x80d00d9d, 0xe4db75b, 0x80cd3c2f,
+  0xe34bd66, 0x80ca6fa9,
+  0xe1bc2e4, 0x80c7a80a, 0xe02c7d7, 0x80c4e553, 0xde9cc40, 0x80c22784,
+  0xdd0d01f, 0x80bf6e9c,
+  0xdb7d376, 0x80bcba9d, 0xd9ed646, 0x80ba0b85, 0xd85d88f, 0x80b76156,
+  0xd6cda53, 0x80b4bc0e,
+  0xd53db92, 0x80b21baf, 0xd3adc4e, 0x80af8039, 0xd21dc87, 0x80ace9ab,
+  0xd08dc3f, 0x80aa5806,
+  0xcefdb76, 0x80a7cb49, 0xcd6da2d, 0x80a54376, 0xcbdd865, 0x80a2c08b,
+  0xca4d620, 0x80a04289,
+  0xc8bd35e, 0x809dc971, 0xc72d020, 0x809b5541, 0xc59cc68, 0x8098e5fb,
+  0xc40c835, 0x80967b9f,
+  0xc27c389, 0x8094162c, 0xc0ebe66, 0x8091b5a2, 0xbf5b8cb, 0x808f5a02,
+  0xbdcb2bb, 0x808d034c,
+  0xbc3ac35, 0x808ab180, 0xbaaa53b, 0x8088649e, 0xb919dcf, 0x80861ca6,
+  0xb7895f0, 0x8083d998,
+  0xb5f8d9f, 0x80819b74, 0xb4684df, 0x807f623b, 0xb2d7baf, 0x807d2dec,
+  0xb147211, 0x807afe87,
+  0xafb6805, 0x8078d40d, 0xae25d8d, 0x8076ae7e, 0xac952aa, 0x80748dd9,
+  0xab0475c, 0x8072721f,
+  0xa973ba5, 0x80705b50, 0xa7e2f85, 0x806e496c, 0xa6522fe, 0x806c3c74,
+  0xa4c1610, 0x806a3466,
+  0xa3308bd, 0x80683143, 0xa19fb04, 0x8066330c, 0xa00ece8, 0x806439c0,
+  0x9e7de6a, 0x80624560,
+  0x9cecf89, 0x806055eb, 0x9b5c048, 0x805e6b62, 0x99cb0a7, 0x805c85c4,
+  0x983a0a7, 0x805aa512,
+  0x96a9049, 0x8058c94c, 0x9517f8f, 0x8056f272, 0x9386e78, 0x80552084,
+  0x91f5d06, 0x80535381,
+  0x9064b3a, 0x80518b6b, 0x8ed3916, 0x804fc841, 0x8d42699, 0x804e0a04,
+  0x8bb13c5, 0x804c50b2,
+  0x8a2009a, 0x804a9c4d, 0x888ed1b, 0x8048ecd5, 0x86fd947, 0x80474248,
+  0x856c520, 0x80459ca9,
+  0x83db0a7, 0x8043fbf6, 0x8249bdd, 0x80426030, 0x80b86c2, 0x8040c956,
+  0x7f27157, 0x803f376a,
+  0x7d95b9e, 0x803daa6a, 0x7c04598, 0x803c2257, 0x7a72f45, 0x803a9f31,
+  0x78e18a7, 0x803920f8,
+  0x77501be, 0x8037a7ac, 0x75bea8c, 0x8036334e, 0x742d311, 0x8034c3dd,
+  0x729bb4e, 0x80335959,
+  0x710a345, 0x8031f3c2, 0x6f78af6, 0x80309318, 0x6de7262, 0x802f375d,
+  0x6c5598a, 0x802de08e,
+  0x6ac406f, 0x802c8ead, 0x6932713, 0x802b41ba, 0x67a0d76, 0x8029f9b4,
+  0x660f398, 0x8028b69c,
+  0x647d97c, 0x80277872, 0x62ebf22, 0x80263f36, 0x615a48b, 0x80250ae7,
+  0x5fc89b8, 0x8023db86,
+  0x5e36ea9, 0x8022b114, 0x5ca5361, 0x80218b8f, 0x5b137df, 0x80206af8,
+  0x5981c26, 0x801f4f4f,
+  0x57f0035, 0x801e3895, 0x565e40d, 0x801d26c8, 0x54cc7b1, 0x801c19ea,
+  0x533ab20, 0x801b11fa,
+  0x51a8e5c, 0x801a0ef8, 0x5017165, 0x801910e4, 0x4e8543e, 0x801817bf,
+  0x4cf36e5, 0x80172388,
+  0x4b6195d, 0x80163440, 0x49cfba7, 0x801549e6, 0x483ddc3, 0x8014647b,
+  0x46abfb3, 0x801383fe,
+  0x451a177, 0x8012a86f, 0x4388310, 0x8011d1d0, 0x41f6480, 0x8011001f,
+  0x40645c7, 0x8010335c,
+  0x3ed26e6, 0x800f6b88, 0x3d407df, 0x800ea8a3, 0x3bae8b2, 0x800deaad,
+  0x3a1c960, 0x800d31a5,
+  0x388a9ea, 0x800c7d8c, 0x36f8a51, 0x800bce63, 0x3566a96, 0x800b2427,
+  0x33d4abb, 0x800a7edb,
+  0x3242abf, 0x8009de7e, 0x30b0aa4, 0x80094310, 0x2f1ea6c, 0x8008ac90,
+  0x2d8ca16, 0x80081b00,
+  0x2bfa9a4, 0x80078e5e, 0x2a68917, 0x800706ac, 0x28d6870, 0x800683e8,
+  0x27447b0, 0x80060614,
+  0x25b26d7, 0x80058d2f, 0x24205e8, 0x80051939, 0x228e4e2, 0x8004aa32,
+  0x20fc3c6, 0x8004401a,
+  0x1f6a297, 0x8003daf1, 0x1dd8154, 0x80037ab7, 0x1c45ffe, 0x80031f6d,
+  0x1ab3e97, 0x8002c912,
+  0x1921d20, 0x800277a6, 0x178fb99, 0x80022b29, 0x15fda03, 0x8001e39b,
+  0x146b860, 0x8001a0fd,
+  0x12d96b1, 0x8001634e, 0x11474f6, 0x80012a8e, 0xfb5330, 0x8000f6bd,
+  0xe23160, 0x8000c7dc,
+  0xc90f88, 0x80009dea, 0xafeda8, 0x800078e7, 0x96cbc1, 0x800058d4, 0x7da9d4,
+  0x80003daf,
+  0x6487e3, 0x8000277a, 0x4b65ee, 0x80001635, 0x3243f5, 0x800009df, 0x1921fb,
+  0x80000278,
+};
+
+/**   
+* \par   
+* cosFactor tables are generated using the formula : 
    cos_factors[n] = 2 * cos((2n+1)*pi/(4*N))
       
+* \par   
+* C command to generate the table   
+* 
       
+* for(i = 0; i< N; i++)   
+* {   
+*   cos_factors[i]= 2 * cos((2*i+1)*c/2);   
+* } 
       
+* \par   
+* where N is the number of factors to generate and c is pi/(2*N)   
+* \par   
+* Then converted to q31 format by multiplying with 2^31 and saturated if required.   
+*/
+
+
+static const q31_t cos_factorsQ31_128[128] = {
+  0x7fff6216, 0x7ffa72d1, 0x7ff09478, 0x7fe1c76b, 0x7fce0c3e, 0x7fb563b3,
+  0x7f97cebd, 0x7f754e80,
+  0x7f4de451, 0x7f2191b4, 0x7ef05860, 0x7eba3a39, 0x7e7f3957, 0x7e3f57ff,
+  0x7dfa98a8, 0x7db0fdf8,
+  0x7d628ac6, 0x7d0f4218, 0x7cb72724, 0x7c5a3d50, 0x7bf88830, 0x7b920b89,
+  0x7b26cb4f, 0x7ab6cba4,
+  0x7a4210d8, 0x79c89f6e, 0x794a7c12, 0x78c7aba2, 0x78403329, 0x77b417df,
+  0x77235f2d, 0x768e0ea6,
+  0x75f42c0b, 0x7555bd4c, 0x74b2c884, 0x740b53fb, 0x735f6626, 0x72af05a7,
+  0x71fa3949, 0x71410805,
+  0x708378ff, 0x6fc19385, 0x6efb5f12, 0x6e30e34a, 0x6d6227fa, 0x6c8f351c,
+  0x6bb812d1, 0x6adcc964,
+  0x69fd614a, 0x6919e320, 0x683257ab, 0x6746c7d8, 0x66573cbb, 0x6563bf92,
+  0x646c59bf, 0x637114cc,
+  0x6271fa69, 0x616f146c, 0x60686ccf, 0x5f5e0db3, 0x5e50015d, 0x5d3e5237,
+  0x5c290acc, 0x5b1035cf,
+  0x59f3de12, 0x58d40e8c, 0x57b0d256, 0x568a34a9, 0x556040e2, 0x5433027d,
+  0x53028518, 0x51ced46e,
+  0x5097fc5e, 0x4f5e08e3, 0x4e210617, 0x4ce10034, 0x4b9e0390, 0x4a581c9e,
+  0x490f57ee, 0x47c3c22f,
+  0x46756828, 0x452456bd, 0x43d09aed, 0x427a41d0, 0x4121589b, 0x3fc5ec98,
+  0x3e680b2c, 0x3d07c1d6,
+  0x3ba51e29, 0x3a402dd2, 0x38d8fe93, 0x376f9e46, 0x36041ad9, 0x34968250,
+  0x3326e2c3, 0x31b54a5e,
+  0x3041c761, 0x2ecc681e, 0x2d553afc, 0x2bdc4e6f, 0x2a61b101, 0x28e5714b,
+  0x27679df4, 0x25e845b6,
+  0x24677758, 0x22e541af, 0x2161b3a0, 0x1fdcdc1b, 0x1e56ca1e, 0x1ccf8cb3,
+  0x1b4732ef, 0x19bdcbf3,
+  0x183366e9, 0x16a81305, 0x151bdf86, 0x138edbb1, 0x120116d5, 0x1072a048,
+  0xee38766, 0xd53db92,
+  0xbc3ac35, 0xa3308bd, 0x8a2009a, 0x710a345, 0x57f0035, 0x3ed26e6, 0x25b26d7,
+  0xc90f88,
+};
+
+static const q31_t cos_factorsQ31_512[512] = {
+  0x7ffff621, 0x7fffa72c, 0x7fff0943, 0x7ffe1c65, 0x7ffce093, 0x7ffb55ce,
+  0x7ff97c18, 0x7ff75370,
+  0x7ff4dbd9, 0x7ff21553, 0x7feeffe1, 0x7feb9b85, 0x7fe7e841, 0x7fe3e616,
+  0x7fdf9508, 0x7fdaf519,
+  0x7fd6064c, 0x7fd0c8a3, 0x7fcb3c23, 0x7fc560cf, 0x7fbf36aa, 0x7fb8bdb8,
+  0x7fb1f5fc, 0x7faadf7c,
+  0x7fa37a3c, 0x7f9bc640, 0x7f93c38c, 0x7f8b7227, 0x7f82d214, 0x7f79e35a,
+  0x7f70a5fe, 0x7f671a05,
+  0x7f5d3f75, 0x7f531655, 0x7f489eaa, 0x7f3dd87c, 0x7f32c3d1, 0x7f2760af,
+  0x7f1baf1e, 0x7f0faf25,
+  0x7f0360cb, 0x7ef6c418, 0x7ee9d914, 0x7edc9fc6, 0x7ecf1837, 0x7ec14270,
+  0x7eb31e78, 0x7ea4ac58,
+  0x7e95ec1a, 0x7e86ddc6, 0x7e778166, 0x7e67d703, 0x7e57dea7, 0x7e47985b,
+  0x7e37042a, 0x7e26221f,
+  0x7e14f242, 0x7e0374a0, 0x7df1a942, 0x7ddf9034, 0x7dcd2981, 0x7dba7534,
+  0x7da77359, 0x7d9423fc,
+  0x7d808728, 0x7d6c9ce9, 0x7d58654d, 0x7d43e05e, 0x7d2f0e2b, 0x7d19eebf,
+  0x7d048228, 0x7ceec873,
+  0x7cd8c1ae, 0x7cc26de5, 0x7cabcd28, 0x7c94df83, 0x7c7da505, 0x7c661dbc,
+  0x7c4e49b7, 0x7c362904,
+  0x7c1dbbb3, 0x7c0501d2, 0x7bebfb70, 0x7bd2a89e, 0x7bb9096b, 0x7b9f1de6,
+  0x7b84e61f, 0x7b6a6227,
+  0x7b4f920e, 0x7b3475e5, 0x7b190dbc, 0x7afd59a4, 0x7ae159ae, 0x7ac50dec,
+  0x7aa8766f, 0x7a8b9348,
+  0x7a6e648a, 0x7a50ea47, 0x7a332490, 0x7a151378, 0x79f6b711, 0x79d80f6f,
+  0x79b91ca4, 0x7999dec4,
+  0x797a55e0, 0x795a820e, 0x793a6361, 0x7919f9ec, 0x78f945c3, 0x78d846fb,
+  0x78b6fda8, 0x789569df,
+  0x78738bb3, 0x7851633b, 0x782ef08b, 0x780c33b8, 0x77e92cd9, 0x77c5dc01,
+  0x77a24148, 0x777e5cc3,
+  0x775a2e89, 0x7735b6af, 0x7710f54c, 0x76ebea77, 0x76c69647, 0x76a0f8d2,
+  0x767b1231, 0x7654e279,
+  0x762e69c4, 0x7607a828, 0x75e09dbd, 0x75b94a9c, 0x7591aedd, 0x7569ca99,
+  0x75419de7, 0x751928e0,
+  0x74f06b9e, 0x74c7663a, 0x749e18cd, 0x74748371, 0x744aa63f, 0x74208150,
+  0x73f614c0, 0x73cb60a8,
+  0x73a06522, 0x73752249, 0x73499838, 0x731dc70a, 0x72f1aed9, 0x72c54fc1,
+  0x7298a9dd, 0x726bbd48,
+  0x723e8a20, 0x7211107e, 0x71e35080, 0x71b54a41, 0x7186fdde, 0x71586b74,
+  0x7129931f, 0x70fa74fc,
+  0x70cb1128, 0x709b67c0, 0x706b78e3, 0x703b44ad, 0x700acb3c, 0x6fda0cae,
+  0x6fa90921, 0x6f77c0b3,
+  0x6f463383, 0x6f1461b0, 0x6ee24b57, 0x6eaff099, 0x6e7d5193, 0x6e4a6e66,
+  0x6e174730, 0x6de3dc11,
+  0x6db02d29, 0x6d7c3a98, 0x6d48047e, 0x6d138afb, 0x6cdece2f, 0x6ca9ce3b,
+  0x6c748b3f, 0x6c3f055d,
+  0x6c093cb6, 0x6bd3316a, 0x6b9ce39b, 0x6b66536b, 0x6b2f80fb, 0x6af86c6c,
+  0x6ac115e2, 0x6a897d7d,
+  0x6a51a361, 0x6a1987b0, 0x69e12a8c, 0x69a88c19, 0x696fac78, 0x69368bce,
+  0x68fd2a3d, 0x68c387e9,
+  0x6889a4f6, 0x684f8186, 0x68151dbe, 0x67da79c3, 0x679f95b7, 0x676471c0,
+  0x67290e02, 0x66ed6aa1,
+  0x66b187c3, 0x6675658c, 0x66390422, 0x65fc63a9, 0x65bf8447, 0x65826622,
+  0x6545095f, 0x65076e25,
+  0x64c99498, 0x648b7ce0, 0x644d2722, 0x640e9386, 0x63cfc231, 0x6390b34a,
+  0x635166f9, 0x6311dd64,
+  0x62d216b3, 0x6292130c, 0x6251d298, 0x6211557e, 0x61d09be5, 0x618fa5f7,
+  0x614e73da, 0x610d05b7,
+  0x60cb5bb7, 0x60897601, 0x604754bf, 0x6004f819, 0x5fc26038, 0x5f7f8d46,
+  0x5f3c7f6b, 0x5ef936d1,
+  0x5eb5b3a2, 0x5e71f606, 0x5e2dfe29, 0x5de9cc33, 0x5da5604f, 0x5d60baa7,
+  0x5d1bdb65, 0x5cd6c2b5,
+  0x5c9170bf, 0x5c4be5b0, 0x5c0621b2, 0x5bc024f0, 0x5b79ef96, 0x5b3381ce,
+  0x5aecdbc5, 0x5aa5fda5,
+  0x5a5ee79a, 0x5a1799d1, 0x59d01475, 0x598857b2, 0x594063b5, 0x58f838a9,
+  0x58afd6bd, 0x58673e1b,
+  0x581e6ef1, 0x57d5696d, 0x578c2dba, 0x5742bc06, 0x56f9147e, 0x56af3750,
+  0x566524aa, 0x561adcb9,
+  0x55d05faa, 0x5585adad, 0x553ac6ee, 0x54efab9c, 0x54a45be6, 0x5458d7f9,
+  0x540d2005, 0x53c13439,
+  0x537514c2, 0x5328c1d0, 0x52dc3b92, 0x528f8238, 0x524295f0, 0x51f576ea,
+  0x51a82555, 0x515aa162,
+  0x510ceb40, 0x50bf031f, 0x5070e92f, 0x50229da1, 0x4fd420a4, 0x4f857269,
+  0x4f369320, 0x4ee782fb,
+  0x4e984229, 0x4e48d0dd, 0x4df92f46, 0x4da95d96, 0x4d595bfe, 0x4d092ab0,
+  0x4cb8c9dd, 0x4c6839b7,
+  0x4c177a6e, 0x4bc68c36, 0x4b756f40, 0x4b2423be, 0x4ad2a9e2, 0x4a8101de,
+  0x4a2f2be6, 0x49dd282a,
+  0x498af6df, 0x49389836, 0x48e60c62, 0x48935397, 0x48406e08, 0x47ed5be6,
+  0x479a1d67, 0x4746b2bc,
+  0x46f31c1a, 0x469f59b4, 0x464b6bbe, 0x45f7526b, 0x45a30df0, 0x454e9e80,
+  0x44fa0450, 0x44a53f93,
+  0x4450507e, 0x43fb3746, 0x43a5f41e, 0x4350873c, 0x42faf0d4, 0x42a5311b,
+  0x424f4845, 0x41f93689,
+  0x41a2fc1a, 0x414c992f, 0x40f60dfb, 0x409f5ab6, 0x40487f94, 0x3ff17cca,
+  0x3f9a5290, 0x3f430119,
+  0x3eeb889c, 0x3e93e950, 0x3e3c2369, 0x3de4371f, 0x3d8c24a8, 0x3d33ec39,
+  0x3cdb8e09, 0x3c830a50,
+  0x3c2a6142, 0x3bd19318, 0x3b78a007, 0x3b1f8848, 0x3ac64c0f, 0x3a6ceb96,
+  0x3a136712, 0x39b9bebc,
+  0x395ff2c9, 0x39060373, 0x38abf0ef, 0x3851bb77, 0x37f76341, 0x379ce885,
+  0x37424b7b, 0x36e78c5b,
+  0x368cab5c, 0x3631a8b8, 0x35d684a6, 0x357b3f5d, 0x351fd918, 0x34c4520d,
+  0x3468aa76, 0x340ce28b,
+  0x33b0fa84, 0x3354f29b, 0x32f8cb07, 0x329c8402, 0x32401dc6, 0x31e39889,
+  0x3186f487, 0x312a31f8,
+  0x30cd5115, 0x30705217, 0x30133539, 0x2fb5fab2, 0x2f58a2be, 0x2efb2d95,
+  0x2e9d9b70, 0x2e3fec8b,
+  0x2de2211e, 0x2d843964, 0x2d263596, 0x2cc815ee, 0x2c69daa6, 0x2c0b83fa,
+  0x2bad1221, 0x2b4e8558,
+  0x2aefddd8, 0x2a911bdc, 0x2a323f9e, 0x29d34958, 0x29743946, 0x29150fa1,
+  0x28b5cca5, 0x2856708d,
+  0x27f6fb92, 0x27976df1, 0x2737c7e3, 0x26d809a5, 0x26783370, 0x26184581,
+  0x25b84012, 0x2558235f,
+  0x24f7efa2, 0x2497a517, 0x243743fa, 0x23d6cc87, 0x23763ef7, 0x23159b88,
+  0x22b4e274, 0x225413f8,
+  0x21f3304f, 0x219237b5, 0x21312a65, 0x20d0089c, 0x206ed295, 0x200d888d,
+  0x1fac2abf, 0x1f4ab968,
+  0x1ee934c3, 0x1e879d0d, 0x1e25f282, 0x1dc4355e, 0x1d6265dd, 0x1d00843d,
+  0x1c9e90b8, 0x1c3c8b8c,
+  0x1bda74f6, 0x1b784d30, 0x1b161479, 0x1ab3cb0d, 0x1a517128, 0x19ef0707,
+  0x198c8ce7, 0x192a0304,
+  0x18c7699b, 0x1864c0ea, 0x1802092c, 0x179f429f, 0x173c6d80, 0x16d98a0c,
+  0x1676987f, 0x16139918,
+  0x15b08c12, 0x154d71aa, 0x14ea4a1f, 0x148715ae, 0x1423d492, 0x13c0870a,
+  0x135d2d53, 0x12f9c7aa,
+  0x1296564d, 0x1232d979, 0x11cf516a, 0x116bbe60, 0x11082096, 0x10a4784b,
+  0x1040c5bb, 0xfdd0926,
+  0xf7942c7, 0xf1572dc, 0xeb199a4, 0xe4db75b, 0xde9cc40, 0xd85d88f, 0xd21dc87,
+  0xcbdd865,
+  0xc59cc68, 0xbf5b8cb, 0xb919dcf, 0xb2d7baf, 0xac952aa, 0xa6522fe, 0xa00ece8,
+  0x99cb0a7,
+  0x9386e78, 0x8d42699, 0x86fd947, 0x80b86c2, 0x7a72f45, 0x742d311, 0x6de7262,
+  0x67a0d76,
+  0x615a48b, 0x5b137df, 0x54cc7b1, 0x4e8543e, 0x483ddc3, 0x41f6480, 0x3bae8b2,
+  0x3566a96,
+  0x2f1ea6c, 0x28d6870, 0x228e4e2, 0x1c45ffe, 0x15fda03, 0xfb5330, 0x96cbc1,
+  0x3243f5,
+};
+
+static const q31_t cos_factorsQ31_2048[2048] = {
+  0x7fffff62, 0x7ffffa73, 0x7ffff094, 0x7fffe1c6, 0x7fffce09, 0x7fffb55c,
+  0x7fff97c1, 0x7fff7536,
+  0x7fff4dbb, 0x7fff2151, 0x7ffeeff8, 0x7ffeb9b0, 0x7ffe7e79, 0x7ffe3e52,
+  0x7ffdf93c, 0x7ffdaf37,
+  0x7ffd6042, 0x7ffd0c5f, 0x7ffcb38c, 0x7ffc55ca, 0x7ffbf319, 0x7ffb8b78,
+  0x7ffb1ee9, 0x7ffaad6a,
+  0x7ffa36fc, 0x7ff9bba0, 0x7ff93b54, 0x7ff8b619, 0x7ff82bef, 0x7ff79cd6,
+  0x7ff708ce, 0x7ff66fd7,
+  0x7ff5d1f1, 0x7ff52f1d, 0x7ff48759, 0x7ff3daa6, 0x7ff32905, 0x7ff27275,
+  0x7ff1b6f6, 0x7ff0f688,
+  0x7ff0312c, 0x7fef66e1, 0x7fee97a7, 0x7fedc37e, 0x7fecea67, 0x7fec0c62,
+  0x7feb296d, 0x7fea418b,
+  0x7fe954ba, 0x7fe862fa, 0x7fe76c4c, 0x7fe670b0, 0x7fe57025, 0x7fe46aac,
+  0x7fe36045, 0x7fe250ef,
+  0x7fe13cac, 0x7fe0237a, 0x7fdf055a, 0x7fdde24d, 0x7fdcba51, 0x7fdb8d67,
+  0x7fda5b8f, 0x7fd924ca,
+  0x7fd7e917, 0x7fd6a875, 0x7fd562e7, 0x7fd4186a, 0x7fd2c900, 0x7fd174a8,
+  0x7fd01b63, 0x7fcebd31,
+  0x7fcd5a11, 0x7fcbf203, 0x7fca8508, 0x7fc91320, 0x7fc79c4b, 0x7fc62089,
+  0x7fc49fda, 0x7fc31a3d,
+  0x7fc18fb4, 0x7fc0003e, 0x7fbe6bdb, 0x7fbcd28b, 0x7fbb344e, 0x7fb99125,
+  0x7fb7e90f, 0x7fb63c0d,
+  0x7fb48a1e, 0x7fb2d343, 0x7fb1177b, 0x7faf56c7, 0x7fad9127, 0x7fabc69b,
+  0x7fa9f723, 0x7fa822bf,
+  0x7fa6496e, 0x7fa46b32, 0x7fa2880b, 0x7fa09ff7, 0x7f9eb2f8, 0x7f9cc10d,
+  0x7f9aca37, 0x7f98ce76,
+  0x7f96cdc9, 0x7f94c831, 0x7f92bdad, 0x7f90ae3f, 0x7f8e99e6, 0x7f8c80a1,
+  0x7f8a6272, 0x7f883f58,
+  0x7f861753, 0x7f83ea64, 0x7f81b88a, 0x7f7f81c6, 0x7f7d4617, 0x7f7b057e,
+  0x7f78bffb, 0x7f76758e,
+  0x7f742637, 0x7f71d1f6, 0x7f6f78cb, 0x7f6d1ab6, 0x7f6ab7b8, 0x7f684fd0,
+  0x7f65e2ff, 0x7f637144,
+  0x7f60faa0, 0x7f5e7f13, 0x7f5bfe9d, 0x7f59793e, 0x7f56eef5, 0x7f545fc5,
+  0x7f51cbab, 0x7f4f32a9,
+  0x7f4c94be, 0x7f49f1eb, 0x7f474a30, 0x7f449d8c, 0x7f41ec01, 0x7f3f358d,
+  0x7f3c7a31, 0x7f39b9ee,
+  0x7f36f4c3, 0x7f342ab1, 0x7f315bb7, 0x7f2e87d6, 0x7f2baf0d, 0x7f28d15d,
+  0x7f25eec7, 0x7f230749,
+  0x7f201ae5, 0x7f1d299a, 0x7f1a3368, 0x7f173850, 0x7f143852, 0x7f11336d,
+  0x7f0e29a3, 0x7f0b1af2,
+  0x7f08075c, 0x7f04eedf, 0x7f01d17d, 0x7efeaf36, 0x7efb8809, 0x7ef85bf7,
+  0x7ef52b00, 0x7ef1f524,
+  0x7eeeba62, 0x7eeb7abc, 0x7ee83632, 0x7ee4ecc3, 0x7ee19e6f, 0x7ede4b38,
+  0x7edaf31c, 0x7ed7961c,
+  0x7ed43438, 0x7ed0cd70, 0x7ecd61c5, 0x7ec9f137, 0x7ec67bc5, 0x7ec3016f,
+  0x7ebf8237, 0x7ebbfe1c,
+  0x7eb8751e, 0x7eb4e73d, 0x7eb1547a, 0x7eadbcd4, 0x7eaa204c, 0x7ea67ee2,
+  0x7ea2d896, 0x7e9f2d68,
+  0x7e9b7d58, 0x7e97c867, 0x7e940e94, 0x7e904fe0, 0x7e8c8c4b, 0x7e88c3d5,
+  0x7e84f67e, 0x7e812447,
+  0x7e7d4d2f, 0x7e797136, 0x7e75905d, 0x7e71aaa4, 0x7e6dc00c, 0x7e69d093,
+  0x7e65dc3b, 0x7e61e303,
+  0x7e5de4ec, 0x7e59e1f5, 0x7e55da20, 0x7e51cd6c, 0x7e4dbbd9, 0x7e49a567,
+  0x7e458a17, 0x7e4169e9,
+  0x7e3d44dd, 0x7e391af3, 0x7e34ec2b, 0x7e30b885, 0x7e2c8002, 0x7e2842a2,
+  0x7e240064, 0x7e1fb94a,
+  0x7e1b6d53, 0x7e171c7f, 0x7e12c6ce, 0x7e0e6c42, 0x7e0a0cd9, 0x7e05a894,
+  0x7e013f74, 0x7dfcd178,
+  0x7df85ea0, 0x7df3e6ee, 0x7def6a60, 0x7deae8f7, 0x7de662b3, 0x7de1d795,
+  0x7ddd479d, 0x7dd8b2ca,
+  0x7dd4191d, 0x7dcf7a96, 0x7dcad736, 0x7dc62efc, 0x7dc181e8, 0x7dbccffc,
+  0x7db81936, 0x7db35d98,
+  0x7dae9d21, 0x7da9d7d2, 0x7da50dab, 0x7da03eab, 0x7d9b6ad3, 0x7d969224,
+  0x7d91b49e, 0x7d8cd240,
+  0x7d87eb0a, 0x7d82fefe, 0x7d7e0e1c, 0x7d791862, 0x7d741dd2, 0x7d6f1e6c,
+  0x7d6a1a31, 0x7d65111f,
+  0x7d600338, 0x7d5af07b, 0x7d55d8e9, 0x7d50bc82, 0x7d4b9b46, 0x7d467536,
+  0x7d414a51, 0x7d3c1a98,
+  0x7d36e60b, 0x7d31acaa, 0x7d2c6e76, 0x7d272b6e, 0x7d21e393, 0x7d1c96e5,
+  0x7d174564, 0x7d11ef11,
+  0x7d0c93eb, 0x7d0733f3, 0x7d01cf29, 0x7cfc658d, 0x7cf6f720, 0x7cf183e1,
+  0x7cec0bd1, 0x7ce68ef0,
+  0x7ce10d3f, 0x7cdb86bd, 0x7cd5fb6a, 0x7cd06b48, 0x7ccad656, 0x7cc53c94,
+  0x7cbf9e03, 0x7cb9faa2,
+  0x7cb45272, 0x7caea574, 0x7ca8f3a7, 0x7ca33d0c, 0x7c9d81a3, 0x7c97c16b,
+  0x7c91fc66, 0x7c8c3294,
+  0x7c8663f4, 0x7c809088, 0x7c7ab84e, 0x7c74db48, 0x7c6ef976, 0x7c6912d7,
+  0x7c63276d, 0x7c5d3737,
+  0x7c574236, 0x7c514869, 0x7c4b49d2, 0x7c45466f, 0x7c3f3e42, 0x7c39314b,
+  0x7c331f8a, 0x7c2d08ff,
+  0x7c26edab, 0x7c20cd8d, 0x7c1aa8a6, 0x7c147ef6, 0x7c0e507e, 0x7c081d3d,
+  0x7c01e534, 0x7bfba863,
+  0x7bf566cb, 0x7bef206b, 0x7be8d544, 0x7be28556, 0x7bdc30a1, 0x7bd5d726,
+  0x7bcf78e5, 0x7bc915dd,
+  0x7bc2ae10, 0x7bbc417e, 0x7bb5d026, 0x7baf5a09, 0x7ba8df28, 0x7ba25f82,
+  0x7b9bdb18, 0x7b9551ea,
+  0x7b8ec3f8, 0x7b883143, 0x7b8199ca, 0x7b7afd8f, 0x7b745c91, 0x7b6db6d0,
+  0x7b670c4d, 0x7b605d09,
+  0x7b59a902, 0x7b52f03a, 0x7b4c32b1, 0x7b457068, 0x7b3ea95d, 0x7b37dd92,
+  0x7b310d07, 0x7b2a37bc,
+  0x7b235db2, 0x7b1c7ee8, 0x7b159b5f, 0x7b0eb318, 0x7b07c612, 0x7b00d44d,
+  0x7af9ddcb, 0x7af2e28b,
+  0x7aebe28d, 0x7ae4ddd2, 0x7addd45b, 0x7ad6c626, 0x7acfb336, 0x7ac89b89,
+  0x7ac17f20, 0x7aba5dfc,
+  0x7ab3381d, 0x7aac0d82, 0x7aa4de2d, 0x7a9daa1d, 0x7a967153, 0x7a8f33d0,
+  0x7a87f192, 0x7a80aa9c,
+  0x7a795eec, 0x7a720e84, 0x7a6ab963, 0x7a635f8a, 0x7a5c00f9, 0x7a549db0,
+  0x7a4d35b0, 0x7a45c8f9,
+  0x7a3e578b, 0x7a36e166, 0x7a2f668c, 0x7a27e6fb, 0x7a2062b5, 0x7a18d9b9,
+  0x7a114c09, 0x7a09b9a4,
+  0x7a02228a, 0x79fa86bc, 0x79f2e63a, 0x79eb4105, 0x79e3971c, 0x79dbe880,
+  0x79d43532, 0x79cc7d31,
+  0x79c4c07e, 0x79bcff19, 0x79b53903, 0x79ad6e3c, 0x79a59ec3, 0x799dca9a,
+  0x7995f1c1, 0x798e1438,
+  0x798631ff, 0x797e4b16, 0x79765f7f, 0x796e6f39, 0x79667a44, 0x795e80a1,
+  0x79568250, 0x794e7f52,
+  0x794677a6, 0x793e6b4e, 0x79365a49, 0x792e4497, 0x79262a3a, 0x791e0b31,
+  0x7915e77c, 0x790dbf1d,
+  0x79059212, 0x78fd605d, 0x78f529fe, 0x78eceef6, 0x78e4af44, 0x78dc6ae8,
+  0x78d421e4, 0x78cbd437,
+  0x78c381e2, 0x78bb2ae5, 0x78b2cf41, 0x78aa6ef5, 0x78a20a03, 0x7899a06a,
+  0x7891322a, 0x7888bf45,
+  0x788047ba, 0x7877cb89, 0x786f4ab4, 0x7866c53a, 0x785e3b1c, 0x7855ac5a,
+  0x784d18f4, 0x784480ea,
+  0x783be43e, 0x783342ef, 0x782a9cfe, 0x7821f26b, 0x78194336, 0x78108f60,
+  0x7807d6e9, 0x77ff19d1,
+  0x77f65819, 0x77ed91c0, 0x77e4c6c9, 0x77dbf732, 0x77d322fc, 0x77ca4a27,
+  0x77c16cb4, 0x77b88aa3,
+  0x77afa3f5, 0x77a6b8a9, 0x779dc8c0, 0x7794d43b, 0x778bdb19, 0x7782dd5c,
+  0x7779db03, 0x7770d40f,
+  0x7767c880, 0x775eb857, 0x7755a394, 0x774c8a36, 0x77436c40, 0x773a49b0,
+  0x77312287, 0x7727f6c6,
+  0x771ec66e, 0x7715917d, 0x770c57f5, 0x770319d6, 0x76f9d721, 0x76f08fd5,
+  0x76e743f4, 0x76ddf37c,
+  0x76d49e70, 0x76cb44cf, 0x76c1e699, 0x76b883d0, 0x76af1c72, 0x76a5b082,
+  0x769c3ffe, 0x7692cae8,
+  0x7689513f, 0x767fd304, 0x76765038, 0x766cc8db, 0x76633ced, 0x7659ac6f,
+  0x76501760, 0x76467dc2,
+  0x763cdf94, 0x76333cd8, 0x7629958c, 0x761fe9b3, 0x7616394c, 0x760c8457,
+  0x7602cad5, 0x75f90cc7,
+  0x75ef4a2c, 0x75e58305, 0x75dbb753, 0x75d1e715, 0x75c8124d, 0x75be38fa,
+  0x75b45b1d, 0x75aa78b6,
+  0x75a091c6, 0x7596a64d, 0x758cb64c, 0x7582c1c2, 0x7578c8b0, 0x756ecb18,
+  0x7564c8f8, 0x755ac251,
+  0x7550b725, 0x7546a772, 0x753c933a, 0x75327a7d, 0x75285d3b, 0x751e3b75,
+  0x7514152b, 0x7509ea5d,
+  0x74ffbb0d, 0x74f58739, 0x74eb4ee3, 0x74e1120c, 0x74d6d0b2, 0x74cc8ad8,
+  0x74c2407d, 0x74b7f1a1,
+  0x74ad9e46, 0x74a3466b, 0x7498ea11, 0x748e8938, 0x748423e0, 0x7479ba0b,
+  0x746f4bb8, 0x7464d8e8,
+  0x745a619b, 0x744fe5d2, 0x7445658d, 0x743ae0cc, 0x74305790, 0x7425c9da,
+  0x741b37a9, 0x7410a0fe,
+  0x740605d9, 0x73fb663c, 0x73f0c226, 0x73e61997, 0x73db6c91, 0x73d0bb13,
+  0x73c6051f, 0x73bb4ab3,
+  0x73b08bd1, 0x73a5c87a, 0x739b00ad, 0x7390346b, 0x738563b5, 0x737a8e8a,
+  0x736fb4ec, 0x7364d6da,
+  0x7359f456, 0x734f0d5f, 0x734421f6, 0x7339321b, 0x732e3dcf, 0x73234512,
+  0x731847e5, 0x730d4648,
+  0x7302403c, 0x72f735c0, 0x72ec26d6, 0x72e1137d, 0x72d5fbb7, 0x72cadf83,
+  0x72bfbee3, 0x72b499d6,
+  0x72a9705c, 0x729e4277, 0x72931027, 0x7287d96c, 0x727c9e47, 0x72715eb8,
+  0x72661abf, 0x725ad25d,
+  0x724f8593, 0x72443460, 0x7238dec5, 0x722d84c4, 0x7222265b, 0x7216c38c,
+  0x720b5c57, 0x71fff0bc,
+  0x71f480bc, 0x71e90c57, 0x71dd938f, 0x71d21662, 0x71c694d2, 0x71bb0edf,
+  0x71af848a, 0x71a3f5d2,
+  0x719862b9, 0x718ccb3f, 0x71812f65, 0x71758f29, 0x7169ea8f, 0x715e4194,
+  0x7152943b, 0x7146e284,
+  0x713b2c6e, 0x712f71fb, 0x7123b32b, 0x7117effe, 0x710c2875, 0x71005c90,
+  0x70f48c50, 0x70e8b7b5,
+  0x70dcdec0, 0x70d10171, 0x70c51fc8, 0x70b939c7, 0x70ad4f6d, 0x70a160ba,
+  0x70956db1, 0x70897650,
+  0x707d7a98, 0x70717a8a, 0x70657626, 0x70596d6d, 0x704d6060, 0x70414efd,
+  0x70353947, 0x70291f3e,
+  0x701d00e1, 0x7010de32, 0x7004b731, 0x6ff88bde, 0x6fec5c3b, 0x6fe02846,
+  0x6fd3f001, 0x6fc7b36d,
+  0x6fbb728a, 0x6faf2d57, 0x6fa2e3d7, 0x6f969608, 0x6f8a43ed, 0x6f7ded84,
+  0x6f7192cf, 0x6f6533ce,
+  0x6f58d082, 0x6f4c68eb, 0x6f3ffd09, 0x6f338cde, 0x6f271868, 0x6f1a9faa,
+  0x6f0e22a3, 0x6f01a155,
+  0x6ef51bbe, 0x6ee891e1, 0x6edc03bc, 0x6ecf7152, 0x6ec2daa2, 0x6eb63fad,
+  0x6ea9a073, 0x6e9cfcf5,
+  0x6e905534, 0x6e83a92f, 0x6e76f8e7, 0x6e6a445d, 0x6e5d8b91, 0x6e50ce84,
+  0x6e440d37, 0x6e3747a9,
+  0x6e2a7ddb, 0x6e1dafce, 0x6e10dd82, 0x6e0406f8, 0x6df72c30, 0x6dea4d2b,
+  0x6ddd69e9, 0x6dd0826a,
+  0x6dc396b0, 0x6db6a6ba, 0x6da9b28a, 0x6d9cba1f, 0x6d8fbd7a, 0x6d82bc9d,
+  0x6d75b786, 0x6d68ae37,
+  0x6d5ba0b0, 0x6d4e8ef2, 0x6d4178fd, 0x6d345ed1, 0x6d274070, 0x6d1a1dda,
+  0x6d0cf70f, 0x6cffcc0f,
+  0x6cf29cdc, 0x6ce56975, 0x6cd831dc, 0x6ccaf610, 0x6cbdb613, 0x6cb071e4,
+  0x6ca32985, 0x6c95dcf6,
+  0x6c888c36, 0x6c7b3748, 0x6c6dde2b, 0x6c6080e0, 0x6c531f67, 0x6c45b9c1,
+  0x6c384fef, 0x6c2ae1f0,
+  0x6c1d6fc6, 0x6c0ff971, 0x6c027ef1, 0x6bf50047, 0x6be77d74, 0x6bd9f677,
+  0x6bcc6b53, 0x6bbedc06,
+  0x6bb14892, 0x6ba3b0f7, 0x6b961536, 0x6b88754f, 0x6b7ad142, 0x6b6d2911,
+  0x6b5f7cbc, 0x6b51cc42,
+  0x6b4417a6, 0x6b365ee7, 0x6b28a206, 0x6b1ae103, 0x6b0d1bdf, 0x6aff529a,
+  0x6af18536, 0x6ae3b3b2,
+  0x6ad5de0f, 0x6ac8044e, 0x6aba266e, 0x6aac4472, 0x6a9e5e58, 0x6a907423,
+  0x6a8285d1, 0x6a749365,
+  0x6a669cdd, 0x6a58a23c, 0x6a4aa381, 0x6a3ca0ad, 0x6a2e99c0, 0x6a208ebb,
+  0x6a127f9f, 0x6a046c6c,
+  0x69f65523, 0x69e839c4, 0x69da1a50, 0x69cbf6c7, 0x69bdcf29, 0x69afa378,
+  0x69a173b5, 0x69933fde,
+  0x698507f6, 0x6976cbfc, 0x69688bf1, 0x695a47d6, 0x694bffab, 0x693db371,
+  0x692f6328, 0x69210ed1,
+  0x6912b66c, 0x690459fb, 0x68f5f97d, 0x68e794f3, 0x68d92c5d, 0x68cabfbd,
+  0x68bc4f13, 0x68adda5f,
+  0x689f61a1, 0x6890e4dc, 0x6882640e, 0x6873df38, 0x6865565c, 0x6856c979,
+  0x68483891, 0x6839a3a4,
+  0x682b0ab1, 0x681c6dbb, 0x680dccc1, 0x67ff27c4, 0x67f07ec5, 0x67e1d1c4,
+  0x67d320c1, 0x67c46bbe,
+  0x67b5b2bb, 0x67a6f5b8, 0x679834b6, 0x67896fb6, 0x677aa6b8, 0x676bd9bd,
+  0x675d08c4, 0x674e33d0,
+  0x673f5ae0, 0x67307df5, 0x67219d10, 0x6712b831, 0x6703cf58, 0x66f4e287,
+  0x66e5f1be, 0x66d6fcfd,
+  0x66c80445, 0x66b90797, 0x66aa06f3, 0x669b0259, 0x668bf9cb, 0x667ced49,
+  0x666ddcd3, 0x665ec86b,
+  0x664fb010, 0x664093c3, 0x66317385, 0x66224f56, 0x66132738, 0x6603fb2a,
+  0x65f4cb2d, 0x65e59742,
+  0x65d65f69, 0x65c723a3, 0x65b7e3f1, 0x65a8a052, 0x659958c9, 0x658a0d54,
+  0x657abdf6, 0x656b6aae,
+  0x655c137d, 0x654cb863, 0x653d5962, 0x652df679, 0x651e8faa, 0x650f24f5,
+  0x64ffb65b, 0x64f043dc,
+  0x64e0cd78, 0x64d15331, 0x64c1d507, 0x64b252fa, 0x64a2cd0c, 0x6493433c,
+  0x6483b58c, 0x647423fb,
+  0x64648e8c, 0x6454f53d, 0x64455810, 0x6435b706, 0x6426121e, 0x6416695a,
+  0x6406bcba, 0x63f70c3f,
+  0x63e757ea, 0x63d79fba, 0x63c7e3b1, 0x63b823cf, 0x63a86015, 0x63989884,
+  0x6388cd1b, 0x6378fddc,
+  0x63692ac7, 0x635953dd, 0x6349791f, 0x63399a8d, 0x6329b827, 0x6319d1ef,
+  0x6309e7e4, 0x62f9fa09,
+  0x62ea085c, 0x62da12df, 0x62ca1992, 0x62ba1c77, 0x62aa1b8d, 0x629a16d5,
+  0x628a0e50, 0x627a01fe,
+  0x6269f1e1, 0x6259ddf8, 0x6249c645, 0x6239aac7, 0x62298b81, 0x62196871,
+  0x62094199, 0x61f916f9,
+  0x61e8e893, 0x61d8b666, 0x61c88074, 0x61b846bc, 0x61a80940, 0x6197c800,
+  0x618782fd, 0x61773a37,
+  0x6166edb0, 0x61569d67, 0x6146495d, 0x6135f193, 0x6125960a, 0x611536c2,
+  0x6104d3bc, 0x60f46cf9,
+  0x60e40278, 0x60d3943b, 0x60c32243, 0x60b2ac8f, 0x60a23322, 0x6091b5fa,
+  0x60813519, 0x6070b080,
+  0x6060282f, 0x604f9c27, 0x603f0c69, 0x602e78f4, 0x601de1ca, 0x600d46ec,
+  0x5ffca859, 0x5fec0613,
+  0x5fdb601b, 0x5fcab670, 0x5fba0914, 0x5fa95807, 0x5f98a34a, 0x5f87eade,
+  0x5f772ec2, 0x5f666ef9,
+  0x5f55ab82, 0x5f44e45e, 0x5f34198e, 0x5f234b12, 0x5f1278eb, 0x5f01a31a,
+  0x5ef0c99f, 0x5edfec7b,
+  0x5ecf0baf, 0x5ebe273b, 0x5ead3f1f, 0x5e9c535e, 0x5e8b63f7, 0x5e7a70ea,
+  0x5e697a39, 0x5e587fe5,
+  0x5e4781ed, 0x5e368053, 0x5e257b17, 0x5e147239, 0x5e0365bb, 0x5df2559e,
+  0x5de141e1, 0x5dd02a85,
+  0x5dbf0f8c, 0x5dadf0f5, 0x5d9ccec2, 0x5d8ba8f3, 0x5d7a7f88, 0x5d695283,
+  0x5d5821e4, 0x5d46edac,
+  0x5d35b5db, 0x5d247a72, 0x5d133b72, 0x5d01f8dc, 0x5cf0b2af, 0x5cdf68ed,
+  0x5cce1b97, 0x5cbccaac,
+  0x5cab762f, 0x5c9a1e1e, 0x5c88c27c, 0x5c776348, 0x5c660084, 0x5c549a30,
+  0x5c43304d, 0x5c31c2db,
+  0x5c2051db, 0x5c0edd4e, 0x5bfd6534, 0x5bebe98e, 0x5bda6a5d, 0x5bc8e7a2,
+  0x5bb7615d, 0x5ba5d78e,
+  0x5b944a37, 0x5b82b958, 0x5b7124f2, 0x5b5f8d06, 0x5b4df193, 0x5b3c529c,
+  0x5b2ab020, 0x5b190a20,
+  0x5b07609d, 0x5af5b398, 0x5ae40311, 0x5ad24f09, 0x5ac09781, 0x5aaedc78,
+  0x5a9d1df1, 0x5a8b5bec,
+  0x5a799669, 0x5a67cd69, 0x5a5600ec, 0x5a4430f5, 0x5a325d82, 0x5a208695,
+  0x5a0eac2e, 0x59fcce4f,
+  0x59eaecf8, 0x59d90829, 0x59c71fe3, 0x59b53427, 0x59a344f6, 0x59915250,
+  0x597f5c36, 0x596d62a9,
+  0x595b65aa, 0x59496538, 0x59376155, 0x59255a02, 0x59134f3e, 0x5901410c,
+  0x58ef2f6b, 0x58dd1a5d,
+  0x58cb01e1, 0x58b8e5f9, 0x58a6c6a5, 0x5894a3e7, 0x58827dbe, 0x5870542c,
+  0x585e2730, 0x584bf6cd,
+  0x5839c302, 0x58278bd1, 0x58155139, 0x5803133c, 0x57f0d1da, 0x57de8d15,
+  0x57cc44ec, 0x57b9f960,
+  0x57a7aa73, 0x57955825, 0x57830276, 0x5770a968, 0x575e4cfa, 0x574bed2f,
+  0x57398a05, 0x5727237f,
+  0x5714b99d, 0x57024c5f, 0x56efdbc7, 0x56dd67d4, 0x56caf088, 0x56b875e4,
+  0x56a5f7e7, 0x56937694,
+  0x5680f1ea, 0x566e69ea, 0x565bde95, 0x56494fec, 0x5636bdef, 0x5624289f,
+  0x56118ffe, 0x55fef40a,
+  0x55ec54c6, 0x55d9b232, 0x55c70c4f, 0x55b4631d, 0x55a1b69d, 0x558f06d0,
+  0x557c53b6, 0x55699d51,
+  0x5556e3a1, 0x554426a7, 0x55316663, 0x551ea2d6, 0x550bdc01, 0x54f911e5,
+  0x54e64482, 0x54d373d9,
+  0x54c09feb, 0x54adc8b8, 0x549aee42, 0x54881089, 0x54752f8d, 0x54624b50,
+  0x544f63d2, 0x543c7914,
+  0x54298b17, 0x541699db, 0x5403a561, 0x53f0adaa, 0x53ddb2b6, 0x53cab486,
+  0x53b7b31c, 0x53a4ae77,
+  0x5391a699, 0x537e9b82, 0x536b8d33, 0x53587bad, 0x534566f0, 0x53324efd,
+  0x531f33d5, 0x530c1579,
+  0x52f8f3e9, 0x52e5cf27, 0x52d2a732, 0x52bf7c0b, 0x52ac4db4, 0x52991c2d,
+  0x5285e777, 0x5272af92,
+  0x525f7480, 0x524c3640, 0x5238f4d4, 0x5225b03d, 0x5212687b, 0x51ff1d8f,
+  0x51ebcf7a, 0x51d87e3c,
+  0x51c529d7, 0x51b1d24a, 0x519e7797, 0x518b19bf, 0x5177b8c2, 0x516454a0,
+  0x5150ed5c, 0x513d82f4,
+  0x512a156b, 0x5116a4c1, 0x510330f7, 0x50efba0d, 0x50dc4005, 0x50c8c2de,
+  0x50b5429a, 0x50a1bf39,
+  0x508e38bd, 0x507aaf25, 0x50672273, 0x505392a8, 0x503fffc4, 0x502c69c8,
+  0x5018d0b4, 0x5005348a,
+  0x4ff1954b, 0x4fddf2f6, 0x4fca4d8d, 0x4fb6a510, 0x4fa2f981, 0x4f8f4ae0,
+  0x4f7b992d, 0x4f67e46a,
+  0x4f542c98, 0x4f4071b6, 0x4f2cb3c7, 0x4f18f2c9, 0x4f052ec0, 0x4ef167aa,
+  0x4edd9d89, 0x4ec9d05e,
+  0x4eb60029, 0x4ea22ceb, 0x4e8e56a5, 0x4e7a7d58, 0x4e66a105, 0x4e52c1ab,
+  0x4e3edf4d, 0x4e2af9ea,
+  0x4e171184, 0x4e03261b, 0x4def37b0, 0x4ddb4644, 0x4dc751d8, 0x4db35a6c,
+  0x4d9f6001, 0x4d8b6298,
+  0x4d776231, 0x4d635ece, 0x4d4f5870, 0x4d3b4f16, 0x4d2742c2, 0x4d133374,
+  0x4cff212e, 0x4ceb0bf0,
+  0x4cd6f3bb, 0x4cc2d88f, 0x4caeba6e, 0x4c9a9958, 0x4c86754e, 0x4c724e50,
+  0x4c5e2460, 0x4c49f77f,
+  0x4c35c7ac, 0x4c2194e9, 0x4c0d5f37, 0x4bf92697, 0x4be4eb08, 0x4bd0ac8d,
+  0x4bbc6b25, 0x4ba826d1,
+  0x4b93df93, 0x4b7f956b, 0x4b6b485a, 0x4b56f861, 0x4b42a580, 0x4b2e4fb8,
+  0x4b19f70a, 0x4b059b77,
+  0x4af13d00, 0x4adcdba5, 0x4ac87767, 0x4ab41046, 0x4a9fa645, 0x4a8b3963,
+  0x4a76c9a2, 0x4a625701,
+  0x4a4de182, 0x4a396926, 0x4a24edee, 0x4a106fda, 0x49fbeeea, 0x49e76b21,
+  0x49d2e47e, 0x49be5b02,
+  0x49a9ceaf, 0x49953f84, 0x4980ad84, 0x496c18ae, 0x49578103, 0x4942e684,
+  0x492e4933, 0x4919a90f,
+  0x4905061a, 0x48f06054, 0x48dbb7be, 0x48c70c59, 0x48b25e25, 0x489dad25,
+  0x4888f957, 0x487442be,
+  0x485f8959, 0x484acd2a, 0x48360e32, 0x48214c71, 0x480c87e8, 0x47f7c099,
+  0x47e2f682, 0x47ce29a7,
+  0x47b95a06, 0x47a487a2, 0x478fb27b, 0x477ada91, 0x4765ffe6, 0x4751227a,
+  0x473c424e, 0x47275f63,
+  0x471279ba, 0x46fd9154, 0x46e8a631, 0x46d3b852, 0x46bec7b8, 0x46a9d464,
+  0x4694de56, 0x467fe590,
+  0x466aea12, 0x4655ebdd, 0x4640eaf2, 0x462be751, 0x4616e0fc, 0x4601d7f3,
+  0x45eccc37, 0x45d7bdc9,
+  0x45c2acaa, 0x45ad98da, 0x4598825a, 0x4583692c, 0x456e4d4f, 0x45592ec6,
+  0x45440d90, 0x452ee9ae,
+  0x4519c321, 0x450499eb, 0x44ef6e0b, 0x44da3f83, 0x44c50e53, 0x44afda7d,
+  0x449aa400, 0x44856adf,
+  0x44702f19, 0x445af0b0, 0x4445afa4, 0x44306bf6, 0x441b25a8, 0x4405dcb9,
+  0x43f0912b, 0x43db42fe,
+  0x43c5f234, 0x43b09ecc, 0x439b48c9, 0x4385f02a, 0x437094f1, 0x435b371f,
+  0x4345d6b3, 0x433073b0,
+  0x431b0e15, 0x4305a5e5, 0x42f03b1e, 0x42dacdc3, 0x42c55dd4, 0x42afeb53,
+  0x429a763f, 0x4284fe99,
+  0x426f8463, 0x425a079e, 0x42448849, 0x422f0667, 0x421981f7, 0x4203fafb,
+  0x41ee7174, 0x41d8e561,
+  0x41c356c5, 0x41adc5a0, 0x419831f3, 0x41829bbe, 0x416d0302, 0x415767c1,
+  0x4141c9fb, 0x412c29b1,
+  0x411686e4, 0x4100e194, 0x40eb39c3, 0x40d58f71, 0x40bfe29f, 0x40aa334e,
+  0x4094817f, 0x407ecd32,
+  0x40691669, 0x40535d24, 0x403da165, 0x4027e32b, 0x40122278, 0x3ffc5f4d,
+  0x3fe699aa, 0x3fd0d191,
+  0x3fbb0702, 0x3fa539fd, 0x3f8f6a85, 0x3f799899, 0x3f63c43b, 0x3f4ded6b,
+  0x3f38142a, 0x3f22387a,
+  0x3f0c5a5a, 0x3ef679cc, 0x3ee096d1, 0x3ecab169, 0x3eb4c995, 0x3e9edf57,
+  0x3e88f2ae, 0x3e73039d,
+  0x3e5d1222, 0x3e471e41, 0x3e3127f9, 0x3e1b2f4a, 0x3e053437, 0x3def36c0,
+  0x3dd936e6, 0x3dc334a9,
+  0x3dad300b, 0x3d97290b, 0x3d811fac, 0x3d6b13ee, 0x3d5505d2, 0x3d3ef559,
+  0x3d28e282, 0x3d12cd51,
+  0x3cfcb5c4, 0x3ce69bde, 0x3cd07f9f, 0x3cba6107, 0x3ca44018, 0x3c8e1cd3,
+  0x3c77f737, 0x3c61cf48,
+  0x3c4ba504, 0x3c35786d, 0x3c1f4983, 0x3c091849, 0x3bf2e4be, 0x3bdcaee3,
+  0x3bc676b9, 0x3bb03c42,
+  0x3b99ff7d, 0x3b83c06c, 0x3b6d7f10, 0x3b573b69, 0x3b40f579, 0x3b2aad3f,
+  0x3b1462be, 0x3afe15f6,
+  0x3ae7c6e7, 0x3ad17593, 0x3abb21fb, 0x3aa4cc1e, 0x3a8e7400, 0x3a78199f,
+  0x3a61bcfd, 0x3a4b5e1b,
+  0x3a34fcf9, 0x3a1e9999, 0x3a0833fc, 0x39f1cc21, 0x39db620b, 0x39c4f5ba,
+  0x39ae872f, 0x3998166a,
+  0x3981a36d, 0x396b2e38, 0x3954b6cd, 0x393e3d2c, 0x3927c155, 0x3911434b,
+  0x38fac30e, 0x38e4409e,
+  0x38cdbbfc, 0x38b7352a, 0x38a0ac29, 0x388a20f8, 0x38739399, 0x385d040d,
+  0x38467255, 0x382fde72,
+  0x38194864, 0x3802b02c, 0x37ec15cb, 0x37d57943, 0x37beda93, 0x37a839be,
+  0x379196c3, 0x377af1a3,
+  0x37644a60, 0x374da0fa, 0x3736f573, 0x372047ca, 0x37099802, 0x36f2e61a,
+  0x36dc3214, 0x36c57bf0,
+  0x36aec3b0, 0x36980954, 0x36814cde, 0x366a8e4d, 0x3653cda3, 0x363d0ae2,
+  0x36264609, 0x360f7f19,
+  0x35f8b614, 0x35e1eafa, 0x35cb1dcc, 0x35b44e8c, 0x359d7d39, 0x3586a9d5,
+  0x356fd461, 0x3558fcde,
+  0x3542234c, 0x352b47ad, 0x35146a00, 0x34fd8a48, 0x34e6a885, 0x34cfc4b7,
+  0x34b8dee1, 0x34a1f702,
+  0x348b0d1c, 0x3474212f, 0x345d333c, 0x34464345, 0x342f5149, 0x34185d4b,
+  0x3401674a, 0x33ea6f48,
+  0x33d37546, 0x33bc7944, 0x33a57b44, 0x338e7b46, 0x3377794b, 0x33607554,
+  0x33496f62, 0x33326776,
+  0x331b5d91, 0x330451b3, 0x32ed43de, 0x32d63412, 0x32bf2250, 0x32a80e99,
+  0x3290f8ef, 0x3279e151,
+  0x3262c7c1, 0x324bac40, 0x32348ecf, 0x321d6f6e, 0x32064e1e, 0x31ef2ae1,
+  0x31d805b7, 0x31c0dea1,
+  0x31a9b5a0, 0x31928ab4, 0x317b5de0, 0x31642f23, 0x314cfe7f, 0x3135cbf4,
+  0x311e9783, 0x3107612e,
+  0x30f028f4, 0x30d8eed8, 0x30c1b2da, 0x30aa74fa, 0x3093353a, 0x307bf39b,
+  0x3064b01d, 0x304d6ac1,
+  0x30362389, 0x301eda75, 0x30078f86, 0x2ff042bd, 0x2fd8f41b, 0x2fc1a3a0,
+  0x2faa514f, 0x2f92fd26,
+  0x2f7ba729, 0x2f644f56, 0x2f4cf5b0, 0x2f359a37, 0x2f1e3ced, 0x2f06ddd1,
+  0x2eef7ce5, 0x2ed81a29,
+  0x2ec0b5a0, 0x2ea94f49, 0x2e91e725, 0x2e7a7d36, 0x2e63117c, 0x2e4ba3f8,
+  0x2e3434ac, 0x2e1cc397,
+  0x2e0550bb, 0x2deddc19, 0x2dd665b2, 0x2dbeed86, 0x2da77397, 0x2d8ff7e5,
+  0x2d787a72, 0x2d60fb3e,
+  0x2d497a4a, 0x2d31f797, 0x2d1a7325, 0x2d02ecf7, 0x2ceb650d, 0x2cd3db67,
+  0x2cbc5006, 0x2ca4c2ed,
+  0x2c8d341a, 0x2c75a390, 0x2c5e114f, 0x2c467d58, 0x2c2ee7ad, 0x2c17504d,
+  0x2bffb73a, 0x2be81c74,
+  0x2bd07ffe, 0x2bb8e1d7, 0x2ba14200, 0x2b89a07b, 0x2b71fd48, 0x2b5a5868,
+  0x2b42b1dd, 0x2b2b09a6,
+  0x2b135fc6, 0x2afbb43c, 0x2ae4070a, 0x2acc5831, 0x2ab4a7b1, 0x2a9cf58c,
+  0x2a8541c3, 0x2a6d8c55,
+  0x2a55d545, 0x2a3e1c93, 0x2a266240, 0x2a0ea64d, 0x29f6e8bb, 0x29df298b,
+  0x29c768be, 0x29afa654,
+  0x2997e24f, 0x29801caf, 0x29685576, 0x29508ca4, 0x2938c23a, 0x2920f63a,
+  0x290928a3, 0x28f15978,
+  0x28d988b8, 0x28c1b666, 0x28a9e281, 0x28920d0a, 0x287a3604, 0x28625d6d,
+  0x284a8349, 0x2832a796,
+  0x281aca57, 0x2802eb8c, 0x27eb0b36, 0x27d32956, 0x27bb45ed, 0x27a360fc,
+  0x278b7a84, 0x27739285,
+  0x275ba901, 0x2743bdf9, 0x272bd16d, 0x2713e35f, 0x26fbf3ce, 0x26e402bd,
+  0x26cc102d, 0x26b41c1d,
+  0x269c268f, 0x26842f84, 0x266c36fe, 0x26543cfb, 0x263c417f, 0x26244489,
+  0x260c461b, 0x25f44635,
+  0x25dc44d9, 0x25c44207, 0x25ac3dc0, 0x25943806, 0x257c30d8, 0x25642839,
+  0x254c1e28, 0x253412a8,
+  0x251c05b8, 0x2503f75a, 0x24ebe78f, 0x24d3d657, 0x24bbc3b4, 0x24a3afa6,
+  0x248b9a2f, 0x2473834f,
+  0x245b6b07, 0x24435158, 0x242b3644, 0x241319ca, 0x23fafbec, 0x23e2dcac,
+  0x23cabc09, 0x23b29a05,
+  0x239a76a0, 0x238251dd, 0x236a2bba, 0x2352043b, 0x2339db5e, 0x2321b126,
+  0x23098593, 0x22f158a7,
+  0x22d92a61, 0x22c0fac4, 0x22a8c9cf, 0x22909785, 0x227863e5, 0x22602ef1,
+  0x2247f8aa, 0x222fc111,
+  0x22178826, 0x21ff4dea, 0x21e71260, 0x21ced586, 0x21b6975f, 0x219e57eb,
+  0x2186172b, 0x216dd521,
+  0x215591cc, 0x213d4d2f, 0x21250749, 0x210cc01d, 0x20f477aa, 0x20dc2df2,
+  0x20c3e2f5, 0x20ab96b5,
+  0x20934933, 0x207afa6f, 0x2062aa6b, 0x204a5927, 0x203206a4, 0x2019b2e4,
+  0x20015de7, 0x1fe907ae,
+  0x1fd0b03a, 0x1fb8578b, 0x1f9ffda4, 0x1f87a285, 0x1f6f462f, 0x1f56e8a2,
+  0x1f3e89e0, 0x1f2629ea,
+  0x1f0dc8c0, 0x1ef56664, 0x1edd02d6, 0x1ec49e17, 0x1eac3829, 0x1e93d10c,
+  0x1e7b68c2, 0x1e62ff4a,
+  0x1e4a94a7, 0x1e3228d9, 0x1e19bbe0, 0x1e014dbf, 0x1de8de75, 0x1dd06e04,
+  0x1db7fc6d, 0x1d9f89b1,
+  0x1d8715d0, 0x1d6ea0cc, 0x1d562aa6, 0x1d3db35e, 0x1d253af5, 0x1d0cc16c,
+  0x1cf446c5, 0x1cdbcb00,
+  0x1cc34e1f, 0x1caad021, 0x1c925109, 0x1c79d0d6, 0x1c614f8b, 0x1c48cd27,
+  0x1c3049ac, 0x1c17c51b,
+  0x1bff3f75, 0x1be6b8ba, 0x1bce30ec, 0x1bb5a80c, 0x1b9d1e1a, 0x1b849317,
+  0x1b6c0705, 0x1b5379e5,
+  0x1b3aebb6, 0x1b225c7b, 0x1b09cc34, 0x1af13ae3, 0x1ad8a887, 0x1ac01522,
+  0x1aa780b6, 0x1a8eeb42,
+  0x1a7654c8, 0x1a5dbd49, 0x1a4524c6, 0x1a2c8b3f, 0x1a13f0b6, 0x19fb552c,
+  0x19e2b8a2, 0x19ca1b17,
+  0x19b17c8f, 0x1998dd09, 0x19803c86, 0x19679b07, 0x194ef88e, 0x1936551b,
+  0x191db0af, 0x19050b4b,
+  0x18ec64f0, 0x18d3bda0, 0x18bb155a, 0x18a26c20, 0x1889c1f3, 0x187116d4,
+  0x18586ac3, 0x183fbdc3,
+  0x18270fd3, 0x180e60f4, 0x17f5b129, 0x17dd0070, 0x17c44ecd, 0x17ab9c3e,
+  0x1792e8c6, 0x177a3466,
+  0x17617f1d, 0x1748c8ee, 0x173011d9, 0x171759df, 0x16fea102, 0x16e5e741,
+  0x16cd2c9f, 0x16b4711b,
+  0x169bb4b7, 0x1682f774, 0x166a3953, 0x16517a55, 0x1638ba7a, 0x161ff9c4,
+  0x16073834, 0x15ee75cb,
+  0x15d5b288, 0x15bcee6f, 0x15a4297f, 0x158b63b9, 0x15729d1f, 0x1559d5b1,
+  0x15410d70, 0x1528445d,
+  0x150f7a7a, 0x14f6afc7, 0x14dde445, 0x14c517f4, 0x14ac4ad7, 0x14937cee,
+  0x147aae3a, 0x1461debc,
+  0x14490e74, 0x14303d65, 0x14176b8e, 0x13fe98f1, 0x13e5c58e, 0x13ccf167,
+  0x13b41c7d, 0x139b46d0,
+  0x13827062, 0x13699933, 0x1350c144, 0x1337e897, 0x131f0f2c, 0x13063505,
+  0x12ed5a21, 0x12d47e83,
+  0x12bba22b, 0x12a2c51b, 0x1289e752, 0x127108d2, 0x1258299c, 0x123f49b2,
+  0x12266913, 0x120d87c1,
+  0x11f4a5bd, 0x11dbc307, 0x11c2dfa2, 0x11a9fb8d, 0x119116c9, 0x11783159,
+  0x115f4b3c, 0x11466473,
+  0x112d7d00, 0x111494e4, 0x10fbac1e, 0x10e2c2b2, 0x10c9d89e, 0x10b0ede5,
+  0x10980287, 0x107f1686,
+  0x106629e1, 0x104d3c9b, 0x10344eb4, 0x101b602d, 0x10027107, 0xfe98143,
+  0xfd090e1, 0xfb79fe4,
+  0xf9eae4c, 0xf85bc19, 0xf6cc94e, 0xf53d5ea, 0xf3ae1ee, 0xf21ed5d, 0xf08f836,
+  0xef0027b,
+  0xed70c2c, 0xebe154b, 0xea51dd8, 0xe8c25d5, 0xe732d42, 0xe5a3421, 0xe413a72,
+  0xe284036,
+  0xe0f456f, 0xdf64a1c, 0xddd4e40, 0xdc451dc, 0xdab54ef, 0xd92577b, 0xd795982,
+  0xd605b03,
+  0xd475c00, 0xd2e5c7b, 0xd155c73, 0xcfc5bea, 0xce35ae1, 0xcca5959, 0xcb15752,
+  0xc9854cf,
+  0xc7f51cf, 0xc664e53, 0xc4d4a5d, 0xc3445ee, 0xc1b4107, 0xc023ba7, 0xbe935d2,
+  0xbd02f87,
+  0xbb728c7, 0xb9e2193, 0xb8519ed, 0xb6c11d5, 0xb53094d, 0xb3a0055, 0xb20f6ee,
+  0xb07ed19,
+  0xaeee2d7, 0xad5d829, 0xabccd11, 0xaa3c18e, 0xa8ab5a2, 0xa71a94f, 0xa589c94,
+  0xa3f8f73,
+  0xa2681ed, 0xa0d7403, 0x9f465b5, 0x9db5706, 0x9c247f5, 0x9a93884, 0x99028b3,
+  0x9771884,
+  0x95e07f8, 0x944f70f, 0x92be5ca, 0x912d42c, 0x8f9c233, 0x8e0afe2, 0x8c79d3a,
+  0x8ae8a3a,
+  0x89576e5, 0x87c633c, 0x8634f3e, 0x84a3aee, 0x831264c, 0x8181159, 0x7fefc16,
+  0x7e5e685,
+  0x7ccd0a5, 0x7b3ba78, 0x79aa400, 0x7818d3c, 0x768762e, 0x74f5ed7, 0x7364738,
+  0x71d2f52,
+  0x7041726, 0x6eafeb4, 0x6d1e5fe, 0x6b8cd05, 0x69fb3c9, 0x6869a4c, 0x66d808f,
+  0x6546692,
+  0x63b4c57, 0x62231de, 0x6091729, 0x5effc38, 0x5d6e10c, 0x5bdc5a7, 0x5a4aa09,
+  0x58b8e34,
+  0x5727228, 0x55955e6, 0x540396f, 0x5271cc4, 0x50dffe7, 0x4f4e2d8, 0x4dbc597,
+  0x4c2a827,
+  0x4a98a88, 0x4906cbb, 0x4774ec1, 0x45e309a, 0x4451249, 0x42bf3cd, 0x412d528,
+  0x3f9b65b,
+  0x3e09767, 0x3c7784d, 0x3ae590d, 0x39539a9, 0x37c1a22, 0x362fa78, 0x349daac,
+  0x330bac1,
+  0x3179ab5, 0x2fe7a8c, 0x2e55a44, 0x2cc39e1, 0x2b31961, 0x299f8c7, 0x280d813,
+  0x267b747,
+  0x24e9662, 0x2357567, 0x21c5457, 0x2033331, 0x1ea11f7, 0x1d0f0ab, 0x1b7cf4d,
+  0x19eaddd,
+  0x1858c5e, 0x16c6ad0, 0x1534934, 0x13a278a, 0x12105d5, 0x107e414, 0xeec249,
+  0xd5a075,
+  0xbc7e99, 0xa35cb5, 0x8a3acb, 0x7118dc, 0x57f6e9, 0x3ed4f2, 0x25b2f8,
+  0xc90fe,
+
+};
+
+/**   
+ * @brief  Initialization function for the Q31 DCT4/IDCT4.  
+ * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.  
+ * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure  
+ * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure  
+ * @param[in]     N          length of the DCT4.  
+ * @param[in]     Nby2       half of the length of the DCT4.  
+ * @param[in]     normalize  normalizing factor.  
+ * @return		  arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.  
+ * \par Normalizing factor:   
+ * The normalizing factor is sqrt(2/N), which depends on the size of transform N.   
+ * Normalizing factors in 1.31 format are mentioned in the table below for different DCT sizes:   
+ * \image html dct4NormalizingQ31Table.gif   
+ */
+
+arm_status arm_dct4_init_q31(
+  arm_dct4_instance_q31 * S,
+  arm_rfft_instance_q31 * S_RFFT,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint16_t N,
+  uint16_t Nby2,
+  q31_t normalize)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /* Initializing the pointer array with the weight table base addresses of different lengths */
+  q31_t *twiddlePtr[3] = { (q31_t *) WeightsQ31_128, (q31_t *) WeightsQ31_512,
+    (q31_t *) WeightsQ31_2048
+  };
+
+  /* Initializing the pointer array with the cos factor table base addresses of different lengths */
+  q31_t *pCosFactor[3] =
+    { (q31_t *) cos_factorsQ31_128, (q31_t *) cos_factorsQ31_512,
+    (q31_t *) cos_factorsQ31_2048
+  };
+
+  /* Initialize the DCT4 length */
+  S->N = N;
+
+  /* Initialize the half of DCT4 length */
+  S->Nby2 = Nby2;
+
+  /* Initialize the DCT4 Normalizing factor */
+  S->normalize = normalize;
+
+  /* Initialize Real FFT Instance */
+  S->pRfft = S_RFFT;
+
+  /* Initialize Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  switch (N)
+  {
+    /* Initialize the table modifier values */
+  case 2048u:
+    S->pTwiddle = twiddlePtr[2];
+    S->pCosFactor = pCosFactor[2];
+    break;
+  case 512u:
+    S->pTwiddle = twiddlePtr[1];
+    S->pCosFactor = pCosFactor[1];
+    break;
+  case 128u:
+    S->pTwiddle = twiddlePtr[0];
+    S->pCosFactor = pCosFactor[0];
+    break;
+  default:
+    status = ARM_MATH_ARGUMENT_ERROR;
+  }
+
+  /* Initialize the RFFT/RIFFT Function */
+  arm_rfft_init_q31(S->pRfft, S->pCfft, S->N, 0, 1);
+
+  /* return the status of DCT4 Init function */
+  return (status);
+}
+
+/**   
+   * @} end of DCT4_IDCT4 group   
+   */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c
new file mode 100644
index 0000000000..77bce95e66
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c
@@ -0,0 +1,383 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_dct4_q15.c   
+*   
+* Description:	Processing function of DCT4 & IDCT4 Q15.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @addtogroup DCT4_IDCT4   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 DCT4/IDCT4.  
+ * @param[in]       *S             points to an instance of the Q15 DCT4 structure.  
+ * @param[in]       *pState        points to state buffer.  
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.  
+ * @return none.  
+ *    
+ * \par Input an output formats:   
+ * Internally inputs are downscaled in the RFFT process function to avoid overflows.   
+ * Number of bits downscaled, depends on the size of the transform.   
+ * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:    
+ *   
+ * \image html dct4FormatsQ15Table.gif   
+ */
+
+void arm_dct4_q15(
+  const arm_dct4_instance_q15 * S,
+  q15_t * pState,
+  q15_t * pInlineBuffer)
+{
+  uint32_t i;                                    /* Loop counter */
+  q15_t *weights = S->pTwiddle;                  /* Pointer to the Weights table */
+  q15_t *cosFact = S->pCosFactor;                /* Pointer to the cos factors table */
+  q15_t *pS1, *pS2, *pbuff;                      /* Temporary pointers for input buffer and pState buffer */
+  q15_t in;                                      /* Temporary variable */
+
+
+  /* DCT4 computation involves DCT2 (which is calculated using RFFT)   
+   * along with some pre-processing and post-processing.   
+   * Computational procedure is explained as follows:   
+   * (a) Pre-processing involves multiplying input with cos factor,   
+   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))   
+   *              where,   
+   *                 r(n) -- output of preprocessing   
+   *                 u(n) -- input to preprocessing(actual Source buffer)   
+   * (b) Calculation of DCT2 using FFT is divided into three steps:   
+   *                  Step1: Re-ordering of even and odd elements of input.   
+   *                  Step2: Calculating FFT of the re-ordered input.   
+   *                  Step3: Taking the real part of the product of FFT output and weights.   
+   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:   
+   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *                        where,   
+   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output   
+   * (d) Multiplying the output with the normalizing factor sqrt(2/N).   
+   */
+
+        /*-------- Pre-processing ------------*/
+  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+  arm_mult_q15(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+  arm_shift_q15(pInlineBuffer, 1, pInlineBuffer, S->N);
+
+  /* ----------------------------------------------------------------   
+   * Step1: Re-ordering of even and odd elements as   
+   *             pState[i] =  pInlineBuffer[2*i] and   
+   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2   
+   ---------------------------------------------------------------------*/
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+  pS2 = pState + (S->N - 1u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+  i = (uint32_t) S->Nby2 >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2u;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.   
+   * Compute 4 outputs at a time */
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------   
+   *     Step2: Calculate RFFT for N-point input   
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------   
+  *  Step3: Multiply the FFT output with the weights.   
+  *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.13 format.   
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
+  arm_shift_q15(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,   
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+  i = ((uint32_t) S->N - 1u) >> 2u;
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1u;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  i = ((uint32_t) S->N - 1u) % 0x4u;
+
+  while(i > 0u)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+   /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = (uint32_t) S->N >> 2u;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initializing the loop counter to N/2 */
+  i = (uint32_t) S->Nby2;
+
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------   
+   *     Step2: Calculate RFFT for N-point input   
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q15(S->pRfft, pInlineBuffer, pState);
+
+ /*----------------------------------------------------------------------   
+  *  Step3: Multiply the FFT output with the weights.   
+  *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q15(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.13 format.   
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.15 format by shifting left by 2 bits. */
+  arm_shift_q15(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,   
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter */
+  i = ((uint32_t) S->N - 1u);
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1u;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+   /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter */
+  i = (uint32_t) S->N;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q15_t) (((q31_t) in * S->normalize) >> 15));
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of DCT4_IDCT4 group   
+   */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c
new file mode 100644
index 0000000000..f949d5ff45
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c
@@ -0,0 +1,384 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_dct4_q31.c   
+*   
+* Description:	Processing function of DCT4 & IDCT4 Q31.   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @addtogroup DCT4_IDCT4   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 DCT4/IDCT4.  
+ * @param[in]       *S             points to an instance of the Q31 DCT4 structure.  
+ * @param[in]       *pState        points to state buffer.  
+ * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.  
+ * @return none.  
+ * \par Input an output formats:   
+ * Input samples need to be downscaled by 1 bit to avoid saturations in the Q31 DCT process,   
+ * as the conversion from DCT2 to DCT4 involves one subtraction.   
+ * Internally inputs are downscaled in the RFFT process function to avoid overflows.   
+ * Number of bits downscaled, depends on the size of the transform.   
+ * The input and output formats for different DCT sizes and number of bits to upscale are mentioned in the table below:    
+ *   
+ * \image html dct4FormatsQ31Table.gif   
+ */
+
+void arm_dct4_q31(
+  const arm_dct4_instance_q31 * S,
+  q31_t * pState,
+  q31_t * pInlineBuffer)
+{
+  uint16_t i;                                    /* Loop counter */
+  q31_t *weights = S->pTwiddle;                  /* Pointer to the Weights table */
+  q31_t *cosFact = S->pCosFactor;                /* Pointer to the cos factors table */
+  q31_t *pS1, *pS2, *pbuff;                      /* Temporary pointers for input buffer and pState buffer */
+  q31_t in;                                      /* Temporary variable */
+
+
+  /* DCT4 computation involves DCT2 (which is calculated using RFFT)   
+   * along with some pre-processing and post-processing.   
+   * Computational procedure is explained as follows:   
+   * (a) Pre-processing involves multiplying input with cos factor,   
+   *     r(n) = 2 * u(n) * cos(pi*(2*n+1)/(4*n))   
+   *              where,   
+   *                 r(n) -- output of preprocessing   
+   *                 u(n) -- input to preprocessing(actual Source buffer)   
+   * (b) Calculation of DCT2 using FFT is divided into three steps:   
+   *                  Step1: Re-ordering of even and odd elements of input.   
+   *                  Step2: Calculating FFT of the re-ordered input.   
+   *                  Step3: Taking the real part of the product of FFT output and weights.   
+   * (c) Post-processing - DCT4 can be obtained from DCT2 output using the following equation:   
+   *                   Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *                        where,   
+   *                           Y4 -- DCT4 output,   Y2 -- DCT2 output   
+   * (d) Multiplying the output with the normalizing factor sqrt(2/N).   
+   */
+
+        /*-------- Pre-processing ------------*/
+  /* Multiplying input with cos factor i.e. r(n) = 2 * x(n) * cos(pi*(2*n+1)/(4*n)) */
+  arm_mult_q31(pInlineBuffer, cosFact, pInlineBuffer, S->N);
+  arm_shift_q31(pInlineBuffer, 1, pInlineBuffer, S->N);
+
+  /* ----------------------------------------------------------------   
+   * Step1: Re-ordering of even and odd elements as   
+   *             pState[i] =  pInlineBuffer[2*i] and   
+   *             pState[N-i-1] = pInlineBuffer[2*i+1] where i = 0 to N/2   
+   ---------------------------------------------------------------------*/
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* pS2 initialized to pState+N-1, so that it points to the end of the state buffer */
+  pS2 = pState + (S->N - 1u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  /* Initializing the loop counter to N/2 >> 2 for loop unrolling by 4 */
+  i = S->Nby2 >> 2u;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    *pS1++ = *pbuff++;
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = S->N >> 2u;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.   
+   * Compute 4 outputs at a time */
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------   
+   *     Step2: Calculate RFFT for N-point input   
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
+
+  /*----------------------------------------------------------------------   
+   *  Step3: Multiply the FFT output with the weights.   
+   *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.29 format.   
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
+  arm_shift_q31(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,   
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* Initializing the loop counter to N >> 2 for loop unrolling by 4 */
+  i = (S->N - 1u) >> 2u;
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1u;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* First part of the processing with loop unrolling.  Compute 4 outputs at a time.   
+   ** a second loop below computes the remaining 1 to 3 samples. */
+  do
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* If the blockSize is not a multiple of 4, compute any remaining output samples here.   
+   ** No loop unrolling is used. */
+  i = (S->N - 1u) % 0x4u;
+
+  while(i > 0u)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter to N/4 instead of N for loop unrolling */
+  i = S->N >> 2u;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  /* Processing with loop unrolling 4 times as N is always multiple of 4.  Compute 4 outputs at a time */
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  /* Initializing the loop counter to N/2 */
+  i = S->Nby2;
+
+  do
+  {
+    /* Re-ordering of even and odd elements */
+    /* pState[i] =  pInlineBuffer[2*i] */
+    *pS1++ = *pbuff++;
+    /* pState[N-i-1] = pInlineBuffer[2*i+1] */
+    *pS2-- = *pbuff++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+  /* pbuff initialized to input buffer */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Initializing the loop counter */
+  i = S->N;
+
+  do
+  {
+    /* Writing the re-ordered output back to inplace input buffer */
+    *pbuff++ = *pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+
+  /* ---------------------------------------------------------   
+   *     Step2: Calculate RFFT for N-point input   
+   * ---------------------------------------------------------- */
+  /* pInlineBuffer is real input of length N , pState is the complex output of length 2N */
+  arm_rfft_q31(S->pRfft, pInlineBuffer, pState);
+
+  /*----------------------------------------------------------------------   
+   *  Step3: Multiply the FFT output with the weights.   
+   *----------------------------------------------------------------------*/
+  arm_cmplx_mult_cmplx_q31(pState, weights, pState, S->N);
+
+  /* The output of complex multiplication is in 3.29 format.   
+   * Hence changing the format of N (i.e. 2*N elements) complex numbers to 1.31 format by shifting left by 2 bits. */
+  arm_shift_q31(pState, 2, pState, S->N * 2);
+
+  /* ----------- Post-processing ---------- */
+  /* DCT-IV can be obtained from DCT-II by the equation,   
+   *       Y4(k) = Y2(k) - Y4(k-1) and Y4(-1) = Y4(0)   
+   *       Hence, Y4(0) = Y2(0)/2  */
+  /* Getting only real part from the output and Converting to DCT-IV */
+
+  /* pbuff initialized to input buffer. */
+  pbuff = pInlineBuffer;
+
+  /* pS1 initialized to pState */
+  pS1 = pState;
+
+  /* Calculating Y4(0) from Y2(0) using Y4(0) = Y2(0)/2 */
+  in = *pS1++ >> 1u;
+  /* input buffer acts as inplace, so output values are stored in the input itself. */
+  *pbuff++ = in;
+
+  /* pState pointer is incremented twice as the real values are located alternatively in the array */
+  pS1++;
+
+  /* Initializing the loop counter */
+  i = (S->N - 1u);
+
+  while(i > 0u)
+  {
+    /* Calculating Y4(1) to Y4(N-1) from Y2 using equation Y4(k) = Y2(k) - Y4(k-1) */
+    /* pState pointer (pS1) is incremented twice as the real values are located alternatively in the array */
+    in = *pS1++ - in;
+    *pbuff++ = in;
+    /* points to the next real value */
+    pS1++;
+
+    /* Decrement the loop counter */
+    i--;
+  }
+
+
+        /*------------ Normalizing the output by multiplying with the normalizing factor ----------*/
+
+  /* Initializing the loop counter */
+  i = S->N;
+
+  /* pbuff initialized to the pInlineBuffer(now contains the output values) */
+  pbuff = pInlineBuffer;
+
+  do
+  {
+    /* Multiplying pInlineBuffer with the normalizing factor sqrt(2/N) */
+    in = *pbuff;
+    *pbuff++ = ((q31_t) (((q63_t) in * S->normalize) >> 31));
+
+    /* Decrement the loop counter */
+    i--;
+  } while(i > 0u);
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+/**   
+   * @} end of DCT4_IDCT4 group   
+   */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c
new file mode 100644
index 0000000000..dd91aacc35
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c
@@ -0,0 +1,383 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_rfft_f32.c   
+*   
+* Description:	RFFT & RIFFT Floating point process function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @defgroup RFFT_RIFFT Real FFT Functions   
+ *   
+ * \par   
+ * Complex FFT/IFFT typically assumes complex input and output. However many applications use real valued data in time domain.    
+ * Real FFT/IFFT efficiently process real valued sequences with the advantage of requirement of low memory and with less complexity.   
+ *   
+ * \par   
+ * This set of functions implements Real Fast Fourier Transforms(RFFT) and Real Inverse Fast Fourier Transform(RIFFT)   
+ * for Q15, Q31, and floating-point data types.     
+ *   
+ *   
+ * \par Algorithm:   
+ *   
+ * Real Fast Fourier Transform:   
+ * \par   
+ * Real FFT of N-point is calculated using CFFT of N/2-point and Split RFFT process as shown below figure.   
+ * \par   
+ * \image html RFFT.gif "Real Fast Fourier Transform"   
+ * \par   
+ * The RFFT functions operate on blocks of input and output data and each call to the function processes   
+ * fftLenR samples through the transform.  pSrc  points to input array containing fftLenR values.   
+ * pDst  points to output array containing 2*fftLenR values. \n  
+ * Input for real FFT is in the order of    
+ * 
    {real[0], real[1], real[2], real[3], ..}
       
+ * Output for real FFT is complex and are in the order of   
+ * 
    {real(0), imag(0), real(1), imag(1), ...}
        
+ *   
+ * Real Inverse Fast Fourier Transform:   
+ * \par   
+ * Real IFFT of N-point is calculated using Split RIFFT process and CFFT of N/2-point as shown below figure.   
+ * \par   
+ * \image html RIFFT.gif "Real Inverse Fast Fourier Transform"   
+ * \par   
+ * The RIFFT functions operate on blocks of input and output data and each call to the function processes   
+ * 2*fftLenR samples through the transform.  pSrc  points to input array containing 2*fftLenR values.   
+ * pDst  points to output array containing fftLenR values. \n   
+ * Input for real IFFT is complex and are in the order of  
+ * 
    {real(0), imag(0), real(1), imag(1), ...}
      
+ *  Output for real IFFT is real and in the order of    
+ * 
    {real[0], real[1], real[2], real[3], ..}
      
+ *   
+ * \par Lengths supported by the transform:  
+ * \par   
+ * Real FFT/IFFT supports the lengths [128, 512, 2048], as it internally uses CFFT/CIFFT.   
+ *   
+ * \par Instance Structure   
+ * A separate instance structure must be defined for each Instance but the twiddle factors can be reused.   
+ * There are separate instance structure declarations for each of the 3 supported data types.   
+ *   
+ * \par Initialization Functions   
+ * There is also an associated initialization function for each data type.   
+ * The initialization function performs the following operations:   
+ * - Sets the values of the internal structure fields.   
+ * - Initializes twiddle factor tables.  
+ * - Initializes CFFT data structure fields.    
+ * \par   
+ * Use of the initialization function is optional.   
+ * However, if the initialization function is used, then the instance structure cannot be placed into a const data section.   
+ * To place an instance structure into a const data section, the instance structure must be manually initialized.   
+ * Manually initialize the instance structure as follows:   
+ * 
       
+ *arm_rfft_instance_f32 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};   
+ *arm_rfft_instance_q31 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};   
+ *arm_rfft_instance_q15 S = {fftLenReal, fftLenBy2, ifftFlagR, bitReverseFlagR, twidCoefRModifier, pTwiddleAReal, pTwiddleBReal, pCfft};   
+ * 
       
+ * where fftLenReal length of RFFT/RIFFT; fftLenBy2 length of CFFT/CIFFT.    
+ * ifftFlagR Flag for selection of RFFT or RIFFT(Set ifftFlagR to calculate RIFFT otherwise calculates RFFT);   
+ * bitReverseFlagR Flag for selection of output order(Set bitReverseFlagR to output in normal order otherwise output in bit reversed order);    
+ * twidCoefRModifier modifier for twiddle factor table which supports 128, 512, 2048 RFFT lengths with same table;   
+ * pTwiddleARealpoints to A array of twiddle coefficients; pTwiddleBRealpoints to B array of twiddle coefficients;   
+ * pCfft points to the CFFT Instance structure. The CFFT structure also needs to be initialized, refer to arm_cfft_radix4_f32() for details regarding   
+ * static initialization of cfft structure.   
+ *   
+ * \par Fixed-Point Behavior   
+ * Care must be taken when using the fixed-point versions of the RFFT/RIFFT function.   
+ * Refer to the function specific documentation below for usage guidelines.   
+ */
+
+/*--------------------------------------------------------------------   
+ *		Internal functions prototypes   
+ *--------------------------------------------------------------------*/
+
+void arm_split_rfft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier);
+void arm_split_rifft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier);
+
+/**   
+ * @addtogroup RFFT_RIFFT   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the floating-point RFFT/RIFFT.  
+ * @param[in]  *S    points to an instance of the floating-point RFFT/RIFFT structure.  
+ * @param[in]  *pSrc points to the input buffer.  
+ * @param[out] *pDst points to the output buffer.  
+ * @return none.  
+ */
+
+void arm_rfft_f32(
+  const arm_rfft_instance_f32 * S,
+  float32_t * pSrc,
+  float32_t * pDst)
+{
+  const arm_cfft_radix4_instance_f32 *S_CFFT = S->pCfft;
+
+
+  /* Calculation of Real IFFT of input */
+  if(S->ifftFlagR == 1u)
+  {
+    /*  Real IFFT core process */
+    arm_split_rifft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+
+    /* Complex radix-4 IFFT process */
+    arm_radix4_butterfly_inverse_f32(pDst, S_CFFT->fftLen,
+                                     S_CFFT->pTwiddle,
+                                     S_CFFT->twidCoefModifier,
+                                     S_CFFT->onebyfftLen);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_f32(pDst, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+  }
+  else
+  {
+
+    /* Calculation of RFFT of input */
+
+    /* Complex radix-4 FFT process */
+    arm_radix4_butterfly_f32(pSrc, S_CFFT->fftLen,
+                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_f32(pSrc, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+
+
+    /*  Real FFT core process */
+    arm_split_rfft_f32(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+  }
+
+}
+
+/**   
+   * @} end of RFFT_RIFFT group   
+   */
+
+/**   
+ * @brief  Core Real FFT process   
+ * @param[in]   *pSrc 				points to the input buffer.   
+ * @param[in]   fftLen  			length of FFT.   
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.   
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.   
+ * @param[out]  *pDst 				points to the output buffer.   
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.   
+ */
+
+void arm_split_rfft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier)
+{
+  uint32_t i;                                    /* Loop Counter */
+  float32_t outR, outI;                          /* Temporary variables for output */
+  float32_t *pCoefA, *pCoefB;                    /* Temporary pointers for twiddle factors */
+  float32_t CoefA1, CoefA2, CoefB1;              /* Temporary variables for twiddle coefficients */
+  float32_t *pDst1 = &pDst[2], *pDst2 = &pDst[(4u * fftLen) - 1u];      /* temp pointers for output buffer */
+  float32_t *pSrc1 = &pSrc[2], *pSrc2 = &pSrc[(2u * fftLen) - 1u];      /* temp pointers for input buffer */
+
+
+  pSrc[2u * fftLen] = pSrc[0];
+  pSrc[(2u * fftLen) + 1u] = pSrc[1];
+
+  /* Init coefficient pointers */
+  pCoefA = &pATable[modifier * 2u];
+  pCoefB = &pBTable[modifier * 2u];
+
+  i = fftLen - 1u;
+
+  while(i > 0u)
+  {
+    /*   
+       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]   
+       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +   
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+     */
+
+    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+    /* read pATable[2 * i] */
+    CoefA1 = *pCoefA++;
+    /* pATable[2 * i + 1] */
+    CoefA2 = *pCoefA;
+
+    /* pSrc[2 * i] * pATable[2 * i] */
+    outR = *pSrc1 * CoefA1;
+    /* pSrc[2 * i] * CoefA2 */
+    outI = *pSrc1++ * CoefA2;
+
+    /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
+    outR -= (*pSrc1 + *pSrc2) * CoefA2;
+    /* pSrc[2 * i + 1] * CoefA1 */
+    outI += *pSrc1++ * CoefA1;
+
+    CoefB1 = *pCoefB;
+
+    /* pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
+    outI -= *pSrc2-- * CoefB1;
+    /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
+    outI -= *pSrc2 * CoefA2;
+
+    /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
+    outR += *pSrc2-- * CoefB1;
+
+    /* write output */
+    *pDst1++ = outR;
+    *pDst1++ = outI;
+
+    /* write complex conjugate output */
+    *pDst2-- = -outI;
+    *pDst2-- = outR;
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (modifier * 2u);
+    pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+    i--;
+
+  }
+
+  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+  pDst[(2u * fftLen) + 1u] = 0.0f;
+
+  pDst[0] = pSrc[0] + pSrc[1];
+  pDst[1] = 0.0f;
+
+}
+
+
+/**   
+ * @brief  Core Real IFFT process   
+ * @param[in]   *pSrc 				points to the input buffer.   
+ * @param[in]   fftLen  			length of FFT.  
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.  
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.  
+ * @param[out]  *pDst 				points to the output buffer.  
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.   
+ * @return none.   
+ */
+
+void arm_split_rifft_f32(
+  float32_t * pSrc,
+  uint32_t fftLen,
+  float32_t * pATable,
+  float32_t * pBTable,
+  float32_t * pDst,
+  uint32_t modifier)
+{
+  float32_t outR, outI;                          /* Temporary variables for output */
+  float32_t *pCoefA, *pCoefB;                    /* Temporary pointers for twiddle factors */
+  float32_t CoefA1, CoefA2, CoefB1;              /* Temporary variables for twiddle coefficients */
+  float32_t *pSrc1 = &pSrc[0], *pSrc2 = &pSrc[(2u * fftLen) + 1u];
+
+  pCoefA = &pATable[0];
+  pCoefB = &pBTable[0];
+
+  while(fftLen > 0u)
+  {
+    /*   
+       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+
+       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   
+
+     */
+
+    CoefA1 = *pCoefA++;
+    CoefA2 = *pCoefA;
+
+    /* outR = (pSrc[2 * i] * CoefA1 */
+    outR = *pSrc1 * CoefA1;
+
+    /* - pSrc[2 * i] * CoefA2 */
+    outI = -(*pSrc1++) * CoefA2;
+
+    /* (pSrc[2 * i + 1] + pSrc[2 * fftLen - 2 * i + 1]) * CoefA2 */
+    outR += (*pSrc1 + *pSrc2) * CoefA2;
+
+    /* pSrc[2 * i + 1] * CoefA1 */
+    outI += (*pSrc1++) * CoefA1;
+
+    CoefB1 = *pCoefB;
+
+    /* - pSrc[2 * fftLen - 2 * i + 1] * CoefB1 */
+    outI -= *pSrc2-- * CoefB1;
+
+    /* pSrc[2 * fftLen - 2 * i] * CoefB1 */
+    outR += *pSrc2 * CoefB1;
+
+    /* pSrc[2 * fftLen - 2 * i] * CoefA2 */
+    outI += *pSrc2-- * CoefA2;
+
+    /* write output */
+    *pDst++ = outR;
+    *pDst++ = outI;
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (modifier * 2u);
+    pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+    /* Decrement loop count */
+    fftLen--;
+  }
+
+}
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c
new file mode 100644
index 0000000000..c144cbea96
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c
@@ -0,0 +1,1707 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_rfft_init_f32.c   
+*   
+* Description:	RFFT & RIFFT Floating point initialisation function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup RFFT_RIFFT   
+ * @{   
+ */
+
+/**   
+* \par   
+* Generation of realCoefA array:   
+* \par   
+* 	n = 1024   
+* 
    for (i = 0; i < n; i++)   
+*  {   
+*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));   
+*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+*  } 
       
+*/
+
+
+
+static const float32_t realCoefA[2048] = {
+  0.500000000000000000f, -0.500000000000000000f, 0.498466014862060550f,
+  -0.499997645616531370f, 0.496932059526443480f, -0.499990582466125490f,
+  0.495398133993148800f, -0.499978810548782350f,
+  0.493864238262176510f, -0.499962359666824340f, 0.492330402135849000f,
+  -0.499941170215606690f, 0.490796625614166260f, -0.499915301799774170f,
+  0.489262968301773070f, -0.499884694814682010f,
+  0.487729400396347050f, -0.499849408864974980f, 0.486195921897888180f,
+  -0.499809414148330690f, 0.484662592411041260f, -0.499764710664749150f,
+  0.483129411935806270f, -0.499715298414230350f,
+  0.481596380472183230f, -0.499661177396774290f, 0.480063527822494510f,
+  -0.499602377414703370f, 0.478530883789062500f, -0.499538868665695190f,
+  0.476998418569564820f, -0.499470651149749760f,
+  0.475466161966323850f, -0.499397724866867070f, 0.473934143781661990f,
+  -0.499320119619369510f, 0.472402364015579220f, -0.499237775802612300f,
+  0.470870882272720340f, -0.499150782823562620f,
+  0.469339638948440550f, -0.499059051275253300f, 0.467808693647384640f,
+  -0.498962640762329100f, 0.466278046369552610f, -0.498861521482467650f,
+  0.464747726917266850f, -0.498755723237991330f,
+  0.463217705488204960f, -0.498645216226577760f, 0.461688071489334110f,
+  -0.498530030250549320f, 0.460158795118331910f, -0.498410135507583620f,
+  0.458629876375198360f, -0.498285561800003050f,
+  0.457101345062255860f, -0.498156309127807620f, 0.455573230981826780f,
+  -0.498022347688674930f, 0.454045534133911130f, -0.497883707284927370f,
+  0.452518254518508910f, -0.497740387916564940f,
+  0.450991421937942500f, -0.497592359781265260f, 0.449465066194534300f,
+  -0.497439652681350710f, 0.447939187288284300f, -0.497282296419143680f,
+  0.446413785219192500f, -0.497120231389999390f,
+  0.444888889789581300f, -0.496953487396240230f, 0.443364530801773070f,
+  -0.496782064437866210f, 0.441840678453445430f, -0.496605962514877320f,
+  0.440317392349243160f, -0.496425211429595950f,
+  0.438794672489166260f, -0.496239781379699710f, 0.437272518873214720f,
+  -0.496049642562866210f, 0.435750931501388550f, -0.495854884386062620f,
+  0.434229999780654910f, -0.495655417442321780f,
+  0.432709634304046630f, -0.495451331138610840f, 0.431189924478530880f,
+  -0.495242536067962650f, 0.429670870304107670f, -0.495029091835021970f,
+  0.428152471780776980f, -0.494810998439788820f,
+  0.426634758710861210f, -0.494588255882263180f, 0.425117731094360350f,
+  -0.494360834360122680f, 0.423601418733596800f, -0.494128793478012080f,
+  0.422085791826248170f, -0.493892073631286620f,
+  0.420570939779281620f, -0.493650704622268680f, 0.419056802988052370f,
+  -0.493404686450958250f, 0.417543441057205200f, -0.493154048919677730f,
+  0.416030853986740110f, -0.492898762226104740f,
+  0.414519041776657100f, -0.492638826370239260f, 0.413008064031600950f,
+  -0.492374241352081300f, 0.411497890949249270f, -0.492105036973953250f,
+  0.409988552331924440f, -0.491831213235855100f,
+  0.408480048179626460f, -0.491552740335464480f, 0.406972438097000120f,
+  -0.491269648075103760f, 0.405465662479400630f, -0.490981936454772950f,
+  0.403959810733795170f, -0.490689605474472050f,
+  0.402454853057861330f, -0.490392625331878660f, 0.400950789451599120f,
+  -0.490091055631637570f, 0.399447679519653320f, -0.489784896373748780f,
+  0.397945523262023930f, -0.489474087953567500f,
+  0.396444320678710940f, -0.489158689975738530f, 0.394944071769714360f,
+  -0.488838672637939450f, 0.393444836139678960f, -0.488514065742492680f,
+  0.391946613788604740f, -0.488184869289398190f,
+  0.390449374914169310f, -0.487851053476333620f, 0.388953179121017460f,
+  -0.487512677907943730f, 0.387458056211471560f, -0.487169682979583740f,
+  0.385963946580886840f, -0.486822128295898440f,
+  0.384470939636230470f, -0.486469984054565430f, 0.382979035377502440f,
+  -0.486113250255584720f, 0.381488204002380370f, -0.485751956701278690f,
+  0.379998475313186650f, -0.485386073589324950f,
+  0.378509908914566040f, -0.485015630722045900f, 0.377022475004196170f,
+  -0.484640628099441530f, 0.375536203384399410f, -0.484261035919189450f,
+  0.374051094055175780f, -0.483876913785934450f,
+  0.372567176818847660f, -0.483488231897354130f, 0.371084451675415040f,
+  -0.483094990253448490f, 0.369602948427200320f, -0.482697218656539920f,
+  0.368122667074203490f, -0.482294887304306030f,
+  0.366643607616424560f, -0.481888025999069210f, 0.365165829658508300f,
+  -0.481476634740829470f, 0.363689333200454710f, -0.481060713529586790f,
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+  0.461688071489334110f, 0.498530030250549320f,
+  0.463217705488204960f, 0.498645216226577760f, 0.464747726917266850f,
+  0.498755723237991330f, 0.466278046369552610f, 0.498861521482467650f,
+  0.467808693647384640f, 0.498962640762329100f,
+  0.469339638948440550f, 0.499059051275253300f, 0.470870882272720340f,
+  0.499150782823562620f, 0.472402364015579220f, 0.499237775802612300f,
+  0.473934143781661990f, 0.499320119619369510f,
+  0.475466161966323850f, 0.499397724866867070f, 0.476998418569564820f,
+  0.499470651149749760f, 0.478530883789062500f, 0.499538868665695190f,
+  0.480063527822494510f, 0.499602377414703370f,
+  0.481596380472183230f, 0.499661177396774290f, 0.483129411935806270f,
+  0.499715298414230350f, 0.484662592411041260f, 0.499764710664749150f,
+  0.486195921897888180f, 0.499809414148330690f,
+  0.487729400396347050f, 0.499849408864974980f, 0.489262968301773070f,
+  0.499884694814682010f, 0.490796625614166260f, 0.499915301799774170f,
+  0.492330402135849000f, 0.499941170215606690f,
+  0.493864238262176510f, 0.499962359666824340f, 0.495398133993148800f,
+  0.499978810548782350f, 0.496932059526443480f, 0.499990582466125490f,
+  0.498466014862060550f, 0.499997645616531370f
+};
+
+
+/**   
+* \par  
+* Generation of realCoefB array:   
+* \par  
+* n = 1024   
+* 
    for (i = 0; i < n; i++)   
+* {   
+*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));   
+*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+*  } 
       
+*   
+*/
+static const float32_t realCoefB[2048] = {
+  0.500000000000000000f, 0.500000000000000000f, 0.501533985137939450f,
+  0.499997645616531370f, 0.503067970275878910f, 0.499990582466125490f,
+  0.504601895809173580f, 0.499978810548782350f,
+  0.506135761737823490f, 0.499962359666824340f, 0.507669627666473390f,
+  0.499941170215606690f, 0.509203374385833740f, 0.499915301799774170f,
+  0.510737061500549320f, 0.499884694814682010f,
+  0.512270629405975340f, 0.499849408864974980f, 0.513804078102111820f,
+  0.499809414148330690f, 0.515337407588958740f, 0.499764710664749150f,
+  0.516870558261871340f, 0.499715298414230350f,
+  0.518403589725494380f, 0.499661177396774290f, 0.519936442375183110f,
+  0.499602377414703370f, 0.521469116210937500f, 0.499538868665695190f,
+  0.523001611232757570f, 0.499470651149749760f,
+  0.524533808231353760f, 0.499397724866867070f, 0.526065826416015630f,
+  0.499320119619369510f, 0.527597606182098390f, 0.499237775802612300f,
+  0.529129147529602050f, 0.499150782823562620f,
+  0.530660390853881840f, 0.499059051275253300f, 0.532191336154937740f,
+  0.498962640762329100f, 0.533721983432769780f, 0.498861521482467650f,
+  0.535252273082733150f, 0.498755723237991330f,
+  0.536782264709472660f, 0.498645216226577760f, 0.538311958312988280f,
+  0.498530030250549320f, 0.539841234683990480f, 0.498410135507583620f,
+  0.541370153427124020f, 0.498285561800003050f,
+  0.542898654937744140f, 0.498156309127807620f, 0.544426798820495610f,
+  0.498022347688674930f, 0.545954465866088870f, 0.497883707284927370f,
+  0.547481775283813480f, 0.497740387916564940f,
+  0.549008548259735110f, 0.497592359781265260f, 0.550534904003143310f,
+  0.497439652681350710f, 0.552060842514038090f, 0.497282296419143680f,
+  0.553586184978485110f, 0.497120231389999390f,
+  0.555111110210418700f, 0.496953487396240230f, 0.556635499000549320f,
+  0.496782064437866210f, 0.558159291744232180f, 0.496605962514877320f,
+  0.559682607650756840f, 0.496425211429595950f,
+  0.561205327510833740f, 0.496239781379699710f, 0.562727510929107670f,
+  0.496049642562866210f, 0.564249038696289060f, 0.495854884386062620f,
+  0.565770030021667480f, 0.495655417442321780f,
+  0.567290365695953370f, 0.495451331138610840f, 0.568810045719146730f,
+  0.495242536067962650f, 0.570329129695892330f, 0.495029091835021970f,
+  0.571847498416900630f, 0.494810998439788820f,
+  0.573365211486816410f, 0.494588255882263180f, 0.574882268905639650f,
+  0.494360834360122680f, 0.576398611068725590f, 0.494128793478012080f,
+  0.577914178371429440f, 0.493892073631286620f,
+  0.579429090023040770f, 0.493650704622268680f, 0.580943167209625240f,
+  0.493404686450958250f, 0.582456588745117190f, 0.493154048919677730f,
+  0.583969175815582280f, 0.492898762226104740f,
+  0.585480928421020510f, 0.492638826370239260f, 0.586991965770721440f,
+  0.492374241352081300f, 0.588502109050750730f, 0.492105036973953250f,
+  0.590011477470397950f, 0.491831213235855100f,
+  0.591519951820373540f, 0.491552740335464480f, 0.593027591705322270f,
+  0.491269648075103760f, 0.594534337520599370f, 0.490981936454772950f,
+  0.596040189266204830f, 0.490689605474472050f,
+  0.597545146942138670f, 0.490392625331878660f, 0.599049210548400880f,
+  0.490091055631637570f, 0.600552320480346680f, 0.489784896373748780f,
+  0.602054476737976070f, 0.489474087953567500f,
+  0.603555679321289060f, 0.489158689975738530f, 0.605055928230285640f,
+  0.488838672637939450f, 0.606555163860321040f, 0.488514065742492680f,
+  0.608053386211395260f, 0.488184869289398190f,
+  0.609550595283508300f, 0.487851053476333620f, 0.611046791076660160f,
+  0.487512677907943730f, 0.612541973590850830f, 0.487169682979583740f,
+  0.614036023616790770f, 0.486822128295898440f,
+  0.615529060363769530f, 0.486469984054565430f, 0.617020964622497560f,
+  0.486113250255584720f, 0.618511795997619630f, 0.485751956701278690f,
+  0.620001494884490970f, 0.485386073589324950f,
+  0.621490061283111570f, 0.485015630722045900f, 0.622977554798126220f,
+  0.484640628099441530f, 0.624463796615600590f, 0.484261035919189450f,
+  0.625948905944824220f, 0.483876913785934450f,
+  0.627432823181152340f, 0.483488231897354130f, 0.628915548324584960f,
+  0.483094990253448490f, 0.630397081375122070f, 0.482697218656539920f,
+  0.631877362728118900f, 0.482294887304306030f,
+  0.633356392383575440f, 0.481888025999069210f, 0.634834170341491700f,
+  0.481476634740829470f, 0.636310696601867680f, 0.481060713529586790f,
+  0.637785911560058590f, 0.480640232563018800f,
+  0.639259815216064450f, 0.480215251445770260f, 0.640732467174530030f,
+  0.479785770177841190f, 0.642203748226165770f, 0.479351729154586790f,
+  0.643673717975616460f, 0.478913217782974240f,
+  0.645142316818237300f, 0.478470176458358760f, 0.646609604358673100f,
+  0.478022634983062740f, 0.648075461387634280f, 0.477570593357086180f,
+  0.649539887905120850f, 0.477114051580429080f,
+  0.651003003120422360f, 0.476653009653091430f, 0.652464628219604490f,
+  0.476187497377395630f, 0.653924822807312010f, 0.475717514753341670f,
+  0.655383586883544920f, 0.475243031978607180f,
+  0.656840860843658450f, 0.474764078855514530f, 0.658296704292297360f,
+  0.474280685186386110f, 0.659750998020172120f, 0.473792791366577150f,
+  0.661203861236572270f, 0.473300457000732420f,
+  0.662655174732208250f, 0.472803652286529540f, 0.664104938507080080f,
+  0.472302407026290890f, 0.665553152561187740f, 0.471796721220016480f,
+  0.666999816894531250f, 0.471286594867706300f,
+  0.668444931507110600f, 0.470772027969360350f, 0.669888436794281010f,
+  0.470253020524978640f, 0.671330332756042480f, 0.469729602336883540f,
+  0.672770678997039790f, 0.469201773405075070f,
+  0.674209356307983400f, 0.468669503927230830f, 0.675646364688873290f,
+  0.468132823705673220f, 0.677081763744354250f, 0.467591762542724610f,
+  0.678515493869781490f, 0.467046260833740230f,
+  0.679947495460510250f, 0.466496407985687260f, 0.681377887725830080f,
+  0.465942144393920900f, 0.682806491851806640f, 0.465383470058441160f,
+  0.684233427047729490f, 0.464820444583892820f,
+  0.685658574104309080f, 0.464253038167953490f, 0.687082052230834960f,
+  0.463681250810623170f, 0.688503682613372800f, 0.463105112314224240f,
+  0.689923584461212160f, 0.462524622678756710f,
+  0.691341698169708250f, 0.461939752101898190f, 0.692758023738861080f,
+  0.461350560188293460f, 0.694172501564025880f, 0.460757017135620120f,
+  0.695585191249847410f, 0.460159152746200560f,
+  0.696996033191680910f, 0.459556937217712400f, 0.698404967784881590f,
+  0.458950400352478030f, 0.699812114238739010f, 0.458339542150497440f,
+  0.701217353343963620f, 0.457724362611770630f,
+  0.702620685100555420f, 0.457104891538620000f, 0.704022109508514400f,
+  0.456481099128723140f, 0.705421566963195800f, 0.455853015184402470f,
+  0.706819176673889160f, 0.455220639705657960f,
+  0.708214759826660160f, 0.454584002494812010f, 0.709608435630798340f,
+  0.453943043947219850f, 0.711000144481658940f, 0.453297853469848630f,
+  0.712389826774597170f, 0.452648371458053590f,
+  0.713777542114257810f, 0.451994657516479490f, 0.715163230895996090f,
+  0.451336652040481570f, 0.716546893119812010f, 0.450674414634704590f,
+  0.717928528785705570f, 0.450007945299148560f,
+  0.719308137893676760f, 0.449337244033813480f, 0.720685660839080810f,
+  0.448662281036376950f, 0.722061097621917720f, 0.447983115911483760f,
+  0.723434448242187500f, 0.447299748659133910f,
+  0.724805653095245360f, 0.446612149477005000f, 0.726174771785736080f,
+  0.445920348167419430f, 0.727541804313659670f, 0.445224374532699580f,
+  0.728906631469726560f, 0.444524168968200680f,
+  0.730269372463226320f, 0.443819820880889890f, 0.731629908084869380f,
+  0.443111270666122440f, 0.732988238334655760f, 0.442398548126220700f,
+  0.734344422817230220f, 0.441681683063507080f,
+  0.735698342323303220f, 0.440960645675659180f, 0.737050116062164310f,
+  0.440235435962677000f, 0.738399624824523930f, 0.439506113529205320f,
+  0.739746868610382080f, 0.438772648572921750f,
+  0.741091907024383540f, 0.438035041093826290f, 0.742434620857238770f,
+  0.437293320894241330f, 0.743775069713592530f, 0.436547487974166870f,
+  0.745113253593444820f, 0.435797542333602910f,
+  0.746449112892150880f, 0.435043483972549440f, 0.747782647609710690f,
+  0.434285342693328860f, 0.749113857746124270f, 0.433523118495941160f,
+  0.750442683696746830f, 0.432756811380386350f,
+  0.751769185066223140f, 0.431986421346664430f, 0.753093302249908450f,
+  0.431211978197097780f, 0.754415094852447510f, 0.430433481931686400f,
+  0.755734443664550780f, 0.429650902748107910f,
+  0.757051348686218260f, 0.428864300251007080f, 0.758365929126739500f,
+  0.428073674440383910f, 0.759678006172180180f, 0.427278995513916020f,
+  0.760987639427185060f, 0.426480293273925780f,
+  0.762294828891754150f, 0.425677597522735600f, 0.763599574565887450f,
+  0.424870878458023070f, 0.764901816844940190f, 0.424060165882110600f,
+  0.766201555728912350f, 0.423245459794998170f,
+  0.767498791217803960f, 0.422426789999008180f, 0.768793523311614990f,
+  0.421604126691818240f, 0.770085752010345460f, 0.420777499675750730f,
+  0.771375417709350590f, 0.419946908950805660f,
+  0.772662520408630370f, 0.419112354516983030f, 0.773947000503540040f,
+  0.418273866176605220f, 0.775228977203369140f, 0.417431443929672240f,
+  0.776508331298828130f, 0.416585087776184080f,
+  0.777785122394561770f, 0.415734797716140750f, 0.779059290885925290f,
+  0.414880603551864620f, 0.780330777168273930f, 0.414022535085678100f,
+  0.781599700450897220f, 0.413160532712936400f,
+  0.782865881919860840f, 0.412294656038284300f, 0.784129500389099120f,
+  0.411424905061721800f, 0.785390377044677730f, 0.410551249980926510f,
+  0.786648571491241460f, 0.409673750400543210f,
+  0.787904083728790280f, 0.408792406320571900f, 0.789156913757324220f,
+  0.407907217741012570f, 0.790407001972198490f, 0.407018154859542850f,
+  0.791654348373413090f, 0.406125307083129880f,
+  0.792898952960968020f, 0.405228585004806520f, 0.794140756130218510f,
+  0.404328078031539920f, 0.795379877090454100f, 0.403423786163330080f,
+  0.796616137027740480f, 0.402515679597854610f,
+  0.797849655151367190f, 0.401603758335113530f, 0.799080371856689450f,
+  0.400688081979751590f, 0.800308227539062500f, 0.399768620729446410f,
+  0.801533281803131100f, 0.398845434188842770f,
+  0.802755534648895260f, 0.397918462753295900f, 0.803974866867065430f,
+  0.396987736225128170f, 0.805191397666931150f, 0.396053284406661990f,
+  0.806405067443847660f, 0.395115107297897340f,
+  0.807615816593170170f, 0.394173204898834230f, 0.808823645114898680f,
+  0.393227607011795040f, 0.810028612613677980f, 0.392278283834457400f,
+  0.811230659484863280f, 0.391325294971466060f,
+  0.812429726123809810f, 0.390368610620498660f, 0.813625931739807130f,
+  0.389408260583877560f, 0.814819097518920900f, 0.388444244861602780f,
+  0.816009342670440670f, 0.387476563453674320f,
+  0.817196667194366460f, 0.386505216360092160f, 0.818380951881408690f,
+  0.385530263185501100f, 0.819562196731567380f, 0.384551674127578740f,
+  0.820740520954132080f, 0.383569449186325070f,
+  0.821915745735168460f, 0.382583618164062500f, 0.823087990283966060f,
+  0.381594210863113400f, 0.824257194995880130f, 0.380601197481155400f,
+  0.825423359870910640f, 0.379604607820510860f,
+  0.826586425304412840f, 0.378604412078857420f, 0.827746450901031490f,
+  0.377600699663162230f, 0.828903317451477050f, 0.376593410968780520f,
+  0.830057144165039060f, 0.375582575798034670f,
+  0.831207871437072750f, 0.374568194150924680f, 0.832355499267578130f,
+  0.373550295829772950f, 0.833499968051910400f, 0.372528880834579470f,
+  0.834641277790069580f, 0.371503978967666630f,
+  0.835779488086700440f, 0.370475560426712040f, 0.836914479732513430f,
+  0.369443655014038090f, 0.838046371936798100f, 0.368408292531967160f,
+  0.839175045490264890f, 0.367369443178176880f,
+  0.840300500392913820f, 0.366327136754989620f, 0.841422796249389650f,
+  0.365281373262405400f, 0.842541813850402830f, 0.364232182502746580f,
+  0.843657672405242920f, 0.363179564476013180f,
+  0.844770252704620360f, 0.362123548984527590f, 0.845879614353179930f,
+  0.361064106225967410f, 0.846985757350921630f, 0.360001266002655030f,
+  0.848088562488555910f, 0.358935028314590450f,
+  0.849188148975372310f, 0.357865422964096070f, 0.850284397602081300f,
+  0.356792420148849490f, 0.851377367973327640f, 0.355716109275817870f,
+  0.852467060089111330f, 0.354636400938034060f,
+  0.853553414344787600f, 0.353553384542465210f, 0.854636430740356450f,
+  0.352467030286788940f, 0.855716109275817870f, 0.351377367973327640f,
+  0.856792449951171880f, 0.350284397602081300f,
+  0.857865393161773680f, 0.349188119173049930f, 0.858934998512268070f,
+  0.348088562488555910f, 0.860001266002655030f, 0.346985727548599240f,
+  0.861064076423645020f, 0.345879614353179930f,
+  0.862123548984527590f, 0.344770282506942750f, 0.863179564476013180f,
+  0.343657672405242920f, 0.864232182502746580f, 0.342541843652725220f,
+  0.865281403064727780f, 0.341422766447067260f,
+  0.866327106952667240f, 0.340300500392913820f, 0.867369413375854490f,
+  0.339175015687942500f, 0.868408262729644780f, 0.338046342134475710f,
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+  0.726174771785736080f, -0.445920348167419430f,
+  0.724805653095245360f, -0.446612149477005000f, 0.723434448242187500f,
+  -0.447299748659133910f, 0.722061097621917720f, -0.447983115911483760f,
+  0.720685660839080810f, -0.448662281036376950f,
+  0.719308137893676760f, -0.449337244033813480f, 0.717928528785705570f,
+  -0.450007945299148560f, 0.716546893119812010f, -0.450674414634704590f,
+  0.715163230895996090f, -0.451336652040481570f,
+  0.713777542114257810f, -0.451994657516479490f, 0.712389826774597170f,
+  -0.452648371458053590f, 0.711000144481658940f, -0.453297853469848630f,
+  0.709608435630798340f, -0.453943043947219850f,
+  0.708214759826660160f, -0.454584002494812010f, 0.706819176673889160f,
+  -0.455220639705657960f, 0.705421566963195800f, -0.455853015184402470f,
+  0.704022109508514400f, -0.456481099128723140f,
+  0.702620685100555420f, -0.457104891538620000f, 0.701217353343963620f,
+  -0.457724362611770630f, 0.699812114238739010f, -0.458339542150497440f,
+  0.698404967784881590f, -0.458950400352478030f,
+  0.696996033191680910f, -0.459556937217712400f, 0.695585191249847410f,
+  -0.460159152746200560f, 0.694172501564025880f, -0.460757017135620120f,
+  0.692758023738861080f, -0.461350560188293460f,
+  0.691341698169708250f, -0.461939752101898190f, 0.689923584461212160f,
+  -0.462524622678756710f, 0.688503682613372800f, -0.463105112314224240f,
+  0.687082052230834960f, -0.463681250810623170f,
+  0.685658574104309080f, -0.464253038167953490f, 0.684233427047729490f,
+  -0.464820444583892820f, 0.682806491851806640f, -0.465383470058441160f,
+  0.681377887725830080f, -0.465942144393920900f,
+  0.679947495460510250f, -0.466496407985687260f, 0.678515493869781490f,
+  -0.467046260833740230f, 0.677081763744354250f, -0.467591762542724610f,
+  0.675646364688873290f, -0.468132823705673220f,
+  0.674209356307983400f, -0.468669503927230830f, 0.672770678997039790f,
+  -0.469201773405075070f, 0.671330332756042480f, -0.469729602336883540f,
+  0.669888436794281010f, -0.470253020524978640f,
+  0.668444931507110600f, -0.470772027969360350f, 0.666999816894531250f,
+  -0.471286594867706300f, 0.665553152561187740f, -0.471796721220016480f,
+  0.664104938507080080f, -0.472302407026290890f,
+  0.662655174732208250f, -0.472803652286529540f, 0.661203861236572270f,
+  -0.473300457000732420f, 0.659750998020172120f, -0.473792791366577150f,
+  0.658296704292297360f, -0.474280685186386110f,
+  0.656840860843658450f, -0.474764078855514530f, 0.655383586883544920f,
+  -0.475243031978607180f, 0.653924822807312010f, -0.475717514753341670f,
+  0.652464628219604490f, -0.476187497377395630f,
+  0.651003003120422360f, -0.476653009653091430f, 0.649539887905120850f,
+  -0.477114051580429080f, 0.648075461387634280f, -0.477570593357086180f,
+  0.646609604358673100f, -0.478022634983062740f,
+  0.645142316818237300f, -0.478470176458358760f, 0.643673717975616460f,
+  -0.478913217782974240f, 0.642203748226165770f, -0.479351729154586790f,
+  0.640732467174530030f, -0.479785770177841190f,
+  0.639259815216064450f, -0.480215251445770260f, 0.637785911560058590f,
+  -0.480640232563018800f, 0.636310696601867680f, -0.481060713529586790f,
+  0.634834170341491700f, -0.481476634740829470f,
+  0.633356392383575440f, -0.481888025999069210f, 0.631877362728118900f,
+  -0.482294887304306030f, 0.630397081375122070f, -0.482697218656539920f,
+  0.628915548324584960f, -0.483094990253448490f,
+  0.627432823181152340f, -0.483488231897354130f, 0.625948905944824220f,
+  -0.483876913785934450f, 0.624463796615600590f, -0.484261035919189450f,
+  0.622977554798126220f, -0.484640628099441530f,
+  0.621490061283111570f, -0.485015630722045900f, 0.620001494884490970f,
+  -0.485386073589324950f, 0.618511795997619630f, -0.485751956701278690f,
+  0.617020964622497560f, -0.486113250255584720f,
+  0.615529060363769530f, -0.486469984054565430f, 0.614036023616790770f,
+  -0.486822128295898440f, 0.612541973590850830f, -0.487169682979583740f,
+  0.611046791076660160f, -0.487512677907943730f,
+  0.609550595283508300f, -0.487851053476333620f, 0.608053386211395260f,
+  -0.488184869289398190f, 0.606555163860321040f, -0.488514065742492680f,
+  0.605055928230285640f, -0.488838672637939450f,
+  0.603555679321289060f, -0.489158689975738530f, 0.602054476737976070f,
+  -0.489474087953567500f, 0.600552320480346680f, -0.489784896373748780f,
+  0.599049210548400880f, -0.490091055631637570f,
+  0.597545146942138670f, -0.490392625331878660f, 0.596040189266204830f,
+  -0.490689605474472050f, 0.594534337520599370f, -0.490981936454772950f,
+  0.593027591705322270f, -0.491269648075103760f,
+  0.591519951820373540f, -0.491552740335464480f, 0.590011477470397950f,
+  -0.491831213235855100f, 0.588502109050750730f, -0.492105036973953250f,
+  0.586991965770721440f, -0.492374241352081300f,
+  0.585480928421020510f, -0.492638826370239260f, 0.583969175815582280f,
+  -0.492898762226104740f, 0.582456588745117190f, -0.493154048919677730f,
+  0.580943167209625240f, -0.493404686450958250f,
+  0.579429090023040770f, -0.493650704622268680f, 0.577914178371429440f,
+  -0.493892073631286620f, 0.576398611068725590f, -0.494128793478012080f,
+  0.574882268905639650f, -0.494360834360122680f,
+  0.573365211486816410f, -0.494588255882263180f, 0.571847498416900630f,
+  -0.494810998439788820f, 0.570329129695892330f, -0.495029091835021970f,
+  0.568810045719146730f, -0.495242536067962650f,
+  0.567290365695953370f, -0.495451331138610840f, 0.565770030021667480f,
+  -0.495655417442321780f, 0.564249038696289060f, -0.495854884386062620f,
+  0.562727510929107670f, -0.496049642562866210f,
+  0.561205327510833740f, -0.496239781379699710f, 0.559682607650756840f,
+  -0.496425211429595950f, 0.558159291744232180f, -0.496605962514877320f,
+  0.556635499000549320f, -0.496782064437866210f,
+  0.555111110210418700f, -0.496953487396240230f, 0.553586184978485110f,
+  -0.497120231389999390f, 0.552060842514038090f, -0.497282296419143680f,
+  0.550534904003143310f, -0.497439652681350710f,
+  0.549008548259735110f, -0.497592359781265260f, 0.547481775283813480f,
+  -0.497740387916564940f, 0.545954465866088870f, -0.497883707284927370f,
+  0.544426798820495610f, -0.498022347688674930f,
+  0.542898654937744140f, -0.498156309127807620f, 0.541370153427124020f,
+  -0.498285561800003050f, 0.539841234683990480f, -0.498410135507583620f,
+  0.538311958312988280f, -0.498530030250549320f,
+  0.536782264709472660f, -0.498645216226577760f, 0.535252273082733150f,
+  -0.498755723237991330f, 0.533721983432769780f, -0.498861521482467650f,
+  0.532191336154937740f, -0.498962640762329100f,
+  0.530660390853881840f, -0.499059051275253300f, 0.529129147529602050f,
+  -0.499150782823562620f, 0.527597606182098390f, -0.499237775802612300f,
+  0.526065826416015630f, -0.499320119619369510f,
+  0.524533808231353760f, -0.499397724866867070f, 0.523001611232757570f,
+  -0.499470651149749760f, 0.521469116210937500f, -0.499538868665695190f,
+  0.519936442375183110f, -0.499602377414703370f,
+  0.518403589725494380f, -0.499661177396774290f, 0.516870558261871340f,
+  -0.499715298414230350f, 0.515337407588958740f, -0.499764710664749150f,
+  0.513804078102111820f, -0.499809414148330690f,
+  0.512270629405975340f, -0.499849408864974980f, 0.510737061500549320f,
+  -0.499884694814682010f, 0.509203374385833740f, -0.499915301799774170f,
+  0.507669627666473390f, -0.499941170215606690f,
+  0.506135761737823490f, -0.499962359666824340f, 0.504601895809173580f,
+  -0.499978810548782350f, 0.503067970275878910f, -0.499990582466125490f,
+  0.501533985137939450f, -0.499997645616531370f
+};
+
+
+
+/**   
+* @brief  Initialization function for the floating-point RFFT/RIFFT.  
+* @param[in,out] *S             points to an instance of the floating-point RFFT/RIFFT structure.  
+* @param[in,out] *S_CFFT        points to an instance of the floating-point CFFT/CIFFT structure.  
+* @param[in]     fftLenReal     length of the FFT.  
+* @param[in]     ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.  
+* @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.  
+*   
+* \par Description:  
+* \par  
+* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.   
+* \par   
+* The parameter ifftFlagR controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.   
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.  
+* \par   
+* This function also initializes Twiddle factor table.    
+*/
+
+arm_status arm_rfft_init_f32(
+  arm_rfft_instance_f32 * S,
+  arm_cfft_radix4_instance_f32 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag)
+{
+
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialize the Real FFT length */
+  S->fftLenReal = (uint16_t) fftLenReal;
+
+  /*  Initialize the Complex FFT length */
+  S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
+
+  /*  Initialize the Twiddle coefficientA pointer */
+  S->pTwiddleAReal = (float32_t *) realCoefA;
+
+  /*  Initialize the Twiddle coefficientB pointer */
+  S->pTwiddleBReal = (float32_t *) realCoefB;
+
+  /*  Initialize the Flag for selection of RFFT or RIFFT */
+  S->ifftFlagR = (uint8_t) ifftFlagR;
+
+  /*  Initialize the Flag for calculation Bit reversal or not */
+  S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+  /*  Initializations of structure parameters depending on the FFT length */
+  switch (S->fftLenReal)
+  {
+    /* Init table modifier value */
+  case 2048u:
+    S->twidCoefRModifier = 1u;
+    break;
+  case 512u:
+    S->twidCoefRModifier = 4u;
+    break;
+  case 128u:
+    S->twidCoefRModifier = 16u;
+    break;
+  default:
+    /*  Reporting argument error if rfftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  /* Init Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  if(S->ifftFlagR)
+  {
+    /* Initializes the CIFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 1u, 0u);
+  }
+  else
+  {
+    /* Initializes the CFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_f32(S->pCfft, S->fftLenBy2, 0u, 0u);
+  }
+
+  /* return the status of RFFT Init function */
+  return (status);
+
+}
+
+  /**   
+   * @} end of RFFT_RIFFT group   
+   */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c
new file mode 100644
index 0000000000..61bcc556a7
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c
@@ -0,0 +1,688 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_rfft_init_q15.c   
+*   
+* Description:	RFFT & RIFFT Q15 initialisation function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup RFFT_RIFFT   
+ * @{   
+ */
+
+
+
+/**   
+* \par   
+* Generation floating point real_CoefA array:   
+* \par   
+* n = 1024   
+* 
    for (i = 0; i < n; i++)   
+*  {   
+*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));   
+*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+*  } 
       
+* \par   
+* Convert to fixed point Q15 format   
+*       round(pATable[i] * pow(2, 15))   
+*/
+
+
+static const q15_t realCoefAQ15[2048] = {
+
+  0x4000, 0xc000, 0x3fce, 0xc000, 0x3f9b, 0xc000, 0x3f69, 0xc001,
+  0x3f37, 0xc001, 0x3f05, 0xc002, 0x3ed2, 0xc003, 0x3ea0, 0xc004,
+  0x3e6e, 0xc005, 0x3e3c, 0xc006, 0x3e09, 0xc008, 0x3dd7, 0xc009,
+  0x3da5, 0xc00b, 0x3d73, 0xc00d, 0x3d40, 0xc00f, 0x3d0e, 0xc011,
+  0x3cdc, 0xc014, 0x3caa, 0xc016, 0x3c78, 0xc019, 0x3c45, 0xc01c,
+  0x3c13, 0xc01f, 0x3be1, 0xc022, 0x3baf, 0xc025, 0x3b7d, 0xc029,
+  0x3b4b, 0xc02c, 0x3b19, 0xc030, 0x3ae6, 0xc034, 0x3ab4, 0xc038,
+  0x3a82, 0xc03c, 0x3a50, 0xc041, 0x3a1e, 0xc045, 0x39ec, 0xc04a,
+  0x39ba, 0xc04f, 0x3988, 0xc054, 0x3956, 0xc059, 0x3924, 0xc05e,
+  0x38f2, 0xc064, 0x38c0, 0xc069, 0x388e, 0xc06f, 0x385c, 0xc075,
+  0x382a, 0xc07b, 0x37f9, 0xc081, 0x37c7, 0xc088, 0x3795, 0xc08e,
+  0x3763, 0xc095, 0x3731, 0xc09c, 0x36ff, 0xc0a3, 0x36ce, 0xc0aa,
+  0x369c, 0xc0b1, 0x366a, 0xc0b9, 0x3639, 0xc0c0, 0x3607, 0xc0c8,
+  0x35d5, 0xc0d0, 0x35a4, 0xc0d8, 0x3572, 0xc0e0, 0x3540, 0xc0e9,
+  0x350f, 0xc0f1, 0x34dd, 0xc0fa, 0x34ac, 0xc103, 0x347b, 0xc10c,
+  0x3449, 0xc115, 0x3418, 0xc11e, 0x33e6, 0xc128, 0x33b5, 0xc131,
+  0x3384, 0xc13b, 0x3352, 0xc145, 0x3321, 0xc14f, 0x32f0, 0xc159,
+  0x32bf, 0xc163, 0x328e, 0xc16e, 0x325c, 0xc178, 0x322b, 0xc183,
+  0x31fa, 0xc18e, 0x31c9, 0xc199, 0x3198, 0xc1a4, 0x3167, 0xc1b0,
+  0x3136, 0xc1bb, 0x3105, 0xc1c7, 0x30d5, 0xc1d3, 0x30a4, 0xc1df,
+  0x3073, 0xc1eb, 0x3042, 0xc1f7, 0x3012, 0xc204, 0x2fe1, 0xc210,
+  0x2fb0, 0xc21d, 0x2f80, 0xc22a, 0x2f4f, 0xc237, 0x2f1f, 0xc244,
+  0x2eee, 0xc251, 0x2ebe, 0xc25f, 0x2e8d, 0xc26d, 0x2e5d, 0xc27a,
+  0x2e2d, 0xc288, 0x2dfc, 0xc296, 0x2dcc, 0xc2a5, 0x2d9c, 0xc2b3,
+  0x2d6c, 0xc2c1, 0x2d3c, 0xc2d0, 0x2d0c, 0xc2df, 0x2cdc, 0xc2ee,
+  0x2cac, 0xc2fd, 0x2c7c, 0xc30c, 0x2c4c, 0xc31c, 0x2c1c, 0xc32b,
+  0x2bed, 0xc33b, 0x2bbd, 0xc34b, 0x2b8d, 0xc35b, 0x2b5e, 0xc36b,
+  0x2b2e, 0xc37b, 0x2aff, 0xc38c, 0x2acf, 0xc39c, 0x2aa0, 0xc3ad,
+  0x2a70, 0xc3be, 0x2a41, 0xc3cf, 0x2a12, 0xc3e0, 0x29e3, 0xc3f1,
+  0x29b4, 0xc403, 0x2984, 0xc414, 0x2955, 0xc426, 0x2926, 0xc438,
+  0x28f7, 0xc44a, 0x28c9, 0xc45c, 0x289a, 0xc46e, 0x286b, 0xc481,
+  0x283c, 0xc493, 0x280e, 0xc4a6, 0x27df, 0xc4b9, 0x27b1, 0xc4cc,
+  0x2782, 0xc4df, 0x2754, 0xc4f2, 0x2725, 0xc506, 0x26f7, 0xc51a,
+  0x26c9, 0xc52d, 0x269b, 0xc541, 0x266d, 0xc555, 0x263f, 0xc569,
+  0x2611, 0xc57e, 0x25e3, 0xc592, 0x25b5, 0xc5a7, 0x2587, 0xc5bb,
+  0x2559, 0xc5d0, 0x252c, 0xc5e5, 0x24fe, 0xc5fa, 0x24d0, 0xc610,
+  0x24a3, 0xc625, 0x2476, 0xc63b, 0x2448, 0xc650, 0x241b, 0xc666,
+  0x23ee, 0xc67c, 0x23c1, 0xc692, 0x2394, 0xc6a8, 0x2367, 0xc6bf,
+  0x233a, 0xc6d5, 0x230d, 0xc6ec, 0x22e0, 0xc703, 0x22b3, 0xc71a,
+  0x2287, 0xc731, 0x225a, 0xc748, 0x222d, 0xc75f, 0x2201, 0xc777,
+  0x21d5, 0xc78f, 0x21a8, 0xc7a6, 0x217c, 0xc7be, 0x2150, 0xc7d6,
+  0x2124, 0xc7ee, 0x20f8, 0xc807, 0x20cc, 0xc81f, 0x20a0, 0xc838,
+  0x2074, 0xc850, 0x2049, 0xc869, 0x201d, 0xc882, 0x1ff1, 0xc89b,
+  0x1fc6, 0xc8b5, 0x1f9b, 0xc8ce, 0x1f6f, 0xc8e8, 0x1f44, 0xc901,
+  0x1f19, 0xc91b, 0x1eee, 0xc935, 0x1ec3, 0xc94f, 0x1e98, 0xc969,
+  0x1e6d, 0xc983, 0x1e42, 0xc99e, 0x1e18, 0xc9b8, 0x1ded, 0xc9d3,
+  0x1dc3, 0xc9ee, 0x1d98, 0xca09, 0x1d6e, 0xca24, 0x1d44, 0xca3f,
+  0x1d19, 0xca5b, 0x1cef, 0xca76, 0x1cc5, 0xca92, 0x1c9b, 0xcaad,
+  0x1c72, 0xcac9, 0x1c48, 0xcae5, 0x1c1e, 0xcb01, 0x1bf5, 0xcb1e,
+  0x1bcb, 0xcb3a, 0x1ba2, 0xcb56, 0x1b78, 0xcb73, 0x1b4f, 0xcb90,
+  0x1b26, 0xcbad, 0x1afd, 0xcbca, 0x1ad4, 0xcbe7, 0x1aab, 0xcc04,
+  0x1a82, 0xcc21, 0x1a5a, 0xcc3f, 0x1a31, 0xcc5d, 0x1a08, 0xcc7a,
+  0x19e0, 0xcc98, 0x19b8, 0xccb6, 0x198f, 0xccd4, 0x1967, 0xccf3,
+  0x193f, 0xcd11, 0x1917, 0xcd30, 0x18ef, 0xcd4e, 0x18c8, 0xcd6d,
+  0x18a0, 0xcd8c, 0x1878, 0xcdab, 0x1851, 0xcdca, 0x182a, 0xcde9,
+  0x1802, 0xce08, 0x17db, 0xce28, 0x17b4, 0xce47, 0x178d, 0xce67,
+  0x1766, 0xce87, 0x173f, 0xcea7, 0x1719, 0xcec7, 0x16f2, 0xcee7,
+  0x16cb, 0xcf07, 0x16a5, 0xcf28, 0x167f, 0xcf48, 0x1659, 0xcf69,
+  0x1632, 0xcf8a, 0x160c, 0xcfab, 0x15e6, 0xcfcc, 0x15c1, 0xcfed,
+  0x159b, 0xd00e, 0x1575, 0xd030, 0x1550, 0xd051, 0x152a, 0xd073,
+  0x1505, 0xd094, 0x14e0, 0xd0b6, 0x14bb, 0xd0d8, 0x1496, 0xd0fa,
+  0x1471, 0xd11c, 0x144c, 0xd13e, 0x1428, 0xd161, 0x1403, 0xd183,
+  0x13df, 0xd1a6, 0x13ba, 0xd1c9, 0x1396, 0xd1eb, 0x1372, 0xd20e,
+  0x134e, 0xd231, 0x132a, 0xd255, 0x1306, 0xd278, 0x12e2, 0xd29b,
+  0x12bf, 0xd2bf, 0x129b, 0xd2e2, 0x1278, 0xd306, 0x1255, 0xd32a,
+  0x1231, 0xd34e, 0x120e, 0xd372, 0x11eb, 0xd396, 0x11c9, 0xd3ba,
+  0x11a6, 0xd3df, 0x1183, 0xd403, 0x1161, 0xd428, 0x113e, 0xd44c,
+  0x111c, 0xd471, 0x10fa, 0xd496, 0x10d8, 0xd4bb, 0x10b6, 0xd4e0,
+  0x1094, 0xd505, 0x1073, 0xd52a, 0x1051, 0xd550, 0x1030, 0xd575,
+  0x100e, 0xd59b, 0xfed, 0xd5c1, 0xfcc, 0xd5e6, 0xfab, 0xd60c,
+  0xf8a, 0xd632, 0xf69, 0xd659, 0xf48, 0xd67f, 0xf28, 0xd6a5,
+  0xf07, 0xd6cb, 0xee7, 0xd6f2, 0xec7, 0xd719, 0xea7, 0xd73f,
+  0xe87, 0xd766, 0xe67, 0xd78d, 0xe47, 0xd7b4, 0xe28, 0xd7db,
+  0xe08, 0xd802, 0xde9, 0xd82a, 0xdca, 0xd851, 0xdab, 0xd878,
+  0xd8c, 0xd8a0, 0xd6d, 0xd8c8, 0xd4e, 0xd8ef, 0xd30, 0xd917,
+  0xd11, 0xd93f, 0xcf3, 0xd967, 0xcd4, 0xd98f, 0xcb6, 0xd9b8,
+  0xc98, 0xd9e0, 0xc7a, 0xda08, 0xc5d, 0xda31, 0xc3f, 0xda5a,
+  0xc21, 0xda82, 0xc04, 0xdaab, 0xbe7, 0xdad4, 0xbca, 0xdafd,
+  0xbad, 0xdb26, 0xb90, 0xdb4f, 0xb73, 0xdb78, 0xb56, 0xdba2,
+  0xb3a, 0xdbcb, 0xb1e, 0xdbf5, 0xb01, 0xdc1e, 0xae5, 0xdc48,
+  0xac9, 0xdc72, 0xaad, 0xdc9b, 0xa92, 0xdcc5, 0xa76, 0xdcef,
+  0xa5b, 0xdd19, 0xa3f, 0xdd44, 0xa24, 0xdd6e, 0xa09, 0xdd98,
+  0x9ee, 0xddc3, 0x9d3, 0xdded, 0x9b8, 0xde18, 0x99e, 0xde42,
+  0x983, 0xde6d, 0x969, 0xde98, 0x94f, 0xdec3, 0x935, 0xdeee,
+  0x91b, 0xdf19, 0x901, 0xdf44, 0x8e8, 0xdf6f, 0x8ce, 0xdf9b,
+  0x8b5, 0xdfc6, 0x89b, 0xdff1, 0x882, 0xe01d, 0x869, 0xe049,
+  0x850, 0xe074, 0x838, 0xe0a0, 0x81f, 0xe0cc, 0x807, 0xe0f8,
+  0x7ee, 0xe124, 0x7d6, 0xe150, 0x7be, 0xe17c, 0x7a6, 0xe1a8,
+  0x78f, 0xe1d5, 0x777, 0xe201, 0x75f, 0xe22d, 0x748, 0xe25a,
+  0x731, 0xe287, 0x71a, 0xe2b3, 0x703, 0xe2e0, 0x6ec, 0xe30d,
+  0x6d5, 0xe33a, 0x6bf, 0xe367, 0x6a8, 0xe394, 0x692, 0xe3c1,
+  0x67c, 0xe3ee, 0x666, 0xe41b, 0x650, 0xe448, 0x63b, 0xe476,
+  0x625, 0xe4a3, 0x610, 0xe4d0, 0x5fa, 0xe4fe, 0x5e5, 0xe52c,
+  0x5d0, 0xe559, 0x5bb, 0xe587, 0x5a7, 0xe5b5, 0x592, 0xe5e3,
+  0x57e, 0xe611, 0x569, 0xe63f, 0x555, 0xe66d, 0x541, 0xe69b,
+  0x52d, 0xe6c9, 0x51a, 0xe6f7, 0x506, 0xe725, 0x4f2, 0xe754,
+  0x4df, 0xe782, 0x4cc, 0xe7b1, 0x4b9, 0xe7df, 0x4a6, 0xe80e,
+  0x493, 0xe83c, 0x481, 0xe86b, 0x46e, 0xe89a, 0x45c, 0xe8c9,
+  0x44a, 0xe8f7, 0x438, 0xe926, 0x426, 0xe955, 0x414, 0xe984,
+  0x403, 0xe9b4, 0x3f1, 0xe9e3, 0x3e0, 0xea12, 0x3cf, 0xea41,
+  0x3be, 0xea70, 0x3ad, 0xeaa0, 0x39c, 0xeacf, 0x38c, 0xeaff,
+  0x37b, 0xeb2e, 0x36b, 0xeb5e, 0x35b, 0xeb8d, 0x34b, 0xebbd,
+  0x33b, 0xebed, 0x32b, 0xec1c, 0x31c, 0xec4c, 0x30c, 0xec7c,
+  0x2fd, 0xecac, 0x2ee, 0xecdc, 0x2df, 0xed0c, 0x2d0, 0xed3c,
+  0x2c1, 0xed6c, 0x2b3, 0xed9c, 0x2a5, 0xedcc, 0x296, 0xedfc,
+  0x288, 0xee2d, 0x27a, 0xee5d, 0x26d, 0xee8d, 0x25f, 0xeebe,
+  0x251, 0xeeee, 0x244, 0xef1f, 0x237, 0xef4f, 0x22a, 0xef80,
+  0x21d, 0xefb0, 0x210, 0xefe1, 0x204, 0xf012, 0x1f7, 0xf042,
+  0x1eb, 0xf073, 0x1df, 0xf0a4, 0x1d3, 0xf0d5, 0x1c7, 0xf105,
+  0x1bb, 0xf136, 0x1b0, 0xf167, 0x1a4, 0xf198, 0x199, 0xf1c9,
+  0x18e, 0xf1fa, 0x183, 0xf22b, 0x178, 0xf25c, 0x16e, 0xf28e,
+  0x163, 0xf2bf, 0x159, 0xf2f0, 0x14f, 0xf321, 0x145, 0xf352,
+  0x13b, 0xf384, 0x131, 0xf3b5, 0x128, 0xf3e6, 0x11e, 0xf418,
+  0x115, 0xf449, 0x10c, 0xf47b, 0x103, 0xf4ac, 0xfa, 0xf4dd,
+  0xf1, 0xf50f, 0xe9, 0xf540, 0xe0, 0xf572, 0xd8, 0xf5a4,
+  0xd0, 0xf5d5, 0xc8, 0xf607, 0xc0, 0xf639, 0xb9, 0xf66a,
+  0xb1, 0xf69c, 0xaa, 0xf6ce, 0xa3, 0xf6ff, 0x9c, 0xf731,
+  0x95, 0xf763, 0x8e, 0xf795, 0x88, 0xf7c7, 0x81, 0xf7f9,
+  0x7b, 0xf82a, 0x75, 0xf85c, 0x6f, 0xf88e, 0x69, 0xf8c0,
+  0x64, 0xf8f2, 0x5e, 0xf924, 0x59, 0xf956, 0x54, 0xf988,
+  0x4f, 0xf9ba, 0x4a, 0xf9ec, 0x45, 0xfa1e, 0x41, 0xfa50,
+  0x3c, 0xfa82, 0x38, 0xfab4, 0x34, 0xfae6, 0x30, 0xfb19,
+  0x2c, 0xfb4b, 0x29, 0xfb7d, 0x25, 0xfbaf, 0x22, 0xfbe1,
+  0x1f, 0xfc13, 0x1c, 0xfc45, 0x19, 0xfc78, 0x16, 0xfcaa,
+  0x14, 0xfcdc, 0x11, 0xfd0e, 0xf, 0xfd40, 0xd, 0xfd73,
+  0xb, 0xfda5, 0x9, 0xfdd7, 0x8, 0xfe09, 0x6, 0xfe3c,
+  0x5, 0xfe6e, 0x4, 0xfea0, 0x3, 0xfed2, 0x2, 0xff05,
+  0x1, 0xff37, 0x1, 0xff69, 0x0, 0xff9b, 0x0, 0xffce,
+  0x0, 0x0, 0x0, 0x32, 0x0, 0x65, 0x1, 0x97,
+  0x1, 0xc9, 0x2, 0xfb, 0x3, 0x12e, 0x4, 0x160,
+  0x5, 0x192, 0x6, 0x1c4, 0x8, 0x1f7, 0x9, 0x229,
+  0xb, 0x25b, 0xd, 0x28d, 0xf, 0x2c0, 0x11, 0x2f2,
+  0x14, 0x324, 0x16, 0x356, 0x19, 0x388, 0x1c, 0x3bb,
+  0x1f, 0x3ed, 0x22, 0x41f, 0x25, 0x451, 0x29, 0x483,
+  0x2c, 0x4b5, 0x30, 0x4e7, 0x34, 0x51a, 0x38, 0x54c,
+  0x3c, 0x57e, 0x41, 0x5b0, 0x45, 0x5e2, 0x4a, 0x614,
+  0x4f, 0x646, 0x54, 0x678, 0x59, 0x6aa, 0x5e, 0x6dc,
+  0x64, 0x70e, 0x69, 0x740, 0x6f, 0x772, 0x75, 0x7a4,
+  0x7b, 0x7d6, 0x81, 0x807, 0x88, 0x839, 0x8e, 0x86b,
+  0x95, 0x89d, 0x9c, 0x8cf, 0xa3, 0x901, 0xaa, 0x932,
+  0xb1, 0x964, 0xb9, 0x996, 0xc0, 0x9c7, 0xc8, 0x9f9,
+  0xd0, 0xa2b, 0xd8, 0xa5c, 0xe0, 0xa8e, 0xe9, 0xac0,
+  0xf1, 0xaf1, 0xfa, 0xb23, 0x103, 0xb54, 0x10c, 0xb85,
+  0x115, 0xbb7, 0x11e, 0xbe8, 0x128, 0xc1a, 0x131, 0xc4b,
+  0x13b, 0xc7c, 0x145, 0xcae, 0x14f, 0xcdf, 0x159, 0xd10,
+  0x163, 0xd41, 0x16e, 0xd72, 0x178, 0xda4, 0x183, 0xdd5,
+  0x18e, 0xe06, 0x199, 0xe37, 0x1a4, 0xe68, 0x1b0, 0xe99,
+  0x1bb, 0xeca, 0x1c7, 0xefb, 0x1d3, 0xf2b, 0x1df, 0xf5c,
+  0x1eb, 0xf8d, 0x1f7, 0xfbe, 0x204, 0xfee, 0x210, 0x101f,
+  0x21d, 0x1050, 0x22a, 0x1080, 0x237, 0x10b1, 0x244, 0x10e1,
+  0x251, 0x1112, 0x25f, 0x1142, 0x26d, 0x1173, 0x27a, 0x11a3,
+  0x288, 0x11d3, 0x296, 0x1204, 0x2a5, 0x1234, 0x2b3, 0x1264,
+  0x2c1, 0x1294, 0x2d0, 0x12c4, 0x2df, 0x12f4, 0x2ee, 0x1324,
+  0x2fd, 0x1354, 0x30c, 0x1384, 0x31c, 0x13b4, 0x32b, 0x13e4,
+  0x33b, 0x1413, 0x34b, 0x1443, 0x35b, 0x1473, 0x36b, 0x14a2,
+  0x37b, 0x14d2, 0x38c, 0x1501, 0x39c, 0x1531, 0x3ad, 0x1560,
+  0x3be, 0x1590, 0x3cf, 0x15bf, 0x3e0, 0x15ee, 0x3f1, 0x161d,
+  0x403, 0x164c, 0x414, 0x167c, 0x426, 0x16ab, 0x438, 0x16da,
+  0x44a, 0x1709, 0x45c, 0x1737, 0x46e, 0x1766, 0x481, 0x1795,
+  0x493, 0x17c4, 0x4a6, 0x17f2, 0x4b9, 0x1821, 0x4cc, 0x184f,
+  0x4df, 0x187e, 0x4f2, 0x18ac, 0x506, 0x18db, 0x51a, 0x1909,
+  0x52d, 0x1937, 0x541, 0x1965, 0x555, 0x1993, 0x569, 0x19c1,
+  0x57e, 0x19ef, 0x592, 0x1a1d, 0x5a7, 0x1a4b, 0x5bb, 0x1a79,
+  0x5d0, 0x1aa7, 0x5e5, 0x1ad4, 0x5fa, 0x1b02, 0x610, 0x1b30,
+  0x625, 0x1b5d, 0x63b, 0x1b8a, 0x650, 0x1bb8, 0x666, 0x1be5,
+  0x67c, 0x1c12, 0x692, 0x1c3f, 0x6a8, 0x1c6c, 0x6bf, 0x1c99,
+  0x6d5, 0x1cc6, 0x6ec, 0x1cf3, 0x703, 0x1d20, 0x71a, 0x1d4d,
+  0x731, 0x1d79, 0x748, 0x1da6, 0x75f, 0x1dd3, 0x777, 0x1dff,
+  0x78f, 0x1e2b, 0x7a6, 0x1e58, 0x7be, 0x1e84, 0x7d6, 0x1eb0,
+  0x7ee, 0x1edc, 0x807, 0x1f08, 0x81f, 0x1f34, 0x838, 0x1f60,
+  0x850, 0x1f8c, 0x869, 0x1fb7, 0x882, 0x1fe3, 0x89b, 0x200f,
+  0x8b5, 0x203a, 0x8ce, 0x2065, 0x8e8, 0x2091, 0x901, 0x20bc,
+  0x91b, 0x20e7, 0x935, 0x2112, 0x94f, 0x213d, 0x969, 0x2168,
+  0x983, 0x2193, 0x99e, 0x21be, 0x9b8, 0x21e8, 0x9d3, 0x2213,
+  0x9ee, 0x223d, 0xa09, 0x2268, 0xa24, 0x2292, 0xa3f, 0x22bc,
+  0xa5b, 0x22e7, 0xa76, 0x2311, 0xa92, 0x233b, 0xaad, 0x2365,
+  0xac9, 0x238e, 0xae5, 0x23b8, 0xb01, 0x23e2, 0xb1e, 0x240b,
+  0xb3a, 0x2435, 0xb56, 0x245e, 0xb73, 0x2488, 0xb90, 0x24b1,
+  0xbad, 0x24da, 0xbca, 0x2503, 0xbe7, 0x252c, 0xc04, 0x2555,
+  0xc21, 0x257e, 0xc3f, 0x25a6, 0xc5d, 0x25cf, 0xc7a, 0x25f8,
+  0xc98, 0x2620, 0xcb6, 0x2648, 0xcd4, 0x2671, 0xcf3, 0x2699,
+  0xd11, 0x26c1, 0xd30, 0x26e9, 0xd4e, 0x2711, 0xd6d, 0x2738,
+  0xd8c, 0x2760, 0xdab, 0x2788, 0xdca, 0x27af, 0xde9, 0x27d6,
+  0xe08, 0x27fe, 0xe28, 0x2825, 0xe47, 0x284c, 0xe67, 0x2873,
+  0xe87, 0x289a, 0xea7, 0x28c1, 0xec7, 0x28e7, 0xee7, 0x290e,
+  0xf07, 0x2935, 0xf28, 0x295b, 0xf48, 0x2981, 0xf69, 0x29a7,
+  0xf8a, 0x29ce, 0xfab, 0x29f4, 0xfcc, 0x2a1a, 0xfed, 0x2a3f,
+  0x100e, 0x2a65, 0x1030, 0x2a8b, 0x1051, 0x2ab0, 0x1073, 0x2ad6,
+  0x1094, 0x2afb, 0x10b6, 0x2b20, 0x10d8, 0x2b45, 0x10fa, 0x2b6a,
+  0x111c, 0x2b8f, 0x113e, 0x2bb4, 0x1161, 0x2bd8, 0x1183, 0x2bfd,
+  0x11a6, 0x2c21, 0x11c9, 0x2c46, 0x11eb, 0x2c6a, 0x120e, 0x2c8e,
+  0x1231, 0x2cb2, 0x1255, 0x2cd6, 0x1278, 0x2cfa, 0x129b, 0x2d1e,
+  0x12bf, 0x2d41, 0x12e2, 0x2d65, 0x1306, 0x2d88, 0x132a, 0x2dab,
+  0x134e, 0x2dcf, 0x1372, 0x2df2, 0x1396, 0x2e15, 0x13ba, 0x2e37,
+  0x13df, 0x2e5a, 0x1403, 0x2e7d, 0x1428, 0x2e9f, 0x144c, 0x2ec2,
+  0x1471, 0x2ee4, 0x1496, 0x2f06, 0x14bb, 0x2f28, 0x14e0, 0x2f4a,
+  0x1505, 0x2f6c, 0x152a, 0x2f8d, 0x1550, 0x2faf, 0x1575, 0x2fd0,
+  0x159b, 0x2ff2, 0x15c1, 0x3013, 0x15e6, 0x3034, 0x160c, 0x3055,
+  0x1632, 0x3076, 0x1659, 0x3097, 0x167f, 0x30b8, 0x16a5, 0x30d8,
+  0x16cb, 0x30f9, 0x16f2, 0x3119, 0x1719, 0x3139, 0x173f, 0x3159,
+  0x1766, 0x3179, 0x178d, 0x3199, 0x17b4, 0x31b9, 0x17db, 0x31d8,
+  0x1802, 0x31f8, 0x182a, 0x3217, 0x1851, 0x3236, 0x1878, 0x3255,
+  0x18a0, 0x3274, 0x18c8, 0x3293, 0x18ef, 0x32b2, 0x1917, 0x32d0,
+  0x193f, 0x32ef, 0x1967, 0x330d, 0x198f, 0x332c, 0x19b8, 0x334a,
+  0x19e0, 0x3368, 0x1a08, 0x3386, 0x1a31, 0x33a3, 0x1a5a, 0x33c1,
+  0x1a82, 0x33df, 0x1aab, 0x33fc, 0x1ad4, 0x3419, 0x1afd, 0x3436,
+  0x1b26, 0x3453, 0x1b4f, 0x3470, 0x1b78, 0x348d, 0x1ba2, 0x34aa,
+  0x1bcb, 0x34c6, 0x1bf5, 0x34e2, 0x1c1e, 0x34ff, 0x1c48, 0x351b,
+  0x1c72, 0x3537, 0x1c9b, 0x3553, 0x1cc5, 0x356e, 0x1cef, 0x358a,
+  0x1d19, 0x35a5, 0x1d44, 0x35c1, 0x1d6e, 0x35dc, 0x1d98, 0x35f7,
+  0x1dc3, 0x3612, 0x1ded, 0x362d, 0x1e18, 0x3648, 0x1e42, 0x3662,
+  0x1e6d, 0x367d, 0x1e98, 0x3697, 0x1ec3, 0x36b1, 0x1eee, 0x36cb,
+  0x1f19, 0x36e5, 0x1f44, 0x36ff, 0x1f6f, 0x3718, 0x1f9b, 0x3732,
+  0x1fc6, 0x374b, 0x1ff1, 0x3765, 0x201d, 0x377e, 0x2049, 0x3797,
+  0x2074, 0x37b0, 0x20a0, 0x37c8, 0x20cc, 0x37e1, 0x20f8, 0x37f9,
+  0x2124, 0x3812, 0x2150, 0x382a, 0x217c, 0x3842, 0x21a8, 0x385a,
+  0x21d5, 0x3871, 0x2201, 0x3889, 0x222d, 0x38a1, 0x225a, 0x38b8,
+  0x2287, 0x38cf, 0x22b3, 0x38e6, 0x22e0, 0x38fd, 0x230d, 0x3914,
+  0x233a, 0x392b, 0x2367, 0x3941, 0x2394, 0x3958, 0x23c1, 0x396e,
+  0x23ee, 0x3984, 0x241b, 0x399a, 0x2448, 0x39b0, 0x2476, 0x39c5,
+  0x24a3, 0x39db, 0x24d0, 0x39f0, 0x24fe, 0x3a06, 0x252c, 0x3a1b,
+  0x2559, 0x3a30, 0x2587, 0x3a45, 0x25b5, 0x3a59, 0x25e3, 0x3a6e,
+  0x2611, 0x3a82, 0x263f, 0x3a97, 0x266d, 0x3aab, 0x269b, 0x3abf,
+  0x26c9, 0x3ad3, 0x26f7, 0x3ae6, 0x2725, 0x3afa, 0x2754, 0x3b0e,
+  0x2782, 0x3b21, 0x27b1, 0x3b34, 0x27df, 0x3b47, 0x280e, 0x3b5a,
+  0x283c, 0x3b6d, 0x286b, 0x3b7f, 0x289a, 0x3b92, 0x28c9, 0x3ba4,
+  0x28f7, 0x3bb6, 0x2926, 0x3bc8, 0x2955, 0x3bda, 0x2984, 0x3bec,
+  0x29b4, 0x3bfd, 0x29e3, 0x3c0f, 0x2a12, 0x3c20, 0x2a41, 0x3c31,
+  0x2a70, 0x3c42, 0x2aa0, 0x3c53, 0x2acf, 0x3c64, 0x2aff, 0x3c74,
+  0x2b2e, 0x3c85, 0x2b5e, 0x3c95, 0x2b8d, 0x3ca5, 0x2bbd, 0x3cb5,
+  0x2bed, 0x3cc5, 0x2c1c, 0x3cd5, 0x2c4c, 0x3ce4, 0x2c7c, 0x3cf4,
+  0x2cac, 0x3d03, 0x2cdc, 0x3d12, 0x2d0c, 0x3d21, 0x2d3c, 0x3d30,
+  0x2d6c, 0x3d3f, 0x2d9c, 0x3d4d, 0x2dcc, 0x3d5b, 0x2dfc, 0x3d6a,
+  0x2e2d, 0x3d78, 0x2e5d, 0x3d86, 0x2e8d, 0x3d93, 0x2ebe, 0x3da1,
+  0x2eee, 0x3daf, 0x2f1f, 0x3dbc, 0x2f4f, 0x3dc9, 0x2f80, 0x3dd6,
+  0x2fb0, 0x3de3, 0x2fe1, 0x3df0, 0x3012, 0x3dfc, 0x3042, 0x3e09,
+  0x3073, 0x3e15, 0x30a4, 0x3e21, 0x30d5, 0x3e2d, 0x3105, 0x3e39,
+  0x3136, 0x3e45, 0x3167, 0x3e50, 0x3198, 0x3e5c, 0x31c9, 0x3e67,
+  0x31fa, 0x3e72, 0x322b, 0x3e7d, 0x325c, 0x3e88, 0x328e, 0x3e92,
+  0x32bf, 0x3e9d, 0x32f0, 0x3ea7, 0x3321, 0x3eb1, 0x3352, 0x3ebb,
+  0x3384, 0x3ec5, 0x33b5, 0x3ecf, 0x33e6, 0x3ed8, 0x3418, 0x3ee2,
+  0x3449, 0x3eeb, 0x347b, 0x3ef4, 0x34ac, 0x3efd, 0x34dd, 0x3f06,
+  0x350f, 0x3f0f, 0x3540, 0x3f17, 0x3572, 0x3f20, 0x35a4, 0x3f28,
+  0x35d5, 0x3f30, 0x3607, 0x3f38, 0x3639, 0x3f40, 0x366a, 0x3f47,
+  0x369c, 0x3f4f, 0x36ce, 0x3f56, 0x36ff, 0x3f5d, 0x3731, 0x3f64,
+  0x3763, 0x3f6b, 0x3795, 0x3f72, 0x37c7, 0x3f78, 0x37f9, 0x3f7f,
+  0x382a, 0x3f85, 0x385c, 0x3f8b, 0x388e, 0x3f91, 0x38c0, 0x3f97,
+  0x38f2, 0x3f9c, 0x3924, 0x3fa2, 0x3956, 0x3fa7, 0x3988, 0x3fac,
+  0x39ba, 0x3fb1, 0x39ec, 0x3fb6, 0x3a1e, 0x3fbb, 0x3a50, 0x3fbf,
+  0x3a82, 0x3fc4, 0x3ab4, 0x3fc8, 0x3ae6, 0x3fcc, 0x3b19, 0x3fd0,
+  0x3b4b, 0x3fd4, 0x3b7d, 0x3fd7, 0x3baf, 0x3fdb, 0x3be1, 0x3fde,
+  0x3c13, 0x3fe1, 0x3c45, 0x3fe4, 0x3c78, 0x3fe7, 0x3caa, 0x3fea,
+  0x3cdc, 0x3fec, 0x3d0e, 0x3fef, 0x3d40, 0x3ff1, 0x3d73, 0x3ff3,
+  0x3da5, 0x3ff5, 0x3dd7, 0x3ff7, 0x3e09, 0x3ff8, 0x3e3c, 0x3ffa,
+  0x3e6e, 0x3ffb, 0x3ea0, 0x3ffc, 0x3ed2, 0x3ffd, 0x3f05, 0x3ffe,
+  0x3f37, 0x3fff, 0x3f69, 0x3fff, 0x3f9b, 0x4000, 0x3fce, 0x4000
+};
+
+/**   
+* \par  
+* Generation of real_CoefB array:   
+* \par   
+* n = 1024   
+* 
    for (i = 0; i < n; i++)   
+*  {   
+*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));   
+*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+*  } 
      
+* \par   
+* Convert to fixed point Q15 format   
+*       round(pBTable[i] * pow(2, 15))   
+*   
+*/
+
+static const q15_t realCoefBQ15[2048] = {
+  0x4000, 0x4000, 0x4032, 0x4000, 0x4065, 0x4000, 0x4097, 0x3fff,
+  0x40c9, 0x3fff, 0x40fb, 0x3ffe, 0x412e, 0x3ffd, 0x4160, 0x3ffc,
+  0x4192, 0x3ffb, 0x41c4, 0x3ffa, 0x41f7, 0x3ff8, 0x4229, 0x3ff7,
+  0x425b, 0x3ff5, 0x428d, 0x3ff3, 0x42c0, 0x3ff1, 0x42f2, 0x3fef,
+  0x4324, 0x3fec, 0x4356, 0x3fea, 0x4388, 0x3fe7, 0x43bb, 0x3fe4,
+  0x43ed, 0x3fe1, 0x441f, 0x3fde, 0x4451, 0x3fdb, 0x4483, 0x3fd7,
+  0x44b5, 0x3fd4, 0x44e7, 0x3fd0, 0x451a, 0x3fcc, 0x454c, 0x3fc8,
+  0x457e, 0x3fc4, 0x45b0, 0x3fbf, 0x45e2, 0x3fbb, 0x4614, 0x3fb6,
+  0x4646, 0x3fb1, 0x4678, 0x3fac, 0x46aa, 0x3fa7, 0x46dc, 0x3fa2,
+  0x470e, 0x3f9c, 0x4740, 0x3f97, 0x4772, 0x3f91, 0x47a4, 0x3f8b,
+  0x47d6, 0x3f85, 0x4807, 0x3f7f, 0x4839, 0x3f78, 0x486b, 0x3f72,
+  0x489d, 0x3f6b, 0x48cf, 0x3f64, 0x4901, 0x3f5d, 0x4932, 0x3f56,
+  0x4964, 0x3f4f, 0x4996, 0x3f47, 0x49c7, 0x3f40, 0x49f9, 0x3f38,
+  0x4a2b, 0x3f30, 0x4a5c, 0x3f28, 0x4a8e, 0x3f20, 0x4ac0, 0x3f17,
+  0x4af1, 0x3f0f, 0x4b23, 0x3f06, 0x4b54, 0x3efd, 0x4b85, 0x3ef4,
+  0x4bb7, 0x3eeb, 0x4be8, 0x3ee2, 0x4c1a, 0x3ed8, 0x4c4b, 0x3ecf,
+  0x4c7c, 0x3ec5, 0x4cae, 0x3ebb, 0x4cdf, 0x3eb1, 0x4d10, 0x3ea7,
+  0x4d41, 0x3e9d, 0x4d72, 0x3e92, 0x4da4, 0x3e88, 0x4dd5, 0x3e7d,
+  0x4e06, 0x3e72, 0x4e37, 0x3e67, 0x4e68, 0x3e5c, 0x4e99, 0x3e50,
+  0x4eca, 0x3e45, 0x4efb, 0x3e39, 0x4f2b, 0x3e2d, 0x4f5c, 0x3e21,
+  0x4f8d, 0x3e15, 0x4fbe, 0x3e09, 0x4fee, 0x3dfc, 0x501f, 0x3df0,
+  0x5050, 0x3de3, 0x5080, 0x3dd6, 0x50b1, 0x3dc9, 0x50e1, 0x3dbc,
+  0x5112, 0x3daf, 0x5142, 0x3da1, 0x5173, 0x3d93, 0x51a3, 0x3d86,
+  0x51d3, 0x3d78, 0x5204, 0x3d6a, 0x5234, 0x3d5b, 0x5264, 0x3d4d,
+  0x5294, 0x3d3f, 0x52c4, 0x3d30, 0x52f4, 0x3d21, 0x5324, 0x3d12,
+  0x5354, 0x3d03, 0x5384, 0x3cf4, 0x53b4, 0x3ce4, 0x53e4, 0x3cd5,
+  0x5413, 0x3cc5, 0x5443, 0x3cb5, 0x5473, 0x3ca5, 0x54a2, 0x3c95,
+  0x54d2, 0x3c85, 0x5501, 0x3c74, 0x5531, 0x3c64, 0x5560, 0x3c53,
+  0x5590, 0x3c42, 0x55bf, 0x3c31, 0x55ee, 0x3c20, 0x561d, 0x3c0f,
+  0x564c, 0x3bfd, 0x567c, 0x3bec, 0x56ab, 0x3bda, 0x56da, 0x3bc8,
+  0x5709, 0x3bb6, 0x5737, 0x3ba4, 0x5766, 0x3b92, 0x5795, 0x3b7f,
+  0x57c4, 0x3b6d, 0x57f2, 0x3b5a, 0x5821, 0x3b47, 0x584f, 0x3b34,
+  0x587e, 0x3b21, 0x58ac, 0x3b0e, 0x58db, 0x3afa, 0x5909, 0x3ae6,
+  0x5937, 0x3ad3, 0x5965, 0x3abf, 0x5993, 0x3aab, 0x59c1, 0x3a97,
+  0x59ef, 0x3a82, 0x5a1d, 0x3a6e, 0x5a4b, 0x3a59, 0x5a79, 0x3a45,
+  0x5aa7, 0x3a30, 0x5ad4, 0x3a1b, 0x5b02, 0x3a06, 0x5b30, 0x39f0,
+  0x5b5d, 0x39db, 0x5b8a, 0x39c5, 0x5bb8, 0x39b0, 0x5be5, 0x399a,
+  0x5c12, 0x3984, 0x5c3f, 0x396e, 0x5c6c, 0x3958, 0x5c99, 0x3941,
+  0x5cc6, 0x392b, 0x5cf3, 0x3914, 0x5d20, 0x38fd, 0x5d4d, 0x38e6,
+  0x5d79, 0x38cf, 0x5da6, 0x38b8, 0x5dd3, 0x38a1, 0x5dff, 0x3889,
+  0x5e2b, 0x3871, 0x5e58, 0x385a, 0x5e84, 0x3842, 0x5eb0, 0x382a,
+  0x5edc, 0x3812, 0x5f08, 0x37f9, 0x5f34, 0x37e1, 0x5f60, 0x37c8,
+  0x5f8c, 0x37b0, 0x5fb7, 0x3797, 0x5fe3, 0x377e, 0x600f, 0x3765,
+  0x603a, 0x374b, 0x6065, 0x3732, 0x6091, 0x3718, 0x60bc, 0x36ff,
+  0x60e7, 0x36e5, 0x6112, 0x36cb, 0x613d, 0x36b1, 0x6168, 0x3697,
+  0x6193, 0x367d, 0x61be, 0x3662, 0x61e8, 0x3648, 0x6213, 0x362d,
+  0x623d, 0x3612, 0x6268, 0x35f7, 0x6292, 0x35dc, 0x62bc, 0x35c1,
+  0x62e7, 0x35a5, 0x6311, 0x358a, 0x633b, 0x356e, 0x6365, 0x3553,
+  0x638e, 0x3537, 0x63b8, 0x351b, 0x63e2, 0x34ff, 0x640b, 0x34e2,
+  0x6435, 0x34c6, 0x645e, 0x34aa, 0x6488, 0x348d, 0x64b1, 0x3470,
+  0x64da, 0x3453, 0x6503, 0x3436, 0x652c, 0x3419, 0x6555, 0x33fc,
+  0x657e, 0x33df, 0x65a6, 0x33c1, 0x65cf, 0x33a3, 0x65f8, 0x3386,
+  0x6620, 0x3368, 0x6648, 0x334a, 0x6671, 0x332c, 0x6699, 0x330d,
+  0x66c1, 0x32ef, 0x66e9, 0x32d0, 0x6711, 0x32b2, 0x6738, 0x3293,
+  0x6760, 0x3274, 0x6788, 0x3255, 0x67af, 0x3236, 0x67d6, 0x3217,
+  0x67fe, 0x31f8, 0x6825, 0x31d8, 0x684c, 0x31b9, 0x6873, 0x3199,
+  0x689a, 0x3179, 0x68c1, 0x3159, 0x68e7, 0x3139, 0x690e, 0x3119,
+  0x6935, 0x30f9, 0x695b, 0x30d8, 0x6981, 0x30b8, 0x69a7, 0x3097,
+  0x69ce, 0x3076, 0x69f4, 0x3055, 0x6a1a, 0x3034, 0x6a3f, 0x3013,
+  0x6a65, 0x2ff2, 0x6a8b, 0x2fd0, 0x6ab0, 0x2faf, 0x6ad6, 0x2f8d,
+  0x6afb, 0x2f6c, 0x6b20, 0x2f4a, 0x6b45, 0x2f28, 0x6b6a, 0x2f06,
+  0x6b8f, 0x2ee4, 0x6bb4, 0x2ec2, 0x6bd8, 0x2e9f, 0x6bfd, 0x2e7d,
+  0x6c21, 0x2e5a, 0x6c46, 0x2e37, 0x6c6a, 0x2e15, 0x6c8e, 0x2df2,
+  0x6cb2, 0x2dcf, 0x6cd6, 0x2dab, 0x6cfa, 0x2d88, 0x6d1e, 0x2d65,
+  0x6d41, 0x2d41, 0x6d65, 0x2d1e, 0x6d88, 0x2cfa, 0x6dab, 0x2cd6,
+  0x6dcf, 0x2cb2, 0x6df2, 0x2c8e, 0x6e15, 0x2c6a, 0x6e37, 0x2c46,
+  0x6e5a, 0x2c21, 0x6e7d, 0x2bfd, 0x6e9f, 0x2bd8, 0x6ec2, 0x2bb4,
+  0x6ee4, 0x2b8f, 0x6f06, 0x2b6a, 0x6f28, 0x2b45, 0x6f4a, 0x2b20,
+  0x6f6c, 0x2afb, 0x6f8d, 0x2ad6, 0x6faf, 0x2ab0, 0x6fd0, 0x2a8b,
+  0x6ff2, 0x2a65, 0x7013, 0x2a3f, 0x7034, 0x2a1a, 0x7055, 0x29f4,
+  0x7076, 0x29ce, 0x7097, 0x29a7, 0x70b8, 0x2981, 0x70d8, 0x295b,
+  0x70f9, 0x2935, 0x7119, 0x290e, 0x7139, 0x28e7, 0x7159, 0x28c1,
+  0x7179, 0x289a, 0x7199, 0x2873, 0x71b9, 0x284c, 0x71d8, 0x2825,
+  0x71f8, 0x27fe, 0x7217, 0x27d6, 0x7236, 0x27af, 0x7255, 0x2788,
+  0x7274, 0x2760, 0x7293, 0x2738, 0x72b2, 0x2711, 0x72d0, 0x26e9,
+  0x72ef, 0x26c1, 0x730d, 0x2699, 0x732c, 0x2671, 0x734a, 0x2648,
+  0x7368, 0x2620, 0x7386, 0x25f8, 0x73a3, 0x25cf, 0x73c1, 0x25a6,
+  0x73df, 0x257e, 0x73fc, 0x2555, 0x7419, 0x252c, 0x7436, 0x2503,
+  0x7453, 0x24da, 0x7470, 0x24b1, 0x748d, 0x2488, 0x74aa, 0x245e,
+  0x74c6, 0x2435, 0x74e2, 0x240b, 0x74ff, 0x23e2, 0x751b, 0x23b8,
+  0x7537, 0x238e, 0x7553, 0x2365, 0x756e, 0x233b, 0x758a, 0x2311,
+  0x75a5, 0x22e7, 0x75c1, 0x22bc, 0x75dc, 0x2292, 0x75f7, 0x2268,
+  0x7612, 0x223d, 0x762d, 0x2213, 0x7648, 0x21e8, 0x7662, 0x21be,
+  0x767d, 0x2193, 0x7697, 0x2168, 0x76b1, 0x213d, 0x76cb, 0x2112,
+  0x76e5, 0x20e7, 0x76ff, 0x20bc, 0x7718, 0x2091, 0x7732, 0x2065,
+  0x774b, 0x203a, 0x7765, 0x200f, 0x777e, 0x1fe3, 0x7797, 0x1fb7,
+  0x77b0, 0x1f8c, 0x77c8, 0x1f60, 0x77e1, 0x1f34, 0x77f9, 0x1f08,
+  0x7812, 0x1edc, 0x782a, 0x1eb0, 0x7842, 0x1e84, 0x785a, 0x1e58,
+  0x7871, 0x1e2b, 0x7889, 0x1dff, 0x78a1, 0x1dd3, 0x78b8, 0x1da6,
+  0x78cf, 0x1d79, 0x78e6, 0x1d4d, 0x78fd, 0x1d20, 0x7914, 0x1cf3,
+  0x792b, 0x1cc6, 0x7941, 0x1c99, 0x7958, 0x1c6c, 0x796e, 0x1c3f,
+  0x7984, 0x1c12, 0x799a, 0x1be5, 0x79b0, 0x1bb8, 0x79c5, 0x1b8a,
+  0x79db, 0x1b5d, 0x79f0, 0x1b30, 0x7a06, 0x1b02, 0x7a1b, 0x1ad4,
+  0x7a30, 0x1aa7, 0x7a45, 0x1a79, 0x7a59, 0x1a4b, 0x7a6e, 0x1a1d,
+  0x7a82, 0x19ef, 0x7a97, 0x19c1, 0x7aab, 0x1993, 0x7abf, 0x1965,
+  0x7ad3, 0x1937, 0x7ae6, 0x1909, 0x7afa, 0x18db, 0x7b0e, 0x18ac,
+  0x7b21, 0x187e, 0x7b34, 0x184f, 0x7b47, 0x1821, 0x7b5a, 0x17f2,
+  0x7b6d, 0x17c4, 0x7b7f, 0x1795, 0x7b92, 0x1766, 0x7ba4, 0x1737,
+  0x7bb6, 0x1709, 0x7bc8, 0x16da, 0x7bda, 0x16ab, 0x7bec, 0x167c,
+  0x7bfd, 0x164c, 0x7c0f, 0x161d, 0x7c20, 0x15ee, 0x7c31, 0x15bf,
+  0x7c42, 0x1590, 0x7c53, 0x1560, 0x7c64, 0x1531, 0x7c74, 0x1501,
+  0x7c85, 0x14d2, 0x7c95, 0x14a2, 0x7ca5, 0x1473, 0x7cb5, 0x1443,
+  0x7cc5, 0x1413, 0x7cd5, 0x13e4, 0x7ce4, 0x13b4, 0x7cf4, 0x1384,
+  0x7d03, 0x1354, 0x7d12, 0x1324, 0x7d21, 0x12f4, 0x7d30, 0x12c4,
+  0x7d3f, 0x1294, 0x7d4d, 0x1264, 0x7d5b, 0x1234, 0x7d6a, 0x1204,
+  0x7d78, 0x11d3, 0x7d86, 0x11a3, 0x7d93, 0x1173, 0x7da1, 0x1142,
+  0x7daf, 0x1112, 0x7dbc, 0x10e1, 0x7dc9, 0x10b1, 0x7dd6, 0x1080,
+  0x7de3, 0x1050, 0x7df0, 0x101f, 0x7dfc, 0xfee, 0x7e09, 0xfbe,
+  0x7e15, 0xf8d, 0x7e21, 0xf5c, 0x7e2d, 0xf2b, 0x7e39, 0xefb,
+  0x7e45, 0xeca, 0x7e50, 0xe99, 0x7e5c, 0xe68, 0x7e67, 0xe37,
+  0x7e72, 0xe06, 0x7e7d, 0xdd5, 0x7e88, 0xda4, 0x7e92, 0xd72,
+  0x7e9d, 0xd41, 0x7ea7, 0xd10, 0x7eb1, 0xcdf, 0x7ebb, 0xcae,
+  0x7ec5, 0xc7c, 0x7ecf, 0xc4b, 0x7ed8, 0xc1a, 0x7ee2, 0xbe8,
+  0x7eeb, 0xbb7, 0x7ef4, 0xb85, 0x7efd, 0xb54, 0x7f06, 0xb23,
+  0x7f0f, 0xaf1, 0x7f17, 0xac0, 0x7f20, 0xa8e, 0x7f28, 0xa5c,
+  0x7f30, 0xa2b, 0x7f38, 0x9f9, 0x7f40, 0x9c7, 0x7f47, 0x996,
+  0x7f4f, 0x964, 0x7f56, 0x932, 0x7f5d, 0x901, 0x7f64, 0x8cf,
+  0x7f6b, 0x89d, 0x7f72, 0x86b, 0x7f78, 0x839, 0x7f7f, 0x807,
+  0x7f85, 0x7d6, 0x7f8b, 0x7a4, 0x7f91, 0x772, 0x7f97, 0x740,
+  0x7f9c, 0x70e, 0x7fa2, 0x6dc, 0x7fa7, 0x6aa, 0x7fac, 0x678,
+  0x7fb1, 0x646, 0x7fb6, 0x614, 0x7fbb, 0x5e2, 0x7fbf, 0x5b0,
+  0x7fc4, 0x57e, 0x7fc8, 0x54c, 0x7fcc, 0x51a, 0x7fd0, 0x4e7,
+  0x7fd4, 0x4b5, 0x7fd7, 0x483, 0x7fdb, 0x451, 0x7fde, 0x41f,
+  0x7fe1, 0x3ed, 0x7fe4, 0x3bb, 0x7fe7, 0x388, 0x7fea, 0x356,
+  0x7fec, 0x324, 0x7fef, 0x2f2, 0x7ff1, 0x2c0, 0x7ff3, 0x28d,
+  0x7ff5, 0x25b, 0x7ff7, 0x229, 0x7ff8, 0x1f7, 0x7ffa, 0x1c4,
+  0x7ffb, 0x192, 0x7ffc, 0x160, 0x7ffd, 0x12e, 0x7ffe, 0xfb,
+  0x7fff, 0xc9, 0x7fff, 0x97, 0x7fff, 0x65, 0x7fff, 0x32,
+  0x7fff, 0x0, 0x7fff, 0xffce, 0x7fff, 0xff9b, 0x7fff, 0xff69,
+  0x7fff, 0xff37, 0x7ffe, 0xff05, 0x7ffd, 0xfed2, 0x7ffc, 0xfea0,
+  0x7ffb, 0xfe6e, 0x7ffa, 0xfe3c, 0x7ff8, 0xfe09, 0x7ff7, 0xfdd7,
+  0x7ff5, 0xfda5, 0x7ff3, 0xfd73, 0x7ff1, 0xfd40, 0x7fef, 0xfd0e,
+  0x7fec, 0xfcdc, 0x7fea, 0xfcaa, 0x7fe7, 0xfc78, 0x7fe4, 0xfc45,
+  0x7fe1, 0xfc13, 0x7fde, 0xfbe1, 0x7fdb, 0xfbaf, 0x7fd7, 0xfb7d,
+  0x7fd4, 0xfb4b, 0x7fd0, 0xfb19, 0x7fcc, 0xfae6, 0x7fc8, 0xfab4,
+  0x7fc4, 0xfa82, 0x7fbf, 0xfa50, 0x7fbb, 0xfa1e, 0x7fb6, 0xf9ec,
+  0x7fb1, 0xf9ba, 0x7fac, 0xf988, 0x7fa7, 0xf956, 0x7fa2, 0xf924,
+  0x7f9c, 0xf8f2, 0x7f97, 0xf8c0, 0x7f91, 0xf88e, 0x7f8b, 0xf85c,
+  0x7f85, 0xf82a, 0x7f7f, 0xf7f9, 0x7f78, 0xf7c7, 0x7f72, 0xf795,
+  0x7f6b, 0xf763, 0x7f64, 0xf731, 0x7f5d, 0xf6ff, 0x7f56, 0xf6ce,
+  0x7f4f, 0xf69c, 0x7f47, 0xf66a, 0x7f40, 0xf639, 0x7f38, 0xf607,
+  0x7f30, 0xf5d5, 0x7f28, 0xf5a4, 0x7f20, 0xf572, 0x7f17, 0xf540,
+  0x7f0f, 0xf50f, 0x7f06, 0xf4dd, 0x7efd, 0xf4ac, 0x7ef4, 0xf47b,
+  0x7eeb, 0xf449, 0x7ee2, 0xf418, 0x7ed8, 0xf3e6, 0x7ecf, 0xf3b5,
+  0x7ec5, 0xf384, 0x7ebb, 0xf352, 0x7eb1, 0xf321, 0x7ea7, 0xf2f0,
+  0x7e9d, 0xf2bf, 0x7e92, 0xf28e, 0x7e88, 0xf25c, 0x7e7d, 0xf22b,
+  0x7e72, 0xf1fa, 0x7e67, 0xf1c9, 0x7e5c, 0xf198, 0x7e50, 0xf167,
+  0x7e45, 0xf136, 0x7e39, 0xf105, 0x7e2d, 0xf0d5, 0x7e21, 0xf0a4,
+  0x7e15, 0xf073, 0x7e09, 0xf042, 0x7dfc, 0xf012, 0x7df0, 0xefe1,
+  0x7de3, 0xefb0, 0x7dd6, 0xef80, 0x7dc9, 0xef4f, 0x7dbc, 0xef1f,
+  0x7daf, 0xeeee, 0x7da1, 0xeebe, 0x7d93, 0xee8d, 0x7d86, 0xee5d,
+  0x7d78, 0xee2d, 0x7d6a, 0xedfc, 0x7d5b, 0xedcc, 0x7d4d, 0xed9c,
+  0x7d3f, 0xed6c, 0x7d30, 0xed3c, 0x7d21, 0xed0c, 0x7d12, 0xecdc,
+  0x7d03, 0xecac, 0x7cf4, 0xec7c, 0x7ce4, 0xec4c, 0x7cd5, 0xec1c,
+  0x7cc5, 0xebed, 0x7cb5, 0xebbd, 0x7ca5, 0xeb8d, 0x7c95, 0xeb5e,
+  0x7c85, 0xeb2e, 0x7c74, 0xeaff, 0x7c64, 0xeacf, 0x7c53, 0xeaa0,
+  0x7c42, 0xea70, 0x7c31, 0xea41, 0x7c20, 0xea12, 0x7c0f, 0xe9e3,
+  0x7bfd, 0xe9b4, 0x7bec, 0xe984, 0x7bda, 0xe955, 0x7bc8, 0xe926,
+  0x7bb6, 0xe8f7, 0x7ba4, 0xe8c9, 0x7b92, 0xe89a, 0x7b7f, 0xe86b,
+  0x7b6d, 0xe83c, 0x7b5a, 0xe80e, 0x7b47, 0xe7df, 0x7b34, 0xe7b1,
+  0x7b21, 0xe782, 0x7b0e, 0xe754, 0x7afa, 0xe725, 0x7ae6, 0xe6f7,
+  0x7ad3, 0xe6c9, 0x7abf, 0xe69b, 0x7aab, 0xe66d, 0x7a97, 0xe63f,
+  0x7a82, 0xe611, 0x7a6e, 0xe5e3, 0x7a59, 0xe5b5, 0x7a45, 0xe587,
+  0x7a30, 0xe559, 0x7a1b, 0xe52c, 0x7a06, 0xe4fe, 0x79f0, 0xe4d0,
+  0x79db, 0xe4a3, 0x79c5, 0xe476, 0x79b0, 0xe448, 0x799a, 0xe41b,
+  0x7984, 0xe3ee, 0x796e, 0xe3c1, 0x7958, 0xe394, 0x7941, 0xe367,
+  0x792b, 0xe33a, 0x7914, 0xe30d, 0x78fd, 0xe2e0, 0x78e6, 0xe2b3,
+  0x78cf, 0xe287, 0x78b8, 0xe25a, 0x78a1, 0xe22d, 0x7889, 0xe201,
+  0x7871, 0xe1d5, 0x785a, 0xe1a8, 0x7842, 0xe17c, 0x782a, 0xe150,
+  0x7812, 0xe124, 0x77f9, 0xe0f8, 0x77e1, 0xe0cc, 0x77c8, 0xe0a0,
+  0x77b0, 0xe074, 0x7797, 0xe049, 0x777e, 0xe01d, 0x7765, 0xdff1,
+  0x774b, 0xdfc6, 0x7732, 0xdf9b, 0x7718, 0xdf6f, 0x76ff, 0xdf44,
+  0x76e5, 0xdf19, 0x76cb, 0xdeee, 0x76b1, 0xdec3, 0x7697, 0xde98,
+  0x767d, 0xde6d, 0x7662, 0xde42, 0x7648, 0xde18, 0x762d, 0xdded,
+  0x7612, 0xddc3, 0x75f7, 0xdd98, 0x75dc, 0xdd6e, 0x75c1, 0xdd44,
+  0x75a5, 0xdd19, 0x758a, 0xdcef, 0x756e, 0xdcc5, 0x7553, 0xdc9b,
+  0x7537, 0xdc72, 0x751b, 0xdc48, 0x74ff, 0xdc1e, 0x74e2, 0xdbf5,
+  0x74c6, 0xdbcb, 0x74aa, 0xdba2, 0x748d, 0xdb78, 0x7470, 0xdb4f,
+  0x7453, 0xdb26, 0x7436, 0xdafd, 0x7419, 0xdad4, 0x73fc, 0xdaab,
+  0x73df, 0xda82, 0x73c1, 0xda5a, 0x73a3, 0xda31, 0x7386, 0xda08,
+  0x7368, 0xd9e0, 0x734a, 0xd9b8, 0x732c, 0xd98f, 0x730d, 0xd967,
+  0x72ef, 0xd93f, 0x72d0, 0xd917, 0x72b2, 0xd8ef, 0x7293, 0xd8c8,
+  0x7274, 0xd8a0, 0x7255, 0xd878, 0x7236, 0xd851, 0x7217, 0xd82a,
+  0x71f8, 0xd802, 0x71d8, 0xd7db, 0x71b9, 0xd7b4, 0x7199, 0xd78d,
+  0x7179, 0xd766, 0x7159, 0xd73f, 0x7139, 0xd719, 0x7119, 0xd6f2,
+  0x70f9, 0xd6cb, 0x70d8, 0xd6a5, 0x70b8, 0xd67f, 0x7097, 0xd659,
+  0x7076, 0xd632, 0x7055, 0xd60c, 0x7034, 0xd5e6, 0x7013, 0xd5c1,
+  0x6ff2, 0xd59b, 0x6fd0, 0xd575, 0x6faf, 0xd550, 0x6f8d, 0xd52a,
+  0x6f6c, 0xd505, 0x6f4a, 0xd4e0, 0x6f28, 0xd4bb, 0x6f06, 0xd496,
+  0x6ee4, 0xd471, 0x6ec2, 0xd44c, 0x6e9f, 0xd428, 0x6e7d, 0xd403,
+  0x6e5a, 0xd3df, 0x6e37, 0xd3ba, 0x6e15, 0xd396, 0x6df2, 0xd372,
+  0x6dcf, 0xd34e, 0x6dab, 0xd32a, 0x6d88, 0xd306, 0x6d65, 0xd2e2,
+  0x6d41, 0xd2bf, 0x6d1e, 0xd29b, 0x6cfa, 0xd278, 0x6cd6, 0xd255,
+  0x6cb2, 0xd231, 0x6c8e, 0xd20e, 0x6c6a, 0xd1eb, 0x6c46, 0xd1c9,
+  0x6c21, 0xd1a6, 0x6bfd, 0xd183, 0x6bd8, 0xd161, 0x6bb4, 0xd13e,
+  0x6b8f, 0xd11c, 0x6b6a, 0xd0fa, 0x6b45, 0xd0d8, 0x6b20, 0xd0b6,
+  0x6afb, 0xd094, 0x6ad6, 0xd073, 0x6ab0, 0xd051, 0x6a8b, 0xd030,
+  0x6a65, 0xd00e, 0x6a3f, 0xcfed, 0x6a1a, 0xcfcc, 0x69f4, 0xcfab,
+  0x69ce, 0xcf8a, 0x69a7, 0xcf69, 0x6981, 0xcf48, 0x695b, 0xcf28,
+  0x6935, 0xcf07, 0x690e, 0xcee7, 0x68e7, 0xcec7, 0x68c1, 0xcea7,
+  0x689a, 0xce87, 0x6873, 0xce67, 0x684c, 0xce47, 0x6825, 0xce28,
+  0x67fe, 0xce08, 0x67d6, 0xcde9, 0x67af, 0xcdca, 0x6788, 0xcdab,
+  0x6760, 0xcd8c, 0x6738, 0xcd6d, 0x6711, 0xcd4e, 0x66e9, 0xcd30,
+  0x66c1, 0xcd11, 0x6699, 0xccf3, 0x6671, 0xccd4, 0x6648, 0xccb6,
+  0x6620, 0xcc98, 0x65f8, 0xcc7a, 0x65cf, 0xcc5d, 0x65a6, 0xcc3f,
+  0x657e, 0xcc21, 0x6555, 0xcc04, 0x652c, 0xcbe7, 0x6503, 0xcbca,
+  0x64da, 0xcbad, 0x64b1, 0xcb90, 0x6488, 0xcb73, 0x645e, 0xcb56,
+  0x6435, 0xcb3a, 0x640b, 0xcb1e, 0x63e2, 0xcb01, 0x63b8, 0xcae5,
+  0x638e, 0xcac9, 0x6365, 0xcaad, 0x633b, 0xca92, 0x6311, 0xca76,
+  0x62e7, 0xca5b, 0x62bc, 0xca3f, 0x6292, 0xca24, 0x6268, 0xca09,
+  0x623d, 0xc9ee, 0x6213, 0xc9d3, 0x61e8, 0xc9b8, 0x61be, 0xc99e,
+  0x6193, 0xc983, 0x6168, 0xc969, 0x613d, 0xc94f, 0x6112, 0xc935,
+  0x60e7, 0xc91b, 0x60bc, 0xc901, 0x6091, 0xc8e8, 0x6065, 0xc8ce,
+  0x603a, 0xc8b5, 0x600f, 0xc89b, 0x5fe3, 0xc882, 0x5fb7, 0xc869,
+  0x5f8c, 0xc850, 0x5f60, 0xc838, 0x5f34, 0xc81f, 0x5f08, 0xc807,
+  0x5edc, 0xc7ee, 0x5eb0, 0xc7d6, 0x5e84, 0xc7be, 0x5e58, 0xc7a6,
+  0x5e2b, 0xc78f, 0x5dff, 0xc777, 0x5dd3, 0xc75f, 0x5da6, 0xc748,
+  0x5d79, 0xc731, 0x5d4d, 0xc71a, 0x5d20, 0xc703, 0x5cf3, 0xc6ec,
+  0x5cc6, 0xc6d5, 0x5c99, 0xc6bf, 0x5c6c, 0xc6a8, 0x5c3f, 0xc692,
+  0x5c12, 0xc67c, 0x5be5, 0xc666, 0x5bb8, 0xc650, 0x5b8a, 0xc63b,
+  0x5b5d, 0xc625, 0x5b30, 0xc610, 0x5b02, 0xc5fa, 0x5ad4, 0xc5e5,
+  0x5aa7, 0xc5d0, 0x5a79, 0xc5bb, 0x5a4b, 0xc5a7, 0x5a1d, 0xc592,
+  0x59ef, 0xc57e, 0x59c1, 0xc569, 0x5993, 0xc555, 0x5965, 0xc541,
+  0x5937, 0xc52d, 0x5909, 0xc51a, 0x58db, 0xc506, 0x58ac, 0xc4f2,
+  0x587e, 0xc4df, 0x584f, 0xc4cc, 0x5821, 0xc4b9, 0x57f2, 0xc4a6,
+  0x57c4, 0xc493, 0x5795, 0xc481, 0x5766, 0xc46e, 0x5737, 0xc45c,
+  0x5709, 0xc44a, 0x56da, 0xc438, 0x56ab, 0xc426, 0x567c, 0xc414,
+  0x564c, 0xc403, 0x561d, 0xc3f1, 0x55ee, 0xc3e0, 0x55bf, 0xc3cf,
+  0x5590, 0xc3be, 0x5560, 0xc3ad, 0x5531, 0xc39c, 0x5501, 0xc38c,
+  0x54d2, 0xc37b, 0x54a2, 0xc36b, 0x5473, 0xc35b, 0x5443, 0xc34b,
+  0x5413, 0xc33b, 0x53e4, 0xc32b, 0x53b4, 0xc31c, 0x5384, 0xc30c,
+  0x5354, 0xc2fd, 0x5324, 0xc2ee, 0x52f4, 0xc2df, 0x52c4, 0xc2d0,
+  0x5294, 0xc2c1, 0x5264, 0xc2b3, 0x5234, 0xc2a5, 0x5204, 0xc296,
+  0x51d3, 0xc288, 0x51a3, 0xc27a, 0x5173, 0xc26d, 0x5142, 0xc25f,
+  0x5112, 0xc251, 0x50e1, 0xc244, 0x50b1, 0xc237, 0x5080, 0xc22a,
+  0x5050, 0xc21d, 0x501f, 0xc210, 0x4fee, 0xc204, 0x4fbe, 0xc1f7,
+  0x4f8d, 0xc1eb, 0x4f5c, 0xc1df, 0x4f2b, 0xc1d3, 0x4efb, 0xc1c7,
+  0x4eca, 0xc1bb, 0x4e99, 0xc1b0, 0x4e68, 0xc1a4, 0x4e37, 0xc199,
+  0x4e06, 0xc18e, 0x4dd5, 0xc183, 0x4da4, 0xc178, 0x4d72, 0xc16e,
+  0x4d41, 0xc163, 0x4d10, 0xc159, 0x4cdf, 0xc14f, 0x4cae, 0xc145,
+  0x4c7c, 0xc13b, 0x4c4b, 0xc131, 0x4c1a, 0xc128, 0x4be8, 0xc11e,
+  0x4bb7, 0xc115, 0x4b85, 0xc10c, 0x4b54, 0xc103, 0x4b23, 0xc0fa,
+  0x4af1, 0xc0f1, 0x4ac0, 0xc0e9, 0x4a8e, 0xc0e0, 0x4a5c, 0xc0d8,
+  0x4a2b, 0xc0d0, 0x49f9, 0xc0c8, 0x49c7, 0xc0c0, 0x4996, 0xc0b9,
+  0x4964, 0xc0b1, 0x4932, 0xc0aa, 0x4901, 0xc0a3, 0x48cf, 0xc09c,
+  0x489d, 0xc095, 0x486b, 0xc08e, 0x4839, 0xc088, 0x4807, 0xc081,
+  0x47d6, 0xc07b, 0x47a4, 0xc075, 0x4772, 0xc06f, 0x4740, 0xc069,
+  0x470e, 0xc064, 0x46dc, 0xc05e, 0x46aa, 0xc059, 0x4678, 0xc054,
+  0x4646, 0xc04f, 0x4614, 0xc04a, 0x45e2, 0xc045, 0x45b0, 0xc041,
+  0x457e, 0xc03c, 0x454c, 0xc038, 0x451a, 0xc034, 0x44e7, 0xc030,
+  0x44b5, 0xc02c, 0x4483, 0xc029, 0x4451, 0xc025, 0x441f, 0xc022,
+  0x43ed, 0xc01f, 0x43bb, 0xc01c, 0x4388, 0xc019, 0x4356, 0xc016,
+  0x4324, 0xc014, 0x42f2, 0xc011, 0x42c0, 0xc00f, 0x428d, 0xc00d,
+  0x425b, 0xc00b, 0x4229, 0xc009, 0x41f7, 0xc008, 0x41c4, 0xc006,
+  0x4192, 0xc005, 0x4160, 0xc004, 0x412e, 0xc003, 0x40fb, 0xc002,
+  0x40c9, 0xc001, 0x4097, 0xc001, 0x4065, 0xc000, 0x4032, 0xc000
+};
+
+/**   
+* @brief  Initialization function for the Q15 RFFT/RIFFT.  
+* @param[in, out] *S             points to an instance of the Q15 RFFT/RIFFT structure.  
+* @param[in]      *S_CFFT        points to an instance of the Q15 CFFT/CIFFT structure.  
+* @param[in]      fftLenReal     length of the FFT.  
+* @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.  
+* @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.  
+*   
+* \par Description:  
+* \par  
+* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.   
+* \par   
+* The parameter ifftFlagR controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.   
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.  
+* \par   
+* This function also initializes Twiddle factor table.    
+*/
+
+arm_status arm_rfft_init_q15(
+  arm_rfft_instance_q15 * S,
+  arm_cfft_radix4_instance_q15 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag)
+{
+
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialize the Real FFT length */
+  S->fftLenReal = (uint16_t) fftLenReal;
+
+  /*  Initialize the Complex FFT length */
+  S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
+
+  /*  Initialize the Twiddle coefficientA pointer */
+  S->pTwiddleAReal = (q15_t *) realCoefAQ15;
+
+  /*  Initialize the Twiddle coefficientB pointer */
+  S->pTwiddleBReal = (q15_t *) realCoefBQ15;
+
+  /*  Initialize the Flag for selection of RFFT or RIFFT */
+  S->ifftFlagR = (uint8_t) ifftFlagR;
+
+  /*  Initialize the Flag for calculation Bit reversal or not */
+  S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+  /*  Initialization of coef modifier depending on the FFT length */
+  switch (S->fftLenReal)
+  {
+  case 2048u:
+    S->twidCoefRModifier = 1u;
+    break;
+  case 512u:
+    S->twidCoefRModifier = 4u;
+    break;
+  case 128u:
+    S->twidCoefRModifier = 16u;
+    break;
+  default:
+    /*  Reporting argument error if rfftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  /* Init Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  if(S->ifftFlagR)
+  {
+    /* Initializes the CIFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_q15(S->pCfft, S->fftLenBy2, 1u, 1u);
+  }
+  else
+  {
+    /* Initializes the CFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_q15(S->pCfft, S->fftLenBy2, 0u, 1u);
+  }
+
+  /* return the status of RFFT Init function */
+  return (status);
+
+}
+
+  /**   
+   * @} end of RFFT_RIFFT group   
+   */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c
new file mode 100644
index 0000000000..94d0c1d590
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c
@@ -0,0 +1,681 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_rfft_init_q31.c   
+*   
+* Description:	RFFT & RIFFT Q31 initialisation function   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/**   
+ * @ingroup groupTransforms   
+ */
+
+/**   
+ * @addtogroup RFFT_RIFFT   
+ * @{   
+ */
+
+/**   
+* \par   
+* Generation floating point realCoefAQ31 array:   
+* \par   
+* n = 1024   
+* 
    for (i = 0; i < n; i++)   
+* {   
+*    pATable[2 * i] = 0.5 * (1.0 - sin (2 * PI / (double) (2 * n) * (double) i));   
+*    pATable[2 * i + 1] = 0.5 * (-1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+* }
       
+* \par   
+* Convert to fixed point Q31 format   
+*     round(pATable[i] * pow(2, 31))   
+*/
+
+
+const q31_t realCoefAQ31[1024] = {
+  0x40000000, 0xc0000000, 0x3f9b783c, 0xc0004ef5,
+  0x3f36f170, 0xc0013bd3, 0x3ed26c94, 0xc002c697,
+  0x3e6deaa1, 0xc004ef3f, 0x3e096c8d, 0xc007b5c4,
+  0x3da4f351, 0xc00b1a20, 0x3d407fe6, 0xc00f1c4a,
+  0x3cdc1342, 0xc013bc39, 0x3c77ae5e, 0xc018f9e1,
+  0x3c135231, 0xc01ed535, 0x3baeffb3, 0xc0254e27,
+  0x3b4ab7db, 0xc02c64a6, 0x3ae67ba2, 0xc03418a2,
+  0x3a824bfd, 0xc03c6a07, 0x3a1e29e5, 0xc04558c0,
+  0x39ba1651, 0xc04ee4b8, 0x39561237, 0xc0590dd8,
+  0x38f21e8e, 0xc063d405, 0x388e3c4d, 0xc06f3726,
+  0x382a6c6a, 0xc07b371e, 0x37c6afdc, 0xc087d3d0,
+  0x37630799, 0xc0950d1d, 0x36ff7496, 0xc0a2e2e3,
+  0x369bf7c9, 0xc0b15502, 0x36389228, 0xc0c06355,
+  0x35d544a7, 0xc0d00db6, 0x3572103d, 0xc0e05401,
+  0x350ef5de, 0xc0f1360b, 0x34abf67e, 0xc102b3ac,
+  0x34491311, 0xc114ccb9, 0x33e64c8c, 0xc1278104,
+  0x3383a3e2, 0xc13ad060, 0x33211a07, 0xc14eba9d,
+  0x32beafed, 0xc1633f8a, 0x325c6688, 0xc1785ef4,
+  0x31fa3ecb, 0xc18e18a7, 0x319839a6, 0xc1a46c6e,
+  0x3136580d, 0xc1bb5a11, 0x30d49af1, 0xc1d2e158,
+  0x30730342, 0xc1eb0209, 0x301191f3, 0xc203bbe8,
+  0x2fb047f2, 0xc21d0eb8, 0x2f4f2630, 0xc236fa3b,
+  0x2eee2d9d, 0xc2517e31, 0x2e8d5f29, 0xc26c9a58,
+  0x2e2cbbc1, 0xc2884e6e, 0x2dcc4454, 0xc2a49a2e,
+  0x2d6bf9d1, 0xc2c17d52, 0x2d0bdd25, 0xc2def794,
+  0x2cabef3d, 0xc2fd08a9, 0x2c4c3106, 0xc31bb049,
+  0x2beca36c, 0xc33aee27, 0x2b8d475b, 0xc35ac1f7,
+  0x2b2e1dbe, 0xc37b2b6a, 0x2acf277f, 0xc39c2a2f,
+  0x2a70658a, 0xc3bdbdf6, 0x2a11d8c8, 0xc3dfe66c,
+  0x29b38223, 0xc402a33c, 0x29556282, 0xc425f410,
+  0x28f77acf, 0xc449d892, 0x2899cbf1, 0xc46e5069,
+  0x283c56cf, 0xc4935b3c, 0x27df1c50, 0xc4b8f8ad,
+  0x27821d59, 0xc4df2862, 0x27255ad1, 0xc505e9fb,
+  0x26c8d59c, 0xc52d3d18, 0x266c8e9f, 0xc555215a,
+  0x261086bc, 0xc57d965d, 0x25b4bed8, 0xc5a69bbe,
+  0x255937d5, 0xc5d03118, 0x24fdf294, 0xc5fa5603,
+  0x24a2eff6, 0xc6250a18, 0x244830dd, 0xc6504ced,
+  0x23edb628, 0xc67c1e18, 0x239380b6, 0xc6a87d2d,
+  0x23399167, 0xc6d569be, 0x22dfe917, 0xc702e35c,
+  0x228688a4, 0xc730e997, 0x222d70eb, 0xc75f7bfe,
+  0x21d4a2c8, 0xc78e9a1d, 0x217c1f15, 0xc7be4381,
+  0x2123e6ad, 0xc7ee77b3, 0x20cbfa6a, 0xc81f363d,
+  0x20745b24, 0xc8507ea7, 0x201d09b4, 0xc8825077,
+  0x1fc606f1, 0xc8b4ab32, 0x1f6f53b3, 0xc8e78e5b,
+  0x1f18f0ce, 0xc91af976, 0x1ec2df18, 0xc94eec03,
+  0x1e6d1f65, 0xc9836582, 0x1e17b28a, 0xc9b86572,
+  0x1dc29958, 0xc9edeb50, 0x1d6dd4a2, 0xca23f698,
+  0x1d196538, 0xca5a86c4, 0x1cc54bec, 0xca919b4e,
+  0x1c71898d, 0xcac933ae, 0x1c1e1ee9, 0xcb014f5b,
+  0x1bcb0cce, 0xcb39edca, 0x1b785409, 0xcb730e70,
+  0x1b25f566, 0xcbacb0bf, 0x1ad3f1b1, 0xcbe6d42b,
+  0x1a8249b4, 0xcc217822, 0x1a30fe38, 0xcc5c9c14,
+  0x19e01006, 0xcc983f70, 0x198f7fe6, 0xccd461a2,
+  0x193f4e9e, 0xcd110216, 0x18ef7cf4, 0xcd4e2037,
+  0x18a00bae, 0xcd8bbb6d, 0x1850fb8e, 0xcdc9d320,
+  0x18024d59, 0xce0866b8, 0x17b401d1, 0xce47759a,
+  0x176619b6, 0xce86ff2a, 0x171895c9, 0xcec702cb,
+  0x16cb76c9, 0xcf077fe1, 0x167ebd74, 0xcf4875ca,
+  0x16326a88, 0xcf89e3e8, 0x15e67ec1, 0xcfcbc999,
+  0x159afadb, 0xd00e2639, 0x154fdf8f, 0xd050f926,
+  0x15052d97, 0xd09441bb, 0x14bae5ab, 0xd0d7ff51,
+  0x14710883, 0xd11c3142, 0x142796d5, 0xd160d6e5,
+  0x13de9156, 0xd1a5ef90, 0x1395f8ba, 0xd1eb7a9a,
+  0x134dcdb4, 0xd2317756, 0x130610f7, 0xd277e518,
+  0x12bec333, 0xd2bec333, 0x1277e518, 0xd30610f7,
+  0x12317756, 0xd34dcdb4, 0x11eb7a9a, 0xd395f8ba,
+  0x11a5ef90, 0xd3de9156, 0x1160d6e5, 0xd42796d5,
+  0x111c3142, 0xd4710883, 0x10d7ff51, 0xd4bae5ab,
+  0x109441bb, 0xd5052d97, 0x1050f926, 0xd54fdf8f,
+  0x100e2639, 0xd59afadb, 0xfcbc999, 0xd5e67ec1,
+  0xf89e3e8, 0xd6326a88, 0xf4875ca, 0xd67ebd74,
+  0xf077fe1, 0xd6cb76c9, 0xec702cb, 0xd71895c9,
+  0xe86ff2a, 0xd76619b6, 0xe47759a, 0xd7b401d1,
+  0xe0866b8, 0xd8024d59, 0xdc9d320, 0xd850fb8e,
+  0xd8bbb6d, 0xd8a00bae, 0xd4e2037, 0xd8ef7cf4,
+  0xd110216, 0xd93f4e9e, 0xcd461a2, 0xd98f7fe6,
+  0xc983f70, 0xd9e01006, 0xc5c9c14, 0xda30fe38,
+  0xc217822, 0xda8249b4, 0xbe6d42b, 0xdad3f1b1,
+  0xbacb0bf, 0xdb25f566, 0xb730e70, 0xdb785409,
+  0xb39edca, 0xdbcb0cce, 0xb014f5b, 0xdc1e1ee9,
+  0xac933ae, 0xdc71898d, 0xa919b4e, 0xdcc54bec,
+  0xa5a86c4, 0xdd196538, 0xa23f698, 0xdd6dd4a2,
+  0x9edeb50, 0xddc29958, 0x9b86572, 0xde17b28a,
+  0x9836582, 0xde6d1f65, 0x94eec03, 0xdec2df18,
+  0x91af976, 0xdf18f0ce, 0x8e78e5b, 0xdf6f53b3,
+  0x8b4ab32, 0xdfc606f1, 0x8825077, 0xe01d09b4,
+  0x8507ea7, 0xe0745b24, 0x81f363d, 0xe0cbfa6a,
+  0x7ee77b3, 0xe123e6ad, 0x7be4381, 0xe17c1f15,
+  0x78e9a1d, 0xe1d4a2c8, 0x75f7bfe, 0xe22d70eb,
+  0x730e997, 0xe28688a4, 0x702e35c, 0xe2dfe917,
+  0x6d569be, 0xe3399167, 0x6a87d2d, 0xe39380b6,
+  0x67c1e18, 0xe3edb628, 0x6504ced, 0xe44830dd,
+  0x6250a18, 0xe4a2eff6, 0x5fa5603, 0xe4fdf294,
+  0x5d03118, 0xe55937d5, 0x5a69bbe, 0xe5b4bed8,
+  0x57d965d, 0xe61086bc, 0x555215a, 0xe66c8e9f,
+  0x52d3d18, 0xe6c8d59c, 0x505e9fb, 0xe7255ad1,
+  0x4df2862, 0xe7821d59, 0x4b8f8ad, 0xe7df1c50,
+  0x4935b3c, 0xe83c56cf, 0x46e5069, 0xe899cbf1,
+  0x449d892, 0xe8f77acf, 0x425f410, 0xe9556282,
+  0x402a33c, 0xe9b38223, 0x3dfe66c, 0xea11d8c8,
+  0x3bdbdf6, 0xea70658a, 0x39c2a2f, 0xeacf277f,
+  0x37b2b6a, 0xeb2e1dbe, 0x35ac1f7, 0xeb8d475b,
+  0x33aee27, 0xebeca36c, 0x31bb049, 0xec4c3106,
+  0x2fd08a9, 0xecabef3d, 0x2def794, 0xed0bdd25,
+  0x2c17d52, 0xed6bf9d1, 0x2a49a2e, 0xedcc4454,
+  0x2884e6e, 0xee2cbbc1, 0x26c9a58, 0xee8d5f29,
+  0x2517e31, 0xeeee2d9d, 0x236fa3b, 0xef4f2630,
+  0x21d0eb8, 0xefb047f2, 0x203bbe8, 0xf01191f3,
+  0x1eb0209, 0xf0730342, 0x1d2e158, 0xf0d49af1,
+  0x1bb5a11, 0xf136580d, 0x1a46c6e, 0xf19839a6,
+  0x18e18a7, 0xf1fa3ecb, 0x1785ef4, 0xf25c6688,
+  0x1633f8a, 0xf2beafed, 0x14eba9d, 0xf3211a07,
+  0x13ad060, 0xf383a3e2, 0x1278104, 0xf3e64c8c,
+  0x114ccb9, 0xf4491311, 0x102b3ac, 0xf4abf67e,
+  0xf1360b, 0xf50ef5de, 0xe05401, 0xf572103d,
+  0xd00db6, 0xf5d544a7, 0xc06355, 0xf6389228,
+  0xb15502, 0xf69bf7c9, 0xa2e2e3, 0xf6ff7496,
+  0x950d1d, 0xf7630799, 0x87d3d0, 0xf7c6afdc,
+  0x7b371e, 0xf82a6c6a, 0x6f3726, 0xf88e3c4d,
+  0x63d405, 0xf8f21e8e, 0x590dd8, 0xf9561237,
+  0x4ee4b8, 0xf9ba1651, 0x4558c0, 0xfa1e29e5,
+  0x3c6a07, 0xfa824bfd, 0x3418a2, 0xfae67ba2,
+  0x2c64a6, 0xfb4ab7db, 0x254e27, 0xfbaeffb3,
+  0x1ed535, 0xfc135231, 0x18f9e1, 0xfc77ae5e,
+  0x13bc39, 0xfcdc1342, 0xf1c4a, 0xfd407fe6,
+  0xb1a20, 0xfda4f351, 0x7b5c4, 0xfe096c8d,
+  0x4ef3f, 0xfe6deaa1, 0x2c697, 0xfed26c94,
+  0x13bd3, 0xff36f170, 0x4ef5, 0xff9b783c,
+  0x0, 0x0, 0x4ef5, 0x6487c4,
+  0x13bd3, 0xc90e90, 0x2c697, 0x12d936c,
+  0x4ef3f, 0x192155f, 0x7b5c4, 0x1f69373,
+  0xb1a20, 0x25b0caf, 0xf1c4a, 0x2bf801a,
+  0x13bc39, 0x323ecbe, 0x18f9e1, 0x38851a2,
+  0x1ed535, 0x3ecadcf, 0x254e27, 0x451004d,
+  0x2c64a6, 0x4b54825, 0x3418a2, 0x519845e,
+  0x3c6a07, 0x57db403, 0x4558c0, 0x5e1d61b,
+  0x4ee4b8, 0x645e9af, 0x590dd8, 0x6a9edc9,
+  0x63d405, 0x70de172, 0x6f3726, 0x771c3b3,
+  0x7b371e, 0x7d59396, 0x87d3d0, 0x8395024,
+  0x950d1d, 0x89cf867, 0xa2e2e3, 0x9008b6a,
+  0xb15502, 0x9640837, 0xc06355, 0x9c76dd8,
+  0xd00db6, 0xa2abb59, 0xe05401, 0xa8defc3,
+  0xf1360b, 0xaf10a22, 0x102b3ac, 0xb540982,
+  0x114ccb9, 0xbb6ecef, 0x1278104, 0xc19b374,
+  0x13ad060, 0xc7c5c1e, 0x14eba9d, 0xcdee5f9,
+  0x1633f8a, 0xd415013, 0x1785ef4, 0xda39978,
+  0x18e18a7, 0xe05c135, 0x1a46c6e, 0xe67c65a,
+  0x1bb5a11, 0xec9a7f3, 0x1d2e158, 0xf2b650f,
+  0x1eb0209, 0xf8cfcbe, 0x203bbe8, 0xfee6e0d,
+  0x21d0eb8, 0x104fb80e, 0x236fa3b, 0x10b0d9d0,
+  0x2517e31, 0x1111d263, 0x26c9a58, 0x1172a0d7,
+  0x2884e6e, 0x11d3443f, 0x2a49a2e, 0x1233bbac,
+  0x2c17d52, 0x1294062f, 0x2def794, 0x12f422db,
+  0x2fd08a9, 0x135410c3, 0x31bb049, 0x13b3cefa,
+  0x33aee27, 0x14135c94, 0x35ac1f7, 0x1472b8a5,
+  0x37b2b6a, 0x14d1e242, 0x39c2a2f, 0x1530d881,
+  0x3bdbdf6, 0x158f9a76, 0x3dfe66c, 0x15ee2738,
+  0x402a33c, 0x164c7ddd, 0x425f410, 0x16aa9d7e,
+  0x449d892, 0x17088531, 0x46e5069, 0x1766340f,
+  0x4935b3c, 0x17c3a931, 0x4b8f8ad, 0x1820e3b0,
+  0x4df2862, 0x187de2a7, 0x505e9fb, 0x18daa52f,
+  0x52d3d18, 0x19372a64, 0x555215a, 0x19937161,
+  0x57d965d, 0x19ef7944, 0x5a69bbe, 0x1a4b4128,
+  0x5d03118, 0x1aa6c82b, 0x5fa5603, 0x1b020d6c,
+  0x6250a18, 0x1b5d100a, 0x6504ced, 0x1bb7cf23,
+  0x67c1e18, 0x1c1249d8, 0x6a87d2d, 0x1c6c7f4a,
+  0x6d569be, 0x1cc66e99, 0x702e35c, 0x1d2016e9,
+  0x730e997, 0x1d79775c, 0x75f7bfe, 0x1dd28f15,
+  0x78e9a1d, 0x1e2b5d38, 0x7be4381, 0x1e83e0eb,
+  0x7ee77b3, 0x1edc1953, 0x81f363d, 0x1f340596,
+  0x8507ea7, 0x1f8ba4dc, 0x8825077, 0x1fe2f64c,
+  0x8b4ab32, 0x2039f90f, 0x8e78e5b, 0x2090ac4d,
+  0x91af976, 0x20e70f32, 0x94eec03, 0x213d20e8,
+  0x9836582, 0x2192e09b, 0x9b86572, 0x21e84d76,
+  0x9edeb50, 0x223d66a8, 0xa23f698, 0x22922b5e,
+  0xa5a86c4, 0x22e69ac8, 0xa919b4e, 0x233ab414,
+  0xac933ae, 0x238e7673, 0xb014f5b, 0x23e1e117,
+  0xb39edca, 0x2434f332, 0xb730e70, 0x2487abf7,
+  0xbacb0bf, 0x24da0a9a, 0xbe6d42b, 0x252c0e4f,
+  0xc217822, 0x257db64c, 0xc5c9c14, 0x25cf01c8,
+  0xc983f70, 0x261feffa, 0xcd461a2, 0x2670801a,
+  0xd110216, 0x26c0b162, 0xd4e2037, 0x2710830c,
+  0xd8bbb6d, 0x275ff452, 0xdc9d320, 0x27af0472,
+  0xe0866b8, 0x27fdb2a7, 0xe47759a, 0x284bfe2f,
+  0xe86ff2a, 0x2899e64a, 0xec702cb, 0x28e76a37,
+  0xf077fe1, 0x29348937, 0xf4875ca, 0x2981428c,
+  0xf89e3e8, 0x29cd9578, 0xfcbc999, 0x2a19813f,
+  0x100e2639, 0x2a650525, 0x1050f926, 0x2ab02071,
+  0x109441bb, 0x2afad269, 0x10d7ff51, 0x2b451a55,
+  0x111c3142, 0x2b8ef77d, 0x1160d6e5, 0x2bd8692b,
+  0x11a5ef90, 0x2c216eaa, 0x11eb7a9a, 0x2c6a0746,
+  0x12317756, 0x2cb2324c, 0x1277e518, 0x2cf9ef09,
+  0x12bec333, 0x2d413ccd, 0x130610f7, 0x2d881ae8,
+  0x134dcdb4, 0x2dce88aa, 0x1395f8ba, 0x2e148566,
+  0x13de9156, 0x2e5a1070, 0x142796d5, 0x2e9f291b,
+  0x14710883, 0x2ee3cebe, 0x14bae5ab, 0x2f2800af,
+  0x15052d97, 0x2f6bbe45, 0x154fdf8f, 0x2faf06da,
+  0x159afadb, 0x2ff1d9c7, 0x15e67ec1, 0x30343667,
+  0x16326a88, 0x30761c18, 0x167ebd74, 0x30b78a36,
+  0x16cb76c9, 0x30f8801f, 0x171895c9, 0x3138fd35,
+  0x176619b6, 0x317900d6, 0x17b401d1, 0x31b88a66,
+  0x18024d59, 0x31f79948, 0x1850fb8e, 0x32362ce0,
+  0x18a00bae, 0x32744493, 0x18ef7cf4, 0x32b1dfc9,
+  0x193f4e9e, 0x32eefdea, 0x198f7fe6, 0x332b9e5e,
+  0x19e01006, 0x3367c090, 0x1a30fe38, 0x33a363ec,
+  0x1a8249b4, 0x33de87de, 0x1ad3f1b1, 0x34192bd5,
+  0x1b25f566, 0x34534f41, 0x1b785409, 0x348cf190,
+  0x1bcb0cce, 0x34c61236, 0x1c1e1ee9, 0x34feb0a5,
+  0x1c71898d, 0x3536cc52, 0x1cc54bec, 0x356e64b2,
+  0x1d196538, 0x35a5793c, 0x1d6dd4a2, 0x35dc0968,
+  0x1dc29958, 0x361214b0, 0x1e17b28a, 0x36479a8e,
+  0x1e6d1f65, 0x367c9a7e, 0x1ec2df18, 0x36b113fd,
+  0x1f18f0ce, 0x36e5068a, 0x1f6f53b3, 0x371871a5,
+  0x1fc606f1, 0x374b54ce, 0x201d09b4, 0x377daf89,
+  0x20745b24, 0x37af8159, 0x20cbfa6a, 0x37e0c9c3,
+  0x2123e6ad, 0x3811884d, 0x217c1f15, 0x3841bc7f,
+  0x21d4a2c8, 0x387165e3, 0x222d70eb, 0x38a08402,
+  0x228688a4, 0x38cf1669, 0x22dfe917, 0x38fd1ca4,
+  0x23399167, 0x392a9642, 0x239380b6, 0x395782d3,
+  0x23edb628, 0x3983e1e8, 0x244830dd, 0x39afb313,
+  0x24a2eff6, 0x39daf5e8, 0x24fdf294, 0x3a05a9fd,
+  0x255937d5, 0x3a2fcee8, 0x25b4bed8, 0x3a596442,
+  0x261086bc, 0x3a8269a3, 0x266c8e9f, 0x3aaadea6,
+  0x26c8d59c, 0x3ad2c2e8, 0x27255ad1, 0x3afa1605,
+  0x27821d59, 0x3b20d79e, 0x27df1c50, 0x3b470753,
+  0x283c56cf, 0x3b6ca4c4, 0x2899cbf1, 0x3b91af97,
+  0x28f77acf, 0x3bb6276e, 0x29556282, 0x3bda0bf0,
+  0x29b38223, 0x3bfd5cc4, 0x2a11d8c8, 0x3c201994,
+  0x2a70658a, 0x3c42420a, 0x2acf277f, 0x3c63d5d1,
+  0x2b2e1dbe, 0x3c84d496, 0x2b8d475b, 0x3ca53e09,
+  0x2beca36c, 0x3cc511d9, 0x2c4c3106, 0x3ce44fb7,
+  0x2cabef3d, 0x3d02f757, 0x2d0bdd25, 0x3d21086c,
+  0x2d6bf9d1, 0x3d3e82ae, 0x2dcc4454, 0x3d5b65d2,
+  0x2e2cbbc1, 0x3d77b192, 0x2e8d5f29, 0x3d9365a8,
+  0x2eee2d9d, 0x3dae81cf, 0x2f4f2630, 0x3dc905c5,
+  0x2fb047f2, 0x3de2f148, 0x301191f3, 0x3dfc4418,
+  0x30730342, 0x3e14fdf7, 0x30d49af1, 0x3e2d1ea8,
+  0x3136580d, 0x3e44a5ef, 0x319839a6, 0x3e5b9392,
+  0x31fa3ecb, 0x3e71e759, 0x325c6688, 0x3e87a10c,
+  0x32beafed, 0x3e9cc076, 0x33211a07, 0x3eb14563,
+  0x3383a3e2, 0x3ec52fa0, 0x33e64c8c, 0x3ed87efc,
+  0x34491311, 0x3eeb3347, 0x34abf67e, 0x3efd4c54,
+  0x350ef5de, 0x3f0ec9f5, 0x3572103d, 0x3f1fabff,
+  0x35d544a7, 0x3f2ff24a, 0x36389228, 0x3f3f9cab,
+  0x369bf7c9, 0x3f4eaafe, 0x36ff7496, 0x3f5d1d1d,
+  0x37630799, 0x3f6af2e3, 0x37c6afdc, 0x3f782c30,
+  0x382a6c6a, 0x3f84c8e2, 0x388e3c4d, 0x3f90c8da,
+  0x38f21e8e, 0x3f9c2bfb, 0x39561237, 0x3fa6f228,
+  0x39ba1651, 0x3fb11b48, 0x3a1e29e5, 0x3fbaa740,
+  0x3a824bfd, 0x3fc395f9, 0x3ae67ba2, 0x3fcbe75e,
+  0x3b4ab7db, 0x3fd39b5a, 0x3baeffb3, 0x3fdab1d9,
+  0x3c135231, 0x3fe12acb, 0x3c77ae5e, 0x3fe7061f,
+  0x3cdc1342, 0x3fec43c7, 0x3d407fe6, 0x3ff0e3b6,
+  0x3da4f351, 0x3ff4e5e0, 0x3e096c8d, 0x3ff84a3c,
+  0x3e6deaa1, 0x3ffb10c1, 0x3ed26c94, 0x3ffd3969,
+  0x3f36f170, 0x3ffec42d, 0x3f9b783c, 0x3fffb10b
+};
+
+
+/**   
+* \par  
+* Generation of realCoefBQ31 array:   
+* \par   
+*  n = 512   
+* 
    for (i = 0; i < n; i++)   
+* {   
+*    pBTable[2 * i] = 0.5 * (1.0 + sin (2 * PI / (double) (2 * n) * (double) i));   
+*    pBTable[2 * i + 1] = 0.5 * (1.0 * cos (2 * PI / (double) (2 * n) * (double) i));   
+* } 
       
+* \par   
+* Convert to fixed point Q31 format   
+*     round(pBTable[i] * pow(2, 31))   
+*   
+*/
+
+const q31_t realCoefBQ31[1024] = {
+  0x40000000, 0x40000000, 0x406487c4, 0x3fffb10b,
+  0x40c90e90, 0x3ffec42d, 0x412d936c, 0x3ffd3969,
+  0x4192155f, 0x3ffb10c1, 0x41f69373, 0x3ff84a3c,
+  0x425b0caf, 0x3ff4e5e0, 0x42bf801a, 0x3ff0e3b6,
+  0x4323ecbe, 0x3fec43c7, 0x438851a2, 0x3fe7061f,
+  0x43ecadcf, 0x3fe12acb, 0x4451004d, 0x3fdab1d9,
+  0x44b54825, 0x3fd39b5a, 0x4519845e, 0x3fcbe75e,
+  0x457db403, 0x3fc395f9, 0x45e1d61b, 0x3fbaa740,
+  0x4645e9af, 0x3fb11b48, 0x46a9edc9, 0x3fa6f228,
+  0x470de172, 0x3f9c2bfb, 0x4771c3b3, 0x3f90c8da,
+  0x47d59396, 0x3f84c8e2, 0x48395024, 0x3f782c30,
+  0x489cf867, 0x3f6af2e3, 0x49008b6a, 0x3f5d1d1d,
+  0x49640837, 0x3f4eaafe, 0x49c76dd8, 0x3f3f9cab,
+  0x4a2abb59, 0x3f2ff24a, 0x4a8defc3, 0x3f1fabff,
+  0x4af10a22, 0x3f0ec9f5, 0x4b540982, 0x3efd4c54,
+  0x4bb6ecef, 0x3eeb3347, 0x4c19b374, 0x3ed87efc,
+  0x4c7c5c1e, 0x3ec52fa0, 0x4cdee5f9, 0x3eb14563,
+  0x4d415013, 0x3e9cc076, 0x4da39978, 0x3e87a10c,
+  0x4e05c135, 0x3e71e759, 0x4e67c65a, 0x3e5b9392,
+  0x4ec9a7f3, 0x3e44a5ef, 0x4f2b650f, 0x3e2d1ea8,
+  0x4f8cfcbe, 0x3e14fdf7, 0x4fee6e0d, 0x3dfc4418,
+  0x504fb80e, 0x3de2f148, 0x50b0d9d0, 0x3dc905c5,
+  0x5111d263, 0x3dae81cf, 0x5172a0d7, 0x3d9365a8,
+  0x51d3443f, 0x3d77b192, 0x5233bbac, 0x3d5b65d2,
+  0x5294062f, 0x3d3e82ae, 0x52f422db, 0x3d21086c,
+  0x535410c3, 0x3d02f757, 0x53b3cefa, 0x3ce44fb7,
+  0x54135c94, 0x3cc511d9, 0x5472b8a5, 0x3ca53e09,
+  0x54d1e242, 0x3c84d496, 0x5530d881, 0x3c63d5d1,
+  0x558f9a76, 0x3c42420a, 0x55ee2738, 0x3c201994,
+  0x564c7ddd, 0x3bfd5cc4, 0x56aa9d7e, 0x3bda0bf0,
+  0x57088531, 0x3bb6276e, 0x5766340f, 0x3b91af97,
+  0x57c3a931, 0x3b6ca4c4, 0x5820e3b0, 0x3b470753,
+  0x587de2a7, 0x3b20d79e, 0x58daa52f, 0x3afa1605,
+  0x59372a64, 0x3ad2c2e8, 0x59937161, 0x3aaadea6,
+  0x59ef7944, 0x3a8269a3, 0x5a4b4128, 0x3a596442,
+  0x5aa6c82b, 0x3a2fcee8, 0x5b020d6c, 0x3a05a9fd,
+  0x5b5d100a, 0x39daf5e8, 0x5bb7cf23, 0x39afb313,
+  0x5c1249d8, 0x3983e1e8, 0x5c6c7f4a, 0x395782d3,
+  0x5cc66e99, 0x392a9642, 0x5d2016e9, 0x38fd1ca4,
+  0x5d79775c, 0x38cf1669, 0x5dd28f15, 0x38a08402,
+  0x5e2b5d38, 0x387165e3, 0x5e83e0eb, 0x3841bc7f,
+  0x5edc1953, 0x3811884d, 0x5f340596, 0x37e0c9c3,
+  0x5f8ba4dc, 0x37af8159, 0x5fe2f64c, 0x377daf89,
+  0x6039f90f, 0x374b54ce, 0x6090ac4d, 0x371871a5,
+  0x60e70f32, 0x36e5068a, 0x613d20e8, 0x36b113fd,
+  0x6192e09b, 0x367c9a7e, 0x61e84d76, 0x36479a8e,
+  0x623d66a8, 0x361214b0, 0x62922b5e, 0x35dc0968,
+  0x62e69ac8, 0x35a5793c, 0x633ab414, 0x356e64b2,
+  0x638e7673, 0x3536cc52, 0x63e1e117, 0x34feb0a5,
+  0x6434f332, 0x34c61236, 0x6487abf7, 0x348cf190,
+  0x64da0a9a, 0x34534f41, 0x652c0e4f, 0x34192bd5,
+  0x657db64c, 0x33de87de, 0x65cf01c8, 0x33a363ec,
+  0x661feffa, 0x3367c090, 0x6670801a, 0x332b9e5e,
+  0x66c0b162, 0x32eefdea, 0x6710830c, 0x32b1dfc9,
+  0x675ff452, 0x32744493, 0x67af0472, 0x32362ce0,
+  0x67fdb2a7, 0x31f79948, 0x684bfe2f, 0x31b88a66,
+  0x6899e64a, 0x317900d6, 0x68e76a37, 0x3138fd35,
+  0x69348937, 0x30f8801f, 0x6981428c, 0x30b78a36,
+  0x69cd9578, 0x30761c18, 0x6a19813f, 0x30343667,
+  0x6a650525, 0x2ff1d9c7, 0x6ab02071, 0x2faf06da,
+  0x6afad269, 0x2f6bbe45, 0x6b451a55, 0x2f2800af,
+  0x6b8ef77d, 0x2ee3cebe, 0x6bd8692b, 0x2e9f291b,
+  0x6c216eaa, 0x2e5a1070, 0x6c6a0746, 0x2e148566,
+  0x6cb2324c, 0x2dce88aa, 0x6cf9ef09, 0x2d881ae8,
+  0x6d413ccd, 0x2d413ccd, 0x6d881ae8, 0x2cf9ef09,
+  0x6dce88aa, 0x2cb2324c, 0x6e148566, 0x2c6a0746,
+  0x6e5a1070, 0x2c216eaa, 0x6e9f291b, 0x2bd8692b,
+  0x6ee3cebe, 0x2b8ef77d, 0x6f2800af, 0x2b451a55,
+  0x6f6bbe45, 0x2afad269, 0x6faf06da, 0x2ab02071,
+  0x6ff1d9c7, 0x2a650525, 0x70343667, 0x2a19813f,
+  0x70761c18, 0x29cd9578, 0x70b78a36, 0x2981428c,
+  0x70f8801f, 0x29348937, 0x7138fd35, 0x28e76a37,
+  0x717900d6, 0x2899e64a, 0x71b88a66, 0x284bfe2f,
+  0x71f79948, 0x27fdb2a7, 0x72362ce0, 0x27af0472,
+  0x72744493, 0x275ff452, 0x72b1dfc9, 0x2710830c,
+  0x72eefdea, 0x26c0b162, 0x732b9e5e, 0x2670801a,
+  0x7367c090, 0x261feffa, 0x73a363ec, 0x25cf01c8,
+  0x73de87de, 0x257db64c, 0x74192bd5, 0x252c0e4f,
+  0x74534f41, 0x24da0a9a, 0x748cf190, 0x2487abf7,
+  0x74c61236, 0x2434f332, 0x74feb0a5, 0x23e1e117,
+  0x7536cc52, 0x238e7673, 0x756e64b2, 0x233ab414,
+  0x75a5793c, 0x22e69ac8, 0x75dc0968, 0x22922b5e,
+  0x761214b0, 0x223d66a8, 0x76479a8e, 0x21e84d76,
+  0x767c9a7e, 0x2192e09b, 0x76b113fd, 0x213d20e8,
+  0x76e5068a, 0x20e70f32, 0x771871a5, 0x2090ac4d,
+  0x774b54ce, 0x2039f90f, 0x777daf89, 0x1fe2f64c,
+  0x77af8159, 0x1f8ba4dc, 0x77e0c9c3, 0x1f340596,
+  0x7811884d, 0x1edc1953, 0x7841bc7f, 0x1e83e0eb,
+  0x787165e3, 0x1e2b5d38, 0x78a08402, 0x1dd28f15,
+  0x78cf1669, 0x1d79775c, 0x78fd1ca4, 0x1d2016e9,
+  0x792a9642, 0x1cc66e99, 0x795782d3, 0x1c6c7f4a,
+  0x7983e1e8, 0x1c1249d8, 0x79afb313, 0x1bb7cf23,
+  0x79daf5e8, 0x1b5d100a, 0x7a05a9fd, 0x1b020d6c,
+  0x7a2fcee8, 0x1aa6c82b, 0x7a596442, 0x1a4b4128,
+  0x7a8269a3, 0x19ef7944, 0x7aaadea6, 0x19937161,
+  0x7ad2c2e8, 0x19372a64, 0x7afa1605, 0x18daa52f,
+  0x7b20d79e, 0x187de2a7, 0x7b470753, 0x1820e3b0,
+  0x7b6ca4c4, 0x17c3a931, 0x7b91af97, 0x1766340f,
+  0x7bb6276e, 0x17088531, 0x7bda0bf0, 0x16aa9d7e,
+  0x7bfd5cc4, 0x164c7ddd, 0x7c201994, 0x15ee2738,
+  0x7c42420a, 0x158f9a76, 0x7c63d5d1, 0x1530d881,
+  0x7c84d496, 0x14d1e242, 0x7ca53e09, 0x1472b8a5,
+  0x7cc511d9, 0x14135c94, 0x7ce44fb7, 0x13b3cefa,
+  0x7d02f757, 0x135410c3, 0x7d21086c, 0x12f422db,
+  0x7d3e82ae, 0x1294062f, 0x7d5b65d2, 0x1233bbac,
+  0x7d77b192, 0x11d3443f, 0x7d9365a8, 0x1172a0d7,
+  0x7dae81cf, 0x1111d263, 0x7dc905c5, 0x10b0d9d0,
+  0x7de2f148, 0x104fb80e, 0x7dfc4418, 0xfee6e0d,
+  0x7e14fdf7, 0xf8cfcbe, 0x7e2d1ea8, 0xf2b650f,
+  0x7e44a5ef, 0xec9a7f3, 0x7e5b9392, 0xe67c65a,
+  0x7e71e759, 0xe05c135, 0x7e87a10c, 0xda39978,
+  0x7e9cc076, 0xd415013, 0x7eb14563, 0xcdee5f9,
+  0x7ec52fa0, 0xc7c5c1e, 0x7ed87efc, 0xc19b374,
+  0x7eeb3347, 0xbb6ecef, 0x7efd4c54, 0xb540982,
+  0x7f0ec9f5, 0xaf10a22, 0x7f1fabff, 0xa8defc3,
+  0x7f2ff24a, 0xa2abb59, 0x7f3f9cab, 0x9c76dd8,
+  0x7f4eaafe, 0x9640837, 0x7f5d1d1d, 0x9008b6a,
+  0x7f6af2e3, 0x89cf867, 0x7f782c30, 0x8395024,
+  0x7f84c8e2, 0x7d59396, 0x7f90c8da, 0x771c3b3,
+  0x7f9c2bfb, 0x70de172, 0x7fa6f228, 0x6a9edc9,
+  0x7fb11b48, 0x645e9af, 0x7fbaa740, 0x5e1d61b,
+  0x7fc395f9, 0x57db403, 0x7fcbe75e, 0x519845e,
+  0x7fd39b5a, 0x4b54825, 0x7fdab1d9, 0x451004d,
+  0x7fe12acb, 0x3ecadcf, 0x7fe7061f, 0x38851a2,
+  0x7fec43c7, 0x323ecbe, 0x7ff0e3b6, 0x2bf801a,
+  0x7ff4e5e0, 0x25b0caf, 0x7ff84a3c, 0x1f69373,
+  0x7ffb10c1, 0x192155f, 0x7ffd3969, 0x12d936c,
+  0x7ffec42d, 0xc90e90, 0x7fffb10b, 0x6487c4,
+  0x7fffffff, 0x0, 0x7fffb10b, 0xff9b783c,
+  0x7ffec42d, 0xff36f170, 0x7ffd3969, 0xfed26c94,
+  0x7ffb10c1, 0xfe6deaa1, 0x7ff84a3c, 0xfe096c8d,
+  0x7ff4e5e0, 0xfda4f351, 0x7ff0e3b6, 0xfd407fe6,
+  0x7fec43c7, 0xfcdc1342, 0x7fe7061f, 0xfc77ae5e,
+  0x7fe12acb, 0xfc135231, 0x7fdab1d9, 0xfbaeffb3,
+  0x7fd39b5a, 0xfb4ab7db, 0x7fcbe75e, 0xfae67ba2,
+  0x7fc395f9, 0xfa824bfd, 0x7fbaa740, 0xfa1e29e5,
+  0x7fb11b48, 0xf9ba1651, 0x7fa6f228, 0xf9561237,
+  0x7f9c2bfb, 0xf8f21e8e, 0x7f90c8da, 0xf88e3c4d,
+  0x7f84c8e2, 0xf82a6c6a, 0x7f782c30, 0xf7c6afdc,
+  0x7f6af2e3, 0xf7630799, 0x7f5d1d1d, 0xf6ff7496,
+  0x7f4eaafe, 0xf69bf7c9, 0x7f3f9cab, 0xf6389228,
+  0x7f2ff24a, 0xf5d544a7, 0x7f1fabff, 0xf572103d,
+  0x7f0ec9f5, 0xf50ef5de, 0x7efd4c54, 0xf4abf67e,
+  0x7eeb3347, 0xf4491311, 0x7ed87efc, 0xf3e64c8c,
+  0x7ec52fa0, 0xf383a3e2, 0x7eb14563, 0xf3211a07,
+  0x7e9cc076, 0xf2beafed, 0x7e87a10c, 0xf25c6688,
+  0x7e71e759, 0xf1fa3ecb, 0x7e5b9392, 0xf19839a6,
+  0x7e44a5ef, 0xf136580d, 0x7e2d1ea8, 0xf0d49af1,
+  0x7e14fdf7, 0xf0730342, 0x7dfc4418, 0xf01191f3,
+  0x7de2f148, 0xefb047f2, 0x7dc905c5, 0xef4f2630,
+  0x7dae81cf, 0xeeee2d9d, 0x7d9365a8, 0xee8d5f29,
+  0x7d77b192, 0xee2cbbc1, 0x7d5b65d2, 0xedcc4454,
+  0x7d3e82ae, 0xed6bf9d1, 0x7d21086c, 0xed0bdd25,
+  0x7d02f757, 0xecabef3d, 0x7ce44fb7, 0xec4c3106,
+  0x7cc511d9, 0xebeca36c, 0x7ca53e09, 0xeb8d475b,
+  0x7c84d496, 0xeb2e1dbe, 0x7c63d5d1, 0xeacf277f,
+  0x7c42420a, 0xea70658a, 0x7c201994, 0xea11d8c8,
+  0x7bfd5cc4, 0xe9b38223, 0x7bda0bf0, 0xe9556282,
+  0x7bb6276e, 0xe8f77acf, 0x7b91af97, 0xe899cbf1,
+  0x7b6ca4c4, 0xe83c56cf, 0x7b470753, 0xe7df1c50,
+  0x7b20d79e, 0xe7821d59, 0x7afa1605, 0xe7255ad1,
+  0x7ad2c2e8, 0xe6c8d59c, 0x7aaadea6, 0xe66c8e9f,
+  0x7a8269a3, 0xe61086bc, 0x7a596442, 0xe5b4bed8,
+  0x7a2fcee8, 0xe55937d5, 0x7a05a9fd, 0xe4fdf294,
+  0x79daf5e8, 0xe4a2eff6, 0x79afb313, 0xe44830dd,
+  0x7983e1e8, 0xe3edb628, 0x795782d3, 0xe39380b6,
+  0x792a9642, 0xe3399167, 0x78fd1ca4, 0xe2dfe917,
+  0x78cf1669, 0xe28688a4, 0x78a08402, 0xe22d70eb,
+  0x787165e3, 0xe1d4a2c8, 0x7841bc7f, 0xe17c1f15,
+  0x7811884d, 0xe123e6ad, 0x77e0c9c3, 0xe0cbfa6a,
+  0x77af8159, 0xe0745b24, 0x777daf89, 0xe01d09b4,
+  0x774b54ce, 0xdfc606f1, 0x771871a5, 0xdf6f53b3,
+  0x76e5068a, 0xdf18f0ce, 0x76b113fd, 0xdec2df18,
+  0x767c9a7e, 0xde6d1f65, 0x76479a8e, 0xde17b28a,
+  0x761214b0, 0xddc29958, 0x75dc0968, 0xdd6dd4a2,
+  0x75a5793c, 0xdd196538, 0x756e64b2, 0xdcc54bec,
+  0x7536cc52, 0xdc71898d, 0x74feb0a5, 0xdc1e1ee9,
+  0x74c61236, 0xdbcb0cce, 0x748cf190, 0xdb785409,
+  0x74534f41, 0xdb25f566, 0x74192bd5, 0xdad3f1b1,
+  0x73de87de, 0xda8249b4, 0x73a363ec, 0xda30fe38,
+  0x7367c090, 0xd9e01006, 0x732b9e5e, 0xd98f7fe6,
+  0x72eefdea, 0xd93f4e9e, 0x72b1dfc9, 0xd8ef7cf4,
+  0x72744493, 0xd8a00bae, 0x72362ce0, 0xd850fb8e,
+  0x71f79948, 0xd8024d59, 0x71b88a66, 0xd7b401d1,
+  0x717900d6, 0xd76619b6, 0x7138fd35, 0xd71895c9,
+  0x70f8801f, 0xd6cb76c9, 0x70b78a36, 0xd67ebd74,
+  0x70761c18, 0xd6326a88, 0x70343667, 0xd5e67ec1,
+  0x6ff1d9c7, 0xd59afadb, 0x6faf06da, 0xd54fdf8f,
+  0x6f6bbe45, 0xd5052d97, 0x6f2800af, 0xd4bae5ab,
+  0x6ee3cebe, 0xd4710883, 0x6e9f291b, 0xd42796d5,
+  0x6e5a1070, 0xd3de9156, 0x6e148566, 0xd395f8ba,
+  0x6dce88aa, 0xd34dcdb4, 0x6d881ae8, 0xd30610f7,
+  0x6d413ccd, 0xd2bec333, 0x6cf9ef09, 0xd277e518,
+  0x6cb2324c, 0xd2317756, 0x6c6a0746, 0xd1eb7a9a,
+  0x6c216eaa, 0xd1a5ef90, 0x6bd8692b, 0xd160d6e5,
+  0x6b8ef77d, 0xd11c3142, 0x6b451a55, 0xd0d7ff51,
+  0x6afad269, 0xd09441bb, 0x6ab02071, 0xd050f926,
+  0x6a650525, 0xd00e2639, 0x6a19813f, 0xcfcbc999,
+  0x69cd9578, 0xcf89e3e8, 0x6981428c, 0xcf4875ca,
+  0x69348937, 0xcf077fe1, 0x68e76a37, 0xcec702cb,
+  0x6899e64a, 0xce86ff2a, 0x684bfe2f, 0xce47759a,
+  0x67fdb2a7, 0xce0866b8, 0x67af0472, 0xcdc9d320,
+  0x675ff452, 0xcd8bbb6d, 0x6710830c, 0xcd4e2037,
+  0x66c0b162, 0xcd110216, 0x6670801a, 0xccd461a2,
+  0x661feffa, 0xcc983f70, 0x65cf01c8, 0xcc5c9c14,
+  0x657db64c, 0xcc217822, 0x652c0e4f, 0xcbe6d42b,
+  0x64da0a9a, 0xcbacb0bf, 0x6487abf7, 0xcb730e70,
+  0x6434f332, 0xcb39edca, 0x63e1e117, 0xcb014f5b,
+  0x638e7673, 0xcac933ae, 0x633ab414, 0xca919b4e,
+  0x62e69ac8, 0xca5a86c4, 0x62922b5e, 0xca23f698,
+  0x623d66a8, 0xc9edeb50, 0x61e84d76, 0xc9b86572,
+  0x6192e09b, 0xc9836582, 0x613d20e8, 0xc94eec03,
+  0x60e70f32, 0xc91af976, 0x6090ac4d, 0xc8e78e5b,
+  0x6039f90f, 0xc8b4ab32, 0x5fe2f64c, 0xc8825077,
+  0x5f8ba4dc, 0xc8507ea7, 0x5f340596, 0xc81f363d,
+  0x5edc1953, 0xc7ee77b3, 0x5e83e0eb, 0xc7be4381,
+  0x5e2b5d38, 0xc78e9a1d, 0x5dd28f15, 0xc75f7bfe,
+  0x5d79775c, 0xc730e997, 0x5d2016e9, 0xc702e35c,
+  0x5cc66e99, 0xc6d569be, 0x5c6c7f4a, 0xc6a87d2d,
+  0x5c1249d8, 0xc67c1e18, 0x5bb7cf23, 0xc6504ced,
+  0x5b5d100a, 0xc6250a18, 0x5b020d6c, 0xc5fa5603,
+  0x5aa6c82b, 0xc5d03118, 0x5a4b4128, 0xc5a69bbe,
+  0x59ef7944, 0xc57d965d, 0x59937161, 0xc555215a,
+  0x59372a64, 0xc52d3d18, 0x58daa52f, 0xc505e9fb,
+  0x587de2a7, 0xc4df2862, 0x5820e3b0, 0xc4b8f8ad,
+  0x57c3a931, 0xc4935b3c, 0x5766340f, 0xc46e5069,
+  0x57088531, 0xc449d892, 0x56aa9d7e, 0xc425f410,
+  0x564c7ddd, 0xc402a33c, 0x55ee2738, 0xc3dfe66c,
+  0x558f9a76, 0xc3bdbdf6, 0x5530d881, 0xc39c2a2f,
+  0x54d1e242, 0xc37b2b6a, 0x5472b8a5, 0xc35ac1f7,
+  0x54135c94, 0xc33aee27, 0x53b3cefa, 0xc31bb049,
+  0x535410c3, 0xc2fd08a9, 0x52f422db, 0xc2def794,
+  0x5294062f, 0xc2c17d52, 0x5233bbac, 0xc2a49a2e,
+  0x51d3443f, 0xc2884e6e, 0x5172a0d7, 0xc26c9a58,
+  0x5111d263, 0xc2517e31, 0x50b0d9d0, 0xc236fa3b,
+  0x504fb80e, 0xc21d0eb8, 0x4fee6e0d, 0xc203bbe8,
+  0x4f8cfcbe, 0xc1eb0209, 0x4f2b650f, 0xc1d2e158,
+  0x4ec9a7f3, 0xc1bb5a11, 0x4e67c65a, 0xc1a46c6e,
+  0x4e05c135, 0xc18e18a7, 0x4da39978, 0xc1785ef4,
+  0x4d415013, 0xc1633f8a, 0x4cdee5f9, 0xc14eba9d,
+  0x4c7c5c1e, 0xc13ad060, 0x4c19b374, 0xc1278104,
+  0x4bb6ecef, 0xc114ccb9, 0x4b540982, 0xc102b3ac,
+  0x4af10a22, 0xc0f1360b, 0x4a8defc3, 0xc0e05401,
+  0x4a2abb59, 0xc0d00db6, 0x49c76dd8, 0xc0c06355,
+  0x49640837, 0xc0b15502, 0x49008b6a, 0xc0a2e2e3,
+  0x489cf867, 0xc0950d1d, 0x48395024, 0xc087d3d0,
+  0x47d59396, 0xc07b371e, 0x4771c3b3, 0xc06f3726,
+  0x470de172, 0xc063d405, 0x46a9edc9, 0xc0590dd8,
+  0x4645e9af, 0xc04ee4b8, 0x45e1d61b, 0xc04558c0,
+  0x457db403, 0xc03c6a07, 0x4519845e, 0xc03418a2,
+  0x44b54825, 0xc02c64a6, 0x4451004d, 0xc0254e27,
+  0x43ecadcf, 0xc01ed535, 0x438851a2, 0xc018f9e1,
+  0x4323ecbe, 0xc013bc39, 0x42bf801a, 0xc00f1c4a,
+  0x425b0caf, 0xc00b1a20, 0x41f69373, 0xc007b5c4,
+  0x4192155f, 0xc004ef3f, 0x412d936c, 0xc002c697,
+  0x40c90e90, 0xc0013bd3, 0x406487c4, 0xc0004ef5
+};
+
+/**   
+* @brief  Initialization function for the Q31 RFFT/RIFFT.  
+* @param[in, out] *S             points to an instance of the Q31 RFFT/RIFFT structure.  
+* @param[in, out] *S_CFFT        points to an instance of the Q31 CFFT/CIFFT structure.  
+* @param[in]      fftLenReal     length of the FFT.  
+* @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.  
+* @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.  
+* @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.  
+*   
+* \par Description:  
+* \par  
+* The parameter fftLenReal	Specifies length of RFFT/RIFFT Process. Supported FFT Lengths are 128, 512, 2048.   
+* \par   
+* The parameter ifftFlagR controls whether a forward or inverse transform is computed.   
+* Set(=1) ifftFlagR to calculate RIFFT, otherwise RFFT is calculated.   
+* \par   
+* The parameter bitReverseFlag controls whether output is in normal order or bit reversed order.   
+* Set(=1) bitReverseFlag for output to be in normal order otherwise output is in bit reversed order.  
+* \par   
+* This function also initializes Twiddle factor table.   
+*/
+
+arm_status arm_rfft_init_q31(
+  arm_rfft_instance_q31 * S,
+  arm_cfft_radix4_instance_q31 * S_CFFT,
+  uint32_t fftLenReal,
+  uint32_t ifftFlagR,
+  uint32_t bitReverseFlag)
+{
+  /*  Initialise the default arm status */
+  arm_status status = ARM_MATH_SUCCESS;
+
+  /*  Initialize the Real FFT length */
+  S->fftLenReal = (uint16_t) fftLenReal;
+
+  /*  Initialize the Complex FFT length */
+  S->fftLenBy2 = (uint16_t) fftLenReal / 2u;
+
+  /*  Initialize the Twiddle coefficientA pointer */
+  S->pTwiddleAReal = (q31_t *) realCoefAQ31;
+
+  /*  Initialize the Twiddle coefficientB pointer */
+  S->pTwiddleBReal = (q31_t *) realCoefBQ31;
+
+  /*  Initialize the Flag for selection of RFFT or RIFFT */
+  S->ifftFlagR = (uint8_t) ifftFlagR;
+
+  /*  Initialize the Flag for calculation Bit reversal or not */
+  S->bitReverseFlagR = (uint8_t) bitReverseFlag;
+
+  /*  Initialization of coef modifier depending on the FFT length */
+  switch (S->fftLenReal)
+  {
+  case 512u:
+    S->twidCoefRModifier = 2u;
+    break;
+  case 128u:
+    S->twidCoefRModifier = 8u;
+    break;
+  default:
+    /*  Reporting argument error if rfftSize is not valid value */
+    status = ARM_MATH_ARGUMENT_ERROR;
+    break;
+  }
+
+  /* Init Complex FFT Instance */
+  S->pCfft = S_CFFT;
+
+  if(S->ifftFlagR)
+  {
+    /* Initializes the CIFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_q31(S->pCfft, (uint16_t) S->fftLenBy2, 1u, 1u);
+  }
+  else
+  {
+    /* Initializes the CFFT Module for fftLenreal/2 length */
+    arm_cfft_radix4_init_q31(S->pCfft, (uint16_t) S->fftLenBy2, 0u, 1u);
+  }
+
+  /* return the status of RFFT Init function */
+  return (status);
+
+}
+
+  /**   
+   * @} end of RFFT_RIFFT group   
+   */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c
new file mode 100644
index 0000000000..cf8e09ea52
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c
@@ -0,0 +1,457 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_rfft_q15.c   
+*   
+* Description:	RFFT & RIFFT Q15 process function   
+*   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------   
+*		Internal functions prototypes   
+--------------------------------------------------------------------*/
+
+void arm_split_rfft_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pATable,
+  q15_t * pBTable,
+  q15_t * pDst,
+  uint32_t modifier);
+
+void arm_split_rifft_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pATable,
+  q15_t * pBTable,
+  q15_t * pDst,
+  uint32_t modifier);
+
+/**   
+ * @addtogroup RFFT_RIFFT   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q15 RFFT/RIFFT.  
+ * @param[in]  *S    points to an instance of the Q15 RFFT/RIFFT structure.  
+ * @param[in]  *pSrc points to the input buffer.  
+ * @param[out] *pDst points to the output buffer.  
+ * @return none.  
+ *   
+ * \par Input an output formats:  
+ * \par   
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.   
+ * Hence the output format is different for different RFFT sizes.   
+ * The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:  
+ * \par   
+ * \image html RFFTQ15.gif "Input and Output Formats for Q15 RFFT"   
+ * \par   
+ * \image html RIFFTQ15.gif "Input and Output Formats for Q15 RIFFT"   
+ */
+
+void arm_rfft_q15(
+  const arm_rfft_instance_q15 * S,
+  q15_t * pSrc,
+  q15_t * pDst)
+{
+  const arm_cfft_radix4_instance_q15 *S_CFFT = S->pCfft;
+
+  /* Calculation of RIFFT of input */
+  if(S->ifftFlagR == 1u)
+  {
+    /*  Real IFFT core process */
+    arm_split_rifft_q15(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+    /* Complex readix-4 IFFT process */
+    arm_radix4_butterfly_inverse_q15(pDst, S_CFFT->fftLen,
+                                     S_CFFT->pTwiddle,
+                                     S_CFFT->twidCoefModifier);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_q15(pDst, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+  }
+  else
+  {
+    /* Calculation of RFFT of input */
+
+    /* Complex readix-4 FFT process */
+    arm_radix4_butterfly_q15(pSrc, S_CFFT->fftLen,
+                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_q15(pSrc, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+
+    arm_split_rfft_q15(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+  }
+
+}
+
+  /**   
+   * @} end of RFFT_RIFFT group   
+   */
+
+/**   
+ * @brief  Core Real FFT process   
+ * @param  *pSrc 				points to the input buffer.  
+ * @param  fftLen  				length of FFT.  
+ * @param  *pATable 			points to the A twiddle Coef buffer.   
+ * @param  *pBTable 			points to the B twiddle Coef buffer.  
+ * @param  *pDst 				points to the output buffer.  
+ * @param  modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.   
+ * The function implements a Real FFT   
+ */
+
+void arm_split_rfft_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pATable,
+  q15_t * pBTable,
+  q15_t * pDst,
+  uint32_t modifier)
+{
+  uint32_t i;                                    /* Loop Counter */
+  q31_t outR, outI;                              /* Temporary variables for output */
+  q15_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+  q15_t *pSrc1, *pSrc2;
+
+
+  pSrc[2u * fftLen] = pSrc[0];
+  pSrc[(2u * fftLen) + 1u] = pSrc[1];
+
+  pCoefA = &pATable[modifier * 2u];
+  pCoefB = &pBTable[modifier * 2u];
+
+  pSrc1 = &pSrc[2];
+  pSrc2 = &pSrc[(2u * fftLen) - 2u];
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  i = 1u;
+
+  while(i < fftLen)
+  {
+    /*   
+       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]   
+       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +   
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+     */
+
+    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1] */
+    outR = __SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA));
+
+#else
+
+    /* -(pSrc[2 * i + 1] * pATable[2 * i + 1] - pSrc[2 * i] * pATable[2 * i]) */
+    outR = -(__SMUSD(*__SIMD32(pSrc1), *__SIMD32(pCoefA)));
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* pSrc[2 * n - 2 * i] * pBTable[2 * i] +   
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
+    outR = __SMLAD(*__SIMD32(pSrc2), *__SIMD32(pCoefB), outR) >> 15u;
+
+    /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    outI = __SMUSDX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
+
+#else
+
+    outI = __SMUSDX(*__SIMD32(pCoefB), *__SIMD32(pSrc2)--);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] */
+    outI = __SMLADX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), outI);
+
+    /* write output */
+    pDst[2u * i] = (q15_t) outR;
+    pDst[(2u * i) + 1u] = outI >> 15u;
+
+    /* write complex conjugate output */
+    pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;
+    pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 15u);
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (2u * modifier);
+    pCoefA = pCoefA + (2u * modifier);
+
+    i++;
+
+  }
+
+  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+  pDst[(2u * fftLen) + 1u] = 0;
+
+  pDst[0] = pSrc[0] + pSrc[1];
+  pDst[1] = 0;
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  i = 1u;
+
+  while(i < fftLen)
+  {
+    /*   
+       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]   
+       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +   
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+     */
+
+    outR = *pSrc1 * *pCoefA;
+    outR = outR - (*(pSrc1 + 1) * *(pCoefA + 1));
+    outR = outR + (*pSrc2 * *pCoefB);
+    outR = (outR + (*(pSrc2 + 1) * *(pCoefB + 1))) >> 15;
+
+
+    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);  
+     */
+
+    outI = *pSrc2 * *(pCoefB + 1);
+    outI = outI - (*(pSrc2 + 1) * *pCoefB);
+    outI = outI + (*(pSrc1 + 1) * *pCoefA);
+    outI = outI + (*pSrc1 * *(pCoefA + 1));
+
+    /* update input pointers */
+    pSrc1 += 2u;
+    pSrc2 -= 2u;
+
+    /* write output */
+    pDst[2u * i] = (q15_t) outR;
+    pDst[(2u * i) + 1u] = outI >> 15u;
+
+    /* write complex conjugate output */
+    pDst[(4u * fftLen) - (2u * i)] = (q15_t) outR;
+    pDst[((4u * fftLen) - (2u * i)) + 1u] = -(outI >> 15u);
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (2u * modifier);
+    pCoefA = pCoefA + (2u * modifier);
+
+    i++;
+
+  }
+
+  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+  pDst[(2u * fftLen) + 1u] = 0;
+
+  pDst[0] = pSrc[0] + pSrc[1];
+  pDst[1] = 0;
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
+
+
+/**   
+ * @brief  Core Real IFFT process   
+ * @param[in]   *pSrc 				points to the input buffer.   
+ * @param[in]   fftLen  		    length of FFT.  
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.  
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.   
+ * @param[out]  *pDst 				points to the output buffer.  
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.   
+ * The function implements a Real IFFT   
+ */
+void arm_split_rifft_q15(
+  q15_t * pSrc,
+  uint32_t fftLen,
+  q15_t * pATable,
+  q15_t * pBTable,
+  q15_t * pDst,
+  uint32_t modifier)
+{
+  uint32_t i;                                    /* Loop Counter */
+  q31_t outR, outI;                              /* Temporary variables for output */
+  q15_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+  q15_t *pSrc1, *pSrc2;
+  q15_t *pDst1 = &pDst[0];
+
+  pCoefA = &pATable[0];
+  pCoefB = &pBTable[0];
+
+  pSrc1 = &pSrc[0];
+  pSrc2 = &pSrc[2u * fftLen];
+
+#ifndef ARM_MATH_CM0
+
+  /* Run the below code for Cortex-M4 and Cortex-M3 */
+
+  i = fftLen;
+
+  while(i > 0u)
+  {
+
+    /*   
+       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+
+       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   
+
+     */
+
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    /* pIn[2 * n - 2 * i] * pBTable[2 * i] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]) */
+    outR = __SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB));
+
+#else
+
+    /* -(-pIn[2 * n - 2 * i] * pBTable[2 * i] + 
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1])) */
+    outR = -(__SMUSD(*__SIMD32(pSrc2), *__SIMD32(pCoefB)));
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i] */
+    outR = __SMLAD(*__SIMD32(pSrc1), *__SIMD32(pCoefA), outR) >> 15u;
+
+    /*   
+       -pIn[2 * n - 2 * i] * pBTable[2 * i + 1] +   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+    outI = __SMUADX(*__SIMD32(pSrc2)--, *__SIMD32(pCoefB));
+
+    /* pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    outI = __SMLSDX(*__SIMD32(pCoefA), *__SIMD32(pSrc1)++, -outI);
+
+#else
+
+    outI = __SMLSDX(*__SIMD32(pSrc1)++, *__SIMD32(pCoefA), -outI);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+    /* write output */
+
+#ifndef ARM_MATH_BIG_ENDIAN
+
+    *__SIMD32(pDst1)++ = __PKHBT(outR, (outI >> 15u), 16);
+
+#else
+
+    *__SIMD32(pDst1)++ = __PKHBT((outI >> 15u), outR, 16);
+
+#endif /*      #ifndef ARM_MATH_BIG_ENDIAN     */
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (2u * modifier);
+    pCoefA = pCoefA + (2u * modifier);
+
+    i--;
+
+  }
+
+
+#else
+
+  /* Run the below code for Cortex-M0 */
+
+  i = fftLen;
+
+  while(i > 0u)
+  {
+
+    /*   
+       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+     */
+
+    outR = *pSrc2 * *pCoefB;
+    outR = outR - (*(pSrc2 + 1) * *(pCoefB + 1));
+    outR = outR + (*pSrc1 * *pCoefA);
+    outR = (outR + (*(pSrc1 + 1) * *(pCoefA + 1))) >> 15;
+
+    /*  
+       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -  
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -  
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);  
+     */
+
+    outI = *(pSrc1 + 1) * *pCoefA;
+    outI = outI - (*pSrc1 * *(pCoefA + 1));
+    outI = outI - (*pSrc2 * *(pCoefB + 1));
+    outI = outI - (*(pSrc2 + 1) * *(pCoefB));
+
+    /* update input pointers */
+    pSrc1 += 2u;
+    pSrc2 -= 2u;
+
+    /* write output */
+    *pDst1++ = (q15_t) outR;
+    *pDst1++ = (q15_t) (outI >> 15);
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (2u * modifier);
+    pCoefA = pCoefA + (2u * modifier);
+
+    i--;
+
+  }
+
+#endif /* #ifndef ARM_MATH_CM0 */
+
+}
diff --git a/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c
new file mode 100644
index 0000000000..49b076883b
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c
@@ -0,0 +1,326 @@
+/* ----------------------------------------------------------------------   
+* Copyright (C) 2010 ARM Limited. All rights reserved.   
+*   
+* $Date:        15. July 2011  
+* $Revision: 	V1.0.10  
+*   
+* Project: 	    CMSIS DSP Library   
+* Title:	    arm_rfft_q31.c   
+*   
+* Description:	RFFT & RIFFT Q31 process function   
+*   
+*   
+* Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+*  
+* Version 1.0.10 2011/7/15 
+*    Big Endian support added and Merged M0 and M3/M4 Source code.  
+*   
+* Version 1.0.3 2010/11/29  
+*    Re-organized the CMSIS folders and updated documentation.   
+*    
+* Version 1.0.2 2010/11/11   
+*    Documentation updated.    
+*   
+* Version 1.0.1 2010/10/05    
+*    Production release and review comments incorporated.   
+*   
+* Version 1.0.0 2010/09/20    
+*    Production release and review comments incorporated.   
+*   
+* Version 0.0.7  2010/06/10    
+*    Misra-C changes done   
+* -------------------------------------------------------------------- */
+
+#include "arm_math.h"
+
+/*--------------------------------------------------------------------   
+*		Internal functions prototypes   
+--------------------------------------------------------------------*/
+
+void arm_split_rfft_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pATable,
+  q31_t * pBTable,
+  q31_t * pDst,
+  uint32_t modifier);
+
+void arm_split_rifft_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pATable,
+  q31_t * pBTable,
+  q31_t * pDst,
+  uint32_t modifier);
+
+/**   
+ * @addtogroup RFFT_RIFFT   
+ * @{   
+ */
+
+/**   
+ * @brief Processing function for the Q31 RFFT/RIFFT.  
+ * @param[in]  *S    points to an instance of the Q31 RFFT/RIFFT structure.  
+ * @param[in]  *pSrc points to the input buffer.  
+ * @param[out] *pDst points to the output buffer.  
+ * @return none.  
+ *   
+ * \par Input an output formats:  
+ * \par   
+ * Internally input is downscaled by 2 for every stage to avoid saturations inside CFFT/CIFFT process.  
+ * Hence the output format is different for different RFFT sizes.   
+ * The input and output formats for different RFFT sizes and number of bits to upscale are mentioned in the tables below for RFFT and RIFFT:  
+ * \par   
+ * \image html RFFTQ31.gif "Input and Output Formats for Q31 RFFT"   
+ *   
+ * \par   
+ * \image html RIFFTQ31.gif "Input and Output Formats for Q31 RIFFT"   
+ */
+
+void arm_rfft_q31(
+  const arm_rfft_instance_q31 * S,
+  q31_t * pSrc,
+  q31_t * pDst)
+{
+  const arm_cfft_radix4_instance_q31 *S_CFFT = S->pCfft;
+
+  /* Calculation of RIFFT of input */
+  if(S->ifftFlagR == 1u)
+  {
+    /*  Real IFFT core process */
+    arm_split_rifft_q31(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                        S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+
+    /* Complex readix-4 IFFT process */
+    arm_radix4_butterfly_inverse_q31(pDst, S_CFFT->fftLen,
+                                     S_CFFT->pTwiddle,
+                                     S_CFFT->twidCoefModifier);
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_q31(pDst, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+  }
+  else
+  {
+    /* Calculation of RFFT of input */
+
+    /* Complex readix-4 FFT process */
+    arm_radix4_butterfly_q31(pSrc, S_CFFT->fftLen,
+                             S_CFFT->pTwiddle, S_CFFT->twidCoefModifier);
+
+    /* Bit reversal process */
+    if(S->bitReverseFlagR == 1u)
+    {
+      arm_bitreversal_q31(pSrc, S_CFFT->fftLen,
+                          S_CFFT->bitRevFactor, S_CFFT->pBitRevTable);
+    }
+
+    /*  Real FFT core process */
+    arm_split_rfft_q31(pSrc, S->fftLenBy2, S->pTwiddleAReal,
+                       S->pTwiddleBReal, pDst, S->twidCoefRModifier);
+  }
+
+}
+
+
+  /**   
+   * @} end of RFFT_RIFFT group   
+   */
+
+/**   
+ * @brief  Core Real FFT process   
+ * @param[in]   *pSrc 				points to the input buffer.   
+ * @param[in]   fftLen  			length of FFT.  
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.   
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.   
+ * @param[out]  *pDst 				points to the output buffer.   
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.   
+ */
+
+void arm_split_rfft_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pATable,
+  q31_t * pBTable,
+  q31_t * pDst,
+  uint32_t modifier)
+{
+  uint32_t i;                                    /* Loop Counter */
+  q31_t outR, outI;                              /* Temporary variables for output */
+  q31_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+  q31_t CoefA1, CoefA2, CoefB1;                  /* Temporary variables for twiddle coefficients */
+  q31_t *pOut1 = &pDst[2], *pOut2 = &pDst[(4u * fftLen) - 1u];
+  q31_t *pIn1 = &pSrc[2], *pIn2 = &pSrc[(2u * fftLen) - 1u];
+
+  pSrc[2u * fftLen] = pSrc[0];
+  pSrc[(2u * fftLen) + 1u] = pSrc[1];
+
+  /* Init coefficient pointers */
+  pCoefA = &pATable[modifier * 2u];
+  pCoefB = &pBTable[modifier * 2u];
+
+  i = fftLen - 1u;
+
+  while(i > 0u)
+  {
+    /*   
+       outR = (pSrc[2 * i] * pATable[2 * i] - pSrc[2 * i + 1] * pATable[2 * i + 1]   
+       + pSrc[2 * n - 2 * i] * pBTable[2 * i] +   
+       pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+     */
+
+    /* outI = (pIn[2 * i + 1] * pATable[2 * i] + pIn[2 * i] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]); */
+
+    CoefA1 = *pCoefA++;
+    CoefA2 = *pCoefA;
+
+    /* outR = (pSrc[2 * i] * pATable[2 * i] */
+    outR = ((int32_t) (((q63_t) * pIn1 * CoefA1) >> 32));
+
+    /* outI = pIn[2 * i] * pATable[2 * i + 1] */
+    outI = ((int32_t) (((q63_t) * pIn1++ * CoefA2) >> 32));
+
+    /* - pSrc[2 * i + 1] * pATable[2 * i + 1] */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn1 * (-CoefA2))) >> 32);
+
+    /* (pIn[2 * i + 1] * pATable[2 * i] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn1++ * (CoefA1))) >> 32);
+
+    /* pSrc[2 * n - 2 * i] * pBTable[2 * i]  */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (-CoefA2))) >> 32);
+    CoefB1 = *pCoefB;
+
+    /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (-CoefB1))) >> 32);
+
+    /* pSrc[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefB1))) >> 32);
+
+    /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (-CoefA2))) >> 32);
+
+    /* write output */
+    *pOut1++ = (outR << 1u);
+    *pOut1++ = (outI << 1u);
+
+    /* write complex conjugate output */
+    *pOut2-- = -(outI << 1u);
+    *pOut2-- = (outR << 1u);
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (modifier * 2u);
+    pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+    i--;
+
+  }
+
+  pDst[2u * fftLen] = pSrc[0] - pSrc[1];
+  pDst[(2u * fftLen) + 1u] = 0;
+
+  pDst[0] = pSrc[0] + pSrc[1];
+  pDst[1] = 0;
+
+}
+
+
+/**   
+ * @brief  Core Real IFFT process   
+ * @param[in]   *pSrc 				points to the input buffer.  
+ * @param[in]   fftLen  			length of FFT.   
+ * @param[in]   *pATable 			points to the twiddle Coef A buffer.  
+ * @param[in]   *pBTable 			points to the twiddle Coef B buffer.   
+ * @param[out]  *pDst 				points to the output buffer.  
+ * @param[in]   modifier 	        twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.  
+ * @return none.   
+ */
+
+void arm_split_rifft_q31(
+  q31_t * pSrc,
+  uint32_t fftLen,
+  q31_t * pATable,
+  q31_t * pBTable,
+  q31_t * pDst,
+  uint32_t modifier)
+{
+  q31_t outR, outI;                              /* Temporary variables for output */
+  q31_t *pCoefA, *pCoefB;                        /* Temporary pointers for twiddle factors */
+  q31_t CoefA1, CoefA2, CoefB1;                  /* Temporary variables for twiddle coefficients */
+  q31_t *pIn1 = &pSrc[0], *pIn2 = &pSrc[(2u * fftLen) + 1u];
+
+  pCoefA = &pATable[0];
+  pCoefB = &pBTable[0];
+
+  while(fftLen > 0u)
+  {
+    /*   
+       outR = (pIn[2 * i] * pATable[2 * i] + pIn[2 * i + 1] * pATable[2 * i + 1] +   
+       pIn[2 * n - 2 * i] * pBTable[2 * i] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1]);   
+
+       outI = (pIn[2 * i + 1] * pATable[2 * i] - pIn[2 * i] * pATable[2 * i + 1] -   
+       pIn[2 * n - 2 * i] * pBTable[2 * i + 1] -   
+       pIn[2 * n - 2 * i + 1] * pBTable[2 * i]);   
+
+     */
+    CoefA1 = *pCoefA++;
+    CoefA2 = *pCoefA;
+
+    /* outR = (pIn[2 * i] * pATable[2 * i] */
+    outR = ((int32_t) (((q63_t) * pIn1 * CoefA1) >> 32));
+
+    /* - pIn[2 * i] * pATable[2 * i + 1] */
+    outI = -((int32_t) (((q63_t) * pIn1++ * CoefA2) >> 32));
+
+    /* pIn[2 * i + 1] * pATable[2 * i + 1] */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn1 * (CoefA2))) >> 32);
+
+    /* pIn[2 * i + 1] * pATable[2 * i] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn1++ * (CoefA1))) >> 32);
+
+    /* pIn[2 * n - 2 * i] * pBTable[2 * i] */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefA2))) >> 32);
+
+    CoefB1 = *pCoefB;
+
+    /* pIn[2 * n - 2 * i] * pBTable[2 * i + 1] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) - ((q63_t) * pIn2-- * (CoefB1))) >> 32);
+
+    /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i + 1] */
+    outR =
+      (q31_t) ((((q63_t) outR << 32) + ((q63_t) * pIn2 * (CoefB1))) >> 32);
+
+    /* pIn[2 * n - 2 * i + 1] * pBTable[2 * i] */
+    outI =
+      (q31_t) ((((q63_t) outI << 32) + ((q63_t) * pIn2-- * (CoefA2))) >> 32);
+
+    /* write output */
+    *pDst++ = (outR << 1u);
+    *pDst++ = (outI << 1u);
+
+    /* update coefficient pointer */
+    pCoefB = pCoefB + (modifier * 2u);
+    pCoefA = pCoefA + ((modifier * 2u) - 1u);
+
+    /* Decrement loop count */
+    fftLen--;
+
+  }
+
+
+}
diff --git a/bsp/stm32f40x/Libraries/CMSIS/Include/arm_common_tables.h b/bsp/stm32f40x/Libraries/CMSIS/Include/arm_common_tables.h
new file mode 100644
index 0000000000..34f910f9ba
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/Include/arm_common_tables.h
@@ -0,0 +1,35 @@
+/* ---------------------------------------------------------------------- 
+* Copyright (C) 2010 ARM Limited. All rights reserved. 
+* 
+* $Date:        11. November 2010  
+* $Revision: 	V1.0.2  
+* 
+* Project: 	    CMSIS DSP Library 
+* Title:	    arm_common_tables.h 
+* 
+* Description:	This file has extern declaration for common tables like Bitreverse, reciprocal etc which are used across different functions 
+* 
+* Target Processor: Cortex-M4/Cortex-M3
+*  
+* Version 1.0.2 2010/11/11 
+*    Documentation updated.  
+* 
+* Version 1.0.1 2010/10/05  
+*    Production release and review comments incorporated. 
+* 
+* Version 1.0.0 2010/09/20  
+*    Production release and review comments incorporated. 
+* -------------------------------------------------------------------- */ 
+ 
+#ifndef _ARM_COMMON_TABLES_H 
+#define _ARM_COMMON_TABLES_H 
+ 
+#include "arm_math.h" 
+ 
+extern uint16_t armBitRevTable[256]; 
+extern q15_t armRecipTableQ15[64]; 
+extern q31_t armRecipTableQ31[64]; 
+extern const q31_t realCoefAQ31[1024];
+extern const q31_t realCoefBQ31[1024];
+ 
+#endif /*  ARM_COMMON_TABLES_H */ 
diff --git a/bsp/stm32f40x/Libraries/CMSIS/Include/arm_math.h b/bsp/stm32f40x/Libraries/CMSIS/Include/arm_math.h
new file mode 100644
index 0000000000..d8901db155
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/Include/arm_math.h
@@ -0,0 +1,7051 @@
+/* ----------------------------------------------------------------------   
+ * Copyright (C) 2010 ARM Limited. All rights reserved.   
+ *   
+ * $Date:        15. July 2011  
+ * $Revision: 	V1.0.10  
+ *   
+ * Project: 	    CMSIS DSP Library   
+ * Title:	     arm_math.h
+ *   
+ * Description:	 Public header file for CMSIS DSP Library
+ *   
+ * Target Processor: Cortex-M4/Cortex-M3/Cortex-M0
+ *  
+ * Version 1.0.10 2011/7/15 
+ *    Big Endian support added and Merged M0 and M3/M4 Source code.  
+ *   
+ * Version 1.0.3 2010/11/29  
+ *    Re-organized the CMSIS folders and updated documentation.   
+ *    
+ * Version 1.0.2 2010/11/11   
+ *    Documentation updated.    
+ *   
+ * Version 1.0.1 2010/10/05    
+ *    Production release and review comments incorporated.   
+ *   
+ * Version 1.0.0 2010/09/20    
+ *    Production release and review comments incorporated.   
+ * -------------------------------------------------------------------- */
+
+/**
+   \mainpage CMSIS DSP Software Library
+   *
+   * Introduction
+   *
+   * This user manual describes the CMSIS DSP software library, 
+   * a suite of common signal processing functions for use on Cortex-M processor based devices.
+   *
+   * The library is divided into a number of modules each covering a specific category:
+   * - Basic math functions
+   * - Fast math functions
+   * - Complex math functions
+   * - Filters
+   * - Matrix functions
+   * - Transforms
+   * - Motor control functions
+   * - Statistical functions
+   * - Support functions
+   * - Interpolation functions
+   *
+   * The library has separate functions for operating on 8-bit integers, 16-bit integers,
+   * 32-bit integer and 32-bit floating-point values. 
+   *
+   * Processor Support
+   *
+   * The library is completely written in C and is fully CMSIS compliant. 
+   * High performance is achieved through maximum use of Cortex-M4 intrinsics. 
+   *
+   * The supplied library source code also builds and runs on the Cortex-M3 and Cortex-M0 processor,
+   * with the DSP intrinsics being emulated through software. 
+   *
+   *
+   * Toolchain Support
+   *
+   * The library has been developed and tested with MDK-ARM version 4.21. 
+   * The library is being tested in GCC and IAR toolchains and updates on this activity will be made available shortly.
+   *
+   * Using the Library
+   *
+   * The library installer contains prebuilt versions of the libraries in the Lib folder.
+   * - arm_cortexM4lf_math.lib (Little endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4bf_math.lib (Big endian and Floating Point Unit on Cortex-M4)
+   * - arm_cortexM4l_math.lib (Little endian on Cortex-M4)
+   * - arm_cortexM4b_math.lib (Big endian on Cortex-M4)
+   * - arm_cortexM3l_math.lib (Little endian on Cortex-M3)
+   * - arm_cortexM3b_math.lib (Big endian on Cortex-M3)
+   * - arm_cortexM0l_math.lib (Little endian on Cortex-M0)
+   * - arm_cortexM0b_math.lib (Big endian on Cortex-M3)
+   *
+   * The library functions are declared in the public file arm_math.h which is placed in the Include folder.
+   * Simply include this file and link the appropriate library in the application and begin calling the library functions. The Library supports single 
+   * public header file  arm_math.h for Cortex-M4/M3/M0 with little endian and big endian. Same header file will be used for floating point unit(FPU) variants. 
+   * Define the appropriate pre processor MACRO ARM_MATH_CM4 or  ARM_MATH_CM3 or 
+   * ARM_MATH_CM0 depending on the target processor in the application.
+   *
+   * Examples
+   *
+   * The library ships with a number of examples which demonstrate how to use the library functions.
+   *
+   * Building the Library
+   *
+   * The library installer contains project files to re build libraries on MDK Tool chain in the CMSIS\DSP_Lib\Source\ARM folder.
+   * - arm_cortexM0b_math.uvproj
+   * - arm_cortexM0l_math.uvproj
+   * - arm_cortexM3b_math.uvproj
+   * - arm_cortexM3l_math.uvproj  
+   * - arm_cortexM4b_math.uvproj
+   * - arm_cortexM4l_math.uvproj
+   * - arm_cortexM4bf_math.uvproj
+   * - arm_cortexM4lf_math.uvproj
+   *
+   * Each library project have differant pre-processor macros.
+   *
+   * ARM_MATH_CMx:
+   * Define macro ARM_MATH_CM4 for building the library on Cortex-M4 target, ARM_MATH_CM3 for building library on Cortex-M3 target
+   * and ARM_MATH_CM0 for building library on cortex-M0 target.
+   *
+   * ARM_MATH_BIG_ENDIAN:
+   * Define macro ARM_MATH_BIG_ENDIAN to build the library for big endian targets. By default library builds for little endian targets.
+   *
+   * ARM_MATH_MATRIX_CHECK:
+   * Define macro for checking on the input and output sizes of matrices
+   *
+   * ARM_MATH_ROUNDING:
+   * Define macro for rounding on support functions
+   *
+   * __FPU_PRESENT:
+   * Initialize macro __FPU_PRESENT = 1 when building on FPU supported Targets. Enable this macro for M4bf and M4lf libraries 
+   *
+   *
+   * The project can be built by opening the appropriate project in MDK-ARM 4.21 chain and defining the optional pre processor MACROs detailed above.
+   *
+   * Copyright Notice
+   *
+   * Copyright (C) 2010 ARM Limited. All rights reserved.
+   */
+
+
+/**
+ * @defgroup groupMath Basic Math Functions
+ */
+
+/**
+ * @defgroup groupFastMath Fast Math Functions
+ * This set of functions provides a fast approximation to sine, cosine, and square root.
+ * As compared to most of the other functions in the CMSIS math library, the fast math functions
+ * operate on individual values and not arrays.
+ * There are separate functions for Q15, Q31, and floating-point data.
+ *
+ */
+
+/**
+ * @defgroup groupCmplxMath Complex Math Functions
+ * This set of functions operates on complex data vectors.
+ * The data in the complex arrays is stored in an interleaved fashion
+ * (real, imag, real, imag, ...).
+ * In the API functions, the number of samples in a complex array refers
+ * to the number of complex values; the array contains twice this number of
+ * real values.
+ */
+
+/**
+ * @defgroup groupFilters Filtering Functions
+ */
+
+/**
+ * @defgroup groupMatrix Matrix Functions
+ *
+ * This set of functions provides basic matrix math operations.
+ * The functions operate on matrix data structures.  For example,
+ * the type
+ * definition for the floating-point matrix structure is shown
+ * below:
+ * 
    + *     typedef struct
+ *     {
+ *       uint16_t numRows;     // number of rows of the matrix.
+ *       uint16_t numCols;     // number of columns of the matrix.
+ *       float32_t *pData;     // points to the data of the matrix.
+ *     } arm_matrix_instance_f32;
+ * 
    
+ * There are similar definitions for Q15 and Q31 data types.
+ *
+ * The structure specifies the size of the matrix and then points to
+ * an array of data.  The array is of size numRows X numCols
+ * and the values are arranged in row order.  That is, the
+ * matrix element (i, j) is stored at:
+ * 
    + *     pData[i*numCols + j]
+ * 
    
+ *
+ * \par Init Functions
+ * There is an associated initialization function for each type of matrix
+ * data structure.
+ * The initialization function sets the values of the internal structure fields.
+ * Refer to the function arm_mat_init_f32(), arm_mat_init_q31()
+ * and arm_mat_init_q15() for floating-point, Q31 and Q15 types,  respectively.
+ *
+ * \par
+ * Use of the initialization function is optional. However, if initialization function is used
+ * then the instance structure cannot be placed into a const data section.
+ * To place the instance structure in a const data
+ * section, manually initialize the data structure.  For example:
+ * 
    + * arm_matrix_instance_f32 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q31 S = {nRows, nColumns, pData};
+ * arm_matrix_instance_q15 S = {nRows, nColumns, pData};
+ * 
    
+ * where nRows specifies the number of rows, nColumns
+ * specifies the number of columns, and pData points to the
+ * data array.
+ *
+ * \par Size Checking
+ * By default all of the matrix functions perform size checking on the input and
+ * output matrices.  For example, the matrix addition function verifies that the
+ * two input matrices and the output matrix all have the same number of rows and
+ * columns.  If the size check fails the functions return:
+ * 
    + *     ARM_MATH_SIZE_MISMATCH
+ * 
    
+ * Otherwise the functions return
+ * 
    + *     ARM_MATH_SUCCESS
+ * 
    
+ * There is some overhead associated with this matrix size checking.
+ * The matrix size checking is enabled via the #define
+ * 
    + *     ARM_MATH_MATRIX_CHECK
+ * 
    
+ * within the library project settings.  By default this macro is defined
+ * and size checking is enabled.  By changing the project settings and
+ * undefining this macro size checking is eliminated and the functions
+ * run a bit faster.  With size checking disabled the functions always
+ * return ARM_MATH_SUCCESS.
+ */
+
+/**
+ * @defgroup groupTransforms Transform Functions
+ */
+
+/**
+ * @defgroup groupController Controller Functions
+ */
+
+/**
+ * @defgroup groupStats Statistics Functions
+ */
+/**
+ * @defgroup groupSupport Support Functions
+ */
+
+/**
+ * @defgroup groupInterpolation Interpolation Functions
+ * These functions perform 1- and 2-dimensional interpolation of data.
+ * Linear interpolation is used for 1-dimensional data and
+ * bilinear interpolation is used for 2-dimensional data.
+ */
+
+/**
+ * @defgroup groupExamples Examples
+ */
+#ifndef _ARM_MATH_H
+#define _ARM_MATH_H
+
+#define __CMSIS_GENERIC              /* disable NVIC and Systick functions */
+
+#if defined (ARM_MATH_CM4)
+  #include "core_cm4.h"
+#elif defined (ARM_MATH_CM3)
+  #include "core_cm3.h"
+#elif defined (ARM_MATH_CM0)
+  #include "core_cm0.h"
+#else
+#include "ARMCM4.h"
+#warning "Define either ARM_MATH_CM4 OR ARM_MATH_CM3...By Default building on ARM_MATH_CM4....."
+#endif
+
+#undef  __CMSIS_GENERIC              /* enable NVIC and Systick functions */
+#include "string.h"
+    #include "math.h"
+#ifdef	__cplusplus
+extern "C"
+{
+#endif
+
+
+  /**
+   * @brief Macros required for reciprocal calculation in Normalized LMS
+   */
+
+#define DELTA_Q31 			(0x100)
+#define DELTA_Q15 			0x5
+#define INDEX_MASK 			0x0000003F
+#define PI					3.14159265358979f
+
+  /**
+   * @brief Macros required for SINE and COSINE Fast math approximations
+   */
+
+#define TABLE_SIZE			256
+#define TABLE_SPACING_Q31	0x800000
+#define TABLE_SPACING_Q15	0x80
+
+  /**
+   * @brief Macros required for SINE and COSINE Controller functions
+   */
+  /* 1.31(q31) Fixed value of 2/360 */
+  /* -1 to +1 is divided into 360 values so total spacing is (2/360) */
+#define INPUT_SPACING			0xB60B61
+
+
+  /**
+   * @brief Error status returned by some functions in the library.
+   */
+
+  typedef enum
+    {
+      ARM_MATH_SUCCESS = 0,              /**< No error */
+      ARM_MATH_ARGUMENT_ERROR = -1,      /**< One or more arguments are incorrect */
+      ARM_MATH_LENGTH_ERROR = -2,        /**< Length of data buffer is incorrect */
+      ARM_MATH_SIZE_MISMATCH = -3,       /**< Size of matrices is not compatible with the operation. */
+      ARM_MATH_NANINF = -4,              /**< Not-a-number (NaN) or infinity is generated */
+      ARM_MATH_SINGULAR = -5,            /**< Generated by matrix inversion if the input matrix is singular and cannot be inverted. */
+      ARM_MATH_TEST_FAILURE = -6         /**< Test Failed  */
+    } arm_status;
+
+  /**
+   * @brief 8-bit fractional data type in 1.7 format.
+   */
+  typedef int8_t q7_t;
+
+  /**
+   * @brief 16-bit fractional data type in 1.15 format.
+   */
+  typedef int16_t q15_t;
+
+  /**
+   * @brief 32-bit fractional data type in 1.31 format.
+   */
+  typedef int32_t q31_t;
+
+  /**
+   * @brief 64-bit fractional data type in 1.63 format.
+   */
+  typedef int64_t q63_t;
+
+  /**
+   * @brief 32-bit floating-point type definition.
+   */
+  typedef float float32_t;
+
+  /**
+   * @brief 64-bit floating-point type definition.
+   */
+  typedef double float64_t;
+
+  /**
+   * @brief definition to read/write two 16 bit values.
+   */
+#define __SIMD32(addr)  (*(int32_t **) & (addr))
+
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
+  /**
+   * @brief definition to pack two 16 bit values.
+   */
+#define __PKHBT(ARG1, ARG2, ARG3)      ( (((int32_t)(ARG1) <<  0) & (int32_t)0x0000FFFF) | \
+                                         (((int32_t)(ARG2) << ARG3) & (int32_t)0xFFFF0000)  )
+
+#endif
+
+
+   /**
+   * @brief definition to pack four 8 bit values.
+   */
+#ifndef ARM_MATH_BIG_ENDIAN
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v0) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v1) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v2) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v3) << 24) & (int32_t)0xFF000000)  )
+#else								
+
+#define __PACKq7(v0,v1,v2,v3) ( (((int32_t)(v3) <<  0) & (int32_t)0x000000FF) |	\
+                                (((int32_t)(v2) <<  8) & (int32_t)0x0000FF00) |	\
+							    (((int32_t)(v1) << 16) & (int32_t)0x00FF0000) |	\
+							    (((int32_t)(v0) << 24) & (int32_t)0xFF000000)  )
+								
+#endif
+
+
+  /**
+   * @brief Clips Q63 to Q31 values.
+   */
+  static __INLINE q31_t clip_q63_to_q31(
+					q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFFFFFF ^ ((q31_t) (x >> 63)))) : (q31_t) x;
+  }
+
+  /**
+   * @brief Clips Q63 to Q15 values.
+   */
+  static __INLINE q15_t clip_q63_to_q15(
+					q63_t x)
+  {
+    return ((q31_t) (x >> 32) != ((q31_t) x >> 31)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 63)))) : (q15_t) (x >> 15);
+  }
+
+  /**
+   * @brief Clips Q31 to Q7 values.
+   */
+  static __INLINE q7_t clip_q31_to_q7(
+				      q31_t x)
+  {
+    return ((q31_t) (x >> 24) != ((q31_t) x >> 23)) ?
+      ((0x7F ^ ((q7_t) (x >> 31)))) : (q7_t) x;
+  }
+
+  /**
+   * @brief Clips Q31 to Q15 values.
+   */
+  static __INLINE q15_t clip_q31_to_q15(
+					q31_t x)
+  {
+    return ((q31_t) (x >> 16) != ((q31_t) x >> 15)) ?
+      ((0x7FFF ^ ((q15_t) (x >> 31)))) : (q15_t) x;
+  }
+
+  /**
+   * @brief Multiplies 32 X 64 and returns 32 bit result in 2.30 format.
+   */
+
+  static __INLINE q63_t mult32x64(
+				  q63_t x,
+				  q31_t y)
+  {
+    return ((((q63_t) (x & 0x00000000FFFFFFFF) * y) >> 32) +
+            (((q63_t) (x >> 32) * y)));
+  }
+
+
+#if defined (ARM_MATH_CM0) && defined ( __CC_ARM   )
+#define __CLZ __clz
+#endif 
+
+#if defined (ARM_MATH_CM0) && ((defined (__ICCARM__)) ||(defined (__GNUC__)) || defined (__TASKING__) )
+
+  static __INLINE  uint32_t __CLZ(q31_t data);
+
+
+  static __INLINE uint32_t __CLZ(q31_t data)
+  {
+	  uint32_t count = 0;
+	  uint32_t mask = 0x80000000;
+
+	  while((data & mask) ==  0)
+	  {
+		  count += 1u;
+		  mask = mask >> 1u;
+	  }
+
+	  return(count);
+
+  }
+
+#endif 
+
+  /**
+   * @brief Function to Calculates 1/in(reciprocal) value of Q31 Data type.
+   */
+
+  static __INLINE uint32_t arm_recip_q31(
+					 q31_t in,
+					 q31_t * dst,
+					 q31_t * pRecipTable)
+  {
+
+    uint32_t out, tempVal;
+    uint32_t index, i;
+    uint32_t signBits;
+
+    if(in > 0)
+      {
+	signBits = __CLZ(in) - 1;
+      }
+    else
+      {
+	signBits = __CLZ(-in) - 1;
+      }
+
+    /* Convert input sample to 1.31 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = (uint32_t) (in >> 24u);
+    index = (index & INDEX_MASK);
+
+    /* 1.31 with exp 1 */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0u; i < 2u; i++)
+      {
+	tempVal = (q31_t) (((q63_t) in * out) >> 31u);
+	tempVal = 0x7FFFFFFF - tempVal;
+	/*      1.31 with exp 1 */
+	//out = (q31_t) (((q63_t) out * tempVal) >> 30u);
+	out = (q31_t) clip_q63_to_q31(((q63_t) out * tempVal) >> 30u);
+      }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1u);
+
+  }
+
+  /**
+   * @brief Function to Calculates 1/in(reciprocal) value of Q15 Data type.
+   */
+  static __INLINE uint32_t arm_recip_q15(
+					 q15_t in,
+					 q15_t * dst,
+					 q15_t * pRecipTable)
+  {
+
+    uint32_t out = 0, tempVal = 0;
+    uint32_t index = 0, i = 0;
+    uint32_t signBits = 0;
+
+    if(in > 0)
+      {
+	signBits = __CLZ(in) - 17;
+      }
+    else
+      {
+	signBits = __CLZ(-in) - 17;
+      }
+
+    /* Convert input sample to 1.15 format */
+    in = in << signBits;
+
+    /* calculation of index for initial approximated Val */
+    index = in >> 8;
+    index = (index & INDEX_MASK);
+
+    /*      1.15 with exp 1  */
+    out = pRecipTable[index];
+
+    /* calculation of reciprocal value */
+    /* running approximation for two iterations */
+    for (i = 0; i < 2; i++)
+      {
+	tempVal = (q15_t) (((q31_t) in * out) >> 15);
+	tempVal = 0x7FFF - tempVal;
+	/*      1.15 with exp 1 */
+	out = (q15_t) (((q31_t) out * tempVal) >> 14);
+      }
+
+    /* write output */
+    *dst = out;
+
+    /* return num of signbits of out = 1/in value */
+    return (signBits + 1);
+
+  }
+
+
+  /*
+   * @brief C custom defined intrinisic function for only M0 processors
+   */
+#if defined(ARM_MATH_CM0)
+
+  static __INLINE q31_t __SSAT(
+			       q31_t x,
+			       uint32_t y)
+  {
+    int32_t posMax, negMin;
+    uint32_t i;
+
+    posMax = 1;
+    for (i = 0; i < (y - 1); i++)
+      {
+	posMax = posMax * 2;
+      }
+
+    if(x > 0)
+      {
+	posMax = (posMax - 1);
+
+	if(x > posMax)
+	  {
+	    x = posMax;
+	  }
+      }
+    else
+      {
+	negMin = -posMax;
+
+	if(x < negMin)
+	  {
+	    x = negMin;
+	  }
+      }
+    return (x);
+
+
+  }
+
+#endif /* end of ARM_MATH_CM0 */
+
+
+
+  /*
+   * @brief C custom defined intrinsic function for M3 and M0 processors
+   */
+#if defined (ARM_MATH_CM3) || defined (ARM_MATH_CM0)
+
+  /*
+   * @brief C custom defined QADD8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD8(
+				q31_t x,
+				q31_t y)
+  {
+
+    q31_t sum;
+    q7_t r, s, t, u;
+
+    r = (char) x;
+    s = (char) y;
+
+    r = __SSAT((q31_t) (r + s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) + ((y << 16) >> 24))), 8);
+    t = __SSAT(((q31_t) (((x << 8) >> 24) + ((y << 8) >> 24))), 8);
+    u = __SSAT(((q31_t) ((x >> 24) + (y >> 24))), 8);
+
+    sum = (((q31_t) u << 24) & 0xFF000000) | (((q31_t) t << 16) & 0x00FF0000) |
+      (((q31_t) s << 8) & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB8 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB8(
+				q31_t x,
+				q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s, t, u;
+
+    r = (char) x;
+    s = (char) y;
+
+    r = __SSAT((r - s), 8);
+    s = __SSAT(((q31_t) (((x << 16) >> 24) - ((y << 16) >> 24))), 8) << 8;
+    t = __SSAT(((q31_t) (((x << 8) >> 24) - ((y << 8) >> 24))), 8) << 16;
+    u = __SSAT(((q31_t) ((x >> 24) - (y >> 24))), 8) << 24;
+
+    sum =
+      (u & 0xFF000000) | (t & 0x00FF0000) | (s & 0x0000FF00) | (r & 0x000000FF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+
+  /*
+   * @brief C custom defined QADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD16(
+				 q31_t x,
+				 q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r + s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) + (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined SHADD16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHADD16(
+				  q31_t x,
+				  q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (s >> 1));
+    s = ((q31_t) ((x >> 17) + (y >> 17))) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+
+  }
+
+  /*
+   * @brief C custom defined QSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB16(
+				 q31_t x,
+				 q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = __SSAT(r - s, 16);
+    s = __SSAT(((q31_t) ((x >> 16) - (y >> 16))), 16) << 16;
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSUB16 for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSUB16(
+				  q31_t x,
+				  q31_t y)
+  {
+
+    q31_t diff;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (s >> 1));
+    s = (((x >> 17) - (y >> 17)) << 16);
+
+    diff = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return diff;
+  }
+
+  /*
+   * @brief C custom defined QASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QASX(
+			       q31_t x,
+			       q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) + (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x - (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHASX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHASX(
+				q31_t x,
+				q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) - (y >> 17));
+    s = (((x >> 17) + (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+
+  /*
+   * @brief C custom defined QSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSAX(
+			       q31_t x,
+			       q31_t y)
+  {
+
+    q31_t sum = 0;
+
+    sum = ((sum + clip_q31_to_q15((q31_t) ((short) (x >> 16) - (short) y))) << 16) +
+      clip_q31_to_q15((q31_t) ((short) x + (short) (y >> 16)));
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SHSAX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SHSAX(
+				q31_t x,
+				q31_t y)
+  {
+
+    q31_t sum;
+    q31_t r, s;
+
+    r = (short) x;
+    s = (short) y;
+
+    r = ((r >> 1) + (y >> 17));
+    s = (((x >> 17) - (s >> 1)) << 16);
+
+    sum = (s & 0xFFFF0000) | (r & 0x0000FFFF);
+
+    return sum;
+  }
+
+  /*
+   * @brief C custom defined SMUSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSDX(
+				 q31_t x,
+				 q31_t y)
+  {
+
+    return ((q31_t)(((short) x * (short) (y >> 16)) -
+		    ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined SMUADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUADX(
+				 q31_t x,
+				 q31_t y)
+  {
+
+    return ((q31_t)(((short) x * (short) (y >> 16)) +
+		    ((short) (x >> 16) * (short) y)));
+  }
+
+  /*
+   * @brief C custom defined QADD for M3 and M0 processors
+   */
+  static __INLINE q31_t __QADD(
+			       q31_t x,
+			       q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x + y);
+  }
+
+  /*
+   * @brief C custom defined QSUB for M3 and M0 processors
+   */
+  static __INLINE q31_t __QSUB(
+			       q31_t x,
+			       q31_t y)
+  {
+    return clip_q63_to_q31((q63_t) x - y);
+  }
+
+  /*
+   * @brief C custom defined SMLAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLAD(
+				q31_t x,
+				q31_t y,
+				q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLADX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLADX(
+				 q31_t x,
+				 q31_t y,
+				 q31_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLSDX for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMLSDX(
+				 q31_t x,
+				 q31_t y,
+				 q31_t sum)
+  {
+
+    return (sum - ((short) (x >> 16) * (short) (y)) +
+            ((short) x * (short) (y >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMLALD for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALD(
+				 q31_t x,
+				 q31_t y,
+				 q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) (y >> 16)) +
+            ((short) x * (short) y));
+  }
+
+  /*
+   * @brief C custom defined SMLALDX for M3 and M0 processors
+   */
+  static __INLINE q63_t __SMLALDX(
+				  q31_t x,
+				  q31_t y,
+				  q63_t sum)
+  {
+
+    return (sum + ((short) (x >> 16) * (short) y)) +
+      ((short) x * (short) (y >> 16));
+  }
+
+  /*
+   * @brief C custom defined SMUAD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUAD(
+				q31_t x,
+				q31_t y)
+  {
+
+    return (((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+  /*
+   * @brief C custom defined SMUSD for M3 and M0 processors
+   */
+  static __INLINE q31_t __SMUSD(
+				q31_t x,
+				q31_t y)
+  {
+
+    return (-((x >> 16) * (y >> 16)) +
+            (((x << 16) >> 16) * ((y << 16) >> 16)));
+  }
+
+
+
+
+#endif /* (ARM_MATH_CM3) || defined (ARM_MATH_CM0) */
+
+
+  /**
+   * @brief Instance structure for the Q7 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;        /**< number of filter coefficients in the filter. */
+    q7_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q7_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q7;
+
+  /**
+   * @brief Instance structure for the Q15 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q15_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+  } arm_fir_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;         /**< number of filter coefficients in the filter. */
+    q31_t *pState;            /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of filter coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+  } arm_fir_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q7 FIR filter.
+   * @param[in] *S points to an instance of the Q7 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q7(
+		  const arm_fir_instance_q7 * S,
+		   q7_t * pSrc,
+		  q7_t * pDst,
+		  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q7 FIR filter.
+   * @param[in,out] *S points to an instance of the Q7 FIR structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed.
+   * @return none
+   */
+  void arm_fir_init_q7(
+		       arm_fir_instance_q7 * S,
+		       uint16_t numTaps,
+		       q7_t * pCoeffs,
+		       q7_t * pState,
+		       uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR filter.
+   * @param[in] *S points to an instance of the Q15 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q15(
+		   const arm_fir_instance_q15 * S,
+		    q15_t * pSrc,
+		   q15_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q15 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q15(
+			const arm_fir_instance_q15 * S,
+			 q15_t * pSrc,
+			q15_t * pDst,
+			uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 FIR filter.
+   * @param[in,out] *S points to an instance of the Q15 FIR filter structure.
+   * @param[in] numTaps  Number of filter coefficients in the filter. Must be even and greater than or equal to 4.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of samples that are processed at a time.
+   * @return The function returns ARM_MATH_SUCCESS if initialization was successful or ARM_MATH_ARGUMENT_ERROR if
+   * numTaps is not a supported value.
+   */
+   
+       arm_status arm_fir_init_q15(
+			      arm_fir_instance_q15 * S,
+			      uint16_t numTaps,
+			      q15_t * pCoeffs,
+			      q15_t * pState,
+			      uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR filter.
+   * @param[in] *S points to an instance of the Q31 FIR filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_q31(
+		   const arm_fir_instance_q31 * S,
+		    q31_t * pSrc,
+		   q31_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the fast Q31 FIR filter for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_fast_q31(
+			const arm_fir_instance_q31 * S,
+			 q31_t * pSrc,
+			q31_t * pDst,
+			uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR filter.
+   * @param[in,out] *S points to an instance of the Q31 FIR structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return 		none.
+   */
+  void arm_fir_init_q31(
+			arm_fir_instance_q31 * S,
+			uint16_t numTaps,
+			q31_t * pCoeffs,
+			q31_t * pState,
+			uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the floating-point FIR filter.
+   * @param[in] *S points to an instance of the floating-point FIR structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_f32(
+		   const arm_fir_instance_f32 * S,
+		    float32_t * pSrc,
+		   float32_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR filter.
+   * @param[in,out] *S points to an instance of the floating-point FIR filter structure.
+   * @param[in] 	numTaps  Number of filter coefficients in the filter.
+   * @param[in] 	*pCoeffs points to the filter coefficients.
+   * @param[in] 	*pState points to the state buffer.
+   * @param[in] 	blockSize number of samples that are processed at a time.
+   * @return    	none.
+   */
+  void arm_fir_init_f32(
+			arm_fir_instance_f32 * S,
+			uint16_t numTaps,
+			float32_t * pCoeffs,
+			float32_t * pState,
+			uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    int8_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q15_t *pState;            /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q15_t *pCoeffs;           /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    int8_t postShift;         /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q15;
+
+
+  /**
+   * @brief Instance structure for the Q31 Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;      /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q31_t *pState;           /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< Additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_casd_df1_inst_q31;
+
+  /**
+   * @brief Instance structure for the floating-point Biquad cascade filter.
+   */
+  typedef struct
+  {
+    uint32_t numStages;         /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;          /**< Points to the array of state coefficients.  The array is of length 4*numStages. */
+    float32_t *pCoeffs;         /**< Points to the array of coefficients.  The array is of length 5*numStages. */
+
+
+  } arm_biquad_casd_df1_inst_f32;
+
+
+
+  /**
+   * @brief Processing function for the Q15 Biquad cascade filter.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q15(
+				  const arm_biquad_casd_df1_inst_q15 * S,
+				   q15_t * pSrc,
+				  q15_t * pDst,
+				  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q15 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q15(
+				       arm_biquad_casd_df1_inst_q15 * S,
+				       uint8_t numStages,
+				       q15_t * pCoeffs,
+				       q15_t * pState,
+				       int8_t postShift);
+
+
+  /**
+   * @brief Fast but less precise processing function for the Q15 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S points to an instance of the Q15 Biquad cascade structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q15(
+				       const arm_biquad_casd_df1_inst_q15 * S,
+				        q15_t * pSrc,
+				       q15_t * pDst,
+				       uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 Biquad cascade filter
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_q31(
+				  const arm_biquad_casd_df1_inst_q31 * S,
+				   q31_t * pSrc,
+				  q31_t * pDst,
+				  uint32_t blockSize);
+
+  /**
+   * @brief Fast but less precise processing function for the Q31 Biquad cascade filter for Cortex-M3 and Cortex-M4.
+   * @param[in]  *S         points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_fast_q31(
+				       const arm_biquad_casd_df1_inst_q31 * S,
+				        q31_t * pSrc,
+				       q31_t * pDst,
+				       uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the Q31 Biquad cascade structure.
+   * @param[in]     numStages      number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    Shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_q31(
+				       arm_biquad_casd_df1_inst_q31 * S,
+				       uint8_t numStages,
+				       q31_t * pCoeffs,
+				       q31_t * pState,
+				       int8_t postShift);
+
+  /**
+   * @brief Processing function for the floating-point Biquad cascade filter.
+   * @param[in]  *S         points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]  *pSrc      points to the block of input data.
+   * @param[out] *pDst      points to the block of output data.
+   * @param[in]  blockSize  number of samples to process.
+   * @return     none.
+   */
+
+  void arm_biquad_cascade_df1_f32(
+				  const arm_biquad_casd_df1_inst_f32 * S,
+				   float32_t * pSrc,
+				  float32_t * pDst,
+				  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the floating-point Biquad cascade structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df1_init_f32(
+				       arm_biquad_casd_df1_inst_f32 * S,
+				       uint8_t numStages,
+				       float32_t * pCoeffs,
+				       float32_t * pState);
+
+
+  /**
+   * @brief Instance structure for the floating-point matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    float32_t *pData;     /**< points to the data of the matrix. */
+  } arm_matrix_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q15 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q15_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 matrix structure.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;     /**< number of rows of the matrix.     */
+    uint16_t numCols;     /**< number of columns of the matrix.  */
+    q31_t *pData;         /**< points to the data of the matrix. */
+
+  } arm_matrix_instance_q31;
+
+
+
+  /**
+   * @brief Floating-point matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_f32(
+			     const arm_matrix_instance_f32 * pSrcA,
+			     const arm_matrix_instance_f32 * pSrcB,
+			     arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q15(
+			     const arm_matrix_instance_q15 * pSrcA,
+			     const arm_matrix_instance_q15 * pSrcB,
+			     arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix addition.
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_add_q31(
+			     const arm_matrix_instance_q31 * pSrcA,
+			     const arm_matrix_instance_q31 * pSrcB,
+			     arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
+   * or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_f32(
+			       const arm_matrix_instance_f32 * pSrc,
+			       arm_matrix_instance_f32 * pDst);
+
+
+  /**
+   * @brief Q15 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
+   * or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q15(
+			       const arm_matrix_instance_q15 * pSrc,
+			       arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix transpose.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[out] *pDst points to the output matrix
+   * @return 	The function returns either  ARM_MATH_SIZE_MISMATCH
+   * or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_trans_q31(
+			       const arm_matrix_instance_q31 * pSrc,
+			       arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_f32(
+			      const arm_matrix_instance_f32 * pSrcA,
+			      const arm_matrix_instance_f32 * pSrcB,
+			      arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q15(
+			      const arm_matrix_instance_q15 * pSrcA,
+			      const arm_matrix_instance_q15 * pSrcB,
+			      arm_matrix_instance_q15 * pDst,
+			      q15_t * pState);
+
+  /**
+   * @brief Q15 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA  points to the first input matrix structure
+   * @param[in]       *pSrcB  points to the second input matrix structure
+   * @param[out]      *pDst   points to output matrix structure
+   * @param[in]		  *pState points to the array for storing intermediate results  
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q15(
+				   const arm_matrix_instance_q15 * pSrcA,
+				   const arm_matrix_instance_q15 * pSrcB,
+				   arm_matrix_instance_q15 * pDst,
+				   q15_t * pState);
+
+  /**
+   * @brief Q31 matrix multiplication
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_q31(
+			      const arm_matrix_instance_q31 * pSrcA,
+			      const arm_matrix_instance_q31 * pSrcB,
+			      arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Q31 matrix multiplication (fast variant) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_mult_fast_q31(
+				   const arm_matrix_instance_q31 * pSrcA,
+				   const arm_matrix_instance_q31 * pSrcB,
+				   arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief Floating-point matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_f32(
+			     const arm_matrix_instance_f32 * pSrcA,
+			     const arm_matrix_instance_f32 * pSrcB,
+			     arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q15(
+			     const arm_matrix_instance_q15 * pSrcA,
+			     const arm_matrix_instance_q15 * pSrcB,
+			     arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix subtraction
+   * @param[in]       *pSrcA points to the first input matrix structure
+   * @param[in]       *pSrcB points to the second input matrix structure
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_sub_q31(
+			     const arm_matrix_instance_q31 * pSrcA,
+			     const arm_matrix_instance_q31 * pSrcB,
+			     arm_matrix_instance_q31 * pDst);
+
+  /**
+   * @brief Floating-point matrix scaling.
+   * @param[in]  *pSrc points to the input matrix
+   * @param[in]  scale scale factor
+   * @param[out] *pDst points to the output matrix
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_f32(
+			       const arm_matrix_instance_f32 * pSrc,
+			       float32_t scale,
+			       arm_matrix_instance_f32 * pDst);
+
+  /**
+   * @brief Q15 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q15(
+			       const arm_matrix_instance_q15 * pSrc,
+			       q15_t scaleFract,
+			       int32_t shift,
+			       arm_matrix_instance_q15 * pDst);
+
+  /**
+   * @brief Q31 matrix scaling.
+   * @param[in]       *pSrc points to input matrix
+   * @param[in]       scaleFract fractional portion of the scale factor
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to output matrix structure
+   * @return     The function returns either
+   * ARM_MATH_SIZE_MISMATCH or ARM_MATH_SUCCESS based on the outcome of size checking.
+   */
+
+  arm_status arm_mat_scale_q31(
+			       const arm_matrix_instance_q31 * pSrc,
+			       q31_t scaleFract,
+			       int32_t shift,
+			       arm_matrix_instance_q31 * pDst);
+
+
+  /**
+   * @brief  Q31 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q31(
+			arm_matrix_instance_q31 * S,
+			uint16_t nRows,
+			uint16_t nColumns,
+			q31_t   *pData);
+
+  /**
+   * @brief  Q15 matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_q15(
+			arm_matrix_instance_q15 * S,
+			uint16_t nRows,
+			uint16_t nColumns,
+			q15_t    *pData);
+
+  /**
+   * @brief  Floating-point matrix initialization.
+   * @param[in,out] *S             points to an instance of the floating-point matrix structure.
+   * @param[in]     nRows          number of rows in the matrix.
+   * @param[in]     nColumns       number of columns in the matrix.
+   * @param[in]     *pData	       points to the matrix data array.
+   * @return        none
+   */
+
+  void arm_mat_init_f32(
+			arm_matrix_instance_f32 * S,
+			uint16_t nRows,
+			uint16_t nColumns,
+			float32_t   *pData);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 PID Control.
+   */
+  typedef struct
+  {
+    q15_t A0; 	 /**< The derived gain, A0 = Kp + Ki + Kd . */
+	#ifdef ARM_MATH_CM0  
+	q15_t A1;
+	q15_t A2; 
+	#else 	      
+    q31_t A1;           /**< The derived gain A1 = -Kp - 2Kd | Kd.*/
+	#endif 
+    q15_t state[3];       /**< The state array of length 3. */
+    q15_t Kp;           /**< The proportional gain. */
+    q15_t Ki;           /**< The integral gain. */
+    q15_t Kd;           /**< The derivative gain. */
+  } arm_pid_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 PID Control.
+   */
+  typedef struct
+  {
+    q31_t A0;            /**< The derived gain, A0 = Kp + Ki + Kd . */
+    q31_t A1;            /**< The derived gain, A1 = -Kp - 2Kd. */
+    q31_t A2;            /**< The derived gain, A2 = Kd . */
+    q31_t state[3];      /**< The state array of length 3. */
+    q31_t Kp;            /**< The proportional gain. */
+    q31_t Ki;            /**< The integral gain. */
+    q31_t Kd;            /**< The derivative gain. */
+
+  } arm_pid_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point PID Control.
+   */
+  typedef struct
+  {
+    float32_t A0;          /**< The derived gain, A0 = Kp + Ki + Kd . */
+    float32_t A1;          /**< The derived gain, A1 = -Kp - 2Kd. */
+    float32_t A2;          /**< The derived gain, A2 = Kd . */
+    float32_t state[3];    /**< The state array of length 3. */
+    float32_t Kp;               /**< The proportional gain. */
+    float32_t Ki;               /**< The integral gain. */
+    float32_t Kd;               /**< The derivative gain. */
+  } arm_pid_instance_f32;
+
+
+
+  /**
+   * @brief  Initialization function for the floating-point PID Control.
+   * @param[in,out] *S      points to an instance of the PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_f32(
+			arm_pid_instance_f32 * S,
+			int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_f32(
+			 arm_pid_instance_f32 * S);
+
+
+  /**
+   * @brief  Initialization function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in]     resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q31(
+			arm_pid_instance_q31 * S,
+			int32_t resetStateFlag);
+
+ 
+  /**
+   * @brief  Reset function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @return none
+   */
+
+  void arm_pid_reset_q31(
+			 arm_pid_instance_q31 * S);
+
+  /**
+   * @brief  Initialization function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID structure.
+   * @param[in] resetStateFlag  flag to reset the state. 0 = no change in state 1 = reset the state.
+   * @return none.
+   */
+  void arm_pid_init_q15(
+			arm_pid_instance_q15 * S,
+			int32_t resetStateFlag);
+
+  /**
+   * @brief  Reset function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the q15 PID Control structure
+   * @return none
+   */
+  void arm_pid_reset_q15(
+			 arm_pid_instance_q15 * S);
+
+
+  /**
+   * @brief Instance structure for the floating-point Linear Interpolate function.
+   */
+  typedef struct
+  {
+    uint32_t nValues;
+    float32_t x1;
+    float32_t xSpacing;
+    float32_t *pYData;          /**< pointer to the table of Y values */
+  } arm_linear_interp_instance_f32;
+
+  /**
+   * @brief Instance structure for the floating-point bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;	/**< number of rows in the data table. */
+    uint16_t numCols;	/**< number of columns in the data table. */
+    float32_t *pData;	/**< points to the data table. */
+  } arm_bilinear_interp_instance_f32;
+
+   /**
+   * @brief Instance structure for the Q31 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;	/**< number of rows in the data table. */
+    uint16_t numCols;	/**< number of columns in the data table. */
+    q31_t *pData;	/**< points to the data table. */
+  } arm_bilinear_interp_instance_q31;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows;	/**< number of rows in the data table. */
+    uint16_t numCols;	/**< number of columns in the data table. */
+    q15_t *pData;	/**< points to the data table. */
+  } arm_bilinear_interp_instance_q15;
+
+   /**
+   * @brief Instance structure for the Q15 bilinear interpolation function.
+   */
+
+  typedef struct
+  {
+    uint16_t numRows; 	/**< number of rows in the data table. */
+    uint16_t numCols;	/**< number of columns in the data table. */
+    q7_t *pData;		/**< points to the data table. */
+  } arm_bilinear_interp_instance_q7;
+
+
+  /**
+   * @brief Q7 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q7(
+		    q7_t * pSrcA,
+		    q7_t * pSrcB,
+		   q7_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst  points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q15(
+		     q15_t * pSrcA,
+		     q15_t * pSrcB,
+		    q15_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_q31(
+		     q31_t * pSrcA,
+		     q31_t * pSrcB,
+		    q31_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector multiplication.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_mult_f32(
+		     float32_t * pSrcA,
+		     float32_t * pSrcB,
+		    float32_t * pDst,
+		    uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q15 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t  fftLen;                /**< length of the FFT. */
+    uint8_t   ifftFlag;              /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t   bitReverseFlag;        /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q15_t     *pTwiddle;             /**< points to the twiddle factor table. */
+    uint16_t  *pBitRevTable;         /**< points to the bit reversal table. */
+    uint16_t  twidCoefModifier;      /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t  bitRevFactor;          /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t    fftLen;              /**< length of the FFT. */
+    uint8_t     ifftFlag;            /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t     bitReverseFlag;      /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    q31_t       *pTwiddle;           /**< points to the twiddle factor table. */
+    uint16_t    *pBitRevTable;       /**< points to the bit reversal table. */
+    uint16_t    twidCoefModifier;    /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t    bitRevFactor;        /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+  } arm_cfft_radix4_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point CFFT/CIFFT function.
+   */
+
+  typedef struct
+  {
+    uint16_t     fftLen;               /**< length of the FFT. */
+    uint8_t      ifftFlag;             /**< flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform. */
+    uint8_t      bitReverseFlag;       /**< flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output. */
+    float32_t    *pTwiddle;            /**< points to the twiddle factor table. */
+    uint16_t     *pBitRevTable;        /**< points to the bit reversal table. */
+    uint16_t     twidCoefModifier;     /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    uint16_t     bitRevFactor;         /**< bit reversal modifier that supports different size FFTs with the same bit reversal table. */
+	float32_t    onebyfftLen;          /**< value of 1/fftLen. */
+  } arm_cfft_radix4_instance_f32;
+
+  /**
+   * @brief Processing function for the Q15 CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the Q15 CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix4_q15(
+			   const arm_cfft_radix4_instance_q15 * S,
+			   q15_t * pSrc);
+
+  /**
+   * @brief Initialization function for the Q15 CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the Q15 CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+   */
+
+  arm_status arm_cfft_radix4_init_q15(
+				      arm_cfft_radix4_instance_q15 * S,
+				      uint16_t fftLen,
+				      uint8_t ifftFlag,
+				      uint8_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the Q31 CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the Q31 CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix4_q31(
+			   const arm_cfft_radix4_instance_q31 * S,
+			   q31_t * pSrc);
+
+  /**
+   * @brief  Initialization function for the Q31 CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the Q31 CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        arm_status     function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+   */
+  
+  arm_status arm_cfft_radix4_init_q31(
+				      arm_cfft_radix4_instance_q31 * S,
+				      uint16_t fftLen,
+				      uint8_t ifftFlag,
+				      uint8_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the floating-point CFFT/CIFFT.
+   * @param[in]      *S    points to an instance of the floating-point CFFT/CIFFT structure.
+   * @param[in, out] *pSrc points to the complex data buffer. Processing occurs in-place.
+   * @return none.
+   */
+
+  void arm_cfft_radix4_f32(
+			   const arm_cfft_radix4_instance_f32 * S,
+			   float32_t * pSrc);
+
+  /**
+   * @brief  Initialization function for the floating-point CFFT/CIFFT.
+   * @param[in,out] *S             points to an instance of the floating-point CFFT/CIFFT structure.
+   * @param[in]     fftLen         length of the FFT.
+   * @param[in]     ifftFlag       flag that selects forward (ifftFlag=0) or inverse (ifftFlag=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLen is not a supported value.
+   */
+  
+  arm_status arm_cfft_radix4_init_f32(
+				      arm_cfft_radix4_instance_f32 * S,
+				      uint16_t fftLen,
+				      uint8_t ifftFlag,
+				      uint8_t bitReverseFlag);
+
+
+
+  /*----------------------------------------------------------------------
+   *		Internal functions prototypes FFT function
+   ----------------------------------------------------------------------*/
+
+  /**
+   * @brief  Core function for the floating-point CFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef           points to the twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+  
+  void arm_radix4_butterfly_f32(
+				float32_t * pSrc,
+				uint16_t fftLen,
+				float32_t * pCoef,
+				uint16_t twidCoefModifier);
+
+  /**
+   * @brief  Core function for the floating-point CIFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of floating-point data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef           points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @param[in]      onebyfftLen      value of 1/fftLen.
+   * @return none.
+   */
+  
+  void arm_radix4_butterfly_inverse_f32(
+					float32_t * pSrc,
+					uint16_t fftLen,
+					float32_t * pCoef,
+					uint16_t twidCoefModifier,
+					float32_t onebyfftLen);
+
+  /**
+   * @brief  In-place bit reversal function.
+   * @param[in, out] *pSrc        points to the in-place buffer of floating-point data type.
+   * @param[in]      fftSize      length of the FFT.
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table.
+   * @param[in]      *pBitRevTab  points to the bit reversal table.
+   * @return none.
+   */
+
+  void arm_bitreversal_f32(
+			   float32_t *pSrc,
+			   uint16_t fftSize,
+			   uint16_t bitRevFactor,
+			   uint16_t *pBitRevTab);
+
+  /**
+   * @brief  Core function for the Q31 CFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef           points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+  
+  void arm_radix4_butterfly_q31(
+				q31_t *pSrc,
+				uint32_t fftLen,
+				q31_t *pCoef,
+				uint32_t twidCoefModifier);
+
+  /**
+   * @brief  Core function for the Q31 CIFFT butterfly process.
+   * @param[in, out] *pSrc            points to the in-place buffer of Q31 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef           points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+  
+  void arm_radix4_butterfly_inverse_q31(
+					q31_t * pSrc,
+					uint32_t fftLen,
+					q31_t * pCoef,
+					uint32_t twidCoefModifier);
+  
+  /**
+   * @brief  In-place bit reversal function.
+   * @param[in, out] *pSrc        points to the in-place buffer of Q31 data type.
+   * @param[in]      fftLen       length of the FFT.
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+   * @param[in]      *pBitRevTab  points to bit reversal table.
+   * @return none.
+   */
+
+  void arm_bitreversal_q31(
+			   q31_t * pSrc,
+			   uint32_t fftLen,
+			   uint16_t bitRevFactor,
+			   uint16_t *pBitRevTab);
+
+  /**
+   * @brief  Core function for the Q15 CFFT butterfly process.
+   * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef16         points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+
+  void arm_radix4_butterfly_q15(
+				q15_t *pSrc16,
+				uint32_t fftLen,
+				q15_t *pCoef16,
+				uint32_t twidCoefModifier);
+
+  /**
+   * @brief  Core function for the Q15 CIFFT butterfly process.
+   * @param[in, out] *pSrc16          points to the in-place buffer of Q15 data type.
+   * @param[in]      fftLen           length of the FFT.
+   * @param[in]      *pCoef16         points to twiddle coefficient buffer.
+   * @param[in]      twidCoefModifier twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table.
+   * @return none.
+   */
+
+  void arm_radix4_butterfly_inverse_q15(
+					q15_t *pSrc16,
+					uint32_t fftLen,
+					q15_t *pCoef16,
+					uint32_t twidCoefModifier);
+
+  /**
+   * @brief  In-place bit reversal function.
+   * @param[in, out] *pSrc        points to the in-place buffer of Q15 data type.
+   * @param[in]      fftLen       length of the FFT.
+   * @param[in]      bitRevFactor bit reversal modifier that supports different size FFTs with the same bit reversal table
+   * @param[in]      *pBitRevTab  points to bit reversal table.
+   * @return none.
+   */
+
+  void arm_bitreversal_q15(
+			   q15_t * pSrc,
+			   uint32_t fftLen,
+			   uint16_t bitRevFactor,
+			   uint16_t *pBitRevTab);
+
+  /**
+   * @brief Instance structure for the Q15 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                      /**< length of the real FFT. */
+    uint32_t fftLenBy2;                       /**< length of the complex FFT. */
+    uint8_t  ifftFlagR;                       /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+	uint8_t  bitReverseFlagR;                 /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;               /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */  
+    q15_t    *pTwiddleAReal;                  /**< points to the real twiddle factor table. */
+    q15_t    *pTwiddleBReal;                  /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q15 *pCfft;	  /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t fftLenReal;                        /**< length of the real FFT. */
+    uint32_t fftLenBy2;                         /**< length of the complex FFT. */
+    uint8_t  ifftFlagR;                         /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+	uint8_t  bitReverseFlagR;                   /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+    uint32_t twidCoefRModifier;                 /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    q31_t    *pTwiddleAReal;                    /**< points to the real twiddle factor table. */
+    q31_t    *pTwiddleBReal;                    /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_q31 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point RFFT/RIFFT function.
+   */
+
+  typedef struct
+  {
+    uint32_t  fftLenReal;                       /**< length of the real FFT. */
+    uint16_t  fftLenBy2;                        /**< length of the complex FFT. */
+    uint8_t   ifftFlagR;                        /**< flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform. */
+    uint8_t   bitReverseFlagR;                  /**< flag that enables (bitReverseFlagR=1) or disables (bitReverseFlagR=0) bit reversal of output. */
+	uint32_t  twidCoefRModifier;                /**< twiddle coefficient modifier that supports different size FFTs with the same twiddle factor table. */
+    float32_t *pTwiddleAReal;                   /**< points to the real twiddle factor table. */
+    float32_t *pTwiddleBReal;                   /**< points to the imag twiddle factor table. */
+    arm_cfft_radix4_instance_f32 *pCfft;        /**< points to the complex FFT instance. */
+  } arm_rfft_instance_f32;
+
+  /**
+   * @brief Processing function for the Q15 RFFT/RIFFT.
+   * @param[in]  *S    points to an instance of the Q15 RFFT/RIFFT structure.
+   * @param[in]  *pSrc points to the input buffer.
+   * @param[out] *pDst points to the output buffer.
+   * @return none.
+   */
+
+  void arm_rfft_q15(
+		    const arm_rfft_instance_q15 * S,
+		    q15_t * pSrc,
+		    q15_t * pDst);
+
+  /**
+   * @brief  Initialization function for the Q15 RFFT/RIFFT.
+   * @param[in, out] *S             points to an instance of the Q15 RFFT/RIFFT structure.
+   * @param[in]      *S_CFFT        points to an instance of the Q15 CFFT/CIFFT structure.
+   * @param[in]      fftLenReal     length of the FFT.
+   * @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+   * @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+   */
+
+  arm_status arm_rfft_init_q15(
+			       arm_rfft_instance_q15 * S,
+			       arm_cfft_radix4_instance_q15 * S_CFFT,
+			       uint32_t fftLenReal,
+			       uint32_t ifftFlagR,
+			       uint32_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the Q31 RFFT/RIFFT.
+   * @param[in]  *S    points to an instance of the Q31 RFFT/RIFFT structure.
+   * @param[in]  *pSrc points to the input buffer.
+   * @param[out] *pDst points to the output buffer.
+   * @return none.
+   */
+
+  void arm_rfft_q31(
+		    const arm_rfft_instance_q31 * S,
+		    q31_t * pSrc,
+		    q31_t * pDst);
+
+  /**
+   * @brief  Initialization function for the Q31 RFFT/RIFFT.
+   * @param[in, out] *S             points to an instance of the Q31 RFFT/RIFFT structure.
+   * @param[in, out] *S_CFFT        points to an instance of the Q31 CFFT/CIFFT structure.
+   * @param[in]      fftLenReal     length of the FFT.
+   * @param[in]      ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+   * @param[in]      bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+   */
+
+  arm_status arm_rfft_init_q31(
+			       arm_rfft_instance_q31 * S,
+			       arm_cfft_radix4_instance_q31 * S_CFFT,
+			       uint32_t fftLenReal,
+			       uint32_t ifftFlagR,
+			       uint32_t bitReverseFlag);
+
+  /**
+   * @brief  Initialization function for the floating-point RFFT/RIFFT.
+   * @param[in,out] *S             points to an instance of the floating-point RFFT/RIFFT structure.
+   * @param[in,out] *S_CFFT        points to an instance of the floating-point CFFT/CIFFT structure.
+   * @param[in]     fftLenReal     length of the FFT.
+   * @param[in]     ifftFlagR      flag that selects forward (ifftFlagR=0) or inverse (ifftFlagR=1) transform.
+   * @param[in]     bitReverseFlag flag that enables (bitReverseFlag=1) or disables (bitReverseFlag=0) bit reversal of output.
+   * @return		The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported value.
+   */
+
+  arm_status arm_rfft_init_f32(
+			       arm_rfft_instance_f32 * S,
+			       arm_cfft_radix4_instance_f32 * S_CFFT,
+			       uint32_t fftLenReal,
+			       uint32_t ifftFlagR,
+			       uint32_t bitReverseFlag);
+
+  /**
+   * @brief Processing function for the floating-point RFFT/RIFFT.
+   * @param[in]  *S    points to an instance of the floating-point RFFT/RIFFT structure.
+   * @param[in]  *pSrc points to the input buffer.
+   * @param[out] *pDst points to the output buffer.
+   * @return none.
+   */
+
+  void arm_rfft_f32(
+		    const arm_rfft_instance_f32 * S,
+		    float32_t * pSrc,
+		    float32_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    float32_t normalize;                /**< normalizing factor. */
+    float32_t *pTwiddle;                /**< points to the twiddle factor table. */
+    float32_t *pCosFactor;              /**< points to the cosFactor table. */
+    arm_rfft_instance_f32 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_f32 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_f32;
+
+  /**
+   * @brief  Initialization function for the floating-point DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of floating-point DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of floating-point RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of floating-point CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if fftLenReal is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_f32(
+			       arm_dct4_instance_f32 * S,
+			       arm_rfft_instance_f32 * S_RFFT,
+			       arm_cfft_radix4_instance_f32 * S_CFFT,
+			       uint16_t N,
+			       uint16_t Nby2,
+			       float32_t normalize);
+
+  /**
+   * @brief Processing function for the floating-point DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the floating-point DCT4/IDCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_f32(
+		    const arm_dct4_instance_f32 * S,
+		    float32_t * pState,
+		    float32_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q31 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q31_t normalize;                    /**< normalizing factor. */
+    q31_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q31_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q31 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q31 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q31;
+
+  /**
+   * @brief  Initialization function for the Q31 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q31 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q31 RFFT/RIFFT structure
+   * @param[in]     *S_CFFT    points to an instance of Q31 CFFT/CIFFT structure
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q31(
+			       arm_dct4_instance_q31 * S,
+			       arm_rfft_instance_q31 * S_RFFT,
+			       arm_cfft_radix4_instance_q31 * S_CFFT,
+			       uint16_t N,
+			       uint16_t Nby2,
+			       q31_t normalize);
+
+  /**
+   * @brief Processing function for the Q31 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q31 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q31(
+		    const arm_dct4_instance_q31 * S,
+		    q31_t * pState,
+		    q31_t * pInlineBuffer);
+
+  /**
+   * @brief Instance structure for the Q15 DCT4/IDCT4 function.
+   */
+
+  typedef struct
+  {
+    uint16_t N;                         /**< length of the DCT4. */
+    uint16_t Nby2;                      /**< half of the length of the DCT4. */
+    q15_t normalize;                    /**< normalizing factor. */
+    q15_t *pTwiddle;                    /**< points to the twiddle factor table. */
+    q15_t *pCosFactor;                  /**< points to the cosFactor table. */
+    arm_rfft_instance_q15 *pRfft;        /**< points to the real FFT instance. */
+    arm_cfft_radix4_instance_q15 *pCfft; /**< points to the complex FFT instance. */
+  } arm_dct4_instance_q15;
+
+  /**
+   * @brief  Initialization function for the Q15 DCT4/IDCT4.
+   * @param[in,out] *S         points to an instance of Q15 DCT4/IDCT4 structure.
+   * @param[in]     *S_RFFT    points to an instance of Q15 RFFT/RIFFT structure.
+   * @param[in]     *S_CFFT    points to an instance of Q15 CFFT/CIFFT structure.
+   * @param[in]     N          length of the DCT4.
+   * @param[in]     Nby2       half of the length of the DCT4.
+   * @param[in]     normalize  normalizing factor.
+   * @return		arm_status function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_ARGUMENT_ERROR if N is not a supported transform length.
+   */
+
+  arm_status arm_dct4_init_q15(
+			       arm_dct4_instance_q15 * S,
+			       arm_rfft_instance_q15 * S_RFFT,
+			       arm_cfft_radix4_instance_q15 * S_CFFT,
+			       uint16_t N,
+			       uint16_t Nby2,
+			       q15_t normalize);
+
+  /**
+   * @brief Processing function for the Q15 DCT4/IDCT4.
+   * @param[in]       *S             points to an instance of the Q15 DCT4 structure.
+   * @param[in]       *pState        points to state buffer.
+   * @param[in,out]   *pInlineBuffer points to the in-place input and output buffer.
+   * @return none.
+   */
+
+  void arm_dct4_q15(
+		    const arm_dct4_instance_q15 * S,
+		    q15_t * pState,
+		    q15_t * pInlineBuffer);
+
+  /**
+   * @brief Floating-point vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_f32(
+		   float32_t * pSrcA,
+		   float32_t * pSrcB,
+		   float32_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q7(
+		  q7_t * pSrcA,
+		  q7_t * pSrcB,
+		  q7_t * pDst,
+		  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q15(
+		    q15_t * pSrcA,
+		    q15_t * pSrcB,
+		   q15_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector addition.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_add_q31(
+		    q31_t * pSrcA,
+		    q31_t * pSrcB,
+		   q31_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_f32(
+		    float32_t * pSrcA,
+		    float32_t * pSrcB,
+		   float32_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q7(
+		   q7_t * pSrcA,
+		   q7_t * pSrcB,
+		  q7_t * pDst,
+		  uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q15(
+		    q15_t * pSrcA,
+		    q15_t * pSrcB,
+		   q15_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector subtraction.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_sub_q31(
+		    q31_t * pSrcA,
+		    q31_t * pSrcB,
+		   q31_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a floating-point vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scale scale factor to be applied
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_f32(
+		      float32_t * pSrc,
+		     float32_t scale,
+		     float32_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q7 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q7(
+		     q7_t * pSrc,
+		    q7_t scaleFract,
+		    int8_t shift,
+		    q7_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q15 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q15(
+		      q15_t * pSrc,
+		     q15_t scaleFract,
+		     int8_t shift,
+		     q15_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief Multiplies a Q31 vector by a scalar.
+   * @param[in]       *pSrc points to the input vector
+   * @param[in]       scaleFract fractional portion of the scale value
+   * @param[in]       shift number of bits to shift the result by
+   * @param[out]      *pDst points to the output vector
+   * @param[in]       blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_scale_q31(
+		      q31_t * pSrc,
+		     q31_t scaleFract,
+		     int8_t shift,
+		     q31_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief Q7 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q7(
+		   q7_t * pSrc,
+		  q7_t * pDst,
+		  uint32_t blockSize);
+
+  /**
+   * @brief Floating-point vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_f32(
+		    float32_t * pSrc,
+		   float32_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q15 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q15(
+		    q15_t * pSrc,
+		   q15_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Q31 vector absolute value.
+   * @param[in]       *pSrc points to the input buffer
+   * @param[out]      *pDst points to the output buffer
+   * @param[in]       blockSize number of samples in each vector
+   * @return none.
+   */
+
+  void arm_abs_q31(
+		    q31_t * pSrc,
+		   q31_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Dot product of floating-point vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_f32(
+			 float32_t * pSrcA,
+			 float32_t * pSrcB,
+			uint32_t blockSize,
+			float32_t * result);
+
+  /**
+   * @brief Dot product of Q7 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q7(
+		        q7_t * pSrcA,
+		        q7_t * pSrcB,
+		       uint32_t blockSize,
+		       q31_t * result);
+
+  /**
+   * @brief Dot product of Q15 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q15(
+			 q15_t * pSrcA,
+			 q15_t * pSrcB,
+			uint32_t blockSize,
+			q63_t * result);
+
+  /**
+   * @brief Dot product of Q31 vectors.
+   * @param[in]       *pSrcA points to the first input vector
+   * @param[in]       *pSrcB points to the second input vector
+   * @param[in]       blockSize number of samples in each vector
+   * @param[out]      *result output result returned here
+   * @return none.
+   */
+
+  void arm_dot_prod_q31(
+			 q31_t * pSrcA,
+			 q31_t * pSrcB,
+			uint32_t blockSize,
+			q63_t * result);
+
+  /**
+   * @brief  Shifts the elements of a Q7 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q7(
+		     q7_t * pSrc,
+		    int8_t shiftBits,
+		    q7_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q15 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q15(
+		      q15_t * pSrc,
+		     int8_t shiftBits,
+		     q15_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief  Shifts the elements of a Q31 vector a specified number of bits.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  shiftBits number of bits to shift.  A positive value shifts left; a negative value shifts right.
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_shift_q31(
+		      q31_t * pSrc,
+		     int8_t shiftBits,
+		     q31_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_f32(
+		       float32_t * pSrc,
+		      float32_t offset,
+		      float32_t * pDst,
+		      uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q7(
+		      q7_t * pSrc,
+		     q7_t offset,
+		     q7_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q15(
+		       q15_t * pSrc,
+		      q15_t offset,
+		      q15_t * pDst,
+		      uint32_t blockSize);
+
+  /**
+   * @brief  Adds a constant offset to a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[in]  offset is the offset to be added
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_offset_q31(
+		       q31_t * pSrc,
+		      q31_t offset,
+		      q31_t * pDst,
+		      uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a floating-point vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_f32(
+		       float32_t * pSrc,
+		      float32_t * pDst,
+		      uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q7 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q7(
+		      q7_t * pSrc,
+		     q7_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q15 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q15(
+		       q15_t * pSrc,
+		      q15_t * pDst,
+		      uint32_t blockSize);
+
+  /**
+   * @brief  Negates the elements of a Q31 vector.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  blockSize number of samples in the vector
+   * @return none.
+   */
+
+  void arm_negate_q31(
+		       q31_t * pSrc,
+		      q31_t * pDst,
+		      uint32_t blockSize);
+  /**
+   * @brief  Copies the elements of a floating-point vector. 
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_f32(
+		     float32_t * pSrc,
+		    float32_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q7 vector. 
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q7(
+		    q7_t * pSrc,
+		   q7_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q15 vector. 
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q15(
+		     q15_t * pSrc,
+		    q15_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief  Copies the elements of a Q31 vector. 
+   * @param[in]  *pSrc input pointer
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_copy_q31(
+		     q31_t * pSrc,
+		    q31_t * pDst,
+		    uint32_t blockSize);
+  /**
+   * @brief  Fills a constant value into a floating-point vector. 
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_f32(
+		     float32_t value,
+		    float32_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q7 vector. 
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q7(
+		    q7_t value,
+		   q7_t * pDst,
+		   uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q15 vector. 
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q15(
+		     q15_t value,
+		    q15_t * pDst,
+		    uint32_t blockSize);
+
+  /**
+   * @brief  Fills a constant value into a Q31 vector. 
+   * @param[in]  value input value to be filled
+   * @param[out]  *pDst output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_fill_q31(
+		     q31_t value,
+		    q31_t * pDst,
+		    uint32_t blockSize);
+
+/**  
+ * @brief Convolution of floating-point sequences.  
+ * @param[in] *pSrcA points to the first input sequence.  
+ * @param[in] srcALen length of the first input sequence.  
+ * @param[in] *pSrcB points to the second input sequence.  
+ * @param[in] srcBLen length of the second input sequence.  
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.  
+ * @return none.  
+ */ 
+
+  void arm_conv_f32(
+		     float32_t * pSrcA,
+		    uint32_t srcALen,
+		     float32_t * pSrcB,
+		    uint32_t srcBLen,
+		    float32_t * pDst);
+
+/**  
+ * @brief Convolution of Q15 sequences.  
+ * @param[in] *pSrcA points to the first input sequence.  
+ * @param[in] srcALen length of the first input sequence.  
+ * @param[in] *pSrcB points to the second input sequence.  
+ * @param[in] srcBLen length of the second input sequence.  
+ * @param[out] *pDst points to the location where the output result is written.  Length srcALen+srcBLen-1.  
+ * @return none.  
+ */
+
+  void arm_conv_q15(
+		     q15_t * pSrcA,
+		    uint32_t srcALen,
+		     q15_t * pSrcB,
+		    uint32_t srcBLen,
+		    q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q31(
+		     q31_t * pSrcA,
+		    uint32_t srcALen,
+		     q31_t * pSrcB,
+		    uint32_t srcBLen,
+		    q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_fast_q31(
+			  q31_t * pSrcA,
+			 uint32_t srcALen,
+			  q31_t * pSrcB,
+			 uint32_t srcBLen,
+			 q31_t * pDst);
+
+  /**
+   * @brief Convolution of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length srcALen+srcBLen-1.
+   * @return none.
+   */
+
+  void arm_conv_q7(
+		    q7_t * pSrcA,
+		   uint32_t srcALen,
+		    q7_t * pSrcB,
+		   uint32_t srcBLen,
+		   q7_t * pDst);
+
+  /**
+   * @brief Partial convolution of floating-point sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_f32(
+				   float32_t * pSrcA,
+				  uint32_t srcALen,
+				   float32_t * pSrcB,
+				  uint32_t srcBLen,
+				  float32_t * pDst,
+				  uint32_t firstIndex,
+				  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q15(
+				   q15_t * pSrcA,
+				  uint32_t srcALen,
+				   q15_t * pSrcB,
+				  uint32_t srcBLen,
+				  q15_t * pDst,
+				  uint32_t firstIndex,
+				  uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q15(
+				        q15_t * pSrcA,
+				       uint32_t srcALen,
+				        q15_t * pSrcB,
+				       uint32_t srcBLen,
+				       q15_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q31 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q31(
+				   q31_t * pSrcA,
+				  uint32_t srcALen,
+				   q31_t * pSrcB,
+				  uint32_t srcBLen,
+				  q31_t * pDst,
+				  uint32_t firstIndex,
+				  uint32_t numPoints);
+
+
+  /**
+   * @brief Partial convolution of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_fast_q31(
+				        q31_t * pSrcA,
+				       uint32_t srcALen,
+				        q31_t * pSrcB,
+				       uint32_t srcBLen,
+				       q31_t * pDst,
+				       uint32_t firstIndex,
+				       uint32_t numPoints);
+
+  /**
+   * @brief Partial convolution of Q7 sequences.
+   * @param[in]       *pSrcA points to the first input sequence.
+   * @param[in]       srcALen length of the first input sequence.
+   * @param[in]       *pSrcB points to the second input sequence.
+   * @param[in]       srcBLen length of the second input sequence.
+   * @param[out]      *pDst points to the block of output data
+   * @param[in]       firstIndex is the first output sample to start with.
+   * @param[in]       numPoints is the number of output points to be computed.
+   * @return  Returns either ARM_MATH_SUCCESS if the function completed correctly or ARM_MATH_ARGUMENT_ERROR if the requested subset is not in the range [0 srcALen+srcBLen-2].
+   */
+
+  arm_status arm_conv_partial_q7(
+				  q7_t * pSrcA,
+				 uint32_t srcALen,
+				  q7_t * pSrcB,
+				 uint32_t srcBLen,
+				 q7_t * pDst,
+				 uint32_t firstIndex,
+				 uint32_t numPoints);
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                      /**< decimation factor. */
+    uint16_t numTaps;               /**< number of coefficients in the filter. */
+    q15_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    q15_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+  } arm_fir_decimate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                  /**< decimation factor. */
+    uint16_t numTaps;           /**< number of coefficients in the filter. */
+    q31_t *pCoeffs;              /**< points to the coefficient array. The array is of length numTaps.*/
+    q31_t *pState;               /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR decimator.
+   */
+
+  typedef struct
+  {
+    uint8_t M;                          /**< decimation factor. */
+    uint16_t numTaps;                   /**< number of coefficients in the filter. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numTaps.*/
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+
+  } arm_fir_decimate_instance_f32;
+
+
+
+  /**
+   * @brief Processing function for the floating-point FIR decimator.
+   * @param[in] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_f32(
+			    const arm_fir_decimate_instance_f32 * S,
+			     float32_t * pSrc,
+			    float32_t * pDst,
+			    uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point FIR decimator.
+   * @param[in,out] *S points to an instance of the floating-point FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * blockSize is not a multiple of M.
+   */
+
+  arm_status arm_fir_decimate_init_f32(
+				       arm_fir_decimate_instance_f32 * S,
+				       uint16_t numTaps,
+				       uint8_t M,
+				       float32_t * pCoeffs,
+				       float32_t * pState,
+				       uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q15(
+			    const arm_fir_decimate_instance_q15 * S,
+			     q15_t * pSrc,
+			    q15_t * pDst,
+			    uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q15(
+				 const arm_fir_decimate_instance_q15 * S,
+				  q15_t * pSrc,
+				 q15_t * pDst,
+				 uint32_t blockSize);
+
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q15 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * blockSize is not a multiple of M.
+   */
+
+  arm_status arm_fir_decimate_init_q15(
+				       arm_fir_decimate_instance_q15 * S,
+				       uint16_t numTaps,
+				       uint8_t M,
+				       q15_t * pCoeffs,
+				       q15_t * pState,
+				       uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_q31(
+			    const arm_fir_decimate_instance_q31 * S,
+			     q31_t * pSrc,
+			    q31_t * pDst,
+			    uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR decimator (fast variant) for Cortex-M3 and Cortex-M4.
+   * @param[in] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none
+   */
+
+  void arm_fir_decimate_fast_q31(
+				 arm_fir_decimate_instance_q31 * S,
+				  q31_t * pSrc,
+				 q31_t * pDst,
+				 uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q31 FIR decimator.
+   * @param[in,out] *S points to an instance of the Q31 FIR decimator structure.
+   * @param[in] numTaps  number of coefficients in the filter.
+   * @param[in] M  decimation factor.
+   * @param[in] *pCoeffs points to the filter coefficients.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return    The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * blockSize is not a multiple of M.
+   */
+
+  arm_status arm_fir_decimate_init_q31(
+				       arm_fir_decimate_instance_q31 * S,
+				       uint16_t numTaps,
+				       uint8_t M,
+				       q31_t * pCoeffs,
+				       q31_t * pState,
+				       uint32_t blockSize);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q15_t *pCoeffs;                 /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q15_t *pState;                  /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                      /**< upsample factor. */
+    uint16_t phaseLength;           /**< length of each polyphase filter component. */
+    q31_t *pCoeffs;                  /**< points to the coefficient array. The array is of length L*phaseLength. */
+    q31_t *pState;                   /**< points to the state variable array. The array is of length blockSize+phaseLength-1. */
+  } arm_fir_interpolate_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR interpolator.
+   */
+
+  typedef struct
+  {
+    uint8_t L;                     /**< upsample factor. */
+    uint16_t phaseLength;          /**< length of each polyphase filter component. */
+    float32_t *pCoeffs;             /**< points to the coefficient array. The array is of length L*phaseLength. */
+    float32_t *pState;              /**< points to the state variable array. The array is of length phaseLength+numTaps-1. */
+  } arm_fir_interpolate_instance_f32;
+
+
+  /**
+   * @brief Processing function for the Q15 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q15(
+			       const arm_fir_interpolate_instance_q15 * S,
+			        q15_t * pSrc,
+			       q15_t * pDst,
+			       uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length numTaps is not a multiple of the interpolation factor L.
+   */
+
+  arm_status arm_fir_interpolate_init_q15(
+					  arm_fir_interpolate_instance_q15 * S,
+					  uint8_t L,
+					  uint16_t numTaps,
+					  q15_t * pCoeffs,
+					  q15_t * pState,
+					  uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 FIR interpolator.
+   * @param[in] *S        points to an instance of the Q15 FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_q31(
+			       const arm_fir_interpolate_instance_q31 * S,
+			        q31_t * pSrc,
+			       q31_t * pDst,
+			       uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 FIR interpolator.
+   * @param[in,out] *S        points to an instance of the Q31 FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length numTaps is not a multiple of the interpolation factor L.
+   */
+
+  arm_status arm_fir_interpolate_init_q31(
+					  arm_fir_interpolate_instance_q31 * S,
+					  uint8_t L,
+					  uint16_t numTaps,
+					  q31_t * pCoeffs,
+					  q31_t * pState,
+					  uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the floating-point FIR interpolator.
+   * @param[in] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in] *pSrc     points to the block of input data.
+   * @param[out] *pDst    points to the block of output data.
+   * @param[in] blockSize number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_interpolate_f32(
+			       const arm_fir_interpolate_instance_f32 * S,
+			        float32_t * pSrc,
+			       float32_t * pDst,
+			       uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point FIR interpolator.
+   * @param[in,out] *S        points to an instance of the floating-point FIR interpolator structure.
+   * @param[in]     L         upsample factor.
+   * @param[in]     numTaps   number of filter coefficients in the filter.
+   * @param[in]     *pCoeffs  points to the filter coefficient buffer.
+   * @param[in]     *pState   points to the state buffer.
+   * @param[in]     blockSize number of input samples to process per call.
+   * @return        The function returns ARM_MATH_SUCCESS if initialization is successful or ARM_MATH_LENGTH_ERROR if
+   * the filter length numTaps is not a multiple of the interpolation factor L.
+   */
+
+  arm_status arm_fir_interpolate_init_f32(
+					  arm_fir_interpolate_instance_f32 * S,
+					  uint8_t L,
+					  uint16_t numTaps,
+					  float32_t * pCoeffs,
+					  float32_t * pState,
+					  uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the high precision Q31 Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    q63_t *pState;           /**< points to the array of state coefficients.  The array is of length 4*numStages. */
+    q31_t *pCoeffs;          /**< points to the array of coefficients.  The array is of length 5*numStages. */
+    uint8_t postShift;       /**< additional shift, in bits, applied to each output sample. */
+
+  } arm_biquad_cas_df1_32x64_ins_q31;
+
+
+  /**
+   * @param[in]  *S        points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cas_df1_32x64_q31(
+				    const arm_biquad_cas_df1_32x64_ins_q31 * S,
+				     q31_t * pSrc,
+				    q31_t * pDst,
+				    uint32_t blockSize);
+
+
+  /**
+   * @param[in,out] *S           points to an instance of the high precision Q31 Biquad cascade filter structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @param[in]     postShift    shift to be applied to the output. Varies according to the coefficients format
+   * @return        none
+   */
+
+  void arm_biquad_cas_df1_32x64_init_q31(
+					 arm_biquad_cas_df1_32x64_ins_q31 * S,
+					 uint8_t numStages,
+					 q31_t * pCoeffs,
+					 q63_t * pState,
+					 uint8_t postShift);
+
+
+
+  /**
+   * @brief Instance structure for the floating-point transposed direct form II Biquad cascade filter.
+   */
+
+  typedef struct
+  {
+    uint8_t   numStages;       /**< number of 2nd order stages in the filter.  Overall order is 2*numStages. */
+    float32_t *pState;         /**< points to the array of state coefficients.  The array is of length 2*numStages. */
+    float32_t *pCoeffs;        /**< points to the array of coefficients.  The array is of length 5*numStages. */
+  } arm_biquad_cascade_df2T_instance_f32;
+
+
+  /**
+   * @brief Processing function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in]  *S        points to an instance of the filter data structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_biquad_cascade_df2T_f32(
+				   const arm_biquad_cascade_df2T_instance_f32 * S,
+				    float32_t * pSrc,
+				   float32_t * pDst,
+				   uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the floating-point transposed direct form II Biquad cascade filter.
+   * @param[in,out] *S           points to an instance of the filter data structure.
+   * @param[in]     numStages    number of 2nd order stages in the filter.
+   * @param[in]     *pCoeffs     points to the filter coefficients.
+   * @param[in]     *pState      points to the state buffer.
+   * @return        none
+   */
+
+  void arm_biquad_cascade_df2T_init_f32(
+					arm_biquad_cascade_df2T_instance_f32 * S,
+					uint8_t numStages,
+					float32_t * pCoeffs,
+					float32_t * pState);
+
+
+
+  /**
+   * @brief Instance structure for the Q15 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q15_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q15_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                          /**< number of filter stages. */
+    q31_t *pState;                               /**< points to the state variable array. The array is of length numStages. */
+    q31_t *pCoeffs;                              /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point FIR lattice filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numStages;                  /**< number of filter stages. */
+    float32_t *pState;                   /**< points to the state variable array. The array is of length numStages. */
+    float32_t *pCoeffs;                  /**< points to the coefficient array. The array is of length numStages. */
+  } arm_fir_lattice_instance_f32;
+
+  /**
+   * @brief Initialization function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages. 
+   * @param[in] *pState points to the state buffer.  The array is of length numStages. 
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q15(
+				arm_fir_lattice_instance_q15 * S,
+				uint16_t numStages,
+				q15_t * pCoeffs,
+				q15_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q15 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 FIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+  void arm_fir_lattice_q15(
+			   const arm_fir_lattice_instance_q15 * S,
+			    q15_t * pSrc,
+			   q15_t * pDst,
+			   uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the Q31 FIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 FIR lattice structure.
+   * @param[in] numStages  number of filter stages.
+   * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+   * @param[in] *pState points to the state buffer.   The array is of length numStages.
+   * @return none.
+   */
+
+  void arm_fir_lattice_init_q31(
+				arm_fir_lattice_instance_q31 * S,
+				uint16_t numStages,
+				q31_t * pCoeffs,
+				q31_t * pState);
+
+
+  /**
+   * @brief Processing function for the Q31 FIR lattice filter.
+   * @param[in]  *S        points to an instance of the Q31 FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_q31(
+			   const arm_fir_lattice_instance_q31 * S,
+			    q31_t * pSrc,
+			   q31_t * pDst,
+			   uint32_t blockSize);
+
+/**
+ * @brief Initialization function for the floating-point FIR lattice filter.
+ * @param[in] *S points to an instance of the floating-point FIR lattice structure.
+ * @param[in] numStages  number of filter stages.
+ * @param[in] *pCoeffs points to the coefficient buffer.  The array is of length numStages.
+ * @param[in] *pState points to the state buffer.  The array is of length numStages.
+ * @return none.
+ */
+
+  void arm_fir_lattice_init_f32(
+				arm_fir_lattice_instance_f32 * S,
+				uint16_t numStages,
+				float32_t * pCoeffs,
+				float32_t * pState);
+
+  /**
+   * @brief Processing function for the floating-point FIR lattice filter.
+   * @param[in]  *S        points to an instance of the floating-point FIR lattice structure.
+   * @param[in]  *pSrc     points to the block of input data.
+   * @param[out] *pDst     points to the block of output data
+   * @param[in]  blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_fir_lattice_f32(
+			   const arm_fir_lattice_instance_f32 * S,
+			    float32_t * pSrc,
+			   float32_t * pDst,
+			   uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q15_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q15_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q15_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q31 IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    q31_t *pState;                              /**< points to the state variable array. The array is of length numStages+blockSize. */
+    q31_t *pkCoeffs;                            /**< points to the reflection coefficient array. The array is of length numStages. */
+    q31_t *pvCoeffs;                            /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_q31;
+
+  /**
+   * @brief Instance structure for the floating-point IIR lattice filter.
+   */
+  typedef struct
+  {
+    uint16_t numStages;                         /**< number of stages in the filter. */
+    float32_t *pState;                          /**< points to the state variable array. The array is of length numStages+blockSize. */
+    float32_t *pkCoeffs;                        /**< points to the reflection coefficient array. The array is of length numStages. */
+    float32_t *pvCoeffs;                        /**< points to the ladder coefficient array. The array is of length numStages+1. */
+  } arm_iir_lattice_instance_f32;
+
+  /**
+   * @brief Processing function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_f32(
+			   const arm_iir_lattice_instance_f32 * S,
+			    float32_t * pSrc,
+			   float32_t * pDst,
+			   uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for the floating-point IIR lattice filter.
+   * @param[in] *S points to an instance of the floating-point IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize-1.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_f32(
+				arm_iir_lattice_instance_f32 * S,
+				uint16_t numStages,
+				float32_t *pkCoeffs,
+				float32_t *pvCoeffs,
+				float32_t *pState,
+				uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q31(
+			   const arm_iir_lattice_instance_q31 * S,
+			    q31_t * pSrc,
+			   q31_t * pDst,
+			   uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for the Q31 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q31 IIR lattice structure.
+   * @param[in] numStages number of stages in the filter.
+   * @param[in] *pkCoeffs points to the reflection coefficient buffer.  The array is of length numStages.
+   * @param[in] *pvCoeffs points to the ladder coefficient buffer.  The array is of length numStages+1.
+   * @param[in] *pState points to the state buffer.  The array is of length numStages+blockSize.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_init_q31(
+				arm_iir_lattice_instance_q31 * S,
+				uint16_t numStages,
+				q31_t *pkCoeffs,
+				q31_t *pvCoeffs,
+				q31_t *pState,
+				uint32_t blockSize);
+
+
+  /**
+   * @brief Processing function for the Q15 IIR lattice filter.
+   * @param[in] *S points to an instance of the Q15 IIR lattice structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[out] *pDst points to the block of output data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_iir_lattice_q15(
+			   const arm_iir_lattice_instance_q15 * S,
+			    q15_t * pSrc,
+			   q15_t * pDst,
+			   uint32_t blockSize);
+
+
+/**
+ * @brief Initialization function for the Q15 IIR lattice filter.
+ * @param[in] *S points to an instance of the fixed-point Q15 IIR lattice structure.
+ * @param[in] numStages  number of stages in the filter.
+ * @param[in] *pkCoeffs points to reflection coefficient buffer.  The array is of length numStages.
+ * @param[in] *pvCoeffs points to ladder coefficient buffer.  The array is of length numStages+1.
+ * @param[in] *pState points to state buffer.  The array is of length numStages+blockSize.
+ * @param[in] blockSize number of samples to process per call.
+ * @return none.
+ */
+
+  void arm_iir_lattice_init_q15(
+				arm_iir_lattice_instance_q15 * S,
+				uint16_t numStages,
+				q15_t *pkCoeffs,
+				q15_t *pvCoeffs,
+				q15_t *pState,
+				uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the floating-point LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;   /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;  /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that controls filter coefficient updates. */
+  } arm_lms_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point LMS filter.
+   * @param[in]  *S points to an instance of the floating-point LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_f32(
+		   const arm_lms_instance_f32 * S,
+		    float32_t * pSrc,
+		    float32_t * pRef,
+		   float32_t * pOut,
+		   float32_t * pErr,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_init_f32(
+			arm_lms_instance_f32 * S,
+			uint16_t numTaps,
+			float32_t * pCoeffs,
+			float32_t * pState,
+			float32_t mu,
+			uint32_t blockSize);
+
+  /**
+   * @brief Instance structure for the Q15 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q15_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+  } arm_lms_instance_q15;
+
+
+  /**
+   * @brief Initialization function for the Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to the coefficient buffer.
+   * @param[in] *pState points to the state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return    none.
+   */
+
+  void arm_lms_init_q15(
+			arm_lms_instance_q15 * S,
+			uint16_t numTaps,
+			q15_t * pCoeffs,
+			q15_t * pState,
+			q15_t mu,
+			uint32_t blockSize,
+			uint32_t postShift);
+
+  /**
+   * @brief Processing function for Q15 LMS filter.
+   * @param[in] *S points to an instance of the Q15 LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_q15(
+		   const arm_lms_instance_q15 * S,
+		    q15_t * pSrc,
+		    q15_t * pRef,
+		   q15_t * pOut,
+		   q15_t * pErr,
+		   uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< number of coefficients in the filter. */
+    q31_t *pState;       /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;      /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;            /**< step size that controls filter coefficient updates. */
+    uint32_t postShift;  /**< bit shift applied to coefficients. */
+
+  } arm_lms_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 LMS filter.
+   * @param[in]  *S points to an instance of the Q15 LMS filter structure.
+   * @param[in]  *pSrc points to the block of input data.
+   * @param[in]  *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in]  blockSize number of samples to process.
+   * @return     none.
+   */
+
+  void arm_lms_q31(
+		   const arm_lms_instance_q31 * S,
+		    q31_t * pSrc,
+		    q31_t * pRef,
+		   q31_t * pOut,
+		   q31_t * pErr,
+		   uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 LMS filter.
+   * @param[in] *S points to an instance of the Q31 LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_init_q31(
+			arm_lms_instance_q31 * S,
+			uint16_t numTaps,
+			q31_t *pCoeffs,
+			q31_t *pState,
+			q31_t mu,
+			uint32_t blockSize,
+			uint32_t postShift);
+
+  /**
+   * @brief Instance structure for the floating-point normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t  numTaps;    /**< number of coefficients in the filter. */
+    float32_t *pState;    /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    float32_t *pCoeffs;   /**< points to the coefficient array. The array is of length numTaps. */
+    float32_t mu;        /**< step size that control filter coefficient updates. */
+    float32_t energy;    /**< saves previous frame energy. */
+    float32_t x0;        /**< saves previous input sample. */
+  } arm_lms_norm_instance_f32;
+
+  /**
+   * @brief Processing function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_f32(
+			arm_lms_norm_instance_f32 * S,
+			 float32_t * pSrc,
+			 float32_t * pRef,
+			float32_t * pOut,
+			float32_t * pErr,
+			uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for floating-point normalized LMS filter.
+   * @param[in] *S points to an instance of the floating-point LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_f32(
+			     arm_lms_norm_instance_f32 * S,
+			     uint16_t numTaps,
+			     float32_t * pCoeffs,
+			     float32_t * pState,
+			     float32_t mu,
+			     uint32_t blockSize);
+
+
+  /**
+   * @brief Instance structure for the Q31 normalized LMS filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;     /**< number of coefficients in the filter. */
+    q31_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q31_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q31_t mu;             /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;    /**< bit shift applied to coefficients. */
+    q31_t *recipTable;    /**< points to the reciprocal initial value table. */
+    q31_t energy;         /**< saves previous frame energy. */
+    q31_t x0;             /**< saves previous input sample. */
+  } arm_lms_norm_instance_q31;
+
+  /**
+   * @brief Processing function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q31(
+			arm_lms_norm_instance_q31 * S,
+			 q31_t * pSrc,
+			 q31_t * pRef,
+			q31_t * pOut,
+			q31_t * pErr,
+			uint32_t blockSize);
+
+  /**
+   * @brief Initialization function for Q31 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q31 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q31(
+			     arm_lms_norm_instance_q31 * S,
+			     uint16_t numTaps,
+			     q31_t * pCoeffs,
+			     q31_t * pState,
+			     q31_t mu,
+			     uint32_t blockSize,
+			     uint8_t postShift);
+
+  /**
+   * @brief Instance structure for the Q15 normalized LMS filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;    /**< Number of coefficients in the filter. */
+    q15_t *pState;        /**< points to the state variable array. The array is of length numTaps+blockSize-1. */
+    q15_t *pCoeffs;       /**< points to the coefficient array. The array is of length numTaps. */
+    q15_t mu;            /**< step size that controls filter coefficient updates. */
+    uint8_t postShift;   /**< bit shift applied to coefficients. */
+    q15_t *recipTable;   /**< Points to the reciprocal initial value table. */
+    q15_t energy;        /**< saves previous frame energy. */
+    q15_t x0;            /**< saves previous input sample. */
+  } arm_lms_norm_instance_q15;
+
+  /**
+   * @brief Processing function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] *pSrc points to the block of input data.
+   * @param[in] *pRef points to the block of reference data.
+   * @param[out] *pOut points to the block of output data.
+   * @param[out] *pErr points to the block of error data.
+   * @param[in] blockSize number of samples to process.
+   * @return none.
+   */
+
+  void arm_lms_norm_q15(
+			arm_lms_norm_instance_q15 * S,
+			 q15_t * pSrc,
+			 q15_t * pRef,
+			q15_t * pOut,
+			q15_t * pErr,
+			uint32_t blockSize);
+
+
+  /**
+   * @brief Initialization function for Q15 normalized LMS filter.
+   * @param[in] *S points to an instance of the Q15 normalized LMS filter structure.
+   * @param[in] numTaps  number of filter coefficients.
+   * @param[in] *pCoeffs points to coefficient buffer.
+   * @param[in] *pState points to state buffer.
+   * @param[in] mu step size that controls filter coefficient updates.
+   * @param[in] blockSize number of samples to process.
+   * @param[in] postShift bit shift applied to coefficients.
+   * @return none.
+   */
+
+  void arm_lms_norm_init_q15(
+			     arm_lms_norm_instance_q15 * S,
+			     uint16_t numTaps,
+			     q15_t * pCoeffs,
+			     q15_t * pState,
+			     q15_t mu,
+			     uint32_t blockSize,
+			     uint8_t postShift);
+
+  /**
+   * @brief Correlation of floating-point sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_f32(
+			  float32_t * pSrcA,
+			 uint32_t srcALen,
+			  float32_t * pSrcB,
+			 uint32_t srcBLen,
+			 float32_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q15(
+			  q15_t * pSrcA,
+			 uint32_t srcALen,
+			  q15_t * pSrcB,
+			 uint32_t srcBLen,
+			 q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q15 sequences (fast version) for Cortex-M3 and Cortex-M4.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q15(
+			       q15_t * pSrcA,
+			      uint32_t srcALen,
+			       q15_t * pSrcB,
+			      uint32_t srcBLen,
+			      q15_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q31(
+			  q31_t * pSrcA,
+			 uint32_t srcALen,
+			  q31_t * pSrcB,
+			 uint32_t srcBLen,
+			 q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q31 sequences (fast version) for Cortex-M3 and Cortex-M4
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_fast_q31(
+			       q31_t * pSrcA,
+			      uint32_t srcALen,
+			       q31_t * pSrcB,
+			      uint32_t srcBLen,
+			      q31_t * pDst);
+
+  /**
+   * @brief Correlation of Q7 sequences.
+   * @param[in] *pSrcA points to the first input sequence.
+   * @param[in] srcALen length of the first input sequence.
+   * @param[in] *pSrcB points to the second input sequence.
+   * @param[in] srcBLen length of the second input sequence.
+   * @param[out] *pDst points to the block of output data  Length 2 * max(srcALen, srcBLen) - 1.
+   * @return none.
+   */
+
+  void arm_correlate_q7(
+			 q7_t * pSrcA,
+			uint32_t srcALen,
+			 q7_t * pSrcB,
+			uint32_t srcBLen,
+			q7_t * pDst);
+
+  /**
+   * @brief Instance structure for the floating-point sparse FIR filter.
+   */
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    float32_t *pState;            /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    float32_t *pCoeffs;           /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_f32;
+
+  /**
+   * @brief Instance structure for the Q31 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q31_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q31_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q31;
+
+  /**
+   * @brief Instance structure for the Q15 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q15_t *pState;                /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q15_t *pCoeffs;               /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q15;
+
+  /**
+   * @brief Instance structure for the Q7 sparse FIR filter.
+   */
+
+  typedef struct
+  {
+    uint16_t numTaps;             /**< number of coefficients in the filter. */
+    uint16_t stateIndex;          /**< state buffer index.  Points to the oldest sample in the state buffer. */
+    q7_t *pState;                 /**< points to the state buffer array. The array is of length maxDelay+blockSize-1. */
+    q7_t *pCoeffs;                /**< points to the coefficient array. The array is of length numTaps.*/
+    uint16_t maxDelay;            /**< maximum offset specified by the pTapDelay array. */
+    int32_t *pTapDelay;           /**< points to the array of delay values.  The array is of length numTaps. */
+  } arm_fir_sparse_instance_q7;
+
+  /**
+   * @brief Processing function for the floating-point sparse FIR filter.
+   * @param[in]  *S          points to an instance of the floating-point sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_f32(
+			  arm_fir_sparse_instance_f32 * S,
+			   float32_t * pSrc,
+			  float32_t * pDst,
+			  float32_t * pScratchIn,
+			  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the floating-point sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the floating-point sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_f32(
+			       arm_fir_sparse_instance_f32 * S,
+			       uint16_t numTaps,
+			       float32_t * pCoeffs,
+			       float32_t * pState,
+			       int32_t * pTapDelay,
+			       uint16_t maxDelay,
+			       uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q31 sparse FIR filter.
+   * @param[in]  *S          points to an instance of the Q31 sparse FIR structure.
+   * @param[in]  *pSrc       points to the block of input data.
+   * @param[out] *pDst       points to the block of output data
+   * @param[in]  *pScratchIn points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize   number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q31(
+			  arm_fir_sparse_instance_q31 * S,
+			   q31_t * pSrc,
+			  q31_t * pDst,
+			  q31_t * pScratchIn,
+			  uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q31 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q31 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q31(
+			       arm_fir_sparse_instance_q31 * S,
+			       uint16_t numTaps,
+			       q31_t * pCoeffs,
+			       q31_t * pState,
+			       int32_t * pTapDelay,
+			       uint16_t maxDelay,
+			       uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q15 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q15 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q15(
+			  arm_fir_sparse_instance_q15 * S,
+			   q15_t * pSrc,
+			  q15_t * pDst,
+			  q15_t * pScratchIn,
+			  q31_t * pScratchOut,
+			  uint32_t blockSize);
+
+
+  /**
+   * @brief  Initialization function for the Q15 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q15 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q15(
+			       arm_fir_sparse_instance_q15 * S,
+			       uint16_t numTaps,
+			       q15_t * pCoeffs,
+			       q15_t * pState,
+			       int32_t * pTapDelay,
+			       uint16_t maxDelay,
+			       uint32_t blockSize);
+
+  /**
+   * @brief Processing function for the Q7 sparse FIR filter.
+   * @param[in]  *S           points to an instance of the Q7 sparse FIR structure.
+   * @param[in]  *pSrc        points to the block of input data.
+   * @param[out] *pDst        points to the block of output data
+   * @param[in]  *pScratchIn  points to a temporary buffer of size blockSize.
+   * @param[in]  *pScratchOut points to a temporary buffer of size blockSize.
+   * @param[in]  blockSize    number of input samples to process per call.
+   * @return none.
+   */
+
+  void arm_fir_sparse_q7(
+			 arm_fir_sparse_instance_q7 * S,
+			  q7_t * pSrc,
+			 q7_t * pDst,
+			 q7_t * pScratchIn,
+			 q31_t * pScratchOut,
+			 uint32_t blockSize);
+
+  /**
+   * @brief  Initialization function for the Q7 sparse FIR filter.
+   * @param[in,out] *S         points to an instance of the Q7 sparse FIR structure.
+   * @param[in]     numTaps    number of nonzero coefficients in the filter.
+   * @param[in]     *pCoeffs   points to the array of filter coefficients.
+   * @param[in]     *pState    points to the state buffer.
+   * @param[in]     *pTapDelay points to the array of offset times.
+   * @param[in]     maxDelay   maximum offset time supported.
+   * @param[in]     blockSize  number of samples that will be processed per block.
+   * @return none
+   */
+
+  void arm_fir_sparse_init_q7(
+			      arm_fir_sparse_instance_q7 * S,
+			      uint16_t numTaps,
+			      q7_t * pCoeffs,
+			      q7_t * pState,
+			      int32_t *pTapDelay,
+			      uint16_t maxDelay,
+			      uint32_t blockSize);
+
+
+  /*
+   * @brief  Floating-point sin_cos function.
+   * @param[in]  theta    input value in degrees 
+   * @param[out] *pSinVal points to the processed sine output. 
+   * @param[out] *pCosVal points to the processed cos output. 
+   * @return none.
+   */
+
+  void arm_sin_cos_f32(
+		       float32_t theta,
+		       float32_t *pSinVal,
+		       float32_t *pCcosVal);
+
+  /*
+   * @brief  Q31 sin_cos function.
+   * @param[in]  theta    scaled input value in degrees 
+   * @param[out] *pSinVal points to the processed sine output. 
+   * @param[out] *pCosVal points to the processed cosine output. 
+   * @return none.
+   */
+
+  void arm_sin_cos_q31(
+		       q31_t theta,
+		       q31_t *pSinVal,
+		       q31_t *pCosVal);
+
+
+  /**
+   * @brief  Floating-point complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_f32(
+			   float32_t * pSrc,
+			  float32_t * pDst,
+			  uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q31(
+			   q31_t * pSrc,
+			  q31_t * pDst,
+			  uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex conjugate.
+   * @param[in]  *pSrc points to the input vector
+   * @param[out]  *pDst points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_conj_q15(
+			   q15_t * pSrc,
+			  q15_t * pDst,
+			  uint32_t numSamples);
+
+
+
+  /**
+   * @brief  Floating-point complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_f32(
+				  float32_t * pSrc,
+				 float32_t * pDst,
+				 uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q31(
+				  q31_t * pSrc,
+				 q31_t * pDst,
+				 uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude squared
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_squared_q15(
+				  q15_t * pSrc,
+				 q15_t * pDst,
+				 uint32_t numSamples);
+
+
+ /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup PID PID Motor Control
+   *
+   * A Proportional Integral Derivative (PID) controller is a generic feedback control 
+   * loop mechanism widely used in industrial control systems.
+   * A PID controller is the most commonly used type of feedback controller.
+   *
+   * This set of functions implements (PID) controllers
+   * for Q15, Q31, and floating-point data types.  The functions operate on a single sample
+   * of data and each call to the function returns a single processed value.
+   * S points to an instance of the PID control data structure.  in
+   * is the input sample value. The functions return the output value.
+   *
+   * \par Algorithm:
+   * 
    +   *    y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]
+   *    A0 = Kp + Ki + Kd
+   *    A1 = (-Kp ) - (2 * Kd )
+   *    A2 = Kd  
    
+   *
+   * \par
+   * where \c Kp is proportional constant, \c Ki is Integral constant and \c Kd is Derivative constant
+   * 
+   * \par 
+   * \image html PID.gif "Proportional Integral Derivative Controller" 
+   *
+   * \par
+   * The PID controller calculates an "error" value as the difference between
+   * the measured output and the reference input.
+   * The controller attempts to minimize the error by adjusting the process control inputs.  
+   * The proportional value determines the reaction to the current error, 
+   * the integral value determines the reaction based on the sum of recent errors, 
+   * and the derivative value determines the reaction based on the rate at which the error has been changing.
+   *
+   * \par Instance Structure 
+   * The Gains A0, A1, A2 and state variables for a PID controller are stored together in an instance data structure. 
+   * A separate instance structure must be defined for each PID Controller. 
+   * There are separate instance structure declarations for each of the 3 supported data types. 
+   * 
+   * \par Reset Functions 
+   * There is also an associated reset function for each data type which clears the state array. 
+   *
+   * \par Initialization Functions 
+   * There is also an associated initialization function for each data type. 
+   * The initialization function performs the following operations: 
+   * - Initializes the Gains A0, A1, A2 from Kp,Ki, Kd gains.
+   * - Zeros out the values in the state buffer.   
+   * 
+   * \par 
+   * Instance structure cannot be placed into a const data section and it is recommended to use the initialization function. 
+   *
+   * \par Fixed-Point Behavior 
+   * Care must be taken when using the fixed-point versions of the PID Controller functions. 
+   * In particular, the overflow and saturation behavior of the accumulator used in each function must be considered. 
+   * Refer to the function specific documentation below for usage guidelines. 
+   */
+
+  /**
+   * @addtogroup PID
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point PID Control.
+   * @param[in,out] *S is an instance of the floating-point PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   */
+
+
+  static __INLINE float32_t arm_pid_f32(
+					arm_pid_instance_f32 * S,
+					float32_t in)
+  {
+    float32_t out;
+
+    /* y[n] = y[n-1] + A0 * x[n] + A1 * x[n-1] + A2 * x[n-2]  */
+    out = (S->A0 * in) +
+      (S->A1 * S->state[0]) + (S->A2 * S->state[1]) + (S->state[2]);
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q31 PID Control.
+   * @param[in,out] *S points to an instance of the Q31 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * Scaling and Overflow Behavior: 
+   * \par 
+   * The function is implemented using an internal 64-bit accumulator. 
+   * The accumulator has a 2.62 format and maintains full precision of the intermediate multiplication results but provides only a single guard bit. 
+   * Thus, if the accumulator result overflows it wraps around rather than clip. 
+   * In order to avoid overflows completely the input signal must be scaled down by 2 bits as there are four additions. 
+   * After all multiply-accumulates are performed, the 2.62 accumulator is truncated to 1.32 format and then saturated to 1.31 format. 
+   */
+
+  static __INLINE q31_t arm_pid_q31(
+				    arm_pid_instance_q31 * S,
+				    q31_t in)
+  {
+    q63_t acc;
+	q31_t out;
+
+    /* acc = A0 * x[n]  */
+    acc = (q63_t) S->A0 * in;
+
+    /* acc += A1 * x[n-1] */
+    acc += (q63_t) S->A1 * S->state[0];
+
+    /* acc += A2 * x[n-2]  */
+    acc += (q63_t) S->A2 * S->state[1];
+
+    /* convert output to 1.31 format to add y[n-1] */
+    out = (q31_t) (acc >> 31u);
+
+    /* out += y[n-1] */
+    out += S->state[2];
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+
+  /**
+   * @brief  Process function for the Q15 PID Control.
+   * @param[in,out] *S points to an instance of the Q15 PID Control structure
+   * @param[in] in input sample to process
+   * @return out processed output sample.
+   *
+   * Scaling and Overflow Behavior: 
+   * \par 
+   * The function is implemented using a 64-bit internal accumulator. 
+   * Both Gains and state variables are represented in 1.15 format and multiplications yield a 2.30 result. 
+   * The 2.30 intermediate results are accumulated in a 64-bit accumulator in 34.30 format. 
+   * There is no risk of internal overflow with this approach and the full precision of intermediate multiplications is preserved. 
+   * After all additions have been performed, the accumulator is truncated to 34.15 format by discarding low 15 bits. 
+   * Lastly, the accumulator is saturated to yield a result in 1.15 format.
+   */
+
+  static __INLINE q15_t arm_pid_q15(
+				    arm_pid_instance_q15 * S,
+				    q15_t in)
+  {
+    q63_t acc;
+    q15_t out;
+
+    /* Implementation of PID controller */
+
+	#ifdef ARM_MATH_CM0
+
+ 	/* acc = A0 * x[n]  */
+	acc = ((q31_t) S->A0 )* in ;
+
+    #else
+				
+    /* acc = A0 * x[n]  */
+    acc = (q31_t) __SMUAD(S->A0, in);
+	
+	#endif
+
+	#ifdef ARM_MATH_CM0
+						   
+	/* acc += A1 * x[n-1] + A2 * x[n-2]  */
+	acc += (q31_t) S->A1  *  S->state[0] ;
+	acc += (q31_t) S->A2  *  S->state[1] ;
+
+	#else
+
+    /* acc += A1 * x[n-1] + A2 * x[n-2]  */
+    acc = __SMLALD(S->A1, (q31_t)__SIMD32(S->state), acc);
+
+	#endif
+
+    /* acc += y[n-1] */
+    acc += (q31_t) S->state[2] << 15;
+
+    /* saturate the output */
+    out = (q15_t) (__SSAT((acc >> 15), 16));
+
+    /* Update state */
+    S->state[1] = S->state[0];
+    S->state[0] = in;
+    S->state[2] = out;
+
+    /* return to application */
+    return (out);
+
+  }
+  
+  /**
+   * @} end of PID group
+   */
+
+
+  /**
+   * @brief Floating-point matrix inverse.
+   * @param[in]  *src points to the instance of the input floating-point matrix structure.
+   * @param[out] *dst points to the instance of the output floating-point matrix structure.
+   * @return The function returns ARM_MATH_SIZE_MISMATCH, if the dimensions do not match.
+   * If the input matrix is singular (does not have an inverse), then the algorithm terminates and returns error status ARM_MATH_SINGULAR.
+   */
+
+  arm_status arm_mat_inverse_f32(
+				 const arm_matrix_instance_f32 * src,
+				 arm_matrix_instance_f32 * dst);
+
+  
+ 
+  /**
+   * @ingroup groupController
+   */
+
+
+  /**
+   * @defgroup clarke Vector Clarke Transform
+   * Forward Clarke transform converts the instantaneous stator phases into a two-coordinate time invariant vector.
+   * Generally the Clarke transform uses three-phase currents Ia, Ib and Ic to calculate currents
+   * in the two-phase orthogonal stator axis Ialpha and Ibeta.
+   * When Ialpha is superposed with Ia as shown in the figure below
+   * \image html clarke.gif Stator current space vector and its components in (a,b).
+   * and Ia + Ib + Ic = 0, in this condition Ialpha and Ibeta
+   * can be calculated using only Ia and Ib.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeFormula.gif
+   * where Ia and Ib are the instantaneous stator phases and
+   * pIalpha and pIbeta are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup clarke
+   * @{
+   */
+
+  /**
+   *
+   * @brief  Floating-point Clarke transform
+   * @param[in]       Ia       input three-phase coordinate a
+   * @param[in]       Ib       input three-phase coordinate b
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   */
+
+  static __INLINE void arm_clarke_f32(
+				      float32_t Ia,
+				      float32_t Ib,
+				      float32_t * pIalpha,
+				      float32_t * pIbeta)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Calculate pIbeta using the equation, pIbeta = (1/sqrt(3)) * Ia + (2/sqrt(3)) * Ib */
+    *pIbeta = ((float32_t) 0.57735026919 * Ia + (float32_t) 1.15470053838 * Ib);
+
+  }
+
+  /**
+   * @brief  Clarke transform for Q31 version
+   * @param[in]       Ia       input three-phase coordinate a
+   * @param[in]       Ib       input three-phase coordinate b
+   * @param[out]      *pIalpha points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta  points to output two-phase orthogonal vector axis beta
+   * @return none.
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_clarke_q31(
+				      q31_t Ia,
+				      q31_t Ib,
+				      q31_t * pIalpha,
+				      q31_t * pIbeta)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIalpha from Ia by equation pIalpha = Ia */
+    *pIalpha = Ia;
+
+    /* Intermediate product is calculated by (1/(sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) Ia * 0x24F34E8B) >> 30);
+
+    /* Intermediate product is calculated by (2/sqrt(3) * Ib) */
+    product2 = (q31_t) (((q63_t) Ib * 0x49E69D16) >> 30);
+
+    /* pIbeta is calculated by adding the intermediate products */
+    *pIbeta = __QADD(product1, product2);
+  }
+
+  /**
+   * @} end of clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q31 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out]  *pDst    output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q31(
+		     q7_t * pSrc,
+		     q31_t * pDst,
+		     uint32_t blockSize);
+
+
+ 
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_clarke Vector Inverse Clarke Transform
+   * Inverse Clarke transform converts the two-coordinate time invariant vector into instantaneous stator phases.
+   * 
+   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html clarkeInvFormula.gif
+   * where pIa and pIb are the instantaneous stator phases and
+   * Ialpha and Ibeta are the two coordinates of time invariant vector.
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Clarke transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_clarke
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Clarke transform
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate a
+   * @param[out]      *pIb    points to output three-phase coordinate b
+   * @return none.
+   */
+
+
+  static __INLINE void arm_inv_clarke_f32(
+					  float32_t Ialpha,
+					  float32_t Ibeta,
+					  float32_t * pIa,
+					  float32_t * pIb)
+  {
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Calculating pIb from Ialpha and Ibeta by equation pIb = -(1/2) * Ialpha + (sqrt(3)/2) * Ibeta */
+    *pIb = -0.5 * Ialpha + (float32_t) 0.8660254039 *Ibeta;
+
+  }
+
+  /**
+   * @brief  Inverse Clarke transform for Q31 version 
+   * @param[in]       Ialpha  input two-phase orthogonal vector axis alpha
+   * @param[in]       Ibeta   input two-phase orthogonal vector axis beta
+   * @param[out]      *pIa    points to output three-phase coordinate a
+   * @param[out]      *pIb    points to output three-phase coordinate b
+   * @return none.
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the subtraction, hence there is no risk of overflow.
+   */
+
+  static __INLINE void arm_inv_clarke_q31(
+					  q31_t Ialpha,
+					  q31_t Ibeta,
+					  q31_t * pIa,
+					  q31_t * pIb)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+
+    /* Calculating pIa from Ialpha by equation pIa = Ialpha */
+    *pIa = Ialpha;
+
+    /* Intermediate product is calculated by (1/(2*sqrt(3)) * Ia) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (0x40000000)) >> 31);
+
+    /* Intermediate product is calculated by (1/sqrt(3) * pIb) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (0x6ED9EBA1)) >> 31);
+
+    /* pIb is calculated by subtracting the products */
+    *pIb = __QSUB(product2, product1);
+
+  }
+
+  /**
+   * @} end of inv_clarke group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to Q15 vector.
+   * @param[in]  *pSrc     input pointer
+   * @param[out] *pDst     output pointer
+   * @param[in]  blockSize number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_q15(
+		      q7_t * pSrc,
+		     q15_t * pDst,
+		     uint32_t blockSize);
+
+  
+
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup park Vector Park Transform
+   *
+   * Forward Park transform converts the input two-coordinate vector to flux and torque components.
+   * The Park transform can be used to realize the transformation of the Ialpha and the Ibeta currents 
+   * from the stationary to the moving reference frame and control the spatial relationship between 
+   * the stator vector current and rotor flux vector.
+   * If we consider the d axis aligned with the rotor flux, the diagram below shows the 
+   * current vector and the relationship from the two reference frames:
+   * \image html park.gif "Stator current space vector and its component in (a,b) and in the d,q rotating reference frame"
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkFormula.gif
+   * where Ialpha and Ibeta are the stator vector components,  
+   * pId and pIq are rotor vector components and cosVal and sinVal are the 
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup park
+   * @{
+   */
+
+  /**
+   * @brief Floating-point Park transform
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output	rotor reference frame d
+   * @param[out]      *pIq   points to output	rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * The function implements the forward Park transform.
+   *
+   */
+
+  static __INLINE void arm_park_f32(
+				    float32_t Ialpha,
+				    float32_t Ibeta,
+				    float32_t * pId,
+				    float32_t * pIq,
+				    float32_t sinVal,
+				    float32_t cosVal)
+  {
+    /* Calculate pId using the equation, pId = Ialpha * cosVal + Ibeta * sinVal */
+    *pId = Ialpha * cosVal + Ibeta * sinVal;
+
+    /* Calculate pIq using the equation, pIq = - Ialpha * sinVal + Ibeta * cosVal */
+    *pIq = -Ialpha * sinVal + Ibeta * cosVal;
+
+  }
+
+  /**
+   * @brief  Park transform for Q31 version 
+   * @param[in]       Ialpha input two-phase vector coordinate alpha
+   * @param[in]       Ibeta  input two-phase vector coordinate beta
+   * @param[out]      *pId   points to output rotor reference frame d
+   * @param[out]      *pIq   points to output rotor reference frame q
+   * @param[in]       sinVal sine value of rotation angle theta
+   * @param[in]       cosVal cosine value of rotation angle theta
+   * @return none.
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition and subtraction, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_park_q31(
+				    q31_t Ialpha,
+				    q31_t Ibeta,
+				    q31_t * pId,
+				    q31_t * pIq,
+				    q31_t sinVal,
+				    q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Ialpha * cosVal) */
+    product1 = (q31_t) (((q63_t) (Ialpha) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * sinVal) */
+    product2 = (q31_t) (((q63_t) (Ibeta) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Ialpha * sinVal) */
+    product3 = (q31_t) (((q63_t) (Ialpha) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Ibeta * cosVal) */
+    product4 = (q31_t) (((q63_t) (Ibeta) * (cosVal)) >> 31);
+
+    /* Calculate pId by adding the two intermediate products 1 and 2 */
+    *pId = __QADD(product1, product2);
+
+    /* Calculate pIq by subtracting the two intermediate products 3 from 4 */
+    *pIq = __QSUB(product4, product3);
+  }
+
+  /**
+   * @} end of park group
+   */
+
+  /**
+   * @brief  Converts the elements of the Q7 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q7_to_float(
+		        q7_t * pSrc,
+		       float32_t * pDst,
+		       uint32_t blockSize);
+
+ 
+  /**
+   * @ingroup groupController
+   */
+
+  /**
+   * @defgroup inv_park Vector Inverse Park transform
+   * Inverse Park transform converts the input flux and torque components to two-coordinate vector.
+   *
+   * The function operates on a single sample of data and each call to the function returns the processed output. 
+   * The library provides separate functions for Q31 and floating-point data types.
+   * \par Algorithm
+   * \image html parkInvFormula.gif
+   * where pIalpha and pIbeta are the stator vector components,  
+   * Id and Iq are rotor vector components and cosVal and sinVal are the 
+   * cosine and sine values of theta (rotor flux position).
+   * \par Fixed-Point Behavior
+   * Care must be taken when using the Q31 version of the Park transform.
+   * In particular, the overflow and saturation behavior of the accumulator used must be considered.
+   * Refer to the function specific documentation below for usage guidelines.
+   */
+
+  /**
+   * @addtogroup inv_park
+   * @{
+   */
+
+   /**
+   * @brief  Floating-point Inverse Park transform
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   */
+
+  static __INLINE void arm_inv_park_f32(
+					float32_t Id,
+					float32_t Iq,
+					float32_t * pIalpha,
+					float32_t * pIbeta,
+					float32_t sinVal,
+					float32_t cosVal)
+  {
+    /* Calculate pIalpha using the equation, pIalpha = Id * cosVal - Iq * sinVal */
+    *pIalpha = Id * cosVal - Iq * sinVal;
+
+    /* Calculate pIbeta using the equation, pIbeta = Id * sinVal + Iq * cosVal */
+    *pIbeta = Id * sinVal + Iq * cosVal;
+
+  }
+
+
+  /**
+   * @brief  Inverse Park transform for	Q31 version 
+   * @param[in]       Id        input coordinate of rotor reference frame d
+   * @param[in]       Iq        input coordinate of rotor reference frame q
+   * @param[out]      *pIalpha  points to output two-phase orthogonal vector axis alpha
+   * @param[out]      *pIbeta   points to output two-phase orthogonal vector axis beta
+   * @param[in]       sinVal    sine value of rotation angle theta
+   * @param[in]       cosVal    cosine value of rotation angle theta
+   * @return none.
+   *
+   * Scaling and Overflow Behavior:
+   * \par
+   * The function is implemented using an internal 32-bit accumulator.
+   * The accumulator maintains 1.31 format by truncating lower 31 bits of the intermediate multiplication in 2.62 format.
+   * There is saturation on the addition, hence there is no risk of overflow.
+   */
+
+
+  static __INLINE void arm_inv_park_q31(
+					q31_t Id,
+					q31_t Iq,
+					q31_t * pIalpha,
+					q31_t * pIbeta,
+					q31_t sinVal,
+					q31_t cosVal)
+  {
+    q31_t product1, product2;                    /* Temporary variables used to store intermediate results */
+    q31_t product3, product4;                    /* Temporary variables used to store intermediate results */
+
+    /* Intermediate product is calculated by (Id * cosVal) */
+    product1 = (q31_t) (((q63_t) (Id) * (cosVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * sinVal) */
+    product2 = (q31_t) (((q63_t) (Iq) * (sinVal)) >> 31);
+
+
+    /* Intermediate product is calculated by (Id * sinVal) */
+    product3 = (q31_t) (((q63_t) (Id) * (sinVal)) >> 31);
+
+    /* Intermediate product is calculated by (Iq * cosVal) */
+    product4 = (q31_t) (((q63_t) (Iq) * (cosVal)) >> 31);
+
+    /* Calculate pIalpha by using the two intermediate products 1 and 2 */
+    *pIalpha = __QSUB(product1, product2);
+
+    /* Calculate pIbeta by using the two intermediate products 3 and 4 */
+    *pIbeta = __QADD(product4, product3);
+
+  }
+
+  /**
+   * @} end of Inverse park group
+   */
+
+   
+  /**
+   * @brief  Converts the elements of the Q31 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_float(
+			 q31_t * pSrc,
+			float32_t * pDst,
+			uint32_t blockSize);
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup LinearInterpolate Linear Interpolation
+   *
+   * Linear interpolation is a method of curve fitting using linear polynomials.
+   * Linear interpolation works by effectively drawing a straight line between two neighboring samples and returning the appropriate point along that line
+   *
+   * \par 
+   * \image html LinearInterp.gif "Linear interpolation"
+   *
+   * \par
+   * A  Linear Interpolate function calculates an output value(y), for the input(x)
+   * using linear interpolation of the input values x0, x1( nearest input values) and the output values y0 and y1(nearest output values)
+   *
+   * \par Algorithm:
+   * 
    +   *       y = y0 + (x - x0) * ((y1 - y0)/(x1-x0))
+   *       where x0, x1 are nearest values of input x
+   *             y0, y1 are nearest values to output y
+   * 
    
+   *
+   * \par
+   * This set of functions implements Linear interpolation process
+   * for Q7, Q15, Q31, and floating-point data types.  The functions operate on a single
+   * sample of data and each call to the function returns a single processed value.
+   * S points to an instance of the Linear Interpolate function data structure.
+   * x is the input sample value. The functions returns the output value.
+   * 
+   * \par
+   * if x is outside of the table boundary, Linear interpolation returns first value of the table 
+   * if x is below input range and returns last value of table if x is above range.  
+   */
+
+  /**
+   * @addtogroup LinearInterpolate
+   * @{
+   */
+
+  /**
+   * @brief  Process function for the floating-point Linear Interpolation Function.
+   * @param[in,out] *S is an instance of the floating-point Linear Interpolation structure
+   * @param[in] x input sample to process
+   * @return y processed output sample.
+   *
+   */
+
+  static __INLINE float32_t arm_linear_interp_f32(
+						  arm_linear_interp_instance_f32 * S,
+						  float32_t x)
+  {
+
+	  float32_t y;
+	  float32_t x0, x1;						/* Nearest input values */
+	  float32_t y0, y1;	  					/* Nearest output values */
+	  float32_t xSpacing = S->xSpacing;		/* spacing between input values */
+	  int32_t i;  							/* Index variable */
+	  float32_t *pYData = S->pYData;	    /* pointer to output table */
+
+	  /* Calculation of index */
+	  i =   (x - S->x1) / xSpacing;
+
+	  if(i < 0)
+	  {
+	     /* Iniatilize output for below specified range as least output value of table */
+		 y = pYData[0];
+	  }
+	  else if(i >= S->nValues)
+	  {
+	  	  /* Iniatilize output for above specified range as last output value of table */
+	  	  y = pYData[S->nValues-1];	
+	  }
+	  else
+	  {	 
+	  	  /* Calculation of nearest input values */
+		  x0 = S->x1 + i * xSpacing;
+		  x1 = S->x1 + (i +1) * xSpacing;
+		 
+		 /* Read of nearest output values */
+		  y0 = pYData[i];
+		  y1 = pYData[i + 1];
+		
+		  /* Calculation of output */
+		  y = y0 + (x - x0) * ((y1 - y0)/(x1-x0));	
+		
+	  }
+
+      /* returns output value */
+	  return (y);
+  }
+
+   /**
+   *
+   * @brief  Process function for the Q31 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q31 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   *
+   */
+
+
+  static __INLINE q31_t arm_linear_interp_q31(q31_t *pYData,
+					      q31_t x, uint32_t nValues)
+  {
+    q31_t y;                                   /* output */
+    q31_t y0, y1;                                /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                              /* Index to read nearest output values */
+    
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20);
+
+	if(index >= (nValues - 1))
+	{
+		return(pYData[nValues - 1]);
+	}
+	else if(index < 0)
+	{
+		return(pYData[0]);
+	}
+	else
+	{
+
+	    /* 20 bits for the fractional part */
+	    /* shift left by 11 to keep fract in 1.31 format */
+	    fract = (x & 0x000FFFFF) << 11;
+	
+	    /* Read two nearest output values from the index in 1.31(q31) format */
+	    y0 = pYData[index];
+	    y1 = pYData[index + 1u];
+	
+	    /* Calculation of y0 * (1-fract) and y is in 2.30 format */
+	    y = ((q31_t) ((q63_t) y0 * (0x7FFFFFFF - fract) >> 32));
+	
+	    /* Calculation of y0 * (1-fract) + y1 *fract and y is in 2.30 format */
+	    y += ((q31_t) (((q63_t) y1 * fract) >> 32));
+	
+	    /* Convert y to 1.31 format */
+	    return (y << 1u);
+
+	}
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q15 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q15 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12. 
+   *
+   */
+
+
+  static __INLINE q15_t arm_linear_interp_q15(q15_t *pYData, q31_t x, uint32_t nValues)
+  {
+    q63_t y;                                   /* output */
+    q15_t y0, y1;                              /* Nearest output values */
+    q31_t fract;                               /* fractional part */
+    int32_t index;                            /* Index to read nearest output values */ 
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u); 
+
+	if(index >= (nValues - 1))
+	{
+		return(pYData[nValues - 1]);
+	}
+	else if(index < 0)
+	{
+		return(pYData[0]);
+	}
+	else
+	{	
+	    /* 20 bits for the fractional part */
+	    /* fract is in 12.20 format */
+	    fract = (x & 0x000FFFFF);
+	
+	    /* Read two nearest output values from the index */
+	    y0 = pYData[index];
+	    y1 = pYData[index + 1u];
+	
+	    /* Calculation of y0 * (1-fract) and y is in 13.35 format */
+	    y = ((q63_t) y0 * (0xFFFFF - fract));
+	
+	    /* Calculation of (y0 * (1-fract) + y1 * fract) and y is in 13.35 format */
+	    y += ((q63_t) y1 * (fract));
+	
+	    /* convert y to 1.15 format */
+	    return (y >> 20);
+	}
+
+
+  }
+
+  /**
+   *
+   * @brief  Process function for the Q7 Linear Interpolation Function.
+   * @param[in] *pYData  pointer to Q7 Linear Interpolation table
+   * @param[in] x input sample to process
+   * @param[in] nValues number of table values
+   * @return y processed output sample.
+   *
+   * \par
+   * Input sample x is in 12.20 format which contains 12 bits for table index and 20 bits for fractional part.
+   * This function can support maximum of table size 2^12.
+   */
+
+
+  static __INLINE q7_t arm_linear_interp_q7(q7_t *pYData, q31_t x,  uint32_t nValues)
+  {
+    q31_t y;                                   /* output */
+    q7_t y0, y1;                                 /* Nearest output values */
+    q31_t fract;                                 /* fractional part */
+    int32_t index;                              /* Index to read nearest output values */
+    
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    index = ((x & 0xFFF00000) >> 20u);
+
+
+    if(index >= (nValues - 1))
+	{
+		return(pYData[nValues - 1]);
+	}
+	else if(index < 0)
+	{
+		return(pYData[0]);
+	}
+	else
+	{
+
+	    /* 20 bits for the fractional part */
+	    /* fract is in 12.20 format */
+	    fract = (x & 0x000FFFFF);
+	
+	    /* Read two nearest output values from the index and are in 1.7(q7) format */
+	    y0 = pYData[index];
+	    y1 = pYData[index + 1u];
+	
+	    /* Calculation of y0 * (1-fract ) and y is in 13.27(q27) format */
+	    y = ((y0 * (0xFFFFF - fract)));
+	
+	    /* Calculation of y1 * fract + y0 * (1-fract) and y is in 13.27(q27) format */
+	    y += (y1 * fract);
+	
+	    /* convert y to 1.7(q7) format */
+	    return (y >> 20u);
+
+	}
+
+  }
+  /**
+   * @} end of LinearInterpolate group
+   */
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  sin(x).
+   */
+
+  float32_t arm_sin_f32(
+			 float32_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q31_t arm_sin_q31(
+		     q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric sine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  sin(x).
+   */
+
+  q15_t arm_sin_q15(
+		     q15_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for floating-point data.
+   * @param[in] x input value in radians.
+   * @return  cos(x).
+   */
+
+  float32_t arm_cos_f32(
+			 float32_t x);
+
+  /**
+   * @brief Fast approximation to the trigonometric cosine function for Q31 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q31_t arm_cos_q31(
+		     q31_t x);
+
+  /**
+   * @brief  Fast approximation to the trigonometric cosine function for Q15 data.
+   * @param[in] x Scaled input value in radians.
+   * @return  cos(x).
+   */
+
+  q15_t arm_cos_q15(
+		     q15_t x);
+
+
+  /**
+   * @ingroup groupFastMath
+   */
+
+
+  /**
+   * @defgroup SQRT Square Root
+   *
+   * Computes the square root of a number.
+   * There are separate functions for Q15, Q31, and floating-point data types.  
+   * The square root function is computed using the Newton-Raphson algorithm.
+   * This is an iterative algorithm of the form:
+   * 
    +   *      x1 = x0 - f(x0)/f'(x0)
+   * 
    
+   * where x1 is the current estimate,
+   * x0 is the previous estimate and
+   * f'(x0) is the derivative of f() evaluated at x0.
+   * For the square root function, the algorithm reduces to:
+   * 
    +   *     x0 = in/2                         [initial guess]
+   *     x1 = 1/2 * ( x0 + in / x0)        [each iteration]
+   * 
    
+   */
+
+
+  /**
+   * @addtogroup SQRT
+   * @{
+   */
+
+  /**
+   * @brief  Floating-point square root function.
+   * @param[in]  in     input value.
+   * @param[out] *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * in is negative value and returns zero output for negative values.
+   */
+
+  static __INLINE arm_status  arm_sqrt_f32(
+					  float32_t in, float32_t *pOut)
+  {
+  	if(in > 0)
+	{
+
+//	#if __FPU_USED
+    #if (__FPU_USED == 1) && defined ( __CC_ARM   )
+		*pOut = __sqrtf(in);
+	#else	  
+		*pOut = sqrtf(in);
+	#endif
+
+		return (ARM_MATH_SUCCESS);
+	}
+  	else
+	{
+		*pOut = 0.0f;
+		return (ARM_MATH_ARGUMENT_ERROR);
+	}
+
+  }
+
+
+  /**
+   * @brief Q31 square root function.
+   * @param[in]   in    input value.  The range of the input value is [0 +1) or 0x00000000 to 0x7FFFFFFF.
+   * @param[out]  *pOut square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * in is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q31(
+		      q31_t in, q31_t *pOut);
+
+  /**
+   * @brief  Q15 square root function.
+   * @param[in]   in     input value.  The range of the input value is [0 +1) or 0x0000 to 0x7FFF.
+   * @param[out]  *pOut  square root of input value.
+   * @return The function returns ARM_MATH_SUCCESS if input value is positive value or ARM_MATH_ARGUMENT_ERROR if
+   * in is negative value and returns zero output for negative values.
+   */
+  arm_status arm_sqrt_q15(
+		      q15_t in, q15_t *pOut);
+
+  /**
+   * @} end of SQRT group
+   */
+
+
+
+
+
+
+  /**
+   * @brief floating-point Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_f32(
+					     int32_t * circBuffer,
+					     int32_t L,
+					     uint16_t * writeOffset,
+					     int32_t bufferInc,
+					     const int32_t * src,
+					     int32_t srcInc,
+					     uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+      {
+	/* copy the input sample to the circular buffer */
+	circBuffer[wOffset] = *src;
+
+	/* Update the input pointer */
+	src += srcInc;
+
+	/* Circularly update wOffset.  Watch out for positive and negative value */
+	wOffset += bufferInc;
+	if(wOffset >= L)
+	  wOffset -= L;
+
+	/* Decrement the loop counter */
+	i--;
+      }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief floating-point Circular Read function.
+   */
+  static __INLINE void arm_circularRead_f32(
+					    int32_t * circBuffer,
+					    int32_t L,
+					    int32_t * readOffset,
+					    int32_t bufferInc,
+					    int32_t * dst,
+					    int32_t * dst_base,
+					    int32_t dst_length,
+					    int32_t dstInc,
+					    uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+      {
+	/* copy the sample from the circular buffer to the destination buffer */
+	*dst = circBuffer[rOffset];
+
+	/* Update the input pointer */
+	dst += dstInc;
+
+	if(dst == (int32_t *) dst_end)
+	  {
+	    dst = dst_base;
+	  }
+
+	/* Circularly update rOffset.  Watch out for positive and negative value  */
+	rOffset += bufferInc;
+
+	if(rOffset >= L)
+	  {
+	    rOffset -= L;
+	  }
+
+	/* Decrement the loop counter */
+	i--;
+      }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+  /**
+   * @brief Q15 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q15(
+					     q15_t * circBuffer,
+					     int32_t L,
+					     uint16_t * writeOffset,
+					     int32_t bufferInc,
+					     const q15_t * src,
+					     int32_t srcInc,
+					     uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+      {
+	/* copy the input sample to the circular buffer */
+	circBuffer[wOffset] = *src;
+
+	/* Update the input pointer */
+	src += srcInc;
+
+	/* Circularly update wOffset.  Watch out for positive and negative value */
+	wOffset += bufferInc;
+	if(wOffset >= L)
+	  wOffset -= L;
+
+	/* Decrement the loop counter */
+	i--;
+      }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q15 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q15(
+					    q15_t * circBuffer,
+					    int32_t L,
+					    int32_t * readOffset,
+					    int32_t bufferInc,
+					    q15_t * dst,
+					    q15_t * dst_base,
+					    int32_t dst_length,
+					    int32_t dstInc,
+					    uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+      {
+	/* copy the sample from the circular buffer to the destination buffer */
+	*dst = circBuffer[rOffset];
+
+	/* Update the input pointer */
+	dst += dstInc;
+
+	if(dst == (q15_t *) dst_end)
+	  {
+	    dst = dst_base;
+	  }
+
+	/* Circularly update wOffset.  Watch out for positive and negative value */
+	rOffset += bufferInc;
+
+	if(rOffset >= L)
+	  {
+	    rOffset -= L;
+	  }
+
+	/* Decrement the loop counter */
+	i--;
+      }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief Q7 Circular write function.
+   */
+
+  static __INLINE void arm_circularWrite_q7(
+					    q7_t * circBuffer,
+					    int32_t L,
+					    uint16_t * writeOffset,
+					    int32_t bufferInc,
+					    const q7_t * src,
+					    int32_t srcInc,
+					    uint32_t blockSize)
+  {
+    uint32_t i = 0u;
+    int32_t wOffset;
+
+    /* Copy the value of Index pointer that points
+     * to the current location where the input samples to be copied */
+    wOffset = *writeOffset;
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+      {
+	/* copy the input sample to the circular buffer */
+	circBuffer[wOffset] = *src;
+
+	/* Update the input pointer */
+	src += srcInc;
+
+	/* Circularly update wOffset.  Watch out for positive and negative value */
+	wOffset += bufferInc;
+	if(wOffset >= L)
+	  wOffset -= L;
+
+	/* Decrement the loop counter */
+	i--;
+      }
+
+    /* Update the index pointer */
+    *writeOffset = wOffset;
+  }
+
+
+
+  /**
+   * @brief Q7 Circular Read function.
+   */
+  static __INLINE void arm_circularRead_q7(
+					   q7_t * circBuffer,
+					   int32_t L,
+					   int32_t * readOffset,
+					   int32_t bufferInc,
+					   q7_t * dst,
+					   q7_t * dst_base,
+					   int32_t dst_length,
+					   int32_t dstInc,
+					   uint32_t blockSize)
+  {
+    uint32_t i = 0;
+    int32_t rOffset, dst_end;
+
+    /* Copy the value of Index pointer that points
+     * to the current location from where the input samples to be read */
+    rOffset = *readOffset;
+
+    dst_end = (int32_t) (dst_base + dst_length);
+
+    /* Loop over the blockSize */
+    i = blockSize;
+
+    while(i > 0u)
+      {
+	/* copy the sample from the circular buffer to the destination buffer */
+	*dst = circBuffer[rOffset];
+
+	/* Update the input pointer */
+	dst += dstInc;
+
+	if(dst == (q7_t *) dst_end)
+	  {
+	    dst = dst_base;
+	  }
+
+	/* Circularly update rOffset.  Watch out for positive and negative value */
+	rOffset += bufferInc;
+
+	if(rOffset >= L)
+	  {
+	    rOffset -= L;
+	  }
+
+	/* Decrement the loop counter */
+	i--;
+      }
+
+    /* Update the index pointer */
+    *readOffset = rOffset;
+  }
+
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q31(
+		      q31_t * pSrc,
+		     uint32_t blockSize,
+		     q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_f32(
+		      float32_t * pSrc,
+		     uint32_t blockSize,
+		     float32_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q15(
+		      q15_t * pSrc,
+		     uint32_t blockSize,
+		     q63_t * pResult);
+
+  /**
+   * @brief  Sum of the squares of the elements of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_power_q7(
+		     q7_t * pSrc,
+		    uint32_t blockSize,
+		    q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_mean_q7(
+		    q7_t * pSrc,
+		   uint32_t blockSize,
+		   q7_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q15(
+		     q15_t * pSrc,
+		    uint32_t blockSize,
+		    q15_t * pResult);
+
+  /**
+   * @brief  Mean value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_q31(
+		     q31_t * pSrc,
+		    uint32_t blockSize,
+		    q31_t * pResult);
+
+  /**
+   * @brief  Mean value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+  void arm_mean_f32(
+		     float32_t * pSrc,
+		    uint32_t blockSize,
+		    float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_f32(
+		    float32_t * pSrc,
+		   uint32_t blockSize,
+		   float32_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q31(
+		    q31_t * pSrc,
+		   uint32_t blockSize,
+		   q63_t * pResult);
+
+  /**
+   * @brief  Variance of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_var_q15(
+		    q15_t * pSrc,
+		   uint32_t blockSize,
+		   q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_f32(
+		    float32_t * pSrc,
+		   uint32_t blockSize,
+		   float32_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q31(
+		    q31_t * pSrc,
+		   uint32_t blockSize,
+		   q31_t * pResult);
+
+  /**
+   * @brief  Root Mean Square of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_rms_q15(
+		    q15_t * pSrc,
+		   uint32_t blockSize,
+		   q15_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_f32(
+		    float32_t * pSrc,
+		   uint32_t blockSize,
+		   float32_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q31(
+		    q31_t * pSrc,
+		   uint32_t blockSize,
+		   q31_t * pResult);
+
+  /**
+   * @brief  Standard deviation of the elements of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output value.
+   * @return none.
+   */
+
+  void arm_std_q15(
+		    q15_t * pSrc,
+		   uint32_t blockSize,
+		   q15_t * pResult);
+
+  /**
+   * @brief  Floating-point complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_f32(
+			  float32_t * pSrc,
+			 float32_t * pDst,
+			 uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q31(
+			  q31_t * pSrc,
+			 q31_t * pDst,
+			 uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex magnitude
+   * @param[in]  *pSrc points to the complex input vector
+   * @param[out]  *pDst points to the real output vector
+   * @param[in]  numSamples number of complex samples in the input vector
+   * @return none.
+   */
+
+  void arm_cmplx_mag_q15(
+			  q15_t * pSrc,
+			 q15_t * pDst,
+			 uint32_t numSamples);
+
+  /**
+   * @brief  Q15 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q15(
+			       q15_t * pSrcA,
+			       q15_t * pSrcB,
+			      uint32_t numSamples,
+			      q31_t * realResult,
+			      q31_t * imagResult);
+
+  /**
+   * @brief  Q31 complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_q31(
+			       q31_t * pSrcA,
+			       q31_t * pSrcB,
+			      uint32_t numSamples,
+			      q63_t * realResult,
+			      q63_t * imagResult);
+
+  /**
+   * @brief  Floating-point complex dot product
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @param[out]  *realResult real part of the result returned here
+   * @param[out]  *imagResult imaginary part of the result returned here
+   * @return none.
+   */
+
+  void arm_cmplx_dot_prod_f32(
+			       float32_t * pSrcA,
+			       float32_t * pSrcB,
+			      uint32_t numSamples,
+			      float32_t * realResult,
+			      float32_t * imagResult);
+
+  /**
+   * @brief  Q15 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q15(
+			        q15_t * pSrcCmplx,
+			        q15_t * pSrcReal,
+			       q15_t * pCmplxDst,
+			       uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_q31(
+			        q31_t * pSrcCmplx,
+			        q31_t * pSrcReal,
+			       q31_t * pCmplxDst,
+			       uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-real multiplication
+   * @param[in]  *pSrcCmplx points to the complex input vector
+   * @param[in]  *pSrcReal points to the real input vector
+   * @param[out]  *pCmplxDst points to the complex output vector
+   * @param[in]  numSamples number of samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_real_f32(
+			        float32_t * pSrcCmplx,
+			        float32_t * pSrcReal,
+			       float32_t * pCmplxDst,
+			       uint32_t numSamples);
+
+  /**
+   * @brief  Minimum value of a Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *result is output pointer
+   * @param[in]  index is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q7(
+		   q7_t * pSrc,
+		  uint32_t blockSize,
+		  q7_t * result,
+		  uint32_t * index);
+
+  /**
+   * @brief  Minimum value of a Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[in]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_q15(
+		    q15_t * pSrc,
+		   uint32_t blockSize,
+		   q15_t * pResult,
+		   uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+  void arm_min_q31(
+		    q31_t * pSrc,
+		   uint32_t blockSize,
+		   q31_t * pResult,
+		   uint32_t * pIndex);
+
+  /**
+   * @brief  Minimum value of a floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @param[out]  *pResult is output pointer
+   * @param[out]  *pIndex is the array index of the minimum value in the input buffer.
+   * @return none.
+   */
+
+  void arm_min_f32(
+		    float32_t * pSrc,
+		   uint32_t blockSize,
+		   float32_t * pResult,
+		   uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q7 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q7(
+		   q7_t * pSrc,
+		  uint32_t blockSize,
+		  q7_t * pResult,
+		  uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q15 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q15(
+		    q15_t * pSrc,
+		   uint32_t blockSize,
+		   q15_t * pResult,
+		   uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a Q31 vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_q31(
+		    q31_t * pSrc,
+		   uint32_t blockSize,
+		   q31_t * pResult,
+		   uint32_t * pIndex);
+
+/**
+ * @brief Maximum value of a floating-point vector.
+ * @param[in]       *pSrc points to the input buffer
+ * @param[in]       blockSize length of the input vector
+ * @param[out]      *pResult maximum value returned here
+ * @param[out]      *pIndex index of maximum value returned here
+ * @return none.
+ */
+
+  void arm_max_f32(
+		    float32_t * pSrc,
+		   uint32_t blockSize,
+		   float32_t * pResult,
+		   uint32_t * pIndex);
+
+  /**
+   * @brief  Q15 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q15(
+			        q15_t * pSrcA,
+			        q15_t * pSrcB,
+			       q15_t * pDst,
+			       uint32_t numSamples);
+
+  /**
+   * @brief  Q31 complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_q31(
+			        q31_t * pSrcA,
+			        q31_t * pSrcB,
+			       q31_t * pDst,
+			       uint32_t numSamples);
+
+  /**
+   * @brief  Floating-point complex-by-complex multiplication
+   * @param[in]  *pSrcA points to the first input vector
+   * @param[in]  *pSrcB points to the second input vector
+   * @param[out]  *pDst  points to the output vector
+   * @param[in]  numSamples number of complex samples in each vector
+   * @return none.
+   */
+
+  void arm_cmplx_mult_cmplx_f32(
+			        float32_t * pSrcA,
+			        float32_t * pSrcB,
+			       float32_t * pDst,
+			       uint32_t numSamples);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q31 vector. 
+   * @param[in]       *pSrc points to the floating-point input vector 
+   * @param[out]      *pDst points to the Q31 output vector
+   * @param[in]       blockSize length of the input vector 
+   * @return none. 
+   */
+  void arm_float_to_q31(
+			       float32_t * pSrc,
+			      q31_t * pDst,
+			      uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q15 vector. 
+   * @param[in]       *pSrc points to the floating-point input vector 
+   * @param[out]      *pDst points to the Q15 output vector
+   * @param[in]       blockSize length of the input vector 
+   * @return          none
+   */
+  void arm_float_to_q15(
+			       float32_t * pSrc,
+			      q15_t * pDst,
+			      uint32_t blockSize);
+
+  /**
+   * @brief Converts the elements of the floating-point vector to Q7 vector. 
+   * @param[in]       *pSrc points to the floating-point input vector 
+   * @param[out]      *pDst points to the Q7 output vector
+   * @param[in]       blockSize length of the input vector 
+   * @return          none
+   */
+  void arm_float_to_q7(
+			      float32_t * pSrc,
+			     q7_t * pDst,
+			     uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q15 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q15(
+		       q31_t * pSrc,
+		      q15_t * pDst,
+		      uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q31 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q31_to_q7(
+		      q31_t * pSrc,
+		     q7_t * pDst,
+		     uint32_t blockSize);
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to floating-point vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_float(
+			 q15_t * pSrc,
+			float32_t * pDst,
+			uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q31 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q31(
+		       q15_t * pSrc,
+		      q31_t * pDst,
+		      uint32_t blockSize);
+
+
+  /**
+   * @brief  Converts the elements of the Q15 vector to Q7 vector.
+   * @param[in]  *pSrc is input pointer
+   * @param[out]  *pDst is output pointer
+   * @param[in]  blockSize is the number of samples to process
+   * @return none.
+   */
+  void arm_q15_to_q7(
+		      q15_t * pSrc,
+		     q7_t * pDst,
+		     uint32_t blockSize);
+
+
+  /**
+   * @ingroup groupInterpolation
+   */
+
+  /**
+   * @defgroup BilinearInterpolate Bilinear Interpolation
+   *
+   * Bilinear interpolation is an extension of linear interpolation applied to a two dimensional grid.
+   * The underlying function f(x, y) is sampled on a regular grid and the interpolation process
+   * determines values between the grid points.
+   * Bilinear interpolation is equivalent to two step linear interpolation, first in the x-dimension and then in the y-dimension.
+   * Bilinear interpolation is often used in image processing to rescale images.
+   * The CMSIS DSP library provides bilinear interpolation functions for Q7, Q15, Q31, and floating-point data types.
+   *
+   * Algorithm
+   * \par
+   * The instance structure used by the bilinear interpolation functions describes a two dimensional data table.
+   * For floating-point, the instance structure is defined as:
+   * 
    +   *   typedef struct
+   *   {
+   *     uint16_t numRows;
+   *     uint16_t numCols;
+   *     float32_t *pData;
+   * } arm_bilinear_interp_instance_f32;
+   * 
    
+   *
+   * \par
+   * where numRows specifies the number of rows in the table;
+   * numCols specifies the number of columns in the table;
+   * and pData points to an array of size numRows*numCols values.
+   * The data table pTable is organized in row order and the supplied data values fall on integer indexes.
+   * That is, table element (x,y) is located at pTable[x + y*numCols] where x and y are integers.
+   *
+   * \par
+   * Let (x, y) specify the desired interpolation point.  Then define:
+   * 
    +   *     XF = floor(x)
+   *     YF = floor(y)
+   * 
    
+   * \par
+   * The interpolated output point is computed as:
+   * 
    +   *  f(x, y) = f(XF, YF) * (1-(x-XF)) * (1-(y-YF))
+   *           + f(XF+1, YF) * (x-XF)*(1-(y-YF))
+   *           + f(XF, YF+1) * (1-(x-XF))*(y-YF)
+   *           + f(XF+1, YF+1) * (x-XF)*(y-YF)
+   * 
    
+   * Note that the coordinates (x, y) contain integer and fractional components.  
+   * The integer components specify which portion of the table to use while the
+   * fractional components control the interpolation processor.
+   *
+   * \par
+   * if (x,y) are outside of the table boundary, Bilinear interpolation returns zero output. 
+   */
+
+  /**
+   * @addtogroup BilinearInterpolate
+   * @{
+   */
+
+  /**
+  *
+  * @brief  Floating-point bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate.
+  * @param[in] Y interpolation coordinate.
+  * @return out interpolated value.
+  */
+
+  
+  static __INLINE float32_t arm_bilinear_interp_f32(
+						    const arm_bilinear_interp_instance_f32 * S,
+						    float32_t X,
+						    float32_t Y)
+  {
+    float32_t out;
+    float32_t f00, f01, f10, f11;
+    float32_t *pData = S->pData;
+    int32_t xIndex, yIndex, index;
+    float32_t xdiff, ydiff;
+    float32_t b1, b2, b3, b4;
+
+    xIndex = (int32_t) X;
+    yIndex = (int32_t) Y;
+
+	/* Care taken for table outside boundary */
+	/* Returns zero output when values are outside table boundary */
+	if(xIndex < 0 || xIndex > (S->numRows-1) || yIndex < 0  || yIndex > ( S->numCols-1))
+	{
+		return(0);
+	}
+	
+    /* Calculation of index for two nearest points in X-direction */
+    index = (xIndex - 1) + (yIndex-1) *  S->numCols ;
+
+
+    /* Read two nearest points in X-direction */
+    f00 = pData[index];
+    f01 = pData[index + 1];
+
+    /* Calculation of index for two nearest points in Y-direction */
+    index = (xIndex-1) + (yIndex) * S->numCols;
+
+
+    /* Read two nearest points in Y-direction */
+    f10 = pData[index];
+    f11 = pData[index + 1];
+
+    /* Calculation of intermediate values */
+    b1 = f00;
+    b2 = f01 - f00;
+    b3 = f10 - f00;
+    b4 = f00 - f01 - f10 + f11;
+
+    /* Calculation of fractional part in X */
+    xdiff = X - xIndex;
+
+    /* Calculation of fractional part in Y */
+    ydiff = Y - yIndex;
+
+    /* Calculation of bi-linear interpolated output */
+     out = b1 + b2 * xdiff + b3 * ydiff + b4 * xdiff * ydiff;
+
+   /* return to application */
+    return (out);
+
+  }
+
+  /**
+  *
+  * @brief  Q31 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q31_t arm_bilinear_interp_q31(
+						arm_bilinear_interp_instance_q31 * S,
+						q31_t X,
+						q31_t Y)
+  {
+    q31_t out;                                   /* Temporary output */
+    q31_t acc = 0;                               /* output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q31_t x1, x2, y1, y2;                        /* Nearest output values */
+    int32_t rI, cI;                             /* Row and column indices */
+    q31_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20u);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20u);
+
+	/* Care taken for table outside boundary */
+	/* Returns zero output when values are outside table boundary */
+	if(rI < 0 || rI > (S->numRows-1) || cI < 0  || cI > ( S->numCols-1))
+	{
+		return(0);
+	}
+
+    /* 20 bits for the fractional part */
+    /* shift left xfract by 11 to keep 1.31 format */
+    xfract = (X & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+    /* 20 bits for the fractional part */
+    /* shift left yfract by 11 to keep 1.31 format */
+    yfract = (Y & 0x000FFFFF) << 11u;
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 3.29(q29) format */
+    out = ((q31_t) (((q63_t) x1 * (0x7FFFFFFF - xfract)) >> 32));
+    acc = ((q31_t) (((q63_t) out * (0x7FFFFFFF - yfract)) >> 32));
+
+    /* x2 * (xfract) * (1-yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) x2 * (0x7FFFFFFF - yfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (xfract) >> 32));
+
+    /* y1 * (1 - xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y1 * (0x7FFFFFFF - xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* y2 * (xfract) * (yfract)  in 3.29(q29) and adding to acc */
+    out = ((q31_t) ((q63_t) y2 * (xfract) >> 32));
+    acc += ((q31_t) ((q63_t) out * (yfract) >> 32));
+
+    /* Convert acc to 1.31(q31) format */
+    return (acc << 2u);
+
+  }
+
+  /**
+  * @brief  Q15 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q15_t arm_bilinear_interp_q15(
+						arm_bilinear_interp_instance_q15 * S,
+						q31_t X,
+						q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q15_t x1, x2, y1, y2;                        /* Nearest output values */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    int32_t rI, cI;                             /* Row and column indices */
+    q15_t *pYData = S->pData;                    /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+	/* Care taken for table outside boundary */
+	/* Returns zero output when values are outside table boundary */
+	if(rI < 0 || rI > (S->numRows-1) || cI < 0  || cI > ( S->numCols-1))
+	{
+		return(0);
+	}
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 13.51 format */
+
+    /* x1 is in 1.15(q15), xfract in 12.20 format and out is in 13.35 format */
+    /* convert 13.35 to 13.31 by right shifting  and out is in 1.31 */
+    out = (q31_t) (((q63_t) x1 * (0xFFFFF - xfract)) >> 4u);
+    acc = ((q63_t) out * (0xFFFFF - yfract));
+
+    /* x2 * (xfract) * (1-yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) x2 * (0xFFFFF - yfract)) >> 4u);
+    acc += ((q63_t) out * (xfract));
+
+    /* y1 * (1 - xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y1 * (0xFFFFF - xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* y2 * (xfract) * (yfract)  in 1.51 and adding to acc */
+    out = (q31_t) (((q63_t) y2 * (xfract)) >> 4u);
+    acc += ((q63_t) out * (yfract));
+
+    /* acc is in 13.51 format and down shift acc by 36 times */
+    /* Convert out to 1.15 format */
+    return (acc >> 36);
+
+  }
+
+  /**
+  * @brief  Q7 bilinear interpolation.
+  * @param[in,out] *S points to an instance of the interpolation structure.
+  * @param[in] X interpolation coordinate in 12.20 format.
+  * @param[in] Y interpolation coordinate in 12.20 format.
+  * @return out interpolated value.
+  */
+
+  static __INLINE q7_t arm_bilinear_interp_q7(
+					      arm_bilinear_interp_instance_q7 * S,
+					      q31_t X,
+					      q31_t Y)
+  {
+    q63_t acc = 0;                               /* output */
+    q31_t out;                                   /* Temporary output */
+    q31_t xfract, yfract;                        /* X, Y fractional parts */
+    q7_t x1, x2, y1, y2;                         /* Nearest output values */
+    int32_t rI, cI;                             /* Row and column indices */
+    q7_t *pYData = S->pData;                     /* pointer to output table values */
+    uint32_t nCols = S->numCols;                 /* num of rows */
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    rI = ((X & 0xFFF00000) >> 20);
+
+    /* Input is in 12.20 format */
+    /* 12 bits for the table index */
+    /* Index value calculation */
+    cI = ((Y & 0xFFF00000) >> 20);
+
+	/* Care taken for table outside boundary */
+	/* Returns zero output when values are outside table boundary */
+	if(rI < 0 || rI > (S->numRows-1) || cI < 0  || cI > ( S->numCols-1))
+	{
+		return(0);
+	}
+
+    /* 20 bits for the fractional part */
+    /* xfract should be in 12.20 format */
+    xfract = (X & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    x1 = pYData[(rI) + nCols * (cI)];
+    x2 = pYData[(rI) + nCols * (cI) + 1u];
+
+
+    /* 20 bits for the fractional part */
+    /* yfract should be in 12.20 format */
+    yfract = (Y & 0x000FFFFF);
+
+    /* Read two nearest output values from the index */
+    y1 = pYData[(rI) + nCols * (cI + 1)];
+    y2 = pYData[(rI) + nCols * (cI + 1) + 1u];
+
+    /* Calculation of x1 * (1-xfract ) * (1-yfract) and acc is in 16.47 format */
+    out = ((x1 * (0xFFFFF - xfract)));
+    acc = (((q63_t) out * (0xFFFFF - yfract)));
+
+    /* x2 * (xfract) * (1-yfract)  in 2.22 and adding to acc */
+    out = ((x2 * (0xFFFFF - yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* y1 * (1 - xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y1 * (0xFFFFF - xfract)));
+    acc += (((q63_t) out * (yfract)));
+
+    /* y2 * (xfract) * (yfract)  in 2.22 and adding to acc */
+    out = ((y2 * (yfract)));
+    acc += (((q63_t) out * (xfract)));
+
+    /* acc in 16.47 format and down shift by 40 to convert to 1.7 format */
+    return (acc >> 40);
+
+  }
+
+  /**
+   * @} end of BilinearInterpolate group
+   */
+
+
+
+
+
+
+#ifdef	__cplusplus
+}
+#endif
+
+
+#endif /* _ARM_MATH_H */
+
+
+/**
+ *
+ * End of file.
+ */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/Include/core_cm0.h b/bsp/stm32f40x/Libraries/CMSIS/Include/core_cm0.h
new file mode 100644
index 0000000000..edd522173e
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/Include/core_cm0.h
@@ -0,0 +1,665 @@
+/**************************************************************************//**
+ * @file     core_cm0.h
+ * @brief    CMSIS Cortex-M0 Core Peripheral Access Layer Header File
+ * @version  V2.10
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM0_H_GENERIC
+#define __CORE_CM0_H_GENERIC
+
+
+/** \mainpage CMSIS Cortex-M0
+
+  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
+  It consists of:
+
+     - Cortex-M Core Register Definitions
+     - Cortex-M functions
+     - Cortex-M instructions
+
+  The CMSIS Cortex-M0 Core Peripheral Access Layer contains C and assembly functions that ease
+  access to the Cortex-M Core
+ */
+
+/** \defgroup CMSIS_MISRA_Exceptions  CMSIS MISRA-C:2004 Compliance Exceptions
+  CMSIS violates following MISRA-C2004 Rules:
+  
+   - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
    
+     Function definitions in header files are used to allow 'inlining'. 
+
+   - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    
+     Unions are used for effective representation of core registers.
+   
+   - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
    
+     Function-like macros are used to allow more efficient code. 
+
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
+  This file defines all structures and symbols for CMSIS core:
+   - CMSIS version number
+   - Cortex-M core
+   - Cortex-M core Revision Number
+  @{
+ */
+
+/*  CMSIS CM0 definitions */
+#define __CM0_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
+#define __CM0_CMSIS_VERSION_SUB   (0x10)                                                       /*!< [15:0]  CMSIS HAL sub version  */
+#define __CM0_CMSIS_VERSION       ((__CM0_CMSIS_VERSION_MAIN << 16) | __CM0_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+
+#define __CORTEX_M                (0x00)                                                       /*!< Cortex core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+    /* add preprocessor checks */
+#endif
+
+#include                       /*!< standard types definitions                      */
+#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
+#include "core_cmFunc.h"                 /*!< Core Function Access                            */
+
+#endif /* __CORE_CM0_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM0_H_DEPENDANT
+#define __CORE_CM0_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM0_REV
+    #define __CM0_REV               0x0000
+    #warning "__CM0_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          2
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< defines 'write only' permissions                */
+#define     __IO    volatile             /*!< defines 'read / write' permissions              */
+
+/*@} end of group CMSIS_core_definitions */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register CMSIS Core Register
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+*/
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CORE CMSIS Core
+  Type definitions for the Cortex-M Core Registers
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_NVIC CMSIS NVIC
+  Type definitions for the Cortex-M NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[1];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[31];
+  __IO uint32_t ICER[1];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register          */
+       uint32_t RSERVED1[31];
+  __IO uint32_t ISPR[1];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register           */
+       uint32_t RESERVED2[31];
+  __IO uint32_t ICPR[1];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register         */
+       uint32_t RESERVED3[31];
+       uint32_t RESERVED4[64];
+  __IO uint32_t IP[8];                   /*!< Offset: 0x300 (R/W)  Interrupt Priority Register              */
+}  NVIC_Type;
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB CMSIS SCB
+  Type definitions for the Cortex-M System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+       uint32_t RESERVED0;
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+       uint32_t RESERVED1;
+  __IO uint32_t SHP[2];                  /*!< Offset: 0x01C (R/W)  System Handlers Priority Registers. [0] is RESERVED   */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick CMSIS SysTick
+  Type definitions for the Cortex-M System Timer Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug CMSIS Core Debug
+  Cortex-M0 Core Debug Registers (DCB registers, SHCSR, and DFSR) are only accessible over DAP
+  and not via processor. Therefore they are not covered by the Cortex-M0 header file.
+  @{
+ */
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup  CMSIS_core_register
+  @{
+ */
+
+/* Memory mapping of Cortex-M0 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address           */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address              */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                 */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address */
+
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Register Access Functions
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
+  @{
+ */
+
+/* Interrupt Priorities are WORD accessible only under ARMv6M                   */
+/* The following MACROS handle generation of the register offset and byte masks */
+#define _BIT_SHIFT(IRQn)         (  (((uint32_t)(IRQn)       )    &  0x03) * 8 )
+#define _SHP_IDX(IRQn)           ( ((((uint32_t)(IRQn) & 0x0F)-8) >>    2)     )
+#define _IP_IDX(IRQn)            (   ((uint32_t)(IRQn)            >>    2)     )
+
+
+/** \brief  Enable External Interrupt
+
+    This function enables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to enable
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Disable External Interrupt
+
+    This function disables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to disable
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    This function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for get pending
+    \return             0  Interrupt status is not pending
+    \return             1  Interrupt status is pending
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[0] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0));
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    This function sets the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for set pending
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F));
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    This function clears the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for clear pending
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[0] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    This function sets the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    Note: The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for set priority
+    \param [in]  priority  Priority to set
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[_SHP_IDX(IRQn)] = (SCB->SHP[_SHP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+  else {
+    NVIC->IP[_IP_IDX(IRQn)] = (NVIC->IP[_IP_IDX(IRQn)] & ~(0xFF << _BIT_SHIFT(IRQn))) |
+        (((priority << (8 - __NVIC_PRIO_BITS)) & 0xFF) << _BIT_SHIFT(IRQn)); }
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    This function reads the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    The returned priority value is automatically aligned to the implemented
+    priority bits of the microcontroller.
+
+    \param [in]   IRQn  Number of the interrupt for get priority
+    \return             Interrupt Priority
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)((SCB->SHP[_SHP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M0 system interrupts */
+  else {
+    return((uint32_t)((NVIC->IP[ _IP_IDX(IRQn)] >> _BIT_SHIFT(IRQn) ) >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  System Reset
+
+    This function initiate a system reset request to reset the MCU.
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 SCB_AIRCR_SYSRESETREQ_Msk);
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    This function initialises the system tick timer and its interrupt and start the system tick timer.
+    Counter is in free running mode to generate periodical interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+
+#endif /* __CORE_CM0_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/stm32f40x/Libraries/CMSIS/Include/core_cm3.h b/bsp/stm32f40x/Libraries/CMSIS/Include/core_cm3.h
new file mode 100644
index 0000000000..c15e10ae2c
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/Include/core_cm3.h
@@ -0,0 +1,1236 @@
+/**************************************************************************//**
+ * @file     core_cm3.h
+ * @brief    CMSIS Cortex-M3 Core Peripheral Access Layer Header File
+ * @version  V2.10
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM3_H_GENERIC
+#define __CORE_CM3_H_GENERIC
+
+
+/** \mainpage CMSIS Cortex-M3
+
+  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
+  It consists of:
+
+     - Cortex-M Core Register Definitions
+     - Cortex-M functions
+     - Cortex-M instructions
+
+  The CMSIS Cortex-M3 Core Peripheral Access Layer contains C and assembly functions that ease
+  access to the Cortex-M Core
+ */
+
+/** \defgroup CMSIS_MISRA_Exceptions  CMSIS MISRA-C:2004 Compliance Exceptions
+  CMSIS violates following MISRA-C2004 Rules:
+  
+   - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
    
+     Function definitions in header files are used to allow 'inlining'. 
+
+   - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    
+     Unions are used for effective representation of core registers.
+   
+   - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
    
+     Function-like macros are used to allow more efficient code. 
+
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
+  This file defines all structures and symbols for CMSIS core:
+   - CMSIS version number
+   - Cortex-M core
+   - Cortex-M core Revision Number
+  @{
+ */
+
+/*  CMSIS CM3 definitions */
+#define __CM3_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
+#define __CM3_CMSIS_VERSION_SUB   (0x10)                                                       /*!< [15:0]  CMSIS HAL sub version  */
+#define __CM3_CMSIS_VERSION       ((__CM3_CMSIS_VERSION_MAIN << 16) | __CM3_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+
+#define __CORTEX_M                (0x03)                                                       /*!< Cortex core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
+#define __FPU_USED       0
+
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+  #endif
+
+#elif defined ( __TASKING__ )
+    /* add preprocessor checks */
+#endif
+
+#include                       /*!< standard types definitions                      */
+#include "core_cmInstr.h"                /*!< Core Instruction Access                         */
+#include "core_cmFunc.h"                 /*!< Core Function Access                            */
+
+#endif /* __CORE_CM3_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM3_H_DEPENDANT
+#define __CORE_CM3_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM3_REV
+    #define __CM3_REV               0x0200
+    #warning "__CM3_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< defines 'write only' permissions                */
+#define     __IO    volatile             /*!< defines 'read / write' permissions              */
+
+/*@} end of group CMSIS_core_definitions */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register CMSIS Core Register
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+*/
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CORE CMSIS Core
+  Type definitions for the Cortex-M Core Registers
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_NVIC CMSIS NVIC
+  Type definitions for the Cortex-M NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB CMSIS SCB
+  Type definitions for the Cortex-M System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB
+  Type definitions for the Cortex-M System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+#if ((defined __CM3_REV) && (__CM3_REV >= 0x200))
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register      */
+#else
+       uint32_t RESERVED1[1];
+#endif
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick CMSIS SysTick
+  Type definitions for the Cortex-M System Timer Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM CMSIS ITM
+  Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                          /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)             /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                          /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                   /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                          /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)          /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                          /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                          /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)             /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                          /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                 /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_TXENA_Pos                   3                                          /*!< ITM TCR: TXENA Position */
+#define ITM_TCR_TXENA_Msk                  (1UL << ITM_TCR_TXENA_Pos)                  /*!< ITM TCR: TXENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                          /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                          /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                  /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                          /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                 /*!< ITM TCR: ITM Enable bit Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU CMSIS MPU
+  Type definitions for the Cortex-M Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug CMSIS Core Debug
+  Type definitions for the Cortex-M Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup  CMSIS_core_register
+  @{
+ */
+
+/* Memory mapping of Cortex-M3 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
+  @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  This function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  This function gets the priority grouping from NVIC Interrupt Controller.
+  Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+
+    \return                Priority grouping field
+ */
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    This function enables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to enable
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    This function disables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to disable
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    This function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for get pending
+    \return             0  Interrupt status is not pending
+    \return             1  Interrupt status is pending
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    This function sets the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for set pending
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    This function clears the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for clear pending
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    This function reads the active register in NVIC and returns the active bit.
+    \param [in]      IRQn  Number of the interrupt for get active
+    \return             0  Interrupt status is not active
+    \return             1  Interrupt status is active
+ */
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    This function sets the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    Note: The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for set priority
+    \param [in]  priority  Priority to set
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    This function reads the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    The returned priority value is automatically aligned to the implemented
+    priority bits of the microcontroller.
+
+    \param [in]   IRQn  Number of the interrupt for get priority
+    \return             Interrupt Priority
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    This function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value and sub priority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    The returned priority value can be used for NVIC_SetPriority(...) function
+
+    \param [in]     PriorityGroup  Used priority group
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0)
+    \param [in]       SubPriority  Sub priority value (starting from 0)
+    \return                        Encoded priority for the interrupt
+ */
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    This function decodes an interrupt priority value with the given priority group to
+    preemptive priority value and sub priority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    The priority value can be retrieved with NVIC_GetPriority(...) function
+
+    \param [in]         Priority   Priority value
+    \param [in]     PriorityGroup  Used priority group
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0)
+    \param [out]     pSubPriority  Sub priority value (starting from 0)
+ */
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    This function initiate a system reset request to reset the MCU.
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    This function initialises the system tick timer and its interrupt and start the system tick timer.
+    Counter is in free running mode to generate periodical interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< external variable to receive characters                    */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+
+
+/** \brief  ITM Send Character
+
+    This function transmits a character via the ITM channel 0.
+    It just returns when no debugger is connected that has booked the output.
+    It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+    \param [in]     ch  Character to transmit
+    \return             Character to transmit
+ */
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
+      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    This function inputs a character via external variable ITM_RxBuffer.
+    It just returns when no debugger is connected that has booked the output.
+    It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+    \return             Received character
+    \return         -1  No character received
+ */
+static __INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    This function checks external variable ITM_RxBuffer whether a character is available or not.
+    It returns '1' if a character is available and '0' if no character is available.
+
+    \return          0  No character available
+    \return          1  Character available
+ */
+static __INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM3_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/stm32f40x/Libraries/CMSIS/Include/core_cm4.h b/bsp/stm32f40x/Libraries/CMSIS/Include/core_cm4.h
new file mode 100644
index 0000000000..76bf8292a9
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/Include/core_cm4.h
@@ -0,0 +1,1378 @@
+/**************************************************************************//**
+ * @file     core_cm4.h
+ * @brief    CMSIS Cortex-M4 Core Peripheral Access Layer Header File
+ * @version  V2.10
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M
+ * processor based microcontrollers.  This file can be freely distributed
+ * within development tools that are supporting such ARM based processors.
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+#if defined ( __ICCARM__ )
+ #pragma system_include  /* treat file as system include file for MISRA check */
+#endif
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+#ifndef __CORE_CM4_H_GENERIC
+#define __CORE_CM4_H_GENERIC
+
+
+/** \mainpage CMSIS Cortex-M4
+
+  This documentation describes the CMSIS Cortex-M Core Peripheral Access Layer.
+  It consists of:
+
+     - Cortex-M Core Register Definitions
+     - Cortex-M functions
+     - Cortex-M instructions
+     - Cortex-M SIMD instructions
+
+  The CMSIS Cortex-M4 Core Peripheral Access Layer contains C and assembly functions that ease
+  access to the Cortex-M Core
+ */
+
+/** \defgroup CMSIS_MISRA_Exceptions  CMSIS MISRA-C:2004 Compliance Exceptions
+  CMSIS violates following MISRA-C2004 Rules:
+  
+   - Violates MISRA 2004 Required Rule 8.5, object/function definition in header file.
    
+     Function definitions in header files are used to allow 'inlining'. 
+
+   - Violates MISRA 2004 Required Rule 18.4, declaration of union type or object of union type: '{...}'.
    
+     Unions are used for effective representation of core registers.
+   
+   - Violates MISRA 2004 Advisory Rule 19.7, Function-like macro defined.
    
+     Function-like macros are used to allow more efficient code. 
+
+ */
+
+
+/*******************************************************************************
+ *                 CMSIS definitions
+ ******************************************************************************/
+/** \defgroup CMSIS_core_definitions CMSIS Core Definitions
+  This file defines all structures and symbols for CMSIS core:
+   - CMSIS version number
+   - Cortex-M core
+   - Cortex-M core Revision Number
+  @{
+ */
+
+/*  CMSIS CM4 definitions */
+#define __CM4_CMSIS_VERSION_MAIN  (0x02)                                                       /*!< [31:16] CMSIS HAL main version */
+#define __CM4_CMSIS_VERSION_SUB   (0x10)                                                       /*!< [15:0]  CMSIS HAL sub version  */
+#define __CM4_CMSIS_VERSION       ((__CM4_CMSIS_VERSION_MAIN << 16) | __CM4_CMSIS_VERSION_SUB) /*!< CMSIS HAL version number       */
+
+#define __CORTEX_M                (0x04)                                                       /*!< Cortex core                    */
+
+
+#if   defined ( __CC_ARM )
+  #define __ASM            __asm                                      /*!< asm keyword for ARM Compiler          */
+  #define __INLINE         __inline                                   /*!< inline keyword for ARM Compiler       */
+
+#elif defined ( __ICCARM__ )
+  #define __ASM           __asm                                       /*!< asm keyword for IAR Compiler          */
+  #define __INLINE        inline                                      /*!< inline keyword for IAR Compiler. Only available in High optimization mode! */
+
+#elif defined ( __GNUC__ )
+  #define __ASM            __asm                                      /*!< asm keyword for GNU Compiler          */
+  #define __INLINE         inline                                     /*!< inline keyword for GNU Compiler       */
+
+#elif defined ( __TASKING__ )
+  #define __ASM            __asm                                      /*!< asm keyword for TASKING Compiler      */
+  #define __INLINE         inline                                     /*!< inline keyword for TASKING Compiler   */
+
+#endif
+
+/*!< __FPU_USED to be checked prior to making use of FPU specific registers and functions */
+#if defined ( __CC_ARM )
+  #if defined __TARGET_FPU_VFP
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __ICCARM__ )
+  #if defined __ARMVFP__
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __GNUC__ )
+  #if defined (__VFP_FP__) && !defined(__SOFTFP__)
+    #if (__FPU_PRESENT == 1)
+      #define __FPU_USED       1
+    #else
+      #warning "Compiler generates FPU instructions for a device without an FPU (check __FPU_PRESENT)"
+      #define __FPU_USED       0
+    #endif
+  #else
+    #define __FPU_USED         0
+  #endif
+
+#elif defined ( __TASKING__ )
+    /* add preprocessor checks to define __FPU_USED */
+    #define __FPU_USED         0
+#endif
+
+#include                       /*!< standard types definitions                      */
+#include                 /*!< Core Instruction Access                         */
+#include                  /*!< Core Function Access                            */
+#include                /*!< Compiler specific SIMD Intrinsics               */
+
+#endif /* __CORE_CM4_H_GENERIC */
+
+#ifndef __CMSIS_GENERIC
+
+#ifndef __CORE_CM4_H_DEPENDANT
+#define __CORE_CM4_H_DEPENDANT
+
+/* check device defines and use defaults */
+#if defined __CHECK_DEVICE_DEFINES
+  #ifndef __CM4_REV
+    #define __CM4_REV               0x0000
+    #warning "__CM4_REV not defined in device header file; using default!"
+  #endif
+
+  #ifndef __FPU_PRESENT
+    #define __FPU_PRESENT             0
+    #warning "__FPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __MPU_PRESENT
+    #define __MPU_PRESENT             0
+    #warning "__MPU_PRESENT not defined in device header file; using default!"
+  #endif
+
+  #ifndef __NVIC_PRIO_BITS
+    #define __NVIC_PRIO_BITS          4
+    #warning "__NVIC_PRIO_BITS not defined in device header file; using default!"
+  #endif
+
+  #ifndef __Vendor_SysTickConfig
+    #define __Vendor_SysTickConfig    0
+    #warning "__Vendor_SysTickConfig not defined in device header file; using default!"
+  #endif
+#endif
+
+/* IO definitions (access restrictions to peripheral registers) */
+#ifdef __cplusplus
+  #define   __I     volatile             /*!< defines 'read only' permissions                 */
+#else
+  #define   __I     volatile const       /*!< defines 'read only' permissions                 */
+#endif
+#define     __O     volatile             /*!< defines 'write only' permissions                */
+#define     __IO    volatile             /*!< defines 'read / write' permissions              */
+
+/*@} end of group CMSIS_core_definitions */
+
+
+
+/*******************************************************************************
+ *                 Register Abstraction
+ ******************************************************************************/
+/** \defgroup CMSIS_core_register CMSIS Core Register
+  Core Register contain:
+  - Core Register
+  - Core NVIC Register
+  - Core SCB Register
+  - Core SysTick Register
+  - Core Debug Register
+  - Core MPU Register
+  - Core FPU Register
+*/
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CORE CMSIS Core
+  Type definitions for the Cortex-M Core Registers
+  @{
+ */
+
+/** \brief  Union type to access the Application Program Status Register (APSR).
+ */
+typedef union
+{
+  struct
+  {
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:27;              /*!< bit:  0..26  Reserved                           */
+#else
+    uint32_t _reserved0:16;              /*!< bit:  0..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:7;               /*!< bit: 20..26  Reserved                           */
+#endif
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} APSR_Type;
+
+
+/** \brief  Union type to access the Interrupt Program Status Register (IPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+    uint32_t _reserved0:23;              /*!< bit:  9..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} IPSR_Type;
+
+
+/** \brief  Union type to access the Special-Purpose Program Status Registers (xPSR).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t ISR:9;                      /*!< bit:  0.. 8  Exception number                   */
+#if (__CORTEX_M != 0x04)
+    uint32_t _reserved0:15;              /*!< bit:  9..23  Reserved                           */
+#else
+    uint32_t _reserved0:7;               /*!< bit:  9..15  Reserved                           */
+    uint32_t GE:4;                       /*!< bit: 16..19  Greater than or Equal flags        */
+    uint32_t _reserved1:4;               /*!< bit: 20..23  Reserved                           */
+#endif
+    uint32_t T:1;                        /*!< bit:     24  Thumb bit        (read 0)          */
+    uint32_t IT:2;                       /*!< bit: 25..26  saved IT state   (read 0)          */
+    uint32_t Q:1;                        /*!< bit:     27  Saturation condition flag          */
+    uint32_t V:1;                        /*!< bit:     28  Overflow condition code flag       */
+    uint32_t C:1;                        /*!< bit:     29  Carry condition code flag          */
+    uint32_t Z:1;                        /*!< bit:     30  Zero condition code flag           */
+    uint32_t N:1;                        /*!< bit:     31  Negative condition code flag       */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} xPSR_Type;
+
+
+/** \brief  Union type to access the Control Registers (CONTROL).
+ */
+typedef union
+{
+  struct
+  {
+    uint32_t nPRIV:1;                    /*!< bit:      0  Execution privilege in Thread mode */
+    uint32_t SPSEL:1;                    /*!< bit:      1  Stack to be used                   */
+    uint32_t FPCA:1;                     /*!< bit:      2  FP extension active flag           */
+    uint32_t _reserved0:29;              /*!< bit:  3..31  Reserved                           */
+  } b;                                   /*!< Structure used for bit  access                  */
+  uint32_t w;                            /*!< Type      used for word access                  */
+} CONTROL_Type;
+
+/*@} end of group CMSIS_CORE */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_NVIC CMSIS NVIC
+  Type definitions for the Cortex-M NVIC Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Nested Vectored Interrupt Controller (NVIC).
+ */
+typedef struct
+{
+  __IO uint32_t ISER[8];                 /*!< Offset: 0x000 (R/W)  Interrupt Set Enable Register           */
+       uint32_t RESERVED0[24];
+  __IO uint32_t ICER[8];                 /*!< Offset: 0x080 (R/W)  Interrupt Clear Enable Register         */
+       uint32_t RSERVED1[24];
+  __IO uint32_t ISPR[8];                 /*!< Offset: 0x100 (R/W)  Interrupt Set Pending Register          */
+       uint32_t RESERVED2[24];
+  __IO uint32_t ICPR[8];                 /*!< Offset: 0x180 (R/W)  Interrupt Clear Pending Register        */
+       uint32_t RESERVED3[24];
+  __IO uint32_t IABR[8];                 /*!< Offset: 0x200 (R/W)  Interrupt Active bit Register           */
+       uint32_t RESERVED4[56];
+  __IO uint8_t  IP[240];                 /*!< Offset: 0x300 (R/W)  Interrupt Priority Register (8Bit wide) */
+       uint32_t RESERVED5[644];
+  __O  uint32_t STIR;                    /*!< Offset: 0xE00 ( /W)  Software Trigger Interrupt Register     */
+}  NVIC_Type;
+
+/* Software Triggered Interrupt Register Definitions */
+#define NVIC_STIR_INTID_Pos                 0                                          /*!< STIR: INTLINESNUM Position */
+#define NVIC_STIR_INTID_Msk                (0x1FFUL << NVIC_STIR_INTID_Pos)            /*!< STIR: INTLINESNUM Mask */
+
+/*@} end of group CMSIS_NVIC */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCB CMSIS SCB
+  Type definitions for the Cortex-M System Control Block Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Control Block (SCB).
+ */
+typedef struct
+{
+  __I  uint32_t CPUID;                   /*!< Offset: 0x000 (R/ )  CPUID Base Register                                   */
+  __IO uint32_t ICSR;                    /*!< Offset: 0x004 (R/W)  Interrupt Control and State Register                  */
+  __IO uint32_t VTOR;                    /*!< Offset: 0x008 (R/W)  Vector Table Offset Register                          */
+  __IO uint32_t AIRCR;                   /*!< Offset: 0x00C (R/W)  Application Interrupt and Reset Control Register      */
+  __IO uint32_t SCR;                     /*!< Offset: 0x010 (R/W)  System Control Register                               */
+  __IO uint32_t CCR;                     /*!< Offset: 0x014 (R/W)  Configuration Control Register                        */
+  __IO uint8_t  SHP[12];                 /*!< Offset: 0x018 (R/W)  System Handlers Priority Registers (4-7, 8-11, 12-15) */
+  __IO uint32_t SHCSR;                   /*!< Offset: 0x024 (R/W)  System Handler Control and State Register             */
+  __IO uint32_t CFSR;                    /*!< Offset: 0x028 (R/W)  Configurable Fault Status Register                    */
+  __IO uint32_t HFSR;                    /*!< Offset: 0x02C (R/W)  HardFault Status Register                             */
+  __IO uint32_t DFSR;                    /*!< Offset: 0x030 (R/W)  Debug Fault Status Register                           */
+  __IO uint32_t MMFAR;                   /*!< Offset: 0x034 (R/W)  MemManage Fault Address Register                      */
+  __IO uint32_t BFAR;                    /*!< Offset: 0x038 (R/W)  BusFault Address Register                             */
+  __IO uint32_t AFSR;                    /*!< Offset: 0x03C (R/W)  Auxiliary Fault Status Register                       */
+  __I  uint32_t PFR[2];                  /*!< Offset: 0x040 (R/ )  Processor Feature Register                            */
+  __I  uint32_t DFR;                     /*!< Offset: 0x048 (R/ )  Debug Feature Register                                */
+  __I  uint32_t ADR;                     /*!< Offset: 0x04C (R/ )  Auxiliary Feature Register                            */
+  __I  uint32_t MMFR[4];                 /*!< Offset: 0x050 (R/ )  Memory Model Feature Register                         */
+  __I  uint32_t ISAR[5];                 /*!< Offset: 0x060 (R/ )  Instruction Set Attributes Register                   */
+       uint32_t RESERVED0[5];
+  __IO uint32_t CPACR;                   /*!< Offset: 0x088 (R/W)  Coprocessor Access Control Register                   */
+} SCB_Type;
+
+/* SCB CPUID Register Definitions */
+#define SCB_CPUID_IMPLEMENTER_Pos          24                                             /*!< SCB CPUID: IMPLEMENTER Position */
+#define SCB_CPUID_IMPLEMENTER_Msk          (0xFFUL << SCB_CPUID_IMPLEMENTER_Pos)          /*!< SCB CPUID: IMPLEMENTER Mask */
+
+#define SCB_CPUID_VARIANT_Pos              20                                             /*!< SCB CPUID: VARIANT Position */
+#define SCB_CPUID_VARIANT_Msk              (0xFUL << SCB_CPUID_VARIANT_Pos)               /*!< SCB CPUID: VARIANT Mask */
+
+#define SCB_CPUID_ARCHITECTURE_Pos         16                                             /*!< SCB CPUID: ARCHITECTURE Position */
+#define SCB_CPUID_ARCHITECTURE_Msk         (0xFUL << SCB_CPUID_ARCHITECTURE_Pos)          /*!< SCB CPUID: ARCHITECTURE Mask */
+
+#define SCB_CPUID_PARTNO_Pos                4                                             /*!< SCB CPUID: PARTNO Position */
+#define SCB_CPUID_PARTNO_Msk               (0xFFFUL << SCB_CPUID_PARTNO_Pos)              /*!< SCB CPUID: PARTNO Mask */
+
+#define SCB_CPUID_REVISION_Pos              0                                             /*!< SCB CPUID: REVISION Position */
+#define SCB_CPUID_REVISION_Msk             (0xFUL << SCB_CPUID_REVISION_Pos)              /*!< SCB CPUID: REVISION Mask */
+
+/* SCB Interrupt Control State Register Definitions */
+#define SCB_ICSR_NMIPENDSET_Pos            31                                             /*!< SCB ICSR: NMIPENDSET Position */
+#define SCB_ICSR_NMIPENDSET_Msk            (1UL << SCB_ICSR_NMIPENDSET_Pos)               /*!< SCB ICSR: NMIPENDSET Mask */
+
+#define SCB_ICSR_PENDSVSET_Pos             28                                             /*!< SCB ICSR: PENDSVSET Position */
+#define SCB_ICSR_PENDSVSET_Msk             (1UL << SCB_ICSR_PENDSVSET_Pos)                /*!< SCB ICSR: PENDSVSET Mask */
+
+#define SCB_ICSR_PENDSVCLR_Pos             27                                             /*!< SCB ICSR: PENDSVCLR Position */
+#define SCB_ICSR_PENDSVCLR_Msk             (1UL << SCB_ICSR_PENDSVCLR_Pos)                /*!< SCB ICSR: PENDSVCLR Mask */
+
+#define SCB_ICSR_PENDSTSET_Pos             26                                             /*!< SCB ICSR: PENDSTSET Position */
+#define SCB_ICSR_PENDSTSET_Msk             (1UL << SCB_ICSR_PENDSTSET_Pos)                /*!< SCB ICSR: PENDSTSET Mask */
+
+#define SCB_ICSR_PENDSTCLR_Pos             25                                             /*!< SCB ICSR: PENDSTCLR Position */
+#define SCB_ICSR_PENDSTCLR_Msk             (1UL << SCB_ICSR_PENDSTCLR_Pos)                /*!< SCB ICSR: PENDSTCLR Mask */
+
+#define SCB_ICSR_ISRPREEMPT_Pos            23                                             /*!< SCB ICSR: ISRPREEMPT Position */
+#define SCB_ICSR_ISRPREEMPT_Msk            (1UL << SCB_ICSR_ISRPREEMPT_Pos)               /*!< SCB ICSR: ISRPREEMPT Mask */
+
+#define SCB_ICSR_ISRPENDING_Pos            22                                             /*!< SCB ICSR: ISRPENDING Position */
+#define SCB_ICSR_ISRPENDING_Msk            (1UL << SCB_ICSR_ISRPENDING_Pos)               /*!< SCB ICSR: ISRPENDING Mask */
+
+#define SCB_ICSR_VECTPENDING_Pos           12                                             /*!< SCB ICSR: VECTPENDING Position */
+#define SCB_ICSR_VECTPENDING_Msk           (0x1FFUL << SCB_ICSR_VECTPENDING_Pos)          /*!< SCB ICSR: VECTPENDING Mask */
+
+#define SCB_ICSR_RETTOBASE_Pos             11                                             /*!< SCB ICSR: RETTOBASE Position */
+#define SCB_ICSR_RETTOBASE_Msk             (1UL << SCB_ICSR_RETTOBASE_Pos)                /*!< SCB ICSR: RETTOBASE Mask */
+
+#define SCB_ICSR_VECTACTIVE_Pos             0                                             /*!< SCB ICSR: VECTACTIVE Position */
+#define SCB_ICSR_VECTACTIVE_Msk            (0x1FFUL << SCB_ICSR_VECTACTIVE_Pos)           /*!< SCB ICSR: VECTACTIVE Mask */
+
+/* SCB Vector Table Offset Register Definitions */
+#define SCB_VTOR_TBLOFF_Pos                 7                                             /*!< SCB VTOR: TBLOFF Position */
+#define SCB_VTOR_TBLOFF_Msk                (0x1FFFFFFUL << SCB_VTOR_TBLOFF_Pos)           /*!< SCB VTOR: TBLOFF Mask */
+
+/* SCB Application Interrupt and Reset Control Register Definitions */
+#define SCB_AIRCR_VECTKEY_Pos              16                                             /*!< SCB AIRCR: VECTKEY Position */
+#define SCB_AIRCR_VECTKEY_Msk              (0xFFFFUL << SCB_AIRCR_VECTKEY_Pos)            /*!< SCB AIRCR: VECTKEY Mask */
+
+#define SCB_AIRCR_VECTKEYSTAT_Pos          16                                             /*!< SCB AIRCR: VECTKEYSTAT Position */
+#define SCB_AIRCR_VECTKEYSTAT_Msk          (0xFFFFUL << SCB_AIRCR_VECTKEYSTAT_Pos)        /*!< SCB AIRCR: VECTKEYSTAT Mask */
+
+#define SCB_AIRCR_ENDIANESS_Pos            15                                             /*!< SCB AIRCR: ENDIANESS Position */
+#define SCB_AIRCR_ENDIANESS_Msk            (1UL << SCB_AIRCR_ENDIANESS_Pos)               /*!< SCB AIRCR: ENDIANESS Mask */
+
+#define SCB_AIRCR_PRIGROUP_Pos              8                                             /*!< SCB AIRCR: PRIGROUP Position */
+#define SCB_AIRCR_PRIGROUP_Msk             (7UL << SCB_AIRCR_PRIGROUP_Pos)                /*!< SCB AIRCR: PRIGROUP Mask */
+
+#define SCB_AIRCR_SYSRESETREQ_Pos           2                                             /*!< SCB AIRCR: SYSRESETREQ Position */
+#define SCB_AIRCR_SYSRESETREQ_Msk          (1UL << SCB_AIRCR_SYSRESETREQ_Pos)             /*!< SCB AIRCR: SYSRESETREQ Mask */
+
+#define SCB_AIRCR_VECTCLRACTIVE_Pos         1                                             /*!< SCB AIRCR: VECTCLRACTIVE Position */
+#define SCB_AIRCR_VECTCLRACTIVE_Msk        (1UL << SCB_AIRCR_VECTCLRACTIVE_Pos)           /*!< SCB AIRCR: VECTCLRACTIVE Mask */
+
+#define SCB_AIRCR_VECTRESET_Pos             0                                             /*!< SCB AIRCR: VECTRESET Position */
+#define SCB_AIRCR_VECTRESET_Msk            (1UL << SCB_AIRCR_VECTRESET_Pos)               /*!< SCB AIRCR: VECTRESET Mask */
+
+/* SCB System Control Register Definitions */
+#define SCB_SCR_SEVONPEND_Pos               4                                             /*!< SCB SCR: SEVONPEND Position */
+#define SCB_SCR_SEVONPEND_Msk              (1UL << SCB_SCR_SEVONPEND_Pos)                 /*!< SCB SCR: SEVONPEND Mask */
+
+#define SCB_SCR_SLEEPDEEP_Pos               2                                             /*!< SCB SCR: SLEEPDEEP Position */
+#define SCB_SCR_SLEEPDEEP_Msk              (1UL << SCB_SCR_SLEEPDEEP_Pos)                 /*!< SCB SCR: SLEEPDEEP Mask */
+
+#define SCB_SCR_SLEEPONEXIT_Pos             1                                             /*!< SCB SCR: SLEEPONEXIT Position */
+#define SCB_SCR_SLEEPONEXIT_Msk            (1UL << SCB_SCR_SLEEPONEXIT_Pos)               /*!< SCB SCR: SLEEPONEXIT Mask */
+
+/* SCB Configuration Control Register Definitions */
+#define SCB_CCR_STKALIGN_Pos                9                                             /*!< SCB CCR: STKALIGN Position */
+#define SCB_CCR_STKALIGN_Msk               (1UL << SCB_CCR_STKALIGN_Pos)                  /*!< SCB CCR: STKALIGN Mask */
+
+#define SCB_CCR_BFHFNMIGN_Pos               8                                             /*!< SCB CCR: BFHFNMIGN Position */
+#define SCB_CCR_BFHFNMIGN_Msk              (1UL << SCB_CCR_BFHFNMIGN_Pos)                 /*!< SCB CCR: BFHFNMIGN Mask */
+
+#define SCB_CCR_DIV_0_TRP_Pos               4                                             /*!< SCB CCR: DIV_0_TRP Position */
+#define SCB_CCR_DIV_0_TRP_Msk              (1UL << SCB_CCR_DIV_0_TRP_Pos)                 /*!< SCB CCR: DIV_0_TRP Mask */
+
+#define SCB_CCR_UNALIGN_TRP_Pos             3                                             /*!< SCB CCR: UNALIGN_TRP Position */
+#define SCB_CCR_UNALIGN_TRP_Msk            (1UL << SCB_CCR_UNALIGN_TRP_Pos)               /*!< SCB CCR: UNALIGN_TRP Mask */
+
+#define SCB_CCR_USERSETMPEND_Pos            1                                             /*!< SCB CCR: USERSETMPEND Position */
+#define SCB_CCR_USERSETMPEND_Msk           (1UL << SCB_CCR_USERSETMPEND_Pos)              /*!< SCB CCR: USERSETMPEND Mask */
+
+#define SCB_CCR_NONBASETHRDENA_Pos          0                                             /*!< SCB CCR: NONBASETHRDENA Position */
+#define SCB_CCR_NONBASETHRDENA_Msk         (1UL << SCB_CCR_NONBASETHRDENA_Pos)            /*!< SCB CCR: NONBASETHRDENA Mask */
+
+/* SCB System Handler Control and State Register Definitions */
+#define SCB_SHCSR_USGFAULTENA_Pos          18                                             /*!< SCB SHCSR: USGFAULTENA Position */
+#define SCB_SHCSR_USGFAULTENA_Msk          (1UL << SCB_SHCSR_USGFAULTENA_Pos)             /*!< SCB SHCSR: USGFAULTENA Mask */
+
+#define SCB_SHCSR_BUSFAULTENA_Pos          17                                             /*!< SCB SHCSR: BUSFAULTENA Position */
+#define SCB_SHCSR_BUSFAULTENA_Msk          (1UL << SCB_SHCSR_BUSFAULTENA_Pos)             /*!< SCB SHCSR: BUSFAULTENA Mask */
+
+#define SCB_SHCSR_MEMFAULTENA_Pos          16                                             /*!< SCB SHCSR: MEMFAULTENA Position */
+#define SCB_SHCSR_MEMFAULTENA_Msk          (1UL << SCB_SHCSR_MEMFAULTENA_Pos)             /*!< SCB SHCSR: MEMFAULTENA Mask */
+
+#define SCB_SHCSR_SVCALLPENDED_Pos         15                                             /*!< SCB SHCSR: SVCALLPENDED Position */
+#define SCB_SHCSR_SVCALLPENDED_Msk         (1UL << SCB_SHCSR_SVCALLPENDED_Pos)            /*!< SCB SHCSR: SVCALLPENDED Mask */
+
+#define SCB_SHCSR_BUSFAULTPENDED_Pos       14                                             /*!< SCB SHCSR: BUSFAULTPENDED Position */
+#define SCB_SHCSR_BUSFAULTPENDED_Msk       (1UL << SCB_SHCSR_BUSFAULTPENDED_Pos)          /*!< SCB SHCSR: BUSFAULTPENDED Mask */
+
+#define SCB_SHCSR_MEMFAULTPENDED_Pos       13                                             /*!< SCB SHCSR: MEMFAULTPENDED Position */
+#define SCB_SHCSR_MEMFAULTPENDED_Msk       (1UL << SCB_SHCSR_MEMFAULTPENDED_Pos)          /*!< SCB SHCSR: MEMFAULTPENDED Mask */
+
+#define SCB_SHCSR_USGFAULTPENDED_Pos       12                                             /*!< SCB SHCSR: USGFAULTPENDED Position */
+#define SCB_SHCSR_USGFAULTPENDED_Msk       (1UL << SCB_SHCSR_USGFAULTPENDED_Pos)          /*!< SCB SHCSR: USGFAULTPENDED Mask */
+
+#define SCB_SHCSR_SYSTICKACT_Pos           11                                             /*!< SCB SHCSR: SYSTICKACT Position */
+#define SCB_SHCSR_SYSTICKACT_Msk           (1UL << SCB_SHCSR_SYSTICKACT_Pos)              /*!< SCB SHCSR: SYSTICKACT Mask */
+
+#define SCB_SHCSR_PENDSVACT_Pos            10                                             /*!< SCB SHCSR: PENDSVACT Position */
+#define SCB_SHCSR_PENDSVACT_Msk            (1UL << SCB_SHCSR_PENDSVACT_Pos)               /*!< SCB SHCSR: PENDSVACT Mask */
+
+#define SCB_SHCSR_MONITORACT_Pos            8                                             /*!< SCB SHCSR: MONITORACT Position */
+#define SCB_SHCSR_MONITORACT_Msk           (1UL << SCB_SHCSR_MONITORACT_Pos)              /*!< SCB SHCSR: MONITORACT Mask */
+
+#define SCB_SHCSR_SVCALLACT_Pos             7                                             /*!< SCB SHCSR: SVCALLACT Position */
+#define SCB_SHCSR_SVCALLACT_Msk            (1UL << SCB_SHCSR_SVCALLACT_Pos)               /*!< SCB SHCSR: SVCALLACT Mask */
+
+#define SCB_SHCSR_USGFAULTACT_Pos           3                                             /*!< SCB SHCSR: USGFAULTACT Position */
+#define SCB_SHCSR_USGFAULTACT_Msk          (1UL << SCB_SHCSR_USGFAULTACT_Pos)             /*!< SCB SHCSR: USGFAULTACT Mask */
+
+#define SCB_SHCSR_BUSFAULTACT_Pos           1                                             /*!< SCB SHCSR: BUSFAULTACT Position */
+#define SCB_SHCSR_BUSFAULTACT_Msk          (1UL << SCB_SHCSR_BUSFAULTACT_Pos)             /*!< SCB SHCSR: BUSFAULTACT Mask */
+
+#define SCB_SHCSR_MEMFAULTACT_Pos           0                                             /*!< SCB SHCSR: MEMFAULTACT Position */
+#define SCB_SHCSR_MEMFAULTACT_Msk          (1UL << SCB_SHCSR_MEMFAULTACT_Pos)             /*!< SCB SHCSR: MEMFAULTACT Mask */
+
+/* SCB Configurable Fault Status Registers Definitions */
+#define SCB_CFSR_USGFAULTSR_Pos            16                                             /*!< SCB CFSR: Usage Fault Status Register Position */
+#define SCB_CFSR_USGFAULTSR_Msk            (0xFFFFUL << SCB_CFSR_USGFAULTSR_Pos)          /*!< SCB CFSR: Usage Fault Status Register Mask */
+
+#define SCB_CFSR_BUSFAULTSR_Pos             8                                             /*!< SCB CFSR: Bus Fault Status Register Position */
+#define SCB_CFSR_BUSFAULTSR_Msk            (0xFFUL << SCB_CFSR_BUSFAULTSR_Pos)            /*!< SCB CFSR: Bus Fault Status Register Mask */
+
+#define SCB_CFSR_MEMFAULTSR_Pos             0                                             /*!< SCB CFSR: Memory Manage Fault Status Register Position */
+#define SCB_CFSR_MEMFAULTSR_Msk            (0xFFUL << SCB_CFSR_MEMFAULTSR_Pos)            /*!< SCB CFSR: Memory Manage Fault Status Register Mask */
+
+/* SCB Hard Fault Status Registers Definitions */
+#define SCB_HFSR_DEBUGEVT_Pos              31                                             /*!< SCB HFSR: DEBUGEVT Position */
+#define SCB_HFSR_DEBUGEVT_Msk              (1UL << SCB_HFSR_DEBUGEVT_Pos)                 /*!< SCB HFSR: DEBUGEVT Mask */
+
+#define SCB_HFSR_FORCED_Pos                30                                             /*!< SCB HFSR: FORCED Position */
+#define SCB_HFSR_FORCED_Msk                (1UL << SCB_HFSR_FORCED_Pos)                   /*!< SCB HFSR: FORCED Mask */
+
+#define SCB_HFSR_VECTTBL_Pos                1                                             /*!< SCB HFSR: VECTTBL Position */
+#define SCB_HFSR_VECTTBL_Msk               (1UL << SCB_HFSR_VECTTBL_Pos)                  /*!< SCB HFSR: VECTTBL Mask */
+
+/* SCB Debug Fault Status Register Definitions */
+#define SCB_DFSR_EXTERNAL_Pos               4                                             /*!< SCB DFSR: EXTERNAL Position */
+#define SCB_DFSR_EXTERNAL_Msk              (1UL << SCB_DFSR_EXTERNAL_Pos)                 /*!< SCB DFSR: EXTERNAL Mask */
+
+#define SCB_DFSR_VCATCH_Pos                 3                                             /*!< SCB DFSR: VCATCH Position */
+#define SCB_DFSR_VCATCH_Msk                (1UL << SCB_DFSR_VCATCH_Pos)                   /*!< SCB DFSR: VCATCH Mask */
+
+#define SCB_DFSR_DWTTRAP_Pos                2                                             /*!< SCB DFSR: DWTTRAP Position */
+#define SCB_DFSR_DWTTRAP_Msk               (1UL << SCB_DFSR_DWTTRAP_Pos)                  /*!< SCB DFSR: DWTTRAP Mask */
+
+#define SCB_DFSR_BKPT_Pos                   1                                             /*!< SCB DFSR: BKPT Position */
+#define SCB_DFSR_BKPT_Msk                  (1UL << SCB_DFSR_BKPT_Pos)                     /*!< SCB DFSR: BKPT Mask */
+
+#define SCB_DFSR_HALTED_Pos                 0                                             /*!< SCB DFSR: HALTED Position */
+#define SCB_DFSR_HALTED_Msk                (1UL << SCB_DFSR_HALTED_Pos)                   /*!< SCB DFSR: HALTED Mask */
+
+/*@} end of group CMSIS_SCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SCnSCB CMSIS System Control and ID Register not in the SCB
+  Type definitions for the Cortex-M System Control and ID Register not in the SCB
+  @{
+ */
+
+/** \brief  Structure type to access the System Control and ID Register not in the SCB.
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __I  uint32_t ICTR;                    /*!< Offset: 0x004 (R/ )  Interrupt Controller Type Register      */
+  __IO uint32_t ACTLR;                   /*!< Offset: 0x008 (R/W)  Auxiliary Control Register              */
+} SCnSCB_Type;
+
+/* Interrupt Controller Type Register Definitions */
+#define SCnSCB_ICTR_INTLINESNUM_Pos         0                                          /*!< ICTR: INTLINESNUM Position */
+#define SCnSCB_ICTR_INTLINESNUM_Msk        (0xFUL << SCnSCB_ICTR_INTLINESNUM_Pos)      /*!< ICTR: INTLINESNUM Mask */
+
+/* Auxiliary Control Register Definitions */
+#define SCnSCB_ACTLR_DISOOFP_Pos            9                                          /*!< ACTLR: DISOOFP Position */
+#define SCnSCB_ACTLR_DISOOFP_Msk           (1UL << SCnSCB_ACTLR_DISOOFP_Pos)           /*!< ACTLR: DISOOFP Mask */
+
+#define SCnSCB_ACTLR_DISFPCA_Pos            8                                          /*!< ACTLR: DISFPCA Position */
+#define SCnSCB_ACTLR_DISFPCA_Msk           (1UL << SCnSCB_ACTLR_DISFPCA_Pos)           /*!< ACTLR: DISFPCA Mask */
+
+#define SCnSCB_ACTLR_DISFOLD_Pos            2                                          /*!< ACTLR: DISFOLD Position */
+#define SCnSCB_ACTLR_DISFOLD_Msk           (1UL << SCnSCB_ACTLR_DISFOLD_Pos)           /*!< ACTLR: DISFOLD Mask */
+
+#define SCnSCB_ACTLR_DISDEFWBUF_Pos         1                                          /*!< ACTLR: DISDEFWBUF Position */
+#define SCnSCB_ACTLR_DISDEFWBUF_Msk        (1UL << SCnSCB_ACTLR_DISDEFWBUF_Pos)        /*!< ACTLR: DISDEFWBUF Mask */
+
+#define SCnSCB_ACTLR_DISMCYCINT_Pos         0                                          /*!< ACTLR: DISMCYCINT Position */
+#define SCnSCB_ACTLR_DISMCYCINT_Msk        (1UL << SCnSCB_ACTLR_DISMCYCINT_Pos)        /*!< ACTLR: DISMCYCINT Mask */
+
+/*@} end of group CMSIS_SCnotSCB */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_SysTick CMSIS SysTick
+  Type definitions for the Cortex-M System Timer Registers
+  @{
+ */
+
+/** \brief  Structure type to access the System Timer (SysTick).
+ */
+typedef struct
+{
+  __IO uint32_t CTRL;                    /*!< Offset: 0x000 (R/W)  SysTick Control and Status Register */
+  __IO uint32_t LOAD;                    /*!< Offset: 0x004 (R/W)  SysTick Reload Value Register       */
+  __IO uint32_t VAL;                     /*!< Offset: 0x008 (R/W)  SysTick Current Value Register      */
+  __I  uint32_t CALIB;                   /*!< Offset: 0x00C (R/ )  SysTick Calibration Register        */
+} SysTick_Type;
+
+/* SysTick Control / Status Register Definitions */
+#define SysTick_CTRL_COUNTFLAG_Pos         16                                             /*!< SysTick CTRL: COUNTFLAG Position */
+#define SysTick_CTRL_COUNTFLAG_Msk         (1UL << SysTick_CTRL_COUNTFLAG_Pos)            /*!< SysTick CTRL: COUNTFLAG Mask */
+
+#define SysTick_CTRL_CLKSOURCE_Pos          2                                             /*!< SysTick CTRL: CLKSOURCE Position */
+#define SysTick_CTRL_CLKSOURCE_Msk         (1UL << SysTick_CTRL_CLKSOURCE_Pos)            /*!< SysTick CTRL: CLKSOURCE Mask */
+
+#define SysTick_CTRL_TICKINT_Pos            1                                             /*!< SysTick CTRL: TICKINT Position */
+#define SysTick_CTRL_TICKINT_Msk           (1UL << SysTick_CTRL_TICKINT_Pos)              /*!< SysTick CTRL: TICKINT Mask */
+
+#define SysTick_CTRL_ENABLE_Pos             0                                             /*!< SysTick CTRL: ENABLE Position */
+#define SysTick_CTRL_ENABLE_Msk            (1UL << SysTick_CTRL_ENABLE_Pos)               /*!< SysTick CTRL: ENABLE Mask */
+
+/* SysTick Reload Register Definitions */
+#define SysTick_LOAD_RELOAD_Pos             0                                             /*!< SysTick LOAD: RELOAD Position */
+#define SysTick_LOAD_RELOAD_Msk            (0xFFFFFFUL << SysTick_LOAD_RELOAD_Pos)        /*!< SysTick LOAD: RELOAD Mask */
+
+/* SysTick Current Register Definitions */
+#define SysTick_VAL_CURRENT_Pos             0                                             /*!< SysTick VAL: CURRENT Position */
+#define SysTick_VAL_CURRENT_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick VAL: CURRENT Mask */
+
+/* SysTick Calibration Register Definitions */
+#define SysTick_CALIB_NOREF_Pos            31                                             /*!< SysTick CALIB: NOREF Position */
+#define SysTick_CALIB_NOREF_Msk            (1UL << SysTick_CALIB_NOREF_Pos)               /*!< SysTick CALIB: NOREF Mask */
+
+#define SysTick_CALIB_SKEW_Pos             30                                             /*!< SysTick CALIB: SKEW Position */
+#define SysTick_CALIB_SKEW_Msk             (1UL << SysTick_CALIB_SKEW_Pos)                /*!< SysTick CALIB: SKEW Mask */
+
+#define SysTick_CALIB_TENMS_Pos             0                                             /*!< SysTick CALIB: TENMS Position */
+#define SysTick_CALIB_TENMS_Msk            (0xFFFFFFUL << SysTick_VAL_CURRENT_Pos)        /*!< SysTick CALIB: TENMS Mask */
+
+/*@} end of group CMSIS_SysTick */
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_ITM CMSIS ITM
+  Type definitions for the Cortex-M Instrumentation Trace Macrocell (ITM)
+  @{
+ */
+
+/** \brief  Structure type to access the Instrumentation Trace Macrocell Register (ITM).
+ */
+typedef struct
+{
+  __O  union
+  {
+    __O  uint8_t    u8;                  /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 8-bit                   */
+    __O  uint16_t   u16;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 16-bit                  */
+    __O  uint32_t   u32;                 /*!< Offset: 0x000 ( /W)  ITM Stimulus Port 32-bit                  */
+  }  PORT [32];                          /*!< Offset: 0x000 ( /W)  ITM Stimulus Port Registers               */
+       uint32_t RESERVED0[864];
+  __IO uint32_t TER;                     /*!< Offset: 0xE00 (R/W)  ITM Trace Enable Register                 */
+       uint32_t RESERVED1[15];
+  __IO uint32_t TPR;                     /*!< Offset: 0xE40 (R/W)  ITM Trace Privilege Register              */
+       uint32_t RESERVED2[15];
+  __IO uint32_t TCR;                     /*!< Offset: 0xE80 (R/W)  ITM Trace Control Register                */
+} ITM_Type;
+
+/* ITM Trace Privilege Register Definitions */
+#define ITM_TPR_PRIVMASK_Pos                0                                          /*!< ITM TPR: PRIVMASK Position */
+#define ITM_TPR_PRIVMASK_Msk               (0xFUL << ITM_TPR_PRIVMASK_Pos)             /*!< ITM TPR: PRIVMASK Mask */
+
+/* ITM Trace Control Register Definitions */
+#define ITM_TCR_BUSY_Pos                   23                                          /*!< ITM TCR: BUSY Position */
+#define ITM_TCR_BUSY_Msk                   (1UL << ITM_TCR_BUSY_Pos)                   /*!< ITM TCR: BUSY Mask */
+
+#define ITM_TCR_TraceBusID_Pos             16                                          /*!< ITM TCR: ATBID Position */
+#define ITM_TCR_TraceBusID_Msk             (0x7FUL << ITM_TCR_TraceBusID_Pos)          /*!< ITM TCR: ATBID Mask */
+
+#define ITM_TCR_GTSFREQ_Pos                10                                          /*!< ITM TCR: Global timestamp frequency Position */
+#define ITM_TCR_GTSFREQ_Msk                (3UL << ITM_TCR_GTSFREQ_Pos)                /*!< ITM TCR: Global timestamp frequency Mask */
+
+#define ITM_TCR_TSPrescale_Pos              8                                          /*!< ITM TCR: TSPrescale Position */
+#define ITM_TCR_TSPrescale_Msk             (3UL << ITM_TCR_TSPrescale_Pos)             /*!< ITM TCR: TSPrescale Mask */
+
+#define ITM_TCR_SWOENA_Pos                  4                                          /*!< ITM TCR: SWOENA Position */
+#define ITM_TCR_SWOENA_Msk                 (1UL << ITM_TCR_SWOENA_Pos)                 /*!< ITM TCR: SWOENA Mask */
+
+#define ITM_TCR_TXENA_Pos                   3                                          /*!< ITM TCR: TXENA Position */
+#define ITM_TCR_TXENA_Msk                  (1UL << ITM_TCR_TXENA_Pos)                  /*!< ITM TCR: TXENA Mask */
+
+#define ITM_TCR_SYNCENA_Pos                 2                                          /*!< ITM TCR: SYNCENA Position */
+#define ITM_TCR_SYNCENA_Msk                (1UL << ITM_TCR_SYNCENA_Pos)                /*!< ITM TCR: SYNCENA Mask */
+
+#define ITM_TCR_TSENA_Pos                   1                                          /*!< ITM TCR: TSENA Position */
+#define ITM_TCR_TSENA_Msk                  (1UL << ITM_TCR_TSENA_Pos)                  /*!< ITM TCR: TSENA Mask */
+
+#define ITM_TCR_ITMENA_Pos                  0                                          /*!< ITM TCR: ITM Enable bit Position */
+#define ITM_TCR_ITMENA_Msk                 (1UL << ITM_TCR_ITMENA_Pos)                 /*!< ITM TCR: ITM Enable bit Mask */
+
+/*@}*/ /* end of group CMSIS_ITM */
+
+
+#if (__MPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_MPU CMSIS MPU
+  Type definitions for the Cortex-M Memory Protection Unit (MPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Memory Protection Unit (MPU).
+ */
+typedef struct
+{
+  __I  uint32_t TYPE;                    /*!< Offset: 0x000 (R/ )  MPU Type Register                              */
+  __IO uint32_t CTRL;                    /*!< Offset: 0x004 (R/W)  MPU Control Register                           */
+  __IO uint32_t RNR;                     /*!< Offset: 0x008 (R/W)  MPU Region RNRber Register                     */
+  __IO uint32_t RBAR;                    /*!< Offset: 0x00C (R/W)  MPU Region Base Address Register               */
+  __IO uint32_t RASR;                    /*!< Offset: 0x010 (R/W)  MPU Region Attribute and Size Register         */
+  __IO uint32_t RBAR_A1;                 /*!< Offset: 0x014 (R/W)  MPU Alias 1 Region Base Address Register       */
+  __IO uint32_t RASR_A1;                 /*!< Offset: 0x018 (R/W)  MPU Alias 1 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A2;                 /*!< Offset: 0x01C (R/W)  MPU Alias 2 Region Base Address Register       */
+  __IO uint32_t RASR_A2;                 /*!< Offset: 0x020 (R/W)  MPU Alias 2 Region Attribute and Size Register */
+  __IO uint32_t RBAR_A3;                 /*!< Offset: 0x024 (R/W)  MPU Alias 3 Region Base Address Register       */
+  __IO uint32_t RASR_A3;                 /*!< Offset: 0x028 (R/W)  MPU Alias 3 Region Attribute and Size Register */
+} MPU_Type;
+
+/* MPU Type Register */
+#define MPU_TYPE_IREGION_Pos               16                                             /*!< MPU TYPE: IREGION Position */
+#define MPU_TYPE_IREGION_Msk               (0xFFUL << MPU_TYPE_IREGION_Pos)               /*!< MPU TYPE: IREGION Mask */
+
+#define MPU_TYPE_DREGION_Pos                8                                             /*!< MPU TYPE: DREGION Position */
+#define MPU_TYPE_DREGION_Msk               (0xFFUL << MPU_TYPE_DREGION_Pos)               /*!< MPU TYPE: DREGION Mask */
+
+#define MPU_TYPE_SEPARATE_Pos               0                                             /*!< MPU TYPE: SEPARATE Position */
+#define MPU_TYPE_SEPARATE_Msk              (1UL << MPU_TYPE_SEPARATE_Pos)                 /*!< MPU TYPE: SEPARATE Mask */
+
+/* MPU Control Register */
+#define MPU_CTRL_PRIVDEFENA_Pos             2                                             /*!< MPU CTRL: PRIVDEFENA Position */
+#define MPU_CTRL_PRIVDEFENA_Msk            (1UL << MPU_CTRL_PRIVDEFENA_Pos)               /*!< MPU CTRL: PRIVDEFENA Mask */
+
+#define MPU_CTRL_HFNMIENA_Pos               1                                             /*!< MPU CTRL: HFNMIENA Position */
+#define MPU_CTRL_HFNMIENA_Msk              (1UL << MPU_CTRL_HFNMIENA_Pos)                 /*!< MPU CTRL: HFNMIENA Mask */
+
+#define MPU_CTRL_ENABLE_Pos                 0                                             /*!< MPU CTRL: ENABLE Position */
+#define MPU_CTRL_ENABLE_Msk                (1UL << MPU_CTRL_ENABLE_Pos)                   /*!< MPU CTRL: ENABLE Mask */
+
+/* MPU Region Number Register */
+#define MPU_RNR_REGION_Pos                  0                                             /*!< MPU RNR: REGION Position */
+#define MPU_RNR_REGION_Msk                 (0xFFUL << MPU_RNR_REGION_Pos)                 /*!< MPU RNR: REGION Mask */
+
+/* MPU Region Base Address Register */
+#define MPU_RBAR_ADDR_Pos                   5                                             /*!< MPU RBAR: ADDR Position */
+#define MPU_RBAR_ADDR_Msk                  (0x7FFFFFFUL << MPU_RBAR_ADDR_Pos)             /*!< MPU RBAR: ADDR Mask */
+
+#define MPU_RBAR_VALID_Pos                  4                                             /*!< MPU RBAR: VALID Position */
+#define MPU_RBAR_VALID_Msk                 (1UL << MPU_RBAR_VALID_Pos)                    /*!< MPU RBAR: VALID Mask */
+
+#define MPU_RBAR_REGION_Pos                 0                                             /*!< MPU RBAR: REGION Position */
+#define MPU_RBAR_REGION_Msk                (0xFUL << MPU_RBAR_REGION_Pos)                 /*!< MPU RBAR: REGION Mask */
+
+/* MPU Region Attribute and Size Register */
+#define MPU_RASR_ATTRS_Pos                 16                                             /*!< MPU RASR: MPU Region Attribute field Position */
+#define MPU_RASR_ATTRS_Msk                 (0xFFFFUL << MPU_RASR_ATTRS_Pos)               /*!< MPU RASR: MPU Region Attribute field Mask */
+
+#define MPU_RASR_SRD_Pos                    8                                             /*!< MPU RASR: Sub-Region Disable Position */
+#define MPU_RASR_SRD_Msk                   (0xFFUL << MPU_RASR_SRD_Pos)                   /*!< MPU RASR: Sub-Region Disable Mask */
+
+#define MPU_RASR_SIZE_Pos                   1                                             /*!< MPU RASR: Region Size Field Position */
+#define MPU_RASR_SIZE_Msk                  (0x1FUL << MPU_RASR_SIZE_Pos)                  /*!< MPU RASR: Region Size Field Mask */
+
+#define MPU_RASR_ENABLE_Pos                 0                                             /*!< MPU RASR: Region enable bit Position */
+#define MPU_RASR_ENABLE_Msk                (1UL << MPU_RASR_ENABLE_Pos)                   /*!< MPU RASR: Region enable bit Disable Mask */
+
+/*@} end of group CMSIS_MPU */
+#endif
+
+
+#if (__FPU_PRESENT == 1)
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_FPU CMSIS FPU
+  Type definitions for the Cortex-M Floating Point Unit (FPU)
+  @{
+ */
+
+/** \brief  Structure type to access the Floating Point Unit (FPU).
+ */
+typedef struct
+{
+       uint32_t RESERVED0[1];
+  __IO uint32_t FPCCR;                   /*!< Offset: 0x004 (R/W)  Floating-Point Context Control Register               */
+  __IO uint32_t FPCAR;                   /*!< Offset: 0x008 (R/W)  Floating-Point Context Address Register               */
+  __IO uint32_t FPDSCR;                  /*!< Offset: 0x00C (R/W)  Floating-Point Default Status Control Register        */
+  __I  uint32_t MVFR0;                   /*!< Offset: 0x010 (R/ )  Media and FP Feature Register 0                       */
+  __I  uint32_t MVFR1;                   /*!< Offset: 0x014 (R/ )  Media and FP Feature Register 1                       */
+} FPU_Type;
+
+/* Floating-Point Context Control Register */
+#define FPU_FPCCR_ASPEN_Pos                31                                             /*!< FPCCR: ASPEN bit Position */
+#define FPU_FPCCR_ASPEN_Msk                (1UL << FPU_FPCCR_ASPEN_Pos)                   /*!< FPCCR: ASPEN bit Mask */
+
+#define FPU_FPCCR_LSPEN_Pos                30                                             /*!< FPCCR: LSPEN Position */
+#define FPU_FPCCR_LSPEN_Msk                (1UL << FPU_FPCCR_LSPEN_Pos)                   /*!< FPCCR: LSPEN bit Mask */
+
+#define FPU_FPCCR_MONRDY_Pos                8                                             /*!< FPCCR: MONRDY Position */
+#define FPU_FPCCR_MONRDY_Msk               (1UL << FPU_FPCCR_MONRDY_Pos)                  /*!< FPCCR: MONRDY bit Mask */
+
+#define FPU_FPCCR_BFRDY_Pos                 6                                             /*!< FPCCR: BFRDY Position */
+#define FPU_FPCCR_BFRDY_Msk                (1UL << FPU_FPCCR_BFRDY_Pos)                   /*!< FPCCR: BFRDY bit Mask */
+
+#define FPU_FPCCR_MMRDY_Pos                 5                                             /*!< FPCCR: MMRDY Position */
+#define FPU_FPCCR_MMRDY_Msk                (1UL << FPU_FPCCR_MMRDY_Pos)                   /*!< FPCCR: MMRDY bit Mask */
+
+#define FPU_FPCCR_HFRDY_Pos                 4                                             /*!< FPCCR: HFRDY Position */
+#define FPU_FPCCR_HFRDY_Msk                (1UL << FPU_FPCCR_HFRDY_Pos)                   /*!< FPCCR: HFRDY bit Mask */
+
+#define FPU_FPCCR_THREAD_Pos                3                                             /*!< FPCCR: processor mode bit Position */
+#define FPU_FPCCR_THREAD_Msk               (1UL << FPU_FPCCR_THREAD_Pos)                  /*!< FPCCR: processor mode active bit Mask */
+
+#define FPU_FPCCR_USER_Pos                  1                                             /*!< FPCCR: privilege level bit Position */
+#define FPU_FPCCR_USER_Msk                 (1UL << FPU_FPCCR_USER_Pos)                    /*!< FPCCR: privilege level bit Mask */
+
+#define FPU_FPCCR_LSPACT_Pos                0                                             /*!< FPCCR: Lazy state preservation active bit Position */
+#define FPU_FPCCR_LSPACT_Msk               (1UL << FPU_FPCCR_LSPACT_Pos)                  /*!< FPCCR: Lazy state preservation active bit Mask */
+
+/* Floating-Point Context Address Register */
+#define FPU_FPCAR_ADDRESS_Pos               3                                             /*!< FPCAR: ADDRESS bit Position */
+#define FPU_FPCAR_ADDRESS_Msk              (0x1FFFFFFFUL << FPU_FPCAR_ADDRESS_Pos)        /*!< FPCAR: ADDRESS bit Mask */
+
+/* Floating-Point Default Status Control Register */
+#define FPU_FPDSCR_AHP_Pos                 26                                             /*!< FPDSCR: AHP bit Position */
+#define FPU_FPDSCR_AHP_Msk                 (1UL << FPU_FPDSCR_AHP_Pos)                    /*!< FPDSCR: AHP bit Mask */
+
+#define FPU_FPDSCR_DN_Pos                  25                                             /*!< FPDSCR: DN bit Position */
+#define FPU_FPDSCR_DN_Msk                  (1UL << FPU_FPDSCR_DN_Pos)                     /*!< FPDSCR: DN bit Mask */
+
+#define FPU_FPDSCR_FZ_Pos                  24                                             /*!< FPDSCR: FZ bit Position */
+#define FPU_FPDSCR_FZ_Msk                  (1UL << FPU_FPDSCR_FZ_Pos)                     /*!< FPDSCR: FZ bit Mask */
+
+#define FPU_FPDSCR_RMode_Pos               22                                             /*!< FPDSCR: RMode bit Position */
+#define FPU_FPDSCR_RMode_Msk               (3UL << FPU_FPDSCR_RMode_Pos)                  /*!< FPDSCR: RMode bit Mask */
+
+/* Media and FP Feature Register 0 */
+#define FPU_MVFR0_FP_rounding_modes_Pos    28                                             /*!< MVFR0: FP rounding modes bits Position */
+#define FPU_MVFR0_FP_rounding_modes_Msk    (0xFUL << FPU_MVFR0_FP_rounding_modes_Pos)     /*!< MVFR0: FP rounding modes bits Mask */
+
+#define FPU_MVFR0_Short_vectors_Pos        24                                             /*!< MVFR0: Short vectors bits Position */
+#define FPU_MVFR0_Short_vectors_Msk        (0xFUL << FPU_MVFR0_Short_vectors_Pos)         /*!< MVFR0: Short vectors bits Mask */
+
+#define FPU_MVFR0_Square_root_Pos          20                                             /*!< MVFR0: Square root bits Position */
+#define FPU_MVFR0_Square_root_Msk          (0xFUL << FPU_MVFR0_Square_root_Pos)           /*!< MVFR0: Square root bits Mask */
+
+#define FPU_MVFR0_Divide_Pos               16                                             /*!< MVFR0: Divide bits Position */
+#define FPU_MVFR0_Divide_Msk               (0xFUL << FPU_MVFR0_Divide_Pos)                /*!< MVFR0: Divide bits Mask */
+
+#define FPU_MVFR0_FP_excep_trapping_Pos    12                                             /*!< MVFR0: FP exception trapping bits Position */
+#define FPU_MVFR0_FP_excep_trapping_Msk    (0xFUL << FPU_MVFR0_FP_excep_trapping_Pos)     /*!< MVFR0: FP exception trapping bits Mask */
+
+#define FPU_MVFR0_Double_precision_Pos      8                                             /*!< MVFR0: Double-precision bits Position */
+#define FPU_MVFR0_Double_precision_Msk     (0xFUL << FPU_MVFR0_Double_precision_Pos)      /*!< MVFR0: Double-precision bits Mask */
+
+#define FPU_MVFR0_Single_precision_Pos      4                                             /*!< MVFR0: Single-precision bits Position */
+#define FPU_MVFR0_Single_precision_Msk     (0xFUL << FPU_MVFR0_Single_precision_Pos)      /*!< MVFR0: Single-precision bits Mask */
+
+#define FPU_MVFR0_A_SIMD_registers_Pos      0                                             /*!< MVFR0: A_SIMD registers bits Position */
+#define FPU_MVFR0_A_SIMD_registers_Msk     (0xFUL << FPU_MVFR0_A_SIMD_registers_Pos)      /*!< MVFR0: A_SIMD registers bits Mask */
+
+/* Media and FP Feature Register 1 */
+#define FPU_MVFR1_FP_fused_MAC_Pos         28                                             /*!< MVFR1: FP fused MAC bits Position */
+#define FPU_MVFR1_FP_fused_MAC_Msk         (0xFUL << FPU_MVFR1_FP_fused_MAC_Pos)          /*!< MVFR1: FP fused MAC bits Mask */
+
+#define FPU_MVFR1_FP_HPFP_Pos              24                                             /*!< MVFR1: FP HPFP bits Position */
+#define FPU_MVFR1_FP_HPFP_Msk              (0xFUL << FPU_MVFR1_FP_HPFP_Pos)               /*!< MVFR1: FP HPFP bits Mask */
+
+#define FPU_MVFR1_D_NaN_mode_Pos            4                                             /*!< MVFR1: D_NaN mode bits Position */
+#define FPU_MVFR1_D_NaN_mode_Msk           (0xFUL << FPU_MVFR1_D_NaN_mode_Pos)            /*!< MVFR1: D_NaN mode bits Mask */
+
+#define FPU_MVFR1_FtZ_mode_Pos              0                                             /*!< MVFR1: FtZ mode bits Position */
+#define FPU_MVFR1_FtZ_mode_Msk             (0xFUL << FPU_MVFR1_FtZ_mode_Pos)              /*!< MVFR1: FtZ mode bits Mask */
+
+/*@} end of group CMSIS_FPU */
+#endif
+
+
+/** \ingroup  CMSIS_core_register
+    \defgroup CMSIS_CoreDebug CMSIS Core Debug
+  Type definitions for the Cortex-M Core Debug Registers
+  @{
+ */
+
+/** \brief  Structure type to access the Core Debug Register (CoreDebug).
+ */
+typedef struct
+{
+  __IO uint32_t DHCSR;                   /*!< Offset: 0x000 (R/W)  Debug Halting Control and Status Register    */
+  __O  uint32_t DCRSR;                   /*!< Offset: 0x004 ( /W)  Debug Core Register Selector Register        */
+  __IO uint32_t DCRDR;                   /*!< Offset: 0x008 (R/W)  Debug Core Register Data Register            */
+  __IO uint32_t DEMCR;                   /*!< Offset: 0x00C (R/W)  Debug Exception and Monitor Control Register */
+} CoreDebug_Type;
+
+/* Debug Halting Control and Status Register */
+#define CoreDebug_DHCSR_DBGKEY_Pos         16                                             /*!< CoreDebug DHCSR: DBGKEY Position */
+#define CoreDebug_DHCSR_DBGKEY_Msk         (0xFFFFUL << CoreDebug_DHCSR_DBGKEY_Pos)       /*!< CoreDebug DHCSR: DBGKEY Mask */
+
+#define CoreDebug_DHCSR_S_RESET_ST_Pos     25                                             /*!< CoreDebug DHCSR: S_RESET_ST Position */
+#define CoreDebug_DHCSR_S_RESET_ST_Msk     (1UL << CoreDebug_DHCSR_S_RESET_ST_Pos)        /*!< CoreDebug DHCSR: S_RESET_ST Mask */
+
+#define CoreDebug_DHCSR_S_RETIRE_ST_Pos    24                                             /*!< CoreDebug DHCSR: S_RETIRE_ST Position */
+#define CoreDebug_DHCSR_S_RETIRE_ST_Msk    (1UL << CoreDebug_DHCSR_S_RETIRE_ST_Pos)       /*!< CoreDebug DHCSR: S_RETIRE_ST Mask */
+
+#define CoreDebug_DHCSR_S_LOCKUP_Pos       19                                             /*!< CoreDebug DHCSR: S_LOCKUP Position */
+#define CoreDebug_DHCSR_S_LOCKUP_Msk       (1UL << CoreDebug_DHCSR_S_LOCKUP_Pos)          /*!< CoreDebug DHCSR: S_LOCKUP Mask */
+
+#define CoreDebug_DHCSR_S_SLEEP_Pos        18                                             /*!< CoreDebug DHCSR: S_SLEEP Position */
+#define CoreDebug_DHCSR_S_SLEEP_Msk        (1UL << CoreDebug_DHCSR_S_SLEEP_Pos)           /*!< CoreDebug DHCSR: S_SLEEP Mask */
+
+#define CoreDebug_DHCSR_S_HALT_Pos         17                                             /*!< CoreDebug DHCSR: S_HALT Position */
+#define CoreDebug_DHCSR_S_HALT_Msk         (1UL << CoreDebug_DHCSR_S_HALT_Pos)            /*!< CoreDebug DHCSR: S_HALT Mask */
+
+#define CoreDebug_DHCSR_S_REGRDY_Pos       16                                             /*!< CoreDebug DHCSR: S_REGRDY Position */
+#define CoreDebug_DHCSR_S_REGRDY_Msk       (1UL << CoreDebug_DHCSR_S_REGRDY_Pos)          /*!< CoreDebug DHCSR: S_REGRDY Mask */
+
+#define CoreDebug_DHCSR_C_SNAPSTALL_Pos     5                                             /*!< CoreDebug DHCSR: C_SNAPSTALL Position */
+#define CoreDebug_DHCSR_C_SNAPSTALL_Msk    (1UL << CoreDebug_DHCSR_C_SNAPSTALL_Pos)       /*!< CoreDebug DHCSR: C_SNAPSTALL Mask */
+
+#define CoreDebug_DHCSR_C_MASKINTS_Pos      3                                             /*!< CoreDebug DHCSR: C_MASKINTS Position */
+#define CoreDebug_DHCSR_C_MASKINTS_Msk     (1UL << CoreDebug_DHCSR_C_MASKINTS_Pos)        /*!< CoreDebug DHCSR: C_MASKINTS Mask */
+
+#define CoreDebug_DHCSR_C_STEP_Pos          2                                             /*!< CoreDebug DHCSR: C_STEP Position */
+#define CoreDebug_DHCSR_C_STEP_Msk         (1UL << CoreDebug_DHCSR_C_STEP_Pos)            /*!< CoreDebug DHCSR: C_STEP Mask */
+
+#define CoreDebug_DHCSR_C_HALT_Pos          1                                             /*!< CoreDebug DHCSR: C_HALT Position */
+#define CoreDebug_DHCSR_C_HALT_Msk         (1UL << CoreDebug_DHCSR_C_HALT_Pos)            /*!< CoreDebug DHCSR: C_HALT Mask */
+
+#define CoreDebug_DHCSR_C_DEBUGEN_Pos       0                                             /*!< CoreDebug DHCSR: C_DEBUGEN Position */
+#define CoreDebug_DHCSR_C_DEBUGEN_Msk      (1UL << CoreDebug_DHCSR_C_DEBUGEN_Pos)         /*!< CoreDebug DHCSR: C_DEBUGEN Mask */
+
+/* Debug Core Register Selector Register */
+#define CoreDebug_DCRSR_REGWnR_Pos         16                                             /*!< CoreDebug DCRSR: REGWnR Position */
+#define CoreDebug_DCRSR_REGWnR_Msk         (1UL << CoreDebug_DCRSR_REGWnR_Pos)            /*!< CoreDebug DCRSR: REGWnR Mask */
+
+#define CoreDebug_DCRSR_REGSEL_Pos          0                                             /*!< CoreDebug DCRSR: REGSEL Position */
+#define CoreDebug_DCRSR_REGSEL_Msk         (0x1FUL << CoreDebug_DCRSR_REGSEL_Pos)         /*!< CoreDebug DCRSR: REGSEL Mask */
+
+/* Debug Exception and Monitor Control Register */
+#define CoreDebug_DEMCR_TRCENA_Pos         24                                             /*!< CoreDebug DEMCR: TRCENA Position */
+#define CoreDebug_DEMCR_TRCENA_Msk         (1UL << CoreDebug_DEMCR_TRCENA_Pos)            /*!< CoreDebug DEMCR: TRCENA Mask */
+
+#define CoreDebug_DEMCR_MON_REQ_Pos        19                                             /*!< CoreDebug DEMCR: MON_REQ Position */
+#define CoreDebug_DEMCR_MON_REQ_Msk        (1UL << CoreDebug_DEMCR_MON_REQ_Pos)           /*!< CoreDebug DEMCR: MON_REQ Mask */
+
+#define CoreDebug_DEMCR_MON_STEP_Pos       18                                             /*!< CoreDebug DEMCR: MON_STEP Position */
+#define CoreDebug_DEMCR_MON_STEP_Msk       (1UL << CoreDebug_DEMCR_MON_STEP_Pos)          /*!< CoreDebug DEMCR: MON_STEP Mask */
+
+#define CoreDebug_DEMCR_MON_PEND_Pos       17                                             /*!< CoreDebug DEMCR: MON_PEND Position */
+#define CoreDebug_DEMCR_MON_PEND_Msk       (1UL << CoreDebug_DEMCR_MON_PEND_Pos)          /*!< CoreDebug DEMCR: MON_PEND Mask */
+
+#define CoreDebug_DEMCR_MON_EN_Pos         16                                             /*!< CoreDebug DEMCR: MON_EN Position */
+#define CoreDebug_DEMCR_MON_EN_Msk         (1UL << CoreDebug_DEMCR_MON_EN_Pos)            /*!< CoreDebug DEMCR: MON_EN Mask */
+
+#define CoreDebug_DEMCR_VC_HARDERR_Pos     10                                             /*!< CoreDebug DEMCR: VC_HARDERR Position */
+#define CoreDebug_DEMCR_VC_HARDERR_Msk     (1UL << CoreDebug_DEMCR_VC_HARDERR_Pos)        /*!< CoreDebug DEMCR: VC_HARDERR Mask */
+
+#define CoreDebug_DEMCR_VC_INTERR_Pos       9                                             /*!< CoreDebug DEMCR: VC_INTERR Position */
+#define CoreDebug_DEMCR_VC_INTERR_Msk      (1UL << CoreDebug_DEMCR_VC_INTERR_Pos)         /*!< CoreDebug DEMCR: VC_INTERR Mask */
+
+#define CoreDebug_DEMCR_VC_BUSERR_Pos       8                                             /*!< CoreDebug DEMCR: VC_BUSERR Position */
+#define CoreDebug_DEMCR_VC_BUSERR_Msk      (1UL << CoreDebug_DEMCR_VC_BUSERR_Pos)         /*!< CoreDebug DEMCR: VC_BUSERR Mask */
+
+#define CoreDebug_DEMCR_VC_STATERR_Pos      7                                             /*!< CoreDebug DEMCR: VC_STATERR Position */
+#define CoreDebug_DEMCR_VC_STATERR_Msk     (1UL << CoreDebug_DEMCR_VC_STATERR_Pos)        /*!< CoreDebug DEMCR: VC_STATERR Mask */
+
+#define CoreDebug_DEMCR_VC_CHKERR_Pos       6                                             /*!< CoreDebug DEMCR: VC_CHKERR Position */
+#define CoreDebug_DEMCR_VC_CHKERR_Msk      (1UL << CoreDebug_DEMCR_VC_CHKERR_Pos)         /*!< CoreDebug DEMCR: VC_CHKERR Mask */
+
+#define CoreDebug_DEMCR_VC_NOCPERR_Pos      5                                             /*!< CoreDebug DEMCR: VC_NOCPERR Position */
+#define CoreDebug_DEMCR_VC_NOCPERR_Msk     (1UL << CoreDebug_DEMCR_VC_NOCPERR_Pos)        /*!< CoreDebug DEMCR: VC_NOCPERR Mask */
+
+#define CoreDebug_DEMCR_VC_MMERR_Pos        4                                             /*!< CoreDebug DEMCR: VC_MMERR Position */
+#define CoreDebug_DEMCR_VC_MMERR_Msk       (1UL << CoreDebug_DEMCR_VC_MMERR_Pos)          /*!< CoreDebug DEMCR: VC_MMERR Mask */
+
+#define CoreDebug_DEMCR_VC_CORERESET_Pos    0                                             /*!< CoreDebug DEMCR: VC_CORERESET Position */
+#define CoreDebug_DEMCR_VC_CORERESET_Msk   (1UL << CoreDebug_DEMCR_VC_CORERESET_Pos)      /*!< CoreDebug DEMCR: VC_CORERESET Mask */
+
+/*@} end of group CMSIS_CoreDebug */
+
+
+/** \ingroup  CMSIS_core_register
+  @{
+ */
+
+/* Memory mapping of Cortex-M4 Hardware */
+#define SCS_BASE            (0xE000E000UL)                            /*!< System Control Space Base Address  */
+#define ITM_BASE            (0xE0000000UL)                            /*!< ITM Base Address                   */
+#define CoreDebug_BASE      (0xE000EDF0UL)                            /*!< Core Debug Base Address            */
+#define SysTick_BASE        (SCS_BASE +  0x0010UL)                    /*!< SysTick Base Address               */
+#define NVIC_BASE           (SCS_BASE +  0x0100UL)                    /*!< NVIC Base Address                  */
+#define SCB_BASE            (SCS_BASE +  0x0D00UL)                    /*!< System Control Block Base Address  */
+
+#define SCnSCB              ((SCnSCB_Type    *)     SCS_BASE      )   /*!< System control Register not in SCB */
+#define SCB                 ((SCB_Type       *)     SCB_BASE      )   /*!< SCB configuration struct           */
+#define SysTick             ((SysTick_Type   *)     SysTick_BASE  )   /*!< SysTick configuration struct       */
+#define NVIC                ((NVIC_Type      *)     NVIC_BASE     )   /*!< NVIC configuration struct          */
+#define ITM                 ((ITM_Type       *)     ITM_BASE      )   /*!< ITM configuration struct           */
+#define CoreDebug           ((CoreDebug_Type *)     CoreDebug_BASE)   /*!< Core Debug configuration struct    */
+
+#if (__MPU_PRESENT == 1)
+  #define MPU_BASE          (SCS_BASE +  0x0D90UL)                    /*!< Memory Protection Unit             */
+  #define MPU               ((MPU_Type       *)     MPU_BASE      )   /*!< Memory Protection Unit             */
+#endif
+
+#if (__FPU_PRESENT == 1)
+  #define FPU_BASE          (SCS_BASE +  0x0F30UL)                    /*!< Floating Point Unit                */
+  #define FPU               ((FPU_Type       *)     FPU_BASE      )   /*!< Floating Point Unit                */
+#endif
+
+/*@} */
+
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+/** \defgroup CMSIS_Core_FunctionInterface CMSIS Core Function Interface
+  Core Function Interface contains:
+  - Core NVIC Functions
+  - Core SysTick Functions
+  - Core Debug Functions
+  - Core Register Access Functions
+*/
+
+
+
+/* ##########################   NVIC functions  #################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_NVICFunctions CMSIS Core NVIC Functions
+  @{
+ */
+
+/** \brief  Set Priority Grouping
+
+  This function sets the priority grouping field using the required unlock sequence.
+  The parameter PriorityGroup is assigned to the field SCB->AIRCR [10:8] PRIGROUP field.
+  Only values from 0..7 are used.
+  In case of a conflict between priority grouping and available
+  priority bits (__NVIC_PRIO_BITS) the smallest possible priority group is set.
+
+    \param [in]      PriorityGroup  Priority grouping field
+ */
+static __INLINE void NVIC_SetPriorityGrouping(uint32_t PriorityGroup)
+{
+  uint32_t reg_value;
+  uint32_t PriorityGroupTmp = (PriorityGroup & (uint32_t)0x07);               /* only values 0..7 are used          */
+
+  reg_value  =  SCB->AIRCR;                                                   /* read old register configuration    */
+  reg_value &= ~(SCB_AIRCR_VECTKEY_Msk | SCB_AIRCR_PRIGROUP_Msk);             /* clear bits to change               */
+  reg_value  =  (reg_value                                 |
+                ((uint32_t)0x5FA << SCB_AIRCR_VECTKEY_Pos) |
+                (PriorityGroupTmp << 8));                                     /* Insert write key and priorty group */
+  SCB->AIRCR =  reg_value;
+}
+
+
+/** \brief  Get Priority Grouping
+
+  This function gets the priority grouping from NVIC Interrupt Controller.
+  Priority grouping is SCB->AIRCR [10:8] PRIGROUP field.
+
+    \return                Priority grouping field
+ */
+static __INLINE uint32_t NVIC_GetPriorityGrouping(void)
+{
+  return ((SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) >> SCB_AIRCR_PRIGROUP_Pos);   /* read priority grouping field */
+}
+
+
+/** \brief  Enable External Interrupt
+
+    This function enables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to enable
+ */
+static __INLINE void NVIC_EnableIRQ(IRQn_Type IRQn)
+{
+/*  NVIC->ISER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F));  enable interrupt */
+  NVIC->ISER[(uint32_t)((int32_t)IRQn) >> 5] = (uint32_t)(1 << ((uint32_t)((int32_t)IRQn) & (uint32_t)0x1F)); /* enable interrupt */
+}
+
+
+/** \brief  Disable External Interrupt
+
+    This function disables a device specific interrupt in the NVIC interrupt controller.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the external interrupt to disable
+ */
+static __INLINE void NVIC_DisableIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICER[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* disable interrupt */
+}
+
+
+/** \brief  Get Pending Interrupt
+
+    This function reads the pending register in the NVIC and returns the pending bit
+    for the specified interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for get pending
+    \return             0  Interrupt status is not pending
+    \return             1  Interrupt status is pending
+ */
+static __INLINE uint32_t NVIC_GetPendingIRQ(IRQn_Type IRQn)
+{
+  return((uint32_t) ((NVIC->ISPR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if pending else 0 */
+}
+
+
+/** \brief  Set Pending Interrupt
+
+    This function sets the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for set pending
+ */
+static __INLINE void NVIC_SetPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ISPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* set interrupt pending */
+}
+
+
+/** \brief  Clear Pending Interrupt
+
+    This function clears the pending bit for the specified interrupt.
+    The interrupt number cannot be a negative value.
+
+    \param [in]      IRQn  Number of the interrupt for clear pending
+ */
+static __INLINE void NVIC_ClearPendingIRQ(IRQn_Type IRQn)
+{
+  NVIC->ICPR[((uint32_t)(IRQn) >> 5)] = (1 << ((uint32_t)(IRQn) & 0x1F)); /* Clear pending interrupt */
+}
+
+
+/** \brief  Get Active Interrupt
+
+    This function reads the active register in NVIC and returns the active bit.
+    \param [in]      IRQn  Number of the interrupt for get active
+    \return             0  Interrupt status is not active
+    \return             1  Interrupt status is active
+ */
+static __INLINE uint32_t NVIC_GetActive(IRQn_Type IRQn)
+{
+  return((uint32_t)((NVIC->IABR[(uint32_t)(IRQn) >> 5] & (1 << ((uint32_t)(IRQn) & 0x1F)))?1:0)); /* Return 1 if active else 0 */
+}
+
+
+/** \brief  Set Interrupt Priority
+
+    This function sets the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    Note: The priority cannot be set for every core interrupt.
+
+    \param [in]      IRQn  Number of the interrupt for set priority
+    \param [in]  priority  Priority to set
+ */
+static __INLINE void NVIC_SetPriority(IRQn_Type IRQn, uint32_t priority)
+{
+  if(IRQn < 0) {
+    SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff); } /* set Priority for Cortex-M  System Interrupts */
+  else {
+    NVIC->IP[(uint32_t)(IRQn)] = ((priority << (8 - __NVIC_PRIO_BITS)) & 0xff);    }        /* set Priority for device specific Interrupts  */
+}
+
+
+/** \brief  Get Interrupt Priority
+
+    This function reads the priority for the specified interrupt. The interrupt
+    number can be positive to specify an external (device specific)
+    interrupt, or negative to specify an internal (core) interrupt.
+
+    The returned priority value is automatically aligned to the implemented
+    priority bits of the microcontroller.
+
+    \param [in]   IRQn  Number of the interrupt for get priority
+    \return             Interrupt Priority
+ */
+static __INLINE uint32_t NVIC_GetPriority(IRQn_Type IRQn)
+{
+
+  if(IRQn < 0) {
+    return((uint32_t)(SCB->SHP[((uint32_t)(IRQn) & 0xF)-4] >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for Cortex-M  system interrupts */
+  else {
+    return((uint32_t)(NVIC->IP[(uint32_t)(IRQn)]           >> (8 - __NVIC_PRIO_BITS)));  } /* get priority for device specific interrupts  */
+}
+
+
+/** \brief  Encode Priority
+
+    This function encodes the priority for an interrupt with the given priority group,
+    preemptive priority value and sub priority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    The returned priority value can be used for NVIC_SetPriority(...) function
+
+    \param [in]     PriorityGroup  Used priority group
+    \param [in]   PreemptPriority  Preemptive priority value (starting from 0)
+    \param [in]       SubPriority  Sub priority value (starting from 0)
+    \return                        Encoded priority for the interrupt
+ */
+static __INLINE uint32_t NVIC_EncodePriority (uint32_t PriorityGroup, uint32_t PreemptPriority, uint32_t SubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  return (
+           ((PreemptPriority & ((1 << (PreemptPriorityBits)) - 1)) << SubPriorityBits) |
+           ((SubPriority     & ((1 << (SubPriorityBits    )) - 1)))
+         );
+}
+
+
+/** \brief  Decode Priority
+
+    This function decodes an interrupt priority value with the given priority group to
+    preemptive priority value and sub priority value.
+    In case of a conflict between priority grouping and available
+    priority bits (__NVIC_PRIO_BITS) the samllest possible priority group is set.
+
+    The priority value can be retrieved with NVIC_GetPriority(...) function
+
+    \param [in]         Priority   Priority value
+    \param [in]     PriorityGroup  Used priority group
+    \param [out] pPreemptPriority  Preemptive priority value (starting from 0)
+    \param [out]     pSubPriority  Sub priority value (starting from 0)
+ */
+static __INLINE void NVIC_DecodePriority (uint32_t Priority, uint32_t PriorityGroup, uint32_t* pPreemptPriority, uint32_t* pSubPriority)
+{
+  uint32_t PriorityGroupTmp = (PriorityGroup & 0x07);          /* only values 0..7 are used          */
+  uint32_t PreemptPriorityBits;
+  uint32_t SubPriorityBits;
+
+  PreemptPriorityBits = ((7 - PriorityGroupTmp) > __NVIC_PRIO_BITS) ? __NVIC_PRIO_BITS : 7 - PriorityGroupTmp;
+  SubPriorityBits     = ((PriorityGroupTmp + __NVIC_PRIO_BITS) < 7) ? 0 : PriorityGroupTmp - 7 + __NVIC_PRIO_BITS;
+
+  *pPreemptPriority = (Priority >> SubPriorityBits) & ((1 << (PreemptPriorityBits)) - 1);
+  *pSubPriority     = (Priority                   ) & ((1 << (SubPriorityBits    )) - 1);
+}
+
+
+/** \brief  System Reset
+
+    This function initiate a system reset request to reset the MCU.
+ */
+static __INLINE void NVIC_SystemReset(void)
+{
+  __DSB();                                                     /* Ensure all outstanding memory accesses included
+                                                                  buffered write are completed before reset */
+  SCB->AIRCR  = ((0x5FA << SCB_AIRCR_VECTKEY_Pos)      |
+                 (SCB->AIRCR & SCB_AIRCR_PRIGROUP_Msk) |
+                 SCB_AIRCR_SYSRESETREQ_Msk);                   /* Keep priority group unchanged */
+  __DSB();                                                     /* Ensure completion of memory access */
+  while(1);                                                    /* wait until reset */
+}
+
+/*@} end of CMSIS_Core_NVICFunctions */
+
+
+
+/* ##################################    SysTick function  ############################################ */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_Core_SysTickFunctions CMSIS Core SysTick Functions
+  @{
+ */
+
+#if (__Vendor_SysTickConfig == 0)
+
+/** \brief  System Tick Configuration
+
+    This function initialises the system tick timer and its interrupt and start the system tick timer.
+    Counter is in free running mode to generate periodical interrupts.
+
+    \param [in]  ticks  Number of ticks between two interrupts
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+static __INLINE uint32_t SysTick_Config(uint32_t ticks)
+{
+  if (ticks > SysTick_LOAD_RELOAD_Msk)  return (1);            /* Reload value impossible */
+
+  SysTick->LOAD  = (ticks & SysTick_LOAD_RELOAD_Msk) - 1;      /* set reload register */
+  NVIC_SetPriority (SysTick_IRQn, (1<<__NVIC_PRIO_BITS) - 1);  /* set Priority for Cortex-M0 System Interrupts */
+  SysTick->VAL   = 0;                                          /* Load the SysTick Counter Value */
+  SysTick->CTRL  = SysTick_CTRL_CLKSOURCE_Msk |
+                   SysTick_CTRL_TICKINT_Msk   |
+                   SysTick_CTRL_ENABLE_Msk;                    /* Enable SysTick IRQ and SysTick Timer */
+  return (0);                                                  /* Function successful */
+}
+
+#endif
+
+/*@} end of CMSIS_Core_SysTickFunctions */
+
+
+
+/* ##################################### Debug In/Output function ########################################### */
+/** \ingroup  CMSIS_Core_FunctionInterface
+    \defgroup CMSIS_core_DebugFunctions CMSIS Core Debug Functions
+  @{
+ */
+
+extern volatile int32_t ITM_RxBuffer;                    /*!< external variable to receive characters                    */
+#define                 ITM_RXBUFFER_EMPTY    0x5AA55AA5 /*!< value identifying ITM_RxBuffer is ready for next character */
+
+
+/** \brief  ITM Send Character
+
+    This function transmits a character via the ITM channel 0.
+    It just returns when no debugger is connected that has booked the output.
+    It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+    \param [in]     ch  Character to transmit
+    \return             Character to transmit
+ */
+static __INLINE uint32_t ITM_SendChar (uint32_t ch)
+{
+  if ((CoreDebug->DEMCR & CoreDebug_DEMCR_TRCENA_Msk)  &&      /* Trace enabled */
+      (ITM->TCR & ITM_TCR_ITMENA_Msk)                  &&      /* ITM enabled */
+      (ITM->TER & (1UL << 0)        )                    )     /* ITM Port #0 enabled */
+  {
+    while (ITM->PORT[0].u32 == 0);
+    ITM->PORT[0].u8 = (uint8_t) ch;
+  }
+  return (ch);
+}
+
+
+/** \brief  ITM Receive Character
+
+    This function inputs a character via external variable ITM_RxBuffer.
+    It just returns when no debugger is connected that has booked the output.
+    It is blocking when a debugger is connected, but the previous character send is not transmitted.
+
+    \return             Received character
+    \return         -1  No character received
+ */
+static __INLINE int32_t ITM_ReceiveChar (void) {
+  int32_t ch = -1;                           /* no character available */
+
+  if (ITM_RxBuffer != ITM_RXBUFFER_EMPTY) {
+    ch = ITM_RxBuffer;
+    ITM_RxBuffer = ITM_RXBUFFER_EMPTY;       /* ready for next character */
+  }
+
+  return (ch);
+}
+
+
+/** \brief  ITM Check Character
+
+    This function checks external variable ITM_RxBuffer whether a character is available or not.
+    It returns '1' if a character is available and '0' if no character is available.
+
+    \return          0  No character available
+    \return          1  Character available
+ */
+static __INLINE int32_t ITM_CheckChar (void) {
+
+  if (ITM_RxBuffer == ITM_RXBUFFER_EMPTY) {
+    return (0);                                 /* no character available */
+  } else {
+    return (1);                                 /*    character available */
+  }
+}
+
+/*@} end of CMSIS_core_DebugFunctions */
+
+#endif /* __CORE_CM4_H_DEPENDANT */
+
+#endif /* __CMSIS_GENERIC */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/stm32f40x/Libraries/CMSIS/Include/core_cm4_simd.h b/bsp/stm32f40x/Libraries/CMSIS/Include/core_cm4_simd.h
new file mode 100644
index 0000000000..479188696b
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/Include/core_cm4_simd.h
@@ -0,0 +1,701 @@
+/**************************************************************************//**
+ * @file     core_cm4_simd.h
+ * @brief    CMSIS Cortex-M4 SIMD Header File
+ * @version  V2.10
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2010-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+#ifndef __CORE_CM4_SIMD_H
+#define __CORE_CM4_SIMD_H
+
+
+/*******************************************************************************
+ *                Hardware Abstraction Layer
+ ******************************************************************************/
+
+
+/* ###################  Compiler specific Intrinsics  ########################### */
+/** \defgroup CMSIS_SIMD_intrinsics CMSIS SIMD Intrinsics
+  Access to dedicated SIMD instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+/*------ CM4 SOMD Intrinsics -----------------------------------------------------*/
+#define __SADD8                           __sadd8
+#define __QADD8                           __qadd8
+#define __SHADD8                          __shadd8
+#define __UADD8                           __uadd8
+#define __UQADD8                          __uqadd8
+#define __UHADD8                          __uhadd8
+#define __SSUB8                           __ssub8
+#define __QSUB8                           __qsub8
+#define __SHSUB8                          __shsub8
+#define __USUB8                           __usub8
+#define __UQSUB8                          __uqsub8
+#define __UHSUB8                          __uhsub8
+#define __SADD16                          __sadd16
+#define __QADD16                          __qadd16
+#define __SHADD16                         __shadd16
+#define __UADD16                          __uadd16
+#define __UQADD16                         __uqadd16
+#define __UHADD16                         __uhadd16
+#define __SSUB16                          __ssub16
+#define __QSUB16                          __qsub16
+#define __SHSUB16                         __shsub16
+#define __USUB16                          __usub16
+#define __UQSUB16                         __uqsub16
+#define __UHSUB16                         __uhsub16
+#define __SASX                            __sasx
+#define __QASX                            __qasx
+#define __SHASX                           __shasx
+#define __UASX                            __uasx
+#define __UQASX                           __uqasx
+#define __UHASX                           __uhasx
+#define __SSAX                            __ssax
+#define __QSAX                            __qsax
+#define __SHSAX                           __shsax
+#define __USAX                            __usax
+#define __UQSAX                           __uqsax
+#define __UHSAX                           __uhsax
+#define __USAD8                           __usad8
+#define __USADA8                          __usada8
+#define __SSAT16                          __ssat16
+#define __USAT16                          __usat16
+#define __UXTB16                          __uxtb16
+#define __UXTAB16                         __uxtab16
+#define __SXTB16                          __sxtb16
+#define __SXTAB16                         __sxtab16
+#define __SMUAD                           __smuad
+#define __SMUADX                          __smuadx
+#define __SMLAD                           __smlad
+#define __SMLADX                          __smladx
+#define __SMLALD                          __smlald
+#define __SMLALDX                         __smlaldx
+#define __SMUSD                           __smusd
+#define __SMUSDX                          __smusdx
+#define __SMLSD                           __smlsd
+#define __SMLSDX                          __smlsdx
+#define __SMLSLD                          __smlsld
+#define __SMLSLDX                         __smlsldx
+#define __SEL                             __sel
+#define __QADD                            __qadd
+#define __QSUB                            __qsub
+
+#define __PKHBT(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0x0000FFFFUL) |  \
+                                           ((((uint32_t)(ARG2)) << (ARG3)) & 0xFFFF0000UL)  )
+
+#define __PKHTB(ARG1,ARG2,ARG3)          ( ((((uint32_t)(ARG1))          ) & 0xFFFF0000UL) |  \
+                                           ((((uint32_t)(ARG2)) >> (ARG3)) & 0x0000FFFFUL)  )
+
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include 
+
+/*------ CM4 SIMDDSP Intrinsics -----------------------------------------------------*/
+/* intrinsic __SADD8      see intrinsics.h */
+/* intrinsic __QADD8      see intrinsics.h */
+/* intrinsic __SHADD8     see intrinsics.h */
+/* intrinsic __UADD8      see intrinsics.h */
+/* intrinsic __UQADD8     see intrinsics.h */
+/* intrinsic __UHADD8     see intrinsics.h */
+/* intrinsic __SSUB8      see intrinsics.h */
+/* intrinsic __QSUB8      see intrinsics.h */
+/* intrinsic __SHSUB8     see intrinsics.h */
+/* intrinsic __USUB8      see intrinsics.h */
+/* intrinsic __UQSUB8     see intrinsics.h */
+/* intrinsic __UHSUB8     see intrinsics.h */
+/* intrinsic __SADD16     see intrinsics.h */
+/* intrinsic __QADD16     see intrinsics.h */
+/* intrinsic __SHADD16    see intrinsics.h */
+/* intrinsic __UADD16     see intrinsics.h */
+/* intrinsic __UQADD16    see intrinsics.h */
+/* intrinsic __UHADD16    see intrinsics.h */
+/* intrinsic __SSUB16     see intrinsics.h */
+/* intrinsic __QSUB16     see intrinsics.h */
+/* intrinsic __SHSUB16    see intrinsics.h */
+/* intrinsic __USUB16     see intrinsics.h */
+/* intrinsic __UQSUB16    see intrinsics.h */
+/* intrinsic __UHSUB16    see intrinsics.h */
+/* intrinsic __SASX       see intrinsics.h */
+/* intrinsic __QASX       see intrinsics.h */
+/* intrinsic __SHASX      see intrinsics.h */
+/* intrinsic __UASX       see intrinsics.h */
+/* intrinsic __UQASX      see intrinsics.h */
+/* intrinsic __UHASX      see intrinsics.h */
+/* intrinsic __SSAX       see intrinsics.h */
+/* intrinsic __QSAX       see intrinsics.h */
+/* intrinsic __SHSAX      see intrinsics.h */
+/* intrinsic __USAX       see intrinsics.h */
+/* intrinsic __UQSAX      see intrinsics.h */
+/* intrinsic __UHSAX      see intrinsics.h */
+/* intrinsic __USAD8      see intrinsics.h */
+/* intrinsic __USADA8     see intrinsics.h */
+/* intrinsic __SSAT16     see intrinsics.h */
+/* intrinsic __USAT16     see intrinsics.h */
+/* intrinsic __UXTB16     see intrinsics.h */
+/* intrinsic __SXTB16     see intrinsics.h */
+/* intrinsic __UXTAB16    see intrinsics.h */
+/* intrinsic __SXTAB16    see intrinsics.h */
+/* intrinsic __SMUAD      see intrinsics.h */
+/* intrinsic __SMUADX     see intrinsics.h */
+/* intrinsic __SMLAD      see intrinsics.h */
+/* intrinsic __SMLADX     see intrinsics.h */
+/* intrinsic __SMLALD     see intrinsics.h */
+/* intrinsic __SMLALDX    see intrinsics.h */
+/* intrinsic __SMUSD      see intrinsics.h */
+/* intrinsic __SMUSDX     see intrinsics.h */
+/* intrinsic __SMLSD      see intrinsics.h */
+/* intrinsic __SMLSDX     see intrinsics.h */
+/* intrinsic __SMLSLD     see intrinsics.h */
+/* intrinsic __SMLSLDX    see intrinsics.h */
+/* intrinsic __SEL        see intrinsics.h */
+/* intrinsic __QADD       see intrinsics.h */
+/* intrinsic __QSUB       see intrinsics.h */
+/* intrinsic __PKHBT      see intrinsics.h */
+/* intrinsic __PKHTB      see intrinsics.h */
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhadd8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("ssub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhsub8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHADD16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhadd16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("ssub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSUB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhsub16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHASX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhasx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("ssax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("shsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UQSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uqsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UHSAX(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uhsax %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USAD8(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usad8 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __USADA8(uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("usada8 %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SSAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+  
+#define __USAT16(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat16 %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTB16(uint32_t op1)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __UXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("uxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTB16(uint32_t op1)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sxtb16 %0, %1" : "=r" (result) : "r" (op1));
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SXTAB16(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sxtab16 %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUAD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smuad %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUADX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smuadx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLAD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smlad %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLADX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smladx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLALD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlald %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLALDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((uint64_t)(ARG3) >> 32), __ARG3_L = (uint32_t)((uint64_t)(ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlaldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSD  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smusd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMUSDX (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smusdx %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSD (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smlsd %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SMLSDX (uint32_t op1, uint32_t op2, uint32_t op3)
+{
+  uint32_t result;
+  
+  __ASM volatile ("smlsdx %0, %1, %2, %3" : "=r" (result) : "r" (op1), "r" (op2), "r" (op3) );
+  return(result);
+}
+
+#define __SMLSLD(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsld %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+#define __SMLSLDX(ARG1,ARG2,ARG3) \
+({ \
+  uint32_t __ARG1 = (ARG1), __ARG2 = (ARG2), __ARG3_H = (uint32_t)((ARG3) >> 32), __ARG3_L = (uint32_t)((ARG3) & 0xFFFFFFFFUL); \
+  __ASM volatile ("smlsldx %0, %1, %2, %3" : "=r" (__ARG3_L), "=r" (__ARG3_H) : "r" (__ARG1), "r" (__ARG2), "0" (__ARG3_L), "1" (__ARG3_H) ); \
+  (uint64_t)(((uint64_t)__ARG3_H << 32) | __ARG3_L); \
+ })
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __SEL  (uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("sel %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QADD(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+
+  __ASM volatile ("qadd %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __QSUB(uint32_t op1, uint32_t op2)
+{
+  uint32_t result;
+  
+  __ASM volatile ("qsub %0, %1, %2" : "=r" (result) : "r" (op1), "r" (op2) );
+  return(result);
+}
+
+#define __PKHBT(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  __ASM ("pkhbt %0, %1, %2, lsl %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+#define __PKHTB(ARG1,ARG2,ARG3) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1), __ARG2 = (ARG2); \
+  if (ARG3 == 0) \
+    __ASM ("pkhtb %0, %1, %2" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2)  ); \
+  else	\
+    __ASM ("pkhtb %0, %1, %2, asr %3" : "=r" (__RES) :  "r" (__ARG1), "r" (__ARG2), "I" (ARG3)  ); \
+  __RES; \
+ })
+
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+
+/*------ CM4 SIMD Intrinsics -----------------------------------------------------*/
+/* not yet supported */
+/*-- End CM4 SIMD Intrinsics -----------------------------------------------------*/
+
+
+#endif
+
+/*@} end of group CMSIS_SIMD_intrinsics */
+
+
+#endif /* __CORE_CM4_SIMD_H */
+
+#ifdef __cplusplus
+}
+#endif
diff --git a/bsp/stm32f40x/Libraries/CMSIS/Include/core_cmFunc.h b/bsp/stm32f40x/Libraries/CMSIS/Include/core_cmFunc.h
new file mode 100644
index 0000000000..c999b1c83b
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/Include/core_cmFunc.h
@@ -0,0 +1,609 @@
+/**************************************************************************//**
+ * @file     core_cmFunc.h
+ * @brief    CMSIS Cortex-M Core Function Access Header File
+ * @version  V2.10
+ * @date     26. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMFUNC_H
+#define __CORE_CMFUNC_H
+
+
+/* ###########################  Core Function Access  ########################### */
+/** \ingroup  CMSIS_Core_FunctionInterface   
+    \defgroup CMSIS_Core_RegAccFunctions CMSIS Core Register Access Functions
+  @{
+ */
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+/* intrinsic void __enable_irq();     */
+/* intrinsic void __disable_irq();    */
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+static __INLINE uint32_t __get_CONTROL(void)
+{
+  register uint32_t __regControl         __ASM("control");
+  return(__regControl);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+static __INLINE void __set_CONTROL(uint32_t control)
+{
+  register uint32_t __regControl         __ASM("control");
+  __regControl = control;
+}
+
+
+/** \brief  Get ISPR Register
+
+    This function returns the content of the ISPR Register.
+
+    \return               ISPR Register value
+ */
+static __INLINE uint32_t __get_IPSR(void)
+{
+  register uint32_t __regIPSR          __ASM("ipsr");
+  return(__regIPSR);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+static __INLINE uint32_t __get_APSR(void)
+{
+  register uint32_t __regAPSR          __ASM("apsr");
+  return(__regAPSR);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+static __INLINE uint32_t __get_xPSR(void)
+{
+  register uint32_t __regXPSR          __ASM("xpsr");
+  return(__regXPSR);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+static __INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  return(__regProcessStackPointer);
+}
+
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  register uint32_t __regProcessStackPointer  __ASM("psp");
+  __regProcessStackPointer = topOfProcStack;
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+static __INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  return(__regMainStackPointer);
+}
+
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  register uint32_t __regMainStackPointer     __ASM("msp");
+  __regMainStackPointer = topOfMainStack;
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+static __INLINE uint32_t __get_PRIMASK(void)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  return(__regPriMask);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  register uint32_t __regPriMask         __ASM("primask");
+  __regPriMask = (priMask);
+}
+ 
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __enable_fault_irq                __enable_fiq
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+#define __disable_fault_irq               __disable_fiq
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+static __INLINE uint32_t  __get_BASEPRI(void)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  return(__regBasePri);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+static __INLINE void __set_BASEPRI(uint32_t basePri)
+{
+  register uint32_t __regBasePri         __ASM("basepri");
+  __regBasePri = (basePri & 0xff);
+}
+ 
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+static __INLINE uint32_t __get_FAULTMASK(void)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  return(__regFaultMask);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  register uint32_t __regFaultMask       __ASM("faultmask");
+  __regFaultMask = (faultMask & (uint32_t)1);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  return(__regfpscr);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  register uint32_t __regfpscr         __ASM("fpscr");
+  __regfpscr = (fpscr);
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include 
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  Enable IRQ Interrupts
+
+  This function enables IRQ interrupts by clearing the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_irq(void)
+{
+  __ASM volatile ("cpsie i");
+}
+
+
+/** \brief  Disable IRQ Interrupts
+
+  This function disables IRQ interrupts by setting the I-bit in the CPSR.
+  Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_irq(void)
+{
+  __ASM volatile ("cpsid i");
+}
+
+
+/** \brief  Get Control Register
+
+    This function returns the content of the Control Register.
+
+    \return               Control Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_CONTROL(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, control" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Control Register
+
+    This function writes the given value to the Control Register.
+
+    \param [in]    control  Control Register value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_CONTROL(uint32_t control)
+{
+  __ASM volatile ("MSR control, %0" : : "r" (control) );
+}
+
+
+/** \brief  Get ISPR Register
+
+    This function returns the content of the ISPR Register.
+
+    \return               ISPR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_IPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, ipsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get APSR Register
+
+    This function returns the content of the APSR Register.
+
+    \return               APSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_APSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, apsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get xPSR Register
+
+    This function returns the content of the xPSR Register.
+
+    \return               xPSR Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_xPSR(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, xpsr" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Get Process Stack Pointer
+
+    This function returns the current value of the Process Stack Pointer (PSP).
+
+    \return               PSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, psp\n"  : "=r" (result) );
+  return(result);
+}
+ 
+
+/** \brief  Set Process Stack Pointer
+
+    This function assigns the given value to the Process Stack Pointer (PSP).
+
+    \param [in]    topOfProcStack  Process Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PSP(uint32_t topOfProcStack)
+{
+  __ASM volatile ("MSR psp, %0\n" : : "r" (topOfProcStack) );
+}
+
+
+/** \brief  Get Main Stack Pointer
+
+    This function returns the current value of the Main Stack Pointer (MSP).
+
+    \return               MSP Register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_MSP(void)
+{
+  register uint32_t result;
+
+  __ASM volatile ("MRS %0, msp\n" : "=r" (result) );
+  return(result);
+}
+ 
+
+/** \brief  Set Main Stack Pointer
+
+    This function assigns the given value to the Main Stack Pointer (MSP).
+
+    \param [in]    topOfMainStack  Main Stack Pointer value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_MSP(uint32_t topOfMainStack)
+{
+  __ASM volatile ("MSR msp, %0\n" : : "r" (topOfMainStack) );
+}
+
+
+/** \brief  Get Priority Mask
+
+    This function returns the current state of the priority mask bit from the Priority Mask Register.
+
+    \return               Priority Mask value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_PRIMASK(void)
+{
+  uint32_t result;
+
+  __ASM volatile ("MRS %0, primask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Priority Mask
+
+    This function assigns the given value to the Priority Mask Register.
+
+    \param [in]    priMask  Priority Mask
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_PRIMASK(uint32_t priMask)
+{
+  __ASM volatile ("MSR primask, %0" : : "r" (priMask) );
+}
+ 
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Enable FIQ
+
+    This function enables FIQ interrupts by clearing the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __enable_fault_irq(void)
+{
+  __ASM volatile ("cpsie f");
+}
+
+
+/** \brief  Disable FIQ
+
+    This function disables FIQ interrupts by setting the F-bit in the CPSR.
+    Can only be executed in Privileged modes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __disable_fault_irq(void)
+{
+  __ASM volatile ("cpsid f");
+}
+
+
+/** \brief  Get Base Priority
+
+    This function returns the current value of the Base Priority register.
+
+    \return               Base Priority register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_BASEPRI(void)
+{
+  uint32_t result;
+  
+  __ASM volatile ("MRS %0, basepri_max" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Base Priority
+
+    This function assigns the given value to the Base Priority register.
+
+    \param [in]    basePri  Base Priority value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_BASEPRI(uint32_t value)
+{
+  __ASM volatile ("MSR basepri, %0" : : "r" (value) );
+}
+
+
+/** \brief  Get Fault Mask
+
+    This function returns the current value of the Fault Mask register.
+
+    \return               Fault Mask register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FAULTMASK(void)
+{
+  uint32_t result;
+  
+  __ASM volatile ("MRS %0, faultmask" : "=r" (result) );
+  return(result);
+}
+
+
+/** \brief  Set Fault Mask
+
+    This function assigns the given value to the Fault Mask register.
+
+    \param [in]    faultMask  Fault Mask value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FAULTMASK(uint32_t faultMask)
+{
+  __ASM volatile ("MSR faultmask, %0" : : "r" (faultMask) );
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+#if       (__CORTEX_M == 0x04)
+
+/** \brief  Get FPSCR
+
+    This function returns the current value of the Floating Point Status/Control register.
+
+    \return               Floating Point Status/Control register value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __get_FPSCR(void)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  uint32_t result;
+
+  __ASM volatile ("VMRS %0, fpscr" : "=r" (result) );
+  return(result);
+#else
+   return(0);
+#endif
+}
+
+
+/** \brief  Set FPSCR
+
+    This function assigns the given value to the Floating Point Status/Control register.
+
+    \param [in]    fpscr  Floating Point Status/Control value to set
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __set_FPSCR(uint32_t fpscr)
+{
+#if (__FPU_PRESENT == 1) && (__FPU_USED == 1)
+  __ASM volatile ("VMSR fpscr, %0" : : "r" (fpscr) );
+#endif
+}
+
+#endif /* (__CORTEX_M == 0x04) */
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all instrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@} end of CMSIS_Core_RegAccFunctions */
+
+
+#endif /* __CORE_CMFUNC_H */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/Include/core_cmInstr.h b/bsp/stm32f40x/Libraries/CMSIS/Include/core_cmInstr.h
new file mode 100644
index 0000000000..ceb4f87568
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/Include/core_cmInstr.h
@@ -0,0 +1,585 @@
+/**************************************************************************//**
+ * @file     core_cmInstr.h
+ * @brief    CMSIS Cortex-M Core Instruction Access Header File
+ * @version  V2.10
+ * @date     19. July 2011
+ *
+ * @note
+ * Copyright (C) 2009-2011 ARM Limited. All rights reserved.
+ *
+ * @par
+ * ARM Limited (ARM) is supplying this software for use with Cortex-M 
+ * processor based microcontrollers.  This file can be freely distributed 
+ * within development tools that are supporting such ARM based processors. 
+ *
+ * @par
+ * THIS SOFTWARE IS PROVIDED "AS IS".  NO WARRANTIES, WHETHER EXPRESS, IMPLIED
+ * OR STATUTORY, INCLUDING, BUT NOT LIMITED TO, IMPLIED WARRANTIES OF
+ * MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE APPLY TO THIS SOFTWARE.
+ * ARM SHALL NOT, IN ANY CIRCUMSTANCES, BE LIABLE FOR SPECIAL, INCIDENTAL, OR
+ * CONSEQUENTIAL DAMAGES, FOR ANY REASON WHATSOEVER.
+ *
+ ******************************************************************************/
+
+#ifndef __CORE_CMINSTR_H
+#define __CORE_CMINSTR_H
+
+
+/* ##########################  Core Instruction Access  ######################### */
+/** \defgroup CMSIS_Core_InstructionInterface CMSIS Core Instruction Interface
+  Access to dedicated instructions
+  @{
+*/
+
+#if   defined ( __CC_ARM ) /*------------------RealView Compiler -----------------*/
+/* ARM armcc specific functions */
+
+#if (__ARMCC_VERSION < 400677)
+  #error "Please use ARM Compiler Toolchain V4.0.677 or later!"
+#endif
+
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+#define __NOP                             __nop
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+#define __WFI                             __wfi
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+#define __WFE                             __wfe
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+#define __SEV                             __sev
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor, 
+    so that all instructions following the ISB are fetched from cache or 
+    memory, after the instruction has been completed.
+ */
+#define __ISB()                           __isb(0xF)
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier. 
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+#define __DSB()                           __dsb(0xF)
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before 
+    and after the instruction, without ensuring their completion.
+ */
+#define __DMB()                           __dmb(0xF)
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __REV                             __rev
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+static __INLINE __ASM uint32_t __REV16(uint32_t value)
+{
+  rev16 r0, r0
+  bx lr
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+static __INLINE __ASM int32_t __REVSH(int32_t value)
+{
+  revsh r0, r0
+  bx lr
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+#define __RBIT                            __rbit
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+#define __LDREXB(ptr)                     ((uint8_t ) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+#define __LDREXH(ptr)                     ((uint16_t) __ldrex(ptr))
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+#define __LDREXW(ptr)                     ((uint32_t ) __ldrex(ptr))
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXB(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXH(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+#define __STREXW(value, ptr)              __strex(value, ptr)
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+#define __CLREX                           __clrex
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT                            __ssat
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT                            __usat
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+#define __CLZ                             __clz 
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+#elif defined ( __ICCARM__ ) /*------------------ ICC Compiler -------------------*/
+/* IAR iccarm specific functions */
+
+#include 
+
+
+#elif defined ( __GNUC__ ) /*------------------ GNU Compiler ---------------------*/
+/* GNU gcc specific functions */
+
+/** \brief  No Operation
+
+    No Operation does nothing. This instruction can be used for code alignment purposes.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __NOP(void)
+{
+  __ASM volatile ("nop");
+}
+
+
+/** \brief  Wait For Interrupt
+
+    Wait For Interrupt is a hint instruction that suspends execution
+    until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFI(void)
+{
+  __ASM volatile ("wfi");
+}
+
+
+/** \brief  Wait For Event
+
+    Wait For Event is a hint instruction that permits the processor to enter
+    a low-power state until one of a number of events occurs.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __WFE(void)
+{
+  __ASM volatile ("wfe");
+}
+
+
+/** \brief  Send Event
+
+    Send Event is a hint instruction. It causes an event to be signaled to the CPU.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __SEV(void)
+{
+  __ASM volatile ("sev");
+}
+
+
+/** \brief  Instruction Synchronization Barrier
+
+    Instruction Synchronization Barrier flushes the pipeline in the processor, 
+    so that all instructions following the ISB are fetched from cache or 
+    memory, after the instruction has been completed.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __ISB(void)
+{
+  __ASM volatile ("isb");
+}
+
+
+/** \brief  Data Synchronization Barrier
+
+    This function acts as a special kind of Data Memory Barrier. 
+    It completes when all explicit memory accesses before this instruction complete.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DSB(void)
+{
+  __ASM volatile ("dsb");
+}
+
+
+/** \brief  Data Memory Barrier
+
+    This function ensures the apparent order of the explicit memory operations before 
+    and after the instruction, without ensuring their completion.
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __DMB(void)
+{
+  __ASM volatile ("dmb");
+}
+
+
+/** \brief  Reverse byte order (32 bit)
+
+    This function reverses the byte order in integer value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV(uint32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("rev %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order (16 bit)
+
+    This function reverses the byte order in two unsigned short values.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __REV16(uint32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("rev16 %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+/** \brief  Reverse byte order in signed short value
+
+    This function reverses the byte order in a signed short value with sign extension to integer.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE int32_t __REVSH(int32_t value)
+{
+  uint32_t result;
+  
+  __ASM volatile ("revsh %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+
+#if       (__CORTEX_M >= 0x03)
+
+/** \brief  Reverse bit order of value
+
+    This function reverses the bit order of the given value.
+
+    \param [in]    value  Value to reverse
+    \return               Reversed value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __RBIT(uint32_t value)
+{
+  uint32_t result;
+  
+   __ASM volatile ("rbit %0, %1" : "=r" (result) : "r" (value) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (8 bit)
+
+    This function performs a exclusive LDR command for 8 bit value.
+
+    \param [in]    ptr  Pointer to data
+    \return             value of type uint8_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __LDREXB(volatile uint8_t *addr)
+{
+    uint8_t result;
+  
+   __ASM volatile ("ldrexb %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (16 bit)
+
+    This function performs a exclusive LDR command for 16 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint16_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint16_t __LDREXH(volatile uint16_t *addr)
+{
+    uint16_t result;
+  
+   __ASM volatile ("ldrexh %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  LDR Exclusive (32 bit)
+
+    This function performs a exclusive LDR command for 32 bit values.
+
+    \param [in]    ptr  Pointer to data
+    \return        value of type uint32_t at (*ptr)
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __LDREXW(volatile uint32_t *addr)
+{
+    uint32_t result;
+  
+   __ASM volatile ("ldrex %0, [%1]" : "=r" (result) : "r" (addr) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (8 bit)
+
+    This function performs a exclusive STR command for 8 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXB(uint8_t value, volatile uint8_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strexb %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (16 bit)
+
+    This function performs a exclusive STR command for 16 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXH(uint16_t value, volatile uint16_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strexh %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  STR Exclusive (32 bit)
+
+    This function performs a exclusive STR command for 32 bit values.
+
+    \param [in]  value  Value to store
+    \param [in]    ptr  Pointer to location
+    \return          0  Function succeeded
+    \return          1  Function failed
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint32_t __STREXW(uint32_t value, volatile uint32_t *addr)
+{
+   uint32_t result;
+  
+   __ASM volatile ("strex %0, %2, [%1]" : "=r" (result) : "r" (addr), "r" (value) );
+   return(result);
+}
+
+
+/** \brief  Remove the exclusive lock
+
+    This function removes the exclusive lock which is created by LDREX.
+
+ */
+__attribute__( ( always_inline ) ) static __INLINE void __CLREX(void)
+{
+  __ASM volatile ("clrex");
+}
+
+
+/** \brief  Signed Saturate
+
+    This function saturates a signed value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (1..32)
+    \return             Saturated value
+ */
+#define __SSAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("ssat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Unsigned Saturate
+
+    This function saturates an unsigned value.
+
+    \param [in]  value  Value to be saturated
+    \param [in]    sat  Bit position to saturate to (0..31)
+    \return             Saturated value
+ */
+#define __USAT(ARG1,ARG2) \
+({                          \
+  uint32_t __RES, __ARG1 = (ARG1); \
+  __ASM ("usat %0, %1, %2" : "=r" (__RES) :  "I" (ARG2), "r" (__ARG1) ); \
+  __RES; \
+ })
+
+
+/** \brief  Count leading zeros
+
+    This function counts the number of leading zeros of a data value.
+
+    \param [in]  value  Value to count the leading zeros
+    \return             number of leading zeros in value
+ */
+__attribute__( ( always_inline ) ) static __INLINE uint8_t __CLZ(uint32_t value)
+{
+  uint8_t result;
+  
+  __ASM volatile ("clz %0, %1" : "=r" (result) : "r" (value) );
+  return(result);
+}
+
+#endif /* (__CORTEX_M >= 0x03) */
+
+
+
+
+#elif defined ( __TASKING__ ) /*------------------ TASKING Compiler --------------*/
+/* TASKING carm specific functions */
+
+/*
+ * The CMSIS functions have been implemented as intrinsics in the compiler.
+ * Please use "carm -?i" to get an up to date list of all intrinsics,
+ * Including the CMSIS ones.
+ */
+
+#endif
+
+/*@}*/ /* end of group CMSIS_Core_InstructionInterface */
+
+#endif /* __CORE_CMINSTR_H */
diff --git a/bsp/stm32f40x/Libraries/CMSIS/README.txt b/bsp/stm32f40x/Libraries/CMSIS/README.txt
new file mode 100644
index 0000000000..cc69e2ca20
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/README.txt
@@ -0,0 +1,34 @@
+* -------------------------------------------------------------------
+* Copyright (C) 2011 ARM Limited. All rights reserved.  
+* 
+* Date:        25 July 2011  
+* Revision:    V2.10 
+*  
+* Project:     Cortex Microcontroller Software Interface Standard (CMSIS)
+* Title:       Release Note for CMSIS
+*
+* -------------------------------------------------------------------
+
+
+NOTE - Open the index.html file to access CMSIS documentation
+
+
+The Cortex Microcontroller Software Interface Standard (CMSIS) provides a single standard across all 
+Cortex-Mx processor series vendors. It enables code re-use and code sharing across software projects 
+and reduces time-to-market for new embedded applications.
+
+CMSIS is released under the terms of the end user license agreement ("CMSIS END USER LICENCE AGREEMENT.pdf").
+Any user of the software package is bound to the terms and conditions of the end user license agreement.
+
+
+You will find the following sub-directories:
+
+Documentation           - Contains CMSIS documentation.
+ 
+DSP_Lib                 - MDK project files, Examples and source files etc.. to build the 
+                          CMSIS DSP Software Library for Cortex-M0, Cortex-M3, Cortex-M4 processors.
+
+Include                 - CMSIS Core Support and CMSIS DSP Include Files.
+
+Lib                     - CMSIS DSP Binaries 
+---
\ No newline at end of file
diff --git a/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Include/stm32f4xx.h b/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Include/stm32f4xx.h
new file mode 100644
index 0000000000..68db7f0fb5
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Include/stm32f4xx.h
@@ -0,0 +1,6945 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer Header File. 
+  *          This file contains all the peripheral register's definitions, bits 
+  *          definitions and memory mapping for STM32F4xx devices.
+  *            
+  *          The file is the unique include file that the application programmer
+  *          is using in the C source code, usually in main.c. This file contains:
+  *           - Configuration section that allows to select:
+  *              - The device used in the target application
+  *              - To use or not the peripheral’s drivers in application code(i.e. 
+  *                code will be based on direct access to peripheral’s registers 
+  *                rather than drivers API), this option is controlled by 
+  *                "#define USE_STDPERIPH_DRIVER"
+  *              - To change few application-specific parameters such as the HSE 
+  *                crystal frequency
+  *           - Data structures and the address mapping for all peripherals
+  *           - Peripheral's registers declarations and bits definition
+  *           - Macros to access peripheral’s registers hardware
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************  
+  */ 
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx
+  * @{
+  */
+    
+#ifndef __STM32F4xx_H
+#define __STM32F4xx_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif /* __cplusplus */
+  
+/** @addtogroup Library_configuration_section
+  * @{
+  */
+  
+/* Uncomment the line below according to the target STM32 device used in your
+   application 
+  */
+
+#if !defined (STM32F4XX) 
+  #define STM32F4XX
+#endif
+
+/*  Tip: To avoid modifying this file each time you need to switch between these
+        devices, you can define the device in your toolchain compiler preprocessor.
+  */
+
+#if !defined (STM32F4XX)
+ #error "Please select first the target STM32F4XX device used in your application (in stm32f4xx.h file)"
+#endif
+
+#if !defined  (USE_STDPERIPH_DRIVER)
+/**
+ * @brief Comment the line below if you will not use the peripherals drivers.
+   In this case, these drivers will not be included and the application code will 
+   be based on direct access to peripherals registers 
+   */
+  /*#define USE_STDPERIPH_DRIVER*/
+#endif /* USE_STDPERIPH_DRIVER */
+
+/**
+ * @brief In the following line adjust the value of External High Speed oscillator (HSE)
+   used in your application 
+   
+   Tip: To avoid modifying this file each time you need to use different HSE, you
+        can define the HSE value in your toolchain compiler preprocessor.
+  */           
+
+#if !defined  (HSE_VALUE) 
+  #define HSE_VALUE    ((uint32_t)25000000) /*!< Value of the External oscillator in Hz */
+#endif /* HSE_VALUE */
+
+/**
+ * @brief In the following line adjust the External High Speed oscillator (HSE) Startup 
+   Timeout value 
+   */
+#if !defined  (HSE_STARTUP_TIMEOUT) 
+  #define HSE_STARTUP_TIMEOUT    ((uint16_t)0x0500)   /*!< Time out for HSE start up */
+#endif /* HSE_STARTUP_TIMEOUT */   
+
+#if !defined  (HSI_VALUE)   
+  #define HSI_VALUE    ((uint32_t)16000000) /*!< Value of the Internal oscillator in Hz*/
+#endif /* HSI_VALUE */   
+
+/**
+ * @brief STM32F4XX Standard Peripherals Library version number V1.0.0RC1
+   */
+#define __STM32F4XX_STDPERIPH_VERSION_MAIN   (0x01) /*!< [31:24] main version */                                  
+#define __STM32F4XX_STDPERIPH_VERSION_SUB1   (0x00) /*!< [23:16] sub1 version */
+#define __STM32F4XX_STDPERIPH_VERSION_SUB2   (0x00) /*!< [15:8]  sub2 version */
+#define __STM32F4XX_STDPERIPH_VERSION_RC     (0x01) /*!< [7:0]  release candidate */ 
+#define __STM32F4XX_STDPERIPH_VERSION        ((__STM32F4XX_STDPERIPH_VERSION_MAIN << 24)\
+                                             |(__STM32F4XX_STDPERIPH_VERSION_SUB1 << 16)\
+                                             |(__STM32F4XX_STDPERIPH_VERSION_SUB2 << 8)\
+                                             |(__STM32F4XX_STDPERIPH_VERSION_RC))
+                                             
+/**
+  * @}
+  */
+
+/** @addtogroup Configuration_section_for_CMSIS
+  * @{
+  */
+
+/**
+ * @brief Configuration of the Cortex-M4 Processor and Core Peripherals 
+ */
+#define __MPU_PRESENT             1 /*!< STM32F4XX provides an MPU */
+#define __NVIC_PRIO_BITS          4 /*!< STM32F4XX uses 4 Bits for the Priority Levels */
+#define __Vendor_SysTickConfig    0 /*!< Set to 1 if different SysTick Config is used */
+#define __FPU_PRESENT             1 /*!< FPU present                                  */
+
+/**
+ * @brief STM32F4XX Interrupt Number Definition, according to the selected device 
+ *        in @ref Library_configuration_section 
+ */
+typedef enum IRQn
+{
+/******  Cortex-M4 Processor Exceptions Numbers ****************************************************************/
+  NonMaskableInt_IRQn         = -14,    /*!< 2 Non Maskable Interrupt                                          */
+  MemoryManagement_IRQn       = -12,    /*!< 4 Cortex-M4 Memory Management Interrupt                           */
+  BusFault_IRQn               = -11,    /*!< 5 Cortex-M4 Bus Fault Interrupt                                   */
+  UsageFault_IRQn             = -10,    /*!< 6 Cortex-M4 Usage Fault Interrupt                                 */
+  SVCall_IRQn                 = -5,     /*!< 11 Cortex-M4 SV Call Interrupt                                    */
+  DebugMonitor_IRQn           = -4,     /*!< 12 Cortex-M4 Debug Monitor Interrupt                              */
+  PendSV_IRQn                 = -2,     /*!< 14 Cortex-M4 Pend SV Interrupt                                    */
+  SysTick_IRQn                = -1,     /*!< 15 Cortex-M4 System Tick Interrupt                                */
+/******  STM32 specific Interrupt Numbers **********************************************************************/
+  WWDG_IRQn                   = 0,      /*!< Window WatchDog Interrupt                                         */
+  PVD_IRQn                    = 1,      /*!< PVD through EXTI Line detection Interrupt                         */
+  TAMP_STAMP_IRQn             = 2,      /*!< Tamper and TimeStamp interrupts through the EXTI line             */
+  RTC_WKUP_IRQn               = 3,      /*!< RTC Wakeup interrupt through the EXTI line                        */
+  FLASH_IRQn                  = 4,      /*!< FLASH global Interrupt                                            */
+  RCC_IRQn                    = 5,      /*!< RCC global Interrupt                                              */
+  EXTI0_IRQn                  = 6,      /*!< EXTI Line0 Interrupt                                              */
+  EXTI1_IRQn                  = 7,      /*!< EXTI Line1 Interrupt                                              */
+  EXTI2_IRQn                  = 8,      /*!< EXTI Line2 Interrupt                                              */
+  EXTI3_IRQn                  = 9,      /*!< EXTI Line3 Interrupt                                              */
+  EXTI4_IRQn                  = 10,     /*!< EXTI Line4 Interrupt                                              */
+  DMA1_Stream0_IRQn           = 11,     /*!< DMA1 Stream 0 global Interrupt                                    */
+  DMA1_Stream1_IRQn           = 12,     /*!< DMA1 Stream 1 global Interrupt                                    */
+  DMA1_Stream2_IRQn           = 13,     /*!< DMA1 Stream 2 global Interrupt                                    */
+  DMA1_Stream3_IRQn           = 14,     /*!< DMA1 Stream 3 global Interrupt                                    */
+  DMA1_Stream4_IRQn           = 15,     /*!< DMA1 Stream 4 global Interrupt                                    */
+  DMA1_Stream5_IRQn           = 16,     /*!< DMA1 Stream 5 global Interrupt                                    */
+  DMA1_Stream6_IRQn           = 17,     /*!< DMA1 Stream 6 global Interrupt                                    */
+  ADC_IRQn                    = 18,     /*!< ADC1, ADC2 and ADC3 global Interrupts                             */
+  CAN1_TX_IRQn                = 19,     /*!< CAN1 TX Interrupt                                                 */
+  CAN1_RX0_IRQn               = 20,     /*!< CAN1 RX0 Interrupt                                                */
+  CAN1_RX1_IRQn               = 21,     /*!< CAN1 RX1 Interrupt                                                */
+  CAN1_SCE_IRQn               = 22,     /*!< CAN1 SCE Interrupt                                                */
+  EXTI9_5_IRQn                = 23,     /*!< External Line[9:5] Interrupts                                     */
+  TIM1_BRK_TIM9_IRQn          = 24,     /*!< TIM1 Break interrupt and TIM9 global interrupt                    */
+  TIM1_UP_TIM10_IRQn          = 25,     /*!< TIM1 Update Interrupt and TIM10 global interrupt                  */
+  TIM1_TRG_COM_TIM11_IRQn     = 26,     /*!< TIM1 Trigger and Commutation Interrupt and TIM11 global interrupt */
+  TIM1_CC_IRQn                = 27,     /*!< TIM1 Capture Compare Interrupt                                    */
+  TIM2_IRQn                   = 28,     /*!< TIM2 global Interrupt                                             */
+  TIM3_IRQn                   = 29,     /*!< TIM3 global Interrupt                                             */
+  TIM4_IRQn                   = 30,     /*!< TIM4 global Interrupt                                             */
+  I2C1_EV_IRQn                = 31,     /*!< I2C1 Event Interrupt                                              */
+  I2C1_ER_IRQn                = 32,     /*!< I2C1 Error Interrupt                                              */
+  I2C2_EV_IRQn                = 33,     /*!< I2C2 Event Interrupt                                              */
+  I2C2_ER_IRQn                = 34,     /*!< I2C2 Error Interrupt                                              */  
+  SPI1_IRQn                   = 35,     /*!< SPI1 global Interrupt                                             */
+  SPI2_IRQn                   = 36,     /*!< SPI2 global Interrupt                                             */
+  USART1_IRQn                 = 37,     /*!< USART1 global Interrupt                                           */
+  USART2_IRQn                 = 38,     /*!< USART2 global Interrupt                                           */
+  USART3_IRQn                 = 39,     /*!< USART3 global Interrupt                                           */
+  EXTI15_10_IRQn              = 40,     /*!< External Line[15:10] Interrupts                                   */
+  RTC_Alarm_IRQn              = 41,     /*!< RTC Alarm (A and B) through EXTI Line Interrupt                   */
+  OTG_FS_WKUP_IRQn            = 42,     /*!< USB OTG FS Wakeup through EXTI line interrupt                     */    
+  TIM8_BRK_TIM12_IRQn         = 43,     /*!< TIM8 Break Interrupt and TIM12 global interrupt                   */
+  TIM8_UP_TIM13_IRQn          = 44,     /*!< TIM8 Update Interrupt and TIM13 global interrupt                  */
+  TIM8_TRG_COM_TIM14_IRQn     = 45,     /*!< TIM8 Trigger and Commutation Interrupt and TIM14 global interrupt */
+  TIM8_CC_IRQn                = 46,     /*!< TIM8 Capture Compare Interrupt                                    */
+  DMA1_Stream7_IRQn           = 47,     /*!< DMA1 Stream7 Interrupt                                            */
+  FSMC_IRQn                   = 48,     /*!< FSMC global Interrupt                                             */
+  SDIO_IRQn                   = 49,     /*!< SDIO global Interrupt                                             */
+  TIM5_IRQn                   = 50,     /*!< TIM5 global Interrupt                                             */
+  SPI3_IRQn                   = 51,     /*!< SPI3 global Interrupt                                             */
+  UART4_IRQn                  = 52,     /*!< UART4 global Interrupt                                            */
+  UART5_IRQn                  = 53,     /*!< UART5 global Interrupt                                            */
+  TIM6_DAC_IRQn               = 54,     /*!< TIM6 global and DAC1&2 underrun error  interrupts                 */
+  TIM7_IRQn                   = 55,     /*!< TIM7 global interrupt                                             */
+  DMA2_Stream0_IRQn           = 56,     /*!< DMA2 Stream 0 global Interrupt                                    */
+  DMA2_Stream1_IRQn           = 57,     /*!< DMA2 Stream 1 global Interrupt                                    */
+  DMA2_Stream2_IRQn           = 58,     /*!< DMA2 Stream 2 global Interrupt                                    */
+  DMA2_Stream3_IRQn           = 59,     /*!< DMA2 Stream 3 global Interrupt                                    */
+  DMA2_Stream4_IRQn           = 60,     /*!< DMA2 Stream 4 global Interrupt                                    */
+  ETH_IRQn                    = 61,     /*!< Ethernet global Interrupt                                         */
+  ETH_WKUP_IRQn               = 62,     /*!< Ethernet Wakeup through EXTI line Interrupt                       */
+  CAN2_TX_IRQn                = 63,     /*!< CAN2 TX Interrupt                                                 */
+  CAN2_RX0_IRQn               = 64,     /*!< CAN2 RX0 Interrupt                                                */
+  CAN2_RX1_IRQn               = 65,     /*!< CAN2 RX1 Interrupt                                                */
+  CAN2_SCE_IRQn               = 66,     /*!< CAN2 SCE Interrupt                                                */
+  OTG_FS_IRQn                 = 67,     /*!< USB OTG FS global Interrupt                                       */
+  DMA2_Stream5_IRQn           = 68,     /*!< DMA2 Stream 5 global interrupt                                    */
+  DMA2_Stream6_IRQn           = 69,     /*!< DMA2 Stream 6 global interrupt                                    */
+  DMA2_Stream7_IRQn           = 70,     /*!< DMA2 Stream 7 global interrupt                                    */
+  USART6_IRQn                 = 71,     /*!< USART6 global interrupt                                           */ 
+  I2C3_EV_IRQn                = 72,     /*!< I2C3 event interrupt                                              */
+  I2C3_ER_IRQn                = 73,     /*!< I2C3 error interrupt                                              */
+  OTG_HS_EP1_OUT_IRQn         = 74,     /*!< USB OTG HS End Point 1 Out global interrupt                       */
+  OTG_HS_EP1_IN_IRQn          = 75,     /*!< USB OTG HS End Point 1 In global interrupt                        */
+  OTG_HS_WKUP_IRQn            = 76,     /*!< USB OTG HS Wakeup through EXTI interrupt                          */
+  OTG_HS_IRQn                 = 77,     /*!< USB OTG HS global interrupt                                       */
+  DCMI_IRQn                   = 78,     /*!< DCMI global interrupt                                             */
+  CRYP_IRQn                   = 79,     /*!< CRYP crypto global interrupt                                      */
+  HASH_RNG_IRQn               = 80,      /*!< Hash and Rng global interrupt                                     */
+  FPU_IRQn                    = 81      /*!< FPU global interrupt                                              */
+} IRQn_Type;
+
+/**
+  * @}
+  */
+
+#include "core_cm4.h"             /* Cortex-M4 processor and core peripherals */
+#include "system_stm32f4xx.h"
+#include 
+
+/** @addtogroup Exported_types
+  * @{
+  */  
+/*!< STM32F10x Standard Peripheral Library old types (maintained for legacy purpose) */
+typedef int32_t  s32;
+typedef int16_t s16;
+typedef int8_t  s8;
+
+typedef const int32_t sc32;  /*!< Read Only */
+typedef const int16_t sc16;  /*!< Read Only */
+typedef const int8_t sc8;   /*!< Read Only */
+
+typedef __IO int32_t  vs32;
+typedef __IO int16_t  vs16;
+typedef __IO int8_t   vs8;
+
+typedef __I int32_t vsc32;  /*!< Read Only */
+typedef __I int16_t vsc16;  /*!< Read Only */
+typedef __I int8_t vsc8;   /*!< Read Only */
+
+typedef uint32_t  u32;
+typedef uint16_t u16;
+typedef uint8_t  u8;
+
+typedef const uint32_t uc32;  /*!< Read Only */
+typedef const uint16_t uc16;  /*!< Read Only */
+typedef const uint8_t uc8;   /*!< Read Only */
+
+typedef __IO uint32_t  vu32;
+typedef __IO uint16_t vu16;
+typedef __IO uint8_t  vu8;
+
+typedef __I uint32_t vuc32;  /*!< Read Only */
+typedef __I uint16_t vuc16;  /*!< Read Only */
+typedef __I uint8_t vuc8;   /*!< Read Only */
+
+typedef enum {RESET = 0, SET = !RESET} FlagStatus, ITStatus;
+
+typedef enum {DISABLE = 0, ENABLE = !DISABLE} FunctionalState;
+#define IS_FUNCTIONAL_STATE(STATE) (((STATE) == DISABLE) || ((STATE) == ENABLE))
+
+typedef enum {ERROR = 0, SUCCESS = !ERROR} ErrorStatus;
+
+/**
+  * @}
+  */
+
+/** @addtogroup Peripheral_registers_structures
+  * @{
+  */   
+
+/** 
+  * @brief Analog to Digital Converter  
+  */
+
+typedef struct
+{
+  __IO uint32_t SR;     /*!< ADC status register,                         Address offset: 0x00 */
+  __IO uint32_t CR1;    /*!< ADC control register 1,                      Address offset: 0x04 */      
+  __IO uint32_t CR2;    /*!< ADC control register 2,                      Address offset: 0x08 */
+  __IO uint32_t SMPR1;  /*!< ADC sample time register 1,                  Address offset: 0x0C */
+  __IO uint32_t SMPR2;  /*!< ADC sample time register 2,                  Address offset: 0x10 */
+  __IO uint32_t JOFR1;  /*!< ADC injected channel data offset register 1, Address offset: 0x14 */
+  __IO uint32_t JOFR2;  /*!< ADC injected channel data offset register 2, Address offset: 0x18 */
+  __IO uint32_t JOFR3;  /*!< ADC injected channel data offset register 3, Address offset: 0x1C */
+  __IO uint32_t JOFR4;  /*!< ADC injected channel data offset register 4, Address offset: 0x20 */
+  __IO uint32_t HTR;    /*!< ADC watchdog higher threshold register,      Address offset: 0x24 */
+  __IO uint32_t LTR;    /*!< ADC watchdog lower threshold register,       Address offset: 0x28 */
+  __IO uint32_t SQR1;   /*!< ADC regular sequence register 1,             Address offset: 0x2C */
+  __IO uint32_t SQR2;   /*!< ADC regular sequence register 2,             Address offset: 0x30 */
+  __IO uint32_t SQR3;   /*!< ADC regular sequence register 3,             Address offset: 0x34 */
+  __IO uint32_t JSQR;   /*!< ADC injected sequence register,              Address offset: 0x38*/
+  __IO uint32_t JDR1;   /*!< ADC injected data register 1,                Address offset: 0x3C */
+  __IO uint32_t JDR2;   /*!< ADC injected data register 2,                Address offset: 0x40 */
+  __IO uint32_t JDR3;   /*!< ADC injected data register 3,                Address offset: 0x44 */
+  __IO uint32_t JDR4;   /*!< ADC injected data register 4,                Address offset: 0x48 */
+  __IO uint32_t DR;     /*!< ADC regular data register,                   Address offset: 0x4C */
+} ADC_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t CSR;    /*!< ADC Common status register,                  Address offset: ADC1 base address + 0x300 */
+  __IO uint32_t CCR;    /*!< ADC common control register,                 Address offset: ADC1 base address + 0x304 */
+  __IO uint32_t CDR;    /*!< ADC common regular data register for dual
+                             AND triple modes,                            Address offset: ADC1 base address + 0x308 */
+} ADC_Common_TypeDef;
+
+
+/** 
+  * @brief Controller Area Network TxMailBox 
+  */
+
+typedef struct
+{
+  __IO uint32_t TIR;  /*!< CAN TX mailbox identifier register */
+  __IO uint32_t TDTR; /*!< CAN mailbox data length control and time stamp register */
+  __IO uint32_t TDLR; /*!< CAN mailbox data low register */
+  __IO uint32_t TDHR; /*!< CAN mailbox data high register */
+} CAN_TxMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FIFOMailBox 
+  */
+  
+typedef struct
+{
+  __IO uint32_t RIR;  /*!< CAN receive FIFO mailbox identifier register */
+  __IO uint32_t RDTR; /*!< CAN receive FIFO mailbox data length control and time stamp register */
+  __IO uint32_t RDLR; /*!< CAN receive FIFO mailbox data low register */
+  __IO uint32_t RDHR; /*!< CAN receive FIFO mailbox data high register */
+} CAN_FIFOMailBox_TypeDef;
+
+/** 
+  * @brief Controller Area Network FilterRegister 
+  */
+  
+typedef struct
+{
+  __IO uint32_t FR1; /*!< CAN Filter bank register 1 */
+  __IO uint32_t FR2; /*!< CAN Filter bank register 1 */
+} CAN_FilterRegister_TypeDef;
+
+/** 
+  * @brief Controller Area Network 
+  */
+  
+typedef struct
+{
+  __IO uint32_t              MCR;                 /*!< CAN master control register,         Address offset: 0x00          */
+  __IO uint32_t              MSR;                 /*!< CAN master status register,          Address offset: 0x04          */
+  __IO uint32_t              TSR;                 /*!< CAN transmit status register,        Address offset: 0x08          */
+  __IO uint32_t              RF0R;                /*!< CAN receive FIFO 0 register,         Address offset: 0x0C          */
+  __IO uint32_t              RF1R;                /*!< CAN receive FIFO 1 register,         Address offset: 0x10          */
+  __IO uint32_t              IER;                 /*!< CAN interrupt enable register,       Address offset: 0x14          */
+  __IO uint32_t              ESR;                 /*!< CAN error status register,           Address offset: 0x18          */
+  __IO uint32_t              BTR;                 /*!< CAN bit timing register,             Address offset: 0x1C          */
+  uint32_t                   RESERVED0[88];       /*!< Reserved, 0x020 - 0x17F                                            */
+  CAN_TxMailBox_TypeDef      sTxMailBox[3];       /*!< CAN Tx MailBox,                      Address offset: 0x180 - 0x1AC */
+  CAN_FIFOMailBox_TypeDef    sFIFOMailBox[2];     /*!< CAN FIFO MailBox,                    Address offset: 0x1B0 - 0x1CC */
+  uint32_t                   RESERVED1[12];       /*!< Reserved, 0x1D0 - 0x1FF                                            */
+  __IO uint32_t              FMR;                 /*!< CAN filter master register,          Address offset: 0x200         */
+  __IO uint32_t              FM1R;                /*!< CAN filter mode register,            Address offset: 0x204         */
+  uint32_t                   RESERVED2;           /*!< Reserved, 0x208                                                    */
+  __IO uint32_t              FS1R;                /*!< CAN filter scale register,           Address offset: 0x20C         */
+  uint32_t                   RESERVED3;           /*!< Reserved, 0x210                                                    */
+  __IO uint32_t              FFA1R;               /*!< CAN filter FIFO assignment register, Address offset: 0x214         */
+  uint32_t                   RESERVED4;           /*!< Reserved, 0x218                                                    */
+  __IO uint32_t              FA1R;                /*!< CAN filter activation register,      Address offset: 0x21C         */
+  uint32_t                   RESERVED5[8];        /*!< Reserved, 0x220-0x23F                                              */ 
+  CAN_FilterRegister_TypeDef sFilterRegister[28]; /*!< CAN Filter Register,                 Address offset: 0x240-0x31C   */
+} CAN_TypeDef;
+
+/** 
+  * @brief CRC calculation unit 
+  */
+
+typedef struct
+{
+  __IO uint32_t DR;         /*!< CRC Data register,             Address offset: 0x00 */
+  __IO uint8_t  IDR;        /*!< CRC Independent data register, Address offset: 0x04 */
+  uint8_t       RESERVED0;  /*!< Reserved, 0x05                                      */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                      */
+  __IO uint32_t CR;         /*!< CRC Control register,          Address offset: 0x08 */
+} CRC_TypeDef;
+
+/** 
+  * @brief Digital to Analog Converter
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DAC control register,                                    Address offset: 0x00 */
+  __IO uint32_t SWTRIGR;  /*!< DAC software trigger register,                           Address offset: 0x04 */
+  __IO uint32_t DHR12R1;  /*!< DAC channel1 12-bit right-aligned data holding register, Address offset: 0x08 */
+  __IO uint32_t DHR12L1;  /*!< DAC channel1 12-bit left aligned data holding register,  Address offset: 0x0C */
+  __IO uint32_t DHR8R1;   /*!< DAC channel1 8-bit right aligned data holding register,  Address offset: 0x10 */
+  __IO uint32_t DHR12R2;  /*!< DAC channel2 12-bit right aligned data holding register, Address offset: 0x14 */
+  __IO uint32_t DHR12L2;  /*!< DAC channel2 12-bit left aligned data holding register,  Address offset: 0x18 */
+  __IO uint32_t DHR8R2;   /*!< DAC channel2 8-bit right-aligned data holding register,  Address offset: 0x1C */
+  __IO uint32_t DHR12RD;  /*!< Dual DAC 12-bit right-aligned data holding register,     Address offset: 0x20 */
+  __IO uint32_t DHR12LD;  /*!< DUAL DAC 12-bit left aligned data holding register,      Address offset: 0x24 */
+  __IO uint32_t DHR8RD;   /*!< DUAL DAC 8-bit right aligned data holding register,      Address offset: 0x28 */
+  __IO uint32_t DOR1;     /*!< DAC channel1 data output register,                       Address offset: 0x2C */
+  __IO uint32_t DOR2;     /*!< DAC channel2 data output register,                       Address offset: 0x30 */
+  __IO uint32_t SR;       /*!< DAC status register,                                     Address offset: 0x34 */
+} DAC_TypeDef;
+
+/** 
+  * @brief Debug MCU
+  */
+
+typedef struct
+{
+  __IO uint32_t IDCODE;  /*!< MCU device ID code,               Address offset: 0x00 */
+  __IO uint32_t CR;      /*!< Debug MCU configuration register, Address offset: 0x04 */
+  __IO uint32_t APB1FZ;  /*!< Debug MCU APB1 freeze register,   Address offset: 0x08 */
+  __IO uint32_t APB2FZ;  /*!< Debug MCU APB2 freeze register,   Address offset: 0x0C */
+}DBGMCU_TypeDef;
+
+/** 
+  * @brief DCMI
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;       /*!< DCMI control register 1,                       Address offset: 0x00 */
+  __IO uint32_t SR;       /*!< DCMI status register,                          Address offset: 0x04 */
+  __IO uint32_t RISR;     /*!< DCMI raw interrupt status register,            Address offset: 0x08 */
+  __IO uint32_t IER;      /*!< DCMI interrupt enable register,                Address offset: 0x0C */
+  __IO uint32_t MISR;     /*!< DCMI masked interrupt status register,         Address offset: 0x10 */
+  __IO uint32_t ICR;      /*!< DCMI interrupt clear register,                 Address offset: 0x14 */
+  __IO uint32_t ESCR;     /*!< DCMI embedded synchronization code register,   Address offset: 0x18 */
+  __IO uint32_t ESUR;     /*!< DCMI embedded synchronization unmask register, Address offset: 0x1C */
+  __IO uint32_t CWSTRTR;  /*!< DCMI crop window start,                        Address offset: 0x20 */
+  __IO uint32_t CWSIZER;  /*!< DCMI crop window size,                         Address offset: 0x24 */
+  __IO uint32_t DR;       /*!< DCMI data register,                            Address offset: 0x28 */
+} DCMI_TypeDef;
+
+/** 
+  * @brief DMA Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;     /*!< DMA stream x configuration register      */
+  __IO uint32_t NDTR;   /*!< DMA stream x number of data register     */
+  __IO uint32_t PAR;    /*!< DMA stream x peripheral address register */
+  __IO uint32_t M0AR;   /*!< DMA stream x memory 0 address register   */
+  __IO uint32_t M1AR;   /*!< DMA stream x memory 1 address register   */
+  __IO uint32_t FCR;    /*!< DMA stream x FIFO control register       */
+} DMA_Stream_TypeDef;
+
+typedef struct
+{
+  __IO uint32_t LISR;   /*!< DMA low interrupt status register,      Address offset: 0x00 */
+  __IO uint32_t HISR;   /*!< DMA high interrupt status register,     Address offset: 0x04 */
+  __IO uint32_t LIFCR;  /*!< DMA low interrupt flag clear register,  Address offset: 0x08 */
+  __IO uint32_t HIFCR;  /*!< DMA high interrupt flag clear register, Address offset: 0x0C */
+} DMA_TypeDef;
+
+/** 
+  * @brief Ethernet MAC
+  */
+
+typedef struct
+{
+  __IO uint32_t MACCR;
+  __IO uint32_t MACFFR;
+  __IO uint32_t MACHTHR;
+  __IO uint32_t MACHTLR;
+  __IO uint32_t MACMIIAR;
+  __IO uint32_t MACMIIDR;
+  __IO uint32_t MACFCR;
+  __IO uint32_t MACVLANTR;             /*    8 */
+  uint32_t      RESERVED0[2];
+  __IO uint32_t MACRWUFFR;             /*   11 */
+  __IO uint32_t MACPMTCSR;
+  uint32_t      RESERVED1[2];
+  __IO uint32_t MACSR;                 /*   15 */
+  __IO uint32_t MACIMR;
+  __IO uint32_t MACA0HR;
+  __IO uint32_t MACA0LR;
+  __IO uint32_t MACA1HR;
+  __IO uint32_t MACA1LR;
+  __IO uint32_t MACA2HR;
+  __IO uint32_t MACA2LR;
+  __IO uint32_t MACA3HR;
+  __IO uint32_t MACA3LR;               /*   24 */
+  uint32_t      RESERVED2[40];
+  __IO uint32_t MMCCR;                 /*   65 */
+  __IO uint32_t MMCRIR;
+  __IO uint32_t MMCTIR;
+  __IO uint32_t MMCRIMR;
+  __IO uint32_t MMCTIMR;               /*   69 */
+  uint32_t      RESERVED3[14];
+  __IO uint32_t MMCTGFSCCR;            /*   84 */
+  __IO uint32_t MMCTGFMSCCR;
+  uint32_t      RESERVED4[5];
+  __IO uint32_t MMCTGFCR;
+  uint32_t      RESERVED5[10];
+  __IO uint32_t MMCRFCECR;
+  __IO uint32_t MMCRFAECR;
+  uint32_t      RESERVED6[10];
+  __IO uint32_t MMCRGUFCR;
+  uint32_t      RESERVED7[334];
+  __IO uint32_t PTPTSCR;
+  __IO uint32_t PTPSSIR;
+  __IO uint32_t PTPTSHR;
+  __IO uint32_t PTPTSLR;
+  __IO uint32_t PTPTSHUR;
+  __IO uint32_t PTPTSLUR;
+  __IO uint32_t PTPTSAR;
+  __IO uint32_t PTPTTHR;
+  __IO uint32_t PTPTTLR;
+  __IO uint32_t RESERVED8;
+  __IO uint32_t PTPTSSR;
+  uint32_t      RESERVED9[565];
+  __IO uint32_t DMABMR;
+  __IO uint32_t DMATPDR;
+  __IO uint32_t DMARPDR;
+  __IO uint32_t DMARDLAR;
+  __IO uint32_t DMATDLAR;
+  __IO uint32_t DMASR;
+  __IO uint32_t DMAOMR;
+  __IO uint32_t DMAIER;
+  __IO uint32_t DMAMFBOCR;
+  __IO uint32_t DMARSWTR;
+  uint32_t      RESERVED10[8];
+  __IO uint32_t DMACHTDR;
+  __IO uint32_t DMACHRDR;
+  __IO uint32_t DMACHTBAR;
+  __IO uint32_t DMACHRBAR;
+} ETH_TypeDef;
+
+/** 
+  * @brief External Interrupt/Event Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t IMR;    /*!< EXTI Interrupt mask register,            Address offset: 0x00 */
+  __IO uint32_t EMR;    /*!< EXTI Event mask register,                Address offset: 0x04 */
+  __IO uint32_t RTSR;   /*!< EXTI Rising trigger selection register,  Address offset: 0x08 */
+  __IO uint32_t FTSR;   /*!< EXTI Falling trigger selection register, Address offset: 0x0C */
+  __IO uint32_t SWIER;  /*!< EXTI Software interrupt event register,  Address offset: 0x10 */
+  __IO uint32_t PR;     /*!< EXTI Pending register,                   Address offset: 0x14 */
+} EXTI_TypeDef;
+
+/** 
+  * @brief FLASH Registers
+  */
+
+typedef struct
+{
+  __IO uint32_t ACR;      /*!< FLASH access control register, Address offset: 0x00 */
+  __IO uint32_t KEYR;     /*!< FLASH key register,            Address offset: 0x04 */
+  __IO uint32_t OPTKEYR;  /*!< FLASH option key register,     Address offset: 0x08 */
+  __IO uint32_t SR;       /*!< FLASH status register,         Address offset: 0x0C */
+  __IO uint32_t CR;       /*!< FLASH control register,        Address offset: 0x10 */
+  __IO uint32_t OPTCR;    /*!< FLASH option control register, Address offset: 0x14 */
+} FLASH_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller
+  */
+
+typedef struct
+{
+  __IO uint32_t BTCR[8];    /*!< NOR/PSRAM chip-select control register(BCR) and chip-select timing register(BTR), Address offset: 0x00-1C */   
+} FSMC_Bank1_TypeDef; 
+
+/** 
+  * @brief Flexible Static Memory Controller Bank1E
+  */
+  
+typedef struct
+{
+  __IO uint32_t BWTR[7];    /*!< NOR/PSRAM write timing registers, Address offset: 0x104-0x11C */
+} FSMC_Bank1E_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller Bank2
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR2;       /*!< NAND Flash control register 2,                       Address offset: 0x60 */
+  __IO uint32_t SR2;        /*!< NAND Flash FIFO status and interrupt register 2,     Address offset: 0x64 */
+  __IO uint32_t PMEM2;      /*!< NAND Flash Common memory space timing register 2,    Address offset: 0x68 */
+  __IO uint32_t PATT2;      /*!< NAND Flash Attribute memory space timing register 2, Address offset: 0x6C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x70                                                            */
+  __IO uint32_t ECCR2;      /*!< NAND Flash ECC result registers 2,                   Address offset: 0x74 */
+} FSMC_Bank2_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller Bank3
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR3;       /*!< NAND Flash control register 3,                       Address offset: 0x80 */
+  __IO uint32_t SR3;        /*!< NAND Flash FIFO status and interrupt register 3,     Address offset: 0x84 */
+  __IO uint32_t PMEM3;      /*!< NAND Flash Common memory space timing register 3,    Address offset: 0x88 */
+  __IO uint32_t PATT3;      /*!< NAND Flash Attribute memory space timing register 3, Address offset: 0x8C */
+  uint32_t      RESERVED0;  /*!< Reserved, 0x90                                                            */
+  __IO uint32_t ECCR3;      /*!< NAND Flash ECC result registers 3,                   Address offset: 0x94 */
+} FSMC_Bank3_TypeDef;
+
+/** 
+  * @brief Flexible Static Memory Controller Bank4
+  */
+  
+typedef struct
+{
+  __IO uint32_t PCR4;       /*!< PC Card  control register 4,                       Address offset: 0xA0 */
+  __IO uint32_t SR4;        /*!< PC Card  FIFO status and interrupt register 4,     Address offset: 0xA4 */
+  __IO uint32_t PMEM4;      /*!< PC Card  Common memory space timing register 4,    Address offset: 0xA8 */
+  __IO uint32_t PATT4;      /*!< PC Card  Attribute memory space timing register 4, Address offset: 0xAC */
+  __IO uint32_t PIO4;       /*!< PC Card  I/O space timing register 4,              Address offset: 0xB0 */
+} FSMC_Bank4_TypeDef; 
+
+/** 
+  * @brief General Purpose I/O
+  */
+
+typedef struct
+{
+  __IO uint32_t MODER;    /*!< GPIO port mode register,               Address offset: 0x00      */
+  __IO uint32_t OTYPER;   /*!< GPIO port output type register,        Address offset: 0x04      */
+  __IO uint32_t OSPEEDR;  /*!< GPIO port output speed register,       Address offset: 0x08      */
+  __IO uint32_t PUPDR;    /*!< GPIO port pull-up/pull-down register,  Address offset: 0x0C      */
+  __IO uint32_t IDR;      /*!< GPIO port input data register,         Address offset: 0x10      */
+  __IO uint32_t ODR;      /*!< GPIO port output data register,        Address offset: 0x14      */
+  __IO uint16_t BSRRL;    /*!< GPIO port bit set/reset low register,  Address offset: 0x18      */
+  __IO uint16_t BSRRH;    /*!< GPIO port bit set/reset high register, Address offset: 0x1A      */
+  __IO uint32_t LCKR;     /*!< GPIO port configuration lock register, Address offset: 0x1C      */
+  __IO uint32_t AFR[2];   /*!< GPIO alternate function registers,     Address offset: 0x24-0x28 */
+} GPIO_TypeDef;
+
+/** 
+  * @brief System configuration controller
+  */
+  
+typedef struct
+{
+  __IO uint32_t MEMRMP;       /*!< SYSCFG memory remap register,                      Address offset: 0x00      */
+  __IO uint32_t PMC;          /*!< SYSCFG peripheral mode configuration register,     Address offset: 0x04      */
+  __IO uint32_t EXTICR[4];    /*!< SYSCFG external interrupt configuration registers, Address offset: 0x08-0x14 */
+  uint32_t      RESERVED[2];  /*!< Reserved, 0x18-0x1C                                                          */ 
+  __IO uint32_t CMPCR;        /*!< SYSCFG Compensation cell control register,         Address offset: 0x20      */
+} SYSCFG_TypeDef;
+
+/** 
+  * @brief Inter-integrated Circuit Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;        /*!< I2C Control register 1,     Address offset: 0x00 */
+  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                   */
+  __IO uint16_t CR2;        /*!< I2C Control register 2,     Address offset: 0x04 */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                   */
+  __IO uint16_t OAR1;       /*!< I2C Own address register 1, Address offset: 0x08 */
+  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                   */
+  __IO uint16_t OAR2;       /*!< I2C Own address register 2, Address offset: 0x0C */
+  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                   */
+  __IO uint16_t DR;         /*!< I2C Data register,          Address offset: 0x10 */
+  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                   */
+  __IO uint16_t SR1;        /*!< I2C Status register 1,      Address offset: 0x14 */
+  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                   */
+  __IO uint16_t SR2;        /*!< I2C Status register 2,      Address offset: 0x18 */
+  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                   */
+  __IO uint16_t CCR;        /*!< I2C Clock control register, Address offset: 0x1C */
+  uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                   */
+  __IO uint16_t TRISE;      /*!< I2C TRISE register,         Address offset: 0x20 */
+  uint16_t      RESERVED8;  /*!< Reserved, 0x22                                   */
+} I2C_TypeDef;
+
+/** 
+  * @brief Independent WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t KR;   /*!< IWDG Key register,       Address offset: 0x00 */
+  __IO uint32_t PR;   /*!< IWDG Prescaler register, Address offset: 0x04 */
+  __IO uint32_t RLR;  /*!< IWDG Reload register,    Address offset: 0x08 */
+  __IO uint32_t SR;   /*!< IWDG Status register,    Address offset: 0x0C */
+} IWDG_TypeDef;
+
+/** 
+  * @brief Power Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< PWR power control register,        Address offset: 0x00 */
+  __IO uint32_t CSR;  /*!< PWR power control/status register, Address offset: 0x04 */
+} PWR_TypeDef;
+
+/** 
+  * @brief Reset and Clock Control
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;            /*!< RCC clock control register,                                  Address offset: 0x00 */
+  __IO uint32_t PLLCFGR;       /*!< RCC PLL configuration register,                              Address offset: 0x04 */
+  __IO uint32_t CFGR;          /*!< RCC clock configuration register,                            Address offset: 0x08 */
+  __IO uint32_t CIR;           /*!< RCC clock interrupt register,                                Address offset: 0x0C */
+  __IO uint32_t AHB1RSTR;      /*!< RCC AHB1 peripheral reset register,                          Address offset: 0x10 */
+  __IO uint32_t AHB2RSTR;      /*!< RCC AHB2 peripheral reset register,                          Address offset: 0x14 */
+  __IO uint32_t AHB3RSTR;      /*!< RCC AHB3 peripheral reset register,                          Address offset: 0x18 */
+  uint32_t      RESERVED0;     /*!< Reserved, 0x1C                                                                    */
+  __IO uint32_t APB1RSTR;      /*!< RCC APB1 peripheral reset register,                          Address offset: 0x20 */
+  __IO uint32_t APB2RSTR;      /*!< RCC APB2 peripheral reset register,                          Address offset: 0x24 */
+  uint32_t      RESERVED1[2];  /*!< Reserved, 0x28-0x2C                                                               */
+  __IO uint32_t AHB1ENR;       /*!< RCC AHB1 peripheral clock register,                          Address offset: 0x30 */
+  __IO uint32_t AHB2ENR;       /*!< RCC AHB2 peripheral clock register,                          Address offset: 0x34 */
+  __IO uint32_t AHB3ENR;       /*!< RCC AHB3 peripheral clock register,                          Address offset: 0x38 */
+  uint32_t      RESERVED2;     /*!< Reserved, 0x3C                                                                    */
+  __IO uint32_t APB1ENR;       /*!< RCC APB1 peripheral clock enable register,                   Address offset: 0x40 */
+  __IO uint32_t APB2ENR;       /*!< RCC APB2 peripheral clock enable register,                   Address offset: 0x44 */
+  uint32_t      RESERVED3[2];  /*!< Reserved, 0x48-0x4C                                                               */
+  __IO uint32_t AHB1LPENR;     /*!< RCC AHB1 peripheral clock enable in low power mode register, Address offset: 0x50 */
+  __IO uint32_t AHB2LPENR;     /*!< RCC AHB2 peripheral clock enable in low power mode register, Address offset: 0x54 */
+  __IO uint32_t AHB3LPENR;     /*!< RCC AHB3 peripheral clock enable in low power mode register, Address offset: 0x58 */
+  uint32_t      RESERVED4;     /*!< Reserved, 0x5C                                                                    */
+  __IO uint32_t APB1LPENR;     /*!< RCC APB1 peripheral clock enable in low power mode register, Address offset: 0x60 */
+  __IO uint32_t APB2LPENR;     /*!< RCC APB2 peripheral clock enable in low power mode register, Address offset: 0x64 */
+  uint32_t      RESERVED5[2];  /*!< Reserved, 0x68-0x6C                                                               */
+  __IO uint32_t BDCR;          /*!< RCC Backup domain control register,                          Address offset: 0x70 */
+  __IO uint32_t CSR;           /*!< RCC clock control & status register,                         Address offset: 0x74 */
+  uint32_t      RESERVED6[2];  /*!< Reserved, 0x78-0x7C                                                               */
+  __IO uint32_t SSCGR;         /*!< RCC spread spectrum clock generation register,               Address offset: 0x80 */
+  __IO uint32_t PLLI2SCFGR;    /*!< RCC PLLI2S configuration register,                           Address offset: 0x84 */
+} RCC_TypeDef;
+
+/** 
+  * @brief Real-Time Clock
+  */
+
+typedef struct
+{
+  __IO uint32_t TR;      /*!< RTC time register,                                        Address offset: 0x00 */
+  __IO uint32_t DR;      /*!< RTC date register,                                        Address offset: 0x04 */
+  __IO uint32_t CR;      /*!< RTC control register,                                     Address offset: 0x08 */
+  __IO uint32_t ISR;     /*!< RTC initialization and status register,                   Address offset: 0x0C */
+  __IO uint32_t PRER;    /*!< RTC prescaler register,                                   Address offset: 0x10 */
+  __IO uint32_t WUTR;    /*!< RTC wakeup timer register,                                Address offset: 0x14 */
+  __IO uint32_t CALIBR;  /*!< RTC calibration register,                                 Address offset: 0x18 */
+  __IO uint32_t ALRMAR;  /*!< RTC alarm A register,                                     Address offset: 0x1C */
+  __IO uint32_t ALRMBR;  /*!< RTC alarm B register,                                     Address offset: 0x20 */
+  __IO uint32_t WPR;     /*!< RTC write protection register,                            Address offset: 0x24 */
+  __IO uint32_t SSR;       /*!< RTC sub second register,                                  Address offset: 0x28                                                                 */
+  __IO uint32_t SHIFTR;    /*!< RTC shift control register,                               Address offset: 0x2C                                                                 */
+  __IO uint32_t TSTR;      /*!< RTC time stamp time register,                             Address offset: 0x30 */
+  __IO uint32_t TSDR;      /*!< RTC time stamp date register,                             Address offset: 0x34 */
+  __IO uint32_t TSSSR;     /*!< RTC time-stamp sub second register,                       Address offset: 0x38                                                                 */
+  __IO uint32_t CALR;      /*!< RTC calibration register,                                 Address offset: 0x3C                                                                 */
+  __IO uint32_t TAFCR;     /*!< RTC tamper and alternate function configuration register, Address offset: 0x40 */
+  __IO uint32_t ALRMASSR;  /*!< RTC alarm A sub second register,                          Address offset: 0x44                                                                 */
+  __IO uint32_t ALRMBSSR;  /*!< RTC alarm B sub second register,                          Address offset: 0x48                                                                 */
+  uint32_t RESERVED7;    /*!< Reserved, 0x4C                                                                 */
+  __IO uint32_t BKP0R;   /*!< RTC backup register 1,                                    Address offset: 0x50 */
+  __IO uint32_t BKP1R;   /*!< RTC backup register 1,                                    Address offset: 0x54 */
+  __IO uint32_t BKP2R;   /*!< RTC backup register 2,                                    Address offset: 0x58 */
+  __IO uint32_t BKP3R;   /*!< RTC backup register 3,                                    Address offset: 0x5C */
+  __IO uint32_t BKP4R;   /*!< RTC backup register 4,                                    Address offset: 0x60 */
+  __IO uint32_t BKP5R;   /*!< RTC backup register 5,                                    Address offset: 0x64 */
+  __IO uint32_t BKP6R;   /*!< RTC backup register 6,                                    Address offset: 0x68 */
+  __IO uint32_t BKP7R;   /*!< RTC backup register 7,                                    Address offset: 0x6C */
+  __IO uint32_t BKP8R;   /*!< RTC backup register 8,                                    Address offset: 0x70 */
+  __IO uint32_t BKP9R;   /*!< RTC backup register 9,                                    Address offset: 0x74 */
+  __IO uint32_t BKP10R;  /*!< RTC backup register 10,                                   Address offset: 0x78 */
+  __IO uint32_t BKP11R;  /*!< RTC backup register 11,                                   Address offset: 0x7C */
+  __IO uint32_t BKP12R;  /*!< RTC backup register 12,                                   Address offset: 0x80 */
+  __IO uint32_t BKP13R;  /*!< RTC backup register 13,                                   Address offset: 0x84 */
+  __IO uint32_t BKP14R;  /*!< RTC backup register 14,                                   Address offset: 0x88 */
+  __IO uint32_t BKP15R;  /*!< RTC backup register 15,                                   Address offset: 0x8C */
+  __IO uint32_t BKP16R;  /*!< RTC backup register 16,                                   Address offset: 0x90 */
+  __IO uint32_t BKP17R;  /*!< RTC backup register 17,                                   Address offset: 0x94 */
+  __IO uint32_t BKP18R;  /*!< RTC backup register 18,                                   Address offset: 0x98 */
+  __IO uint32_t BKP19R;  /*!< RTC backup register 19,                                   Address offset: 0x9C */
+} RTC_TypeDef;
+
+/** 
+  * @brief SD host Interface
+  */
+
+typedef struct
+{
+  __IO uint32_t POWER;          /*!< SDIO power control register,    Address offset: 0x00 */
+  __IO uint32_t CLKCR;          /*!< SDI clock control register,     Address offset: 0x04 */
+  __IO uint32_t ARG;            /*!< SDIO argument register,         Address offset: 0x08 */
+  __IO uint32_t CMD;            /*!< SDIO command register,          Address offset: 0x0C */
+  __I uint32_t  RESPCMD;        /*!< SDIO command response register, Address offset: 0x10 */
+  __I uint32_t  RESP1;          /*!< SDIO response 1 register,       Address offset: 0x14 */
+  __I uint32_t  RESP2;          /*!< SDIO response 2 register,       Address offset: 0x18 */
+  __I uint32_t  RESP3;          /*!< SDIO response 3 register,       Address offset: 0x1C */
+  __I uint32_t  RESP4;          /*!< SDIO response 4 register,       Address offset: 0x20 */
+  __IO uint32_t DTIMER;         /*!< SDIO data timer register,       Address offset: 0x24 */
+  __IO uint32_t DLEN;           /*!< SDIO data length register,      Address offset: 0x28 */
+  __IO uint32_t DCTRL;          /*!< SDIO data control register,     Address offset: 0x2C */
+  __I uint32_t  DCOUNT;         /*!< SDIO data counter register,     Address offset: 0x30 */
+  __I uint32_t  STA;            /*!< SDIO status register,           Address offset: 0x34 */
+  __IO uint32_t ICR;            /*!< SDIO interrupt clear register,  Address offset: 0x38 */
+  __IO uint32_t MASK;           /*!< SDIO mask register,             Address offset: 0x3C */
+  uint32_t      RESERVED0[2];   /*!< Reserved, 0x40-0x44                                  */
+  __I uint32_t  FIFOCNT;        /*!< SDIO FIFO counter register,     Address offset: 0x48 */
+  uint32_t      RESERVED1[13];  /*!< Reserved, 0x4C-0x7C                                  */
+  __IO uint32_t FIFO;           /*!< SDIO data FIFO register,        Address offset: 0x80 */
+} SDIO_TypeDef;
+
+/** 
+  * @brief Serial Peripheral Interface
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;        /*!< SPI control register 1 (not used in I2S mode),      Address offset: 0x00 */
+  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                           */
+  __IO uint16_t CR2;        /*!< SPI control register 2,                             Address offset: 0x04 */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                           */
+  __IO uint16_t SR;         /*!< SPI status register,                                Address offset: 0x08 */
+  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                           */
+  __IO uint16_t DR;         /*!< SPI data register,                                  Address offset: 0x0C */
+  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                           */
+  __IO uint16_t CRCPR;      /*!< SPI CRC polynomial register (not used in I2S mode), Address offset: 0x10 */
+  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                           */
+  __IO uint16_t RXCRCR;     /*!< SPI RX CRC register (not used in I2S mode),         Address offset: 0x14 */
+  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                           */
+  __IO uint16_t TXCRCR;     /*!< SPI TX CRC register (not used in I2S mode),         Address offset: 0x18 */
+  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                           */
+  __IO uint16_t I2SCFGR;    /*!< SPI_I2S configuration register,                     Address offset: 0x1C */
+  uint16_t      RESERVED7;  /*!< Reserved, 0x1E                                                           */
+  __IO uint16_t I2SPR;      /*!< SPI_I2S prescaler register,                         Address offset: 0x20 */
+  uint16_t      RESERVED8;  /*!< Reserved, 0x22                                                           */
+} SPI_TypeDef;
+
+/** 
+  * @brief TIM
+  */
+
+typedef struct
+{
+  __IO uint16_t CR1;         /*!< TIM control register 1,              Address offset: 0x00 */
+  uint16_t      RESERVED0;   /*!< Reserved, 0x02                                            */
+  __IO uint16_t CR2;         /*!< TIM control register 2,              Address offset: 0x04 */
+  uint16_t      RESERVED1;   /*!< Reserved, 0x06                                            */
+  __IO uint16_t SMCR;        /*!< TIM slave mode control register,     Address offset: 0x08 */
+  uint16_t      RESERVED2;   /*!< Reserved, 0x0A                                            */
+  __IO uint16_t DIER;        /*!< TIM DMA/interrupt enable register,   Address offset: 0x0C */
+  uint16_t      RESERVED3;   /*!< Reserved, 0x0E                                            */
+  __IO uint16_t SR;          /*!< TIM status register,                 Address offset: 0x10 */
+  uint16_t      RESERVED4;   /*!< Reserved, 0x12                                            */
+  __IO uint16_t EGR;         /*!< TIM event generation register,       Address offset: 0x14 */
+  uint16_t      RESERVED5;   /*!< Reserved, 0x16                                            */
+  __IO uint16_t CCMR1;       /*!< TIM capture/compare mode register 1, Address offset: 0x18 */
+  uint16_t      RESERVED6;   /*!< Reserved, 0x1A                                            */
+  __IO uint16_t CCMR2;       /*!< TIM capture/compare mode register 2, Address offset: 0x1C */
+  uint16_t      RESERVED7;   /*!< Reserved, 0x1E                                            */
+  __IO uint16_t CCER;        /*!< TIM capture/compare enable register, Address offset: 0x20 */
+  uint16_t      RESERVED8;   /*!< Reserved, 0x22                                            */
+  __IO uint32_t CNT;         /*!< TIM counter register,                Address offset: 0x24 */
+  __IO uint16_t PSC;         /*!< TIM prescaler,                       Address offset: 0x28 */
+  uint16_t      RESERVED9;   /*!< Reserved, 0x2A                                            */
+  __IO uint32_t ARR;         /*!< TIM auto-reload register,            Address offset: 0x2C */
+  __IO uint16_t RCR;         /*!< TIM repetition counter register,     Address offset: 0x30 */
+  uint16_t      RESERVED10;  /*!< Reserved, 0x32                                            */
+  __IO uint32_t CCR1;        /*!< TIM capture/compare register 1,      Address offset: 0x34 */
+  __IO uint32_t CCR2;        /*!< TIM capture/compare register 2,      Address offset: 0x38 */
+  __IO uint32_t CCR3;        /*!< TIM capture/compare register 3,      Address offset: 0x3C */
+  __IO uint32_t CCR4;        /*!< TIM capture/compare register 4,      Address offset: 0x40 */
+  __IO uint16_t BDTR;        /*!< TIM break and dead-time register,    Address offset: 0x44 */
+  uint16_t      RESERVED11;  /*!< Reserved, 0x46                                            */
+  __IO uint16_t DCR;         /*!< TIM DMA control register,            Address offset: 0x48 */
+  uint16_t      RESERVED12;  /*!< Reserved, 0x4A                                            */
+  __IO uint16_t DMAR;        /*!< TIM DMA address for full transfer,   Address offset: 0x4C */
+  uint16_t      RESERVED13;  /*!< Reserved, 0x4E                                            */
+  __IO uint16_t OR;          /*!< TIM option register,                 Address offset: 0x50 */
+  uint16_t      RESERVED14;  /*!< Reserved, 0x52                                            */
+} TIM_TypeDef;
+
+/** 
+  * @brief Universal Synchronous Asynchronous Receiver Transmitter
+  */
+ 
+typedef struct
+{
+  __IO uint16_t SR;         /*!< USART Status register,                   Address offset: 0x00 */
+  uint16_t      RESERVED0;  /*!< Reserved, 0x02                                                */
+  __IO uint16_t DR;         /*!< USART Data register,                     Address offset: 0x04 */
+  uint16_t      RESERVED1;  /*!< Reserved, 0x06                                                */
+  __IO uint16_t BRR;        /*!< USART Baud rate register,                Address offset: 0x08 */
+  uint16_t      RESERVED2;  /*!< Reserved, 0x0A                                                */
+  __IO uint16_t CR1;        /*!< USART Control register 1,                Address offset: 0x0C */
+  uint16_t      RESERVED3;  /*!< Reserved, 0x0E                                                */
+  __IO uint16_t CR2;        /*!< USART Control register 2,                Address offset: 0x10 */
+  uint16_t      RESERVED4;  /*!< Reserved, 0x12                                                */
+  __IO uint16_t CR3;        /*!< USART Control register 3,                Address offset: 0x14 */
+  uint16_t      RESERVED5;  /*!< Reserved, 0x16                                                */
+  __IO uint16_t GTPR;       /*!< USART Guard time and prescaler register, Address offset: 0x18 */
+  uint16_t      RESERVED6;  /*!< Reserved, 0x1A                                                */
+} USART_TypeDef;
+
+/** 
+  * @brief Window WATCHDOG
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;   /*!< WWDG Control register,       Address offset: 0x00 */
+  __IO uint32_t CFR;  /*!< WWDG Configuration register, Address offset: 0x04 */
+  __IO uint32_t SR;   /*!< WWDG Status register,        Address offset: 0x08 */
+} WWDG_TypeDef;
+
+/** 
+  * @brief Crypto Processor
+  */
+
+typedef struct
+{
+  __IO uint32_t CR;     /*!< CRYP control register,                            Address offset: 0x00 */
+  __IO uint32_t SR;     /*!< CRYP status register,                             Address offset: 0x04 */
+  __IO uint32_t DR;     /*!< CRYP data input register,                         Address offset: 0x08 */
+  __IO uint32_t DOUT;   /*!< CRYP data output register,                        Address offset: 0x0C */
+  __IO uint32_t DMACR;  /*!< CRYP DMA control register,                        Address offset: 0x10 */
+  __IO uint32_t IMSCR;  /*!< CRYP interrupt mask set/clear register,           Address offset: 0x14 */
+  __IO uint32_t RISR;   /*!< CRYP raw interrupt status register,               Address offset: 0x18 */
+  __IO uint32_t MISR;   /*!< CRYP masked interrupt status register,            Address offset: 0x1C */
+  __IO uint32_t K0LR;   /*!< CRYP key left  register 0,                        Address offset: 0x20 */
+  __IO uint32_t K0RR;   /*!< CRYP key right register 0,                        Address offset: 0x24 */
+  __IO uint32_t K1LR;   /*!< CRYP key left  register 1,                        Address offset: 0x28 */
+  __IO uint32_t K1RR;   /*!< CRYP key right register 1,                        Address offset: 0x2C */
+  __IO uint32_t K2LR;   /*!< CRYP key left  register 2,                        Address offset: 0x30 */
+  __IO uint32_t K2RR;   /*!< CRYP key right register 2,                        Address offset: 0x34 */
+  __IO uint32_t K3LR;   /*!< CRYP key left  register 3,                        Address offset: 0x38 */
+  __IO uint32_t K3RR;   /*!< CRYP key right register 3,                        Address offset: 0x3C */
+  __IO uint32_t IV0LR;  /*!< CRYP initialization vector left-word  register 0, Address offset: 0x40 */
+  __IO uint32_t IV0RR;  /*!< CRYP initialization vector right-word register 0, Address offset: 0x44 */
+  __IO uint32_t IV1LR;  /*!< CRYP initialization vector left-word  register 1, Address offset: 0x48 */
+  __IO uint32_t IV1RR;  /*!< CRYP initialization vector right-word register 1, Address offset: 0x4C */
+} CRYP_TypeDef;
+
+/** 
+  * @brief HASH
+  */
+  
+typedef struct 
+{
+  __IO uint32_t CR;        /*!< HASH control register,          Address offset: 0x00        */
+  __IO uint32_t DIN;       /*!< HASH data input register,       Address offset: 0x04        */
+  __IO uint32_t STR;       /*!< HASH start register,            Address offset: 0x08        */
+  __IO uint32_t HR[5];     /*!< HASH digest registers,          Address offset: 0x0C-0x1C   */
+  __IO uint32_t IMR;       /*!< HASH interrupt enable register, Address offset: 0x20        */
+  __IO uint32_t SR;        /*!< HASH status register,           Address offset: 0x24        */
+  uint32_t  RESERVED[52];  /*!< Reserved, 0x28-0xF4                                         */
+  __IO uint32_t CSR[51];   /*!< HASH context swap registers,    Address offset: 0x0F8-0x1C0 */  
+} HASH_TypeDef;
+
+/** 
+  * @brief HASH
+  */
+  
+typedef struct 
+{
+  __IO uint32_t CR;  /*!< RNG control register, Address offset: 0x00 */
+  __IO uint32_t SR;  /*!< RNG status register,  Address offset: 0x04 */
+  __IO uint32_t DR;  /*!< RNG data register,    Address offset: 0x08 */
+} RNG_TypeDef;
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_memory_map
+  * @{
+  */
+
+#define FLASH_BASE            ((uint32_t)0x08000000) /*!< FLASH base address in the alias region */
+#define SRAM_BASE             ((uint32_t)0x20000000) /*!< SRAM base address in the alias region */
+#define PERIPH_BASE           ((uint32_t)0x40000000) /*!< Peripheral base address in the alias region */
+
+#define SRAM_BB_BASE          ((uint32_t)0x22000000) /*!< SRAM base address in the bit-band region */
+#define PERIPH_BB_BASE        ((uint32_t)0x42000000) /*!< Peripheral base address in the bit-band region */
+
+#define FSMC_R_BASE           ((uint32_t)0xA0000000) /*!< FSMC registers base address */
+
+/*!< Peripheral memory map */
+#define APB1PERIPH_BASE       PERIPH_BASE
+#define APB2PERIPH_BASE       (PERIPH_BASE + 0x00010000)
+#define AHB1PERIPH_BASE       (PERIPH_BASE + 0x00020000)
+#define AHB2PERIPH_BASE       (PERIPH_BASE + 0x10000000)
+
+/*!< APB1 peripherals */
+#define TIM2_BASE             (APB1PERIPH_BASE + 0x0000)
+#define TIM3_BASE             (APB1PERIPH_BASE + 0x0400)
+#define TIM4_BASE             (APB1PERIPH_BASE + 0x0800)
+#define TIM5_BASE             (APB1PERIPH_BASE + 0x0C00)
+#define TIM6_BASE             (APB1PERIPH_BASE + 0x1000)
+#define TIM7_BASE             (APB1PERIPH_BASE + 0x1400)
+#define TIM12_BASE            (APB1PERIPH_BASE + 0x1800)
+#define TIM13_BASE            (APB1PERIPH_BASE + 0x1C00)
+#define TIM14_BASE            (APB1PERIPH_BASE + 0x2000)
+#define RTC_BASE              (APB1PERIPH_BASE + 0x2800)
+#define WWDG_BASE             (APB1PERIPH_BASE + 0x2C00)
+#define IWDG_BASE             (APB1PERIPH_BASE + 0x3000)
+#define I2S2ext_BASE          (APB1PERIPH_BASE + 0x3400)
+#define SPI2_BASE             (APB1PERIPH_BASE + 0x3800)
+#define SPI3_BASE             (APB1PERIPH_BASE + 0x3C00)
+#define I2S3ext_BASE          (APB1PERIPH_BASE + 0x4000)
+#define USART2_BASE           (APB1PERIPH_BASE + 0x4400)
+#define USART3_BASE           (APB1PERIPH_BASE + 0x4800)
+#define UART4_BASE            (APB1PERIPH_BASE + 0x4C00)
+#define UART5_BASE            (APB1PERIPH_BASE + 0x5000)
+#define I2C1_BASE             (APB1PERIPH_BASE + 0x5400)
+#define I2C2_BASE             (APB1PERIPH_BASE + 0x5800)
+#define I2C3_BASE             (APB1PERIPH_BASE + 0x5C00)
+#define CAN1_BASE             (APB1PERIPH_BASE + 0x6400)
+#define CAN2_BASE             (APB1PERIPH_BASE + 0x6800)
+#define PWR_BASE              (APB1PERIPH_BASE + 0x7000)
+#define DAC_BASE              (APB1PERIPH_BASE + 0x7400)
+
+/*!< APB2 peripherals */
+#define TIM1_BASE             (APB2PERIPH_BASE + 0x0000)
+#define TIM8_BASE             (APB2PERIPH_BASE + 0x0400)
+#define USART1_BASE           (APB2PERIPH_BASE + 0x1000)
+#define USART6_BASE           (APB2PERIPH_BASE + 0x1400)
+#define ADC1_BASE             (APB2PERIPH_BASE + 0x2000)
+#define ADC2_BASE             (APB2PERIPH_BASE + 0x2100)
+#define ADC3_BASE             (APB2PERIPH_BASE + 0x2200)
+#define ADC_BASE              (APB2PERIPH_BASE + 0x2300)
+#define SDIO_BASE             (APB2PERIPH_BASE + 0x2C00)
+#define SPI1_BASE             (APB2PERIPH_BASE + 0x3000)
+#define SYSCFG_BASE           (APB2PERIPH_BASE + 0x3800)
+#define EXTI_BASE             (APB2PERIPH_BASE + 0x3C00)
+#define TIM9_BASE             (APB2PERIPH_BASE + 0x4000)
+#define TIM10_BASE            (APB2PERIPH_BASE + 0x4400)
+#define TIM11_BASE            (APB2PERIPH_BASE + 0x4800)
+
+/*!< AHB1 peripherals */
+#define GPIOA_BASE            (AHB1PERIPH_BASE + 0x0000)
+#define GPIOB_BASE            (AHB1PERIPH_BASE + 0x0400)
+#define GPIOC_BASE            (AHB1PERIPH_BASE + 0x0800)
+#define GPIOD_BASE            (AHB1PERIPH_BASE + 0x0C00)
+#define GPIOE_BASE            (AHB1PERIPH_BASE + 0x1000)
+#define GPIOF_BASE            (AHB1PERIPH_BASE + 0x1400)
+#define GPIOG_BASE            (AHB1PERIPH_BASE + 0x1800)
+#define GPIOH_BASE            (AHB1PERIPH_BASE + 0x1C00)
+#define GPIOI_BASE            (AHB1PERIPH_BASE + 0x2000)
+#define CRC_BASE              (AHB1PERIPH_BASE + 0x3000)
+#define RCC_BASE              (AHB1PERIPH_BASE + 0x3800)
+#define FLASH_R_BASE          (AHB1PERIPH_BASE + 0x3C00) 
+#define BKPSRAM_BASE          (AHB1PERIPH_BASE + 0x4000)
+#define DMA1_BASE             (AHB1PERIPH_BASE + 0x6000)
+#define DMA1_Stream0_BASE     (DMA1_BASE + 0x010)
+#define DMA1_Stream1_BASE     (DMA1_BASE + 0x028)
+#define DMA1_Stream2_BASE     (DMA1_BASE + 0x040)
+#define DMA1_Stream3_BASE     (DMA1_BASE + 0x058)
+#define DMA1_Stream4_BASE     (DMA1_BASE + 0x070)
+#define DMA1_Stream5_BASE     (DMA1_BASE + 0x088)
+#define DMA1_Stream6_BASE     (DMA1_BASE + 0x0A0)
+#define DMA1_Stream7_BASE     (DMA1_BASE + 0x0B8)
+#define DMA2_BASE             (AHB1PERIPH_BASE + 0x6400)
+#define DMA2_Stream0_BASE     (DMA2_BASE + 0x010)
+#define DMA2_Stream1_BASE     (DMA2_BASE + 0x028)
+#define DMA2_Stream2_BASE     (DMA2_BASE + 0x040)
+#define DMA2_Stream3_BASE     (DMA2_BASE + 0x058)
+#define DMA2_Stream4_BASE     (DMA2_BASE + 0x070)
+#define DMA2_Stream5_BASE     (DMA2_BASE + 0x088)
+#define DMA2_Stream6_BASE     (DMA2_BASE + 0x0A0)
+#define DMA2_Stream7_BASE     (DMA2_BASE + 0x0B8)
+#define ETH_BASE              (AHB1PERIPH_BASE + 0x8000)
+#define ETH_MAC_BASE          (ETH_BASE)
+#define ETH_MMC_BASE          (ETH_BASE + 0x0100)
+#define ETH_PTP_BASE          (ETH_BASE + 0x0700)
+#define ETH_DMA_BASE          (ETH_BASE + 0x1000)
+
+/*!< AHB2 peripherals */
+#define DCMI_BASE             (AHB2PERIPH_BASE + 0x50000)
+#define CRYP_BASE             (AHB2PERIPH_BASE + 0x60000)
+#define HASH_BASE             (AHB2PERIPH_BASE + 0x60400)
+#define RNG_BASE              (AHB2PERIPH_BASE + 0x60800)
+
+/*!< FSMC Bankx registers base address */
+#define FSMC_Bank1_R_BASE     (FSMC_R_BASE + 0x0000)
+#define FSMC_Bank1E_R_BASE    (FSMC_R_BASE + 0x0104)
+#define FSMC_Bank2_R_BASE     (FSMC_R_BASE + 0x0060)
+#define FSMC_Bank3_R_BASE     (FSMC_R_BASE + 0x0080)
+#define FSMC_Bank4_R_BASE     (FSMC_R_BASE + 0x00A0)
+
+/* Debug MCU registers base address */
+#define DBGMCU_BASE           ((uint32_t )0xE0042000)
+
+/**
+  * @}
+  */
+  
+/** @addtogroup Peripheral_declaration
+  * @{
+  */  
+#define TIM2                ((TIM_TypeDef *) TIM2_BASE)
+#define TIM3                ((TIM_TypeDef *) TIM3_BASE)
+#define TIM4                ((TIM_TypeDef *) TIM4_BASE)
+#define TIM5                ((TIM_TypeDef *) TIM5_BASE)
+#define TIM6                ((TIM_TypeDef *) TIM6_BASE)
+#define TIM7                ((TIM_TypeDef *) TIM7_BASE)
+#define TIM12               ((TIM_TypeDef *) TIM12_BASE)
+#define TIM13               ((TIM_TypeDef *) TIM13_BASE)
+#define TIM14               ((TIM_TypeDef *) TIM14_BASE)
+#define RTC                 ((RTC_TypeDef *) RTC_BASE)
+#define WWDG                ((WWDG_TypeDef *) WWDG_BASE)
+#define IWDG                ((IWDG_TypeDef *) IWDG_BASE)
+#define I2S2ext             ((SPI_TypeDef *) I2S2ext_BASE)
+#define SPI2                ((SPI_TypeDef *) SPI2_BASE)
+#define SPI3                ((SPI_TypeDef *) SPI3_BASE)
+#define I2S3ext             ((SPI_TypeDef *) I2S3ext_BASE)
+#define USART2              ((USART_TypeDef *) USART2_BASE)
+#define USART3              ((USART_TypeDef *) USART3_BASE)
+#define UART4               ((USART_TypeDef *) UART4_BASE)
+#define UART5               ((USART_TypeDef *) UART5_BASE)
+#define I2C1                ((I2C_TypeDef *) I2C1_BASE)
+#define I2C2                ((I2C_TypeDef *) I2C2_BASE)
+#define I2C3                ((I2C_TypeDef *) I2C3_BASE)
+#define CAN1                ((CAN_TypeDef *) CAN1_BASE)
+#define CAN2                ((CAN_TypeDef *) CAN2_BASE)
+#define PWR                 ((PWR_TypeDef *) PWR_BASE)
+#define DAC                 ((DAC_TypeDef *) DAC_BASE)
+#define TIM1                ((TIM_TypeDef *) TIM1_BASE)
+#define TIM8                ((TIM_TypeDef *) TIM8_BASE)
+#define USART1              ((USART_TypeDef *) USART1_BASE)
+#define USART6              ((USART_TypeDef *) USART6_BASE)
+#define ADC                 ((ADC_Common_TypeDef *) ADC_BASE)
+#define ADC1                ((ADC_TypeDef *) ADC1_BASE)
+#define ADC2                ((ADC_TypeDef *) ADC2_BASE)
+#define ADC3                ((ADC_TypeDef *) ADC3_BASE)
+#define SDIO                ((SDIO_TypeDef *) SDIO_BASE)
+#define SPI1                ((SPI_TypeDef *) SPI1_BASE)
+#define SYSCFG              ((SYSCFG_TypeDef *) SYSCFG_BASE)
+#define EXTI                ((EXTI_TypeDef *) EXTI_BASE)
+#define TIM9                ((TIM_TypeDef *) TIM9_BASE)
+#define TIM10               ((TIM_TypeDef *) TIM10_BASE)
+#define TIM11               ((TIM_TypeDef *) TIM11_BASE)
+#define GPIOA               ((GPIO_TypeDef *) GPIOA_BASE)
+#define GPIOB               ((GPIO_TypeDef *) GPIOB_BASE)
+#define GPIOC               ((GPIO_TypeDef *) GPIOC_BASE)
+#define GPIOD               ((GPIO_TypeDef *) GPIOD_BASE)
+#define GPIOE               ((GPIO_TypeDef *) GPIOE_BASE)
+#define GPIOF               ((GPIO_TypeDef *) GPIOF_BASE)
+#define GPIOG               ((GPIO_TypeDef *) GPIOG_BASE)
+#define GPIOH               ((GPIO_TypeDef *) GPIOH_BASE)
+#define GPIOI               ((GPIO_TypeDef *) GPIOI_BASE)
+#define CRC                 ((CRC_TypeDef *) CRC_BASE)
+#define RCC                 ((RCC_TypeDef *) RCC_BASE)
+#define FLASH               ((FLASH_TypeDef *) FLASH_R_BASE)
+#define DMA1                ((DMA_TypeDef *) DMA1_BASE)
+#define DMA1_Stream0        ((DMA_Stream_TypeDef *) DMA1_Stream0_BASE)
+#define DMA1_Stream1        ((DMA_Stream_TypeDef *) DMA1_Stream1_BASE)
+#define DMA1_Stream2        ((DMA_Stream_TypeDef *) DMA1_Stream2_BASE)
+#define DMA1_Stream3        ((DMA_Stream_TypeDef *) DMA1_Stream3_BASE)
+#define DMA1_Stream4        ((DMA_Stream_TypeDef *) DMA1_Stream4_BASE)
+#define DMA1_Stream5        ((DMA_Stream_TypeDef *) DMA1_Stream5_BASE)
+#define DMA1_Stream6        ((DMA_Stream_TypeDef *) DMA1_Stream6_BASE)
+#define DMA1_Stream7        ((DMA_Stream_TypeDef *) DMA1_Stream7_BASE)
+#define DMA2                ((DMA_TypeDef *) DMA2_BASE)
+#define DMA2_Stream0        ((DMA_Stream_TypeDef *) DMA2_Stream0_BASE)
+#define DMA2_Stream1        ((DMA_Stream_TypeDef *) DMA2_Stream1_BASE)
+#define DMA2_Stream2        ((DMA_Stream_TypeDef *) DMA2_Stream2_BASE)
+#define DMA2_Stream3        ((DMA_Stream_TypeDef *) DMA2_Stream3_BASE)
+#define DMA2_Stream4        ((DMA_Stream_TypeDef *) DMA2_Stream4_BASE)
+#define DMA2_Stream5        ((DMA_Stream_TypeDef *) DMA2_Stream5_BASE)
+#define DMA2_Stream6        ((DMA_Stream_TypeDef *) DMA2_Stream6_BASE)
+#define DMA2_Stream7        ((DMA_Stream_TypeDef *) DMA2_Stream7_BASE)
+#define ETH                 ((ETH_TypeDef *) ETH_BASE)  
+#define DCMI                ((DCMI_TypeDef *) DCMI_BASE)
+#define CRYP                ((CRYP_TypeDef *) CRYP_BASE)
+#define HASH                ((HASH_TypeDef *) HASH_BASE)
+#define RNG                 ((RNG_TypeDef *) RNG_BASE)
+#define FSMC_Bank1          ((FSMC_Bank1_TypeDef *) FSMC_Bank1_R_BASE)
+#define FSMC_Bank1E         ((FSMC_Bank1E_TypeDef *) FSMC_Bank1E_R_BASE)
+#define FSMC_Bank2          ((FSMC_Bank2_TypeDef *) FSMC_Bank2_R_BASE)
+#define FSMC_Bank3          ((FSMC_Bank3_TypeDef *) FSMC_Bank3_R_BASE)
+#define FSMC_Bank4          ((FSMC_Bank4_TypeDef *) FSMC_Bank4_R_BASE)
+#define DBGMCU              ((DBGMCU_TypeDef *) DBGMCU_BASE)
+
+/**
+  * @}
+  */
+
+/** @addtogroup Exported_constants
+  * @{
+  */
+  
+  /** @addtogroup Peripheral_Registers_Bits_Definition
+  * @{
+  */
+    
+/******************************************************************************/
+/*                         Peripheral Registers_Bits_Definition               */
+/******************************************************************************/
+
+/******************************************************************************/
+/*                                                                            */
+/*                        Analog to Digital Converter                         */
+/*                                                                            */
+/******************************************************************************/
+/********************  Bit definition for ADC_SR register  ********************/
+#define  ADC_SR_AWD                          ((uint8_t)0x01)               /*!
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************  
+  */ 
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */  
+  
+/**
+  * @brief Define to prevent recursive inclusion
+  */
+#ifndef __SYSTEM_STM32F4XX_H
+#define __SYSTEM_STM32F4XX_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/** @addtogroup STM32F4xx_System_Includes
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+
+/** @addtogroup STM32F4xx_System_Exported_types
+  * @{
+  */
+
+extern uint32_t SystemCoreClock;          /*!< System Clock Frequency (Core Clock) */
+
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Exported_Functions
+  * @{
+  */
+  
+extern void SystemInit(void);
+extern void SystemCoreClockUpdate(void);
+/**
+  * @}
+  */
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__SYSTEM_STM32F4XX_H */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */  
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Release_Notes.html b/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Release_Notes.html
new file mode 100644
index 0000000000..25123149dd
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Release_Notes.html
@@ -0,0 +1,137 @@
+
+
+
+
+
+
+
+Release Notes for STM32F40x CMSIS
+
+
+
+
+
+
    
+

    
+
    
+
    
+
+
+
+
+
+
+
    
+
+
+          
+            
+          
+
+
+
+
+
    Back to Release page
    
+
    Release
+Notes for STM32F4xx CMSIS
    
+
    Copyright 2011 STMicroelectronics
    
+
    
+
    
+
     
    
+
+
+
+
+
+
+
    
+
    Contents
    
+
      
+
    1. STM32F4xx CMSIS
+update History
      2. 
+
    2. License
      3. 
+
    
+
+
    STM32F4xx CMSIS
+update History
    V1.0.0RC1 / 25-August-2011
    Main
+Changes
    
+
    • Official version (V1.0.0) Release Candidate1 for STM32F4xx devices
    
+
+
      
+
    
+
    License
    
+
    The
+enclosed firmware and all the related documentation are not covered by
+a License Agreement, if you need such License you can contact your
+local STMicroelectronics office.
    
+
    THE
+PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO
+SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR
+ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
+CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
+CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
+THEIR PRODUCTS. 
    
+
     
    
+
    
+
    
+
    For
+complete documentation on STM32(CORTEX M3) 32-Bit Microcontrollers
+visit www.st.com/STM32
    
+
    
+
    
+
    
+
    
+
     
    
+
    
+
\ No newline at end of file
diff --git a/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/TASKING/cstart_thumb2.asm b/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/TASKING/cstart_thumb2.asm
new file mode 100644
index 0000000000..b574378f81
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/TASKING/cstart_thumb2.asm
@@ -0,0 +1,145 @@
+
+
+;;  NOTE: To allow the use of this file for both ARMv6M and ARMv7M,
+;;        we will only use 16-bit Thumb intructions.
+
+        .extern _lc_ub_stack            ; usr/sys mode stack pointer
+        .extern _lc_ue_stack            ; symbol required by debugger
+        .extern _lc_ub_table            ; ROM to RAM copy table
+        .extern main
+        .extern _Exit
+        .extern exit
+        .weak   exit
+        .global __get_argcv
+        .weak   __get_argcv
+        .extern __argcvbuf
+        .weak   __argcvbuf
+        .extern  SystemInit
+        
+    .if @defined('__PROF_ENABLE__')
+        .extern __prof_init
+    .endif
+    .if @defined('__POSIX__')
+        .extern posix_main
+        .extern _posix_boot_stack_top
+    .endif
+
+        .global _START
+
+        .section .text.cstart
+
+        .thumb
+_START: 
+        ;; anticipate possible ROM/RAM remapping
+        ;; by loading the 'real' program address
+        ldr     r1,=_Next
+        bx      r1
+_Next:
+        ;; initialize the stack pointer
+        ldr     r1,=_lc_ub_stack        ; TODO: make this part of the vector table
+        mov     sp,r1
+
+        ;FPU settings
+	    ldr     r0, =0xE000ED88           ; Enable CP10,CP11
+        ldr     r1,[r0]
+        orr     r1,r1,#(0xF << 20)
+        str     r1,[r0]
+	
+	; Call the clock system intitialization function.
+		bl  SystemInit
+
+        ;; copy initialized sections from ROM to RAM
+        ;; and clear uninitialized data sections in RAM
+
+        ldr     r3,=_lc_ub_table
+        movs    r0,#0
+cploop:
+        ldr     r4,[r3,#0]      ; load type
+        ldr     r5,[r3,#4]      ; dst address
+        ldr     r6,[r3,#8]      ; src address
+        ldr     r7,[r3,#12]     ; size
+
+        cmp     r4,#1
+        beq     copy
+        cmp     r4,#2
+        beq     clear
+        b       done
+
+copy:
+        subs    r7,r7,#1
+        ldrb    r1,[r6,r7]
+        strb    r1,[r5,r7]
+        bne     copy
+
+        adds    r3,r3,#16
+        b       cploop
+
+clear:
+        subs    r7,r7,#1
+        strb    r0,[r5,r7]
+        bne     clear
+        
+        adds    r3,r3,#16
+        b       cploop
+        
+done:   
+
+      .if @defined('__POSIX__')
+        
+        ;; posix stack buffer for system upbringing
+        ldr     r0,=_posix_boot_stack_top
+        ldr     r0, [r0]
+        mov     sp,r0
+     
+     .else
+        
+        ;; load r10 with end of USR/SYS stack, which is
+        ;; needed in case stack overflow checking is on
+        ;; NOTE: use 16-bit instructions only, for ARMv6M
+        ldr     r0,=_lc_ue_stack
+        mov     r10,r0
+     
+     .endif
+
+    .if @defined('__PROF_ENABLE__')
+        bl      __prof_init
+    .endif
+
+    .if @defined('__POSIX__')
+        ;; call posix_main with no arguments
+        bl      posix_main
+    .else
+        ;; retrieve argc and argv (default argv[0]==NULL & argc==0)
+        bl      __get_argcv
+        ldr     r1,=__argcvbuf
+        ;; call main
+        bl       main
+    .endif
+
+        ;; call exit using the return value from main()
+        ;; Note. Calling exit will also run all functions
+        ;; that were supplied through atexit().
+        bl      exit
+        
+__get_argcv:                    ; weak definition
+        movs     r0,#0
+        bx      lr
+
+        .ltorg
+        .endsec
+
+        .calls  '_START', '  '
+        .calls  '_START','__init_vector_table'
+    .if @defined('__PROF_ENABLE__')
+        .calls  '_START','__prof_init'
+    .endif
+    .if @defined('__POSIX__')
+        .calls  '_START','posix_main'
+    .else
+        .calls  '_START','__get_argcv'
+        .calls  '_START','main'
+    .endif
+        .calls  '_START','exit'
+        .calls  '_START','',0
+
+        .end
diff --git a/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/TrueSTUDIO/startup_stm32f4xx.s b/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/TrueSTUDIO/startup_stm32f4xx.s
new file mode 100644
index 0000000000..2833617b73
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/TrueSTUDIO/startup_stm32f4xx.s
@@ -0,0 +1,519 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f4xx.s
+  * @author    MCD Application Team
+  * @version   V1.0.0RC1
+  * @date      25-August-2011
+  * @brief     STM32F4xx Devices vector table for Atollic TrueSTUDIO toolchain. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM mounted on 
+  *                  STM3220F-EVAL board to be used as data memory (optional, 
+  *                  to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+    
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */  
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:  
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+  
+  
+/*FPU settings*/
+ ldr     r0, =0xE000ED88           // Enable CP10,CP11
+ ldr     r1,[r0]
+ orr     r1,r1,#(0xF << 20)
+ str     r1,[r0]
+	
+/* Call the clock system intitialization function.*/
+  bl  SystemInit   
+/* Call static constructors */
+    bl __libc_init_array
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+    
+    
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */                                        
+  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */                        
+  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */            
+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */                      
+  .word     FLASH_IRQHandler                  /* FLASH                        */                                          
+  .word     RCC_IRQHandler                    /* RCC                          */                                            
+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */                        
+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */                          
+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */                          
+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */                          
+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */                          
+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */                  
+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */                   
+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */                   
+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */                   
+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */                   
+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */                   
+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */                   
+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */                   
+  .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */                         
+  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */                          
+  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */                          
+  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */                          
+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */                          
+  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */         
+  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */         
+  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */
+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */                          
+  .word     TIM2_IRQHandler                   /* TIM2                         */                   
+  .word     TIM3_IRQHandler                   /* TIM3                         */                   
+  .word     TIM4_IRQHandler                   /* TIM4                         */                   
+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */                          
+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */                          
+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */                          
+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */                            
+  .word     SPI1_IRQHandler                   /* SPI1                         */                   
+  .word     SPI2_IRQHandler                   /* SPI2                         */                   
+  .word     USART1_IRQHandler                 /* USART1                       */                   
+  .word     USART2_IRQHandler                 /* USART2                       */                   
+  .word     USART3_IRQHandler                 /* USART3                       */                   
+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */                          
+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */                 
+  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */                       
+  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */         
+  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */         
+  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
+  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */                          
+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */                          
+  .word     FSMC_IRQHandler                   /* FSMC                         */                   
+  .word     SDIO_IRQHandler                   /* SDIO                         */                   
+  .word     TIM5_IRQHandler                   /* TIM5                         */                   
+  .word     SPI3_IRQHandler                   /* SPI3                         */                   
+  .word     UART4_IRQHandler                  /* UART4                        */                   
+  .word     UART5_IRQHandler                  /* UART5                        */                   
+  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */                   
+  .word     TIM7_IRQHandler                   /* TIM7                         */
+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */                   
+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */                   
+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */                   
+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */                   
+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */                   
+  .word     ETH_IRQHandler                    /* Ethernet                     */                   
+  .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */                     
+  .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */                          
+  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */                          
+  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */                          
+  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */                          
+  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */                   
+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */                   
+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */                   
+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */                   
+  .word     USART6_IRQHandler                 /* USART6                       */                    
+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */                          
+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */                          
+  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */                   
+  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */                   
+  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */                         
+  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */                   
+  .word     DCMI_IRQHandler                   /* DCMI                         */                   
+  .word     CRYP_IRQHandler                   /* CRYP crypto                  */                   
+  .word     HASH_RNG_IRQHandler               /* Hash and Rng                 */
+  .word     FPU_IRQHandler                    /* FPU                          */
+                         
+                         
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler                   
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+                  
+   .weak      PVD_IRQHandler      
+   .thumb_set PVD_IRQHandler,Default_Handler
+               
+   .weak      TAMP_STAMP_IRQHandler            
+   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+            
+   .weak      RTC_WKUP_IRQHandler                  
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+            
+   .weak      FLASH_IRQHandler         
+   .thumb_set FLASH_IRQHandler,Default_Handler
+                  
+   .weak      RCC_IRQHandler      
+   .thumb_set RCC_IRQHandler,Default_Handler
+                  
+   .weak      EXTI0_IRQHandler         
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+                  
+   .weak      EXTI1_IRQHandler         
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+                     
+   .weak      EXTI2_IRQHandler         
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+                 
+   .weak      EXTI3_IRQHandler         
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+                        
+   .weak      EXTI4_IRQHandler         
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream0_IRQHandler               
+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+         
+   .weak      DMA1_Stream1_IRQHandler               
+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream2_IRQHandler               
+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream3_IRQHandler               
+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler 
+                 
+   .weak      DMA1_Stream4_IRQHandler              
+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream5_IRQHandler               
+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream6_IRQHandler               
+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      ADC_IRQHandler      
+   .thumb_set ADC_IRQHandler,Default_Handler
+               
+   .weak      CAN1_TX_IRQHandler   
+   .thumb_set CAN1_TX_IRQHandler,Default_Handler
+            
+   .weak      CAN1_RX0_IRQHandler                  
+   .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN1_RX1_IRQHandler                  
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+            
+   .weak      CAN1_SCE_IRQHandler                  
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+            
+   .weak      EXTI9_5_IRQHandler   
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+            
+   .weak      TIM1_BRK_TIM9_IRQHandler            
+   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+            
+   .weak      TIM1_UP_TIM10_IRQHandler            
+   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+      
+   .weak      TIM1_TRG_COM_TIM11_IRQHandler      
+   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+      
+   .weak      TIM1_CC_IRQHandler   
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+                  
+   .weak      TIM2_IRQHandler            
+   .thumb_set TIM2_IRQHandler,Default_Handler
+                  
+   .weak      TIM3_IRQHandler            
+   .thumb_set TIM3_IRQHandler,Default_Handler
+                  
+   .weak      TIM4_IRQHandler            
+   .thumb_set TIM4_IRQHandler,Default_Handler
+                  
+   .weak      I2C1_EV_IRQHandler   
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+                     
+   .weak      I2C1_ER_IRQHandler   
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+                     
+   .weak      I2C2_EV_IRQHandler   
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+                  
+   .weak      I2C2_ER_IRQHandler   
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+                           
+   .weak      SPI1_IRQHandler            
+   .thumb_set SPI1_IRQHandler,Default_Handler
+                        
+   .weak      SPI2_IRQHandler            
+   .thumb_set SPI2_IRQHandler,Default_Handler
+                  
+   .weak      USART1_IRQHandler      
+   .thumb_set USART1_IRQHandler,Default_Handler
+                     
+   .weak      USART2_IRQHandler      
+   .thumb_set USART2_IRQHandler,Default_Handler
+                     
+   .weak      USART3_IRQHandler      
+   .thumb_set USART3_IRQHandler,Default_Handler
+                  
+   .weak      EXTI15_10_IRQHandler               
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+               
+   .weak      RTC_Alarm_IRQHandler               
+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+            
+   .weak      OTG_FS_WKUP_IRQHandler         
+   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      TIM8_BRK_TIM12_IRQHandler         
+   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+         
+   .weak      TIM8_UP_TIM13_IRQHandler            
+   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+         
+   .weak      TIM8_TRG_COM_TIM14_IRQHandler      
+   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+      
+   .weak      TIM8_CC_IRQHandler   
+   .thumb_set TIM8_CC_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream7_IRQHandler               
+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+                     
+   .weak      FSMC_IRQHandler            
+   .thumb_set FSMC_IRQHandler,Default_Handler
+                     
+   .weak      SDIO_IRQHandler            
+   .thumb_set SDIO_IRQHandler,Default_Handler
+                     
+   .weak      TIM5_IRQHandler            
+   .thumb_set TIM5_IRQHandler,Default_Handler
+                     
+   .weak      SPI3_IRQHandler            
+   .thumb_set SPI3_IRQHandler,Default_Handler
+                     
+   .weak      UART4_IRQHandler         
+   .thumb_set UART4_IRQHandler,Default_Handler
+                  
+   .weak      UART5_IRQHandler         
+   .thumb_set UART5_IRQHandler,Default_Handler
+                  
+   .weak      TIM6_DAC_IRQHandler                  
+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+               
+   .weak      TIM7_IRQHandler            
+   .thumb_set TIM7_IRQHandler,Default_Handler
+         
+   .weak      DMA2_Stream0_IRQHandler               
+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+               
+   .weak      DMA2_Stream1_IRQHandler               
+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream2_IRQHandler               
+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream3_IRQHandler               
+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream4_IRQHandler               
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+            
+   .weak      ETH_IRQHandler      
+   .thumb_set ETH_IRQHandler,Default_Handler
+                  
+   .weak      ETH_WKUP_IRQHandler                  
+   .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+            
+   .weak      CAN2_TX_IRQHandler   
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_RX0_IRQHandler                  
+   .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_RX1_IRQHandler                  
+   .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_SCE_IRQHandler                  
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+                           
+   .weak      OTG_FS_IRQHandler      
+   .thumb_set OTG_FS_IRQHandler,Default_Handler
+                     
+   .weak      DMA2_Stream5_IRQHandler               
+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream6_IRQHandler               
+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream7_IRQHandler               
+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+                  
+   .weak      USART6_IRQHandler      
+   .thumb_set USART6_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_EV_IRQHandler   
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_ER_IRQHandler   
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+                        
+   .weak      OTG_HS_EP1_OUT_IRQHandler         
+   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+               
+   .weak      OTG_HS_EP1_IN_IRQHandler            
+   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+               
+   .weak      OTG_HS_WKUP_IRQHandler         
+   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      OTG_HS_IRQHandler      
+   .thumb_set OTG_HS_IRQHandler,Default_Handler
+                  
+   .weak      DCMI_IRQHandler            
+   .thumb_set DCMI_IRQHandler,Default_Handler
+                     
+   .weak      CRYP_IRQHandler            
+   .thumb_set CRYP_IRQHandler,Default_Handler
+               
+   .weak      HASH_RNG_IRQHandler                  
+   .thumb_set HASH_RNG_IRQHandler,Default_Handler   
+
+   .weak      FPU_IRQHandler                  
+   .thumb_set FPU_IRQHandler,Default_Handler  
+
+/*******************   (C)   COPYRIGHT   2011   STMicroelectronics   *****END   OF   FILE****/
diff --git a/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/arm/startup_stm32f4xx.s b/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/arm/startup_stm32f4xx.s
new file mode 100644
index 0000000000..a4fad3f168
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/arm/startup_stm32f4xx.s
@@ -0,0 +1,430 @@
+;******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f4xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.0.0RC1
+;* Date               : 25-August-2011
+;* Description        : STM32F4xx devices vector table for MDK-ARM toolchain. 
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == Reset_Handler
+;*                      - Set the vector table entries with the exceptions ISR address
+;*                      - Branches to __main in the C library (which eventually
+;*                        calls main()).
+;*                      After Reset the CortexM4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;* <<< Use Configuration Wizard in Context Menu >>>   
+;*******************************************************************************
+; THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+; WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+; AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+; INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+; CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+; INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************
+
+; Amount of memory (in bytes) allocated for Stack
+; Tailor this value to your application needs
+;  Stack Configuration
+;    Stack Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Stack_Size      EQU     0x00000400
+
+                AREA    STACK, NOINIT, READWRITE, ALIGN=3
+Stack_Mem       SPACE   Stack_Size
+__initial_sp
+
+
+;  Heap Configuration
+;     Heap Size (in Bytes) <0x0-0xFFFFFFFF:8>
+; 
+
+Heap_Size       EQU     0x00000200
+
+                AREA    HEAP, NOINIT, READWRITE, ALIGN=3
+__heap_base
+Heap_Mem        SPACE   Heap_Size
+__heap_limit
+
+                PRESERVE8
+                THUMB
+
+
+; Vector Table Mapped to Address 0 at Reset
+                AREA    RESET, DATA, READONLY
+                EXPORT  __Vectors
+                EXPORT  __Vectors_End
+                EXPORT  __Vectors_Size
+
+__Vectors       DCD     __initial_sp               ; Top of Stack
+                DCD     Reset_Handler              ; Reset Handler
+                DCD     NMI_Handler                ; NMI Handler
+                DCD     HardFault_Handler          ; Hard Fault Handler
+                DCD     MemManage_Handler          ; MPU Fault Handler
+                DCD     BusFault_Handler           ; Bus Fault Handler
+                DCD     UsageFault_Handler         ; Usage Fault Handler
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     0                          ; Reserved
+                DCD     SVC_Handler                ; SVCall Handler
+                DCD     DebugMon_Handler           ; Debug Monitor Handler
+                DCD     0                          ; Reserved
+                DCD     PendSV_Handler             ; PendSV Handler
+                DCD     SysTick_Handler            ; SysTick Handler
+
+                ; External Interrupts
+                DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+                DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+                DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+                DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+                DCD     FLASH_IRQHandler                  ; FLASH                                           
+                DCD     RCC_IRQHandler                    ; RCC                                             
+                DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+                DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+                DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+                DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+                DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+                DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
+                DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+                DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+                DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+                DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+                DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+                DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
+                DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
+                DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+                DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+                DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+                DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+                DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+                DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
+                DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
+                DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+                DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+                DCD     TIM2_IRQHandler                   ; TIM2                                            
+                DCD     TIM3_IRQHandler                   ; TIM3                                            
+                DCD     TIM4_IRQHandler                   ; TIM4                                            
+                DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+                DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+                DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+                DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+                DCD     SPI1_IRQHandler                   ; SPI1                                            
+                DCD     SPI2_IRQHandler                   ; SPI2                                            
+                DCD     USART1_IRQHandler                 ; USART1                                          
+                DCD     USART2_IRQHandler                 ; USART2                                          
+                DCD     USART3_IRQHandler                 ; USART3                                          
+                DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+                DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+                DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
+                DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
+                DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
+                DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+                DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+                DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+                DCD     FSMC_IRQHandler                   ; FSMC                                            
+                DCD     SDIO_IRQHandler                   ; SDIO                                            
+                DCD     TIM5_IRQHandler                   ; TIM5                                            
+                DCD     SPI3_IRQHandler                   ; SPI3                                            
+                DCD     UART4_IRQHandler                  ; UART4                                           
+                DCD     UART5_IRQHandler                  ; UART5                                           
+                DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+                DCD     TIM7_IRQHandler                   ; TIM7                   
+                DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
+                DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
+                DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
+                DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
+                DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
+                DCD     ETH_IRQHandler                    ; Ethernet                                        
+                DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
+                DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
+                DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
+                DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
+                DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
+                DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
+                DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
+                DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
+                DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
+                DCD     USART6_IRQHandler                 ; USART6                                           
+                DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
+                DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
+                DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+                DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+                DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+                DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
+                DCD     DCMI_IRQHandler                   ; DCMI                                            
+                DCD     CRYP_IRQHandler                   ; CRYP crypto                                     
+                DCD     HASH_RNG_IRQHandler               ; Hash and Rng
+                DCD     FPU_IRQHandler                    ; FPU
+                         
+__Vectors_End
+
+__Vectors_Size  EQU  __Vectors_End - __Vectors
+
+                AREA    |.text|, CODE, READONLY
+
+; Reset handler
+Reset_Handler    PROC
+                 EXPORT  Reset_Handler             [WEAK]
+        IMPORT  SystemInit
+        IMPORT  __main
+
+                 ;FPU settings
+                 LDR     R0, =0xE000ED88           ; Enable CP10,CP11
+                 LDR     R1,[R0]
+                 ORR     R1,R1,#(0xF << 20)
+                 STR     R1,[R0]
+
+                 LDR     R0, =SystemInit
+                 BLX     R0
+                 LDR     R0, =__main
+                 BX      R0
+                 ENDP
+
+; Dummy Exception Handlers (infinite loops which can be modified)
+
+NMI_Handler     PROC
+                EXPORT  NMI_Handler                [WEAK]
+                B       .
+                ENDP
+HardFault_Handler\
+                PROC
+                EXPORT  HardFault_Handler          [WEAK]
+                B       .
+                ENDP
+MemManage_Handler\
+                PROC
+                EXPORT  MemManage_Handler          [WEAK]
+                B       .
+                ENDP
+BusFault_Handler\
+                PROC
+                EXPORT  BusFault_Handler           [WEAK]
+                B       .
+                ENDP
+UsageFault_Handler\
+                PROC
+                EXPORT  UsageFault_Handler         [WEAK]
+                B       .
+                ENDP
+SVC_Handler     PROC
+                EXPORT  SVC_Handler                [WEAK]
+                B       .
+                ENDP
+DebugMon_Handler\
+                PROC
+                EXPORT  DebugMon_Handler           [WEAK]
+                B       .
+                ENDP
+PendSV_Handler  PROC
+                EXPORT  PendSV_Handler             [WEAK]
+                B       .
+                ENDP
+SysTick_Handler PROC
+                EXPORT  SysTick_Handler            [WEAK]
+                B       .
+                ENDP
+
+Default_Handler PROC
+
+                EXPORT  WWDG_IRQHandler                   [WEAK]                                        
+                EXPORT  PVD_IRQHandler                    [WEAK]                      
+                EXPORT  TAMP_STAMP_IRQHandler             [WEAK]         
+                EXPORT  RTC_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  FLASH_IRQHandler                  [WEAK]                                         
+                EXPORT  RCC_IRQHandler                    [WEAK]                                            
+                EXPORT  EXTI0_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI1_IRQHandler                  [WEAK]                                             
+                EXPORT  EXTI2_IRQHandler                  [WEAK]                                            
+                EXPORT  EXTI3_IRQHandler                  [WEAK]                                           
+                EXPORT  EXTI4_IRQHandler                  [WEAK]                                            
+                EXPORT  DMA1_Stream0_IRQHandler           [WEAK]                                
+                EXPORT  DMA1_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream2_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream3_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream4_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA1_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  ADC_IRQHandler                    [WEAK]                         
+                EXPORT  CAN1_TX_IRQHandler                [WEAK]                                                
+                EXPORT  CAN1_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN1_RX1_IRQHandler               [WEAK]                                                
+                EXPORT  CAN1_SCE_IRQHandler               [WEAK]                                                
+                EXPORT  EXTI9_5_IRQHandler                [WEAK]                                    
+                EXPORT  TIM1_BRK_TIM9_IRQHandler          [WEAK]                  
+                EXPORT  TIM1_UP_TIM10_IRQHandler          [WEAK]                
+                EXPORT  TIM1_TRG_COM_TIM11_IRQHandler     [WEAK] 
+                EXPORT  TIM1_CC_IRQHandler                [WEAK]                                   
+                EXPORT  TIM2_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM3_IRQHandler                   [WEAK]                                            
+                EXPORT  TIM4_IRQHandler                   [WEAK]                                            
+                EXPORT  I2C1_EV_IRQHandler                [WEAK]                                             
+                EXPORT  I2C1_ER_IRQHandler                [WEAK]                                             
+                EXPORT  I2C2_EV_IRQHandler                [WEAK]                                            
+                EXPORT  I2C2_ER_IRQHandler                [WEAK]                                               
+                EXPORT  SPI1_IRQHandler                   [WEAK]                                           
+                EXPORT  SPI2_IRQHandler                   [WEAK]                                            
+                EXPORT  USART1_IRQHandler                 [WEAK]                                          
+                EXPORT  USART2_IRQHandler                 [WEAK]                                          
+                EXPORT  USART3_IRQHandler                 [WEAK]                                         
+                EXPORT  EXTI15_10_IRQHandler              [WEAK]                                  
+                EXPORT  RTC_Alarm_IRQHandler              [WEAK]                  
+                EXPORT  OTG_FS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  TIM8_BRK_TIM12_IRQHandler         [WEAK]                 
+                EXPORT  TIM8_UP_TIM13_IRQHandler          [WEAK]                 
+                EXPORT  TIM8_TRG_COM_TIM14_IRQHandler     [WEAK] 
+                EXPORT  TIM8_CC_IRQHandler                [WEAK]                                   
+                EXPORT  DMA1_Stream7_IRQHandler           [WEAK]                                          
+                EXPORT  FSMC_IRQHandler                   [WEAK]                                             
+                EXPORT  SDIO_IRQHandler                   [WEAK]                                             
+                EXPORT  TIM5_IRQHandler                   [WEAK]                                             
+                EXPORT  SPI3_IRQHandler                   [WEAK]                                             
+                EXPORT  UART4_IRQHandler                  [WEAK]                                            
+                EXPORT  UART5_IRQHandler                  [WEAK]                                            
+                EXPORT  TIM6_DAC_IRQHandler               [WEAK]                   
+                EXPORT  TIM7_IRQHandler                   [WEAK]                    
+                EXPORT  DMA2_Stream0_IRQHandler           [WEAK]                                  
+                EXPORT  DMA2_Stream1_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream2_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream3_IRQHandler           [WEAK]                                    
+                EXPORT  DMA2_Stream4_IRQHandler           [WEAK]                                 
+                EXPORT  ETH_IRQHandler                    [WEAK]                                         
+                EXPORT  ETH_WKUP_IRQHandler               [WEAK]                     
+                EXPORT  CAN2_TX_IRQHandler                [WEAK]                                               
+                EXPORT  CAN2_RX0_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_RX1_IRQHandler               [WEAK]                                               
+                EXPORT  CAN2_SCE_IRQHandler               [WEAK]                                               
+                EXPORT  OTG_FS_IRQHandler                 [WEAK]                                       
+                EXPORT  DMA2_Stream5_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream6_IRQHandler           [WEAK]                                   
+                EXPORT  DMA2_Stream7_IRQHandler           [WEAK]                                   
+                EXPORT  USART6_IRQHandler                 [WEAK]                                           
+                EXPORT  I2C3_EV_IRQHandler                [WEAK]                                              
+                EXPORT  I2C3_ER_IRQHandler                [WEAK]                                              
+                EXPORT  OTG_HS_EP1_OUT_IRQHandler         [WEAK]                      
+                EXPORT  OTG_HS_EP1_IN_IRQHandler          [WEAK]                      
+                EXPORT  OTG_HS_WKUP_IRQHandler            [WEAK]                        
+                EXPORT  OTG_HS_IRQHandler                 [WEAK]                                      
+                EXPORT  DCMI_IRQHandler                   [WEAK]                                             
+                EXPORT  CRYP_IRQHandler                   [WEAK]                                     
+                EXPORT  HASH_RNG_IRQHandler               [WEAK]
+                EXPORT  FPU_IRQHandler                    [WEAK]                
+
+WWDG_IRQHandler                                                       
+PVD_IRQHandler                                      
+TAMP_STAMP_IRQHandler                  
+RTC_WKUP_IRQHandler                                
+FLASH_IRQHandler                                                       
+RCC_IRQHandler                                                            
+EXTI0_IRQHandler                                                          
+EXTI1_IRQHandler                                                           
+EXTI2_IRQHandler                                                          
+EXTI3_IRQHandler                                                         
+EXTI4_IRQHandler                                                          
+DMA1_Stream0_IRQHandler                                       
+DMA1_Stream1_IRQHandler                                          
+DMA1_Stream2_IRQHandler                                          
+DMA1_Stream3_IRQHandler                                          
+DMA1_Stream4_IRQHandler                                          
+DMA1_Stream5_IRQHandler                                          
+DMA1_Stream6_IRQHandler                                          
+ADC_IRQHandler                                         
+CAN1_TX_IRQHandler                                                            
+CAN1_RX0_IRQHandler                                                          
+CAN1_RX1_IRQHandler                                                           
+CAN1_SCE_IRQHandler                                                           
+EXTI9_5_IRQHandler                                                
+TIM1_BRK_TIM9_IRQHandler                        
+TIM1_UP_TIM10_IRQHandler                      
+TIM1_TRG_COM_TIM11_IRQHandler  
+TIM1_CC_IRQHandler                                               
+TIM2_IRQHandler                                                           
+TIM3_IRQHandler                                                           
+TIM4_IRQHandler                                                           
+I2C1_EV_IRQHandler                                                         
+I2C1_ER_IRQHandler                                                         
+I2C2_EV_IRQHandler                                                        
+I2C2_ER_IRQHandler                                                           
+SPI1_IRQHandler                                                          
+SPI2_IRQHandler                                                           
+USART1_IRQHandler                                                       
+USART2_IRQHandler                                                       
+USART3_IRQHandler                                                      
+EXTI15_10_IRQHandler                                            
+RTC_Alarm_IRQHandler                            
+OTG_FS_WKUP_IRQHandler                                
+TIM8_BRK_TIM12_IRQHandler                      
+TIM8_UP_TIM13_IRQHandler                       
+TIM8_TRG_COM_TIM14_IRQHandler  
+TIM8_CC_IRQHandler                                               
+DMA1_Stream7_IRQHandler                                                 
+FSMC_IRQHandler                                                            
+SDIO_IRQHandler                                                            
+TIM5_IRQHandler                                                            
+SPI3_IRQHandler                                                            
+UART4_IRQHandler                                                          
+UART5_IRQHandler                                                          
+TIM6_DAC_IRQHandler                            
+TIM7_IRQHandler                              
+DMA2_Stream0_IRQHandler                                         
+DMA2_Stream1_IRQHandler                                          
+DMA2_Stream2_IRQHandler                                           
+DMA2_Stream3_IRQHandler                                           
+DMA2_Stream4_IRQHandler                                        
+ETH_IRQHandler                                                         
+ETH_WKUP_IRQHandler                                
+CAN2_TX_IRQHandler                                                           
+CAN2_RX0_IRQHandler                                                          
+CAN2_RX1_IRQHandler                                                          
+CAN2_SCE_IRQHandler                                                          
+OTG_FS_IRQHandler                                                    
+DMA2_Stream5_IRQHandler                                          
+DMA2_Stream6_IRQHandler                                          
+DMA2_Stream7_IRQHandler                                          
+USART6_IRQHandler                                                        
+I2C3_EV_IRQHandler                                                          
+I2C3_ER_IRQHandler                                                          
+OTG_HS_EP1_OUT_IRQHandler                           
+OTG_HS_EP1_IN_IRQHandler                            
+OTG_HS_WKUP_IRQHandler                                
+OTG_HS_IRQHandler                                                   
+DCMI_IRQHandler                                                            
+CRYP_IRQHandler                                                    
+HASH_RNG_IRQHandler
+FPU_IRQHandler                                                 
+
+                B       .
+
+                ENDP
+
+                ALIGN
+
+;*******************************************************************************
+; User Stack and Heap initialization
+;*******************************************************************************
+                 IF      :DEF:__MICROLIB
+                
+                 EXPORT  __initial_sp
+                 EXPORT  __heap_base
+                 EXPORT  __heap_limit
+                
+                 ELSE
+                
+                 IMPORT  __use_two_region_memory
+                 EXPORT  __user_initial_stackheap
+                 
+__user_initial_stackheap
+
+                 LDR     R0, =  Heap_Mem
+                 LDR     R1, =(Stack_Mem + Stack_Size)
+                 LDR     R2, = (Heap_Mem +  Heap_Size)
+                 LDR     R3, = Stack_Mem
+                 BX      LR
+
+                 ALIGN
+
+                 ENDIF
+
+                 END
+
+;******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE*****
diff --git a/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/gcc_ride7/startup_stm32f4xx.s b/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/gcc_ride7/startup_stm32f4xx.s
new file mode 100644
index 0000000000..945802ae26
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/gcc_ride7/startup_stm32f4xx.s
@@ -0,0 +1,515 @@
+/**
+  ******************************************************************************
+  * @file      startup_stm32f4xx.s
+  * @author    MCD Application Team
+  * @version   V1.0.0RC1
+  * @date      25-August-2011
+  * @brief     STM32F4xx Devices vector table for RIDE7 toolchain. 
+  *            This module performs:
+  *                - Set the initial SP
+  *                - Set the initial PC == Reset_Handler,
+  *                - Set the vector table entries with the exceptions ISR address
+  *                - Configure the clock system and the external SRAM mounted on 
+  *                  STM3220F-EVAL board to be used as data memory (optional, 
+  *                  to be enabled by user)
+  *                - Branches to main in the C library (which eventually
+  *                  calls main()).
+  *            After Reset the Cortex-M4 processor is in Thread mode,
+  *            priority is Privileged, and the Stack is set to Main.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+    
+  .syntax unified
+  .cpu cortex-m3
+  .fpu softvfp
+  .thumb
+
+.global  g_pfnVectors
+.global  Default_Handler
+
+/* start address for the initialization values of the .data section. 
+defined in linker script */
+.word  _sidata
+/* start address for the .data section. defined in linker script */  
+.word  _sdata
+/* end address for the .data section. defined in linker script */
+.word  _edata
+/* start address for the .bss section. defined in linker script */
+.word  _sbss
+/* end address for the .bss section. defined in linker script */
+.word  _ebss
+/* stack used for SystemInit_ExtMemCtl; always internal RAM used */
+
+/**
+ * @brief  This is the code that gets called when the processor first
+ *          starts execution following a reset event. Only the absolutely
+ *          necessary set is performed, after which the application
+ *          supplied main() routine is called. 
+ * @param  None
+ * @retval : None
+*/
+
+    .section  .text.Reset_Handler
+  .weak  Reset_Handler
+  .type  Reset_Handler, %function
+Reset_Handler:  
+
+/* Copy the data segment initializers from flash to SRAM */  
+  movs  r1, #0
+  b  LoopCopyDataInit
+
+CopyDataInit:
+  ldr  r3, =_sidata
+  ldr  r3, [r3, r1]
+  str  r3, [r0, r1]
+  adds  r1, r1, #4
+    
+LoopCopyDataInit:
+  ldr  r0, =_sdata
+  ldr  r3, =_edata
+  adds  r2, r0, r1
+  cmp  r2, r3
+  bcc  CopyDataInit
+  ldr  r2, =_sbss
+  b  LoopFillZerobss
+/* Zero fill the bss segment. */  
+FillZerobss:
+  movs  r3, #0
+  str  r3, [r2], #4
+    
+LoopFillZerobss:
+  ldr  r3, = _ebss
+  cmp  r2, r3
+  bcc  FillZerobss
+
+/* FPU settings */
+ ldr     r0, =0xE000ED88           ; Enable CP10,CP11
+ ldr     r1,[r0]
+ orr     r1,r1,#(0xF << 20)
+ str     r1,[r0]
+
+/* Call the clock system intitialization function.*/
+  bl  SystemInit   
+/* Call the application's entry point.*/
+  bl  main
+  bx  lr    
+.size  Reset_Handler, .-Reset_Handler
+
+/**
+ * @brief  This is the code that gets called when the processor receives an 
+ *         unexpected interrupt.  This simply enters an infinite loop, preserving
+ *         the system state for examination by a debugger.
+ * @param  None     
+ * @retval None       
+*/
+    .section  .text.Default_Handler,"ax",%progbits
+Default_Handler:
+Infinite_Loop:
+  b  Infinite_Loop
+  .size  Default_Handler, .-Default_Handler
+/******************************************************************************
+*
+* The minimal vector table for a Cortex M3. Note that the proper constructs
+* must be placed on this to ensure that it ends up at physical address
+* 0x0000.0000.
+* 
+*******************************************************************************/
+   .section  .isr_vector,"a",%progbits
+  .type  g_pfnVectors, %object
+  .size  g_pfnVectors, .-g_pfnVectors
+    
+    
+g_pfnVectors:
+  .word  _estack
+  .word  Reset_Handler
+  .word  NMI_Handler
+  .word  HardFault_Handler
+  .word  MemManage_Handler
+  .word  BusFault_Handler
+  .word  UsageFault_Handler
+  .word  0
+  .word  0
+  .word  0
+  .word  0
+  .word  SVC_Handler
+  .word  DebugMon_Handler
+  .word  0
+  .word  PendSV_Handler
+  .word  SysTick_Handler
+  
+  /* External Interrupts */
+  .word     WWDG_IRQHandler                   /* Window WatchDog              */                                        
+  .word     PVD_IRQHandler                    /* PVD through EXTI Line detection */                        
+  .word     TAMP_STAMP_IRQHandler             /* Tamper and TimeStamps through the EXTI line */            
+  .word     RTC_WKUP_IRQHandler               /* RTC Wakeup through the EXTI line */                      
+  .word     FLASH_IRQHandler                  /* FLASH                        */                                          
+  .word     RCC_IRQHandler                    /* RCC                          */                                            
+  .word     EXTI0_IRQHandler                  /* EXTI Line0                   */                        
+  .word     EXTI1_IRQHandler                  /* EXTI Line1                   */                          
+  .word     EXTI2_IRQHandler                  /* EXTI Line2                   */                          
+  .word     EXTI3_IRQHandler                  /* EXTI Line3                   */                          
+  .word     EXTI4_IRQHandler                  /* EXTI Line4                   */                          
+  .word     DMA1_Stream0_IRQHandler           /* DMA1 Stream 0                */                  
+  .word     DMA1_Stream1_IRQHandler           /* DMA1 Stream 1                */                   
+  .word     DMA1_Stream2_IRQHandler           /* DMA1 Stream 2                */                   
+  .word     DMA1_Stream3_IRQHandler           /* DMA1 Stream 3                */                   
+  .word     DMA1_Stream4_IRQHandler           /* DMA1 Stream 4                */                   
+  .word     DMA1_Stream5_IRQHandler           /* DMA1 Stream 5                */                   
+  .word     DMA1_Stream6_IRQHandler           /* DMA1 Stream 6                */                   
+  .word     ADC_IRQHandler                    /* ADC1, ADC2 and ADC3s         */                   
+  .word     CAN1_TX_IRQHandler                /* CAN1 TX                      */                         
+  .word     CAN1_RX0_IRQHandler               /* CAN1 RX0                     */                          
+  .word     CAN1_RX1_IRQHandler               /* CAN1 RX1                     */                          
+  .word     CAN1_SCE_IRQHandler               /* CAN1 SCE                     */                          
+  .word     EXTI9_5_IRQHandler                /* External Line[9:5]s          */                          
+  .word     TIM1_BRK_TIM9_IRQHandler          /* TIM1 Break and TIM9          */         
+  .word     TIM1_UP_TIM10_IRQHandler          /* TIM1 Update and TIM10        */         
+  .word     TIM1_TRG_COM_TIM11_IRQHandler     /* TIM1 Trigger and Commutation and TIM11 */
+  .word     TIM1_CC_IRQHandler                /* TIM1 Capture Compare         */                          
+  .word     TIM2_IRQHandler                   /* TIM2                         */                   
+  .word     TIM3_IRQHandler                   /* TIM3                         */                   
+  .word     TIM4_IRQHandler                   /* TIM4                         */                   
+  .word     I2C1_EV_IRQHandler                /* I2C1 Event                   */                          
+  .word     I2C1_ER_IRQHandler                /* I2C1 Error                   */                          
+  .word     I2C2_EV_IRQHandler                /* I2C2 Event                   */                          
+  .word     I2C2_ER_IRQHandler                /* I2C2 Error                   */                            
+  .word     SPI1_IRQHandler                   /* SPI1                         */                   
+  .word     SPI2_IRQHandler                   /* SPI2                         */                   
+  .word     USART1_IRQHandler                 /* USART1                       */                   
+  .word     USART2_IRQHandler                 /* USART2                       */                   
+  .word     USART3_IRQHandler                 /* USART3                       */                   
+  .word     EXTI15_10_IRQHandler              /* External Line[15:10]s        */                          
+  .word     RTC_Alarm_IRQHandler              /* RTC Alarm (A and B) through EXTI Line */                 
+  .word     OTG_FS_WKUP_IRQHandler            /* USB OTG FS Wakeup through EXTI line */                       
+  .word     TIM8_BRK_TIM12_IRQHandler         /* TIM8 Break and TIM12         */         
+  .word     TIM8_UP_TIM13_IRQHandler          /* TIM8 Update and TIM13        */         
+  .word     TIM8_TRG_COM_TIM14_IRQHandler     /* TIM8 Trigger and Commutation and TIM14 */
+  .word     TIM8_CC_IRQHandler                /* TIM8 Capture Compare         */                          
+  .word     DMA1_Stream7_IRQHandler           /* DMA1 Stream7                 */                          
+  .word     FSMC_IRQHandler                   /* FSMC                         */                   
+  .word     SDIO_IRQHandler                   /* SDIO                         */                   
+  .word     TIM5_IRQHandler                   /* TIM5                         */                   
+  .word     SPI3_IRQHandler                   /* SPI3                         */                   
+  .word     UART4_IRQHandler                  /* UART4                        */                   
+  .word     UART5_IRQHandler                  /* UART5                        */                   
+  .word     TIM6_DAC_IRQHandler               /* TIM6 and DAC1&2 underrun errors */                   
+  .word     TIM7_IRQHandler                   /* TIM7                         */
+  .word     DMA2_Stream0_IRQHandler           /* DMA2 Stream 0                */                   
+  .word     DMA2_Stream1_IRQHandler           /* DMA2 Stream 1                */                   
+  .word     DMA2_Stream2_IRQHandler           /* DMA2 Stream 2                */                   
+  .word     DMA2_Stream3_IRQHandler           /* DMA2 Stream 3                */                   
+  .word     DMA2_Stream4_IRQHandler           /* DMA2 Stream 4                */                   
+  .word     ETH_IRQHandler                    /* Ethernet                     */                   
+  .word     ETH_WKUP_IRQHandler               /* Ethernet Wakeup through EXTI line */                     
+  .word     CAN2_TX_IRQHandler                /* CAN2 TX                      */                          
+  .word     CAN2_RX0_IRQHandler               /* CAN2 RX0                     */                          
+  .word     CAN2_RX1_IRQHandler               /* CAN2 RX1                     */                          
+  .word     CAN2_SCE_IRQHandler               /* CAN2 SCE                     */                          
+  .word     OTG_FS_IRQHandler                 /* USB OTG FS                   */                   
+  .word     DMA2_Stream5_IRQHandler           /* DMA2 Stream 5                */                   
+  .word     DMA2_Stream6_IRQHandler           /* DMA2 Stream 6                */                   
+  .word     DMA2_Stream7_IRQHandler           /* DMA2 Stream 7                */                   
+  .word     USART6_IRQHandler                 /* USART6                       */                    
+  .word     I2C3_EV_IRQHandler                /* I2C3 event                   */                          
+  .word     I2C3_ER_IRQHandler                /* I2C3 error                   */                          
+  .word     OTG_HS_EP1_OUT_IRQHandler         /* USB OTG HS End Point 1 Out   */                   
+  .word     OTG_HS_EP1_IN_IRQHandler          /* USB OTG HS End Point 1 In    */                   
+  .word     OTG_HS_WKUP_IRQHandler            /* USB OTG HS Wakeup through EXTI */                         
+  .word     OTG_HS_IRQHandler                 /* USB OTG HS                   */                   
+  .word     DCMI_IRQHandler                   /* DCMI                         */                   
+  .word     CRYP_IRQHandler                   /* CRYP crypto                  */                   
+  .word     HASH_RNG_IRQHandler               /* Hash and Rng                 */
+  .word     FPU_IRQHandler                    /* FPU                          */                         
+                         
+/*******************************************************************************
+*
+* Provide weak aliases for each Exception handler to the Default_Handler. 
+* As they are weak aliases, any function with the same name will override 
+* this definition.
+* 
+*******************************************************************************/
+   .weak      NMI_Handler
+   .thumb_set NMI_Handler,Default_Handler
+  
+   .weak      HardFault_Handler
+   .thumb_set HardFault_Handler,Default_Handler
+  
+   .weak      MemManage_Handler
+   .thumb_set MemManage_Handler,Default_Handler
+  
+   .weak      BusFault_Handler
+   .thumb_set BusFault_Handler,Default_Handler
+
+   .weak      UsageFault_Handler
+   .thumb_set UsageFault_Handler,Default_Handler
+
+   .weak      SVC_Handler
+   .thumb_set SVC_Handler,Default_Handler
+
+   .weak      DebugMon_Handler
+   .thumb_set DebugMon_Handler,Default_Handler
+
+   .weak      PendSV_Handler
+   .thumb_set PendSV_Handler,Default_Handler
+
+   .weak      SysTick_Handler
+   .thumb_set SysTick_Handler,Default_Handler              
+  
+   .weak      WWDG_IRQHandler                   
+   .thumb_set WWDG_IRQHandler,Default_Handler      
+                  
+   .weak      PVD_IRQHandler      
+   .thumb_set PVD_IRQHandler,Default_Handler
+               
+   .weak      TAMP_STAMP_IRQHandler            
+   .thumb_set TAMP_STAMP_IRQHandler,Default_Handler
+            
+   .weak      RTC_WKUP_IRQHandler                  
+   .thumb_set RTC_WKUP_IRQHandler,Default_Handler
+            
+   .weak      FLASH_IRQHandler         
+   .thumb_set FLASH_IRQHandler,Default_Handler
+                  
+   .weak      RCC_IRQHandler      
+   .thumb_set RCC_IRQHandler,Default_Handler
+                  
+   .weak      EXTI0_IRQHandler         
+   .thumb_set EXTI0_IRQHandler,Default_Handler
+                  
+   .weak      EXTI1_IRQHandler         
+   .thumb_set EXTI1_IRQHandler,Default_Handler
+                     
+   .weak      EXTI2_IRQHandler         
+   .thumb_set EXTI2_IRQHandler,Default_Handler 
+                 
+   .weak      EXTI3_IRQHandler         
+   .thumb_set EXTI3_IRQHandler,Default_Handler
+                        
+   .weak      EXTI4_IRQHandler         
+   .thumb_set EXTI4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream0_IRQHandler               
+   .thumb_set DMA1_Stream0_IRQHandler,Default_Handler
+         
+   .weak      DMA1_Stream1_IRQHandler               
+   .thumb_set DMA1_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream2_IRQHandler               
+   .thumb_set DMA1_Stream2_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream3_IRQHandler               
+   .thumb_set DMA1_Stream3_IRQHandler,Default_Handler 
+                 
+   .weak      DMA1_Stream4_IRQHandler              
+   .thumb_set DMA1_Stream4_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream5_IRQHandler               
+   .thumb_set DMA1_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream6_IRQHandler               
+   .thumb_set DMA1_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      ADC_IRQHandler      
+   .thumb_set ADC_IRQHandler,Default_Handler
+               
+   .weak      CAN1_TX_IRQHandler   
+   .thumb_set CAN1_TX_IRQHandler,Default_Handler
+            
+   .weak      CAN1_RX0_IRQHandler                  
+   .thumb_set CAN1_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN1_RX1_IRQHandler                  
+   .thumb_set CAN1_RX1_IRQHandler,Default_Handler
+            
+   .weak      CAN1_SCE_IRQHandler                  
+   .thumb_set CAN1_SCE_IRQHandler,Default_Handler
+            
+   .weak      EXTI9_5_IRQHandler   
+   .thumb_set EXTI9_5_IRQHandler,Default_Handler
+            
+   .weak      TIM1_BRK_TIM9_IRQHandler            
+   .thumb_set TIM1_BRK_TIM9_IRQHandler,Default_Handler
+            
+   .weak      TIM1_UP_TIM10_IRQHandler            
+   .thumb_set TIM1_UP_TIM10_IRQHandler,Default_Handler
+      
+   .weak      TIM1_TRG_COM_TIM11_IRQHandler      
+   .thumb_set TIM1_TRG_COM_TIM11_IRQHandler,Default_Handler
+      
+   .weak      TIM1_CC_IRQHandler   
+   .thumb_set TIM1_CC_IRQHandler,Default_Handler
+                  
+   .weak      TIM2_IRQHandler            
+   .thumb_set TIM2_IRQHandler,Default_Handler
+                  
+   .weak      TIM3_IRQHandler            
+   .thumb_set TIM3_IRQHandler,Default_Handler
+                  
+   .weak      TIM4_IRQHandler            
+   .thumb_set TIM4_IRQHandler,Default_Handler
+                  
+   .weak      I2C1_EV_IRQHandler   
+   .thumb_set I2C1_EV_IRQHandler,Default_Handler
+                     
+   .weak      I2C1_ER_IRQHandler   
+   .thumb_set I2C1_ER_IRQHandler,Default_Handler
+                     
+   .weak      I2C2_EV_IRQHandler   
+   .thumb_set I2C2_EV_IRQHandler,Default_Handler
+                  
+   .weak      I2C2_ER_IRQHandler   
+   .thumb_set I2C2_ER_IRQHandler,Default_Handler
+                           
+   .weak      SPI1_IRQHandler            
+   .thumb_set SPI1_IRQHandler,Default_Handler
+                        
+   .weak      SPI2_IRQHandler            
+   .thumb_set SPI2_IRQHandler,Default_Handler
+                  
+   .weak      USART1_IRQHandler      
+   .thumb_set USART1_IRQHandler,Default_Handler
+                     
+   .weak      USART2_IRQHandler      
+   .thumb_set USART2_IRQHandler,Default_Handler
+                     
+   .weak      USART3_IRQHandler      
+   .thumb_set USART3_IRQHandler,Default_Handler
+                  
+   .weak      EXTI15_10_IRQHandler               
+   .thumb_set EXTI15_10_IRQHandler,Default_Handler
+               
+   .weak      RTC_Alarm_IRQHandler               
+   .thumb_set RTC_Alarm_IRQHandler,Default_Handler
+            
+   .weak      OTG_FS_WKUP_IRQHandler         
+   .thumb_set OTG_FS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      TIM8_BRK_TIM12_IRQHandler         
+   .thumb_set TIM8_BRK_TIM12_IRQHandler,Default_Handler
+         
+   .weak      TIM8_UP_TIM13_IRQHandler            
+   .thumb_set TIM8_UP_TIM13_IRQHandler,Default_Handler
+         
+   .weak      TIM8_TRG_COM_TIM14_IRQHandler      
+   .thumb_set TIM8_TRG_COM_TIM14_IRQHandler,Default_Handler
+      
+   .weak      TIM8_CC_IRQHandler   
+   .thumb_set TIM8_CC_IRQHandler,Default_Handler
+                  
+   .weak      DMA1_Stream7_IRQHandler               
+   .thumb_set DMA1_Stream7_IRQHandler,Default_Handler
+                     
+   .weak      FSMC_IRQHandler            
+   .thumb_set FSMC_IRQHandler,Default_Handler
+                     
+   .weak      SDIO_IRQHandler            
+   .thumb_set SDIO_IRQHandler,Default_Handler
+                     
+   .weak      TIM5_IRQHandler            
+   .thumb_set TIM5_IRQHandler,Default_Handler
+                     
+   .weak      SPI3_IRQHandler            
+   .thumb_set SPI3_IRQHandler,Default_Handler
+                     
+   .weak      UART4_IRQHandler         
+   .thumb_set UART4_IRQHandler,Default_Handler
+                  
+   .weak      UART5_IRQHandler         
+   .thumb_set UART5_IRQHandler,Default_Handler
+                  
+   .weak      TIM6_DAC_IRQHandler                  
+   .thumb_set TIM6_DAC_IRQHandler,Default_Handler
+               
+   .weak      TIM7_IRQHandler            
+   .thumb_set TIM7_IRQHandler,Default_Handler
+         
+   .weak      DMA2_Stream0_IRQHandler               
+   .thumb_set DMA2_Stream0_IRQHandler,Default_Handler
+               
+   .weak      DMA2_Stream1_IRQHandler               
+   .thumb_set DMA2_Stream1_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream2_IRQHandler               
+   .thumb_set DMA2_Stream2_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream3_IRQHandler               
+   .thumb_set DMA2_Stream3_IRQHandler,Default_Handler
+            
+   .weak      DMA2_Stream4_IRQHandler               
+   .thumb_set DMA2_Stream4_IRQHandler,Default_Handler
+            
+   .weak      ETH_IRQHandler      
+   .thumb_set ETH_IRQHandler,Default_Handler
+                  
+   .weak      ETH_WKUP_IRQHandler                  
+   .thumb_set ETH_WKUP_IRQHandler,Default_Handler
+            
+   .weak      CAN2_TX_IRQHandler   
+   .thumb_set CAN2_TX_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_RX0_IRQHandler                  
+   .thumb_set CAN2_RX0_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_RX1_IRQHandler                  
+   .thumb_set CAN2_RX1_IRQHandler,Default_Handler
+                           
+   .weak      CAN2_SCE_IRQHandler                  
+   .thumb_set CAN2_SCE_IRQHandler,Default_Handler
+                           
+   .weak      OTG_FS_IRQHandler      
+   .thumb_set OTG_FS_IRQHandler,Default_Handler
+                     
+   .weak      DMA2_Stream5_IRQHandler               
+   .thumb_set DMA2_Stream5_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream6_IRQHandler               
+   .thumb_set DMA2_Stream6_IRQHandler,Default_Handler
+                  
+   .weak      DMA2_Stream7_IRQHandler               
+   .thumb_set DMA2_Stream7_IRQHandler,Default_Handler
+                  
+   .weak      USART6_IRQHandler      
+   .thumb_set USART6_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_EV_IRQHandler   
+   .thumb_set I2C3_EV_IRQHandler,Default_Handler
+                        
+   .weak      I2C3_ER_IRQHandler   
+   .thumb_set I2C3_ER_IRQHandler,Default_Handler
+                        
+   .weak      OTG_HS_EP1_OUT_IRQHandler         
+   .thumb_set OTG_HS_EP1_OUT_IRQHandler,Default_Handler
+               
+   .weak      OTG_HS_EP1_IN_IRQHandler            
+   .thumb_set OTG_HS_EP1_IN_IRQHandler,Default_Handler
+               
+   .weak      OTG_HS_WKUP_IRQHandler         
+   .thumb_set OTG_HS_WKUP_IRQHandler,Default_Handler
+            
+   .weak      OTG_HS_IRQHandler      
+   .thumb_set OTG_HS_IRQHandler,Default_Handler
+                  
+   .weak      DCMI_IRQHandler            
+   .thumb_set DCMI_IRQHandler,Default_Handler
+                     
+   .weak      CRYP_IRQHandler            
+   .thumb_set CRYP_IRQHandler,Default_Handler
+               
+   .weak      HASH_RNG_IRQHandler                  
+   .thumb_set HASH_RNG_IRQHandler,Default_Handler   
+
+   .weak      FPU_IRQHandler                  
+   .thumb_set FPU_IRQHandler,Default_Handler  
+   
+/*******************   (C)   COPYRIGHT   2011   STMicroelectronics   *****END   OF   FILE****/
diff --git a/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/iar/startup_stm32f4xx.s b/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/iar/startup_stm32f4xx.s
new file mode 100644
index 0000000000..ffc38b8865
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/iar/startup_stm32f4xx.s
@@ -0,0 +1,630 @@
+;/******************** (C) COPYRIGHT 2011 STMicroelectronics ********************
+;* File Name          : startup_stm32f4xx.s
+;* Author             : MCD Application Team
+;* Version            : V1.0.0RC1
+;* Date               : 25-August-2011
+;* Description        : STM32F40x devices vector table for EWARM toolchain.
+;*                      This module performs:
+;*                      - Set the initial SP
+;*                      - Set the initial PC == _iar_program_start,
+;*                      - Set the vector table entries with the exceptions ISR 
+;*                        address.
+;*                      After Reset the Cortex-M4 processor is in Thread mode,
+;*                      priority is Privileged, and the Stack is set to Main.
+;********************************************************************************
+;* THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+;* WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE TIME.
+;* AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY DIRECT,
+;* INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING FROM THE
+;* CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE CODING
+;* INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+;*******************************************************************************/
+;
+;
+; The modules in this file are included in the libraries, and may be replaced
+; by any user-defined modules that define the PUBLIC symbol _program_start or
+; a user defined start symbol.
+; To override the cstartup defined in the library, simply add your modified
+; version to the workbench project.
+;
+; The vector table is normally located at address 0.
+; When debugging in RAM, it can be located in RAM, aligned to at least 2^6.
+; The name "__vector_table" has special meaning for C-SPY:
+; it is where the SP start value is found, and the NVIC vector
+; table register (VTOR) is initialized to this address if != 0.
+;
+; Cortex-M version
+;
+
+        MODULE  ?cstartup
+
+        ;; Forward declaration of sections.
+        SECTION CSTACK:DATA:NOROOT(3)
+
+        SECTION .intvec:CODE:NOROOT(2)
+
+        EXTERN  __iar_program_start
+        EXTERN  SystemInit
+        PUBLIC  __vector_table
+
+        DATA
+__vector_table
+        DCD     sfe(CSTACK)
+        DCD     Reset_Handler             ; Reset Handler
+
+        DCD     NMI_Handler               ; NMI Handler
+        DCD     HardFault_Handler         ; Hard Fault Handler
+        DCD     MemManage_Handler         ; MPU Fault Handler
+        DCD     BusFault_Handler          ; Bus Fault Handler
+        DCD     UsageFault_Handler        ; Usage Fault Handler
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     0                         ; Reserved
+        DCD     SVC_Handler               ; SVCall Handler
+        DCD     DebugMon_Handler          ; Debug Monitor Handler
+        DCD     0                         ; Reserved
+        DCD     PendSV_Handler            ; PendSV Handler
+        DCD     SysTick_Handler           ; SysTick Handler
+
+         ; External Interrupts
+        DCD     WWDG_IRQHandler                   ; Window WatchDog                                        
+        DCD     PVD_IRQHandler                    ; PVD through EXTI Line detection                        
+        DCD     TAMP_STAMP_IRQHandler             ; Tamper and TimeStamps through the EXTI line            
+        DCD     RTC_WKUP_IRQHandler               ; RTC Wakeup through the EXTI line                       
+        DCD     FLASH_IRQHandler                  ; FLASH                                           
+        DCD     RCC_IRQHandler                    ; RCC                                             
+        DCD     EXTI0_IRQHandler                  ; EXTI Line0                                             
+        DCD     EXTI1_IRQHandler                  ; EXTI Line1                                             
+        DCD     EXTI2_IRQHandler                  ; EXTI Line2                                             
+        DCD     EXTI3_IRQHandler                  ; EXTI Line3                                             
+        DCD     EXTI4_IRQHandler                  ; EXTI Line4                                             
+        DCD     DMA1_Stream0_IRQHandler           ; DMA1 Stream 0                                   
+        DCD     DMA1_Stream1_IRQHandler           ; DMA1 Stream 1                                   
+        DCD     DMA1_Stream2_IRQHandler           ; DMA1 Stream 2                                   
+        DCD     DMA1_Stream3_IRQHandler           ; DMA1 Stream 3                                   
+        DCD     DMA1_Stream4_IRQHandler           ; DMA1 Stream 4                                   
+        DCD     DMA1_Stream5_IRQHandler           ; DMA1 Stream 5                                   
+        DCD     DMA1_Stream6_IRQHandler           ; DMA1 Stream 6                                   
+        DCD     ADC_IRQHandler                    ; ADC1, ADC2 and ADC3s                            
+        DCD     CAN1_TX_IRQHandler                ; CAN1 TX                                                
+        DCD     CAN1_RX0_IRQHandler               ; CAN1 RX0                                               
+        DCD     CAN1_RX1_IRQHandler               ; CAN1 RX1                                               
+        DCD     CAN1_SCE_IRQHandler               ; CAN1 SCE                                               
+        DCD     EXTI9_5_IRQHandler                ; External Line[9:5]s                                    
+        DCD     TIM1_BRK_TIM9_IRQHandler          ; TIM1 Break and TIM9                   
+        DCD     TIM1_UP_TIM10_IRQHandler          ; TIM1 Update and TIM10                 
+        DCD     TIM1_TRG_COM_TIM11_IRQHandler     ; TIM1 Trigger and Commutation and TIM11
+        DCD     TIM1_CC_IRQHandler                ; TIM1 Capture Compare                                   
+        DCD     TIM2_IRQHandler                   ; TIM2                                            
+        DCD     TIM3_IRQHandler                   ; TIM3                                            
+        DCD     TIM4_IRQHandler                   ; TIM4                                            
+        DCD     I2C1_EV_IRQHandler                ; I2C1 Event                                             
+        DCD     I2C1_ER_IRQHandler                ; I2C1 Error                                             
+        DCD     I2C2_EV_IRQHandler                ; I2C2 Event                                             
+        DCD     I2C2_ER_IRQHandler                ; I2C2 Error                                               
+        DCD     SPI1_IRQHandler                   ; SPI1                                            
+        DCD     SPI2_IRQHandler                   ; SPI2                                            
+        DCD     USART1_IRQHandler                 ; USART1                                          
+        DCD     USART2_IRQHandler                 ; USART2                                          
+        DCD     USART3_IRQHandler                 ; USART3                                          
+        DCD     EXTI15_10_IRQHandler              ; External Line[15:10]s                                  
+        DCD     RTC_Alarm_IRQHandler              ; RTC Alarm (A and B) through EXTI Line                  
+        DCD     OTG_FS_WKUP_IRQHandler            ; USB OTG FS Wakeup through EXTI line                        
+        DCD     TIM8_BRK_TIM12_IRQHandler         ; TIM8 Break and TIM12                  
+        DCD     TIM8_UP_TIM13_IRQHandler          ; TIM8 Update and TIM13                 
+        DCD     TIM8_TRG_COM_TIM14_IRQHandler     ; TIM8 Trigger and Commutation and TIM14
+        DCD     TIM8_CC_IRQHandler                ; TIM8 Capture Compare                                   
+        DCD     DMA1_Stream7_IRQHandler           ; DMA1 Stream7                                           
+        DCD     FSMC_IRQHandler                   ; FSMC                                            
+        DCD     SDIO_IRQHandler                   ; SDIO                                            
+        DCD     TIM5_IRQHandler                   ; TIM5                                            
+        DCD     SPI3_IRQHandler                   ; SPI3                                            
+        DCD     UART4_IRQHandler                  ; UART4                                           
+        DCD     UART5_IRQHandler                  ; UART5                                           
+        DCD     TIM6_DAC_IRQHandler               ; TIM6 and DAC1&2 underrun errors                   
+        DCD     TIM7_IRQHandler                   ; TIM7                   
+        DCD     DMA2_Stream0_IRQHandler           ; DMA2 Stream 0                                   
+        DCD     DMA2_Stream1_IRQHandler           ; DMA2 Stream 1                                   
+        DCD     DMA2_Stream2_IRQHandler           ; DMA2 Stream 2                                   
+        DCD     DMA2_Stream3_IRQHandler           ; DMA2 Stream 3                                   
+        DCD     DMA2_Stream4_IRQHandler           ; DMA2 Stream 4                                   
+        DCD     ETH_IRQHandler                    ; Ethernet                                        
+        DCD     ETH_WKUP_IRQHandler               ; Ethernet Wakeup through EXTI line                      
+        DCD     CAN2_TX_IRQHandler                ; CAN2 TX                                                
+        DCD     CAN2_RX0_IRQHandler               ; CAN2 RX0                                               
+        DCD     CAN2_RX1_IRQHandler               ; CAN2 RX1                                               
+        DCD     CAN2_SCE_IRQHandler               ; CAN2 SCE                                               
+        DCD     OTG_FS_IRQHandler                 ; USB OTG FS                                      
+        DCD     DMA2_Stream5_IRQHandler           ; DMA2 Stream 5                                   
+        DCD     DMA2_Stream6_IRQHandler           ; DMA2 Stream 6                                   
+        DCD     DMA2_Stream7_IRQHandler           ; DMA2 Stream 7                                   
+        DCD     USART6_IRQHandler                 ; USART6                                           
+        DCD     I2C3_EV_IRQHandler                ; I2C3 event                                             
+        DCD     I2C3_ER_IRQHandler                ; I2C3 error                                             
+        DCD     OTG_HS_EP1_OUT_IRQHandler         ; USB OTG HS End Point 1 Out                      
+        DCD     OTG_HS_EP1_IN_IRQHandler          ; USB OTG HS End Point 1 In                       
+        DCD     OTG_HS_WKUP_IRQHandler            ; USB OTG HS Wakeup through EXTI                         
+        DCD     OTG_HS_IRQHandler                 ; USB OTG HS                                      
+        DCD     DCMI_IRQHandler                   ; DCMI                                            
+        DCD     CRYP_IRQHandler                   ; CRYP crypto                                     
+        DCD     HASH_RNG_IRQHandler               ; Hash and Rng
+        DCD     FPU_IRQHandler                    ; FPU
+
+;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;;
+;;
+;; Default interrupt handlers.
+;;
+        THUMB
+        PUBWEAK Reset_Handler
+        SECTION .text:CODE:REORDER(2)
+Reset_Handler
+
+        ;FPU settings
+        LDR     R0, =0xE000ED88           ; Enable CP10,CP11
+        LDR     R1,[R0]
+        ORR     R1,R1,#(0xF << 20)
+        STR     R1,[R0]
+
+        LDR     R0, =SystemInit
+        BLX     R0
+        LDR     R0, =__iar_program_start
+        BX      R0
+
+        PUBWEAK NMI_Handler
+        SECTION .text:CODE:REORDER(1)
+NMI_Handler
+        B NMI_Handler
+
+        PUBWEAK HardFault_Handler
+        SECTION .text:CODE:REORDER(1)
+HardFault_Handler
+        B HardFault_Handler
+
+        PUBWEAK MemManage_Handler
+        SECTION .text:CODE:REORDER(1)
+MemManage_Handler
+        B MemManage_Handler
+
+        PUBWEAK BusFault_Handler
+        SECTION .text:CODE:REORDER(1)
+BusFault_Handler
+        B BusFault_Handler
+
+        PUBWEAK UsageFault_Handler
+        SECTION .text:CODE:REORDER(1)
+UsageFault_Handler
+        B UsageFault_Handler
+
+        PUBWEAK SVC_Handler
+        SECTION .text:CODE:REORDER(1)
+SVC_Handler
+        B SVC_Handler
+
+        PUBWEAK DebugMon_Handler
+        SECTION .text:CODE:REORDER(1)
+DebugMon_Handler
+        B DebugMon_Handler
+
+        PUBWEAK PendSV_Handler
+        SECTION .text:CODE:REORDER(1)
+PendSV_Handler
+        B PendSV_Handler
+
+        PUBWEAK SysTick_Handler
+        SECTION .text:CODE:REORDER(1)
+SysTick_Handler
+        B SysTick_Handler
+
+        PUBWEAK WWDG_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+WWDG_IRQHandler  
+        B WWDG_IRQHandler
+
+        PUBWEAK PVD_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+PVD_IRQHandler  
+        B PVD_IRQHandler
+
+        PUBWEAK TAMP_STAMP_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TAMP_STAMP_IRQHandler  
+        B TAMP_STAMP_IRQHandler
+
+        PUBWEAK RTC_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+RTC_WKUP_IRQHandler  
+        B RTC_WKUP_IRQHandler
+
+        PUBWEAK FLASH_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+FLASH_IRQHandler  
+        B FLASH_IRQHandler
+
+        PUBWEAK RCC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+RCC_IRQHandler  
+        B RCC_IRQHandler
+
+        PUBWEAK EXTI0_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI0_IRQHandler  
+        B EXTI0_IRQHandler
+
+        PUBWEAK EXTI1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI1_IRQHandler  
+        B EXTI1_IRQHandler
+
+        PUBWEAK EXTI2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI2_IRQHandler  
+        B EXTI2_IRQHandler
+
+        PUBWEAK EXTI3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+EXTI3_IRQHandler
+        B EXTI3_IRQHandler
+
+        PUBWEAK EXTI4_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+EXTI4_IRQHandler  
+        B EXTI4_IRQHandler
+
+        PUBWEAK DMA1_Stream0_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Stream0_IRQHandler  
+        B DMA1_Stream0_IRQHandler
+
+        PUBWEAK DMA1_Stream1_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Stream1_IRQHandler  
+        B DMA1_Stream1_IRQHandler
+
+        PUBWEAK DMA1_Stream2_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Stream2_IRQHandler  
+        B DMA1_Stream2_IRQHandler
+
+        PUBWEAK DMA1_Stream3_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Stream3_IRQHandler  
+        B DMA1_Stream3_IRQHandler
+
+        PUBWEAK DMA1_Stream4_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Stream4_IRQHandler  
+        B DMA1_Stream4_IRQHandler
+
+        PUBWEAK DMA1_Stream5_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Stream5_IRQHandler  
+        B DMA1_Stream5_IRQHandler
+
+        PUBWEAK DMA1_Stream6_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Stream6_IRQHandler  
+        B DMA1_Stream6_IRQHandler
+
+        PUBWEAK ADC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ADC_IRQHandler  
+        B ADC_IRQHandler
+
+        PUBWEAK CAN1_TX_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+CAN1_TX_IRQHandler  
+        B CAN1_TX_IRQHandler
+
+        PUBWEAK CAN1_RX0_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+CAN1_RX0_IRQHandler  
+        B CAN1_RX0_IRQHandler
+
+        PUBWEAK CAN1_RX1_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+CAN1_RX1_IRQHandler  
+        B CAN1_RX1_IRQHandler
+
+        PUBWEAK CAN1_SCE_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+CAN1_SCE_IRQHandler  
+        B CAN1_SCE_IRQHandler
+
+        PUBWEAK EXTI9_5_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+EXTI9_5_IRQHandler  
+        B EXTI9_5_IRQHandler
+
+        PUBWEAK TIM1_BRK_TIM9_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM1_BRK_TIM9_IRQHandler  
+        B TIM1_BRK_TIM9_IRQHandler
+
+        PUBWEAK TIM1_UP_TIM10_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM1_UP_TIM10_IRQHandler  
+        B TIM1_UP_TIM10_IRQHandler
+
+        PUBWEAK TIM1_TRG_COM_TIM11_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM1_TRG_COM_TIM11_IRQHandler  
+        B TIM1_TRG_COM_TIM11_IRQHandler
+        
+        PUBWEAK TIM1_CC_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM1_CC_IRQHandler  
+        B TIM1_CC_IRQHandler
+
+        PUBWEAK TIM2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM2_IRQHandler  
+        B TIM2_IRQHandler
+
+        PUBWEAK TIM3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM3_IRQHandler  
+        B TIM3_IRQHandler
+
+        PUBWEAK TIM4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM4_IRQHandler  
+        B TIM4_IRQHandler
+
+        PUBWEAK I2C1_EV_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+I2C1_EV_IRQHandler  
+        B I2C1_EV_IRQHandler
+
+        PUBWEAK I2C1_ER_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+I2C1_ER_IRQHandler  
+        B I2C1_ER_IRQHandler
+
+        PUBWEAK I2C2_EV_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+I2C2_EV_IRQHandler  
+        B I2C2_EV_IRQHandler
+
+        PUBWEAK I2C2_ER_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+I2C2_ER_IRQHandler  
+        B I2C2_ER_IRQHandler
+
+        PUBWEAK SPI1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI1_IRQHandler  
+        B SPI1_IRQHandler
+
+        PUBWEAK SPI2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI2_IRQHandler  
+        B SPI2_IRQHandler
+
+        PUBWEAK USART1_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART1_IRQHandler  
+        B USART1_IRQHandler
+
+        PUBWEAK USART2_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART2_IRQHandler  
+        B USART2_IRQHandler
+
+        PUBWEAK USART3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART3_IRQHandler  
+        B USART3_IRQHandler
+
+        PUBWEAK EXTI15_10_IRQHandler
+        SECTION .text:CODE:REORDER(1)   
+EXTI15_10_IRQHandler  
+        B EXTI15_10_IRQHandler
+
+        PUBWEAK RTC_Alarm_IRQHandler
+        SECTION .text:CODE:REORDER(1)   
+RTC_Alarm_IRQHandler  
+        B RTC_Alarm_IRQHandler
+
+        PUBWEAK OTG_FS_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+OTG_FS_WKUP_IRQHandler  
+        B OTG_FS_WKUP_IRQHandler
+      
+        PUBWEAK TIM8_BRK_TIM12_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM8_BRK_TIM12_IRQHandler  
+        B TIM8_BRK_TIM12_IRQHandler
+
+        PUBWEAK TIM8_UP_TIM13_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM8_UP_TIM13_IRQHandler  
+        B TIM8_UP_TIM13_IRQHandler
+
+        PUBWEAK TIM8_TRG_COM_TIM14_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+TIM8_TRG_COM_TIM14_IRQHandler  
+        B TIM8_TRG_COM_TIM14_IRQHandler
+
+        PUBWEAK TIM8_CC_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+TIM8_CC_IRQHandler  
+        B TIM8_CC_IRQHandler
+
+        PUBWEAK DMA1_Stream7_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA1_Stream7_IRQHandler  
+        B DMA1_Stream7_IRQHandler
+
+        PUBWEAK FSMC_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+FSMC_IRQHandler  
+        B FSMC_IRQHandler
+
+        PUBWEAK SDIO_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SDIO_IRQHandler  
+        B SDIO_IRQHandler
+
+        PUBWEAK TIM5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+TIM5_IRQHandler  
+        B TIM5_IRQHandler
+
+        PUBWEAK SPI3_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+SPI3_IRQHandler  
+        B SPI3_IRQHandler
+
+        PUBWEAK UART4_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART4_IRQHandler  
+        B UART4_IRQHandler
+
+        PUBWEAK UART5_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+UART5_IRQHandler  
+        B UART5_IRQHandler
+
+        PUBWEAK TIM6_DAC_IRQHandler
+        SECTION .text:CODE:REORDER(1)   
+TIM6_DAC_IRQHandler  
+        B TIM6_DAC_IRQHandler
+
+        PUBWEAK TIM7_IRQHandler
+        SECTION .text:CODE:REORDER(1)   
+TIM7_IRQHandler  
+        B TIM7_IRQHandler
+
+        PUBWEAK DMA2_Stream0_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA2_Stream0_IRQHandler  
+        B DMA2_Stream0_IRQHandler
+
+        PUBWEAK DMA2_Stream1_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA2_Stream1_IRQHandler  
+        B DMA2_Stream1_IRQHandler
+
+        PUBWEAK DMA2_Stream2_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA2_Stream2_IRQHandler  
+        B DMA2_Stream2_IRQHandler
+
+        PUBWEAK DMA2_Stream3_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA2_Stream3_IRQHandler  
+        B DMA2_Stream3_IRQHandler
+
+        PUBWEAK DMA2_Stream4_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA2_Stream4_IRQHandler  
+        B DMA2_Stream4_IRQHandler
+
+        PUBWEAK ETH_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+ETH_IRQHandler  
+        B ETH_IRQHandler
+
+        PUBWEAK ETH_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+ETH_WKUP_IRQHandler  
+        B ETH_WKUP_IRQHandler
+
+        PUBWEAK CAN2_TX_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+CAN2_TX_IRQHandler  
+        B CAN2_TX_IRQHandler
+
+        PUBWEAK CAN2_RX0_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+CAN2_RX0_IRQHandler  
+        B CAN2_RX0_IRQHandler
+
+        PUBWEAK CAN2_RX1_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+CAN2_RX1_IRQHandler  
+        B CAN2_RX1_IRQHandler
+
+        PUBWEAK CAN2_SCE_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+CAN2_SCE_IRQHandler  
+        B CAN2_SCE_IRQHandler
+
+        PUBWEAK OTG_FS_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+OTG_FS_IRQHandler  
+        B OTG_FS_IRQHandler
+
+        PUBWEAK DMA2_Stream5_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA2_Stream5_IRQHandler  
+        B DMA2_Stream5_IRQHandler
+
+        PUBWEAK DMA2_Stream6_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA2_Stream6_IRQHandler  
+        B DMA2_Stream6_IRQHandler
+
+        PUBWEAK DMA2_Stream7_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+DMA2_Stream7_IRQHandler  
+        B DMA2_Stream7_IRQHandler
+
+        PUBWEAK USART6_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+USART6_IRQHandler  
+        B USART6_IRQHandler
+
+        PUBWEAK I2C3_EV_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+I2C3_EV_IRQHandler  
+        B I2C3_EV_IRQHandler
+
+        PUBWEAK I2C3_ER_IRQHandler
+        SECTION .text:CODE:REORDER(1) 
+I2C3_ER_IRQHandler  
+        B I2C3_ER_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_OUT_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+OTG_HS_EP1_OUT_IRQHandler  
+        B OTG_HS_EP1_OUT_IRQHandler
+
+        PUBWEAK OTG_HS_EP1_IN_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+OTG_HS_EP1_IN_IRQHandler  
+        B OTG_HS_EP1_IN_IRQHandler
+
+        PUBWEAK OTG_HS_WKUP_IRQHandler
+        SECTION .text:CODE:REORDER(1)    
+OTG_HS_WKUP_IRQHandler  
+        B OTG_HS_WKUP_IRQHandler
+
+        PUBWEAK OTG_HS_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+OTG_HS_IRQHandler  
+        B OTG_HS_IRQHandler
+
+        PUBWEAK DCMI_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+DCMI_IRQHandler  
+        B DCMI_IRQHandler
+
+        PUBWEAK CRYP_IRQHandler
+        SECTION .text:CODE:REORDER(1)
+CRYP_IRQHandler  
+        B CRYP_IRQHandler
+
+        PUBWEAK HASH_RNG_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+HASH_RNG_IRQHandler  
+        B HASH_RNG_IRQHandler
+
+        PUBWEAK FPU_IRQHandler
+        SECTION .text:CODE:REORDER(1)  
+FPU_IRQHandler  
+        B FPU_IRQHandler
+
+        END
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c b/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c
new file mode 100644
index 0000000000..80c885febc
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c
@@ -0,0 +1,544 @@
+/**
+  ******************************************************************************
+  * @file    system_stm32f4xx.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   CMSIS Cortex-M4 Device Peripheral Access Layer System Source File.
+  *          This file contains the system clock configuration for STM32F4xx devices,
+  *          and is generated by the clock configuration tool
+  *          stm32f4xx_Clock_Configuration_V1.0.0.xls
+  *             
+  * 1.  This file provides two functions and one global variable to be called from 
+  *     user application:
+  *      - SystemInit(): Setups the system clock (System clock source, PLL Multiplier
+  *                      and Divider factors, AHB/APBx prescalers and Flash settings),
+  *                      depending on the configuration made in the clock xls tool. 
+  *                      This function is called at startup just after reset and 
+  *                      before branch to main program. This call is made inside
+  *                      the "startup_stm32f4xx.s" file.
+  *
+  *      - SystemCoreClock variable: Contains the core clock (HCLK), it can be used
+  *                                  by the user application to setup the SysTick 
+  *                                  timer or configure other parameters.
+  *                                     
+  *      - SystemCoreClockUpdate(): Updates the variable SystemCoreClock and must
+  *                                 be called whenever the core clock is changed
+  *                                 during program execution.
+  *
+  * 2. After each device reset the HSI (16 MHz) is used as system clock source.
+  *    Then SystemInit() function is called, in "startup_stm32f4xx.s" file, to
+  *    configure the system clock before to branch to main program.
+  *
+  * 3. If the system clock source selected by user fails to startup, the SystemInit()
+  *    function will do nothing and HSI still used as system clock source. User can 
+  *    add some code to deal with this issue inside the SetSysClock() function.
+  *
+  * 4. The default value of HSE crystal is set to 25MHz, refer to "HSE_VALUE" define
+  *    in "stm32f4xx.h" file. When HSE is used as system clock source, directly or
+  *    through PLL, and you are using different crystal you have to adapt the HSE
+  *    value to your own configuration.
+  *
+  * 5. This file configures the system clock as follows:
+  *=============================================================================
+  *=============================================================================
+  *        Supported STM32F4xx device revision    | Rev A
+  *-----------------------------------------------------------------------------
+  *        System Clock source                    | PLL (HSE)
+  *-----------------------------------------------------------------------------
+  *        SYSCLK(Hz)                             | 168000000
+  *-----------------------------------------------------------------------------
+  *        HCLK(Hz)                               | 168000000
+  *-----------------------------------------------------------------------------
+  *        AHB Prescaler                          | 1
+  *-----------------------------------------------------------------------------
+  *        APB1 Prescaler                         | 4
+  *-----------------------------------------------------------------------------
+  *        APB2 Prescaler                         | 2
+  *-----------------------------------------------------------------------------
+  *        HSE Frequency(Hz)                      | 25000000
+  *-----------------------------------------------------------------------------
+  *        PLL_M                                  | 25
+  *-----------------------------------------------------------------------------
+  *        PLL_N                                  | 336
+  *-----------------------------------------------------------------------------
+  *        PLL_P                                  | 2
+  *-----------------------------------------------------------------------------
+  *        PLL_Q                                  | 7
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_N                               | NA
+  *-----------------------------------------------------------------------------
+  *        PLLI2S_R                               | NA
+  *-----------------------------------------------------------------------------
+  *        I2S input clock                        | NA
+  *-----------------------------------------------------------------------------
+  *        VDD(V)                                 | 3.3
+  *-----------------------------------------------------------------------------
+  *        High Performance mode                  | Enabled
+  *-----------------------------------------------------------------------------
+  *        Flash Latency(WS)                      | 5
+  *-----------------------------------------------------------------------------
+  *        Prefetch Buffer                        | OFF
+  *-----------------------------------------------------------------------------
+  *        Instruction cache                      | ON
+  *-----------------------------------------------------------------------------
+  *        Data cache                             | ON
+  *-----------------------------------------------------------------------------
+  *        Require 48MHz for USB OTG FS,          | Enabled
+  *        SDIO and RNG clock                     |
+  *-----------------------------------------------------------------------------
+  *=============================================================================
+  ****************************************************************************** 
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/** @addtogroup CMSIS
+  * @{
+  */
+
+/** @addtogroup stm32f4xx_system
+  * @{
+  */  
+  
+/** @addtogroup STM32F4xx_System_Private_Includes
+  * @{
+  */
+
+#include "stm32f4xx.h"
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_TypesDefinitions
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Defines
+  * @{
+  */
+
+/*!< Uncomment the following line if you need to use external SRAM mounted
+     on STM324xG_EVAL board as data memory  */
+/* #define DATA_IN_ExtSRAM */
+
+/*!< Uncomment the following line if you need to relocate your vector Table in
+     Internal SRAM. */
+/* #define VECT_TAB_SRAM */
+#define VECT_TAB_OFFSET  0x00 /*!< Vector Table base offset field. 
+                                   This value must be a multiple of 0x200. */
+
+
+/* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N */
+#define PLL_M      25
+#define PLL_N      336
+
+/* SYSCLK = PLL_VCO / PLL_P */
+#define PLL_P      2
+
+/* USB OTG FS, SDIO and RNG Clock =  PLL_VCO / PLLQ */
+#define PLL_Q      7
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Macros
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Variables
+  * @{
+  */
+
+  uint32_t SystemCoreClock = 168000000;
+
+  __I uint8_t AHBPrescTable[16] = {0, 0, 0, 0, 0, 0, 0, 0, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_FunctionPrototypes
+  * @{
+  */
+
+static void SetSysClock(void);
+#ifdef DATA_IN_ExtSRAM
+  static void SystemInit_ExtMemCtl(void); 
+#endif /* DATA_IN_ExtSRAM */
+
+/**
+  * @}
+  */
+
+/** @addtogroup STM32F4xx_System_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Setup the microcontroller system
+  *         Initialize the Embedded Flash Interface, the PLL and update the 
+  *         SystemFrequency variable.
+  * @param  None
+  * @retval None
+  */
+void SystemInit(void)
+{
+  /* Reset the RCC clock configuration to the default reset state ------------*/
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+
+#ifdef DATA_IN_ExtSRAM
+  SystemInit_ExtMemCtl(); 
+#endif /* DATA_IN_ExtSRAM */
+         
+  /* Configure the System clock source, PLL Multiplier and Divider factors, 
+     AHB/APBx prescalers and Flash settings ----------------------------------*/
+  SetSysClock();
+
+  /* Configure the Vector Table location add offset address ------------------*/
+#ifdef VECT_TAB_SRAM
+  SCB->VTOR = SRAM_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal SRAM */
+#else
+  SCB->VTOR = FLASH_BASE | VECT_TAB_OFFSET; /* Vector Table Relocation in Internal FLASH */
+#endif
+}
+
+/**
+   * @brief  Update SystemCoreClock variable according to Clock Register Values.
+  *         The SystemCoreClock variable contains the core clock (HCLK), it can
+  *         be used by the user application to setup the SysTick timer or configure
+  *         other parameters.
+  *           
+  * @note   Each time the core clock (HCLK) changes, this function must be called
+  *         to update SystemCoreClock variable value. Otherwise, any configuration
+  *         based on this variable will be incorrect.         
+  *     
+  * @note   - The system frequency computed by this function is not the real 
+  *           frequency in the chip. It is calculated based on the predefined 
+  *           constant and the selected clock source:
+  *             
+  *           - If SYSCLK source is HSI, SystemCoreClock will contain the HSI_VALUE(*)
+  *                                              
+  *           - If SYSCLK source is HSE, SystemCoreClock will contain the HSE_VALUE(**)
+  *                          
+  *           - If SYSCLK source is PLL, SystemCoreClock will contain the HSE_VALUE(**) 
+  *             or HSI_VALUE(*) multiplied/divided by the PLL factors.
+  *         
+  *         (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
+  *             16 MHz) but the real value may vary depending on the variations
+  *             in voltage and temperature.   
+  *    
+  *         (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
+  *              25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *              frequency of the crystal used. Otherwise, this function may
+  *              have wrong result.
+  *                
+  *         - The result of this function could be not correct when using fractional
+  *           value for HSE crystal.
+  *     
+  * @param  None
+  * @retval None
+  */
+void SystemCoreClockUpdate(void)
+{
+  uint32_t tmp = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+  
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      SystemCoreClock = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock source */
+      SystemCoreClock = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLL_M) * PLL_N
+         SYSCLK = PLL_VCO / PLL_P
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      SystemCoreClock = pllvco/pllp;
+      break;
+    default:
+      SystemCoreClock = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK frequency --------------------------------------------------*/
+  /* Get HCLK prescaler */
+  tmp = AHBPrescTable[((RCC->CFGR & RCC_CFGR_HPRE) >> 4)];
+  /* HCLK frequency */
+  SystemCoreClock >>= tmp;
+}
+
+/**
+  * @brief  Configures the System clock source, PLL Multiplier and Divider factors, 
+  *         AHB/APBx prescalers and Flash settings
+  * @Note   This function should be called only once the RCC clock configuration  
+  *         is reset to the default reset state (done in SystemInit() function).   
+  * @param  None
+  * @retval None
+  */
+static void SetSysClock(void)
+{
+/******************************************************************************/
+/*            PLL (clocked by HSE) used as System clock source                */
+/******************************************************************************/
+  __IO uint32_t StartUpCounter = 0, HSEStatus = 0;
+  
+  /* Enable HSE */
+  RCC->CR |= ((uint32_t)RCC_CR_HSEON);
+ 
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    HSEStatus = RCC->CR & RCC_CR_HSERDY;
+    StartUpCounter++;
+  } while((HSEStatus == 0) && (StartUpCounter != HSE_STARTUP_TIMEOUT));
+
+  if ((RCC->CR & RCC_CR_HSERDY) != RESET)
+  {
+    HSEStatus = (uint32_t)0x01;
+  }
+  else
+  {
+    HSEStatus = (uint32_t)0x00;
+  }
+
+  if (HSEStatus == (uint32_t)0x01)
+  {
+    /* Enable high performance mode, System frequency up to 168 MHz */
+    RCC->APB1ENR |= RCC_APB1ENR_PWREN;
+    PWR->CR |= PWR_CR_PMODE;  
+
+    /* HCLK = SYSCLK / 1*/
+    RCC->CFGR |= RCC_CFGR_HPRE_DIV1;
+      
+    /* PCLK2 = HCLK / 2*/
+    RCC->CFGR |= RCC_CFGR_PPRE2_DIV2;
+    
+    /* PCLK1 = HCLK / 4*/
+    RCC->CFGR |= RCC_CFGR_PPRE1_DIV4;
+
+    /* Configure the main PLL */
+    RCC->PLLCFGR = PLL_M | (PLL_N << 6) | (((PLL_P >> 1) -1) << 16) |
+                   (RCC_PLLCFGR_PLLSRC_HSE) | (PLL_Q << 24);
+
+    /* Enable the main PLL */
+    RCC->CR |= RCC_CR_PLLON;
+
+    /* Wait till the main PLL is ready */
+    while((RCC->CR & RCC_CR_PLLRDY) == 0)
+    {
+    }
+   
+    /* Configure Flash prefetch, Instruction cache, Data cache and wait state */
+    FLASH->ACR = FLASH_ACR_ICEN |FLASH_ACR_DCEN |FLASH_ACR_LATENCY_5WS;
+
+    /* Select the main PLL as system clock source */
+    RCC->CFGR &= (uint32_t)((uint32_t)~(RCC_CFGR_SW));
+    RCC->CFGR |= RCC_CFGR_SW_PLL;
+
+    /* Wait till the main PLL is used as system clock source */
+    while ((RCC->CFGR & (uint32_t)RCC_CFGR_SWS ) != RCC_CFGR_SWS_PLL);
+    {
+    }
+  }
+  else
+  { /* If HSE fails to start-up, the application will have wrong clock
+         configuration. User can add here some code to deal with this error */
+  }
+
+}
+
+/**
+  * @brief  Setup the external memory controller. Called in startup_stm32f4xx.s 
+  *          before jump to __main
+  * @param  None
+  * @retval None
+  */ 
+#ifdef DATA_IN_ExtSRAM
+/**
+  * @brief  Setup the external memory controller.
+  *         Called in startup_stm32f4xx.s before jump to main.
+  *         This function configures the external SRAM mounted on STM324xG_EVAL board
+  *         This SRAM will be used as program data memory (including heap and stack).
+  * @param  None
+  * @retval None
+  */
+void SystemInit_ExtMemCtl(void)
+{
+/*-- GPIOs Configuration -----------------------------------------------------*/
+/*
+ +-------------------+--------------------+------------------+------------------+
+ +                       SRAM pins assignment                                   +
+ +-------------------+--------------------+------------------+------------------+
+ | PD0  <-> FSMC_D2  | PE0  <-> FSMC_NBL0 | PF0  <-> FSMC_A0 | PG0 <-> FSMC_A10 | 
+ | PD1  <-> FSMC_D3  | PE1  <-> FSMC_NBL1 | PF1  <-> FSMC_A1 | PG1 <-> FSMC_A11 | 
+ | PD4  <-> FSMC_NOE | PE3  <-> FSMC_A19  | PF2  <-> FSMC_A2 | PG2 <-> FSMC_A12 | 
+ | PD5  <-> FSMC_NWE | PE4  <-> FSMC_A20  | PF3  <-> FSMC_A3 | PG3 <-> FSMC_A13 | 
+ | PD8  <-> FSMC_D13 | PE7  <-> FSMC_D4   | PF4  <-> FSMC_A4 | PG4 <-> FSMC_A14 | 
+ | PD9  <-> FSMC_D14 | PE8  <-> FSMC_D5   | PF5  <-> FSMC_A5 | PG5 <-> FSMC_A15 | 
+ | PD10 <-> FSMC_D15 | PE9  <-> FSMC_D6   | PF12 <-> FSMC_A6 | PG9 <-> FSMC_NE2 | 
+ | PD11 <-> FSMC_A16 | PE10 <-> FSMC_D7   | PF13 <-> FSMC_A7 |------------------+
+ | PD12 <-> FSMC_A17 | PE11 <-> FSMC_D8   | PF14 <-> FSMC_A8 | 
+ | PD13 <-> FSMC_A18 | PE12 <-> FSMC_D9   | PF15 <-> FSMC_A9 | 
+ | PD14 <-> FSMC_D0  | PE13 <-> FSMC_D10  |------------------+
+ | PD15 <-> FSMC_D1  | PE14 <-> FSMC_D11  |
+ |                   | PE15 <-> FSMC_D12  |
+ +-------------------+--------------------+
+*/
+   /* Enable GPIOD, GPIOE, GPIOF and GPIOG interface clock */
+  RCC->AHB1ENR   = 0x00000078;
+  
+  /* Connect PDx pins to FSMC Alternate function */
+  GPIOD->AFR[0]  = 0x00cc00cc;
+  GPIOD->AFR[1]  = 0xcc0ccccc;
+  /* Configure PDx pins in Alternate function mode */  
+  GPIOD->MODER   = 0xaaaa0a0a;
+  /* Configure PDx pins speed to 100 MHz */  
+  GPIOD->OSPEEDR = 0xffff0f0f;
+  /* Configure PDx pins Output type to push-pull */  
+  GPIOD->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PDx pins */ 
+  GPIOD->PUPDR   = 0x00000000;
+
+  /* Connect PEx pins to FSMC Alternate function */
+  GPIOE->AFR[0]  = 0xc00cc0cc;
+  GPIOE->AFR[1]  = 0xcccccccc;
+  /* Configure PEx pins in Alternate function mode */ 
+  GPIOE->MODER   = 0xaaaa828a;
+  /* Configure PEx pins speed to 100 MHz */ 
+  GPIOE->OSPEEDR = 0xffffc3cf;
+  /* Configure PEx pins Output type to push-pull */  
+  GPIOE->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PEx pins */ 
+  GPIOE->PUPDR   = 0x00000000;
+
+  /* Connect PFx pins to FSMC Alternate function */
+  GPIOF->AFR[0]  = 0x00cccccc;
+  GPIOF->AFR[1]  = 0xcccc0000;
+  /* Configure PFx pins in Alternate function mode */   
+  GPIOF->MODER   = 0xaa000aaa;
+  /* Configure PFx pins speed to 100 MHz */ 
+  GPIOF->OSPEEDR = 0xff000fff;
+  /* Configure PFx pins Output type to push-pull */  
+  GPIOF->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PFx pins */ 
+  GPIOF->PUPDR   = 0x00000000;
+
+  /* Connect PGx pins to FSMC Alternate function */
+  GPIOG->AFR[0]  = 0x00cccccc;
+  GPIOG->AFR[1]  = 0x000000c0;
+  /* Configure PGx pins in Alternate function mode */ 
+  GPIOG->MODER   = 0x00080aaa;
+  /* Configure PGx pins speed to 100 MHz */ 
+  GPIOG->OSPEEDR = 0x000c0fff;
+  /* Configure PGx pins Output type to push-pull */  
+  GPIOG->OTYPER  = 0x00000000;
+  /* No pull-up, pull-down for PGx pins */ 
+  GPIOG->PUPDR   = 0x00000000;
+  
+/*-- FSMC Configuration ------------------------------------------------------*/
+  /* Enable the FSMC interface clock */
+  RCC->AHB3ENR         = 0x00000001;
+
+  /* Configure and enable Bank1_SRAM2 */
+  FSMC_Bank1->BTCR[2]  = 0x00001015;
+  FSMC_Bank1->BTCR[3]  = 0x00010603;//0x00010400;
+  FSMC_Bank1E->BWTR[2] = 0x0fffffff;
+/*
+  Bank1_SRAM2 is configured as follow:
+
+  p.FSMC_AddressSetupTime = 3;//0;
+  p.FSMC_AddressHoldTime = 0;
+  p.FSMC_DataSetupTime = 6;//4;
+  p.FSMC_BusTurnAroundDuration = 1;
+  p.FSMC_CLKDivision = 0;
+  p.FSMC_DataLatency = 0;
+  p.FSMC_AccessMode = FSMC_AccessMode_A;
+
+  FSMC_NORSRAMInitStructure.FSMC_Bank = FSMC_Bank1_NORSRAM2;
+  FSMC_NORSRAMInitStructure.FSMC_DataAddressMux = FSMC_DataAddressMux_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryType = FSMC_MemoryType_PSRAM;
+  FSMC_NORSRAMInitStructure.FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_16b;
+  FSMC_NORSRAMInitStructure.FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;  
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStructure.FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStructure.FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStructure.FSMC_WaitSignal = FSMC_WaitSignal_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStructure.FSMC_ReadWriteTimingStruct = &p;
+  FSMC_NORSRAMInitStructure.FSMC_WriteTimingStruct = &p;
+*/
+  
+}
+#endif /* DATA_IN_ExtSRAM */
+
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */    
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/CMSIS/index.htm b/bsp/stm32f40x/Libraries/CMSIS/index.htm
new file mode 100644
index 0000000000..40e52b3737
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/CMSIS/index.htm
@@ -0,0 +1,115 @@
+
+
+
+CMSIS Release Notes
+
+
+
+
+
+
+
+
+
    CMSIS Release Notes
    
+
    Release Notes for CMSIS V2.00
    
+
    November 2010
    
+
+
    Information in this file, the accompany manuals, and software is
    
+                 Copyright © ARM Ltd.
    All rights reserved.
+
    
+
    
+
+
    
+
+
    Contents
    
+
+
+
+
+
+
+
\ No newline at end of file
diff --git a/bsp/stm32f40x/Libraries/SConscript b/bsp/stm32f40x/Libraries/SConscript
new file mode 100644
index 0000000000..c618a7b0fb
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/SConscript
@@ -0,0 +1,305 @@
+import rtconfig
+from building import *
+
+# get current directory
+cwd = GetCurrentDir()
+
+dsp_src = Split('''
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_f32.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q15.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q31.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_abs_q7.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_f32.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q15.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q31.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_add_q7.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_f32.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q15.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q31.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_dot_prod_q7.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_f32.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q15.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q31.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_mult_q7.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_f32.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q15.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q31.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_negate_q7.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_f32.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q15.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q31.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_offset_q7.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_f32.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q15.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q31.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_scale_q7.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q15.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q31.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_shift_q7.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_f32.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q15.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q31.c
+CMSIS/DSP_Lib/Source/BasicMathFunctions/arm_sub_q7.c
+CMSIS/DSP_Lib/Source/CommonTables/arm_common_tables.c
+CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_f32.c
+CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q15.c
+CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_conj_q31.c
+CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_f32.c
+CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q15.c
+CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_dot_prod_q31.c
+CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_f32.c
+CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q15.c
+CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_q31.c
+CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_f32.c
+CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q15.c
+CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mag_squared_q31.c
+CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_f32.c
+CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q15.c
+CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_cmplx_q31.c
+CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_f32.c
+CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q15.c
+CMSIS/DSP_Lib/Source/ComplexMathFunctions/arm_cmplx_mult_real_q31.c
+CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_f32.c
+CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q15.c
+CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_init_q31.c
+CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_f32.c
+CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q15.c
+CMSIS/DSP_Lib/Source/ControllerFunctions/arm_pid_reset_q31.c
+CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_f32.c
+CMSIS/DSP_Lib/Source/ControllerFunctions/arm_sin_cos_q31.c
+CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_f32.c
+CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q15.c
+CMSIS/DSP_Lib/Source/FastMathFunctions/arm_cos_q31.c
+CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_f32.c
+CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q15.c
+CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sin_q31.c
+CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q15.c
+CMSIS/DSP_Lib/Source/FastMathFunctions/arm_sqrt_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_init_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_32x64_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_fast_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_init_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df1_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_biquad_cascade_df2T_init_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_fast_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_fast_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_partial_q7.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_conv_q7.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_fast_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_correlate_q7.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_fast_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_init_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_decimate_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_fast_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_init_q7.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_init_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_interpolate_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_init_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_lattice_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_q7.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_init_q7.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_fir_sparse_q7.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_init_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_iir_lattice_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_init_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_f32.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_init_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_norm_q31.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q15.c
+CMSIS/DSP_Lib/Source/FilteringFunctions/arm_lms_q31.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_f32.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q15.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_add_q31.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_f32.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q15.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_init_q31.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_inverse_f32.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_f32.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q15.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_fast_q31.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q15.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_mult_q31.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_f32.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q15.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_scale_q31.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_f32.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q15.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_sub_q31.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_f32.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q15.c
+CMSIS/DSP_Lib/Source/MatrixFunctions/arm_mat_trans_q31.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_f32.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q15.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q31.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_max_q7.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_f32.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q15.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q31.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_mean_q7.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_f32.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q15.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q31.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_min_q7.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_f32.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q15.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q31.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_power_q7.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_f32.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q15.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_rms_q31.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_f32.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q15.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_std_q31.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_f32.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q15.c
+CMSIS/DSP_Lib/Source/StatisticsFunctions/arm_var_q31.c
+CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_f32.c
+CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q15.c
+CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q31.c
+CMSIS/DSP_Lib/Source/SupportFunctions/arm_copy_q7.c
+CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_f32.c
+CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q15.c
+CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q31.c
+CMSIS/DSP_Lib/Source/SupportFunctions/arm_fill_q7.c
+CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q15.c
+CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q31.c
+CMSIS/DSP_Lib/Source/SupportFunctions/arm_float_to_q7.c
+CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_float.c
+CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q31.c
+CMSIS/DSP_Lib/Source/SupportFunctions/arm_q15_to_q7.c
+CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_float.c
+CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q15.c
+CMSIS/DSP_Lib/Source/SupportFunctions/arm_q31_to_q7.c
+CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_float.c
+CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q15.c
+CMSIS/DSP_Lib/Source/SupportFunctions/arm_q7_to_q31.c
+CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_f32.c
+CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_f32.c
+CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q15.c
+CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_init_q31.c
+CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q15.c
+CMSIS/DSP_Lib/Source/TransformFunctions/arm_cfft_radix4_q31.c
+CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_f32.c
+CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_f32.c
+CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q15.c
+CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_init_q31.c
+CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q15.c
+CMSIS/DSP_Lib/Source/TransformFunctions/arm_dct4_q31.c
+CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_f32.c
+CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_f32.c
+CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q15.c
+CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_init_q31.c
+CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q15.c
+CMSIS/DSP_Lib/Source/TransformFunctions/arm_rfft_q31.c
+''')
+
+src = Split("""
+CMSIS/ST/STM32F4xx/Source/Templates/system_stm32f4xx.c
+STM32F4xx_StdPeriph_Driver/src/misc.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_des.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_tdes.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dac.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_sha1.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_i2c.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c
+STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c
+""")
+
+# starupt scripts for STM32F4xx
+startup_scripts = 'startup_stm32f4xx.s'
+
+# add for startup script
+if rtconfig.CROSS_TOOL == 'gcc':
+    src = src + ['CMSIS/ST/STM32F4xx/Source/Templates/gcc_ride7/' + startup_scripts]
+elif rtconfig.CROSS_TOOL == 'keil':
+    src = src + ['CMSIS/ST/STM32F4xx/Source/Templates/arm/' + startup_scripts]
+elif rtconfig.CROSS_TOOL == 'iar':
+    src = src + ['CMSIS/ST/STM32F4xx/Source/Templates/iar/' + startup_scripts]
+
+path = [cwd + '/STM32F4xx_StdPeriph_Driver/inc',
+    cwd + '/CMSIS/Include',
+    cwd + '/CMSIS/ST/STM32F4xx/Include']
+
+src = src + dsp_src
+
+CPPDEFINES = ['USE_STDPERIPH_DRIVER', 'ARM_MATH_CM4', 'ARM_MATH_MATRIX_CHECK', 'ARM_MATH_ROUNDING', 'ARM_MATH_BIG_ENDIAN', '__FPU_PRESENT=1']
+group = DefineGroup('STM32_StdPeriph', src, depend = [''], CPPPATH = path, CPPDEFINES = CPPDEFINES)
+
+Return('group')
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/Release_Notes.html b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/Release_Notes.html
new file mode 100644
index 0000000000..d7d0235be7
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/Release_Notes.html
@@ -0,0 +1,954 @@
+
+
+
+
+
+
+
+
+Release Notes for STM32F4xx Standard Peripherals Library Drivers
+
+
+
+
+
+
    
+
+
     
    
+
+
    
+
+
+ 
+  
+ 
+
    
+  
+   
+    
+   
+   
+    
+   
+  
    
+    
    Back to Release page
    
+    
    
+    
    Release Notes for STM32F4xx Standard
+    Peripherals Library Drivers (StdPeriph_Driver)
    
+    
    Copyright
+    2011 STMicroelectronics
    
+    
    
+    
    
+  
     
    
+  
+   
+    
+   
+  
    
+    
    Contents
    
+    
      
+     
    1. STM32F4xx Standard Peripherals Library Drivers
+         update History
      2. 
+     
    2. License
      3. 
+    
    
+    
    STM32F4xx
+    Standard Peripherals Library Drivers  update History
    V1.0.0RC1 / 25-August-2011
    Main
+Changes
    
+
    • Official version (V1.0.0) Release Candidate1 for STM32F4xx devices
    
+    
    License
    
+    
    The enclosed firmware and all the related documentation are
+    not covered by a License Agreement, if you need such License you can
+    contact your local STMicroelectronics office.
    
+    
    THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING
+    CUSTOMERS WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR
+    THEM TO SAVE TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE
+    FOR ANY DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY
+    CLAIMS ARISING FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY
+    CUSTOMERS OF THE CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH
+    THEIR PRODUCTS. 
    
+    
     
    
+    
    
+    
    
+    
    
+    
    For
+    complete documentation on STM32(CORTEX M3) 32-Bit
+    Microcontrollers visit www.st.com/STM32
    
+    
    
+  
    
+  
    
+
+
    
+
+
     
    
+
+
    
+
+
\ No newline at end of file
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h
new file mode 100644
index 0000000000..100058fe39
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/misc.h
@@ -0,0 +1,172 @@
+/**
+  ******************************************************************************
+  * @file    misc.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the miscellaneous
+  *          firmware library functions (add-on to CMSIS functions).
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __MISC_H
+#define __MISC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup MISC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  NVIC Init Structure definition  
+  */
+
+typedef struct
+{
+  uint8_t NVIC_IRQChannel;                    /*!< Specifies the IRQ channel to be enabled or disabled.
+                                                   This parameter can be an enumerator of @ref IRQn_Type 
+                                                   enumeration (For the complete STM32 Devices IRQ Channels
+                                                   list, please refer to stm32f4xx.h file) */
+
+  uint8_t NVIC_IRQChannelPreemptionPriority;  /*!< Specifies the pre-emption priority for the IRQ channel
+                                                   specified in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
+                                                   A lower priority value indicates a higher priority */
+
+  uint8_t NVIC_IRQChannelSubPriority;         /*!< Specifies the subpriority level for the IRQ channel specified
+                                                   in NVIC_IRQChannel. This parameter can be a value
+                                                   between 0 and 15 as described in the table @ref MISC_NVIC_Priority_Table
+                                                   A lower priority value indicates a higher priority */
+
+  FunctionalState NVIC_IRQChannelCmd;         /*!< Specifies whether the IRQ channel defined in NVIC_IRQChannel
+                                                   will be enabled or disabled. 
+                                                   This parameter can be set either to ENABLE or DISABLE */   
+} NVIC_InitTypeDef;
+ 
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup MISC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup MISC_Vector_Table_Base 
+  * @{
+  */
+
+#define NVIC_VectTab_RAM             ((uint32_t)0x20000000)
+#define NVIC_VectTab_FLASH           ((uint32_t)0x08000000)
+#define IS_NVIC_VECTTAB(VECTTAB) (((VECTTAB) == NVIC_VectTab_RAM) || \
+                                  ((VECTTAB) == NVIC_VectTab_FLASH))
+/**
+  * @}
+  */
+
+/** @defgroup MISC_System_Low_Power 
+  * @{
+  */
+
+#define NVIC_LP_SEVONPEND            ((uint8_t)0x10)
+#define NVIC_LP_SLEEPDEEP            ((uint8_t)0x04)
+#define NVIC_LP_SLEEPONEXIT          ((uint8_t)0x02)
+#define IS_NVIC_LP(LP) (((LP) == NVIC_LP_SEVONPEND) || \
+                        ((LP) == NVIC_LP_SLEEPDEEP) || \
+                        ((LP) == NVIC_LP_SLEEPONEXIT))
+/**
+  * @}
+  */
+
+/** @defgroup MISC_Preemption_Priority_Group 
+  * @{
+  */
+
+#define NVIC_PriorityGroup_0         ((uint32_t)0x700) /*!< 0 bits for pre-emption priority
+                                                            4 bits for subpriority */
+#define NVIC_PriorityGroup_1         ((uint32_t)0x600) /*!< 1 bits for pre-emption priority
+                                                            3 bits for subpriority */
+#define NVIC_PriorityGroup_2         ((uint32_t)0x500) /*!< 2 bits for pre-emption priority
+                                                            2 bits for subpriority */
+#define NVIC_PriorityGroup_3         ((uint32_t)0x400) /*!< 3 bits for pre-emption priority
+                                                            1 bits for subpriority */
+#define NVIC_PriorityGroup_4         ((uint32_t)0x300) /*!< 4 bits for pre-emption priority
+                                                            0 bits for subpriority */
+
+#define IS_NVIC_PRIORITY_GROUP(GROUP) (((GROUP) == NVIC_PriorityGroup_0) || \
+                                       ((GROUP) == NVIC_PriorityGroup_1) || \
+                                       ((GROUP) == NVIC_PriorityGroup_2) || \
+                                       ((GROUP) == NVIC_PriorityGroup_3) || \
+                                       ((GROUP) == NVIC_PriorityGroup_4))
+
+#define IS_NVIC_PREEMPTION_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_SUB_PRIORITY(PRIORITY)  ((PRIORITY) < 0x10)
+
+#define IS_NVIC_OFFSET(OFFSET)  ((OFFSET) < 0x000FFFFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup MISC_SysTick_clock_source 
+  * @{
+  */
+
+#define SysTick_CLKSource_HCLK_Div8    ((uint32_t)0xFFFFFFFB)
+#define SysTick_CLKSource_HCLK         ((uint32_t)0x00000004)
+#define IS_SYSTICK_CLK_SOURCE(SOURCE) (((SOURCE) == SysTick_CLKSource_HCLK) || \
+                                       ((SOURCE) == SysTick_CLKSource_HCLK_Div8))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup);
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct);
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset);
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState);
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __MISC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h
new file mode 100644
index 0000000000..6bff148d88
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_adc.h
@@ -0,0 +1,643 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_adc.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the ADC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_ADC_H
+#define __STM32F4xx_ADC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup ADC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief   ADC Init structure definition  
+  */ 
+typedef struct
+{
+  uint32_t ADC_Resolution;                /*!< Configures the ADC resolution dual mode. 
+                                               This parameter can be a value of @ref ADC_resolution */                                   
+  FunctionalState ADC_ScanConvMode;       /*!< Specifies whether the conversion 
+                                               is performed in Scan (multichannels) 
+                                               or Single (one channel) mode.
+                                               This parameter can be set to ENABLE or DISABLE */ 
+  FunctionalState ADC_ContinuousConvMode; /*!< Specifies whether the conversion 
+                                               is performed in Continuous or Single mode.
+                                               This parameter can be set to ENABLE or DISABLE. */
+  uint32_t ADC_ExternalTrigConvEdge;      /*!< Select the external trigger edge and
+                                               enable the trigger of a regular group. 
+                                               This parameter can be a value of 
+                                               @ref ADC_external_trigger_edge_for_regular_channels_conversion */
+  uint32_t ADC_ExternalTrigConv;          /*!< Select the external event used to trigger 
+                                               the start of conversion of a regular group.
+                                               This parameter can be a value of 
+                                               @ref ADC_extrenal_trigger_sources_for_regular_channels_conversion */
+  uint32_t ADC_DataAlign;                 /*!< Specifies whether the ADC data  alignment
+                                               is left or right. This parameter can be 
+                                               a value of @ref ADC_data_align */
+  uint8_t  ADC_NbrOfConversion;           /*!< Specifies the number of ADC conversions
+                                               that will be done using the sequencer for
+                                               regular channel group.
+                                               This parameter must range from 1 to 16. */
+}ADC_InitTypeDef;
+  
+/** 
+  * @brief   ADC Common Init structure definition  
+  */ 
+typedef struct 
+{
+  uint32_t ADC_Mode;                      /*!< Configures the ADC to operate in 
+                                               independent or multi mode. 
+                                               This parameter can be a value of @ref ADC_Common_mode */                                              
+  uint32_t ADC_Prescaler;                 /*!< Select the frequency of the clock 
+                                               to the ADC. The clock is common for all the ADCs.
+                                               This parameter can be a value of @ref ADC_Prescaler */
+  uint32_t ADC_DMAAccessMode;             /*!< Configures the Direct memory access 
+                                              mode for multi ADC mode.
+                                               This parameter can be a value of 
+                                               @ref ADC_Direct_memory_access_mode_for_multi_mode */
+  uint32_t ADC_TwoSamplingDelay;          /*!< Configures the Delay between 2 sampling phases.
+                                               This parameter can be a value of 
+                                               @ref ADC_delay_between_2_sampling_phases */
+  
+}ADC_CommonInitTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup ADC_Exported_Constants
+  * @{
+  */ 
+#define IS_ADC_ALL_PERIPH(PERIPH) (((PERIPH) == ADC1) || \
+                                   ((PERIPH) == ADC2) || \
+                                   ((PERIPH) == ADC3))  
+
+/** @defgroup ADC_Common_mode 
+  * @{
+  */ 
+#define ADC_Mode_Independent                       ((uint32_t)0x00000000)       
+#define ADC_DualMode_RegSimult_InjecSimult         ((uint32_t)0x00000001)
+#define ADC_DualMode_RegSimult_AlterTrig           ((uint32_t)0x00000002)
+#define ADC_DualMode_InjecSimult                   ((uint32_t)0x00000005)
+#define ADC_DualMode_RegSimult                     ((uint32_t)0x00000006)
+#define ADC_DualMode_Interl                        ((uint32_t)0x00000007)
+#define ADC_DualMode_AlterTrig                     ((uint32_t)0x00000009)
+#define ADC_TripleMode_RegSimult_InjecSimult       ((uint32_t)0x00000011)
+#define ADC_TripleMode_RegSimult_AlterTrig         ((uint32_t)0x00000012)
+#define ADC_TripleMode_InjecSimult                 ((uint32_t)0x00000015)
+#define ADC_TripleMode_RegSimult                   ((uint32_t)0x00000016)
+#define ADC_TripleMode_Interl                      ((uint32_t)0x00000017)
+#define ADC_TripleMode_AlterTrig                   ((uint32_t)0x00000019)
+#define IS_ADC_MODE(MODE) (((MODE) == ADC_Mode_Independent) || \
+                           ((MODE) == ADC_DualMode_RegSimult_InjecSimult) || \
+                           ((MODE) == ADC_DualMode_RegSimult_AlterTrig) || \
+                           ((MODE) == ADC_DualMode_InjecSimult) || \
+                           ((MODE) == ADC_DualMode_RegSimult) || \
+                           ((MODE) == ADC_DualMode_Interl) || \
+                           ((MODE) == ADC_DualMode_AlterTrig) || \
+                           ((MODE) == ADC_TripleMode_RegSimult_InjecSimult) || \
+                           ((MODE) == ADC_TripleMode_RegSimult_AlterTrig) || \
+                           ((MODE) == ADC_TripleMode_InjecSimult) || \
+                           ((MODE) == ADC_TripleMode_RegSimult) || \
+                           ((MODE) == ADC_TripleMode_Interl) || \
+                           ((MODE) == ADC_TripleMode_AlterTrig))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_Prescaler 
+  * @{
+  */ 
+#define ADC_Prescaler_Div2                         ((uint32_t)0x00000000)
+#define ADC_Prescaler_Div4                         ((uint32_t)0x00010000)
+#define ADC_Prescaler_Div6                         ((uint32_t)0x00020000)
+#define ADC_Prescaler_Div8                         ((uint32_t)0x00030000)
+#define IS_ADC_PRESCALER(PRESCALER) (((PRESCALER) == ADC_Prescaler_Div2) || \
+                                     ((PRESCALER) == ADC_Prescaler_Div4) || \
+                                     ((PRESCALER) == ADC_Prescaler_Div6) || \
+                                     ((PRESCALER) == ADC_Prescaler_Div8))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_Direct_memory_access_mode_for_multi_mode 
+  * @{
+  */ 
+#define ADC_DMAAccessMode_Disabled      ((uint32_t)0x00000000)     /* DMA mode disabled */
+#define ADC_DMAAccessMode_1             ((uint32_t)0x00004000)     /* DMA mode 1 enabled (2 / 3 half-words one by one - 1 then 2 then 3)*/
+#define ADC_DMAAccessMode_2             ((uint32_t)0x00008000)     /* DMA mode 2 enabled (2 / 3 half-words by pairs - 2&1 then 1&3 then 3&2)*/
+#define ADC_DMAAccessMode_3             ((uint32_t)0x0000C000)     /* DMA mode 3 enabled (2 / 3 bytes by pairs - 2&1 then 1&3 then 3&2) */
+#define IS_ADC_DMA_ACCESS_MODE(MODE) (((MODE) == ADC_DMAAccessMode_Disabled) || \
+                                      ((MODE) == ADC_DMAAccessMode_1) || \
+                                      ((MODE) == ADC_DMAAccessMode_2) || \
+                                      ((MODE) == ADC_DMAAccessMode_3))
+                                     
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_delay_between_2_sampling_phases 
+  * @{
+  */ 
+#define ADC_TwoSamplingDelay_5Cycles               ((uint32_t)0x00000000)
+#define ADC_TwoSamplingDelay_6Cycles               ((uint32_t)0x00000100)
+#define ADC_TwoSamplingDelay_7Cycles               ((uint32_t)0x00000200)
+#define ADC_TwoSamplingDelay_8Cycles               ((uint32_t)0x00000300)
+#define ADC_TwoSamplingDelay_9Cycles               ((uint32_t)0x00000400)
+#define ADC_TwoSamplingDelay_10Cycles              ((uint32_t)0x00000500)
+#define ADC_TwoSamplingDelay_11Cycles              ((uint32_t)0x00000600)
+#define ADC_TwoSamplingDelay_12Cycles              ((uint32_t)0x00000700)
+#define ADC_TwoSamplingDelay_13Cycles              ((uint32_t)0x00000800)
+#define ADC_TwoSamplingDelay_14Cycles              ((uint32_t)0x00000900)
+#define ADC_TwoSamplingDelay_15Cycles              ((uint32_t)0x00000A00)
+#define ADC_TwoSamplingDelay_16Cycles              ((uint32_t)0x00000B00)
+#define ADC_TwoSamplingDelay_17Cycles              ((uint32_t)0x00000C00)
+#define ADC_TwoSamplingDelay_18Cycles              ((uint32_t)0x00000D00)
+#define ADC_TwoSamplingDelay_19Cycles              ((uint32_t)0x00000E00)
+#define ADC_TwoSamplingDelay_20Cycles              ((uint32_t)0x00000F00)
+#define IS_ADC_SAMPLING_DELAY(DELAY) (((DELAY) == ADC_TwoSamplingDelay_5Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_6Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_7Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_8Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_9Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_10Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_11Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_12Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_13Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_14Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_15Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_16Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_17Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_18Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_19Cycles) || \
+                                      ((DELAY) == ADC_TwoSamplingDelay_20Cycles))
+                                     
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_resolution 
+  * @{
+  */ 
+#define ADC_Resolution_12b                         ((uint32_t)0x00000000)
+#define ADC_Resolution_10b                         ((uint32_t)0x01000000)
+#define ADC_Resolution_8b                          ((uint32_t)0x02000000)
+#define ADC_Resolution_6b                          ((uint32_t)0x03000000)
+#define IS_ADC_RESOLUTION(RESOLUTION) (((RESOLUTION) == ADC_Resolution_12b) || \
+                                       ((RESOLUTION) == ADC_Resolution_10b) || \
+                                       ((RESOLUTION) == ADC_Resolution_8b) || \
+                                       ((RESOLUTION) == ADC_Resolution_6b))
+                                      
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_external_trigger_edge_for_regular_channels_conversion 
+  * @{
+  */ 
+#define ADC_ExternalTrigConvEdge_None          ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConvEdge_Rising        ((uint32_t)0x10000000)
+#define ADC_ExternalTrigConvEdge_Falling       ((uint32_t)0x20000000)
+#define ADC_ExternalTrigConvEdge_RisingFalling ((uint32_t)0x30000000)
+#define IS_ADC_EXT_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigConvEdge_None) || \
+                             ((EDGE) == ADC_ExternalTrigConvEdge_Rising) || \
+                             ((EDGE) == ADC_ExternalTrigConvEdge_Falling) || \
+                             ((EDGE) == ADC_ExternalTrigConvEdge_RisingFalling))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_extrenal_trigger_sources_for_regular_channels_conversion 
+  * @{
+  */ 
+#define ADC_ExternalTrigConv_T1_CC1                ((uint32_t)0x00000000)
+#define ADC_ExternalTrigConv_T1_CC2                ((uint32_t)0x01000000)
+#define ADC_ExternalTrigConv_T1_CC3                ((uint32_t)0x02000000)
+#define ADC_ExternalTrigConv_T2_CC2                ((uint32_t)0x03000000)
+#define ADC_ExternalTrigConv_T2_CC3                ((uint32_t)0x04000000)
+#define ADC_ExternalTrigConv_T2_CC4                ((uint32_t)0x05000000)
+#define ADC_ExternalTrigConv_T2_TRGO               ((uint32_t)0x06000000)
+#define ADC_ExternalTrigConv_T3_CC1                ((uint32_t)0x07000000)
+#define ADC_ExternalTrigConv_T3_TRGO               ((uint32_t)0x08000000)
+#define ADC_ExternalTrigConv_T4_CC4                ((uint32_t)0x09000000)
+#define ADC_ExternalTrigConv_T5_CC1                ((uint32_t)0x0A000000)
+#define ADC_ExternalTrigConv_T5_CC2                ((uint32_t)0x0B000000)
+#define ADC_ExternalTrigConv_T5_CC3                ((uint32_t)0x0C000000)
+#define ADC_ExternalTrigConv_T8_CC1                ((uint32_t)0x0D000000)
+#define ADC_ExternalTrigConv_T8_TRGO               ((uint32_t)0x0E000000)
+#define ADC_ExternalTrigConv_Ext_IT11              ((uint32_t)0x0F000000)
+#define IS_ADC_EXT_TRIG(REGTRIG) (((REGTRIG) == ADC_ExternalTrigConv_T1_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC2) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T1_CC3) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC2) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC3) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_CC4) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T2_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T3_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T4_CC4) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC2) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T5_CC3) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_CC1) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_T8_TRGO) || \
+                                  ((REGTRIG) == ADC_ExternalTrigConv_Ext_IT11))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_data_align 
+  * @{
+  */ 
+#define ADC_DataAlign_Right                        ((uint32_t)0x00000000)
+#define ADC_DataAlign_Left                         ((uint32_t)0x00000800)
+#define IS_ADC_DATA_ALIGN(ALIGN) (((ALIGN) == ADC_DataAlign_Right) || \
+                                  ((ALIGN) == ADC_DataAlign_Left))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_channels 
+  * @{
+  */ 
+#define ADC_Channel_0                               ((uint8_t)0x00)
+#define ADC_Channel_1                               ((uint8_t)0x01)
+#define ADC_Channel_2                               ((uint8_t)0x02)
+#define ADC_Channel_3                               ((uint8_t)0x03)
+#define ADC_Channel_4                               ((uint8_t)0x04)
+#define ADC_Channel_5                               ((uint8_t)0x05)
+#define ADC_Channel_6                               ((uint8_t)0x06)
+#define ADC_Channel_7                               ((uint8_t)0x07)
+#define ADC_Channel_8                               ((uint8_t)0x08)
+#define ADC_Channel_9                               ((uint8_t)0x09)
+#define ADC_Channel_10                              ((uint8_t)0x0A)
+#define ADC_Channel_11                              ((uint8_t)0x0B)
+#define ADC_Channel_12                              ((uint8_t)0x0C)
+#define ADC_Channel_13                              ((uint8_t)0x0D)
+#define ADC_Channel_14                              ((uint8_t)0x0E)
+#define ADC_Channel_15                              ((uint8_t)0x0F)
+#define ADC_Channel_16                              ((uint8_t)0x10)
+#define ADC_Channel_17                              ((uint8_t)0x11)
+#define ADC_Channel_18                              ((uint8_t)0x12)
+
+#define ADC_Channel_TempSensor                      ((uint8_t)ADC_Channel_16)
+#define ADC_Channel_Vrefint                         ((uint8_t)ADC_Channel_17)
+#define ADC_Channel_Vbat                            ((uint8_t)ADC_Channel_18)
+
+#define IS_ADC_CHANNEL(CHANNEL) (((CHANNEL) == ADC_Channel_0) || \
+                                 ((CHANNEL) == ADC_Channel_1) || \
+                                 ((CHANNEL) == ADC_Channel_2) || \
+                                 ((CHANNEL) == ADC_Channel_3) || \
+                                 ((CHANNEL) == ADC_Channel_4) || \
+                                 ((CHANNEL) == ADC_Channel_5) || \
+                                 ((CHANNEL) == ADC_Channel_6) || \
+                                 ((CHANNEL) == ADC_Channel_7) || \
+                                 ((CHANNEL) == ADC_Channel_8) || \
+                                 ((CHANNEL) == ADC_Channel_9) || \
+                                 ((CHANNEL) == ADC_Channel_10) || \
+                                 ((CHANNEL) == ADC_Channel_11) || \
+                                 ((CHANNEL) == ADC_Channel_12) || \
+                                 ((CHANNEL) == ADC_Channel_13) || \
+                                 ((CHANNEL) == ADC_Channel_14) || \
+                                 ((CHANNEL) == ADC_Channel_15) || \
+                                 ((CHANNEL) == ADC_Channel_16) || \
+                                 ((CHANNEL) == ADC_Channel_17) || \
+                                 ((CHANNEL) == ADC_Channel_18))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_sampling_times 
+  * @{
+  */ 
+#define ADC_SampleTime_3Cycles                    ((uint8_t)0x00)
+#define ADC_SampleTime_15Cycles                   ((uint8_t)0x01)
+#define ADC_SampleTime_28Cycles                   ((uint8_t)0x02)
+#define ADC_SampleTime_56Cycles                   ((uint8_t)0x03)
+#define ADC_SampleTime_84Cycles                   ((uint8_t)0x04)
+#define ADC_SampleTime_112Cycles                  ((uint8_t)0x05)
+#define ADC_SampleTime_144Cycles                  ((uint8_t)0x06)
+#define ADC_SampleTime_480Cycles                  ((uint8_t)0x07)
+#define IS_ADC_SAMPLE_TIME(TIME) (((TIME) == ADC_SampleTime_3Cycles) || \
+                                  ((TIME) == ADC_SampleTime_15Cycles) || \
+                                  ((TIME) == ADC_SampleTime_28Cycles) || \
+                                  ((TIME) == ADC_SampleTime_56Cycles) || \
+                                  ((TIME) == ADC_SampleTime_84Cycles) || \
+                                  ((TIME) == ADC_SampleTime_112Cycles) || \
+                                  ((TIME) == ADC_SampleTime_144Cycles) || \
+                                  ((TIME) == ADC_SampleTime_480Cycles))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_external_trigger_edge_for_injected_channels_conversion 
+  * @{
+  */ 
+#define ADC_ExternalTrigInjecConvEdge_None          ((uint32_t)0x00000000)
+#define ADC_ExternalTrigInjecConvEdge_Rising        ((uint32_t)0x00100000)
+#define ADC_ExternalTrigInjecConvEdge_Falling       ((uint32_t)0x00200000)
+#define ADC_ExternalTrigInjecConvEdge_RisingFalling ((uint32_t)0x00300000)
+#define IS_ADC_EXT_INJEC_TRIG_EDGE(EDGE) (((EDGE) == ADC_ExternalTrigInjecConvEdge_None) || \
+                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_Rising) || \
+                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_Falling) || \
+                                          ((EDGE) == ADC_ExternalTrigInjecConvEdge_RisingFalling))
+                                            
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_extrenal_trigger_sources_for_injected_channels_conversion 
+  * @{
+  */ 
+#define ADC_ExternalTrigInjecConv_T1_CC4            ((uint32_t)0x00000000)
+#define ADC_ExternalTrigInjecConv_T1_TRGO           ((uint32_t)0x00010000)
+#define ADC_ExternalTrigInjecConv_T2_CC1            ((uint32_t)0x00020000)
+#define ADC_ExternalTrigInjecConv_T2_TRGO           ((uint32_t)0x00030000)
+#define ADC_ExternalTrigInjecConv_T3_CC2            ((uint32_t)0x00040000)
+#define ADC_ExternalTrigInjecConv_T3_CC4            ((uint32_t)0x00050000)
+#define ADC_ExternalTrigInjecConv_T4_CC1            ((uint32_t)0x00060000)
+#define ADC_ExternalTrigInjecConv_T4_CC2            ((uint32_t)0x00070000)
+#define ADC_ExternalTrigInjecConv_T4_CC3            ((uint32_t)0x00080000)
+#define ADC_ExternalTrigInjecConv_T4_TRGO           ((uint32_t)0x00090000)
+#define ADC_ExternalTrigInjecConv_T5_CC4            ((uint32_t)0x000A0000)
+#define ADC_ExternalTrigInjecConv_T5_TRGO           ((uint32_t)0x000B0000)
+#define ADC_ExternalTrigInjecConv_T8_CC2            ((uint32_t)0x000C0000)
+#define ADC_ExternalTrigInjecConv_T8_CC3            ((uint32_t)0x000D0000)
+#define ADC_ExternalTrigInjecConv_T8_CC4            ((uint32_t)0x000E0000)
+#define ADC_ExternalTrigInjecConv_Ext_IT15          ((uint32_t)0x000F0000)
+#define IS_ADC_EXT_INJEC_TRIG(INJTRIG) (((INJTRIG) == ADC_ExternalTrigInjecConv_T1_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T1_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_CC1) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T2_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC2) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T3_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC1) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC2) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_CC3) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T4_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T5_TRGO) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC2) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC3) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_T8_CC4) || \
+                                        ((INJTRIG) == ADC_ExternalTrigInjecConv_Ext_IT15))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_injected_channel_selection 
+  * @{
+  */ 
+#define ADC_InjectedChannel_1                       ((uint8_t)0x14)
+#define ADC_InjectedChannel_2                       ((uint8_t)0x18)
+#define ADC_InjectedChannel_3                       ((uint8_t)0x1C)
+#define ADC_InjectedChannel_4                       ((uint8_t)0x20)
+#define IS_ADC_INJECTED_CHANNEL(CHANNEL) (((CHANNEL) == ADC_InjectedChannel_1) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_2) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_3) || \
+                                          ((CHANNEL) == ADC_InjectedChannel_4))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_analog_watchdog_selection 
+  * @{
+  */ 
+#define ADC_AnalogWatchdog_SingleRegEnable         ((uint32_t)0x00800200)
+#define ADC_AnalogWatchdog_SingleInjecEnable       ((uint32_t)0x00400200)
+#define ADC_AnalogWatchdog_SingleRegOrInjecEnable  ((uint32_t)0x00C00200)
+#define ADC_AnalogWatchdog_AllRegEnable            ((uint32_t)0x00800000)
+#define ADC_AnalogWatchdog_AllInjecEnable          ((uint32_t)0x00400000)
+#define ADC_AnalogWatchdog_AllRegAllInjecEnable    ((uint32_t)0x00C00000)
+#define ADC_AnalogWatchdog_None                    ((uint32_t)0x00000000)
+#define IS_ADC_ANALOG_WATCHDOG(WATCHDOG) (((WATCHDOG) == ADC_AnalogWatchdog_SingleRegEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_SingleRegOrInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_AllRegAllInjecEnable) || \
+                                          ((WATCHDOG) == ADC_AnalogWatchdog_None))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_interrupts_definition 
+  * @{
+  */ 
+#define ADC_IT_EOC                                 ((uint16_t)0x0205)  
+#define ADC_IT_AWD                                 ((uint16_t)0x0106)  
+#define ADC_IT_JEOC                                ((uint16_t)0x0407)  
+#define ADC_IT_OVR                                 ((uint16_t)0x201A)  
+#define IS_ADC_IT(IT) (((IT) == ADC_IT_EOC) || ((IT) == ADC_IT_AWD) || \
+                       ((IT) == ADC_IT_JEOC)|| ((IT) == ADC_IT_OVR)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_flags_definition 
+  * @{
+  */ 
+#define ADC_FLAG_AWD                               ((uint8_t)0x01)
+#define ADC_FLAG_EOC                               ((uint8_t)0x02)
+#define ADC_FLAG_JEOC                              ((uint8_t)0x04)
+#define ADC_FLAG_JSTRT                             ((uint8_t)0x08)
+#define ADC_FLAG_STRT                              ((uint8_t)0x10)
+#define ADC_FLAG_OVR                               ((uint8_t)0x20)   
+  
+#define IS_ADC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint8_t)0xC0) == 0x00) && ((FLAG) != 0x00))   
+#define IS_ADC_GET_FLAG(FLAG) (((FLAG) == ADC_FLAG_AWD) || \
+                               ((FLAG) == ADC_FLAG_EOC) || \
+                               ((FLAG) == ADC_FLAG_JEOC) || \
+                               ((FLAG)== ADC_FLAG_JSTRT) || \
+                               ((FLAG) == ADC_FLAG_STRT) || \
+                               ((FLAG)== ADC_FLAG_OVR))     
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_thresholds 
+  * @{
+  */ 
+#define IS_ADC_THRESHOLD(THRESHOLD) ((THRESHOLD) <= 0xFFF)
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_injected_offset 
+  * @{
+  */ 
+#define IS_ADC_OFFSET(OFFSET) ((OFFSET) <= 0xFFF)
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_injected_length 
+  * @{
+  */ 
+#define IS_ADC_INJECTED_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x4))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_injected_rank 
+  * @{
+  */ 
+#define IS_ADC_INJECTED_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x4))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_regular_length 
+  * @{
+  */ 
+#define IS_ADC_REGULAR_LENGTH(LENGTH) (((LENGTH) >= 0x1) && ((LENGTH) <= 0x10))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_regular_rank 
+  * @{
+  */ 
+#define IS_ADC_REGULAR_RANK(RANK) (((RANK) >= 0x1) && ((RANK) <= 0x10))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup ADC_regular_discontinuous_mode_number 
+  * @{
+  */ 
+#define IS_ADC_REGULAR_DISC_NUMBER(NUMBER) (((NUMBER) >= 0x1) && ((NUMBER) <= 0x8))
+/**
+  * @}
+  */ 
+
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/  
+
+/*  Function used to set the ADC configuration to the default reset state *****/  
+void ADC_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct);
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct);
+void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct);
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+
+/* Analog Watchdog configuration functions ************************************/
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog);
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,uint16_t LowThreshold);
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel);
+
+/* Temperature Sensor, Vrefint and VBAT management functions ******************/
+void ADC_TempSensorVrefintCmd(FunctionalState NewState);
+void ADC_VBATCmd(FunctionalState NewState);
+
+/* Regular Channels Configuration functions ***********************************/
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx);
+void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number);
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx);
+uint32_t ADC_GetMultiModeConversionValue(void);
+
+/* Regular Channels DMA Configuration functions *******************************/
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState);
+
+/* Injected channels Configuration functions **********************************/
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime);
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length);
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset);
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv);
+void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge);
+void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx);
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx);
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState);
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel);
+
+/* Interrupts and flags management functions **********************************/
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState);
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG);
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_ADC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h
new file mode 100644
index 0000000000..b1774f5629
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_can.h
@@ -0,0 +1,638 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_can.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the CAN firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_CAN_H
+#define __STM32F4xx_CAN_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CAN
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+#define IS_CAN_ALL_PERIPH(PERIPH) (((PERIPH) == CAN1) || \
+                                   ((PERIPH) == CAN2))
+
+/** 
+  * @brief  CAN init structure definition
+  */
+typedef struct
+{
+  uint16_t CAN_Prescaler;   /*!< Specifies the length of a time quantum. 
+                                 It ranges from 1 to 1024. */
+  
+  uint8_t CAN_Mode;         /*!< Specifies the CAN operating mode.
+                                 This parameter can be a value of @ref CAN_operating_mode */
+
+  uint8_t CAN_SJW;          /*!< Specifies the maximum number of time quanta 
+                                 the CAN hardware is allowed to lengthen or 
+                                 shorten a bit to perform resynchronization.
+                                 This parameter can be a value of @ref CAN_synchronisation_jump_width */
+
+  uint8_t CAN_BS1;          /*!< Specifies the number of time quanta in Bit 
+                                 Segment 1. This parameter can be a value of 
+                                 @ref CAN_time_quantum_in_bit_segment_1 */
+
+  uint8_t CAN_BS2;          /*!< Specifies the number of time quanta in Bit Segment 2.
+                                 This parameter can be a value of @ref CAN_time_quantum_in_bit_segment_2 */
+  
+  FunctionalState CAN_TTCM; /*!< Enable or disable the time triggered communication mode.
+                                This parameter can be set either to ENABLE or DISABLE. */
+  
+  FunctionalState CAN_ABOM;  /*!< Enable or disable the automatic bus-off management.
+                                  This parameter can be set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_AWUM;  /*!< Enable or disable the automatic wake-up mode. 
+                                  This parameter can be set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_NART;  /*!< Enable or disable the non-automatic retransmission mode.
+                                  This parameter can be set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_RFLM;  /*!< Enable or disable the Receive FIFO Locked mode.
+                                  This parameter can be set either to ENABLE or DISABLE. */
+
+  FunctionalState CAN_TXFP;  /*!< Enable or disable the transmit FIFO priority.
+                                  This parameter can be set either to ENABLE or DISABLE. */
+} CAN_InitTypeDef;
+
+/** 
+  * @brief  CAN filter init structure definition
+  */
+typedef struct
+{
+  uint16_t CAN_FilterIdHigh;         /*!< Specifies the filter identification number (MSBs for a 32-bit
+                                              configuration, first one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterIdLow;          /*!< Specifies the filter identification number (LSBs for a 32-bit
+                                              configuration, second one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterMaskIdHigh;     /*!< Specifies the filter mask number or identification number,
+                                              according to the mode (MSBs for a 32-bit configuration,
+                                              first one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterMaskIdLow;      /*!< Specifies the filter mask number or identification number,
+                                              according to the mode (LSBs for a 32-bit configuration,
+                                              second one for a 16-bit configuration).
+                                              This parameter can be a value between 0x0000 and 0xFFFF */
+
+  uint16_t CAN_FilterFIFOAssignment; /*!< Specifies the FIFO (0 or 1) which will be assigned to the filter.
+                                              This parameter can be a value of @ref CAN_filter_FIFO */
+  
+  uint8_t CAN_FilterNumber;          /*!< Specifies the filter which will be initialized. It ranges from 0 to 13. */
+
+  uint8_t CAN_FilterMode;            /*!< Specifies the filter mode to be initialized.
+                                              This parameter can be a value of @ref CAN_filter_mode */
+
+  uint8_t CAN_FilterScale;           /*!< Specifies the filter scale.
+                                              This parameter can be a value of @ref CAN_filter_scale */
+
+  FunctionalState CAN_FilterActivation; /*!< Enable or disable the filter.
+                                              This parameter can be set either to ENABLE or DISABLE. */
+} CAN_FilterInitTypeDef;
+
+/** 
+  * @brief  CAN Tx message structure definition  
+  */
+typedef struct
+{
+  uint32_t StdId;  /*!< Specifies the standard identifier.
+                        This parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t ExtId;  /*!< Specifies the extended identifier.
+                        This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
+                        will be transmitted. This parameter can be a value 
+                        of @ref CAN_identifier_type */
+
+  uint8_t RTR;     /*!< Specifies the type of frame for the message that will 
+                        be transmitted. This parameter can be a value of 
+                        @ref CAN_remote_transmission_request */
+
+  uint8_t DLC;     /*!< Specifies the length of the frame that will be 
+                        transmitted. This parameter can be a value between 
+                        0 to 8 */
+
+  uint8_t Data[8]; /*!< Contains the data to be transmitted. It ranges from 0 
+                        to 0xFF. */
+} CanTxMsg;
+
+/** 
+  * @brief  CAN Rx message structure definition  
+  */
+typedef struct
+{
+  uint32_t StdId;  /*!< Specifies the standard identifier.
+                        This parameter can be a value between 0 to 0x7FF. */
+
+  uint32_t ExtId;  /*!< Specifies the extended identifier.
+                        This parameter can be a value between 0 to 0x1FFFFFFF. */
+
+  uint8_t IDE;     /*!< Specifies the type of identifier for the message that 
+                        will be received. This parameter can be a value of 
+                        @ref CAN_identifier_type */
+
+  uint8_t RTR;     /*!< Specifies the type of frame for the received message.
+                        This parameter can be a value of 
+                        @ref CAN_remote_transmission_request */
+
+  uint8_t DLC;     /*!< Specifies the length of the frame that will be received.
+                        This parameter can be a value between 0 to 8 */
+
+  uint8_t Data[8]; /*!< Contains the data to be received. It ranges from 0 to 
+                        0xFF. */
+
+  uint8_t FMI;     /*!< Specifies the index of the filter the message stored in 
+                        the mailbox passes through. This parameter can be a 
+                        value between 0 to 0xFF */
+} CanRxMsg;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CAN_Exported_Constants
+  * @{
+  */
+
+/** @defgroup CAN_InitStatus 
+  * @{
+  */
+
+#define CAN_InitStatus_Failed              ((uint8_t)0x00) /*!< CAN initialization failed */
+#define CAN_InitStatus_Success             ((uint8_t)0x01) /*!< CAN initialization OK */
+
+
+/* Legacy defines */
+#define CANINITFAILED    CAN_InitStatus_Failed
+#define CANINITOK        CAN_InitStatus_Success
+/**
+  * @}
+  */
+
+/** @defgroup CAN_operating_mode 
+  * @{
+  */
+
+#define CAN_Mode_Normal             ((uint8_t)0x00)  /*!< normal mode */
+#define CAN_Mode_LoopBack           ((uint8_t)0x01)  /*!< loopback mode */
+#define CAN_Mode_Silent             ((uint8_t)0x02)  /*!< silent mode */
+#define CAN_Mode_Silent_LoopBack    ((uint8_t)0x03)  /*!< loopback combined with silent mode */
+
+#define IS_CAN_MODE(MODE) (((MODE) == CAN_Mode_Normal) || \
+                           ((MODE) == CAN_Mode_LoopBack)|| \
+                           ((MODE) == CAN_Mode_Silent) || \
+                           ((MODE) == CAN_Mode_Silent_LoopBack))
+/**
+  * @}
+  */
+
+
+ /**
+  * @defgroup CAN_operating_mode 
+  * @{
+  */  
+#define CAN_OperatingMode_Initialization  ((uint8_t)0x00) /*!< Initialization mode */
+#define CAN_OperatingMode_Normal          ((uint8_t)0x01) /*!< Normal mode */
+#define CAN_OperatingMode_Sleep           ((uint8_t)0x02) /*!< sleep mode */
+
+
+#define IS_CAN_OPERATING_MODE(MODE) (((MODE) == CAN_OperatingMode_Initialization) ||\
+                                    ((MODE) == CAN_OperatingMode_Normal)|| \
+																		((MODE) == CAN_OperatingMode_Sleep))
+/**
+  * @}
+  */
+  
+/**
+  * @defgroup CAN_operating_mode_status
+  * @{
+  */  
+
+#define CAN_ModeStatus_Failed    ((uint8_t)0x00)                /*!< CAN entering the specific mode failed */
+#define CAN_ModeStatus_Success   ((uint8_t)!CAN_ModeStatus_Failed)   /*!< CAN entering the specific mode Succeed */
+/**
+  * @}
+  */
+
+/** @defgroup CAN_synchronisation_jump_width 
+  * @{
+  */
+#define CAN_SJW_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_SJW_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_SJW_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_SJW_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+
+#define IS_CAN_SJW(SJW) (((SJW) == CAN_SJW_1tq) || ((SJW) == CAN_SJW_2tq)|| \
+                         ((SJW) == CAN_SJW_3tq) || ((SJW) == CAN_SJW_4tq))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_1 
+  * @{
+  */
+#define CAN_BS1_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_BS1_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_BS1_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_BS1_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_BS1_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_BS1_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_BS1_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_BS1_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
+#define CAN_BS1_9tq                 ((uint8_t)0x08)  /*!< 9 time quantum */
+#define CAN_BS1_10tq                ((uint8_t)0x09)  /*!< 10 time quantum */
+#define CAN_BS1_11tq                ((uint8_t)0x0A)  /*!< 11 time quantum */
+#define CAN_BS1_12tq                ((uint8_t)0x0B)  /*!< 12 time quantum */
+#define CAN_BS1_13tq                ((uint8_t)0x0C)  /*!< 13 time quantum */
+#define CAN_BS1_14tq                ((uint8_t)0x0D)  /*!< 14 time quantum */
+#define CAN_BS1_15tq                ((uint8_t)0x0E)  /*!< 15 time quantum */
+#define CAN_BS1_16tq                ((uint8_t)0x0F)  /*!< 16 time quantum */
+
+#define IS_CAN_BS1(BS1) ((BS1) <= CAN_BS1_16tq)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_time_quantum_in_bit_segment_2 
+  * @{
+  */
+#define CAN_BS2_1tq                 ((uint8_t)0x00)  /*!< 1 time quantum */
+#define CAN_BS2_2tq                 ((uint8_t)0x01)  /*!< 2 time quantum */
+#define CAN_BS2_3tq                 ((uint8_t)0x02)  /*!< 3 time quantum */
+#define CAN_BS2_4tq                 ((uint8_t)0x03)  /*!< 4 time quantum */
+#define CAN_BS2_5tq                 ((uint8_t)0x04)  /*!< 5 time quantum */
+#define CAN_BS2_6tq                 ((uint8_t)0x05)  /*!< 6 time quantum */
+#define CAN_BS2_7tq                 ((uint8_t)0x06)  /*!< 7 time quantum */
+#define CAN_BS2_8tq                 ((uint8_t)0x07)  /*!< 8 time quantum */
+
+#define IS_CAN_BS2(BS2) ((BS2) <= CAN_BS2_8tq)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_clock_prescaler 
+  * @{
+  */
+#define IS_CAN_PRESCALER(PRESCALER) (((PRESCALER) >= 1) && ((PRESCALER) <= 1024))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_number 
+  * @{
+  */
+#define IS_CAN_FILTER_NUMBER(NUMBER) ((NUMBER) <= 27)
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_mode 
+  * @{
+  */
+#define CAN_FilterMode_IdMask       ((uint8_t)0x00)  /*!< identifier/mask mode */
+#define CAN_FilterMode_IdList       ((uint8_t)0x01)  /*!< identifier list mode */
+
+#define IS_CAN_FILTER_MODE(MODE) (((MODE) == CAN_FilterMode_IdMask) || \
+                                  ((MODE) == CAN_FilterMode_IdList))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_scale 
+  * @{
+  */
+#define CAN_FilterScale_16bit       ((uint8_t)0x00) /*!< Two 16-bit filters */
+#define CAN_FilterScale_32bit       ((uint8_t)0x01) /*!< One 32-bit filter */
+
+#define IS_CAN_FILTER_SCALE(SCALE) (((SCALE) == CAN_FilterScale_16bit) || \
+                                    ((SCALE) == CAN_FilterScale_32bit))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_filter_FIFO
+  * @{
+  */
+#define CAN_Filter_FIFO0             ((uint8_t)0x00)  /*!< Filter FIFO 0 assignment for filter x */
+#define CAN_Filter_FIFO1             ((uint8_t)0x01)  /*!< Filter FIFO 1 assignment for filter x */
+#define IS_CAN_FILTER_FIFO(FIFO) (((FIFO) == CAN_FilterFIFO0) || \
+                                  ((FIFO) == CAN_FilterFIFO1))
+
+/* Legacy defines */
+#define CAN_FilterFIFO0  CAN_Filter_FIFO0
+#define CAN_FilterFIFO1  CAN_Filter_FIFO1
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Start_bank_filter_for_slave_CAN 
+  * @{
+  */
+#define IS_CAN_BANKNUMBER(BANKNUMBER) (((BANKNUMBER) >= 1) && ((BANKNUMBER) <= 27))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Tx 
+  * @{
+  */
+#define IS_CAN_TRANSMITMAILBOX(TRANSMITMAILBOX) ((TRANSMITMAILBOX) <= ((uint8_t)0x02))
+#define IS_CAN_STDID(STDID)   ((STDID) <= ((uint32_t)0x7FF))
+#define IS_CAN_EXTID(EXTID)   ((EXTID) <= ((uint32_t)0x1FFFFFFF))
+#define IS_CAN_DLC(DLC)       ((DLC) <= ((uint8_t)0x08))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_identifier_type 
+  * @{
+  */
+#define CAN_Id_Standard             ((uint32_t)0x00000000)  /*!< Standard Id */
+#define CAN_Id_Extended             ((uint32_t)0x00000004)  /*!< Extended Id */
+#define IS_CAN_IDTYPE(IDTYPE) (((IDTYPE) == CAN_Id_Standard) || \
+                               ((IDTYPE) == CAN_Id_Extended))
+
+/* Legacy defines */
+#define CAN_ID_STD      CAN_Id_Standard           
+#define CAN_ID_EXT      CAN_Id_Extended
+/**
+  * @}
+  */
+
+/** @defgroup CAN_remote_transmission_request 
+  * @{
+  */
+#define CAN_RTR_Data                ((uint32_t)0x00000000)  /*!< Data frame */
+#define CAN_RTR_Remote              ((uint32_t)0x00000002)  /*!< Remote frame */
+#define IS_CAN_RTR(RTR) (((RTR) == CAN_RTR_Data) || ((RTR) == CAN_RTR_Remote))
+
+/* Legacy defines */
+#define CAN_RTR_DATA     CAN_RTR_Data         
+#define CAN_RTR_REMOTE   CAN_RTR_Remote
+/**
+  * @}
+  */
+
+/** @defgroup CAN_transmit_constants 
+  * @{
+  */
+#define CAN_TxStatus_Failed         ((uint8_t)0x00)/*!< CAN transmission failed */
+#define CAN_TxStatus_Ok             ((uint8_t)0x01) /*!< CAN transmission succeeded */
+#define CAN_TxStatus_Pending        ((uint8_t)0x02) /*!< CAN transmission pending */
+#define CAN_TxStatus_NoMailBox      ((uint8_t)0x04) /*!< CAN cell did not provide 
+                                                         an empty mailbox */
+/* Legacy defines */	
+#define CANTXFAILED                  CAN_TxStatus_Failed
+#define CANTXOK                      CAN_TxStatus_Ok
+#define CANTXPENDING                 CAN_TxStatus_Pending
+#define CAN_NO_MB                    CAN_TxStatus_NoMailBox
+/**
+  * @}
+  */
+
+/** @defgroup CAN_receive_FIFO_number_constants 
+  * @{
+  */
+#define CAN_FIFO0                 ((uint8_t)0x00) /*!< CAN FIFO 0 used to receive */
+#define CAN_FIFO1                 ((uint8_t)0x01) /*!< CAN FIFO 1 used to receive */
+
+#define IS_CAN_FIFO(FIFO) (((FIFO) == CAN_FIFO0) || ((FIFO) == CAN_FIFO1))
+/**
+  * @}
+  */
+
+/** @defgroup CAN_sleep_constants 
+  * @{
+  */
+#define CAN_Sleep_Failed     ((uint8_t)0x00) /*!< CAN did not enter the sleep mode */
+#define CAN_Sleep_Ok         ((uint8_t)0x01) /*!< CAN entered the sleep mode */
+
+/* Legacy defines */	
+#define CANSLEEPFAILED   CAN_Sleep_Failed
+#define CANSLEEPOK       CAN_Sleep_Ok
+/**
+  * @}
+  */
+
+/** @defgroup CAN_wake_up_constants 
+  * @{
+  */
+#define CAN_WakeUp_Failed        ((uint8_t)0x00) /*!< CAN did not leave the sleep mode */
+#define CAN_WakeUp_Ok            ((uint8_t)0x01) /*!< CAN leaved the sleep mode */
+
+/* Legacy defines */
+#define CANWAKEUPFAILED   CAN_WakeUp_Failed        
+#define CANWAKEUPOK       CAN_WakeUp_Ok        
+/**
+  * @}
+  */
+
+/**
+  * @defgroup CAN_Error_Code_constants
+  * @{
+  */                                                         
+#define CAN_ErrorCode_NoErr           ((uint8_t)0x00) /*!< No Error */ 
+#define	CAN_ErrorCode_StuffErr        ((uint8_t)0x10) /*!< Stuff Error */ 
+#define	CAN_ErrorCode_FormErr         ((uint8_t)0x20) /*!< Form Error */ 
+#define	CAN_ErrorCode_ACKErr          ((uint8_t)0x30) /*!< Acknowledgment Error */ 
+#define	CAN_ErrorCode_BitRecessiveErr ((uint8_t)0x40) /*!< Bit Recessive Error */ 
+#define	CAN_ErrorCode_BitDominantErr  ((uint8_t)0x50) /*!< Bit Dominant Error */ 
+#define	CAN_ErrorCode_CRCErr          ((uint8_t)0x60) /*!< CRC Error  */ 
+#define	CAN_ErrorCode_SoftwareSetErr  ((uint8_t)0x70) /*!< Software Set Error */ 
+/**
+  * @}
+  */
+
+/** @defgroup CAN_flags 
+  * @{
+  */
+/* If the flag is 0x3XXXXXXX, it means that it can be used with CAN_GetFlagStatus()
+   and CAN_ClearFlag() functions. */
+/* If the flag is 0x1XXXXXXX, it means that it can only be used with 
+   CAN_GetFlagStatus() function.  */
+
+/* Transmit Flags */
+#define CAN_FLAG_RQCP0             ((uint32_t)0x38000001) /*!< Request MailBox0 Flag */
+#define CAN_FLAG_RQCP1             ((uint32_t)0x38000100) /*!< Request MailBox1 Flag */
+#define CAN_FLAG_RQCP2             ((uint32_t)0x38010000) /*!< Request MailBox2 Flag */
+
+/* Receive Flags */
+#define CAN_FLAG_FMP0              ((uint32_t)0x12000003) /*!< FIFO 0 Message Pending Flag */
+#define CAN_FLAG_FF0               ((uint32_t)0x32000008) /*!< FIFO 0 Full Flag            */
+#define CAN_FLAG_FOV0              ((uint32_t)0x32000010) /*!< FIFO 0 Overrun Flag         */
+#define CAN_FLAG_FMP1              ((uint32_t)0x14000003) /*!< FIFO 1 Message Pending Flag */
+#define CAN_FLAG_FF1               ((uint32_t)0x34000008) /*!< FIFO 1 Full Flag            */
+#define CAN_FLAG_FOV1              ((uint32_t)0x34000010) /*!< FIFO 1 Overrun Flag         */
+
+/* Operating Mode Flags */
+#define CAN_FLAG_WKU               ((uint32_t)0x31000008) /*!< Wake up Flag */
+#define CAN_FLAG_SLAK              ((uint32_t)0x31000012) /*!< Sleep acknowledge Flag */
+/* @note When SLAK interrupt is disabled (SLKIE=0), no polling on SLAKI is possible. 
+         In this case the SLAK bit can be polled.*/
+
+/* Error Flags */
+#define CAN_FLAG_EWG               ((uint32_t)0x10F00001) /*!< Error Warning Flag   */
+#define CAN_FLAG_EPV               ((uint32_t)0x10F00002) /*!< Error Passive Flag   */
+#define CAN_FLAG_BOF               ((uint32_t)0x10F00004) /*!< Bus-Off Flag         */
+#define CAN_FLAG_LEC               ((uint32_t)0x30F00070) /*!< Last error code Flag */
+
+#define IS_CAN_GET_FLAG(FLAG) (((FLAG) == CAN_FLAG_LEC)  || ((FLAG) == CAN_FLAG_BOF)   || \
+                               ((FLAG) == CAN_FLAG_EPV)  || ((FLAG) == CAN_FLAG_EWG)   || \
+                               ((FLAG) == CAN_FLAG_WKU)  || ((FLAG) == CAN_FLAG_FOV0)  || \
+                               ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FMP0)  || \
+                               ((FLAG) == CAN_FLAG_FOV1) || ((FLAG) == CAN_FLAG_FF1)   || \
+                               ((FLAG) == CAN_FLAG_FMP1) || ((FLAG) == CAN_FLAG_RQCP2) || \
+                               ((FLAG) == CAN_FLAG_RQCP1)|| ((FLAG) == CAN_FLAG_RQCP0) || \
+                               ((FLAG) == CAN_FLAG_SLAK ))
+
+#define IS_CAN_CLEAR_FLAG(FLAG)(((FLAG) == CAN_FLAG_LEC) || ((FLAG) == CAN_FLAG_RQCP2) || \
+                                ((FLAG) == CAN_FLAG_RQCP1)  || ((FLAG) == CAN_FLAG_RQCP0) || \
+                                ((FLAG) == CAN_FLAG_FF0)  || ((FLAG) == CAN_FLAG_FOV0) ||\
+                                ((FLAG) == CAN_FLAG_FF1) || ((FLAG) == CAN_FLAG_FOV1) || \
+                                ((FLAG) == CAN_FLAG_WKU) || ((FLAG) == CAN_FLAG_SLAK))
+/**
+  * @}
+  */
+
+  
+/** @defgroup CAN_interrupts 
+  * @{
+  */ 
+#define CAN_IT_TME                  ((uint32_t)0x00000001) /*!< Transmit mailbox empty Interrupt*/
+
+/* Receive Interrupts */
+#define CAN_IT_FMP0                 ((uint32_t)0x00000002) /*!< FIFO 0 message pending Interrupt*/
+#define CAN_IT_FF0                  ((uint32_t)0x00000004) /*!< FIFO 0 full Interrupt*/
+#define CAN_IT_FOV0                 ((uint32_t)0x00000008) /*!< FIFO 0 overrun Interrupt*/
+#define CAN_IT_FMP1                 ((uint32_t)0x00000010) /*!< FIFO 1 message pending Interrupt*/
+#define CAN_IT_FF1                  ((uint32_t)0x00000020) /*!< FIFO 1 full Interrupt*/
+#define CAN_IT_FOV1                 ((uint32_t)0x00000040) /*!< FIFO 1 overrun Interrupt*/
+
+/* Operating Mode Interrupts */
+#define CAN_IT_WKU                  ((uint32_t)0x00010000) /*!< Wake-up Interrupt*/
+#define CAN_IT_SLK                  ((uint32_t)0x00020000) /*!< Sleep acknowledge Interrupt*/
+
+/* Error Interrupts */
+#define CAN_IT_EWG                  ((uint32_t)0x00000100) /*!< Error warning Interrupt*/
+#define CAN_IT_EPV                  ((uint32_t)0x00000200) /*!< Error passive Interrupt*/
+#define CAN_IT_BOF                  ((uint32_t)0x00000400) /*!< Bus-off Interrupt*/
+#define CAN_IT_LEC                  ((uint32_t)0x00000800) /*!< Last error code Interrupt*/
+#define CAN_IT_ERR                  ((uint32_t)0x00008000) /*!< Error Interrupt*/
+
+/* Flags named as Interrupts : kept only for FW compatibility */
+#define CAN_IT_RQCP0   CAN_IT_TME
+#define CAN_IT_RQCP1   CAN_IT_TME
+#define CAN_IT_RQCP2   CAN_IT_TME
+
+
+#define IS_CAN_IT(IT)        (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FMP0)  ||\
+                             ((IT) == CAN_IT_FF0)  || ((IT) == CAN_IT_FOV0)  ||\
+                             ((IT) == CAN_IT_FMP1) || ((IT) == CAN_IT_FF1)   ||\
+                             ((IT) == CAN_IT_FOV1) || ((IT) == CAN_IT_EWG)   ||\
+                             ((IT) == CAN_IT_EPV)  || ((IT) == CAN_IT_BOF)   ||\
+                             ((IT) == CAN_IT_LEC)  || ((IT) == CAN_IT_ERR)   ||\
+                             ((IT) == CAN_IT_WKU)  || ((IT) == CAN_IT_SLK))
+
+#define IS_CAN_CLEAR_IT(IT) (((IT) == CAN_IT_TME) || ((IT) == CAN_IT_FF0)    ||\
+                             ((IT) == CAN_IT_FOV0)|| ((IT) == CAN_IT_FF1)    ||\
+                             ((IT) == CAN_IT_FOV1)|| ((IT) == CAN_IT_EWG)    ||\
+                             ((IT) == CAN_IT_EPV) || ((IT) == CAN_IT_BOF)    ||\
+                             ((IT) == CAN_IT_LEC) || ((IT) == CAN_IT_ERR)    ||\
+                             ((IT) == CAN_IT_WKU) || ((IT) == CAN_IT_SLK))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/  
+
+/*  Function used to set the CAN configuration to the default reset state *****/ 
+void CAN_DeInit(CAN_TypeDef* CANx);
+
+/* Initialization and Configuration functions *********************************/ 
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct);
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct);
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct);
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber); 
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState);
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState);
+
+/* CAN Frames Transmission functions ******************************************/
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage);
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox);
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox);
+
+/* CAN Frames Reception functions *********************************************/
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage);
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber);
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber);
+
+/* Operation modes functions **************************************************/
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode);
+uint8_t CAN_Sleep(CAN_TypeDef* CANx);
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx);
+
+/* CAN Bus Error management functions *****************************************/
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx);
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx);
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx);
+
+/* Interrupts and flags management functions **********************************/
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState);
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG);
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT);
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_CAN_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h
new file mode 100644
index 0000000000..fc2d3b1958
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_crc.h
@@ -0,0 +1,77 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_crc.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the CRC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_CRC_H
+#define __STM32F4xx_CRC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CRC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRC_Exported_Constants
+  * @{
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/  
+
+void CRC_ResetDR(void);
+uint32_t CRC_CalcCRC(uint32_t Data);
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength);
+uint32_t CRC_GetCRC(void);
+void CRC_SetIDRegister(uint8_t IDValue);
+uint8_t CRC_GetIDRegister(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_CRC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h
new file mode 100644
index 0000000000..4a43d5d71e
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_cryp.h
@@ -0,0 +1,338 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_cryp.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the Cryptographic
+  *          processor(CRYP) firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_CRYP_H
+#define __STM32F4xx_CRYP_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup CRYP
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief   CRYP Init structure definition  
+  */ 
+typedef struct
+{
+  uint16_t CRYP_AlgoDir;   /*!< Encrypt or Decrypt. This parameter can be a 
+                                value of @ref CRYP_Algorithm_Direction */
+  uint16_t CRYP_AlgoMode;  /*!< TDES-ECB, TDES-CBC, DES-ECB, DES-CBC, AES-ECB, 
+                                AES-CBC, AES-CTR, AES-Key. This parameter can be
+                                a value of @ref CRYP_Algorithm_Mode */
+  uint16_t CRYP_DataType;  /*!< 32-bit data, 16-bit data, bit data or bit-string.
+                                This parameter can be a value of @ref CRYP_Data_Type */ 
+  uint16_t CRYP_KeySize;   /*!< Used only in AES mode only : 128, 192 or 256 bit 
+                                key length. This parameter can be a value of 
+                                @ref CRYP_Key_Size_for_AES_only */
+}CRYP_InitTypeDef;
+
+/** 
+  * @brief   CRYP Key(s) structure definition  
+  */ 
+typedef struct
+{
+  uint32_t CRYP_Key0Left;  /*!< Key 0 Left  */
+  uint32_t CRYP_Key0Right; /*!< Key 0 Right */
+  uint32_t CRYP_Key1Left;  /*!< Key 1 left  */
+  uint32_t CRYP_Key1Right; /*!< Key 1 Right */
+  uint32_t CRYP_Key2Left;  /*!< Key 2 left  */
+  uint32_t CRYP_Key2Right; /*!< Key 2 Right */
+  uint32_t CRYP_Key3Left;  /*!< Key 3 left  */
+  uint32_t CRYP_Key3Right; /*!< Key 3 Right */
+}CRYP_KeyInitTypeDef;
+/** 
+  * @brief   CRYP Initialization Vectors (IV) structure definition  
+  */ 
+typedef struct
+{
+  uint32_t CRYP_IV0Left;  /*!< Init Vector 0 Left  */
+  uint32_t CRYP_IV0Right; /*!< Init Vector 0 Right */
+  uint32_t CRYP_IV1Left;  /*!< Init Vector 1 left  */
+  uint32_t CRYP_IV1Right; /*!< Init Vector 1 Right */
+}CRYP_IVInitTypeDef;
+
+/** 
+  * @brief  CRYP context swapping structure definition  
+  */ 
+typedef struct
+{
+  /*!< Configuration */
+  uint32_t CR_bits9to2;
+  /*!< KEY */
+  uint32_t CRYP_IV0LR;
+  uint32_t CRYP_IV0RR;
+  uint32_t CRYP_IV1LR;
+  uint32_t CRYP_IV1RR;
+  /*!< IV */
+  uint32_t CRYP_K0LR;
+  uint32_t CRYP_K0RR;
+  uint32_t CRYP_K1LR;
+  uint32_t CRYP_K1RR;
+  uint32_t CRYP_K2LR;
+  uint32_t CRYP_K2RR;
+  uint32_t CRYP_K3LR;
+  uint32_t CRYP_K3RR;
+}CRYP_Context;
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup CRYP_Exported_Constants
+  * @{
+  */
+
+/** @defgroup CRYP_Algorithm_Direction 
+  * @{
+  */
+#define CRYP_AlgoDir_Encrypt      ((uint16_t)0x0000)
+#define CRYP_AlgoDir_Decrypt      ((uint16_t)0x0004)
+#define IS_CRYP_ALGODIR(ALGODIR) (((ALGODIR) == CRYP_AlgoDir_Encrypt) || \
+                                  ((ALGODIR) == CRYP_AlgoDir_Decrypt))
+
+/**
+  * @}
+  */ 
+ 
+/** @defgroup CRYP_Algorithm_Mode 
+  * @{
+  */
+
+/*!< TDES Modes */
+#define CRYP_AlgoMode_TDES_ECB    ((uint16_t)0x0000)
+#define CRYP_AlgoMode_TDES_CBC    ((uint16_t)0x0008)
+
+/*!< DES Modes */
+#define CRYP_AlgoMode_DES_ECB     ((uint16_t)0x0010)
+#define CRYP_AlgoMode_DES_CBC     ((uint16_t)0x0018)
+
+/*!< AES Modes */
+#define CRYP_AlgoMode_AES_ECB     ((uint16_t)0x0020)
+#define CRYP_AlgoMode_AES_CBC     ((uint16_t)0x0028)
+#define CRYP_AlgoMode_AES_CTR     ((uint16_t)0x0030)
+#define CRYP_AlgoMode_AES_Key     ((uint16_t)0x0038)
+
+#define IS_CRYP_ALGOMODE(ALGOMODE) (((ALGOMODE) == CRYP_AlgoMode_TDES_ECB) || \
+                                   ((ALGOMODE) == CRYP_AlgoMode_TDES_CBC)|| \
+                                   ((ALGOMODE) == CRYP_AlgoMode_DES_ECB)|| \
+                                   ((ALGOMODE) == CRYP_AlgoMode_DES_CBC) || \
+                                   ((ALGOMODE) == CRYP_AlgoMode_AES_ECB) || \
+                                   ((ALGOMODE) == CRYP_AlgoMode_AES_CBC) || \
+                                   ((ALGOMODE) == CRYP_AlgoMode_AES_CTR) || \
+                                   ((ALGOMODE) == CRYP_AlgoMode_AES_Key))
+/**
+  * @}
+  */ 
+ 
+/** @defgroup CRYP_Data_Type 
+  * @{
+  */
+#define CRYP_DataType_32b         ((uint16_t)0x0000)
+#define CRYP_DataType_16b         ((uint16_t)0x0040)
+#define CRYP_DataType_8b          ((uint16_t)0x0080)
+#define CRYP_DataType_1b          ((uint16_t)0x00C0)
+#define IS_CRYP_DATATYPE(DATATYPE) (((DATATYPE) == CRYP_DataType_32b) || \
+                                    ((DATATYPE) == CRYP_DataType_16b)|| \
+                                    ((DATATYPE) == CRYP_DataType_8b)|| \
+                                    ((DATATYPE) == CRYP_DataType_1b))  
+/**
+  * @}
+  */
+                                     
+/** @defgroup CRYP_Key_Size_for_AES_only 
+  * @{
+  */
+#define CRYP_KeySize_128b         ((uint16_t)0x0000)
+#define CRYP_KeySize_192b         ((uint16_t)0x0100)
+#define CRYP_KeySize_256b         ((uint16_t)0x0200)
+#define IS_CRYP_KEYSIZE(KEYSIZE) (((KEYSIZE) == CRYP_KeySize_128b)|| \
+                                  ((KEYSIZE) == CRYP_KeySize_192b)|| \
+                                  ((KEYSIZE) == CRYP_KeySize_256b))
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_flags_definition 
+  * @{
+  */
+#define CRYP_FLAG_BUSY            ((uint8_t)0x10)  /*!< The CRYP core is currently 
+                                                        processing a block of data 
+                                                        or a key preparation (for 
+                                                        AES decryption). */
+#define CRYP_FLAG_IFEM            ((uint8_t)0x01)  /*!< Input Fifo Empty */
+#define CRYP_FLAG_IFNF            ((uint8_t)0x02)  /*!< Input Fifo is Not Full */
+#define CRYP_FLAG_INRIS           ((uint8_t)0x22)  /*!< Raw interrupt pending */
+#define CRYP_FLAG_OFNE            ((uint8_t)0x04)  /*!< Input Fifo service raw 
+                                                        interrupt status */
+#define CRYP_FLAG_OFFU            ((uint8_t)0x08)  /*!< Output Fifo is Full */
+#define CRYP_FLAG_OUTRIS          ((uint8_t)0x21)  /*!< Output Fifo service raw 
+                                                        interrupt status */
+
+#define IS_CRYP_GET_FLAG(FLAG) (((FLAG) == CRYP_FLAG_IFEM)  || \
+                                ((FLAG) == CRYP_FLAG_IFNF)  || \
+                                ((FLAG) == CRYP_FLAG_OFNE)  || \
+                                ((FLAG) == CRYP_FLAG_OFFU)  || \
+                                ((FLAG) == CRYP_FLAG_BUSY)  || \
+                                ((FLAG) == CRYP_FLAG_OUTRIS)|| \
+                                ((FLAG) == CRYP_FLAG_INRIS))
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_interrupts_definition 
+  * @{
+  */
+#define CRYP_IT_INI               ((uint8_t)0x01) /*!< IN Fifo Interrupt */
+#define CRYP_IT_OUTI              ((uint8_t)0x02) /*!< OUT Fifo Interrupt */
+#define IS_CRYP_CONFIG_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))
+#define IS_CRYP_GET_IT(IT) (((IT) == CRYP_IT_INI) || ((IT) == CRYP_IT_OUTI))
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Encryption_Decryption_modes_definition 
+  * @{
+  */
+#define MODE_ENCRYPT             ((uint8_t)0x01)
+#define MODE_DECRYPT             ((uint8_t)0x00)
+
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_DMA_transfer_requests 
+  * @{
+  */
+#define CRYP_DMAReq_DataIN             ((uint8_t)0x01)
+#define CRYP_DMAReq_DataOUT            ((uint8_t)0x02)
+#define IS_CRYP_DMAREQ(DMAREQ) ((((DMAREQ) & (uint8_t)0xFC) == 0x00) && ((DMAREQ) != 0x00))
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/*  Function used to set the CRYP configuration to the default reset state ****/
+void CRYP_DeInit(void);
+
+/* CRYP Initialization and Configuration functions ****************************/
+void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct);
+void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct);
+void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
+void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
+void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
+void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct);
+void CRYP_Cmd(FunctionalState NewState);
+
+/* CRYP Data processing functions *********************************************/
+void CRYP_DataIn(uint32_t Data);
+uint32_t CRYP_DataOut(void);
+void CRYP_FIFOFlush(void);
+
+/* CRYP Context swapping functions ********************************************/
+ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
+                             CRYP_KeyInitTypeDef* CRYP_KeyInitStruct);
+void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore);
+
+/* CRYP's DMA interface function **********************************************/
+void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState);
+ITStatus CRYP_GetITStatus(uint8_t CRYP_IT);
+FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG);
+
+/* High Level AES functions **************************************************/
+ErrorStatus CRYP_AES_ECB(uint8_t Mode,
+                         uint8_t *Key, uint16_t Keysize,
+                         uint8_t *Input, uint32_t Ilength,
+                         uint8_t *Output);
+
+ErrorStatus CRYP_AES_CBC(uint8_t Mode,
+                         uint8_t InitVectors[16],
+                         uint8_t *Key, uint16_t Keysize,
+                         uint8_t *Input, uint32_t Ilength,
+                         uint8_t *Output);
+
+ErrorStatus CRYP_AES_CTR(uint8_t Mode,
+                         uint8_t InitVectors[16],
+                         uint8_t *Key, uint16_t Keysize,
+                         uint8_t *Input, uint32_t Ilength,
+                         uint8_t *Output);
+
+/* High Level TDES functions **************************************************/
+ErrorStatus CRYP_TDES_ECB(uint8_t Mode,
+                           uint8_t Key[24], 
+                           uint8_t *Input, uint32_t Ilength,
+                           uint8_t *Output);
+
+ErrorStatus CRYP_TDES_CBC(uint8_t Mode,
+                          uint8_t Key[24],
+                          uint8_t InitVectors[8],
+                          uint8_t *Input, uint32_t Ilength,
+                          uint8_t *Output);
+
+/* High Level DES functions **************************************************/
+ErrorStatus CRYP_DES_ECB(uint8_t Mode,
+                         uint8_t Key[8],
+                         uint8_t *Input, uint32_t Ilength,
+                         uint8_t *Output);
+
+ErrorStatus CRYP_DES_CBC(uint8_t Mode,
+                         uint8_t Key[8],
+                         uint8_t InitVectors[8],
+                         uint8_t *Input,uint32_t Ilength,
+                         uint8_t *Output);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_CRYP_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h
new file mode 100644
index 0000000000..4eebc3fafb
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dac.h
@@ -0,0 +1,298 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dac.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the DAC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_DAC_H
+#define __STM32F4xx_DAC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DAC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  DAC Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t DAC_Trigger;                      /*!< Specifies the external trigger for the selected DAC channel.
+                                                  This parameter can be a value of @ref DAC_trigger_selection */
+
+  uint32_t DAC_WaveGeneration;               /*!< Specifies whether DAC channel noise waves or triangle waves
+                                                  are generated, or whether no wave is generated.
+                                                  This parameter can be a value of @ref DAC_wave_generation */
+
+  uint32_t DAC_LFSRUnmask_TriangleAmplitude; /*!< Specifies the LFSR mask for noise wave generation or
+                                                  the maximum amplitude triangle generation for the DAC channel. 
+                                                  This parameter can be a value of @ref DAC_lfsrunmask_triangleamplitude */
+
+  uint32_t DAC_OutputBuffer;                 /*!< Specifies whether the DAC channel output buffer is enabled or disabled.
+                                                  This parameter can be a value of @ref DAC_output_buffer */
+}DAC_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DAC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup DAC_trigger_selection 
+  * @{
+  */
+
+#define DAC_Trigger_None                   ((uint32_t)0x00000000) /*!< Conversion is automatic once the DAC1_DHRxxxx register 
+                                                                       has been loaded, and not by external trigger */
+#define DAC_Trigger_T2_TRGO                ((uint32_t)0x00000024) /*!< TIM2 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T4_TRGO                ((uint32_t)0x0000002C) /*!< TIM4 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T5_TRGO                ((uint32_t)0x0000001C) /*!< TIM5 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T6_TRGO                ((uint32_t)0x00000004) /*!< TIM6 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T7_TRGO                ((uint32_t)0x00000014) /*!< TIM7 TRGO selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_T8_TRGO                ((uint32_t)0x0000000C) /*!< TIM8 TRGO selected as external conversion trigger for DAC channel */                                                                       
+
+#define DAC_Trigger_Ext_IT9                ((uint32_t)0x00000034) /*!< EXTI Line9 event selected as external conversion trigger for DAC channel */
+#define DAC_Trigger_Software               ((uint32_t)0x0000003C) /*!< Conversion started by software trigger for DAC channel */
+
+#define IS_DAC_TRIGGER(TRIGGER) (((TRIGGER) == DAC_Trigger_None) || \
+                                 ((TRIGGER) == DAC_Trigger_T6_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T8_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T7_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T5_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T2_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_T4_TRGO) || \
+                                 ((TRIGGER) == DAC_Trigger_Ext_IT9) || \
+                                 ((TRIGGER) == DAC_Trigger_Software))
+
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation 
+  * @{
+  */
+
+#define DAC_WaveGeneration_None            ((uint32_t)0x00000000)
+#define DAC_WaveGeneration_Noise           ((uint32_t)0x00000040)
+#define DAC_WaveGeneration_Triangle        ((uint32_t)0x00000080)
+#define IS_DAC_GENERATE_WAVE(WAVE) (((WAVE) == DAC_WaveGeneration_None) || \
+                                    ((WAVE) == DAC_WaveGeneration_Noise) || \
+                                    ((WAVE) == DAC_WaveGeneration_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_lfsrunmask_triangleamplitude
+  * @{
+  */
+
+#define DAC_LFSRUnmask_Bit0                ((uint32_t)0x00000000) /*!< Unmask DAC channel LFSR bit0 for noise wave generation */
+#define DAC_LFSRUnmask_Bits1_0             ((uint32_t)0x00000100) /*!< Unmask DAC channel LFSR bit[1:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits2_0             ((uint32_t)0x00000200) /*!< Unmask DAC channel LFSR bit[2:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits3_0             ((uint32_t)0x00000300) /*!< Unmask DAC channel LFSR bit[3:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits4_0             ((uint32_t)0x00000400) /*!< Unmask DAC channel LFSR bit[4:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits5_0             ((uint32_t)0x00000500) /*!< Unmask DAC channel LFSR bit[5:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits6_0             ((uint32_t)0x00000600) /*!< Unmask DAC channel LFSR bit[6:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits7_0             ((uint32_t)0x00000700) /*!< Unmask DAC channel LFSR bit[7:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits8_0             ((uint32_t)0x00000800) /*!< Unmask DAC channel LFSR bit[8:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits9_0             ((uint32_t)0x00000900) /*!< Unmask DAC channel LFSR bit[9:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits10_0            ((uint32_t)0x00000A00) /*!< Unmask DAC channel LFSR bit[10:0] for noise wave generation */
+#define DAC_LFSRUnmask_Bits11_0            ((uint32_t)0x00000B00) /*!< Unmask DAC channel LFSR bit[11:0] for noise wave generation */
+#define DAC_TriangleAmplitude_1            ((uint32_t)0x00000000) /*!< Select max triangle amplitude of 1 */
+#define DAC_TriangleAmplitude_3            ((uint32_t)0x00000100) /*!< Select max triangle amplitude of 3 */
+#define DAC_TriangleAmplitude_7            ((uint32_t)0x00000200) /*!< Select max triangle amplitude of 7 */
+#define DAC_TriangleAmplitude_15           ((uint32_t)0x00000300) /*!< Select max triangle amplitude of 15 */
+#define DAC_TriangleAmplitude_31           ((uint32_t)0x00000400) /*!< Select max triangle amplitude of 31 */
+#define DAC_TriangleAmplitude_63           ((uint32_t)0x00000500) /*!< Select max triangle amplitude of 63 */
+#define DAC_TriangleAmplitude_127          ((uint32_t)0x00000600) /*!< Select max triangle amplitude of 127 */
+#define DAC_TriangleAmplitude_255          ((uint32_t)0x00000700) /*!< Select max triangle amplitude of 255 */
+#define DAC_TriangleAmplitude_511          ((uint32_t)0x00000800) /*!< Select max triangle amplitude of 511 */
+#define DAC_TriangleAmplitude_1023         ((uint32_t)0x00000900) /*!< Select max triangle amplitude of 1023 */
+#define DAC_TriangleAmplitude_2047         ((uint32_t)0x00000A00) /*!< Select max triangle amplitude of 2047 */
+#define DAC_TriangleAmplitude_4095         ((uint32_t)0x00000B00) /*!< Select max triangle amplitude of 4095 */
+
+#define IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(VALUE) (((VALUE) == DAC_LFSRUnmask_Bit0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits1_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits2_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits3_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits4_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits5_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits6_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits7_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits8_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits9_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits10_0) || \
+                                                      ((VALUE) == DAC_LFSRUnmask_Bits11_0) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_1) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_3) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_7) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_15) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_31) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_63) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_127) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_255) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_511) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_1023) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_2047) || \
+                                                      ((VALUE) == DAC_TriangleAmplitude_4095))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_output_buffer 
+  * @{
+  */
+
+#define DAC_OutputBuffer_Enable            ((uint32_t)0x00000000)
+#define DAC_OutputBuffer_Disable           ((uint32_t)0x00000002)
+#define IS_DAC_OUTPUT_BUFFER_STATE(STATE) (((STATE) == DAC_OutputBuffer_Enable) || \
+                                           ((STATE) == DAC_OutputBuffer_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Channel_selection 
+  * @{
+  */
+
+#define DAC_Channel_1                      ((uint32_t)0x00000000)
+#define DAC_Channel_2                      ((uint32_t)0x00000010)
+#define IS_DAC_CHANNEL(CHANNEL) (((CHANNEL) == DAC_Channel_1) || \
+                                 ((CHANNEL) == DAC_Channel_2))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data_alignement 
+  * @{
+  */
+
+#define DAC_Align_12b_R                    ((uint32_t)0x00000000)
+#define DAC_Align_12b_L                    ((uint32_t)0x00000004)
+#define DAC_Align_8b_R                     ((uint32_t)0x00000008)
+#define IS_DAC_ALIGN(ALIGN) (((ALIGN) == DAC_Align_12b_R) || \
+                             ((ALIGN) == DAC_Align_12b_L) || \
+                             ((ALIGN) == DAC_Align_8b_R))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_wave_generation 
+  * @{
+  */
+
+#define DAC_Wave_Noise                     ((uint32_t)0x00000040)
+#define DAC_Wave_Triangle                  ((uint32_t)0x00000080)
+#define IS_DAC_WAVE(WAVE) (((WAVE) == DAC_Wave_Noise) || \
+                           ((WAVE) == DAC_Wave_Triangle))
+/**
+  * @}
+  */
+
+/** @defgroup DAC_data 
+  * @{
+  */
+
+#define IS_DAC_DATA(DATA) ((DATA) <= 0xFFF0) 
+/**
+  * @}
+  */
+  
+/** @defgroup DAC_interrupts_definition 
+  * @{
+  */   
+#define DAC_IT_DMAUDR                      ((uint32_t)0x00002000)  
+#define IS_DAC_IT(IT) (((IT) == DAC_IT_DMAUDR)) 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup DAC_flags_definition 
+  * @{
+  */ 
+  
+#define DAC_FLAG_DMAUDR                    ((uint32_t)0x00002000)  
+#define IS_DAC_FLAG(FLAG) (((FLAG) == DAC_FLAG_DMAUDR))  
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/  
+
+/*  Function used to set the DAC configuration to the default reset state *****/  
+void DAC_DeInit(void);
+
+/*  DAC channels configuration: trigger, output buffer, data format functions */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct);
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct);
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState);
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState);
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState);
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data);
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1);
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel);
+
+/* DMA management functions ***************************************************/
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState);
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG);
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT);
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_DAC_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h
new file mode 100644
index 0000000000..353d3b3616
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dbgmcu.h
@@ -0,0 +1,103 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dbgmcu.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the DBGMCU firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_DBGMCU_H
+#define __STM32F4xx_DBGMCU_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DBGMCU
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Exported_Constants
+  * @{
+  */ 
+#define DBGMCU_SLEEP                 ((uint32_t)0x00000001)
+#define DBGMCU_STOP                  ((uint32_t)0x00000002)
+#define DBGMCU_STANDBY               ((uint32_t)0x00000004)
+#define IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM2_STOP             ((uint32_t)0x00000001)
+#define DBGMCU_TIM3_STOP             ((uint32_t)0x00000002)
+#define DBGMCU_TIM4_STOP             ((uint32_t)0x00000004)
+#define DBGMCU_TIM5_STOP             ((uint32_t)0x00000008)
+#define DBGMCU_TIM6_STOP             ((uint32_t)0x00000010)
+#define DBGMCU_TIM7_STOP             ((uint32_t)0x00000020)
+#define DBGMCU_TIM12_STOP            ((uint32_t)0x00000040)
+#define DBGMCU_TIM13_STOP            ((uint32_t)0x00000080)
+#define DBGMCU_TIM14_STOP            ((uint32_t)0x00000100)
+#define DBGMCU_RTC_STOP              ((uint32_t)0x00000400)
+#define DBGMCU_WWDG_STOP             ((uint32_t)0x00000800)
+#define DBGMCU_IWDG_STOP             ((uint32_t)0x00001000)
+#define DBGMCU_I2C1_SMBUS_TIMEOUT    ((uint32_t)0x00200000)
+#define DBGMCU_I2C2_SMBUS_TIMEOUT    ((uint32_t)0x00400000)
+#define DBGMCU_I2C3_SMBUS_TIMEOUT    ((uint32_t)0x00800000)
+#define DBGMCU_CAN1_STOP             ((uint32_t)0x02000000)
+#define DBGMCU_CAN2_STOP             ((uint32_t)0x04000000)
+#define IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xF91FE200) == 0x00) && ((PERIPH) != 0x00))
+
+#define DBGMCU_TIM1_STOP             ((uint32_t)0x00000001)
+#define DBGMCU_TIM8_STOP             ((uint32_t)0x00000002)
+#define DBGMCU_TIM9_STOP             ((uint32_t)0x00010000)
+#define DBGMCU_TIM10_STOP            ((uint32_t)0x00020000)
+#define DBGMCU_TIM11_STOP            ((uint32_t)0x00040000)
+#define IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFF8FFFC) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+uint32_t DBGMCU_GetREVID(void);
+uint32_t DBGMCU_GetDEVID(void);
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_DBGMCU_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h
new file mode 100644
index 0000000000..b0034142b9
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dcmi.h
@@ -0,0 +1,306 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dcmi.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the DCMI firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_DCMI_H
+#define __STM32F4xx_DCMI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DCMI
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** 
+  * @brief   DCMI Init structure definition  
+  */ 
+typedef struct
+{
+  uint16_t DCMI_CaptureMode;      /*!< Specifies the Capture Mode: Continuous or Snapshot.
+                                       This parameter can be a value of @ref DCMI_Capture_Mode */
+
+  uint16_t DCMI_SynchroMode;      /*!< Specifies the Synchronization Mode: Hardware or Embedded.
+                                       This parameter can be a value of @ref DCMI_Synchronization_Mode */
+
+  uint16_t DCMI_PCKPolarity;      /*!< Specifies the Pixel clock polarity: Falling or Rising.
+                                       This parameter can be a value of @ref DCMI_PIXCK_Polarity */
+
+  uint16_t DCMI_VSPolarity;       /*!< Specifies the Vertical synchronization polarity: High or Low.
+                                       This parameter can be a value of @ref DCMI_VSYNC_Polarity */
+
+  uint16_t DCMI_HSPolarity;       /*!< Specifies the Horizontal synchronization polarity: High or Low.
+                                       This parameter can be a value of @ref DCMI_HSYNC_Polarity */
+
+  uint16_t DCMI_CaptureRate;      /*!< Specifies the frequency of frame capture: All, 1/2 or 1/4.
+                                       This parameter can be a value of @ref DCMI_Capture_Rate */
+
+  uint16_t DCMI_ExtendedDataMode; /*!< Specifies the data width: 8-bit, 10-bit, 12-bit or 14-bit.
+                                       This parameter can be a value of @ref DCMI_Extended_Data_Mode */
+} DCMI_InitTypeDef;
+
+/** 
+  * @brief   DCMI CROP Init structure definition  
+  */ 
+typedef struct
+{
+  uint16_t DCMI_VerticalStartLine;      /*!< Specifies the Vertical start line count from which the image capture
+                                             will start. This parameter can be a value between 0x00 and 0x1FFF */
+
+  uint16_t DCMI_HorizontalOffsetCount;  /*!< Specifies the number of pixel clocks to count before starting a capture.
+                                             This parameter can be a value between 0x00 and 0x3FFF */
+
+  uint16_t DCMI_VerticalLineCount;      /*!< Specifies the number of lines to be captured from the starting point.
+                                             This parameter can be a value between 0x00 and 0x3FFF */
+
+  uint16_t DCMI_CaptureCount;           /*!< Specifies the number of pixel clocks to be captured from the starting
+                                             point on the same line.
+                                             This parameter can be a value between 0x00 and 0x3FFF */
+} DCMI_CROPInitTypeDef;
+
+/** 
+  * @brief   DCMI Embedded Synchronisation CODE Init structure definition  
+  */ 
+typedef struct
+{
+  uint8_t DCMI_FrameStartCode; /*!< Specifies the code of the frame start delimiter. */
+  uint8_t DCMI_LineStartCode;  /*!< Specifies the code of the line start delimiter. */
+  uint8_t DCMI_LineEndCode;    /*!< Specifies the code of the line end delimiter. */
+  uint8_t DCMI_FrameEndCode;   /*!< Specifies the code of the frame end delimiter. */
+} DCMI_CodesInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DCMI_Exported_Constants
+  * @{
+  */
+
+/** @defgroup DCMI_Capture_Mode 
+  * @{
+  */ 
+#define DCMI_CaptureMode_Continuous    ((uint16_t)0x0000) /*!< The received data are transferred continuously 
+                                                               into the destination memory through the DMA */
+#define DCMI_CaptureMode_SnapShot      ((uint16_t)0x0002) /*!< Once activated, the interface waits for the start of 
+                                                               frame and then transfers a single frame through the DMA */
+#define IS_DCMI_CAPTURE_MODE(MODE)(((MODE) == DCMI_CaptureMode_Continuous) || \
+                                   ((MODE) == DCMI_CaptureMode_SnapShot))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DCMI_Synchronization_Mode
+  * @{
+  */ 
+#define DCMI_SynchroMode_Hardware    ((uint16_t)0x0000) /*!< Hardware synchronization data capture (frame/line start/stop)
+                                                             is synchronized with the HSYNC/VSYNC signals */
+#define DCMI_SynchroMode_Embedded    ((uint16_t)0x0010) /*!< Embedded synchronization data capture is synchronized with 
+                                                             synchronization codes embedded in the data flow */
+#define IS_DCMI_SYNCHRO(MODE)(((MODE) == DCMI_SynchroMode_Hardware) || \
+                              ((MODE) == DCMI_SynchroMode_Embedded))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DCMI_PIXCK_Polarity 
+  * @{
+  */ 
+#define DCMI_PCKPolarity_Falling    ((uint16_t)0x0000) /*!< Pixel clock active on Falling edge */
+#define DCMI_PCKPolarity_Rising     ((uint16_t)0x0020) /*!< Pixel clock active on Rising edge */
+#define IS_DCMI_PCKPOLARITY(POLARITY)(((POLARITY) == DCMI_PCKPolarity_Falling) || \
+                                      ((POLARITY) == DCMI_PCKPolarity_Rising))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DCMI_VSYNC_Polarity 
+  * @{
+  */ 
+#define DCMI_VSPolarity_Low     ((uint16_t)0x0000) /*!< Vertical synchronization active Low */
+#define DCMI_VSPolarity_High    ((uint16_t)0x0080) /*!< Vertical synchronization active High */
+#define IS_DCMI_VSPOLARITY(POLARITY)(((POLARITY) == DCMI_VSPolarity_Low) || \
+                                     ((POLARITY) == DCMI_VSPolarity_High))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DCMI_HSYNC_Polarity 
+  * @{
+  */ 
+#define DCMI_HSPolarity_Low     ((uint16_t)0x0000) /*!< Horizontal synchronization active Low */
+#define DCMI_HSPolarity_High    ((uint16_t)0x0040) /*!< Horizontal synchronization active High */
+#define IS_DCMI_HSPOLARITY(POLARITY)(((POLARITY) == DCMI_HSPolarity_Low) || \
+                                     ((POLARITY) == DCMI_HSPolarity_High))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DCMI_Capture_Rate 
+  * @{
+  */ 
+#define DCMI_CaptureRate_All_Frame     ((uint16_t)0x0000) /*!< All frames are captured */
+#define DCMI_CaptureRate_1of2_Frame    ((uint16_t)0x0100) /*!< Every alternate frame captured */
+#define DCMI_CaptureRate_1of4_Frame    ((uint16_t)0x0200) /*!< One frame in 4 frames captured */
+#define IS_DCMI_CAPTURE_RATE(RATE) (((RATE) == DCMI_CaptureRate_All_Frame) || \
+                                    ((RATE) == DCMI_CaptureRate_1of2_Frame) ||\
+                                    ((RATE) == DCMI_CaptureRate_1of4_Frame))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DCMI_Extended_Data_Mode 
+  * @{
+  */ 
+#define DCMI_ExtendedDataMode_8b     ((uint16_t)0x0000) /*!< Interface captures 8-bit data on every pixel clock */
+#define DCMI_ExtendedDataMode_10b    ((uint16_t)0x0400) /*!< Interface captures 10-bit data on every pixel clock */
+#define DCMI_ExtendedDataMode_12b    ((uint16_t)0x0800) /*!< Interface captures 12-bit data on every pixel clock */
+#define DCMI_ExtendedDataMode_14b    ((uint16_t)0x0C00) /*!< Interface captures 14-bit data on every pixel clock */
+#define IS_DCMI_EXTENDED_DATA(DATA)(((DATA) == DCMI_ExtendedDataMode_8b) || \
+                                    ((DATA) == DCMI_ExtendedDataMode_10b) ||\
+                                    ((DATA) == DCMI_ExtendedDataMode_12b) ||\
+                                    ((DATA) == DCMI_ExtendedDataMode_14b))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DCMI_interrupt_sources 
+  * @{
+  */ 
+#define DCMI_IT_FRAME    ((uint16_t)0x0001)
+#define DCMI_IT_OVF      ((uint16_t)0x0002)
+#define DCMI_IT_ERR      ((uint16_t)0x0004)
+#define DCMI_IT_VSYNC    ((uint16_t)0x0008)
+#define DCMI_IT_LINE     ((uint16_t)0x0010)
+#define IS_DCMI_CONFIG_IT(IT) ((((IT) & (uint16_t)0xFFE0) == 0x0000) && ((IT) != 0x0000))
+#define IS_DCMI_GET_IT(IT) (((IT) == DCMI_IT_FRAME) || \
+                            ((IT) == DCMI_IT_OVF) || \
+                            ((IT) == DCMI_IT_ERR) || \
+                            ((IT) == DCMI_IT_VSYNC) || \
+                            ((IT) == DCMI_IT_LINE))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DCMI_Flags 
+  * @{
+  */ 
+/** 
+  * @brief   DCMI SR register  
+  */ 
+#define DCMI_FLAG_HSYNC     ((uint16_t)0x2001)
+#define DCMI_FLAG_VSYNC     ((uint16_t)0x2002)
+#define DCMI_FLAG_FNE       ((uint16_t)0x2004)
+/** 
+  * @brief   DCMI RISR register  
+  */ 
+#define DCMI_FLAG_FRAMERI    ((uint16_t)0x0001)
+#define DCMI_FLAG_OVFRI      ((uint16_t)0x0002)
+#define DCMI_FLAG_ERRRI      ((uint16_t)0x0004)
+#define DCMI_FLAG_VSYNCRI    ((uint16_t)0x0008)
+#define DCMI_FLAG_LINERI     ((uint16_t)0x0010)
+/** 
+  * @brief   DCMI MISR register  
+  */ 
+#define DCMI_FLAG_FRAMEMI    ((uint16_t)0x1001)
+#define DCMI_FLAG_OVFMI      ((uint16_t)0x1002)
+#define DCMI_FLAG_ERRMI      ((uint16_t)0x1004)
+#define DCMI_FLAG_VSYNCMI    ((uint16_t)0x1008)
+#define DCMI_FLAG_LINEMI     ((uint16_t)0x1010)
+#define IS_DCMI_GET_FLAG(FLAG) (((FLAG) == DCMI_FLAG_HSYNC) || \
+                                ((FLAG) == DCMI_FLAG_VSYNC) || \
+                                ((FLAG) == DCMI_FLAG_FNE) || \
+                                ((FLAG) == DCMI_FLAG_FRAMERI) || \
+                                ((FLAG) == DCMI_FLAG_OVFRI) || \
+                                ((FLAG) == DCMI_FLAG_ERRRI) || \
+                                ((FLAG) == DCMI_FLAG_VSYNCRI) || \
+                                ((FLAG) == DCMI_FLAG_LINERI) || \
+                                ((FLAG) == DCMI_FLAG_FRAMEMI) || \
+                                ((FLAG) == DCMI_FLAG_OVFMI) || \
+                                ((FLAG) == DCMI_FLAG_ERRMI) || \
+                                ((FLAG) == DCMI_FLAG_VSYNCMI) || \
+                                ((FLAG) == DCMI_FLAG_LINEMI))
+                                
+#define IS_DCMI_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFFE0) == 0x0000) && ((FLAG) != 0x0000))
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/*  Function used to set the DCMI configuration to the default reset state ****/ 
+void DCMI_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct);
+void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct);
+void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct);
+void DCMI_CROPCmd(FunctionalState NewState);
+void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct);
+void DCMI_JPEGCmd(FunctionalState NewState);
+
+/* Image capture functions ****************************************************/
+void DCMI_Cmd(FunctionalState NewState);
+void DCMI_CaptureCmd(FunctionalState NewState);
+uint32_t DCMI_ReadData(void);
+
+/* Interrupts and flags management functions **********************************/
+void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState);
+FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG);
+void DCMI_ClearFlag(uint16_t DCMI_FLAG);
+ITStatus DCMI_GetITStatus(uint16_t DCMI_IT);
+void DCMI_ClearITPendingBit(uint16_t DCMI_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_DCMI_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h
new file mode 100644
index 0000000000..e286a8739f
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_dma.h
@@ -0,0 +1,603 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dma.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the DMA firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************  
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_DMA_H
+#define __STM32F4xx_DMA_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup DMA
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  DMA Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t DMA_Channel;            /*!< Specifies the channel used for the specified stream. 
+                                        This parameter can be a value of @ref DMA_channel */
+ 
+  uint32_t DMA_PeripheralBaseAddr; /*!< Specifies the peripheral base address for DMAy Streamx. */
+
+  uint32_t DMA_Memory0BaseAddr;    /*!< Specifies the memory 0 base address for DMAy Streamx. 
+                                        This memory is the default memory used when double buffer mode is
+                                        not enabled. */
+
+  uint32_t DMA_DIR;                /*!< Specifies if the data will be transferred from memory to peripheral, 
+                                        from memory to memory or from peripheral to memory.
+                                        This parameter can be a value of @ref DMA_data_transfer_direction */
+
+  uint32_t DMA_BufferSize;         /*!< Specifies the buffer size, in data unit, of the specified Stream. 
+                                        The data unit is equal to the configuration set in DMA_PeripheralDataSize
+                                        or DMA_MemoryDataSize members depending in the transfer direction. */
+
+  uint32_t DMA_PeripheralInc;      /*!< Specifies whether the Peripheral address register should be incremented or not.
+                                        This parameter can be a value of @ref DMA_peripheral_incremented_mode */
+
+  uint32_t DMA_MemoryInc;          /*!< Specifies whether the memory address register should be incremented or not.
+                                        This parameter can be a value of @ref DMA_memory_incremented_mode */
+
+  uint32_t DMA_PeripheralDataSize; /*!< Specifies the Peripheral data width.
+                                        This parameter can be a value of @ref DMA_peripheral_data_size */
+
+  uint32_t DMA_MemoryDataSize;     /*!< Specifies the Memory data width.
+                                        This parameter can be a value of @ref DMA_memory_data_size */
+
+  uint32_t DMA_Mode;               /*!< Specifies the operation mode of the DMAy Streamx.
+                                        This parameter can be a value of @ref DMA_circular_normal_mode
+                                        @note The circular buffer mode cannot be used if the memory-to-memory
+                                              data transfer is configured on the selected Stream */
+
+  uint32_t DMA_Priority;           /*!< Specifies the software priority for the DMAy Streamx.
+                                        This parameter can be a value of @ref DMA_priority_level */
+
+  uint32_t DMA_FIFOMode;          /*!< Specifies if the FIFO mode or Direct mode will be used for the specified Stream.
+                                        This parameter can be a value of @ref DMA_fifo_direct_mode
+                                        @note The Direct mode (FIFO mode disabled) cannot be used if the 
+                                               memory-to-memory data transfer is configured on the selected Stream */
+
+  uint32_t DMA_FIFOThreshold;      /*!< Specifies the FIFO threshold level.
+                                        This parameter can be a value of @ref DMA_fifo_threshold_level */
+
+  uint32_t DMA_MemoryBurst;        /*!< Specifies the Burst transfer configuration for the memory transfers. 
+                                        It specifies the amount of data to be transferred in a single non interruptable 
+                                        transaction. This parameter can be a value of @ref DMA_memory_burst 
+                                        @note The burst mode is possible only if the address Increment mode is enabled. */
+
+  uint32_t DMA_PeripheralBurst;    /*!< Specifies the Burst transfer configuration for the peripheral transfers. 
+                                        It specifies the amount of data to be transferred in a single non interruptable 
+                                        transaction. This parameter can be a value of @ref DMA_peripheral_burst
+                                        @note The burst mode is possible only if the address Increment mode is enabled. */  
+}DMA_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup DMA_Exported_Constants
+  * @{
+  */
+
+#define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Stream0) || \
+                                   ((PERIPH) == DMA1_Stream1) || \
+                                   ((PERIPH) == DMA1_Stream2) || \
+                                   ((PERIPH) == DMA1_Stream3) || \
+                                   ((PERIPH) == DMA1_Stream4) || \
+                                   ((PERIPH) == DMA1_Stream5) || \
+                                   ((PERIPH) == DMA1_Stream6) || \
+                                   ((PERIPH) == DMA1_Stream7) || \
+                                   ((PERIPH) == DMA2_Stream0) || \
+                                   ((PERIPH) == DMA2_Stream1) || \
+                                   ((PERIPH) == DMA2_Stream2) || \
+                                   ((PERIPH) == DMA2_Stream3) || \
+                                   ((PERIPH) == DMA2_Stream4) || \
+                                   ((PERIPH) == DMA2_Stream5) || \
+                                   ((PERIPH) == DMA2_Stream6) || \
+                                   ((PERIPH) == DMA2_Stream7))
+
+#define IS_DMA_ALL_CONTROLLER(CONTROLLER) (((CONTROLLER) == DMA1) || \
+                                           ((CONTROLLER) == DMA2))
+
+/** @defgroup DMA_channel 
+  * @{
+  */ 
+#define DMA_Channel_0                     ((uint32_t)0x00000000)
+#define DMA_Channel_1                     ((uint32_t)0x02000000)
+#define DMA_Channel_2                     ((uint32_t)0x04000000)
+#define DMA_Channel_3                     ((uint32_t)0x06000000)
+#define DMA_Channel_4                     ((uint32_t)0x08000000)
+#define DMA_Channel_5                     ((uint32_t)0x0A000000)
+#define DMA_Channel_6                     ((uint32_t)0x0C000000)
+#define DMA_Channel_7                     ((uint32_t)0x0E000000)
+
+#define IS_DMA_CHANNEL(CHANNEL) (((CHANNEL) == DMA_Channel_0) || \
+                                 ((CHANNEL) == DMA_Channel_1) || \
+                                 ((CHANNEL) == DMA_Channel_2) || \
+                                 ((CHANNEL) == DMA_Channel_3) || \
+                                 ((CHANNEL) == DMA_Channel_4) || \
+                                 ((CHANNEL) == DMA_Channel_5) || \
+                                 ((CHANNEL) == DMA_Channel_6) || \
+                                 ((CHANNEL) == DMA_Channel_7))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_data_transfer_direction 
+  * @{
+  */ 
+#define DMA_DIR_PeripheralToMemory        ((uint32_t)0x00000000)
+#define DMA_DIR_MemoryToPeripheral        ((uint32_t)0x00000040) 
+#define DMA_DIR_MemoryToMemory            ((uint32_t)0x00000080)
+
+#define IS_DMA_DIRECTION(DIRECTION) (((DIRECTION) == DMA_DIR_PeripheralToMemory ) || \
+                                     ((DIRECTION) == DMA_DIR_MemoryToPeripheral)  || \
+                                     ((DIRECTION) == DMA_DIR_MemoryToMemory)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_data_buffer_size 
+  * @{
+  */ 
+#define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_peripheral_incremented_mode 
+  * @{
+  */ 
+#define DMA_PeripheralInc_Enable          ((uint32_t)0x00000200)
+#define DMA_PeripheralInc_Disable         ((uint32_t)0x00000000)
+
+#define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Enable) || \
+                                            ((STATE) == DMA_PeripheralInc_Disable))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_memory_incremented_mode 
+  * @{
+  */ 
+#define DMA_MemoryInc_Enable              ((uint32_t)0x00000400)
+#define DMA_MemoryInc_Disable             ((uint32_t)0x00000000)
+
+#define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Enable) || \
+                                        ((STATE) == DMA_MemoryInc_Disable))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_peripheral_data_size 
+  * @{
+  */ 
+#define DMA_PeripheralDataSize_Byte       ((uint32_t)0x00000000) 
+#define DMA_PeripheralDataSize_HalfWord   ((uint32_t)0x00000800) 
+#define DMA_PeripheralDataSize_Word       ((uint32_t)0x00001000)
+
+#define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte)  || \
+                                           ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
+                                           ((SIZE) == DMA_PeripheralDataSize_Word))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_memory_data_size 
+  * @{
+  */ 
+#define DMA_MemoryDataSize_Byte           ((uint32_t)0x00000000) 
+#define DMA_MemoryDataSize_HalfWord       ((uint32_t)0x00002000) 
+#define DMA_MemoryDataSize_Word           ((uint32_t)0x00004000)
+
+#define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte)  || \
+                                       ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
+                                       ((SIZE) == DMA_MemoryDataSize_Word ))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_circular_normal_mode 
+  * @{
+  */ 
+#define DMA_Mode_Normal                   ((uint32_t)0x00000000) 
+#define DMA_Mode_Circular                 ((uint32_t)0x00000100)
+
+#define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal ) || \
+                           ((MODE) == DMA_Mode_Circular)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_priority_level 
+  * @{
+  */ 
+#define DMA_Priority_Low                  ((uint32_t)0x00000000)
+#define DMA_Priority_Medium               ((uint32_t)0x00010000) 
+#define DMA_Priority_High                 ((uint32_t)0x00020000)
+#define DMA_Priority_VeryHigh             ((uint32_t)0x00030000)
+
+#define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_Low )   || \
+                                   ((PRIORITY) == DMA_Priority_Medium) || \
+                                   ((PRIORITY) == DMA_Priority_High)   || \
+                                   ((PRIORITY) == DMA_Priority_VeryHigh)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_fifo_direct_mode 
+  * @{
+  */ 
+#define DMA_FIFOMode_Disable              ((uint32_t)0x00000000) 
+#define DMA_FIFOMode_Enable               ((uint32_t)0x00000004)
+
+#define IS_DMA_FIFO_MODE_STATE(STATE) (((STATE) == DMA_FIFOMode_Disable ) || \
+                                       ((STATE) == DMA_FIFOMode_Enable)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_fifo_threshold_level 
+  * @{
+  */ 
+#define DMA_FIFOThreshold_1QuarterFull    ((uint32_t)0x00000000)
+#define DMA_FIFOThreshold_HalfFull        ((uint32_t)0x00000001) 
+#define DMA_FIFOThreshold_3QuartersFull   ((uint32_t)0x00000002)
+#define DMA_FIFOThreshold_Full            ((uint32_t)0x00000003)
+
+#define IS_DMA_FIFO_THRESHOLD(THRESHOLD) (((THRESHOLD) == DMA_FIFOThreshold_1QuarterFull ) || \
+                                          ((THRESHOLD) == DMA_FIFOThreshold_HalfFull)      || \
+                                          ((THRESHOLD) == DMA_FIFOThreshold_3QuartersFull) || \
+                                          ((THRESHOLD) == DMA_FIFOThreshold_Full)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_memory_burst 
+  * @{
+  */ 
+#define DMA_MemoryBurst_Single            ((uint32_t)0x00000000)
+#define DMA_MemoryBurst_INC4              ((uint32_t)0x00800000)  
+#define DMA_MemoryBurst_INC8              ((uint32_t)0x01000000)
+#define DMA_MemoryBurst_INC16             ((uint32_t)0x01800000)
+
+#define IS_DMA_MEMORY_BURST(BURST) (((BURST) == DMA_MemoryBurst_Single) || \
+                                    ((BURST) == DMA_MemoryBurst_INC4)  || \
+                                    ((BURST) == DMA_MemoryBurst_INC8)  || \
+                                    ((BURST) == DMA_MemoryBurst_INC16))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_peripheral_burst 
+  * @{
+  */ 
+#define DMA_PeripheralBurst_Single        ((uint32_t)0x00000000)
+#define DMA_PeripheralBurst_INC4          ((uint32_t)0x00200000)  
+#define DMA_PeripheralBurst_INC8          ((uint32_t)0x00400000)
+#define DMA_PeripheralBurst_INC16         ((uint32_t)0x00600000)
+
+#define IS_DMA_PERIPHERAL_BURST(BURST) (((BURST) == DMA_PeripheralBurst_Single) || \
+                                        ((BURST) == DMA_PeripheralBurst_INC4)  || \
+                                        ((BURST) == DMA_PeripheralBurst_INC8)  || \
+                                        ((BURST) == DMA_PeripheralBurst_INC16))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_fifo_status_level 
+  * @{
+  */
+#define DMA_FIFOStatus_Less1QuarterFull   ((uint32_t)0x00000000 << 3)
+#define DMA_FIFOStatus_1QuarterFull       ((uint32_t)0x00000001 << 3)
+#define DMA_FIFOStatus_HalfFull           ((uint32_t)0x00000002 << 3) 
+#define DMA_FIFOStatus_3QuartersFull      ((uint32_t)0x00000003 << 3)
+#define DMA_FIFOStatus_Empty              ((uint32_t)0x00000004 << 3)
+#define DMA_FIFOStatus_Full               ((uint32_t)0x00000005 << 3)
+
+#define IS_DMA_FIFO_STATUS(STATUS) (((STATUS) == DMA_FIFOStatus_Less1QuarterFull ) || \
+                                    ((STATUS) == DMA_FIFOStatus_HalfFull)          || \
+                                    ((STATUS) == DMA_FIFOStatus_1QuarterFull)      || \
+                                    ((STATUS) == DMA_FIFOStatus_3QuartersFull)     || \
+                                    ((STATUS) == DMA_FIFOStatus_Full)              || \
+                                    ((STATUS) == DMA_FIFOStatus_Empty)) 
+/**
+  * @}
+  */ 
+
+/** @defgroup DMA_flags_definition 
+  * @{
+  */
+#define DMA_FLAG_FEIF0                    ((uint32_t)0x10800001)
+#define DMA_FLAG_DMEIF0                   ((uint32_t)0x10800004)
+#define DMA_FLAG_TEIF0                    ((uint32_t)0x10000008)
+#define DMA_FLAG_HTIF0                    ((uint32_t)0x10000010)
+#define DMA_FLAG_TCIF0                    ((uint32_t)0x10000020)
+#define DMA_FLAG_FEIF1                    ((uint32_t)0x10000040)
+#define DMA_FLAG_DMEIF1                   ((uint32_t)0x10000100)
+#define DMA_FLAG_TEIF1                    ((uint32_t)0x10000200)
+#define DMA_FLAG_HTIF1                    ((uint32_t)0x10000400)
+#define DMA_FLAG_TCIF1                    ((uint32_t)0x10000800)
+#define DMA_FLAG_FEIF2                    ((uint32_t)0x10010000)
+#define DMA_FLAG_DMEIF2                   ((uint32_t)0x10040000)
+#define DMA_FLAG_TEIF2                    ((uint32_t)0x10080000)
+#define DMA_FLAG_HTIF2                    ((uint32_t)0x10100000)
+#define DMA_FLAG_TCIF2                    ((uint32_t)0x10200000)
+#define DMA_FLAG_FEIF3                    ((uint32_t)0x10400000)
+#define DMA_FLAG_DMEIF3                   ((uint32_t)0x11000000)
+#define DMA_FLAG_TEIF3                    ((uint32_t)0x12000000)
+#define DMA_FLAG_HTIF3                    ((uint32_t)0x14000000)
+#define DMA_FLAG_TCIF3                    ((uint32_t)0x18000000)
+#define DMA_FLAG_FEIF4                    ((uint32_t)0x20000001)
+#define DMA_FLAG_DMEIF4                   ((uint32_t)0x20000004)
+#define DMA_FLAG_TEIF4                    ((uint32_t)0x20000008)
+#define DMA_FLAG_HTIF4                    ((uint32_t)0x20000010)
+#define DMA_FLAG_TCIF4                    ((uint32_t)0x20000020)
+#define DMA_FLAG_FEIF5                    ((uint32_t)0x20000040)
+#define DMA_FLAG_DMEIF5                   ((uint32_t)0x20000100)
+#define DMA_FLAG_TEIF5                    ((uint32_t)0x20000200)
+#define DMA_FLAG_HTIF5                    ((uint32_t)0x20000400)
+#define DMA_FLAG_TCIF5                    ((uint32_t)0x20000800)
+#define DMA_FLAG_FEIF6                    ((uint32_t)0x20010000)
+#define DMA_FLAG_DMEIF6                   ((uint32_t)0x20040000)
+#define DMA_FLAG_TEIF6                    ((uint32_t)0x20080000)
+#define DMA_FLAG_HTIF6                    ((uint32_t)0x20100000)
+#define DMA_FLAG_TCIF6                    ((uint32_t)0x20200000)
+#define DMA_FLAG_FEIF7                    ((uint32_t)0x20400000)
+#define DMA_FLAG_DMEIF7                   ((uint32_t)0x21000000)
+#define DMA_FLAG_TEIF7                    ((uint32_t)0x22000000)
+#define DMA_FLAG_HTIF7                    ((uint32_t)0x24000000)
+#define DMA_FLAG_TCIF7                    ((uint32_t)0x28000000)
+
+#define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0x30000000) != 0x30000000) && (((FLAG) & 0x30000000) != 0) && \
+                                 (((FLAG) & 0xC082F082) == 0x00) && ((FLAG) != 0x00))
+
+#define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA_FLAG_TCIF0)  || ((FLAG) == DMA_FLAG_HTIF0)  || \
+                               ((FLAG) == DMA_FLAG_TEIF0)  || ((FLAG) == DMA_FLAG_DMEIF0) || \
+                               ((FLAG) == DMA_FLAG_FEIF0)  || ((FLAG) == DMA_FLAG_TCIF1)  || \
+                               ((FLAG) == DMA_FLAG_HTIF1)  || ((FLAG) == DMA_FLAG_TEIF1)  || \
+                               ((FLAG) == DMA_FLAG_DMEIF1) || ((FLAG) == DMA_FLAG_FEIF1)  || \
+                               ((FLAG) == DMA_FLAG_TCIF2)  || ((FLAG) == DMA_FLAG_HTIF2)  || \
+                               ((FLAG) == DMA_FLAG_TEIF2)  || ((FLAG) == DMA_FLAG_DMEIF2) || \
+                               ((FLAG) == DMA_FLAG_FEIF2)  || ((FLAG) == DMA_FLAG_TCIF3)  || \
+                               ((FLAG) == DMA_FLAG_HTIF3)  || ((FLAG) == DMA_FLAG_TEIF3)  || \
+                               ((FLAG) == DMA_FLAG_DMEIF3) || ((FLAG) == DMA_FLAG_FEIF3)  || \
+                               ((FLAG) == DMA_FLAG_TCIF4)  || ((FLAG) == DMA_FLAG_HTIF4)  || \
+                               ((FLAG) == DMA_FLAG_TEIF4)  || ((FLAG) == DMA_FLAG_DMEIF4) || \
+                               ((FLAG) == DMA_FLAG_FEIF4)  || ((FLAG) == DMA_FLAG_TCIF5)  || \
+                               ((FLAG) == DMA_FLAG_HTIF5)  || ((FLAG) == DMA_FLAG_TEIF5)  || \
+                               ((FLAG) == DMA_FLAG_DMEIF5) || ((FLAG) == DMA_FLAG_FEIF5)  || \
+                               ((FLAG) == DMA_FLAG_TCIF6)  || ((FLAG) == DMA_FLAG_HTIF6)  || \
+                               ((FLAG) == DMA_FLAG_TEIF6)  || ((FLAG) == DMA_FLAG_DMEIF6) || \
+                               ((FLAG) == DMA_FLAG_FEIF6)  || ((FLAG) == DMA_FLAG_TCIF7)  || \
+                               ((FLAG) == DMA_FLAG_HTIF7)  || ((FLAG) == DMA_FLAG_TEIF7)  || \
+                               ((FLAG) == DMA_FLAG_DMEIF7) || ((FLAG) == DMA_FLAG_FEIF7))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_interrupt_enable_definitions 
+  * @{
+  */ 
+#define DMA_IT_TC                         ((uint32_t)0x00000010)
+#define DMA_IT_HT                         ((uint32_t)0x00000008)
+#define DMA_IT_TE                         ((uint32_t)0x00000004)
+#define DMA_IT_DME                        ((uint32_t)0x00000002)
+#define DMA_IT_FE                         ((uint32_t)0x00000080)
+
+#define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFF61) == 0x00) && ((IT) != 0x00))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_interrupts_definitions 
+  * @{
+  */ 
+#define DMA_IT_FEIF0                      ((uint32_t)0x90000001)
+#define DMA_IT_DMEIF0                     ((uint32_t)0x10001004)
+#define DMA_IT_TEIF0                      ((uint32_t)0x10002008)
+#define DMA_IT_HTIF0                      ((uint32_t)0x10004010)
+#define DMA_IT_TCIF0                      ((uint32_t)0x10008020)
+#define DMA_IT_FEIF1                      ((uint32_t)0x90000040)
+#define DMA_IT_DMEIF1                     ((uint32_t)0x10001100)
+#define DMA_IT_TEIF1                      ((uint32_t)0x10002200)
+#define DMA_IT_HTIF1                      ((uint32_t)0x10004400)
+#define DMA_IT_TCIF1                      ((uint32_t)0x10008800)
+#define DMA_IT_FEIF2                      ((uint32_t)0x90010000)
+#define DMA_IT_DMEIF2                     ((uint32_t)0x10041000)
+#define DMA_IT_TEIF2                      ((uint32_t)0x10082000)
+#define DMA_IT_HTIF2                      ((uint32_t)0x10104000)
+#define DMA_IT_TCIF2                      ((uint32_t)0x10208000)
+#define DMA_IT_FEIF3                      ((uint32_t)0x90400000)
+#define DMA_IT_DMEIF3                     ((uint32_t)0x11001000)
+#define DMA_IT_TEIF3                      ((uint32_t)0x12002000)
+#define DMA_IT_HTIF3                      ((uint32_t)0x14004000)
+#define DMA_IT_TCIF3                      ((uint32_t)0x18008000)
+#define DMA_IT_FEIF4                      ((uint32_t)0xA0000001)
+#define DMA_IT_DMEIF4                     ((uint32_t)0x20001004)
+#define DMA_IT_TEIF4                      ((uint32_t)0x20002008)
+#define DMA_IT_HTIF4                      ((uint32_t)0x20004010)
+#define DMA_IT_TCIF4                      ((uint32_t)0x20008020)
+#define DMA_IT_FEIF5                      ((uint32_t)0xA0000040)
+#define DMA_IT_DMEIF5                     ((uint32_t)0x20001100)
+#define DMA_IT_TEIF5                      ((uint32_t)0x20002200)
+#define DMA_IT_HTIF5                      ((uint32_t)0x20004400)
+#define DMA_IT_TCIF5                      ((uint32_t)0x20008800)
+#define DMA_IT_FEIF6                      ((uint32_t)0xA0010000)
+#define DMA_IT_DMEIF6                     ((uint32_t)0x20041000)
+#define DMA_IT_TEIF6                      ((uint32_t)0x20082000)
+#define DMA_IT_HTIF6                      ((uint32_t)0x20104000)
+#define DMA_IT_TCIF6                      ((uint32_t)0x20208000)
+#define DMA_IT_FEIF7                      ((uint32_t)0xA0400000)
+#define DMA_IT_DMEIF7                     ((uint32_t)0x21001000)
+#define DMA_IT_TEIF7                      ((uint32_t)0x22002000)
+#define DMA_IT_HTIF7                      ((uint32_t)0x24004000)
+#define DMA_IT_TCIF7                      ((uint32_t)0x28008000)
+
+#define IS_DMA_CLEAR_IT(IT) ((((IT) & 0x30000000) != 0x30000000) && \
+                             (((IT) & 0x30000000) != 0) && ((IT) != 0x00) && \
+                             (((IT) & 0x40820082) == 0x00))
+
+#define IS_DMA_GET_IT(IT) (((IT) == DMA_IT_TCIF0) || ((IT) == DMA_IT_HTIF0)  || \
+                           ((IT) == DMA_IT_TEIF0) || ((IT) == DMA_IT_DMEIF0) || \
+                           ((IT) == DMA_IT_FEIF0) || ((IT) == DMA_IT_TCIF1)  || \
+                           ((IT) == DMA_IT_HTIF1) || ((IT) == DMA_IT_TEIF1)  || \
+                           ((IT) == DMA_IT_DMEIF1)|| ((IT) == DMA_IT_FEIF1)  || \
+                           ((IT) == DMA_IT_TCIF2) || ((IT) == DMA_IT_HTIF2)  || \
+                           ((IT) == DMA_IT_TEIF2) || ((IT) == DMA_IT_DMEIF2) || \
+                           ((IT) == DMA_IT_FEIF2) || ((IT) == DMA_IT_TCIF3)  || \
+                           ((IT) == DMA_IT_HTIF3) || ((IT) == DMA_IT_TEIF3)  || \
+                           ((IT) == DMA_IT_DMEIF3)|| ((IT) == DMA_IT_FEIF3)  || \
+                           ((IT) == DMA_IT_TCIF4) || ((IT) == DMA_IT_HTIF4)  || \
+                           ((IT) == DMA_IT_TEIF4) || ((IT) == DMA_IT_DMEIF4) || \
+                           ((IT) == DMA_IT_FEIF4) || ((IT) == DMA_IT_TCIF5)  || \
+                           ((IT) == DMA_IT_HTIF5) || ((IT) == DMA_IT_TEIF5)  || \
+                           ((IT) == DMA_IT_DMEIF5)|| ((IT) == DMA_IT_FEIF5)  || \
+                           ((IT) == DMA_IT_TCIF6) || ((IT) == DMA_IT_HTIF6)  || \
+                           ((IT) == DMA_IT_TEIF6) || ((IT) == DMA_IT_DMEIF6) || \
+                           ((IT) == DMA_IT_FEIF6) || ((IT) == DMA_IT_TCIF7)  || \
+                           ((IT) == DMA_IT_HTIF7) || ((IT) == DMA_IT_TEIF7)  || \
+                           ((IT) == DMA_IT_DMEIF7)|| ((IT) == DMA_IT_FEIF7))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_peripheral_increment_offset 
+  * @{
+  */ 
+#define DMA_PINCOS_Psize                  ((uint32_t)0x00000000)
+#define DMA_PINCOS_WordAligned            ((uint32_t)0x00008000)
+
+#define IS_DMA_PINCOS_SIZE(SIZE) (((SIZE) == DMA_PINCOS_Psize) || \
+                                  ((SIZE) == DMA_PINCOS_WordAligned))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_flow_controller_definitions 
+  * @{
+  */ 
+#define DMA_FlowCtrl_Memory               ((uint32_t)0x00000000)
+#define DMA_FlowCtrl_Peripheral           ((uint32_t)0x00000020)
+
+#define IS_DMA_FLOW_CTRL(CTRL) (((CTRL) == DMA_FlowCtrl_Memory) || \
+                                ((CTRL) == DMA_FlowCtrl_Peripheral))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup DMA_memory_targets_definitions 
+  * @{
+  */ 
+#define DMA_Memory_0                      ((uint32_t)0x00000000)
+#define DMA_Memory_1                      ((uint32_t)0x00080000)
+
+#define IS_DMA_CURRENT_MEM(MEM) (((MEM) == DMA_Memory_0) || ((MEM) == DMA_Memory_1))
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/*  Function used to set the DMA configuration to the default reset state *****/ 
+void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx);
+
+/* Initialization and Configuration functions *********************************/
+void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct);
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct);
+void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
+
+/* Optional Configuration functions *******************************************/
+void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos);
+void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl);
+
+/* Data Counter functions *****************************************************/
+void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
+uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
+
+/* Double Buffer mode functions ***********************************************/
+void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
+                                uint32_t DMA_CurrentMemory);
+void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
+void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
+                            uint32_t DMA_MemoryTarget);
+uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
+
+/* Interrupts and flags management functions **********************************/
+FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx);
+uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx);
+FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
+void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
+void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
+ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
+void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_DMA_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h
new file mode 100644
index 0000000000..dac7012511
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_exti.h
@@ -0,0 +1,177 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_exti.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the EXTI firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_EXTI_H
+#define __STM32F4xx_EXTI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup EXTI
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  EXTI mode enumeration  
+  */
+
+typedef enum
+{
+  EXTI_Mode_Interrupt = 0x00,
+  EXTI_Mode_Event = 0x04
+}EXTIMode_TypeDef;
+
+#define IS_EXTI_MODE(MODE) (((MODE) == EXTI_Mode_Interrupt) || ((MODE) == EXTI_Mode_Event))
+
+/** 
+  * @brief  EXTI Trigger enumeration  
+  */
+
+typedef enum
+{
+  EXTI_Trigger_Rising = 0x08,
+  EXTI_Trigger_Falling = 0x0C,  
+  EXTI_Trigger_Rising_Falling = 0x10
+}EXTITrigger_TypeDef;
+
+#define IS_EXTI_TRIGGER(TRIGGER) (((TRIGGER) == EXTI_Trigger_Rising) || \
+                                  ((TRIGGER) == EXTI_Trigger_Falling) || \
+                                  ((TRIGGER) == EXTI_Trigger_Rising_Falling))
+/** 
+  * @brief  EXTI Init Structure definition  
+  */
+
+typedef struct
+{
+  uint32_t EXTI_Line;               /*!< Specifies the EXTI lines to be enabled or disabled.
+                                         This parameter can be any combination value of @ref EXTI_Lines */
+   
+  EXTIMode_TypeDef EXTI_Mode;       /*!< Specifies the mode for the EXTI lines.
+                                         This parameter can be a value of @ref EXTIMode_TypeDef */
+
+  EXTITrigger_TypeDef EXTI_Trigger; /*!< Specifies the trigger signal active edge for the EXTI lines.
+                                         This parameter can be a value of @ref EXTITrigger_TypeDef */
+
+  FunctionalState EXTI_LineCmd;     /*!< Specifies the new state of the selected EXTI lines.
+                                         This parameter can be set either to ENABLE or DISABLE */ 
+}EXTI_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup EXTI_Exported_Constants
+  * @{
+  */
+
+/** @defgroup EXTI_Lines 
+  * @{
+  */
+
+#define EXTI_Line0       ((uint32_t)0x00001)     /*!< External interrupt line 0 */
+#define EXTI_Line1       ((uint32_t)0x00002)     /*!< External interrupt line 1 */
+#define EXTI_Line2       ((uint32_t)0x00004)     /*!< External interrupt line 2 */
+#define EXTI_Line3       ((uint32_t)0x00008)     /*!< External interrupt line 3 */
+#define EXTI_Line4       ((uint32_t)0x00010)     /*!< External interrupt line 4 */
+#define EXTI_Line5       ((uint32_t)0x00020)     /*!< External interrupt line 5 */
+#define EXTI_Line6       ((uint32_t)0x00040)     /*!< External interrupt line 6 */
+#define EXTI_Line7       ((uint32_t)0x00080)     /*!< External interrupt line 7 */
+#define EXTI_Line8       ((uint32_t)0x00100)     /*!< External interrupt line 8 */
+#define EXTI_Line9       ((uint32_t)0x00200)     /*!< External interrupt line 9 */
+#define EXTI_Line10      ((uint32_t)0x00400)     /*!< External interrupt line 10 */
+#define EXTI_Line11      ((uint32_t)0x00800)     /*!< External interrupt line 11 */
+#define EXTI_Line12      ((uint32_t)0x01000)     /*!< External interrupt line 12 */
+#define EXTI_Line13      ((uint32_t)0x02000)     /*!< External interrupt line 13 */
+#define EXTI_Line14      ((uint32_t)0x04000)     /*!< External interrupt line 14 */
+#define EXTI_Line15      ((uint32_t)0x08000)     /*!< External interrupt line 15 */
+#define EXTI_Line16      ((uint32_t)0x10000)     /*!< External interrupt line 16 Connected to the PVD Output */
+#define EXTI_Line17      ((uint32_t)0x20000)     /*!< External interrupt line 17 Connected to the RTC Alarm event */
+#define EXTI_Line18      ((uint32_t)0x40000)     /*!< External interrupt line 18 Connected to the USB OTG FS Wakeup from suspend event */                                    
+#define EXTI_Line19      ((uint32_t)0x80000)     /*!< External interrupt line 19 Connected to the Ethernet Wakeup event */
+#define EXTI_Line20      ((uint32_t)0x00100000)  /*!< External interrupt line 20 Connected to the USB OTG HS (configured in FS) Wakeup event  */
+#define EXTI_Line21      ((uint32_t)0x00200000)  /*!< External interrupt line 21 Connected to the RTC Tamper and Time Stamp events */                                               
+#define EXTI_Line22      ((uint32_t)0x00400000)  /*!< External interrupt line 22 Connected to the RTC Wakeup event */                                               
+                                          
+#define IS_EXTI_LINE(LINE) ((((LINE) & (uint32_t)0xFF800000) == 0x00) && ((LINE) != (uint16_t)0x00))
+
+#define IS_GET_EXTI_LINE(LINE) (((LINE) == EXTI_Line0) || ((LINE) == EXTI_Line1) || \
+                                ((LINE) == EXTI_Line2) || ((LINE) == EXTI_Line3) || \
+                                ((LINE) == EXTI_Line4) || ((LINE) == EXTI_Line5) || \
+                                ((LINE) == EXTI_Line6) || ((LINE) == EXTI_Line7) || \
+                                ((LINE) == EXTI_Line8) || ((LINE) == EXTI_Line9) || \
+                                ((LINE) == EXTI_Line10) || ((LINE) == EXTI_Line11) || \
+                                ((LINE) == EXTI_Line12) || ((LINE) == EXTI_Line13) || \
+                                ((LINE) == EXTI_Line14) || ((LINE) == EXTI_Line15) || \
+                                ((LINE) == EXTI_Line16) || ((LINE) == EXTI_Line17) || \
+                                ((LINE) == EXTI_Line18) || ((LINE) == EXTI_Line19) || \
+                                ((LINE) == EXTI_Line20) || ((LINE) == EXTI_Line21) ||\
+                                ((LINE) == EXTI_Line22))
+                    
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/*  Function used to set the EXTI configuration to the default reset state *****/
+void EXTI_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct);
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line);
+void EXTI_ClearFlag(uint32_t EXTI_Line);
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line);
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_EXTI_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h
new file mode 100644
index 0000000000..f3a5b6ad75
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_flash.h
@@ -0,0 +1,334 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_flash.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the FLASH 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_FLASH_H
+#define __STM32F4xx_FLASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup FLASH
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/** 
+  * @brief FLASH Status  
+  */ 
+typedef enum
+{ 
+  FLASH_BUSY = 1,
+  FLASH_ERROR_PGS,
+  FLASH_ERROR_PGP,
+  FLASH_ERROR_PGA,
+  FLASH_ERROR_WRP,
+  FLASH_ERROR_PROGRAM,
+  FLASH_ERROR_OPERATION,
+  FLASH_COMPLETE
+}FLASH_Status;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FLASH_Exported_Constants
+  * @{
+  */  
+
+/** @defgroup Flash_Latency 
+  * @{
+  */ 
+#define FLASH_Latency_0                ((uint8_t)0x0000)  /*!< FLASH Zero Latency cycle */
+#define FLASH_Latency_1                ((uint8_t)0x0001)  /*!< FLASH One Latency cycle */
+#define FLASH_Latency_2                ((uint8_t)0x0002)  /*!< FLASH Two Latency cycles */
+#define FLASH_Latency_3                ((uint8_t)0x0003)  /*!< FLASH Three Latency cycles */
+#define FLASH_Latency_4                ((uint8_t)0x0004)  /*!< FLASH Four Latency cycles */
+#define FLASH_Latency_5                ((uint8_t)0x0005)  /*!< FLASH Five Latency cycles */
+#define FLASH_Latency_6                ((uint8_t)0x0006)  /*!< FLASH Six Latency cycles */
+#define FLASH_Latency_7                ((uint8_t)0x0007)  /*!< FLASH Seven Latency cycles */
+
+#define IS_FLASH_LATENCY(LATENCY) (((LATENCY) == FLASH_Latency_0) || \
+                                   ((LATENCY) == FLASH_Latency_1) || \
+                                   ((LATENCY) == FLASH_Latency_2) || \
+                                   ((LATENCY) == FLASH_Latency_3) || \
+                                   ((LATENCY) == FLASH_Latency_4) || \
+                                   ((LATENCY) == FLASH_Latency_5) || \
+                                   ((LATENCY) == FLASH_Latency_6) || \
+                                   ((LATENCY) == FLASH_Latency_7))
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Voltage_Range 
+  * @{
+  */ 
+#define VoltageRange_1        ((uint8_t)0x00)  /*!< Device operating range: 1.8V to 2.1V */
+#define VoltageRange_2        ((uint8_t)0x01)  /*!= 0x08000000) && ((ADDRESS) < 0x080FFFFF)) ||\
+                                   (((ADDRESS) >= 0x1FFF7800) && ((ADDRESS) < 0x1FFF7A0F)))  
+/**
+  * @}
+  */ 
+
+/** @defgroup Option_Bytes_Write_Protection 
+  * @{
+  */ 
+#define OB_WRP_Sector_0       ((uint32_t)0x00000001) /*!< Write protection of Sector0 */
+#define OB_WRP_Sector_1       ((uint32_t)0x00000002) /*!< Write protection of Sector1 */
+#define OB_WRP_Sector_2       ((uint32_t)0x00000004) /*!< Write protection of Sector2 */
+#define OB_WRP_Sector_3       ((uint32_t)0x00000008) /*!< Write protection of Sector3 */
+#define OB_WRP_Sector_4       ((uint32_t)0x00000010) /*!< Write protection of Sector4 */
+#define OB_WRP_Sector_5       ((uint32_t)0x00000020) /*!< Write protection of Sector5 */
+#define OB_WRP_Sector_6       ((uint32_t)0x00000040) /*!< Write protection of Sector6 */
+#define OB_WRP_Sector_7       ((uint32_t)0x00000080) /*!< Write protection of Sector7 */
+#define OB_WRP_Sector_8       ((uint32_t)0x00000100) /*!< Write protection of Sector8 */
+#define OB_WRP_Sector_9       ((uint32_t)0x00000200) /*!< Write protection of Sector9 */
+#define OB_WRP_Sector_10      ((uint32_t)0x00000400) /*!< Write protection of Sector10 */
+#define OB_WRP_Sector_11      ((uint32_t)0x00000800) /*!< Write protection of Sector11 */
+#define OB_WRP_Sector_All     ((uint32_t)0x00000FFF) /*!< Write protection of all Sectors */
+
+#define IS_OB_WRP(SECTOR)((((SECTOR) & (uint32_t)0xFFFFF000) == 0x00000000) && ((SECTOR) != 0x00000000))
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Option_Bytes_Read_Protection 
+  * @{
+  */
+#define OB_RDP_Level_0   ((uint8_t)0xAA)
+#define OB_RDP_Level_1   ((uint8_t)0x55)
+/*#define OB_RDP_Level_2   ((uint8_t)0xCC)*/ /*!< Warning: When enabling read protection level 2 
+                                                  it's no more possible to go back to level 1 or 0 */
+#define IS_OB_RDP(LEVEL) (((LEVEL) == OB_RDP_Level_0)||\
+                          ((LEVEL) == OB_RDP_Level_1))/*||\
+                          ((LEVEL) == OB_RDP_Level_2))*/
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Option_Bytes_IWatchdog 
+  * @{
+  */ 
+#define OB_IWDG_SW                     ((uint8_t)0x20)  /*!< Software IWDG selected */
+#define OB_IWDG_HW                     ((uint8_t)0x00)  /*!< Hardware IWDG selected */
+#define IS_OB_IWDG_SOURCE(SOURCE) (((SOURCE) == OB_IWDG_SW) || ((SOURCE) == OB_IWDG_HW))
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Option_Bytes_nRST_STOP 
+  * @{
+  */ 
+#define OB_STOP_NoRST                  ((uint8_t)0x40) /*!< No reset generated when entering in STOP */
+#define OB_STOP_RST                    ((uint8_t)0x00) /*!< Reset generated when entering in STOP */
+#define IS_OB_STOP_SOURCE(SOURCE) (((SOURCE) == OB_STOP_NoRST) || ((SOURCE) == OB_STOP_RST))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup FLASH_Option_Bytes_nRST_STDBY 
+  * @{
+  */ 
+#define OB_STDBY_NoRST                 ((uint8_t)0x80) /*!< No reset generated when entering in STANDBY */
+#define OB_STDBY_RST                   ((uint8_t)0x00) /*!< Reset generated when entering in STANDBY */
+#define IS_OB_STDBY_SOURCE(SOURCE) (((SOURCE) == OB_STDBY_NoRST) || ((SOURCE) == OB_STDBY_RST))
+/**
+  * @}
+  */
+  
+/** @defgroup FLASH_BOR_Reset_Level 
+  * @{
+  */  
+#define OB_BOR_LEVEL3          ((uint8_t)0x00)  /*!< Supply voltage ranges from 2.70 to 3.60 V */
+#define OB_BOR_LEVEL2          ((uint8_t)0x04)  /*!< Supply voltage ranges from 2.40 to 2.70 V */
+#define OB_BOR_LEVEL1          ((uint8_t)0x08)  /*!< Supply voltage ranges from 2.10 to 2.40 V */
+#define OB_BOR_OFF             ((uint8_t)0x0C)  /*!< Supply voltage ranges from 1.62 to 2.10 V */
+#define IS_OB_BOR(LEVEL) (((LEVEL) == OB_BOR_LEVEL1) || ((LEVEL) == OB_BOR_LEVEL2) ||\
+                          ((LEVEL) == OB_BOR_LEVEL3) || ((LEVEL) == OB_BOR_OFF))
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Interrupts 
+  * @{
+  */ 
+#define FLASH_IT_EOP                   ((uint32_t)0x01000000)  /*!< End of FLASH Operation Interrupt source */
+#define FLASH_IT_ERR                   ((uint32_t)0x02000000)  /*!< Error Interrupt source */
+#define IS_FLASH_IT(IT) ((((IT) & (uint32_t)0xFCFFFFFF) == 0x00000000) && ((IT) != 0x00000000))
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Flags 
+  * @{
+  */ 
+#define FLASH_FLAG_EOP                 ((uint32_t)0x00000001)  /*!< FLASH End of Operation flag */
+#define FLASH_FLAG_OPERR               ((uint32_t)0x00000002)  /*!< FLASH operation Error flag */
+#define FLASH_FLAG_WRPERR              ((uint32_t)0x00000010)  /*!< FLASH Write protected error flag */
+#define FLASH_FLAG_PGAERR              ((uint32_t)0x00000020)  /*!< FLASH Programming Alignment error flag */
+#define FLASH_FLAG_PGPERR              ((uint32_t)0x00000040)  /*!< FLASH Programming Parallelism error flag  */
+#define FLASH_FLAG_PGSERR              ((uint32_t)0x00000080)  /*!< FLASH Programming Sequence error flag  */
+#define FLASH_FLAG_BSY                 ((uint32_t)0x00010000)  /*!< FLASH Busy flag */ 
+#define IS_FLASH_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFF0C) == 0x00000000) && ((FLAG) != 0x00000000))
+#define IS_FLASH_GET_FLAG(FLAG)  (((FLAG) == FLASH_FLAG_EOP) || ((FLAG) == FLASH_FLAG_OPERR) || \
+                                  ((FLAG) == FLASH_FLAG_WRPERR) || ((FLAG) == FLASH_FLAG_PGAERR) || \
+                                  ((FLAG) == FLASH_FLAG_PGPERR) || ((FLAG) == FLASH_FLAG_PGSERR) || \
+                                  ((FLAG) == FLASH_FLAG_BSY))
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Program_Parallelism   
+  * @{
+  */
+#define FLASH_PSIZE_BYTE           ((uint32_t)0x00000000)
+#define FLASH_PSIZE_HALF_WORD      ((uint32_t)0x00000100)
+#define FLASH_PSIZE_WORD           ((uint32_t)0x00000200)
+#define FLASH_PSIZE_DOUBLE_WORD    ((uint32_t)0x00000300)
+#define CR_PSIZE_MASK              ((uint32_t)0xFFFFFCFF)
+/**
+  * @}
+  */ 
+
+/** @defgroup FLASH_Keys 
+  * @{
+  */ 
+#define RDP_KEY                  ((uint16_t)0x00A5)
+#define FLASH_KEY1               ((uint32_t)0x45670123)
+#define FLASH_KEY2               ((uint32_t)0xCDEF89AB)
+#define FLASH_OPT_KEY1           ((uint32_t)0x08192A3B)
+#define FLASH_OPT_KEY2           ((uint32_t)0x4C5D6E7F)
+/**
+  * @}
+  */ 
+
+/** 
+  * @brief   ACR register byte 0 (Bits[8:0]) base address  
+  */ 
+#define ACR_BYTE0_ADDRESS           ((uint32_t)0x40023C00) 
+/** 
+  * @brief   OPTCR register byte 3 (Bits[24:16]) base address  
+  */ 
+#define OPTCR_BYTE0_ADDRESS         ((uint32_t)0x40023C14)
+#define OPTCR_BYTE1_ADDRESS         ((uint32_t)0x40023C15)
+#define OPTCR_BYTE2_ADDRESS         ((uint32_t)0x40023C16)
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+ 
+/* FLASH Interface configuration functions ************************************/
+void FLASH_SetLatency(uint32_t FLASH_Latency);
+void FLASH_PrefetchBufferCmd(FunctionalState NewState);
+void FLASH_InstructionCacheCmd(FunctionalState NewState);
+void FLASH_DataCacheCmd(FunctionalState NewState);
+void FLASH_InstructionCacheReset(void);
+void FLASH_DataCacheReset(void);
+
+/* FLASH Memory Programming functions *****************************************/   
+void FLASH_Unlock(void);
+void FLASH_Lock(void);
+FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange);
+FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange);
+FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data);
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data);
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data);
+FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data);
+
+/* Option Bytes Programming functions *****************************************/ 
+void FLASH_OB_Unlock(void);
+void FLASH_OB_Lock(void);
+void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState);
+void FLASH_OB_RDPConfig(uint8_t OB_RDP);
+void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY);
+void FLASH_OB_BORConfig(uint8_t OB_BOR);
+FLASH_Status FLASH_OB_Launch(void);
+uint8_t FLASH_OB_GetUser(void);
+uint16_t FLASH_OB_GetWRP(void);
+FlagStatus FLASH_OB_GetRDP(void);
+uint8_t FLASH_OB_GetBOR(void);
+
+/* Interrupts and flags management functions **********************************/
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState);
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG);
+void FLASH_ClearFlag(uint32_t FLASH_FLAG);
+FLASH_Status FLASH_GetStatus(void);
+FLASH_Status FLASH_WaitForLastOperation(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_FLASH_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h
new file mode 100644
index 0000000000..bd33668efe
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_fsmc.h
@@ -0,0 +1,669 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_fsmc.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the FSMC firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_FSMC_H
+#define __STM32F4xx_FSMC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup FSMC
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  Timing parameters For NOR/SRAM Banks  
+  */
+typedef struct
+{
+  uint32_t FSMC_AddressSetupTime;       /*!< Defines the number of HCLK cycles to configure
+                                             the duration of the address setup time. 
+                                             This parameter can be a value between 0 and 0xF.
+                                             @note This parameter is not used with synchronous NOR Flash memories. */
+
+  uint32_t FSMC_AddressHoldTime;        /*!< Defines the number of HCLK cycles to configure
+                                             the duration of the address hold time.
+                                             This parameter can be a value between 0 and 0xF. 
+                                             @note This parameter is not used with synchronous NOR Flash memories.*/
+
+  uint32_t FSMC_DataSetupTime;          /*!< Defines the number of HCLK cycles to configure
+                                             the duration of the data setup time.
+                                             This parameter can be a value between 0 and 0xFF.
+                                             @note This parameter is used for SRAMs, ROMs and asynchronous multiplexed NOR Flash memories. */
+
+  uint32_t FSMC_BusTurnAroundDuration;  /*!< Defines the number of HCLK cycles to configure
+                                             the duration of the bus turnaround.
+                                             This parameter can be a value between 0 and 0xF.
+                                             @note This parameter is only used for multiplexed NOR Flash memories. */
+
+  uint32_t FSMC_CLKDivision;            /*!< Defines the period of CLK clock output signal, expressed in number of HCLK cycles.
+                                             This parameter can be a value between 1 and 0xF.
+                                             @note This parameter is not used for asynchronous NOR Flash, SRAM or ROM accesses. */
+
+  uint32_t FSMC_DataLatency;            /*!< Defines the number of memory clock cycles to issue
+                                             to the memory before getting the first data.
+                                             The parameter value depends on the memory type as shown below:
+                                              - It must be set to 0 in case of a CRAM
+                                              - It is don't care in asynchronous NOR, SRAM or ROM accesses
+                                              - It may assume a value between 0 and 0xF in NOR Flash memories
+                                                with synchronous burst mode enable */
+
+  uint32_t FSMC_AccessMode;             /*!< Specifies the asynchronous access mode. 
+                                             This parameter can be a value of @ref FSMC_Access_Mode */
+}FSMC_NORSRAMTimingInitTypeDef;
+
+/** 
+  * @brief  FSMC NOR/SRAM Init structure definition
+  */
+typedef struct
+{
+  uint32_t FSMC_Bank;                /*!< Specifies the NOR/SRAM memory bank that will be used.
+                                          This parameter can be a value of @ref FSMC_NORSRAM_Bank */
+
+  uint32_t FSMC_DataAddressMux;      /*!< Specifies whether the address and data values are
+                                          multiplexed on the databus or not. 
+                                          This parameter can be a value of @ref FSMC_Data_Address_Bus_Multiplexing */
+
+  uint32_t FSMC_MemoryType;          /*!< Specifies the type of external memory attached to
+                                          the corresponding memory bank.
+                                          This parameter can be a value of @ref FSMC_Memory_Type */
+
+  uint32_t FSMC_MemoryDataWidth;     /*!< Specifies the external memory device width.
+                                          This parameter can be a value of @ref FSMC_Data_Width */
+
+  uint32_t FSMC_BurstAccessMode;     /*!< Enables or disables the burst access mode for Flash memory,
+                                          valid only with synchronous burst Flash memories.
+                                          This parameter can be a value of @ref FSMC_Burst_Access_Mode */
+
+  uint32_t FSMC_AsynchronousWait;     /*!< Enables or disables wait signal during asynchronous transfers,
+                                          valid only with asynchronous Flash memories.
+                                          This parameter can be a value of @ref FSMC_AsynchronousWait */                                          
+
+  uint32_t FSMC_WaitSignalPolarity;  /*!< Specifies the wait signal polarity, valid only when accessing
+                                          the Flash memory in burst mode.
+                                          This parameter can be a value of @ref FSMC_Wait_Signal_Polarity */
+
+  uint32_t FSMC_WrapMode;            /*!< Enables or disables the Wrapped burst access mode for Flash
+                                          memory, valid only when accessing Flash memories in burst mode.
+                                          This parameter can be a value of @ref FSMC_Wrap_Mode */
+
+  uint32_t FSMC_WaitSignalActive;    /*!< Specifies if the wait signal is asserted by the memory one
+                                          clock cycle before the wait state or during the wait state,
+                                          valid only when accessing memories in burst mode. 
+                                          This parameter can be a value of @ref FSMC_Wait_Timing */
+
+  uint32_t FSMC_WriteOperation;      /*!< Enables or disables the write operation in the selected bank by the FSMC. 
+                                          This parameter can be a value of @ref FSMC_Write_Operation */
+
+  uint32_t FSMC_WaitSignal;          /*!< Enables or disables the wait-state insertion via wait
+                                          signal, valid for Flash memory access in burst mode. 
+                                          This parameter can be a value of @ref FSMC_Wait_Signal */
+
+  uint32_t FSMC_ExtendedMode;        /*!< Enables or disables the extended mode.
+                                          This parameter can be a value of @ref FSMC_Extended_Mode */
+
+  uint32_t FSMC_WriteBurst;          /*!< Enables or disables the write burst operation.
+                                          This parameter can be a value of @ref FSMC_Write_Burst */ 
+
+  FSMC_NORSRAMTimingInitTypeDef* FSMC_ReadWriteTimingStruct; /*!< Timing Parameters for write and read access if the  ExtendedMode is not used*/  
+
+  FSMC_NORSRAMTimingInitTypeDef* FSMC_WriteTimingStruct;     /*!< Timing Parameters for write access if the  ExtendedMode is used*/      
+}FSMC_NORSRAMInitTypeDef;
+
+/** 
+  * @brief  Timing parameters For FSMC NAND and PCCARD Banks
+  */
+typedef struct
+{
+  uint32_t FSMC_SetupTime;      /*!< Defines the number of HCLK cycles to setup address before
+                                     the command assertion for NAND-Flash read or write access
+                                     to common/Attribute or I/O memory space (depending on
+                                     the memory space timing to be configured).
+                                     This parameter can be a value between 0 and 0xFF.*/
+
+  uint32_t FSMC_WaitSetupTime;  /*!< Defines the minimum number of HCLK cycles to assert the
+                                     command for NAND-Flash read or write access to
+                                     common/Attribute or I/O memory space (depending on the
+                                     memory space timing to be configured). 
+                                     This parameter can be a number between 0x00 and 0xFF */
+
+  uint32_t FSMC_HoldSetupTime;  /*!< Defines the number of HCLK clock cycles to hold address
+                                     (and data for write access) after the command deassertion
+                                     for NAND-Flash read or write access to common/Attribute
+                                     or I/O memory space (depending on the memory space timing
+                                     to be configured).
+                                     This parameter can be a number between 0x00 and 0xFF */
+
+  uint32_t FSMC_HiZSetupTime;   /*!< Defines the number of HCLK clock cycles during which the
+                                     databus is kept in HiZ after the start of a NAND-Flash
+                                     write access to common/Attribute or I/O memory space (depending
+                                     on the memory space timing to be configured).
+                                     This parameter can be a number between 0x00 and 0xFF */
+}FSMC_NAND_PCCARDTimingInitTypeDef;
+
+/** 
+  * @brief  FSMC NAND Init structure definition
+  */
+typedef struct
+{
+  uint32_t FSMC_Bank;              /*!< Specifies the NAND memory bank that will be used.
+                                      This parameter can be a value of @ref FSMC_NAND_Bank */
+
+  uint32_t FSMC_Waitfeature;      /*!< Enables or disables the Wait feature for the NAND Memory Bank.
+                                       This parameter can be any value of @ref FSMC_Wait_feature */
+
+  uint32_t FSMC_MemoryDataWidth;  /*!< Specifies the external memory device width.
+                                       This parameter can be any value of @ref FSMC_Data_Width */
+
+  uint32_t FSMC_ECC;              /*!< Enables or disables the ECC computation.
+                                       This parameter can be any value of @ref FSMC_ECC */
+
+  uint32_t FSMC_ECCPageSize;      /*!< Defines the page size for the extended ECC.
+                                       This parameter can be any value of @ref FSMC_ECC_Page_Size */
+
+  uint32_t FSMC_TCLRSetupTime;    /*!< Defines the number of HCLK cycles to configure the
+                                       delay between CLE low and RE low.
+                                       This parameter can be a value between 0 and 0xFF. */
+
+  uint32_t FSMC_TARSetupTime;     /*!< Defines the number of HCLK cycles to configure the
+                                       delay between ALE low and RE low.
+                                       This parameter can be a number between 0x0 and 0xFF */ 
+
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct;   /*!< FSMC Common Space Timing */ 
+
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct; /*!< FSMC Attribute Space Timing */
+}FSMC_NANDInitTypeDef;
+
+/** 
+  * @brief  FSMC PCCARD Init structure definition
+  */
+
+typedef struct
+{
+  uint32_t FSMC_Waitfeature;    /*!< Enables or disables the Wait feature for the Memory Bank.
+                                    This parameter can be any value of @ref FSMC_Wait_feature */
+
+  uint32_t FSMC_TCLRSetupTime;  /*!< Defines the number of HCLK cycles to configure the
+                                     delay between CLE low and RE low.
+                                     This parameter can be a value between 0 and 0xFF. */
+
+  uint32_t FSMC_TARSetupTime;   /*!< Defines the number of HCLK cycles to configure the
+                                     delay between ALE low and RE low.
+                                     This parameter can be a number between 0x0 and 0xFF */ 
+
+  
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_CommonSpaceTimingStruct; /*!< FSMC Common Space Timing */
+
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_AttributeSpaceTimingStruct;  /*!< FSMC Attribute Space Timing */ 
+  
+  FSMC_NAND_PCCARDTimingInitTypeDef*  FSMC_IOSpaceTimingStruct; /*!< FSMC IO Space Timing */  
+}FSMC_PCCARDInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup FSMC_Exported_Constants
+  * @{
+  */
+
+/** @defgroup FSMC_NORSRAM_Bank 
+  * @{
+  */
+#define FSMC_Bank1_NORSRAM1                      ((uint32_t)0x00000000)
+#define FSMC_Bank1_NORSRAM2                      ((uint32_t)0x00000002)
+#define FSMC_Bank1_NORSRAM3                      ((uint32_t)0x00000004)
+#define FSMC_Bank1_NORSRAM4                      ((uint32_t)0x00000006)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_NAND_Bank 
+  * @{
+  */  
+#define FSMC_Bank2_NAND                          ((uint32_t)0x00000010)
+#define FSMC_Bank3_NAND                          ((uint32_t)0x00000100)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_PCCARD_Bank 
+  * @{
+  */    
+#define FSMC_Bank4_PCCARD                        ((uint32_t)0x00001000)
+/**
+  * @}
+  */
+
+#define IS_FSMC_NORSRAM_BANK(BANK) (((BANK) == FSMC_Bank1_NORSRAM1) || \
+                                    ((BANK) == FSMC_Bank1_NORSRAM2) || \
+                                    ((BANK) == FSMC_Bank1_NORSRAM3) || \
+                                    ((BANK) == FSMC_Bank1_NORSRAM4))
+
+#define IS_FSMC_NAND_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+                                 ((BANK) == FSMC_Bank3_NAND))
+
+#define IS_FSMC_GETFLAG_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+                                    ((BANK) == FSMC_Bank3_NAND) || \
+                                    ((BANK) == FSMC_Bank4_PCCARD))
+
+#define IS_FSMC_IT_BANK(BANK) (((BANK) == FSMC_Bank2_NAND) || \
+                               ((BANK) == FSMC_Bank3_NAND) || \
+                               ((BANK) == FSMC_Bank4_PCCARD))
+
+/** @defgroup FSMC_NOR_SRAM_Controller 
+  * @{
+  */
+
+/** @defgroup FSMC_Data_Address_Bus_Multiplexing 
+  * @{
+  */
+
+#define FSMC_DataAddressMux_Disable                ((uint32_t)0x00000000)
+#define FSMC_DataAddressMux_Enable                 ((uint32_t)0x00000002)
+#define IS_FSMC_MUX(MUX) (((MUX) == FSMC_DataAddressMux_Disable) || \
+                          ((MUX) == FSMC_DataAddressMux_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Memory_Type 
+  * @{
+  */
+
+#define FSMC_MemoryType_SRAM                     ((uint32_t)0x00000000)
+#define FSMC_MemoryType_PSRAM                    ((uint32_t)0x00000004)
+#define FSMC_MemoryType_NOR                      ((uint32_t)0x00000008)
+#define IS_FSMC_MEMORY(MEMORY) (((MEMORY) == FSMC_MemoryType_SRAM) || \
+                                ((MEMORY) == FSMC_MemoryType_PSRAM)|| \
+                                ((MEMORY) == FSMC_MemoryType_NOR))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Width 
+  * @{
+  */
+
+#define FSMC_MemoryDataWidth_8b                  ((uint32_t)0x00000000)
+#define FSMC_MemoryDataWidth_16b                 ((uint32_t)0x00000010)
+#define IS_FSMC_MEMORY_WIDTH(WIDTH) (((WIDTH) == FSMC_MemoryDataWidth_8b) || \
+                                     ((WIDTH) == FSMC_MemoryDataWidth_16b))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Burst_Access_Mode 
+  * @{
+  */
+
+#define FSMC_BurstAccessMode_Disable             ((uint32_t)0x00000000) 
+#define FSMC_BurstAccessMode_Enable              ((uint32_t)0x00000100)
+#define IS_FSMC_BURSTMODE(STATE) (((STATE) == FSMC_BurstAccessMode_Disable) || \
+                                  ((STATE) == FSMC_BurstAccessMode_Enable))
+/**
+  * @}
+  */
+    
+/** @defgroup FSMC_AsynchronousWait 
+  * @{
+  */
+#define FSMC_AsynchronousWait_Disable            ((uint32_t)0x00000000)
+#define FSMC_AsynchronousWait_Enable             ((uint32_t)0x00008000)
+#define IS_FSMC_ASYNWAIT(STATE) (((STATE) == FSMC_AsynchronousWait_Disable) || \
+                                 ((STATE) == FSMC_AsynchronousWait_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Signal_Polarity 
+  * @{
+  */
+#define FSMC_WaitSignalPolarity_Low              ((uint32_t)0x00000000)
+#define FSMC_WaitSignalPolarity_High             ((uint32_t)0x00000200)
+#define IS_FSMC_WAIT_POLARITY(POLARITY) (((POLARITY) == FSMC_WaitSignalPolarity_Low) || \
+                                         ((POLARITY) == FSMC_WaitSignalPolarity_High))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wrap_Mode 
+  * @{
+  */
+#define FSMC_WrapMode_Disable                    ((uint32_t)0x00000000)
+#define FSMC_WrapMode_Enable                     ((uint32_t)0x00000400) 
+#define IS_FSMC_WRAP_MODE(MODE) (((MODE) == FSMC_WrapMode_Disable) || \
+                                 ((MODE) == FSMC_WrapMode_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Timing 
+  * @{
+  */
+#define FSMC_WaitSignalActive_BeforeWaitState    ((uint32_t)0x00000000)
+#define FSMC_WaitSignalActive_DuringWaitState    ((uint32_t)0x00000800) 
+#define IS_FSMC_WAIT_SIGNAL_ACTIVE(ACTIVE) (((ACTIVE) == FSMC_WaitSignalActive_BeforeWaitState) || \
+                                            ((ACTIVE) == FSMC_WaitSignalActive_DuringWaitState))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Write_Operation 
+  * @{
+  */
+#define FSMC_WriteOperation_Disable                     ((uint32_t)0x00000000)
+#define FSMC_WriteOperation_Enable                      ((uint32_t)0x00001000)
+#define IS_FSMC_WRITE_OPERATION(OPERATION) (((OPERATION) == FSMC_WriteOperation_Disable) || \
+                                            ((OPERATION) == FSMC_WriteOperation_Enable))                         
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Signal 
+  * @{
+  */
+#define FSMC_WaitSignal_Disable                  ((uint32_t)0x00000000)
+#define FSMC_WaitSignal_Enable                   ((uint32_t)0x00002000) 
+#define IS_FSMC_WAITE_SIGNAL(SIGNAL) (((SIGNAL) == FSMC_WaitSignal_Disable) || \
+                                      ((SIGNAL) == FSMC_WaitSignal_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Extended_Mode 
+  * @{
+  */
+#define FSMC_ExtendedMode_Disable                ((uint32_t)0x00000000)
+#define FSMC_ExtendedMode_Enable                 ((uint32_t)0x00004000)
+
+#define IS_FSMC_EXTENDED_MODE(MODE) (((MODE) == FSMC_ExtendedMode_Disable) || \
+                                     ((MODE) == FSMC_ExtendedMode_Enable)) 
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Write_Burst 
+  * @{
+  */
+
+#define FSMC_WriteBurst_Disable                  ((uint32_t)0x00000000)
+#define FSMC_WriteBurst_Enable                   ((uint32_t)0x00080000) 
+#define IS_FSMC_WRITE_BURST(BURST) (((BURST) == FSMC_WriteBurst_Disable) || \
+                                    ((BURST) == FSMC_WriteBurst_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Address_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_ADDRESS_SETUP_TIME(TIME) ((TIME) <= 0xF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Address_Hold_Time 
+  * @{
+  */
+#define IS_FSMC_ADDRESS_HOLD_TIME(TIME) ((TIME) <= 0xF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_DATASETUP_TIME(TIME) (((TIME) > 0) && ((TIME) <= 0xFF))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Bus_Turn_around_Duration 
+  * @{
+  */
+#define IS_FSMC_TURNAROUND_TIME(TIME) ((TIME) <= 0xF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_CLK_Division 
+  * @{
+  */
+#define IS_FSMC_CLK_DIV(DIV) ((DIV) <= 0xF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Data_Latency 
+  * @{
+  */
+#define IS_FSMC_DATA_LATENCY(LATENCY) ((LATENCY) <= 0xF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Access_Mode 
+  * @{
+  */
+#define FSMC_AccessMode_A                        ((uint32_t)0x00000000)
+#define FSMC_AccessMode_B                        ((uint32_t)0x10000000) 
+#define FSMC_AccessMode_C                        ((uint32_t)0x20000000)
+#define FSMC_AccessMode_D                        ((uint32_t)0x30000000)
+#define IS_FSMC_ACCESS_MODE(MODE) (((MODE) == FSMC_AccessMode_A) || \
+                                   ((MODE) == FSMC_AccessMode_B) || \
+                                   ((MODE) == FSMC_AccessMode_C) || \
+                                   ((MODE) == FSMC_AccessMode_D))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+  
+/** @defgroup FSMC_NAND_PCCARD_Controller 
+  * @{
+  */
+
+/** @defgroup FSMC_Wait_feature 
+  * @{
+  */
+#define FSMC_Waitfeature_Disable                 ((uint32_t)0x00000000)
+#define FSMC_Waitfeature_Enable                  ((uint32_t)0x00000002)
+#define IS_FSMC_WAIT_FEATURE(FEATURE) (((FEATURE) == FSMC_Waitfeature_Disable) || \
+                                       ((FEATURE) == FSMC_Waitfeature_Enable))
+/**
+  * @}
+  */
+
+
+/** @defgroup FSMC_ECC 
+  * @{
+  */
+#define FSMC_ECC_Disable                         ((uint32_t)0x00000000)
+#define FSMC_ECC_Enable                          ((uint32_t)0x00000040)
+#define IS_FSMC_ECC_STATE(STATE) (((STATE) == FSMC_ECC_Disable) || \
+                                  ((STATE) == FSMC_ECC_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_ECC_Page_Size 
+  * @{
+  */
+#define FSMC_ECCPageSize_256Bytes                ((uint32_t)0x00000000)
+#define FSMC_ECCPageSize_512Bytes                ((uint32_t)0x00020000)
+#define FSMC_ECCPageSize_1024Bytes               ((uint32_t)0x00040000)
+#define FSMC_ECCPageSize_2048Bytes               ((uint32_t)0x00060000)
+#define FSMC_ECCPageSize_4096Bytes               ((uint32_t)0x00080000)
+#define FSMC_ECCPageSize_8192Bytes               ((uint32_t)0x000A0000)
+#define IS_FSMC_ECCPAGE_SIZE(SIZE) (((SIZE) == FSMC_ECCPageSize_256Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_512Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_1024Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_2048Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_4096Bytes) || \
+                                    ((SIZE) == FSMC_ECCPageSize_8192Bytes))
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_TCLR_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_TCLR_TIME(TIME) ((TIME) <= 0xFF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_TAR_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_TAR_TIME(TIME) ((TIME) <= 0xFF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_SETUP_TIME(TIME) ((TIME) <= 0xFF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Wait_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_WAIT_TIME(TIME) ((TIME) <= 0xFF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Hold_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_HOLD_TIME(TIME) ((TIME) <= 0xFF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_HiZ_Setup_Time 
+  * @{
+  */
+#define IS_FSMC_HIZ_TIME(TIME) ((TIME) <= 0xFF)
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Interrupt_sources 
+  * @{
+  */
+#define FSMC_IT_RisingEdge                       ((uint32_t)0x00000008)
+#define FSMC_IT_Level                            ((uint32_t)0x00000010)
+#define FSMC_IT_FallingEdge                      ((uint32_t)0x00000020)
+#define IS_FSMC_IT(IT) ((((IT) & (uint32_t)0xFFFFFFC7) == 0x00000000) && ((IT) != 0x00000000))
+#define IS_FSMC_GET_IT(IT) (((IT) == FSMC_IT_RisingEdge) || \
+                            ((IT) == FSMC_IT_Level) || \
+                            ((IT) == FSMC_IT_FallingEdge)) 
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Flags 
+  * @{
+  */
+#define FSMC_FLAG_RisingEdge                     ((uint32_t)0x00000001)
+#define FSMC_FLAG_Level                          ((uint32_t)0x00000002)
+#define FSMC_FLAG_FallingEdge                    ((uint32_t)0x00000004)
+#define FSMC_FLAG_FEMPT                          ((uint32_t)0x00000040)
+#define IS_FSMC_GET_FLAG(FLAG) (((FLAG) == FSMC_FLAG_RisingEdge) || \
+                                ((FLAG) == FSMC_FLAG_Level) || \
+                                ((FLAG) == FSMC_FLAG_FallingEdge) || \
+                                ((FLAG) == FSMC_FLAG_FEMPT))
+
+#define IS_FSMC_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFFFFFFF8) == 0x00000000) && ((FLAG) != 0x00000000))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/* NOR/SRAM Controller functions **********************************************/
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank);
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct);
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+
+/* NAND Controller functions **************************************************/
+void FSMC_NANDDeInit(uint32_t FSMC_Bank);
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct);
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState);
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank);
+
+/* PCCARD Controller functions ************************************************/
+void FSMC_PCCARDDeInit(void);
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct);
+void FSMC_PCCARDCmd(FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState);
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG);
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_FSMC_H */
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h
new file mode 100644
index 0000000000..43286751f9
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_gpio.h
@@ -0,0 +1,406 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_gpio.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the GPIO firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_GPIO_H
+#define __STM32F4xx_GPIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup GPIO
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+#define IS_GPIO_ALL_PERIPH(PERIPH) (((PERIPH) == GPIOA) || \
+                                    ((PERIPH) == GPIOB) || \
+                                    ((PERIPH) == GPIOC) || \
+                                    ((PERIPH) == GPIOD) || \
+                                    ((PERIPH) == GPIOE) || \
+                                    ((PERIPH) == GPIOF) || \
+                                    ((PERIPH) == GPIOG) || \
+                                    ((PERIPH) == GPIOH) || \
+                                    ((PERIPH) == GPIOI))
+                                                                
+/** 
+  * @brief  GPIO Configuration Mode enumeration 
+  */   
+typedef enum
+{ 
+  GPIO_Mode_IN   = 0x00, /*!< GPIO Input Mode */
+  GPIO_Mode_OUT  = 0x01, /*!< GPIO Output Mode */
+  GPIO_Mode_AF   = 0x02, /*!< GPIO Alternate function Mode */
+  GPIO_Mode_AN   = 0x03  /*!< GPIO Analog Mode */
+}GPIOMode_TypeDef;
+#define IS_GPIO_MODE(MODE) (((MODE) == GPIO_Mode_IN)  || ((MODE) == GPIO_Mode_OUT) || \
+                            ((MODE) == GPIO_Mode_AF)|| ((MODE) == GPIO_Mode_AN))
+
+/** 
+  * @brief  GPIO Output type enumeration 
+  */  
+typedef enum
+{ 
+  GPIO_OType_PP = 0x00,
+  GPIO_OType_OD = 0x01
+}GPIOOType_TypeDef;
+#define IS_GPIO_OTYPE(OTYPE) (((OTYPE) == GPIO_OType_PP) || ((OTYPE) == GPIO_OType_OD))
+
+
+/** 
+  * @brief  GPIO Output Maximum frequency enumeration 
+  */  
+typedef enum
+{ 
+  GPIO_Speed_2MHz   = 0x00, /*!< Low speed */
+  GPIO_Speed_25MHz  = 0x01, /*!< Medium speed */
+  GPIO_Speed_50MHz  = 0x02, /*!< Fast speed */
+  GPIO_Speed_100MHz = 0x03  /*!< High speed on 30 pF (80 MHz Output max speed on 15 pF) */
+}GPIOSpeed_TypeDef;
+#define IS_GPIO_SPEED(SPEED) (((SPEED) == GPIO_Speed_2MHz) || ((SPEED) == GPIO_Speed_25MHz) || \
+                              ((SPEED) == GPIO_Speed_50MHz)||  ((SPEED) == GPIO_Speed_100MHz)) 
+
+/** 
+  * @brief  GPIO Configuration PullUp PullDown enumeration 
+  */ 
+typedef enum
+{ 
+  GPIO_PuPd_NOPULL = 0x00,
+  GPIO_PuPd_UP     = 0x01,
+  GPIO_PuPd_DOWN   = 0x02
+}GPIOPuPd_TypeDef;
+#define IS_GPIO_PUPD(PUPD) (((PUPD) == GPIO_PuPd_NOPULL) || ((PUPD) == GPIO_PuPd_UP) || \
+                            ((PUPD) == GPIO_PuPd_DOWN))
+
+/** 
+  * @brief  GPIO Bit SET and Bit RESET enumeration 
+  */ 
+typedef enum
+{ 
+  Bit_RESET = 0,
+  Bit_SET
+}BitAction;
+#define IS_GPIO_BIT_ACTION(ACTION) (((ACTION) == Bit_RESET) || ((ACTION) == Bit_SET))
+
+
+/** 
+  * @brief   GPIO Init structure definition  
+  */ 
+typedef struct
+{
+  uint32_t GPIO_Pin;              /*!< Specifies the GPIO pins to be configured.
+                                       This parameter can be any value of @ref GPIO_pins_define */
+
+  GPIOMode_TypeDef GPIO_Mode;     /*!< Specifies the operating mode for the selected pins.
+                                       This parameter can be a value of @ref GPIOMode_TypeDef */
+
+  GPIOSpeed_TypeDef GPIO_Speed;   /*!< Specifies the speed for the selected pins.
+                                       This parameter can be a value of @ref GPIOSpeed_TypeDef */
+
+  GPIOOType_TypeDef GPIO_OType;   /*!< Specifies the operating output type for the selected pins.
+                                       This parameter can be a value of @ref GPIOOType_TypeDef */
+
+  GPIOPuPd_TypeDef GPIO_PuPd;     /*!< Specifies the operating Pull-up/Pull down for the selected pins.
+                                       This parameter can be a value of @ref GPIOPuPd_TypeDef */
+}GPIO_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup GPIO_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup GPIO_pins_define 
+  * @{
+  */ 
+#define GPIO_Pin_0                 ((uint16_t)0x0001)  /* Pin 0 selected */
+#define GPIO_Pin_1                 ((uint16_t)0x0002)  /* Pin 1 selected */
+#define GPIO_Pin_2                 ((uint16_t)0x0004)  /* Pin 2 selected */
+#define GPIO_Pin_3                 ((uint16_t)0x0008)  /* Pin 3 selected */
+#define GPIO_Pin_4                 ((uint16_t)0x0010)  /* Pin 4 selected */
+#define GPIO_Pin_5                 ((uint16_t)0x0020)  /* Pin 5 selected */
+#define GPIO_Pin_6                 ((uint16_t)0x0040)  /* Pin 6 selected */
+#define GPIO_Pin_7                 ((uint16_t)0x0080)  /* Pin 7 selected */
+#define GPIO_Pin_8                 ((uint16_t)0x0100)  /* Pin 8 selected */
+#define GPIO_Pin_9                 ((uint16_t)0x0200)  /* Pin 9 selected */
+#define GPIO_Pin_10                ((uint16_t)0x0400)  /* Pin 10 selected */
+#define GPIO_Pin_11                ((uint16_t)0x0800)  /* Pin 11 selected */
+#define GPIO_Pin_12                ((uint16_t)0x1000)  /* Pin 12 selected */
+#define GPIO_Pin_13                ((uint16_t)0x2000)  /* Pin 13 selected */
+#define GPIO_Pin_14                ((uint16_t)0x4000)  /* Pin 14 selected */
+#define GPIO_Pin_15                ((uint16_t)0x8000)  /* Pin 15 selected */
+#define GPIO_Pin_All               ((uint16_t)0xFFFF)  /* All pins selected */
+
+#define IS_GPIO_PIN(PIN) ((((PIN) & (uint16_t)0x00) == 0x00) && ((PIN) != (uint16_t)0x00))
+#define IS_GET_GPIO_PIN(PIN) (((PIN) == GPIO_Pin_0) || \
+                              ((PIN) == GPIO_Pin_1) || \
+                              ((PIN) == GPIO_Pin_2) || \
+                              ((PIN) == GPIO_Pin_3) || \
+                              ((PIN) == GPIO_Pin_4) || \
+                              ((PIN) == GPIO_Pin_5) || \
+                              ((PIN) == GPIO_Pin_6) || \
+                              ((PIN) == GPIO_Pin_7) || \
+                              ((PIN) == GPIO_Pin_8) || \
+                              ((PIN) == GPIO_Pin_9) || \
+                              ((PIN) == GPIO_Pin_10) || \
+                              ((PIN) == GPIO_Pin_11) || \
+                              ((PIN) == GPIO_Pin_12) || \
+                              ((PIN) == GPIO_Pin_13) || \
+                              ((PIN) == GPIO_Pin_14) || \
+                              ((PIN) == GPIO_Pin_15))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup GPIO_Pin_sources 
+  * @{
+  */ 
+#define GPIO_PinSource0            ((uint8_t)0x00)
+#define GPIO_PinSource1            ((uint8_t)0x01)
+#define GPIO_PinSource2            ((uint8_t)0x02)
+#define GPIO_PinSource3            ((uint8_t)0x03)
+#define GPIO_PinSource4            ((uint8_t)0x04)
+#define GPIO_PinSource5            ((uint8_t)0x05)
+#define GPIO_PinSource6            ((uint8_t)0x06)
+#define GPIO_PinSource7            ((uint8_t)0x07)
+#define GPIO_PinSource8            ((uint8_t)0x08)
+#define GPIO_PinSource9            ((uint8_t)0x09)
+#define GPIO_PinSource10           ((uint8_t)0x0A)
+#define GPIO_PinSource11           ((uint8_t)0x0B)
+#define GPIO_PinSource12           ((uint8_t)0x0C)
+#define GPIO_PinSource13           ((uint8_t)0x0D)
+#define GPIO_PinSource14           ((uint8_t)0x0E)
+#define GPIO_PinSource15           ((uint8_t)0x0F)
+
+#define IS_GPIO_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == GPIO_PinSource0) || \
+                                       ((PINSOURCE) == GPIO_PinSource1) || \
+                                       ((PINSOURCE) == GPIO_PinSource2) || \
+                                       ((PINSOURCE) == GPIO_PinSource3) || \
+                                       ((PINSOURCE) == GPIO_PinSource4) || \
+                                       ((PINSOURCE) == GPIO_PinSource5) || \
+                                       ((PINSOURCE) == GPIO_PinSource6) || \
+                                       ((PINSOURCE) == GPIO_PinSource7) || \
+                                       ((PINSOURCE) == GPIO_PinSource8) || \
+                                       ((PINSOURCE) == GPIO_PinSource9) || \
+                                       ((PINSOURCE) == GPIO_PinSource10) || \
+                                       ((PINSOURCE) == GPIO_PinSource11) || \
+                                       ((PINSOURCE) == GPIO_PinSource12) || \
+                                       ((PINSOURCE) == GPIO_PinSource13) || \
+                                       ((PINSOURCE) == GPIO_PinSource14) || \
+                                       ((PINSOURCE) == GPIO_PinSource15))
+/**
+  * @}
+  */ 
+
+/** @defgroup GPIO_Alternat_function_selection_define 
+  * @{
+  */ 
+/** 
+  * @brief   AF 0 selection  
+  */ 
+#define GPIO_AF_RTC_50Hz      ((uint8_t)0x00)  /* RTC_50Hz Alternate Function mapping */
+#define GPIO_AF_MCO           ((uint8_t)0x00)  /* MCO (MCO1 and MCO2) Alternate Function mapping */
+#define GPIO_AF_TAMPER        ((uint8_t)0x00)  /* TAMPER (TAMPER_1 and TAMPER_2) Alternate Function mapping */
+#define GPIO_AF_SWJ           ((uint8_t)0x00)  /* SWJ (SWD and JTAG) Alternate Function mapping */
+#define GPIO_AF_TRACE         ((uint8_t)0x00)  /* TRACE Alternate Function mapping */
+
+/** 
+  * @brief   AF 1 selection  
+  */ 
+#define GPIO_AF_TIM1          ((uint8_t)0x01)  /* TIM1 Alternate Function mapping */
+#define GPIO_AF_TIM2          ((uint8_t)0x01)  /* TIM2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 2 selection  
+  */ 
+#define GPIO_AF_TIM3          ((uint8_t)0x02)  /* TIM3 Alternate Function mapping */
+#define GPIO_AF_TIM4          ((uint8_t)0x02)  /* TIM4 Alternate Function mapping */
+#define GPIO_AF_TIM5          ((uint8_t)0x02)  /* TIM5 Alternate Function mapping */
+
+/** 
+  * @brief   AF 3 selection  
+  */ 
+#define GPIO_AF_TIM8          ((uint8_t)0x03)  /* TIM8 Alternate Function mapping */
+#define GPIO_AF_TIM9          ((uint8_t)0x03)  /* TIM9 Alternate Function mapping */
+#define GPIO_AF_TIM10         ((uint8_t)0x03)  /* TIM10 Alternate Function mapping */
+#define GPIO_AF_TIM11         ((uint8_t)0x03)  /* TIM11 Alternate Function mapping */
+
+/** 
+  * @brief   AF 4 selection  
+  */ 
+#define GPIO_AF_I2C1          ((uint8_t)0x04)  /* I2C1 Alternate Function mapping */
+#define GPIO_AF_I2C2          ((uint8_t)0x04)  /* I2C2 Alternate Function mapping */
+#define GPIO_AF_I2C3          ((uint8_t)0x04)  /* I2C3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 5 selection  
+  */ 
+#define GPIO_AF_SPI1          ((uint8_t)0x05)  /* SPI1 Alternate Function mapping */
+#define GPIO_AF_SPI2          ((uint8_t)0x05)  /* SPI2/I2S2 Alternate Function mapping */
+
+/** 
+  * @brief   AF 6 selection  
+  */ 
+#define GPIO_AF_SPI3          ((uint8_t)0x06)  /* SPI3/I2S3 Alternate Function mapping */
+
+/** 
+  * @brief   AF 7 selection  
+  */ 
+#define GPIO_AF_USART1        ((uint8_t)0x07)  /* USART1 Alternate Function mapping */
+#define GPIO_AF_USART2        ((uint8_t)0x07)  /* USART2 Alternate Function mapping */
+#define GPIO_AF_USART3        ((uint8_t)0x07)  /* USART3 Alternate Function mapping */
+#define GPIO_AF_I2S3ext       ((uint8_t)0x07)  /* I2S3ext Alternate Function mapping */
+
+/** 
+  * @brief   AF 8 selection  
+  */ 
+#define GPIO_AF_UART4         ((uint8_t)0x08)  /* UART4 Alternate Function mapping */
+#define GPIO_AF_UART5         ((uint8_t)0x08)  /* UART5 Alternate Function mapping */
+#define GPIO_AF_USART6        ((uint8_t)0x08)  /* USART6 Alternate Function mapping */
+
+/** 
+  * @brief   AF 9 selection 
+  */ 
+#define GPIO_AF_CAN1          ((uint8_t)0x09)  /* CAN1 Alternate Function mapping */
+#define GPIO_AF_CAN2          ((uint8_t)0x09)  /* CAN2 Alternate Function mapping */
+#define GPIO_AF_TIM12         ((uint8_t)0x09)  /* TIM12 Alternate Function mapping */
+#define GPIO_AF_TIM13         ((uint8_t)0x09)  /* TIM13 Alternate Function mapping */
+#define GPIO_AF_TIM14         ((uint8_t)0x09)  /* TIM14 Alternate Function mapping */
+
+/** 
+  * @brief   AF 10 selection  
+  */ 
+#define GPIO_AF_OTG_FS         ((uint8_t)0xA)  /* OTG_FS Alternate Function mapping */
+#define GPIO_AF_OTG_HS         ((uint8_t)0xA)  /* OTG_HS Alternate Function mapping */
+
+/** 
+  * @brief   AF 11 selection  
+  */ 
+#define GPIO_AF_ETH             ((uint8_t)0x0B)  /* ETHERNET Alternate Function mapping */
+
+/** 
+  * @brief   AF 12 selection  
+  */ 
+#define GPIO_AF_FSMC            ((uint8_t)0xC)  /* FSMC Alternate Function mapping */
+#define GPIO_AF_OTG_HS_FS       ((uint8_t)0xC)  /* OTG HS configured in FS, Alternate Function mapping */
+#define GPIO_AF_SDIO            ((uint8_t)0xC)  /* SDIO Alternate Function mapping */
+
+/** 
+  * @brief   AF 13 selection  
+  */ 
+#define GPIO_AF_DCMI          ((uint8_t)0x0D)  /* DCMI Alternate Function mapping */
+
+/** 
+  * @brief   AF 15 selection  
+  */ 
+#define GPIO_AF_EVENTOUT      ((uint8_t)0x0F)  /* EVENTOUT Alternate Function mapping */
+
+#define IS_GPIO_AF(AF)   (((AF) == GPIO_AF_RTC_50Hz)  || ((AF) == GPIO_AF_TIM14)  || \
+                          ((AF) == GPIO_AF_MCO)       || ((AF) == GPIO_AF_TAMPER) || \
+                          ((AF) == GPIO_AF_SWJ)       || ((AF) == GPIO_AF_TRACE)  || \
+                          ((AF) == GPIO_AF_TIM1)      || ((AF) == GPIO_AF_TIM2)   || \
+                          ((AF) == GPIO_AF_TIM3)      || ((AF) == GPIO_AF_TIM4)   || \
+                          ((AF) == GPIO_AF_TIM5)      || ((AF) == GPIO_AF_TIM8)   || \
+                          ((AF) == GPIO_AF_I2C1)      || ((AF) == GPIO_AF_I2C2)   || \
+                          ((AF) == GPIO_AF_I2C3)      || ((AF) == GPIO_AF_SPI1)   || \
+                          ((AF) == GPIO_AF_SPI2)      || ((AF) == GPIO_AF_TIM13)  || \
+                          ((AF) == GPIO_AF_SPI3)      || ((AF) == GPIO_AF_TIM14)  || \
+                          ((AF) == GPIO_AF_USART1)    || ((AF) == GPIO_AF_USART2) || \
+                          ((AF) == GPIO_AF_USART3)    || ((AF) == GPIO_AF_UART4)  || \
+                          ((AF) == GPIO_AF_UART5)     || ((AF) == GPIO_AF_USART6) || \
+                          ((AF) == GPIO_AF_CAN1)      || ((AF) == GPIO_AF_CAN2)   || \
+                          ((AF) == GPIO_AF_OTG_FS)    || ((AF) == GPIO_AF_OTG_HS) || \
+                          ((AF) == GPIO_AF_ETH)       || ((AF) == GPIO_AF_FSMC)   || \
+                          ((AF) == GPIO_AF_OTG_HS_FS) || ((AF) == GPIO_AF_SDIO)   || \
+                          ((AF) == GPIO_AF_DCMI)      || ((AF) == GPIO_AF_EVENTOUT))
+/**
+  * @}
+  */ 
+
+/** @defgroup GPIO_Legacy 
+  * @{
+  */
+    
+#define GPIO_Mode_AIN           GPIO_Mode_AN
+
+#define GPIO_AF_OTG1_FS         GPIO_AF_OTG_FS
+#define GPIO_AF_OTG2_HS         GPIO_AF_OTG_HS
+#define GPIO_AF_OTG2_FS         GPIO_AF_OTG_HS_FS
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/*  Function used to set the GPIO configuration to the default reset state ****/
+void GPIO_DeInit(GPIO_TypeDef* GPIOx);
+
+/* Initialization and Configuration functions *********************************/
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct);
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
+/* GPIO Read and Write functions **********************************************/
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx);
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx);
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal);
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal);
+void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin);
+
+/* GPIO Alternate functions configuration function ****************************/
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_GPIO_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h
new file mode 100644
index 0000000000..52d3c529ea
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_hash.h
@@ -0,0 +1,244 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hash.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the HASH 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_HASH_H
+#define __STM32F4xx_HASH_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup HASH
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief   HASH Init structure definition
+  */ 
+typedef struct
+{
+  uint32_t HASH_AlgoSelection; /*!< SHA-1 or MD5. This parameter can be a value 
+                                    of @ref HASH_Algo_Selection */
+  uint32_t HASH_AlgoMode;      /*!< HASH or HMAC. This parameter can be a value 
+                                    of @ref HASH_processor_Algorithm_Mode */
+  uint32_t HASH_DataType;      /*!< 32-bit data, 16-bit data, 8-bit data or 
+                                    bit-string. This parameter can be a value of
+                                    @ref HASH_Data_Type */
+  uint32_t HASH_HMACKeyType;   /*!< HMAC Short key or HMAC Long Key. This parameter
+                                    can be a value of @ref HASH_HMAC_Long_key_only_for_HMAC_mode */
+}HASH_InitTypeDef;
+
+/** 
+  * @brief  HASH message digest result structure definition  
+  */ 
+typedef struct
+{
+  uint32_t Data[5];      /*!< Message digest result : 5x 32bit words for SHA1 or 
+                                                      4x 32bit words for MD5  */
+} HASH_MsgDigest; 
+
+/** 
+  * @brief  HASH context swapping structure definition  
+  */ 
+typedef struct
+{
+  uint32_t HASH_IMR; 
+  uint32_t HASH_STR;      
+  uint32_t HASH_CR;     
+  uint32_t HASH_CSR[51];       
+}HASH_Context;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup HASH_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup HASH_Algo_Selection 
+  * @{
+  */ 
+#define HASH_AlgoSelection_SHA1    ((uint16_t)0x0000) /*!< HASH function is SHA1 */
+#define HASH_AlgoSelection_MD5     ((uint16_t)0x0080) /*!< HASH function is MD5 */
+
+#define IS_HASH_ALGOSELECTION(ALGOSELECTION) (((ALGOSELECTION) == HASH_AlgoSelection_SHA1) || \
+                                              ((ALGOSELECTION) == HASH_AlgoSelection_MD5))
+/**
+  * @}
+  */
+
+/** @defgroup HASH_processor_Algorithm_Mode 
+  * @{
+  */ 
+#define HASH_AlgoMode_HASH         ((uint16_t)0x0000) /*!< Algorithm is HASH */ 
+#define HASH_AlgoMode_HMAC         ((uint16_t)0x0040) /*!< Algorithm is HMAC */
+
+#define IS_HASH_ALGOMODE(ALGOMODE) (((ALGOMODE) == HASH_AlgoMode_HASH) || \
+                                    ((ALGOMODE) == HASH_AlgoMode_HMAC))
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Data_Type  
+  * @{
+  */  
+#define HASH_DataType_32b          ((uint16_t)0x0000)
+#define HASH_DataType_16b          ((uint16_t)0x0010)
+#define HASH_DataType_8b           ((uint16_t)0x0020)
+#define HASH_DataType_1b           ((uint16_t)0x0030)
+
+#define IS_HASH_DATATYPE(DATATYPE) (((DATATYPE) == HASH_DataType_32b)|| \
+                                    ((DATATYPE) == HASH_DataType_16b)|| \
+                                    ((DATATYPE) == HASH_DataType_8b)|| \
+                                    ((DATATYPE) == HASH_DataType_1b))
+/**
+  * @}
+  */
+
+/** @defgroup HASH_HMAC_Long_key_only_for_HMAC_mode  
+  * @{
+  */ 
+#define HASH_HMACKeyType_ShortKey      ((uint32_t)0x00000000) /*!< HMAC Key is <= 64 bytes */
+#define HASH_HMACKeyType_LongKey       ((uint32_t)0x00010000) /*!< HMAC Key is > 64 bytes */
+
+#define IS_HASH_HMAC_KEYTYPE(KEYTYPE) (((KEYTYPE) == HASH_HMACKeyType_ShortKey) || \
+                                  ((KEYTYPE) == HASH_HMACKeyType_LongKey))
+/**
+  * @}
+  */
+
+/** @defgroup Number_of_valid_bits_in_last_word_of_the_message   
+  * @{
+  */  
+#define IS_HASH_VALIDBITSNUMBER(VALIDBITS) ((VALIDBITS) <= 0x1F)
+
+/**
+  * @}
+  */
+
+/** @defgroup HASH_interrupts_definition   
+  * @{
+  */  
+#define HASH_IT_DINI               ((uint8_t)0x01)  /*!< A new block can be entered into the input buffer (DIN)*/
+#define HASH_IT_DCI                ((uint8_t)0x02)  /*!< Digest calculation complete */
+
+#define IS_HASH_IT(IT) ((((IT) & (uint8_t)0xFC) == 0x00) && ((IT) != 0x00))
+#define IS_HASH_GET_IT(IT) (((IT) == HASH_IT_DINI) || ((IT) == HASH_IT_DCI))
+				   
+/**
+  * @}
+  */
+
+/** @defgroup HASH_flags_definition   
+  * @{
+  */  
+#define HASH_FLAG_DINIS            ((uint16_t)0x0001)  /*!< 16 locations are free in the DIN : A new block can be entered into the input buffer.*/
+#define HASH_FLAG_DCIS             ((uint16_t)0x0002)  /*!< Digest calculation complete */
+#define HASH_FLAG_DMAS             ((uint16_t)0x0004)  /*!< DMA interface is enabled (DMAE=1) or a transfer is ongoing */
+#define HASH_FLAG_BUSY             ((uint16_t)0x0008)  /*!< The hash core is Busy : processing a block of data */
+#define HASH_FLAG_DINNE            ((uint16_t)0x1000)  /*!< DIN not empty : The input buffer contains at least one word of data */
+
+#define IS_HASH_GET_FLAG(FLAG) (((FLAG) == HASH_FLAG_DINIS) || \
+                                ((FLAG) == HASH_FLAG_DCIS)  || \
+                                ((FLAG) == HASH_FLAG_DMAS)  || \
+                                ((FLAG) == HASH_FLAG_BUSY)  || \
+                                ((FLAG) == HASH_FLAG_DINNE)) 
+
+#define IS_HASH_CLEAR_FLAG(FLAG)(((FLAG) == HASH_FLAG_DINIS) || \
+                                 ((FLAG) == HASH_FLAG_DCIS))                                 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+  
+/*  Function used to set the HASH configuration to the default reset state ****/
+void HASH_DeInit(void);
+
+/* HASH Configuration function ************************************************/
+void HASH_Init(HASH_InitTypeDef* HASH_InitStruct);
+void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct);
+void HASH_Reset(void);
+
+/* HASH Message Digest generation functions ***********************************/
+void HASH_DataIn(uint32_t Data);
+uint8_t HASH_GetInFIFOWordsNbr(void);
+void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber);
+void HASH_StartDigest(void);
+void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest);
+
+/* HASH Context swapping functions ********************************************/
+void HASH_SaveContext(HASH_Context* HASH_ContextSave);
+void HASH_RestoreContext(HASH_Context* HASH_ContextRestore);
+
+/* HASH's DMA interface function **********************************************/
+void HASH_DMACmd(FunctionalState NewState);
+
+/* HASH Interrupts and flags management functions *****************************/
+void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState);
+FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG);
+void HASH_ClearFlag(uint16_t HASH_FLAG);
+ITStatus HASH_GetITStatus(uint8_t HASH_IT);
+void HASH_ClearITPendingBit(uint8_t HASH_IT);
+
+/* High Level SHA1 functions **************************************************/
+ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20]);
+ErrorStatus HMAC_SHA1(uint8_t *Key, uint32_t Keylen,
+                      uint8_t *Input, uint32_t Ilen,
+                      uint8_t Output[20]);
+
+/* High Level MD5 functions ***************************************************/
+ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16]);
+ErrorStatus HMAC_MD5(uint8_t *Key, uint32_t Keylen,
+                     uint8_t *Input, uint32_t Ilen,
+                     uint8_t Output[16]);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_HASH_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h
new file mode 100644
index 0000000000..9ef916bce5
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_i2c.h
@@ -0,0 +1,692 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_i2c.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the I2C firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************  
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_I2C_H
+#define __STM32F4xx_I2C_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup I2C
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  I2C Init structure definition  
+  */
+
+typedef struct
+{
+  uint32_t I2C_ClockSpeed;          /*!< Specifies the clock frequency.
+                                         This parameter must be set to a value lower than 400kHz */
+
+  uint16_t I2C_Mode;                /*!< Specifies the I2C mode.
+                                         This parameter can be a value of @ref I2C_mode */
+
+  uint16_t I2C_DutyCycle;           /*!< Specifies the I2C fast mode duty cycle.
+                                         This parameter can be a value of @ref I2C_duty_cycle_in_fast_mode */
+
+  uint16_t I2C_OwnAddress1;         /*!< Specifies the first device own address.
+                                         This parameter can be a 7-bit or 10-bit address. */
+
+  uint16_t I2C_Ack;                 /*!< Enables or disables the acknowledgement.
+                                         This parameter can be a value of @ref I2C_acknowledgement */
+
+  uint16_t I2C_AcknowledgedAddress; /*!< Specifies if 7-bit or 10-bit address is acknowledged.
+                                         This parameter can be a value of @ref I2C_acknowledged_address */
+}I2C_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+
+/** @defgroup I2C_Exported_Constants
+  * @{
+  */
+
+#define IS_I2C_ALL_PERIPH(PERIPH) (((PERIPH) == I2C1) || \
+                                   ((PERIPH) == I2C2) || \
+                                   ((PERIPH) == I2C3))
+/** @defgroup I2C_mode 
+  * @{
+  */
+
+#define I2C_Mode_I2C                    ((uint16_t)0x0000)
+#define I2C_Mode_SMBusDevice            ((uint16_t)0x0002)  
+#define I2C_Mode_SMBusHost              ((uint16_t)0x000A)
+#define IS_I2C_MODE(MODE) (((MODE) == I2C_Mode_I2C) || \
+                           ((MODE) == I2C_Mode_SMBusDevice) || \
+                           ((MODE) == I2C_Mode_SMBusHost))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_duty_cycle_in_fast_mode 
+  * @{
+  */
+
+#define I2C_DutyCycle_16_9              ((uint16_t)0x4000) /*!< I2C fast mode Tlow/Thigh = 16/9 */
+#define I2C_DutyCycle_2                 ((uint16_t)0xBFFF) /*!< I2C fast mode Tlow/Thigh = 2 */
+#define IS_I2C_DUTY_CYCLE(CYCLE) (((CYCLE) == I2C_DutyCycle_16_9) || \
+                                  ((CYCLE) == I2C_DutyCycle_2))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_acknowledgement
+  * @{
+  */
+
+#define I2C_Ack_Enable                  ((uint16_t)0x0400)
+#define I2C_Ack_Disable                 ((uint16_t)0x0000)
+#define IS_I2C_ACK_STATE(STATE) (((STATE) == I2C_Ack_Enable) || \
+                                 ((STATE) == I2C_Ack_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_transfer_direction 
+  * @{
+  */
+
+#define  I2C_Direction_Transmitter      ((uint8_t)0x00)
+#define  I2C_Direction_Receiver         ((uint8_t)0x01)
+#define IS_I2C_DIRECTION(DIRECTION) (((DIRECTION) == I2C_Direction_Transmitter) || \
+                                     ((DIRECTION) == I2C_Direction_Receiver))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_acknowledged_address 
+  * @{
+  */
+
+#define I2C_AcknowledgedAddress_7bit    ((uint16_t)0x4000)
+#define I2C_AcknowledgedAddress_10bit   ((uint16_t)0xC000)
+#define IS_I2C_ACKNOWLEDGE_ADDRESS(ADDRESS) (((ADDRESS) == I2C_AcknowledgedAddress_7bit) || \
+                                             ((ADDRESS) == I2C_AcknowledgedAddress_10bit))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_registers 
+  * @{
+  */
+
+#define I2C_Register_CR1                ((uint8_t)0x00)
+#define I2C_Register_CR2                ((uint8_t)0x04)
+#define I2C_Register_OAR1               ((uint8_t)0x08)
+#define I2C_Register_OAR2               ((uint8_t)0x0C)
+#define I2C_Register_DR                 ((uint8_t)0x10)
+#define I2C_Register_SR1                ((uint8_t)0x14)
+#define I2C_Register_SR2                ((uint8_t)0x18)
+#define I2C_Register_CCR                ((uint8_t)0x1C)
+#define I2C_Register_TRISE              ((uint8_t)0x20)
+#define IS_I2C_REGISTER(REGISTER) (((REGISTER) == I2C_Register_CR1) || \
+                                   ((REGISTER) == I2C_Register_CR2) || \
+                                   ((REGISTER) == I2C_Register_OAR1) || \
+                                   ((REGISTER) == I2C_Register_OAR2) || \
+                                   ((REGISTER) == I2C_Register_DR) || \
+                                   ((REGISTER) == I2C_Register_SR1) || \
+                                   ((REGISTER) == I2C_Register_SR2) || \
+                                   ((REGISTER) == I2C_Register_CCR) || \
+                                   ((REGISTER) == I2C_Register_TRISE))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_NACK_position 
+  * @{
+  */
+
+#define I2C_NACKPosition_Next           ((uint16_t)0x0800)
+#define I2C_NACKPosition_Current        ((uint16_t)0xF7FF)
+#define IS_I2C_NACK_POSITION(POSITION)  (((POSITION) == I2C_NACKPosition_Next) || \
+                                         ((POSITION) == I2C_NACKPosition_Current))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_SMBus_alert_pin_level 
+  * @{
+  */
+
+#define I2C_SMBusAlert_Low              ((uint16_t)0x2000)
+#define I2C_SMBusAlert_High             ((uint16_t)0xDFFF)
+#define IS_I2C_SMBUS_ALERT(ALERT) (((ALERT) == I2C_SMBusAlert_Low) || \
+                                   ((ALERT) == I2C_SMBusAlert_High))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_PEC_position 
+  * @{
+  */
+
+#define I2C_PECPosition_Next            ((uint16_t)0x0800)
+#define I2C_PECPosition_Current         ((uint16_t)0xF7FF)
+#define IS_I2C_PEC_POSITION(POSITION) (((POSITION) == I2C_PECPosition_Next) || \
+                                       ((POSITION) == I2C_PECPosition_Current))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_interrupts_definition 
+  * @{
+  */
+
+#define I2C_IT_BUF                      ((uint16_t)0x0400)
+#define I2C_IT_EVT                      ((uint16_t)0x0200)
+#define I2C_IT_ERR                      ((uint16_t)0x0100)
+#define IS_I2C_CONFIG_IT(IT) ((((IT) & (uint16_t)0xF8FF) == 0x00) && ((IT) != 0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup I2C_interrupts_definition 
+  * @{
+  */
+
+#define I2C_IT_SMBALERT                 ((uint32_t)0x01008000)
+#define I2C_IT_TIMEOUT                  ((uint32_t)0x01004000)
+#define I2C_IT_PECERR                   ((uint32_t)0x01001000)
+#define I2C_IT_OVR                      ((uint32_t)0x01000800)
+#define I2C_IT_AF                       ((uint32_t)0x01000400)
+#define I2C_IT_ARLO                     ((uint32_t)0x01000200)
+#define I2C_IT_BERR                     ((uint32_t)0x01000100)
+#define I2C_IT_TXE                      ((uint32_t)0x06000080)
+#define I2C_IT_RXNE                     ((uint32_t)0x06000040)
+#define I2C_IT_STOPF                    ((uint32_t)0x02000010)
+#define I2C_IT_ADD10                    ((uint32_t)0x02000008)
+#define I2C_IT_BTF                      ((uint32_t)0x02000004)
+#define I2C_IT_ADDR                     ((uint32_t)0x02000002)
+#define I2C_IT_SB                       ((uint32_t)0x02000001)
+
+#define IS_I2C_CLEAR_IT(IT) ((((IT) & (uint16_t)0x20FF) == 0x00) && ((IT) != (uint16_t)0x00))
+
+#define IS_I2C_GET_IT(IT) (((IT) == I2C_IT_SMBALERT) || ((IT) == I2C_IT_TIMEOUT) || \
+                           ((IT) == I2C_IT_PECERR) || ((IT) == I2C_IT_OVR) || \
+                           ((IT) == I2C_IT_AF) || ((IT) == I2C_IT_ARLO) || \
+                           ((IT) == I2C_IT_BERR) || ((IT) == I2C_IT_TXE) || \
+                           ((IT) == I2C_IT_RXNE) || ((IT) == I2C_IT_STOPF) || \
+                           ((IT) == I2C_IT_ADD10) || ((IT) == I2C_IT_BTF) || \
+                           ((IT) == I2C_IT_ADDR) || ((IT) == I2C_IT_SB))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_flags_definition 
+  * @{
+  */
+
+/** 
+  * @brief  SR2 register flags  
+  */
+
+#define I2C_FLAG_DUALF                  ((uint32_t)0x00800000)
+#define I2C_FLAG_SMBHOST                ((uint32_t)0x00400000)
+#define I2C_FLAG_SMBDEFAULT             ((uint32_t)0x00200000)
+#define I2C_FLAG_GENCALL                ((uint32_t)0x00100000)
+#define I2C_FLAG_TRA                    ((uint32_t)0x00040000)
+#define I2C_FLAG_BUSY                   ((uint32_t)0x00020000)
+#define I2C_FLAG_MSL                    ((uint32_t)0x00010000)
+
+/** 
+  * @brief  SR1 register flags  
+  */
+
+#define I2C_FLAG_SMBALERT               ((uint32_t)0x10008000)
+#define I2C_FLAG_TIMEOUT                ((uint32_t)0x10004000)
+#define I2C_FLAG_PECERR                 ((uint32_t)0x10001000)
+#define I2C_FLAG_OVR                    ((uint32_t)0x10000800)
+#define I2C_FLAG_AF                     ((uint32_t)0x10000400)
+#define I2C_FLAG_ARLO                   ((uint32_t)0x10000200)
+#define I2C_FLAG_BERR                   ((uint32_t)0x10000100)
+#define I2C_FLAG_TXE                    ((uint32_t)0x10000080)
+#define I2C_FLAG_RXNE                   ((uint32_t)0x10000040)
+#define I2C_FLAG_STOPF                  ((uint32_t)0x10000010)
+#define I2C_FLAG_ADD10                  ((uint32_t)0x10000008)
+#define I2C_FLAG_BTF                    ((uint32_t)0x10000004)
+#define I2C_FLAG_ADDR                   ((uint32_t)0x10000002)
+#define I2C_FLAG_SB                     ((uint32_t)0x10000001)
+
+#define IS_I2C_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0x20FF) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_I2C_GET_FLAG(FLAG) (((FLAG) == I2C_FLAG_DUALF) || ((FLAG) == I2C_FLAG_SMBHOST) || \
+                               ((FLAG) == I2C_FLAG_SMBDEFAULT) || ((FLAG) == I2C_FLAG_GENCALL) || \
+                               ((FLAG) == I2C_FLAG_TRA) || ((FLAG) == I2C_FLAG_BUSY) || \
+                               ((FLAG) == I2C_FLAG_MSL) || ((FLAG) == I2C_FLAG_SMBALERT) || \
+                               ((FLAG) == I2C_FLAG_TIMEOUT) || ((FLAG) == I2C_FLAG_PECERR) || \
+                               ((FLAG) == I2C_FLAG_OVR) || ((FLAG) == I2C_FLAG_AF) || \
+                               ((FLAG) == I2C_FLAG_ARLO) || ((FLAG) == I2C_FLAG_BERR) || \
+                               ((FLAG) == I2C_FLAG_TXE) || ((FLAG) == I2C_FLAG_RXNE) || \
+                               ((FLAG) == I2C_FLAG_STOPF) || ((FLAG) == I2C_FLAG_ADD10) || \
+                               ((FLAG) == I2C_FLAG_BTF) || ((FLAG) == I2C_FLAG_ADDR) || \
+                               ((FLAG) == I2C_FLAG_SB))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Events 
+  * @{
+  */
+
+/**
+ ===============================================================================
+               I2C Master Events (Events grouped in order of communication)
+ ===============================================================================
+ */
+
+/** 
+  * @brief  Communication start
+  * 
+  * After sending the START condition (I2C_GenerateSTART() function) the master 
+  * has to wait for this event. It means that the Start condition has been correctly 
+  * released on the I2C bus (the bus is free, no other devices is communicating).
+  * 
+  */
+/* --EV5 */
+#define  I2C_EVENT_MASTER_MODE_SELECT                      ((uint32_t)0x00030001)  /* BUSY, MSL and SB flag */
+
+/** 
+  * @brief  Address Acknowledge
+  * 
+  * After checking on EV5 (start condition correctly released on the bus), the 
+  * master sends the address of the slave(s) with which it will communicate 
+  * (I2C_Send7bitAddress() function, it also determines the direction of the communication: 
+  * Master transmitter or Receiver). Then the master has to wait that a slave acknowledges 
+  * his address. If an acknowledge is sent on the bus, one of the following events will 
+  * be set:
+  * 
+  *  1) In case of Master Receiver (7-bit addressing): the I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED 
+  *     event is set.
+  *  
+  *  2) In case of Master Transmitter (7-bit addressing): the I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED 
+  *     is set
+  *  
+  *  3) In case of 10-Bit addressing mode, the master (just after generating the START 
+  *  and checking on EV5) has to send the header of 10-bit addressing mode (I2C_SendData() 
+  *  function). Then master should wait on EV9. It means that the 10-bit addressing 
+  *  header has been correctly sent on the bus. Then master should send the second part of 
+  *  the 10-bit address (LSB) using the function I2C_Send7bitAddress(). Then master 
+  *  should wait for event EV6. 
+  *     
+  */
+
+/* --EV6 */
+#define  I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED        ((uint32_t)0x00070082)  /* BUSY, MSL, ADDR, TXE and TRA flags */
+#define  I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED           ((uint32_t)0x00030002)  /* BUSY, MSL and ADDR flags */
+/* --EV9 */
+#define  I2C_EVENT_MASTER_MODE_ADDRESS10                   ((uint32_t)0x00030008)  /* BUSY, MSL and ADD10 flags */
+
+/** 
+  * @brief Communication events
+  * 
+  * If a communication is established (START condition generated and slave address 
+  * acknowledged) then the master has to check on one of the following events for 
+  * communication procedures:
+  *  
+  * 1) Master Receiver mode: The master has to wait on the event EV7 then to read 
+  *    the data received from the slave (I2C_ReceiveData() function).
+  * 
+  * 2) Master Transmitter mode: The master has to send data (I2C_SendData() 
+  *    function) then to wait on event EV8 or EV8_2.
+  *    These two events are similar: 
+  *     - EV8 means that the data has been written in the data register and is 
+  *       being shifted out.
+  *     - EV8_2 means that the data has been physically shifted out and output 
+  *       on the bus.
+  *     In most cases, using EV8 is sufficient for the application.
+  *     Using EV8_2 leads to a slower communication but ensure more reliable test.
+  *     EV8_2 is also more suitable than EV8 for testing on the last data transmission 
+  *     (before Stop condition generation).
+  *     
+  *  @note In case the  user software does not guarantee that this event EV7 is 
+  *        managed before the current byte end of transfer, then user may check on EV7 
+  *        and BTF flag at the same time (ie. (I2C_EVENT_MASTER_BYTE_RECEIVED | I2C_FLAG_BTF)).
+  *        In this case the communication may be slower.
+  * 
+  */
+
+/* Master RECEIVER mode -----------------------------*/ 
+/* --EV7 */
+#define  I2C_EVENT_MASTER_BYTE_RECEIVED                    ((uint32_t)0x00030040)  /* BUSY, MSL and RXNE flags */
+
+/* Master TRANSMITTER mode --------------------------*/
+/* --EV8 */
+#define I2C_EVENT_MASTER_BYTE_TRANSMITTING                 ((uint32_t)0x00070080) /* TRA, BUSY, MSL, TXE flags */
+/* --EV8_2 */
+#define  I2C_EVENT_MASTER_BYTE_TRANSMITTED                 ((uint32_t)0x00070084)  /* TRA, BUSY, MSL, TXE and BTF flags */
+
+
+/**
+ ===============================================================================
+               I2C Slave Events (Events grouped in order of communication)
+ ===============================================================================
+ */
+
+
+/** 
+  * @brief  Communication start events
+  * 
+  * Wait on one of these events at the start of the communication. It means that 
+  * the I2C peripheral detected a Start condition on the bus (generated by master 
+  * device) followed by the peripheral address. The peripheral generates an ACK 
+  * condition on the bus (if the acknowledge feature is enabled through function 
+  * I2C_AcknowledgeConfig()) and the events listed above are set :
+  *  
+  * 1) In normal case (only one address managed by the slave), when the address 
+  *   sent by the master matches the own address of the peripheral (configured by 
+  *   I2C_OwnAddress1 field) the I2C_EVENT_SLAVE_XXX_ADDRESS_MATCHED event is set 
+  *   (where XXX could be TRANSMITTER or RECEIVER).
+  *    
+  * 2) In case the address sent by the master matches the second address of the 
+  *   peripheral (configured by the function I2C_OwnAddress2Config() and enabled 
+  *   by the function I2C_DualAddressCmd()) the events I2C_EVENT_SLAVE_XXX_SECONDADDRESS_MATCHED 
+  *   (where XXX could be TRANSMITTER or RECEIVER) are set.
+  *   
+  * 3) In case the address sent by the master is General Call (address 0x00) and 
+  *   if the General Call is enabled for the peripheral (using function I2C_GeneralCallCmd()) 
+  *   the following event is set I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED.   
+  * 
+  */
+
+/* --EV1  (all the events below are variants of EV1) */   
+/* 1) Case of One Single Address managed by the slave */
+#define  I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED          ((uint32_t)0x00020002) /* BUSY and ADDR flags */
+#define  I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED       ((uint32_t)0x00060082) /* TRA, BUSY, TXE and ADDR flags */
+
+/* 2) Case of Dual address managed by the slave */
+#define  I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED    ((uint32_t)0x00820000)  /* DUALF and BUSY flags */
+#define  I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED ((uint32_t)0x00860080)  /* DUALF, TRA, BUSY and TXE flags */
+
+/* 3) Case of General Call enabled for the slave */
+#define  I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED        ((uint32_t)0x00120000)  /* GENCALL and BUSY flags */
+
+/** 
+  * @brief  Communication events
+  * 
+  * Wait on one of these events when EV1 has already been checked and: 
+  * 
+  * - Slave RECEIVER mode:
+  *     - EV2: When the application is expecting a data byte to be received. 
+  *     - EV4: When the application is expecting the end of the communication: master 
+  *       sends a stop condition and data transmission is stopped.
+  *    
+  * - Slave Transmitter mode:
+  *    - EV3: When a byte has been transmitted by the slave and the application is expecting 
+  *      the end of the byte transmission. The two events I2C_EVENT_SLAVE_BYTE_TRANSMITTED and
+  *      I2C_EVENT_SLAVE_BYTE_TRANSMITTING are similar. The second one can optionally be 
+  *      used when the user software doesn't guarantee the EV3 is managed before the
+  *      current byte end of transfer.
+  *    - EV3_2: When the master sends a NACK in order to tell slave that data transmission 
+  *      shall end (before sending the STOP condition). In this case slave has to stop sending 
+  *      data bytes and expect a Stop condition on the bus.
+  *      
+  *  @note In case the  user software does not guarantee that the event EV2 is 
+  *        managed before the current byte end of transfer, then user may check on EV2 
+  *        and BTF flag at the same time (ie. (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_BTF)).
+  *        In this case the communication may be slower.
+  *
+  */
+
+/* Slave RECEIVER mode --------------------------*/ 
+/* --EV2 */
+#define  I2C_EVENT_SLAVE_BYTE_RECEIVED                     ((uint32_t)0x00020040)  /* BUSY and RXNE flags */
+/* --EV4  */
+#define  I2C_EVENT_SLAVE_STOP_DETECTED                     ((uint32_t)0x00000010)  /* STOPF flag */
+
+/* Slave TRANSMITTER mode -----------------------*/
+/* --EV3 */
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTED                  ((uint32_t)0x00060084)  /* TRA, BUSY, TXE and BTF flags */
+#define  I2C_EVENT_SLAVE_BYTE_TRANSMITTING                 ((uint32_t)0x00060080)  /* TRA, BUSY and TXE flags */
+/* --EV3_2 */
+#define  I2C_EVENT_SLAVE_ACK_FAILURE                       ((uint32_t)0x00000400)  /* AF flag */
+
+/*
+ ===============================================================================
+                          End of Events Description
+ ===============================================================================
+ */
+
+#define IS_I2C_EVENT(EVENT) (((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_RECEIVED) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF)) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL)) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_BYTE_TRANSMITTED) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF)) || \
+                             ((EVENT) == (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL)) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_STOP_DETECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_MODE_SELECT) || \
+                             ((EVENT) == I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_RECEIVED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTED) || \
+                             ((EVENT) == I2C_EVENT_MASTER_BYTE_TRANSMITTING) || \
+                             ((EVENT) == I2C_EVENT_MASTER_MODE_ADDRESS10) || \
+                             ((EVENT) == I2C_EVENT_SLAVE_ACK_FAILURE))
+/**
+  * @}
+  */
+
+/** @defgroup I2C_own_address1 
+  * @{
+  */
+
+#define IS_I2C_OWN_ADDRESS1(ADDRESS1) ((ADDRESS1) <= 0x3FF)
+/**
+  * @}
+  */
+
+/** @defgroup I2C_clock_speed 
+  * @{
+  */
+
+#define IS_I2C_CLOCK_SPEED(SPEED) (((SPEED) >= 0x1) && ((SPEED) <= 400000))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/*  Function used to set the I2C configuration to the default reset state *****/
+void I2C_DeInit(I2C_TypeDef* I2Cx);
+
+/* Initialization and Configuration functions *********************************/
+void I2C_Init(I2C_TypeDef* I2Cx, I2C_InitTypeDef* I2C_InitStruct);
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct);
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction);
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address);
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle);
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition);
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert);
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
+/* Data transfers functions ***************************************************/ 
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data);
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx);
+
+/* PEC management functions ***************************************************/ 
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition);
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState);
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx);
+
+/* DMA transfers management functions *****************************************/
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState);
+
+/* Interrupts, events and flags management functions **************************/
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register);
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState);
+
+/* 
+ ===============================================================================
+                          I2C State Monitoring Functions
+ ===============================================================================
+  This I2C driver provides three different ways for I2C state monitoring
+  depending on the application requirements and constraints:
+         
+   
+     1. Basic state monitoring (Using I2C_CheckEvent() function)
+     -----------------------------------------------------------
+        It compares the status registers (SR1 and SR2) content to a given event
+        (can be the combination of one or more flags).
+        It returns SUCCESS if the current status includes the given flags 
+        and returns ERROR if one or more flags are missing in the current status.
+
+          - When to use
+             - This function is suitable for most applications as well as for startup 
+               activity since the events are fully described in the product reference 
+               manual (RM0090).
+             - It is also suitable for users who need to define their own events.
+
+          - Limitations
+             - If an error occurs (ie. error flags are set besides to the monitored 
+               flags), the I2C_CheckEvent() function may return SUCCESS despite 
+               the communication hold or corrupted real state. 
+               In this case, it is advised to use error interrupts to monitor 
+               the error events and handle them in the interrupt IRQ handler.
+         
+     Note 
+         For error management, it is advised to use the following functions:
+           - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
+           - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+             Where x is the peripheral instance (I2C1, I2C2 ...)
+           - I2C_GetFlagStatus() or I2C_GetITStatus()  to be called into the 
+             I2Cx_ER_IRQHandler() function in order to determine which error occurred.
+           - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() 
+             and/or I2C_GenerateStop() in order to clear the error flag and source 
+             and return to correct  communication status.
+             
+ 
+     2. Advanced state monitoring (Using the function I2C_GetLastEvent())
+     -------------------------------------------------------------------- 
+        Using the function I2C_GetLastEvent() which returns the image of both status 
+        registers in a single word (uint32_t) (Status Register 2 value is shifted left 
+        by 16 bits and concatenated to Status Register 1).
+
+          - When to use
+             - This function is suitable for the same applications above but it 
+               allows to overcome the mentioned limitation of I2C_GetFlagStatus() 
+               function.
+             - The returned value could be compared to events already defined in 
+               this file or to custom values defined by user.
+               This function is suitable when multiple flags are monitored at the 
+               same time.
+             - At the opposite of I2C_CheckEvent() function, this function allows 
+               user to choose when an event is accepted (when all events flags are 
+               set and no other flags are set or just when the needed flags are set 
+               like I2C_CheckEvent() function.
+
+          - Limitations
+             - User may need to define his own events.
+             - Same remark concerning the error management is applicable for this 
+               function if user decides to check only regular communication flags 
+               (and ignores error flags).
+      
+ 
+     3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
+     -----------------------------------------------------------------------
+     
+      Using the function I2C_GetFlagStatus() which simply returns the status of 
+      one single flag (ie. I2C_FLAG_RXNE ...). 
+
+          - When to use
+             - This function could be used for specific applications or in debug 
+               phase.
+             - It is suitable when only one flag checking is needed (most I2C 
+               events are monitored through multiple flags).
+          - Limitations: 
+             - When calling this function, the Status register is accessed. 
+               Some flags are cleared when the status register is accessed. 
+               So checking the status of one Flag, may clear other ones.
+             - Function may need to be called twice or more in order to monitor 
+               one single event.           
+ */
+
+/*
+ ===============================================================================
+                          1. Basic state monitoring
+ ===============================================================================
+ */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT);
+/*
+ ===============================================================================
+                          2. Advanced state monitoring
+ ===============================================================================
+ */
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx);
+/*
+ ===============================================================================
+                          3. Flag-based state monitoring
+ ===============================================================================
+ */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+
+
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG);
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_I2C_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h
new file mode 100644
index 0000000000..e830cfa7ab
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_iwdg.h
@@ -0,0 +1,125 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_iwdg.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the IWDG 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_IWDG_H
+#define __STM32F4xx_IWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup IWDG
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup IWDG_Exported_Constants
+  * @{
+  */
+  
+/** @defgroup IWDG_WriteAccess
+  * @{
+  */
+#define IWDG_WriteAccess_Enable     ((uint16_t)0x5555)
+#define IWDG_WriteAccess_Disable    ((uint16_t)0x0000)
+#define IS_IWDG_WRITE_ACCESS(ACCESS) (((ACCESS) == IWDG_WriteAccess_Enable) || \
+                                      ((ACCESS) == IWDG_WriteAccess_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_prescaler 
+  * @{
+  */
+#define IWDG_Prescaler_4            ((uint8_t)0x00)
+#define IWDG_Prescaler_8            ((uint8_t)0x01)
+#define IWDG_Prescaler_16           ((uint8_t)0x02)
+#define IWDG_Prescaler_32           ((uint8_t)0x03)
+#define IWDG_Prescaler_64           ((uint8_t)0x04)
+#define IWDG_Prescaler_128          ((uint8_t)0x05)
+#define IWDG_Prescaler_256          ((uint8_t)0x06)
+#define IS_IWDG_PRESCALER(PRESCALER) (((PRESCALER) == IWDG_Prescaler_4)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_8)  || \
+                                      ((PRESCALER) == IWDG_Prescaler_16) || \
+                                      ((PRESCALER) == IWDG_Prescaler_32) || \
+                                      ((PRESCALER) == IWDG_Prescaler_64) || \
+                                      ((PRESCALER) == IWDG_Prescaler_128)|| \
+                                      ((PRESCALER) == IWDG_Prescaler_256))
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Flag 
+  * @{
+  */
+#define IWDG_FLAG_PVU               ((uint16_t)0x0001)
+#define IWDG_FLAG_RVU               ((uint16_t)0x0002)
+#define IS_IWDG_FLAG(FLAG) (((FLAG) == IWDG_FLAG_PVU) || ((FLAG) == IWDG_FLAG_RVU))
+#define IS_IWDG_RELOAD(RELOAD) ((RELOAD) <= 0xFFF)
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+
+/* Prescaler and Counter configuration functions ******************************/
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess);
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler);
+void IWDG_SetReload(uint16_t Reload);
+void IWDG_ReloadCounter(void);
+
+/* IWDG activation function ***************************************************/
+void IWDG_Enable(void);
+
+/* Flag management function ***************************************************/
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_IWDG_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h
new file mode 100644
index 0000000000..556e36d287
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_pwr.h
@@ -0,0 +1,163 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_pwr.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the PWR firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_PWR_H
+#define __STM32F4xx_PWR_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup PWR
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup PWR_Exported_Constants
+  * @{
+  */ 
+
+/** @defgroup PWR_PVD_detection_level 
+  * @{
+  */ 
+
+#define PWR_PVDLevel_0                  PWR_CR_PLS_LEV0
+#define PWR_PVDLevel_1                  PWR_CR_PLS_LEV1
+#define PWR_PVDLevel_2                  PWR_CR_PLS_LEV2
+#define PWR_PVDLevel_3                  PWR_CR_PLS_LEV3
+#define PWR_PVDLevel_4                  PWR_CR_PLS_LEV4
+#define PWR_PVDLevel_5                  PWR_CR_PLS_LEV5
+#define PWR_PVDLevel_6                  PWR_CR_PLS_LEV6
+#define PWR_PVDLevel_7                  PWR_CR_PLS_LEV7
+
+#define IS_PWR_PVD_LEVEL(LEVEL) (((LEVEL) == PWR_PVDLevel_0) || ((LEVEL) == PWR_PVDLevel_1)|| \
+                                 ((LEVEL) == PWR_PVDLevel_2) || ((LEVEL) == PWR_PVDLevel_3)|| \
+                                 ((LEVEL) == PWR_PVDLevel_4) || ((LEVEL) == PWR_PVDLevel_5)|| \
+                                 ((LEVEL) == PWR_PVDLevel_6) || ((LEVEL) == PWR_PVDLevel_7))
+/**
+  * @}
+  */
+
+  
+/** @defgroup PWR_Regulator_state_in_STOP_mode 
+  * @{
+  */
+
+#define PWR_Regulator_ON                ((uint32_t)0x00000000)
+#define PWR_Regulator_LowPower          PWR_CR_LPDS
+#define IS_PWR_REGULATOR(REGULATOR) (((REGULATOR) == PWR_Regulator_ON) || \
+                                     ((REGULATOR) == PWR_Regulator_LowPower))
+/**
+  * @}
+  */
+
+/** @defgroup PWR_STOP_mode_entry 
+  * @{
+  */
+
+#define PWR_STOPEntry_WFI               ((uint8_t)0x01)
+#define PWR_STOPEntry_WFE               ((uint8_t)0x02)
+#define IS_PWR_STOP_ENTRY(ENTRY) (((ENTRY) == PWR_STOPEntry_WFI) || ((ENTRY) == PWR_STOPEntry_WFE))
+ 
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Flag 
+  * @{
+  */
+
+#define PWR_FLAG_WU                     PWR_CSR_WUF
+#define PWR_FLAG_SB                     PWR_CSR_SBF
+#define PWR_FLAG_PVDO                   PWR_CSR_PVDO
+#define PWR_FLAG_BRR                    PWR_CSR_BRR
+#define PWR_FLAG_REGRDY                 PWR_CSR_REGRDY
+
+#define IS_PWR_GET_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB) || \
+                               ((FLAG) == PWR_FLAG_PVDO) || ((FLAG) == PWR_FLAG_BRR) || \
+                               ((FLAG) == PWR_FLAG_REGRDY))
+
+#define IS_PWR_CLEAR_FLAG(FLAG) (((FLAG) == PWR_FLAG_WU) || ((FLAG) == PWR_FLAG_SB))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/* Function used to set the PWR configuration to the default reset state ******/ 
+void PWR_DeInit(void);
+
+/* Backup Domain Access function **********************************************/ 
+void PWR_BackupAccessCmd(FunctionalState NewState);
+
+/* PVD configuration functions ************************************************/ 
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel);
+void PWR_PVDCmd(FunctionalState NewState);
+
+/* WakeUp pins configuration functions ****************************************/ 
+void PWR_WakeUpPinCmd(FunctionalState NewState);
+
+/* Backup Regulator configuration functions ***********************************/ 
+void PWR_BackupRegulatorCmd(FunctionalState NewState);
+
+/* Performance Mode and FLASH Power Down configuration functions **************/ 
+void PWR_HighPerformanceModeCmd(FunctionalState NewState);
+void PWR_FlashPowerDownCmd(FunctionalState NewState);
+
+/* Low Power modes configuration functions ************************************/ 
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry);
+void PWR_EnterSTANDBYMode(void);
+
+/* Flags management functions *************************************************/ 
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG);
+void PWR_ClearFlag(uint32_t PWR_FLAG);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_PWR_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h
new file mode 100644
index 0000000000..bb1230f49e
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rcc.h
@@ -0,0 +1,509 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_rcc.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the RCC firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_RCC_H
+#define __STM32F4xx_RCC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup RCC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+typedef struct
+{
+  uint32_t SYSCLK_Frequency; /*!<  SYSCLK clock frequency expressed in Hz */
+  uint32_t HCLK_Frequency;   /*!<  HCLK clock frequency expressed in Hz */
+  uint32_t PCLK1_Frequency;  /*!<  PCLK1 clock frequency expressed in Hz */
+  uint32_t PCLK2_Frequency;  /*!<  PCLK2 clock frequency expressed in Hz */
+}RCC_ClocksTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RCC_Exported_Constants
+  * @{
+  */
+  
+/** @defgroup RCC_HSE_configuration 
+  * @{
+  */
+#define RCC_HSE_OFF                      ((uint8_t)0x00)
+#define RCC_HSE_ON                       ((uint8_t)0x01)
+#define RCC_HSE_Bypass                   ((uint8_t)0x05)
+#define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
+                         ((HSE) == RCC_HSE_Bypass))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_PLL_Clock_Source 
+  * @{
+  */
+#define RCC_PLLSource_HSI                ((uint32_t)0x00000000)
+#define RCC_PLLSource_HSE                ((uint32_t)0x00400000)
+#define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI) || \
+                                   ((SOURCE) == RCC_PLLSource_HSE))
+#define IS_RCC_PLLM_VALUE(VALUE) ((VALUE) <= 63)
+#define IS_RCC_PLLN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLP_VALUE(VALUE) (((VALUE) == 2) || ((VALUE) == 4) || ((VALUE) == 6) || ((VALUE) == 8))
+#define IS_RCC_PLLQ_VALUE(VALUE) ((4 <= (VALUE)) && ((VALUE) <= 15))
+ 
+#define IS_RCC_PLLI2SN_VALUE(VALUE) ((192 <= (VALUE)) && ((VALUE) <= 432))
+#define IS_RCC_PLLI2SR_VALUE(VALUE) ((2 <= (VALUE)) && ((VALUE) <= 7))   
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_System_Clock_Source 
+  * @{
+  */
+#define RCC_SYSCLKSource_HSI             ((uint32_t)0x00000000)
+#define RCC_SYSCLKSource_HSE             ((uint32_t)0x00000001)
+#define RCC_SYSCLKSource_PLLCLK          ((uint32_t)0x00000002)
+#define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
+                                      ((SOURCE) == RCC_SYSCLKSource_HSE) || \
+                                      ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_AHB_Clock_Source
+  * @{
+  */
+#define RCC_SYSCLK_Div1                  ((uint32_t)0x00000000)
+#define RCC_SYSCLK_Div2                  ((uint32_t)0x00000080)
+#define RCC_SYSCLK_Div4                  ((uint32_t)0x00000090)
+#define RCC_SYSCLK_Div8                  ((uint32_t)0x000000A0)
+#define RCC_SYSCLK_Div16                 ((uint32_t)0x000000B0)
+#define RCC_SYSCLK_Div64                 ((uint32_t)0x000000C0)
+#define RCC_SYSCLK_Div128                ((uint32_t)0x000000D0)
+#define RCC_SYSCLK_Div256                ((uint32_t)0x000000E0)
+#define RCC_SYSCLK_Div512                ((uint32_t)0x000000F0)
+#define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
+                           ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
+                           ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
+                           ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
+                           ((HCLK) == RCC_SYSCLK_Div512))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_APB1_APB2_Clock_Source
+  * @{
+  */
+#define RCC_HCLK_Div1                    ((uint32_t)0x00000000)
+#define RCC_HCLK_Div2                    ((uint32_t)0x00001000)
+#define RCC_HCLK_Div4                    ((uint32_t)0x00001400)
+#define RCC_HCLK_Div8                    ((uint32_t)0x00001800)
+#define RCC_HCLK_Div16                   ((uint32_t)0x00001C00)
+#define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
+                           ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
+                           ((PCLK) == RCC_HCLK_Div16))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_Interrupt_Source 
+  * @{
+  */
+#define RCC_IT_LSIRDY                    ((uint8_t)0x01)
+#define RCC_IT_LSERDY                    ((uint8_t)0x02)
+#define RCC_IT_HSIRDY                    ((uint8_t)0x04)
+#define RCC_IT_HSERDY                    ((uint8_t)0x08)
+#define RCC_IT_PLLRDY                    ((uint8_t)0x10)
+#define RCC_IT_PLLI2SRDY                 ((uint8_t)0x20)
+#define RCC_IT_CSS                       ((uint8_t)0x80)
+#define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
+#define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
+                           ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
+                           ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS) || \
+                           ((IT) == RCC_IT_PLLI2SRDY))
+#define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_LSE_Configuration 
+  * @{
+  */
+#define RCC_LSE_OFF                      ((uint8_t)0x00)
+#define RCC_LSE_ON                       ((uint8_t)0x01)
+#define RCC_LSE_Bypass                   ((uint8_t)0x04)
+#define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
+                         ((LSE) == RCC_LSE_Bypass))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_RTC_Clock_Source
+  * @{
+  */
+#define RCC_RTCCLKSource_LSE             ((uint32_t)0x00000100)
+#define RCC_RTCCLKSource_LSI             ((uint32_t)0x00000200)
+#define RCC_RTCCLKSource_HSE_Div2        ((uint32_t)0x00020300)
+#define RCC_RTCCLKSource_HSE_Div3        ((uint32_t)0x00030300)
+#define RCC_RTCCLKSource_HSE_Div4        ((uint32_t)0x00040300)
+#define RCC_RTCCLKSource_HSE_Div5        ((uint32_t)0x00050300)
+#define RCC_RTCCLKSource_HSE_Div6        ((uint32_t)0x00060300)
+#define RCC_RTCCLKSource_HSE_Div7        ((uint32_t)0x00070300)
+#define RCC_RTCCLKSource_HSE_Div8        ((uint32_t)0x00080300)
+#define RCC_RTCCLKSource_HSE_Div9        ((uint32_t)0x00090300)
+#define RCC_RTCCLKSource_HSE_Div10       ((uint32_t)0x000A0300)
+#define RCC_RTCCLKSource_HSE_Div11       ((uint32_t)0x000B0300)
+#define RCC_RTCCLKSource_HSE_Div12       ((uint32_t)0x000C0300)
+#define RCC_RTCCLKSource_HSE_Div13       ((uint32_t)0x000D0300)
+#define RCC_RTCCLKSource_HSE_Div14       ((uint32_t)0x000E0300)
+#define RCC_RTCCLKSource_HSE_Div15       ((uint32_t)0x000F0300)
+#define RCC_RTCCLKSource_HSE_Div16       ((uint32_t)0x00100300)
+#define RCC_RTCCLKSource_HSE_Div17       ((uint32_t)0x00110300)
+#define RCC_RTCCLKSource_HSE_Div18       ((uint32_t)0x00120300)
+#define RCC_RTCCLKSource_HSE_Div19       ((uint32_t)0x00130300)
+#define RCC_RTCCLKSource_HSE_Div20       ((uint32_t)0x00140300)
+#define RCC_RTCCLKSource_HSE_Div21       ((uint32_t)0x00150300)
+#define RCC_RTCCLKSource_HSE_Div22       ((uint32_t)0x00160300)
+#define RCC_RTCCLKSource_HSE_Div23       ((uint32_t)0x00170300)
+#define RCC_RTCCLKSource_HSE_Div24       ((uint32_t)0x00180300)
+#define RCC_RTCCLKSource_HSE_Div25       ((uint32_t)0x00190300)
+#define RCC_RTCCLKSource_HSE_Div26       ((uint32_t)0x001A0300)
+#define RCC_RTCCLKSource_HSE_Div27       ((uint32_t)0x001B0300)
+#define RCC_RTCCLKSource_HSE_Div28       ((uint32_t)0x001C0300)
+#define RCC_RTCCLKSource_HSE_Div29       ((uint32_t)0x001D0300)
+#define RCC_RTCCLKSource_HSE_Div30       ((uint32_t)0x001E0300)
+#define RCC_RTCCLKSource_HSE_Div31       ((uint32_t)0x001F0300)
+#define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_LSI) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div2) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div3) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div4) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div5) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div6) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div7) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div8) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div9) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div10) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div11) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div12) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div13) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div14) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div15) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div16) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div17) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div18) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div19) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div20) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div21) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div22) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div23) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div24) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div25) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div26) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div27) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div28) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div29) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div30) || \
+                                      ((SOURCE) == RCC_RTCCLKSource_HSE_Div31))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_I2S_Clock_Source
+  * @{
+  */
+#define RCC_I2S2CLKSource_PLLI2S             ((uint8_t)0x00)
+#define RCC_I2S2CLKSource_Ext                ((uint8_t)0x01)
+
+#define IS_RCC_I2SCLK_SOURCE(SOURCE) (((SOURCE) == RCC_I2S2CLKSource_PLLI2S) || ((SOURCE) == RCC_I2S2CLKSource_Ext))                                
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_AHB1_Peripherals 
+  * @{
+  */ 
+#define RCC_AHB1Periph_GPIOA             ((uint32_t)0x00000001)
+#define RCC_AHB1Periph_GPIOB             ((uint32_t)0x00000002)
+#define RCC_AHB1Periph_GPIOC             ((uint32_t)0x00000004)
+#define RCC_AHB1Periph_GPIOD             ((uint32_t)0x00000008)
+#define RCC_AHB1Periph_GPIOE             ((uint32_t)0x00000010)
+#define RCC_AHB1Periph_GPIOF             ((uint32_t)0x00000020)
+#define RCC_AHB1Periph_GPIOG             ((uint32_t)0x00000040)
+#define RCC_AHB1Periph_GPIOH             ((uint32_t)0x00000080)
+#define RCC_AHB1Periph_GPIOI             ((uint32_t)0x00000100)
+#define RCC_AHB1Periph_CRC               ((uint32_t)0x00001000)
+#define RCC_AHB1Periph_FLITF             ((uint32_t)0x00008000)
+#define RCC_AHB1Periph_SRAM1             ((uint32_t)0x00010000)
+#define RCC_AHB1Periph_SRAM2             ((uint32_t)0x00020000)
+#define RCC_AHB1Periph_BKPSRAM           ((uint32_t)0x00040000)
+#define RCC_AHB1Periph_DMA1              ((uint32_t)0x00200000)
+#define RCC_AHB1Periph_DMA2              ((uint32_t)0x00400000)
+#define RCC_AHB1Periph_ETH_MAC           ((uint32_t)0x02000000)
+#define RCC_AHB1Periph_ETH_MAC_Tx        ((uint32_t)0x04000000)
+#define RCC_AHB1Periph_ETH_MAC_Rx        ((uint32_t)0x08000000)
+#define RCC_AHB1Periph_ETH_MAC_PTP       ((uint32_t)0x10000000)
+#define RCC_AHB1Periph_OTG_HS            ((uint32_t)0x20000000)
+#define RCC_AHB1Periph_OTG_HS_ULPI       ((uint32_t)0x40000000)
+#define IS_RCC_AHB1_CLOCK_PERIPH(PERIPH) ((((PERIPH) & 0x819BEE00) == 0x00) && ((PERIPH) != 0x00))
+#define IS_RCC_AHB1_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xDD9FEE00) == 0x00) && ((PERIPH) != 0x00))
+#define IS_RCC_AHB1_LPMODE_PERIPH(PERIPH) ((((PERIPH) & 0x81986E00) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_AHB2_Peripherals 
+  * @{
+  */  
+#define RCC_AHB2Periph_DCMI              ((uint32_t)0x00000001)
+#define RCC_AHB2Periph_CRYP              ((uint32_t)0x00000010)
+#define RCC_AHB2Periph_HASH              ((uint32_t)0x00000020)
+#define RCC_AHB2Periph_RNG               ((uint32_t)0x00000040)
+#define RCC_AHB2Periph_OTG_FS            ((uint32_t)0x00000080)
+#define IS_RCC_AHB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFF0E) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_AHB3_Peripherals 
+  * @{
+  */ 
+#define RCC_AHB3Periph_FSMC               ((uint32_t)0x00000001)
+#define IS_RCC_AHB3_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFFE) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_APB1_Peripherals 
+  * @{
+  */ 
+#define RCC_APB1Periph_TIM2              ((uint32_t)0x00000001)
+#define RCC_APB1Periph_TIM3              ((uint32_t)0x00000002)
+#define RCC_APB1Periph_TIM4              ((uint32_t)0x00000004)
+#define RCC_APB1Periph_TIM5              ((uint32_t)0x00000008)
+#define RCC_APB1Periph_TIM6              ((uint32_t)0x00000010)
+#define RCC_APB1Periph_TIM7              ((uint32_t)0x00000020)
+#define RCC_APB1Periph_TIM12             ((uint32_t)0x00000040)
+#define RCC_APB1Periph_TIM13             ((uint32_t)0x00000080)
+#define RCC_APB1Periph_TIM14             ((uint32_t)0x00000100)
+#define RCC_APB1Periph_WWDG              ((uint32_t)0x00000800)
+#define RCC_APB1Periph_SPI2              ((uint32_t)0x00004000)
+#define RCC_APB1Periph_SPI3              ((uint32_t)0x00008000)
+#define RCC_APB1Periph_USART2            ((uint32_t)0x00020000)
+#define RCC_APB1Periph_USART3            ((uint32_t)0x00040000)
+#define RCC_APB1Periph_UART4             ((uint32_t)0x00080000)
+#define RCC_APB1Periph_UART5             ((uint32_t)0x00100000)
+#define RCC_APB1Periph_I2C1              ((uint32_t)0x00200000)
+#define RCC_APB1Periph_I2C2              ((uint32_t)0x00400000)
+#define RCC_APB1Periph_I2C3              ((uint32_t)0x00800000)
+#define RCC_APB1Periph_CAN1              ((uint32_t)0x02000000)
+#define RCC_APB1Periph_CAN2              ((uint32_t)0x04000000)
+#define RCC_APB1Periph_PWR               ((uint32_t)0x10000000)
+#define RCC_APB1Periph_DAC               ((uint32_t)0x20000000)
+#define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0xC9013600) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_APB2_Peripherals 
+  * @{
+  */ 
+#define RCC_APB2Periph_TIM1              ((uint32_t)0x00000001)
+#define RCC_APB2Periph_TIM8              ((uint32_t)0x00000002)
+#define RCC_APB2Periph_USART1            ((uint32_t)0x00000010)
+#define RCC_APB2Periph_USART6            ((uint32_t)0x00000020)
+#define RCC_APB2Periph_ADC               ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC1              ((uint32_t)0x00000100)
+#define RCC_APB2Periph_ADC2              ((uint32_t)0x00000200)
+#define RCC_APB2Periph_ADC3              ((uint32_t)0x00000400)
+#define RCC_APB2Periph_SDIO              ((uint32_t)0x00000800)
+#define RCC_APB2Periph_SPI1              ((uint32_t)0x00001000)
+#define RCC_APB2Periph_SYSCFG            ((uint32_t)0x00004000)
+#define RCC_APB2Periph_TIM9              ((uint32_t)0x00010000)
+#define RCC_APB2Periph_TIM10             ((uint32_t)0x00020000)
+#define RCC_APB2Periph_TIM11             ((uint32_t)0x00040000)
+#define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A0CC) == 0x00) && ((PERIPH) != 0x00))
+#define IS_RCC_APB2_RESET_PERIPH(PERIPH) ((((PERIPH) & 0xFFF8A6CC) == 0x00) && ((PERIPH) != 0x00))
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_MCO1_Clock_Source_Prescaler
+  * @{
+  */
+#define RCC_MCO1Source_HSI               ((uint32_t)0x00000000)
+#define RCC_MCO1Source_LSE               ((uint32_t)0x00200000)
+#define RCC_MCO1Source_HSE               ((uint32_t)0x00400000)
+#define RCC_MCO1Source_PLLCLK            ((uint32_t)0x00600000)
+#define RCC_MCO1Div_1                    ((uint32_t)0x00000000)
+#define RCC_MCO1Div_2                    ((uint32_t)0x04000000)
+#define RCC_MCO1Div_3                    ((uint32_t)0x05000000)
+#define RCC_MCO1Div_4                    ((uint32_t)0x06000000)
+#define RCC_MCO1Div_5                    ((uint32_t)0x07000000)
+#define IS_RCC_MCO1SOURCE(SOURCE) (((SOURCE) == RCC_MCO1Source_HSI) || ((SOURCE) == RCC_MCO1Source_LSE) || \
+                                   ((SOURCE) == RCC_MCO1Source_HSE) || ((SOURCE) == RCC_MCO1Source_PLLCLK))
+                                   
+#define IS_RCC_MCO1DIV(DIV) (((DIV) == RCC_MCO1Div_1) || ((DIV) == RCC_MCO1Div_2) || \
+                             ((DIV) == RCC_MCO1Div_3) || ((DIV) == RCC_MCO1Div_4) || \
+                             ((DIV) == RCC_MCO1Div_5)) 
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_MCO2_Clock_Source_Prescaler
+  * @{
+  */
+#define RCC_MCO2Source_SYSCLK            ((uint32_t)0x00000000)
+#define RCC_MCO2Source_PLLI2SCLK         ((uint32_t)0x40000000)
+#define RCC_MCO2Source_HSE               ((uint32_t)0x80000000)
+#define RCC_MCO2Source_PLLCLK            ((uint32_t)0xC0000000)
+#define RCC_MCO2Div_1                    ((uint32_t)0x00000000)
+#define RCC_MCO2Div_2                    ((uint32_t)0x20000000)
+#define RCC_MCO2Div_3                    ((uint32_t)0x28000000)
+#define RCC_MCO2Div_4                    ((uint32_t)0x30000000)
+#define RCC_MCO2Div_5                    ((uint32_t)0x38000000)
+#define IS_RCC_MCO2SOURCE(SOURCE) (((SOURCE) == RCC_MCO2Source_SYSCLK) || ((SOURCE) == RCC_MCO2Source_PLLI2SCLK)|| \
+                                   ((SOURCE) == RCC_MCO2Source_HSE) || ((SOURCE) == RCC_MCO2Source_PLLCLK))
+                                   
+#define IS_RCC_MCO2DIV(DIV) (((DIV) == RCC_MCO2Div_1) || ((DIV) == RCC_MCO2Div_2) || \
+                             ((DIV) == RCC_MCO2Div_3) || ((DIV) == RCC_MCO2Div_4) || \
+                             ((DIV) == RCC_MCO2Div_5))                             
+/**
+  * @}
+  */ 
+  
+/** @defgroup RCC_Flag 
+  * @{
+  */
+#define RCC_FLAG_HSIRDY                  ((uint8_t)0x21)
+#define RCC_FLAG_HSERDY                  ((uint8_t)0x31)
+#define RCC_FLAG_PLLRDY                  ((uint8_t)0x39)
+#define RCC_FLAG_PLLI2SRDY               ((uint8_t)0x3B)
+#define RCC_FLAG_LSERDY                  ((uint8_t)0x41)
+#define RCC_FLAG_LSIRDY                  ((uint8_t)0x61)
+#define RCC_FLAG_BORRST                  ((uint8_t)0x79)
+#define RCC_FLAG_PINRST                  ((uint8_t)0x7A)
+#define RCC_FLAG_PORRST                  ((uint8_t)0x7B)
+#define RCC_FLAG_SFTRST                  ((uint8_t)0x7C)
+#define RCC_FLAG_IWDGRST                 ((uint8_t)0x7D)
+#define RCC_FLAG_WWDGRST                 ((uint8_t)0x7E)
+#define RCC_FLAG_LPWRRST                 ((uint8_t)0x7F)
+#define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
+                           ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
+                           ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_BORRST) || \
+                           ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
+                           ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
+                           ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
+                           ((FLAG) == RCC_FLAG_PLLI2SRDY))
+#define IS_RCC_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/* Function used to set the RCC clock configuration to the default reset state */
+void RCC_DeInit(void);
+
+/* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
+void RCC_HSEConfig(uint8_t RCC_HSE);
+ErrorStatus RCC_WaitForHSEStartUp(void);
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
+void RCC_HSICmd(FunctionalState NewState);
+void RCC_LSEConfig(uint8_t RCC_LSE);
+void RCC_LSICmd(FunctionalState NewState);
+
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ);
+void RCC_PLLCmd(FunctionalState NewState);
+void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR);
+void RCC_PLLI2SCmd(FunctionalState NewState);
+
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
+void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div);
+void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div);
+
+/* System, AHB and APB busses clocks configuration functions ******************/
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
+uint8_t RCC_GetSYSCLKSource(void);
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
+void RCC_PCLK1Config(uint32_t RCC_HCLK);
+void RCC_PCLK2Config(uint32_t RCC_HCLK);
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
+
+/* Peripheral clocks configuration functions **********************************/
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
+void RCC_RTCCLKCmd(FunctionalState NewState);
+void RCC_BackupResetCmd(FunctionalState NewState);
+void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource); 
+
+void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
+void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
+void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+
+void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
+void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
+void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+
+void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState);
+void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState);
+void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState);
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
+void RCC_ClearFlag(void);
+ITStatus RCC_GetITStatus(uint8_t RCC_IT);
+void RCC_ClearITPendingBit(uint8_t RCC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_RCC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h
new file mode 100644
index 0000000000..873b8abd64
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rng.h
@@ -0,0 +1,114 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_rng.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the Random 
+  *          Number Generator(RNG) firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_RNG_H
+#define __STM32F4xx_RNG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup RNG
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/ 
+
+/** @defgroup RNG_Exported_Constants
+  * @{
+  */
+  
+/** @defgroup RNG_flags_definition  
+  * @{
+  */ 
+#define RNG_FLAG_DRDY               ((uint8_t)0x0001) /*!< Data ready */
+#define RNG_FLAG_CECS               ((uint8_t)0x0002) /*!< Clock error current status */
+#define RNG_FLAG_SECS               ((uint8_t)0x0004) /*!< Seed error current status */
+
+#define IS_RNG_GET_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_DRDY) || \
+                                   ((RNG_FLAG) == RNG_FLAG_CECS) || \
+                                   ((RNG_FLAG) == RNG_FLAG_SECS))
+#define IS_RNG_CLEAR_FLAG(RNG_FLAG) (((RNG_FLAG) == RNG_FLAG_CECS) || \
+                                    ((RNG_FLAG) == RNG_FLAG_SECS))
+/**
+  * @}
+  */ 
+
+/** @defgroup RNG_interrupts_definition   
+  * @{
+  */  
+#define RNG_IT_CEI                  ((uint8_t)0x20) /*!< Clock error interrupt */
+#define RNG_IT_SEI                  ((uint8_t)0x40) /*!< Seed error interrupt */
+
+#define IS_RNG_IT(IT) ((((IT) & (uint8_t)0x9F) == 0x00) && ((IT) != 0x00))
+#define IS_RNG_GET_IT(RNG_IT) (((RNG_IT) == RNG_IT_CEI) || ((RNG_IT) == RNG_IT_SEI))
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/*  Function used to set the RNG configuration to the default reset state *****/ 
+void RNG_DeInit(void);
+
+/* Configuration function *****************************************************/
+void RNG_Cmd(FunctionalState NewState);
+
+/* Get 32 bit Random number function ******************************************/
+uint32_t RNG_GetRandomNumber(void);
+
+/* Interrupts and flags management functions **********************************/
+void RNG_ITConfig(FunctionalState NewState);
+FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG);
+void RNG_ClearFlag(uint8_t RNG_FLAG);
+ITStatus RNG_GetITStatus(uint8_t RNG_IT);
+void RNG_ClearITPendingBit(uint8_t RNG_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_RNG_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h
new file mode 100644
index 0000000000..125d9b8a6c
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_rtc.h
@@ -0,0 +1,875 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_rtc.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the RTC firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ****************************************************************************** 
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_RTC_H
+#define __STM32F4xx_RTC_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup RTC
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  RTC Init structures definition  
+  */ 
+typedef struct
+{
+  uint32_t RTC_HourFormat;   /*!< Specifies the RTC Hour Format.
+                             This parameter can be a value of @ref RTC_Hour_Formats */
+  
+  uint32_t RTC_AsynchPrediv; /*!< Specifies the RTC Asynchronous Predivider value.
+                             This parameter must be set to a value lower than 0x7F */
+  
+  uint32_t RTC_SynchPrediv;  /*!< Specifies the RTC Synchronous Predivider value.
+                             This parameter must be set to a value lower than 0x7FFF */
+}RTC_InitTypeDef;
+
+/** 
+  * @brief  RTC Time structure definition  
+  */
+typedef struct
+{
+  uint8_t RTC_Hours;    /*!< Specifies the RTC Time Hour.
+                        This parameter must be set to a value in the 0-12 range
+                        if the RTC_HourFormat_12 is selected or 0-23 range if
+                        the RTC_HourFormat_24 is selected. */
+
+  uint8_t RTC_Minutes;  /*!< Specifies the RTC Time Minutes.
+                        This parameter must be set to a value in the 0-59 range. */
+  
+  uint8_t RTC_Seconds;  /*!< Specifies the RTC Time Seconds.
+                        This parameter must be set to a value in the 0-59 range. */
+
+  uint8_t RTC_H12;      /*!< Specifies the RTC AM/PM Time.
+                        This parameter can be a value of @ref RTC_AM_PM_Definitions */
+}RTC_TimeTypeDef; 
+
+/** 
+  * @brief  RTC Date structure definition  
+  */
+typedef struct
+{
+  uint8_t RTC_WeekDay; /*!< Specifies the RTC Date WeekDay.
+                        This parameter can be a value of @ref RTC_WeekDay_Definitions */
+  
+  uint8_t RTC_Month;   /*!< Specifies the RTC Date Month (in BCD format).
+                        This parameter can be a value of @ref RTC_Month_Date_Definitions */
+
+  uint8_t RTC_Date;     /*!< Specifies the RTC Date.
+                        This parameter must be set to a value in the 1-31 range. */
+  
+  uint8_t RTC_Year;     /*!< Specifies the RTC Date Year.
+                        This parameter must be set to a value in the 0-99 range. */
+}RTC_DateTypeDef;
+
+/** 
+  * @brief  RTC Alarm structure definition  
+  */
+typedef struct
+{
+  RTC_TimeTypeDef RTC_AlarmTime;     /*!< Specifies the RTC Alarm Time members. */
+
+  uint32_t RTC_AlarmMask;            /*!< Specifies the RTC Alarm Masks.
+                                     This parameter can be a value of @ref RTC_AlarmMask_Definitions */
+
+  uint32_t RTC_AlarmDateWeekDaySel;  /*!< Specifies the RTC Alarm is on Date or WeekDay.
+                                     This parameter can be a value of @ref RTC_AlarmDateWeekDay_Definitions */
+  
+  uint8_t RTC_AlarmDateWeekDay;      /*!< Specifies the RTC Alarm Date/WeekDay.
+                                     If the Alarm Date is selected, this parameter
+                                     must be set to a value in the 1-31 range.
+                                     If the Alarm WeekDay is selected, this 
+                                     parameter can be a value of @ref RTC_WeekDay_Definitions */
+}RTC_AlarmTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup RTC_Exported_Constants
+  * @{
+  */ 
+
+
+/** @defgroup RTC_Hour_Formats 
+  * @{
+  */ 
+#define RTC_HourFormat_24              ((uint32_t)0x00000000)
+#define RTC_HourFormat_12              ((uint32_t)0x00000040)
+#define IS_RTC_HOUR_FORMAT(FORMAT)     (((FORMAT) == RTC_HourFormat_12) || \
+                                        ((FORMAT) == RTC_HourFormat_24))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Asynchronous_Predivider 
+  * @{
+  */ 
+#define IS_RTC_ASYNCH_PREDIV(PREDIV)   ((PREDIV) <= 0x7F)
+ 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_Synchronous_Predivider 
+  * @{
+  */ 
+#define IS_RTC_SYNCH_PREDIV(PREDIV)    ((PREDIV) <= 0x7FFF)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Time_Definitions 
+  * @{
+  */ 
+#define IS_RTC_HOUR12(HOUR)            (((HOUR) > 0) && ((HOUR) <= 12))
+#define IS_RTC_HOUR24(HOUR)            ((HOUR) <= 23)
+#define IS_RTC_MINUTES(MINUTES)        ((MINUTES) <= 59)
+#define IS_RTC_SECONDS(SECONDS)        ((SECONDS) <= 59)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_AM_PM_Definitions 
+  * @{
+  */ 
+#define RTC_H12_AM                     ((uint8_t)0x00)
+#define RTC_H12_PM                     ((uint8_t)0x40)
+#define IS_RTC_H12(PM) (((PM) == RTC_H12_AM) || ((PM) == RTC_H12_PM))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Year_Date_Definitions 
+  * @{
+  */ 
+#define IS_RTC_YEAR(YEAR)              ((YEAR) <= 99)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Month_Date_Definitions 
+  * @{
+  */ 
+
+/* Coded in BCD format */
+#define RTC_Month_January              ((uint8_t)0x01)
+#define RTC_Month_February             ((uint8_t)0x02)
+#define RTC_Month_March                ((uint8_t)0x03)
+#define RTC_Month_April                ((uint8_t)0x04)
+#define RTC_Month_May                  ((uint8_t)0x05)
+#define RTC_Month_June                 ((uint8_t)0x06)
+#define RTC_Month_July                 ((uint8_t)0x07)
+#define RTC_Month_August               ((uint8_t)0x08)
+#define RTC_Month_September            ((uint8_t)0x09)
+#define RTC_Month_October              ((uint8_t)0x10)
+#define RTC_Month_November             ((uint8_t)0x11)
+#define RTC_Month_December             ((uint8_t)0x12)
+#define IS_RTC_MONTH(MONTH)            (((MONTH) >= 1) && ((MONTH) <= 12))
+#define IS_RTC_DATE(DATE)              (((DATE) >= 1) && ((DATE) <= 31))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_WeekDay_Definitions 
+  * @{
+  */ 
+  
+#define RTC_Weekday_Monday             ((uint8_t)0x01)
+#define RTC_Weekday_Tuesday            ((uint8_t)0x02)
+#define RTC_Weekday_Wednesday          ((uint8_t)0x03)
+#define RTC_Weekday_Thursday           ((uint8_t)0x04)
+#define RTC_Weekday_Friday             ((uint8_t)0x05)
+#define RTC_Weekday_Saturday           ((uint8_t)0x06)
+#define RTC_Weekday_Sunday             ((uint8_t)0x07)
+#define IS_RTC_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Tuesday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Wednesday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Thursday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Friday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Saturday) || \
+                                 ((WEEKDAY) == RTC_Weekday_Sunday))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_Alarm_Definitions
+  * @{
+  */ 
+#define IS_RTC_ALARM_DATE_WEEKDAY_DATE(DATE) (((DATE) > 0) && ((DATE) <= 31))
+#define IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(WEEKDAY) (((WEEKDAY) == RTC_Weekday_Monday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Tuesday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Wednesday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Thursday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Friday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Saturday) || \
+                                                    ((WEEKDAY) == RTC_Weekday_Sunday))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_AlarmDateWeekDay_Definitions 
+  * @{
+  */ 
+#define RTC_AlarmDateWeekDaySel_Date      ((uint32_t)0x00000000)
+#define RTC_AlarmDateWeekDaySel_WeekDay   ((uint32_t)0x40000000)
+
+#define IS_RTC_ALARM_DATE_WEEKDAY_SEL(SEL) (((SEL) == RTC_AlarmDateWeekDaySel_Date) || \
+                                            ((SEL) == RTC_AlarmDateWeekDaySel_WeekDay))
+
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_AlarmMask_Definitions 
+  * @{
+  */ 
+#define RTC_AlarmMask_None                ((uint32_t)0x00000000)
+#define RTC_AlarmMask_DateWeekDay         ((uint32_t)0x80000000)
+#define RTC_AlarmMask_Hours               ((uint32_t)0x00800000)
+#define RTC_AlarmMask_Minutes             ((uint32_t)0x00008000)
+#define RTC_AlarmMask_Seconds             ((uint32_t)0x00000080)
+#define RTC_AlarmMask_All                 ((uint32_t)0x80808080)
+#define IS_ALARM_MASK(MASK)  (((MASK) & 0x7F7F7F7F) == (uint32_t)RESET)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Alarms_Definitions 
+  * @{
+  */ 
+#define RTC_Alarm_A                       ((uint32_t)0x00000100)
+#define RTC_Alarm_B                       ((uint32_t)0x00000200)
+#define IS_RTC_ALARM(ALARM)     (((ALARM) == RTC_Alarm_A) || ((ALARM) == RTC_Alarm_B))
+#define IS_RTC_CMD_ALARM(ALARM) (((ALARM) & (RTC_Alarm_A | RTC_Alarm_B)) != (uint32_t)RESET)
+
+/**
+  * @}
+  */ 
+
+  /** @defgroup RTC_Alarm_Sub_Seconds_Masks_Definitions
+  * @{
+  */ 
+#define RTC_AlarmSubSecondMask_All         ((uint32_t)0x00000000) /*!< All Alarm SS fields are masked. 
+                                                                       There is no comparison on sub seconds 
+                                                                       for Alarm */
+#define RTC_AlarmSubSecondMask_SS14_1      ((uint32_t)0x01000000) /*!< SS[14:1] are don't care in Alarm 
+                                                                       comparison. Only SS[0] is compared. */
+#define RTC_AlarmSubSecondMask_SS14_2      ((uint32_t)0x02000000) /*!< SS[14:2] are don't care in Alarm 
+                                                                       comparison. Only SS[1:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_3      ((uint32_t)0x03000000) /*!< SS[14:3] are don't care in Alarm 
+                                                                       comparison. Only SS[2:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_4      ((uint32_t)0x04000000) /*!< SS[14:4] are don't care in Alarm 
+                                                                       comparison. Only SS[3:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_5      ((uint32_t)0x05000000) /*!< SS[14:5] are don't care in Alarm 
+                                                                       comparison. Only SS[4:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_6      ((uint32_t)0x06000000) /*!< SS[14:6] are don't care in Alarm 
+                                                                       comparison. Only SS[5:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_7      ((uint32_t)0x07000000) /*!< SS[14:7] are don't care in Alarm 
+                                                                       comparison. Only SS[6:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_8      ((uint32_t)0x08000000) /*!< SS[14:8] are don't care in Alarm 
+                                                                       comparison. Only SS[7:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_9      ((uint32_t)0x09000000) /*!< SS[14:9] are don't care in Alarm 
+                                                                       comparison. Only SS[8:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_10     ((uint32_t)0x0A000000) /*!< SS[14:10] are don't care in Alarm 
+                                                                       comparison. Only SS[9:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_11     ((uint32_t)0x0B000000) /*!< SS[14:11] are don't care in Alarm 
+                                                                       comparison. Only SS[10:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_12     ((uint32_t)0x0C000000) /*!< SS[14:12] are don't care in Alarm 
+                                                                       comparison.Only SS[11:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14_13     ((uint32_t)0x0D000000) /*!< SS[14:13] are don't care in Alarm 
+                                                                       comparison. Only SS[12:0] are compared */
+#define RTC_AlarmSubSecondMask_SS14        ((uint32_t)0x0E000000) /*!< SS[14] is don't care in Alarm 
+                                                                       comparison.Only SS[13:0] are compared */
+#define RTC_AlarmSubSecondMask_None        ((uint32_t)0x0F000000) /*!< SS[14:0] are compared and must match 
+                                                                       to activate alarm. */
+#define IS_RTC_ALARM_SUB_SECOND_MASK(MASK)   (((MASK) == RTC_AlarmSubSecondMask_All) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_1) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_2) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_3) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_4) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_5) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_6) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_7) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_8) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_9) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_10) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_11) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_12) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14_13) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_SS14) || \
+                                              ((MASK) == RTC_AlarmSubSecondMask_None))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Alarm_Sub_Seconds_Value
+  * @{
+  */ 
+
+#define IS_RTC_ALARM_SUB_SECOND_VALUE(VALUE) ((VALUE) <= 0x00007FFF)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Wakeup_Timer_Definitions 
+  * @{
+  */ 
+#define RTC_WakeUpClock_RTCCLK_Div16        ((uint32_t)0x00000000)
+#define RTC_WakeUpClock_RTCCLK_Div8         ((uint32_t)0x00000001)
+#define RTC_WakeUpClock_RTCCLK_Div4         ((uint32_t)0x00000002)
+#define RTC_WakeUpClock_RTCCLK_Div2         ((uint32_t)0x00000003)
+#define RTC_WakeUpClock_CK_SPRE_16bits      ((uint32_t)0x00000004)
+#define RTC_WakeUpClock_CK_SPRE_17bits      ((uint32_t)0x00000006)
+#define IS_RTC_WAKEUP_CLOCK(CLOCK) (((CLOCK) == RTC_WakeUpClock_RTCCLK_Div16) || \
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div8) || \
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div4) || \
+                                    ((CLOCK) == RTC_WakeUpClock_RTCCLK_Div2) || \
+                                    ((CLOCK) == RTC_WakeUpClock_CK_SPRE_16bits) || \
+                                    ((CLOCK) == RTC_WakeUpClock_CK_SPRE_17bits))
+#define IS_RTC_WAKEUP_COUNTER(COUNTER)  ((COUNTER) <= 0xFFFF)
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Time_Stamp_Edges_definitions 
+  * @{
+  */ 
+#define RTC_TimeStampEdge_Rising          ((uint32_t)0x00000000)
+#define RTC_TimeStampEdge_Falling         ((uint32_t)0x00000008)
+#define IS_RTC_TIMESTAMP_EDGE(EDGE) (((EDGE) == RTC_TimeStampEdge_Rising) || \
+                                     ((EDGE) == RTC_TimeStampEdge_Falling))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Output_selection_Definitions 
+  * @{
+  */ 
+#define RTC_Output_Disable             ((uint32_t)0x00000000)
+#define RTC_Output_AlarmA              ((uint32_t)0x00200000)
+#define RTC_Output_AlarmB              ((uint32_t)0x00400000)
+#define RTC_Output_WakeUp              ((uint32_t)0x00600000)
+ 
+#define IS_RTC_OUTPUT(OUTPUT) (((OUTPUT) == RTC_Output_Disable) || \
+                               ((OUTPUT) == RTC_Output_AlarmA) || \
+                               ((OUTPUT) == RTC_Output_AlarmB) || \
+                               ((OUTPUT) == RTC_Output_WakeUp))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Output_Polarity_Definitions 
+  * @{
+  */ 
+#define RTC_OutputPolarity_High           ((uint32_t)0x00000000)
+#define RTC_OutputPolarity_Low            ((uint32_t)0x00100000)
+#define IS_RTC_OUTPUT_POL(POL) (((POL) == RTC_OutputPolarity_High) || \
+                                ((POL) == RTC_OutputPolarity_Low))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup RTC_Digital_Calibration_Definitions 
+  * @{
+  */ 
+#define RTC_CalibSign_Positive            ((uint32_t)0x00000000) 
+#define RTC_CalibSign_Negative            ((uint32_t)0x00000080)
+#define IS_RTC_CALIB_SIGN(SIGN) (((SIGN) == RTC_CalibSign_Positive) || \
+                                 ((SIGN) == RTC_CalibSign_Negative))
+#define IS_RTC_CALIB_VALUE(VALUE) ((VALUE) < 0x20)
+
+/**
+  * @}
+  */ 
+
+ /** @defgroup RTC_Calib_Output_selection_Definitions 
+  * @{
+  */ 
+#define RTC_CalibOutput_512Hz            ((uint32_t)0x00000000) 
+#define RTC_CalibOutput_1Hz              ((uint32_t)0x00080000)
+#define IS_RTC_CALIB_OUTPUT(OUTPUT)  (((OUTPUT) == RTC_CalibOutput_512Hz) || \
+                                      ((OUTPUT) == RTC_CalibOutput_1Hz))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_period_Definitions 
+  * @{
+  */ 
+#define RTC_SmoothCalibPeriod_32sec   ((uint32_t)0x00000000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation
+                                                             period is 32s,  else 2exp20 RTCCLK seconds */
+#define RTC_SmoothCalibPeriod_16sec   ((uint32_t)0x00002000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation 
+                                                             period is 16s, else 2exp19 RTCCLK seconds */
+#define RTC_SmoothCalibPeriod_8sec    ((uint32_t)0x00004000) /*!<  if RTCCLK = 32768 Hz, Smooth calibation 
+                                                             period is 8s, else 2exp18 RTCCLK seconds */
+#define IS_RTC_SMOOTH_CALIB_PERIOD(PERIOD) (((PERIOD) == RTC_SmoothCalibPeriod_32sec) || \
+                                             ((PERIOD) == RTC_SmoothCalibPeriod_16sec) || \
+                                             ((PERIOD) == RTC_SmoothCalibPeriod_8sec))
+                                          
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_Plus_pulses_Definitions 
+  * @{
+  */ 
+#define RTC_SmoothCalibPlusPulses_Set    ((uint32_t)0x00008000) /*!<  The number of RTCCLK pulses added  
+                                                                during a X -second window = Y - CALM[8:0]. 
+                                                                 with Y = 512, 256, 128 when X = 32, 16, 8 */
+#define RTC_SmoothCalibPlusPulses_Reset  ((uint32_t)0x00000000) /*!<  The number of RTCCLK pulses subbstited
+                                                                 during a 32-second window =   CALM[8:0]. */
+#define IS_RTC_SMOOTH_CALIB_PLUS(PLUS) (((PLUS) == RTC_SmoothCalibPlusPulses_Set) || \
+                                         ((PLUS) == RTC_SmoothCalibPlusPulses_Reset))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Smooth_calib_Minus_pulses_Definitions 
+  * @{
+  */ 
+#define  IS_RTC_SMOOTH_CALIB_MINUS(VALUE) ((VALUE) <= 0x000001FF)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_DayLightSaving_Definitions 
+  * @{
+  */ 
+#define RTC_DayLightSaving_SUB1H   ((uint32_t)0x00020000)
+#define RTC_DayLightSaving_ADD1H   ((uint32_t)0x00010000)
+#define IS_RTC_DAYLIGHT_SAVING(SAVE) (((SAVE) == RTC_DayLightSaving_SUB1H) || \
+                                      ((SAVE) == RTC_DayLightSaving_ADD1H))
+
+#define RTC_StoreOperation_Reset        ((uint32_t)0x00000000)
+#define RTC_StoreOperation_Set          ((uint32_t)0x00040000)
+#define IS_RTC_STORE_OPERATION(OPERATION) (((OPERATION) == RTC_StoreOperation_Reset) || \
+                                           ((OPERATION) == RTC_StoreOperation_Set))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Trigger_Definitions 
+  * @{
+  */ 
+#define RTC_TamperTrigger_RisingEdge            ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_FallingEdge           ((uint32_t)0x00000001)
+#define RTC_TamperTrigger_LowLevel              ((uint32_t)0x00000000)
+#define RTC_TamperTrigger_HighLevel             ((uint32_t)0x00000001)
+#define IS_RTC_TAMPER_TRIGGER(TRIGGER) (((TRIGGER) == RTC_TamperTrigger_RisingEdge) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_FallingEdge) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_LowLevel) || \
+                                        ((TRIGGER) == RTC_TamperTrigger_HighLevel)) 
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Filter_Definitions 
+  * @{
+  */ 
+#define RTC_TamperFilter_Disable   ((uint32_t)0x00000000) /*!< Tamper filter is disabled */
+
+#define RTC_TamperFilter_2Sample   ((uint32_t)0x00000800) /*!< Tamper is activated after 2 
+                                                          consecutive samples at the active level */
+#define RTC_TamperFilter_4Sample   ((uint32_t)0x00001000) /*!< Tamper is activated after 4 
+                                                          consecutive samples at the active level */
+#define RTC_TamperFilter_8Sample   ((uint32_t)0x00001800) /*!< Tamper is activated after 8 
+                                                          consecutive samples at the active leve. */
+#define IS_RTC_TAMPER_FILTER(FILTER) (((FILTER) == RTC_TamperFilter_Disable) || \
+                                      ((FILTER) == RTC_TamperFilter_2Sample) || \
+                                      ((FILTER) == RTC_TamperFilter_4Sample) || \
+                                      ((FILTER) == RTC_TamperFilter_8Sample))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Tamper_Sampling_Frequencies_Definitions 
+  * @{
+  */ 
+#define RTC_TamperSamplingFreq_RTCCLK_Div32768  ((uint32_t)0x00000000) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 32768 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div16384  ((uint32_t)0x000000100) /*!< Each of the tamper inputs are sampled
+                                                                            with a frequency =  RTCCLK / 16384 */
+#define RTC_TamperSamplingFreq_RTCCLK_Div8192   ((uint32_t)0x00000200) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 8192  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div4096   ((uint32_t)0x00000300) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 4096  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div2048   ((uint32_t)0x00000400) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 2048  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div1024   ((uint32_t)0x00000500) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 1024  */
+#define RTC_TamperSamplingFreq_RTCCLK_Div512    ((uint32_t)0x00000600) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 512   */
+#define RTC_TamperSamplingFreq_RTCCLK_Div256    ((uint32_t)0x00000700) /*!< Each of the tamper inputs are sampled
+                                                                           with a frequency =  RTCCLK / 256   */
+#define IS_RTC_TAMPER_SAMPLING_FREQ(FREQ) (((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div32768) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div16384) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div8192) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div4096) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div2048) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div1024) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div512) || \
+                                           ((FREQ) ==RTC_TamperSamplingFreq_RTCCLK_Div256))
+
+/**
+  * @}
+  */
+
+  /** @defgroup RTC_Tamper_Pin_Precharge_Duration_Definitions 
+  * @{
+  */ 
+#define RTC_TamperPrechargeDuration_1RTCCLK ((uint32_t)0x00000000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 1 RTCCLK cycle */
+#define RTC_TamperPrechargeDuration_2RTCCLK ((uint32_t)0x00002000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 2 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_4RTCCLK ((uint32_t)0x00004000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 4 RTCCLK cycles */
+#define RTC_TamperPrechargeDuration_8RTCCLK ((uint32_t)0x00006000)  /*!< Tamper pins are pre-charged before 
+                                                                         sampling during 8 RTCCLK cycles */
+
+#define IS_RTC_TAMPER_PRECHARGE_DURATION(DURATION) (((DURATION) == RTC_TamperPrechargeDuration_1RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_2RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_4RTCCLK) || \
+                                                    ((DURATION) == RTC_TamperPrechargeDuration_8RTCCLK))
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Tamper_Pins_Definitions 
+  * @{
+  */ 
+#define RTC_Tamper_1                    RTC_TAFCR_TAMP1E
+#define IS_RTC_TAMPER(TAMPER) (((TAMPER) == RTC_Tamper_1))
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Tamper_Pin_Selection 
+  * @{
+  */ 
+#define RTC_TamperPin_PC13                 ((uint32_t)0x00000000)
+#define RTC_TamperPin_PI8                  ((uint32_t)0x00010000)
+#define IS_RTC_TAMPER_PIN(PIN) (((PIN) == RTC_TamperPin_PC13) || \
+                                ((PIN) == RTC_TamperPin_PI8))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_TimeStamp_Pin_Selection 
+  * @{
+  */ 
+#define RTC_TimeStampPin_PC13              ((uint32_t)0x00000000)
+#define RTC_TimeStampPin_PI8               ((uint32_t)0x00020000)
+#define IS_RTC_TIMESTAMP_PIN(PIN) (((PIN) == RTC_TimeStampPin_PC13) || \
+                                   ((PIN) == RTC_TimeStampPin_PI8))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Output_Type_ALARM_OUT 
+  * @{
+  */ 
+#define RTC_OutputType_OpenDrain           ((uint32_t)0x00000000)
+#define RTC_OutputType_PushPull            ((uint32_t)0x00040000)
+#define IS_RTC_OUTPUT_TYPE(TYPE) (((TYPE) == RTC_OutputType_OpenDrain) || \
+                                  ((TYPE) == RTC_OutputType_PushPull))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Add_1_Second_Parameter_Definitions
+  * @{
+  */ 
+#define RTC_ShiftAdd1S_Reset      ((uint32_t)0x00000000)
+#define RTC_ShiftAdd1S_Set        ((uint32_t)0x80000000)
+#define IS_RTC_SHIFT_ADD1S(SEL) (((SEL) == RTC_ShiftAdd1S_Reset) || \
+                                 ((SEL) == RTC_ShiftAdd1S_Set))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Substract_Fraction_Of_Second_Value
+  * @{
+  */ 
+#define IS_RTC_SHIFT_SUBFS(FS) ((FS) <= 0x00007FFF)
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Backup_Registers_Definitions 
+  * @{
+  */
+
+#define RTC_BKP_DR0                       ((uint32_t)0x00000000)
+#define RTC_BKP_DR1                       ((uint32_t)0x00000001)
+#define RTC_BKP_DR2                       ((uint32_t)0x00000002)
+#define RTC_BKP_DR3                       ((uint32_t)0x00000003)
+#define RTC_BKP_DR4                       ((uint32_t)0x00000004)
+#define RTC_BKP_DR5                       ((uint32_t)0x00000005)
+#define RTC_BKP_DR6                       ((uint32_t)0x00000006)
+#define RTC_BKP_DR7                       ((uint32_t)0x00000007)
+#define RTC_BKP_DR8                       ((uint32_t)0x00000008)
+#define RTC_BKP_DR9                       ((uint32_t)0x00000009)
+#define RTC_BKP_DR10                      ((uint32_t)0x0000000A)
+#define RTC_BKP_DR11                      ((uint32_t)0x0000000B)
+#define RTC_BKP_DR12                      ((uint32_t)0x0000000C)
+#define RTC_BKP_DR13                      ((uint32_t)0x0000000D)
+#define RTC_BKP_DR14                      ((uint32_t)0x0000000E)
+#define RTC_BKP_DR15                      ((uint32_t)0x0000000F)
+#define RTC_BKP_DR16                      ((uint32_t)0x00000010)
+#define RTC_BKP_DR17                      ((uint32_t)0x00000011)
+#define RTC_BKP_DR18                      ((uint32_t)0x00000012)
+#define RTC_BKP_DR19                      ((uint32_t)0x00000013)
+#define IS_RTC_BKP(BKP)                   (((BKP) == RTC_BKP_DR0) || \
+                                           ((BKP) == RTC_BKP_DR1) || \
+                                           ((BKP) == RTC_BKP_DR2) || \
+                                           ((BKP) == RTC_BKP_DR3) || \
+                                           ((BKP) == RTC_BKP_DR4) || \
+                                           ((BKP) == RTC_BKP_DR5) || \
+                                           ((BKP) == RTC_BKP_DR6) || \
+                                           ((BKP) == RTC_BKP_DR7) || \
+                                           ((BKP) == RTC_BKP_DR8) || \
+                                           ((BKP) == RTC_BKP_DR9) || \
+                                           ((BKP) == RTC_BKP_DR10) || \
+                                           ((BKP) == RTC_BKP_DR11) || \
+                                           ((BKP) == RTC_BKP_DR12) || \
+                                           ((BKP) == RTC_BKP_DR13) || \
+                                           ((BKP) == RTC_BKP_DR14) || \
+                                           ((BKP) == RTC_BKP_DR15) || \
+                                           ((BKP) == RTC_BKP_DR16) || \
+                                           ((BKP) == RTC_BKP_DR17) || \
+                                           ((BKP) == RTC_BKP_DR18) || \
+                                           ((BKP) == RTC_BKP_DR19))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Input_parameter_format_definitions 
+  * @{
+  */ 
+#define RTC_Format_BIN                    ((uint32_t)0x000000000)
+#define RTC_Format_BCD                    ((uint32_t)0x000000001)
+#define IS_RTC_FORMAT(FORMAT) (((FORMAT) == RTC_Format_BIN) || ((FORMAT) == RTC_Format_BCD))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Flags_Definitions 
+  * @{
+  */ 
+#define RTC_FLAG_RECALPF                  ((uint32_t)0x00010000)
+#define RTC_FLAG_TAMP1F                   ((uint32_t)0x00002000)
+#define RTC_FLAG_TSOVF                    ((uint32_t)0x00001000)
+#define RTC_FLAG_TSF                      ((uint32_t)0x00000800)
+#define RTC_FLAG_WUTF                     ((uint32_t)0x00000400)
+#define RTC_FLAG_ALRBF                    ((uint32_t)0x00000200)
+#define RTC_FLAG_ALRAF                    ((uint32_t)0x00000100)
+#define RTC_FLAG_INITF                    ((uint32_t)0x00000040)
+#define RTC_FLAG_RSF                      ((uint32_t)0x00000020)
+#define RTC_FLAG_INITS                    ((uint32_t)0x00000010)
+#define RTC_FLAG_SHPF                     ((uint32_t)0x00000008)
+#define RTC_FLAG_WUTWF                    ((uint32_t)0x00000004)
+#define RTC_FLAG_ALRBWF                   ((uint32_t)0x00000002)
+#define RTC_FLAG_ALRAWF                   ((uint32_t)0x00000001)
+#define IS_RTC_GET_FLAG(FLAG) (((FLAG) == RTC_FLAG_TSOVF) || ((FLAG) == RTC_FLAG_TSF) || \
+                               ((FLAG) == RTC_FLAG_WUTF) || ((FLAG) == RTC_FLAG_ALRBF) || \
+                               ((FLAG) == RTC_FLAG_ALRAF) || ((FLAG) == RTC_FLAG_INITF) || \
+                               ((FLAG) == RTC_FLAG_RSF) || ((FLAG) == RTC_FLAG_WUTWF) || \
+                               ((FLAG) == RTC_FLAG_ALRBWF) || ((FLAG) == RTC_FLAG_ALRAWF) || \
+                               ((FLAG) == RTC_FLAG_TAMP1F) || ((FLAG) == RTC_FLAG_RECALPF) || \
+                                ((FLAG) == RTC_FLAG_SHPF))
+#define IS_RTC_CLEAR_FLAG(FLAG) (((FLAG) != (uint32_t)RESET) && (((FLAG) & 0xFFFF00DF) == (uint32_t)RESET))
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Interrupts_Definitions 
+  * @{
+  */ 
+#define RTC_IT_TS                         ((uint32_t)0x00008000)
+#define RTC_IT_WUT                        ((uint32_t)0x00004000)
+#define RTC_IT_ALRB                       ((uint32_t)0x00002000)
+#define RTC_IT_ALRA                       ((uint32_t)0x00001000)
+#define RTC_IT_TAMP                       ((uint32_t)0x00000004) /* Used only to Enable the Tamper Interrupt */
+#define RTC_IT_TAMP1                      ((uint32_t)0x00020000)
+
+#define IS_RTC_CONFIG_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFF0FFB) == (uint32_t)RESET))
+#define IS_RTC_GET_IT(IT) (((IT) == RTC_IT_TS) || ((IT) == RTC_IT_WUT) || \
+                           ((IT) == RTC_IT_ALRB) || ((IT) == RTC_IT_ALRA) || \
+                           ((IT) == RTC_IT_TAMP1))
+#define IS_RTC_CLEAR_IT(IT) (((IT) != (uint32_t)RESET) && (((IT) & 0xFFFD0FFF) == (uint32_t)RESET))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup RTC_Legacy 
+  * @{
+  */ 
+#define RTC_DigitalCalibConfig  RTC_CoarseCalibConfig
+#define RTC_DigitalCalibCmd     RTC_CoarseCalibCmd
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/*  Function used to set the RTC configuration to the default reset state *****/
+ErrorStatus RTC_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct);
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct);
+void RTC_WriteProtectionCmd(FunctionalState NewState);
+ErrorStatus RTC_EnterInitMode(void);
+void RTC_ExitInitMode(void);
+ErrorStatus RTC_WaitForSynchro(void);
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState);
+void RTC_BypassShadowCmd(FunctionalState NewState);
+
+/* Time and Date configuration functions **************************************/
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct);
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct);
+uint32_t RTC_GetSubSecond(void);
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct);
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct);
+
+/* Alarms (Alarm A and Alarm B) configuration functions  **********************/
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct);
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct);
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState);
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask);
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm);
+
+/* WakeUp Timer configuration functions ***************************************/
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock);
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter);
+uint32_t RTC_GetWakeUpCounter(void);
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState);
+
+/* Daylight Saving configuration functions ************************************/
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation);
+uint32_t RTC_GetStoreOperation(void);
+
+/* Output pin Configuration function ******************************************/
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity);
+
+/* Digital Calibration configuration functions *********************************/
+ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value);
+ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState);
+void RTC_CalibOutputCmd(FunctionalState NewState);
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput);
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod, 
+                                  uint32_t RTC_SmoothCalibPlusPulses,
+                                  uint32_t RTC_SmouthCalibMinusPulsesValue);
+
+/* TimeStamp configuration functions ******************************************/
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState);
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct,
+                                      RTC_DateTypeDef* RTC_StampDateStruct);
+uint32_t RTC_GetTimeStampSubSecond(void);
+
+/* Tampers configuration functions ********************************************/
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger);
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState);
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter);
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq);
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration);
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState);
+void RTC_TamperPullUpCmd(FunctionalState NewState);
+
+/* Backup Data Registers configuration functions ******************************/
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data);
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR);
+
+/* RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
+   functions ******************************************************************/
+void RTC_TamperPinSelection(uint32_t RTC_TamperPin);
+void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin);
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType);
+
+/* RTC_Shift_control_synchonisation_functions *********************************/
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS);
+
+/* Interrupts and flags management functions **********************************/
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState);
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG);
+void RTC_ClearFlag(uint32_t RTC_FLAG);
+ITStatus RTC_GetITStatus(uint32_t RTC_IT);
+void RTC_ClearITPendingBit(uint32_t RTC_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_RTC_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h
new file mode 100644
index 0000000000..7535e0fd28
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_sdio.h
@@ -0,0 +1,530 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_sdio.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the SDIO firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_SDIO_H
+#define __STM32F4xx_SDIO_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SDIO
+  * @{
+  */
+
+/* Exported types ------------------------------------------------------------*/
+
+typedef struct
+{
+  uint32_t SDIO_ClockEdge;            /*!< Specifies the clock transition on which the bit capture is made.
+                                           This parameter can be a value of @ref SDIO_Clock_Edge */
+
+  uint32_t SDIO_ClockBypass;          /*!< Specifies whether the SDIO Clock divider bypass is
+                                           enabled or disabled.
+                                           This parameter can be a value of @ref SDIO_Clock_Bypass */
+
+  uint32_t SDIO_ClockPowerSave;       /*!< Specifies whether SDIO Clock output is enabled or
+                                           disabled when the bus is idle.
+                                           This parameter can be a value of @ref SDIO_Clock_Power_Save */
+
+  uint32_t SDIO_BusWide;              /*!< Specifies the SDIO bus width.
+                                           This parameter can be a value of @ref SDIO_Bus_Wide */
+
+  uint32_t SDIO_HardwareFlowControl;  /*!< Specifies whether the SDIO hardware flow control is enabled or disabled.
+                                           This parameter can be a value of @ref SDIO_Hardware_Flow_Control */
+
+  uint8_t SDIO_ClockDiv;              /*!< Specifies the clock frequency of the SDIO controller.
+                                           This parameter can be a value between 0x00 and 0xFF. */
+                                           
+} SDIO_InitTypeDef;
+
+typedef struct
+{
+  uint32_t SDIO_Argument;  /*!< Specifies the SDIO command argument which is sent
+                                to a card as part of a command message. If a command
+                                contains an argument, it must be loaded into this register
+                                before writing the command to the command register */
+
+  uint32_t SDIO_CmdIndex;  /*!< Specifies the SDIO command index. It must be lower than 0x40. */
+
+  uint32_t SDIO_Response;  /*!< Specifies the SDIO response type.
+                                This parameter can be a value of @ref SDIO_Response_Type */
+
+  uint32_t SDIO_Wait;      /*!< Specifies whether SDIO wait-for-interrupt request is enabled or disabled.
+                                This parameter can be a value of @ref SDIO_Wait_Interrupt_State */
+
+  uint32_t SDIO_CPSM;      /*!< Specifies whether SDIO Command path state machine (CPSM)
+                                is enabled or disabled.
+                                This parameter can be a value of @ref SDIO_CPSM_State */
+} SDIO_CmdInitTypeDef;
+
+typedef struct
+{
+  uint32_t SDIO_DataTimeOut;    /*!< Specifies the data timeout period in card bus clock periods. */
+
+  uint32_t SDIO_DataLength;     /*!< Specifies the number of data bytes to be transferred. */
+ 
+  uint32_t SDIO_DataBlockSize;  /*!< Specifies the data block size for block transfer.
+                                     This parameter can be a value of @ref SDIO_Data_Block_Size */
+ 
+  uint32_t SDIO_TransferDir;    /*!< Specifies the data transfer direction, whether the transfer
+                                     is a read or write.
+                                     This parameter can be a value of @ref SDIO_Transfer_Direction */
+ 
+  uint32_t SDIO_TransferMode;   /*!< Specifies whether data transfer is in stream or block mode.
+                                     This parameter can be a value of @ref SDIO_Transfer_Type */
+ 
+  uint32_t SDIO_DPSM;           /*!< Specifies whether SDIO Data path state machine (DPSM)
+                                     is enabled or disabled.
+                                     This parameter can be a value of @ref SDIO_DPSM_State */
+} SDIO_DataInitTypeDef;
+
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SDIO_Exported_Constants
+  * @{
+  */
+
+/** @defgroup SDIO_Clock_Edge 
+  * @{
+  */
+
+#define SDIO_ClockEdge_Rising               ((uint32_t)0x00000000)
+#define SDIO_ClockEdge_Falling              ((uint32_t)0x00002000)
+#define IS_SDIO_CLOCK_EDGE(EDGE) (((EDGE) == SDIO_ClockEdge_Rising) || \
+                                  ((EDGE) == SDIO_ClockEdge_Falling))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Clock_Bypass 
+  * @{
+  */
+
+#define SDIO_ClockBypass_Disable             ((uint32_t)0x00000000)
+#define SDIO_ClockBypass_Enable              ((uint32_t)0x00000400)    
+#define IS_SDIO_CLOCK_BYPASS(BYPASS) (((BYPASS) == SDIO_ClockBypass_Disable) || \
+                                     ((BYPASS) == SDIO_ClockBypass_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Clock_Power_Save 
+  * @{
+  */
+
+#define SDIO_ClockPowerSave_Disable         ((uint32_t)0x00000000)
+#define SDIO_ClockPowerSave_Enable          ((uint32_t)0x00000200) 
+#define IS_SDIO_CLOCK_POWER_SAVE(SAVE) (((SAVE) == SDIO_ClockPowerSave_Disable) || \
+                                        ((SAVE) == SDIO_ClockPowerSave_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Bus_Wide 
+  * @{
+  */
+
+#define SDIO_BusWide_1b                     ((uint32_t)0x00000000)
+#define SDIO_BusWide_4b                     ((uint32_t)0x00000800)
+#define SDIO_BusWide_8b                     ((uint32_t)0x00001000)
+#define IS_SDIO_BUS_WIDE(WIDE) (((WIDE) == SDIO_BusWide_1b) || ((WIDE) == SDIO_BusWide_4b) || \
+                                ((WIDE) == SDIO_BusWide_8b))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Hardware_Flow_Control 
+  * @{
+  */
+
+#define SDIO_HardwareFlowControl_Disable    ((uint32_t)0x00000000)
+#define SDIO_HardwareFlowControl_Enable     ((uint32_t)0x00004000)
+#define IS_SDIO_HARDWARE_FLOW_CONTROL(CONTROL) (((CONTROL) == SDIO_HardwareFlowControl_Disable) || \
+                                                ((CONTROL) == SDIO_HardwareFlowControl_Enable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Power_State 
+  * @{
+  */
+
+#define SDIO_PowerState_OFF                 ((uint32_t)0x00000000)
+#define SDIO_PowerState_ON                  ((uint32_t)0x00000003)
+#define IS_SDIO_POWER_STATE(STATE) (((STATE) == SDIO_PowerState_OFF) || ((STATE) == SDIO_PowerState_ON))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup SDIO_Interrupt_sources
+  * @{
+  */
+
+#define SDIO_IT_CCRCFAIL                    ((uint32_t)0x00000001)
+#define SDIO_IT_DCRCFAIL                    ((uint32_t)0x00000002)
+#define SDIO_IT_CTIMEOUT                    ((uint32_t)0x00000004)
+#define SDIO_IT_DTIMEOUT                    ((uint32_t)0x00000008)
+#define SDIO_IT_TXUNDERR                    ((uint32_t)0x00000010)
+#define SDIO_IT_RXOVERR                     ((uint32_t)0x00000020)
+#define SDIO_IT_CMDREND                     ((uint32_t)0x00000040)
+#define SDIO_IT_CMDSENT                     ((uint32_t)0x00000080)
+#define SDIO_IT_DATAEND                     ((uint32_t)0x00000100)
+#define SDIO_IT_STBITERR                    ((uint32_t)0x00000200)
+#define SDIO_IT_DBCKEND                     ((uint32_t)0x00000400)
+#define SDIO_IT_CMDACT                      ((uint32_t)0x00000800)
+#define SDIO_IT_TXACT                       ((uint32_t)0x00001000)
+#define SDIO_IT_RXACT                       ((uint32_t)0x00002000)
+#define SDIO_IT_TXFIFOHE                    ((uint32_t)0x00004000)
+#define SDIO_IT_RXFIFOHF                    ((uint32_t)0x00008000)
+#define SDIO_IT_TXFIFOF                     ((uint32_t)0x00010000)
+#define SDIO_IT_RXFIFOF                     ((uint32_t)0x00020000)
+#define SDIO_IT_TXFIFOE                     ((uint32_t)0x00040000)
+#define SDIO_IT_RXFIFOE                     ((uint32_t)0x00080000)
+#define SDIO_IT_TXDAVL                      ((uint32_t)0x00100000)
+#define SDIO_IT_RXDAVL                      ((uint32_t)0x00200000)
+#define SDIO_IT_SDIOIT                      ((uint32_t)0x00400000)
+#define SDIO_IT_CEATAEND                    ((uint32_t)0x00800000)
+#define IS_SDIO_IT(IT) ((((IT) & (uint32_t)0xFF000000) == 0x00) && ((IT) != (uint32_t)0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Command_Index
+  * @{
+  */
+
+#define IS_SDIO_CMD_INDEX(INDEX)            ((INDEX) < 0x40)
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Response_Type
+  * @{
+  */
+
+#define SDIO_Response_No                    ((uint32_t)0x00000000)
+#define SDIO_Response_Short                 ((uint32_t)0x00000040)
+#define SDIO_Response_Long                  ((uint32_t)0x000000C0)
+#define IS_SDIO_RESPONSE(RESPONSE) (((RESPONSE) == SDIO_Response_No) || \
+                                    ((RESPONSE) == SDIO_Response_Short) || \
+                                    ((RESPONSE) == SDIO_Response_Long))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Wait_Interrupt_State
+  * @{
+  */
+
+#define SDIO_Wait_No                        ((uint32_t)0x00000000) /*!< SDIO No Wait, TimeOut is enabled */
+#define SDIO_Wait_IT                        ((uint32_t)0x00000100) /*!< SDIO Wait Interrupt Request */
+#define SDIO_Wait_Pend                      ((uint32_t)0x00000200) /*!< SDIO Wait End of transfer */
+#define IS_SDIO_WAIT(WAIT) (((WAIT) == SDIO_Wait_No) || ((WAIT) == SDIO_Wait_IT) || \
+                            ((WAIT) == SDIO_Wait_Pend))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_CPSM_State
+  * @{
+  */
+
+#define SDIO_CPSM_Disable                    ((uint32_t)0x00000000)
+#define SDIO_CPSM_Enable                     ((uint32_t)0x00000400)
+#define IS_SDIO_CPSM(CPSM) (((CPSM) == SDIO_CPSM_Enable) || ((CPSM) == SDIO_CPSM_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup SDIO_Response_Registers
+  * @{
+  */
+
+#define SDIO_RESP1                          ((uint32_t)0x00000000)
+#define SDIO_RESP2                          ((uint32_t)0x00000004)
+#define SDIO_RESP3                          ((uint32_t)0x00000008)
+#define SDIO_RESP4                          ((uint32_t)0x0000000C)
+#define IS_SDIO_RESP(RESP) (((RESP) == SDIO_RESP1) || ((RESP) == SDIO_RESP2) || \
+                            ((RESP) == SDIO_RESP3) || ((RESP) == SDIO_RESP4))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Data_Length 
+  * @{
+  */
+
+#define IS_SDIO_DATA_LENGTH(LENGTH) ((LENGTH) <= 0x01FFFFFF)
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Data_Block_Size 
+  * @{
+  */
+
+#define SDIO_DataBlockSize_1b               ((uint32_t)0x00000000)
+#define SDIO_DataBlockSize_2b               ((uint32_t)0x00000010)
+#define SDIO_DataBlockSize_4b               ((uint32_t)0x00000020)
+#define SDIO_DataBlockSize_8b               ((uint32_t)0x00000030)
+#define SDIO_DataBlockSize_16b              ((uint32_t)0x00000040)
+#define SDIO_DataBlockSize_32b              ((uint32_t)0x00000050)
+#define SDIO_DataBlockSize_64b              ((uint32_t)0x00000060)
+#define SDIO_DataBlockSize_128b             ((uint32_t)0x00000070)
+#define SDIO_DataBlockSize_256b             ((uint32_t)0x00000080)
+#define SDIO_DataBlockSize_512b             ((uint32_t)0x00000090)
+#define SDIO_DataBlockSize_1024b            ((uint32_t)0x000000A0)
+#define SDIO_DataBlockSize_2048b            ((uint32_t)0x000000B0)
+#define SDIO_DataBlockSize_4096b            ((uint32_t)0x000000C0)
+#define SDIO_DataBlockSize_8192b            ((uint32_t)0x000000D0)
+#define SDIO_DataBlockSize_16384b           ((uint32_t)0x000000E0)
+#define IS_SDIO_BLOCK_SIZE(SIZE) (((SIZE) == SDIO_DataBlockSize_1b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_2b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_4b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_8b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_16b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_32b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_64b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_128b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_256b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_512b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_1024b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_2048b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_4096b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_8192b) || \
+                                  ((SIZE) == SDIO_DataBlockSize_16384b)) 
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Transfer_Direction 
+  * @{
+  */
+
+#define SDIO_TransferDir_ToCard             ((uint32_t)0x00000000)
+#define SDIO_TransferDir_ToSDIO             ((uint32_t)0x00000002)
+#define IS_SDIO_TRANSFER_DIR(DIR) (((DIR) == SDIO_TransferDir_ToCard) || \
+                                   ((DIR) == SDIO_TransferDir_ToSDIO))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Transfer_Type 
+  * @{
+  */
+
+#define SDIO_TransferMode_Block             ((uint32_t)0x00000000)
+#define SDIO_TransferMode_Stream            ((uint32_t)0x00000004)
+#define IS_SDIO_TRANSFER_MODE(MODE) (((MODE) == SDIO_TransferMode_Stream) || \
+                                     ((MODE) == SDIO_TransferMode_Block))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_DPSM_State 
+  * @{
+  */
+
+#define SDIO_DPSM_Disable                    ((uint32_t)0x00000000)
+#define SDIO_DPSM_Enable                     ((uint32_t)0x00000001)
+#define IS_SDIO_DPSM(DPSM) (((DPSM) == SDIO_DPSM_Enable) || ((DPSM) == SDIO_DPSM_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Flags 
+  * @{
+  */
+
+#define SDIO_FLAG_CCRCFAIL                  ((uint32_t)0x00000001)
+#define SDIO_FLAG_DCRCFAIL                  ((uint32_t)0x00000002)
+#define SDIO_FLAG_CTIMEOUT                  ((uint32_t)0x00000004)
+#define SDIO_FLAG_DTIMEOUT                  ((uint32_t)0x00000008)
+#define SDIO_FLAG_TXUNDERR                  ((uint32_t)0x00000010)
+#define SDIO_FLAG_RXOVERR                   ((uint32_t)0x00000020)
+#define SDIO_FLAG_CMDREND                   ((uint32_t)0x00000040)
+#define SDIO_FLAG_CMDSENT                   ((uint32_t)0x00000080)
+#define SDIO_FLAG_DATAEND                   ((uint32_t)0x00000100)
+#define SDIO_FLAG_STBITERR                  ((uint32_t)0x00000200)
+#define SDIO_FLAG_DBCKEND                   ((uint32_t)0x00000400)
+#define SDIO_FLAG_CMDACT                    ((uint32_t)0x00000800)
+#define SDIO_FLAG_TXACT                     ((uint32_t)0x00001000)
+#define SDIO_FLAG_RXACT                     ((uint32_t)0x00002000)
+#define SDIO_FLAG_TXFIFOHE                  ((uint32_t)0x00004000)
+#define SDIO_FLAG_RXFIFOHF                  ((uint32_t)0x00008000)
+#define SDIO_FLAG_TXFIFOF                   ((uint32_t)0x00010000)
+#define SDIO_FLAG_RXFIFOF                   ((uint32_t)0x00020000)
+#define SDIO_FLAG_TXFIFOE                   ((uint32_t)0x00040000)
+#define SDIO_FLAG_RXFIFOE                   ((uint32_t)0x00080000)
+#define SDIO_FLAG_TXDAVL                    ((uint32_t)0x00100000)
+#define SDIO_FLAG_RXDAVL                    ((uint32_t)0x00200000)
+#define SDIO_FLAG_SDIOIT                    ((uint32_t)0x00400000)
+#define SDIO_FLAG_CEATAEND                  ((uint32_t)0x00800000)
+#define IS_SDIO_FLAG(FLAG) (((FLAG)  == SDIO_FLAG_CCRCFAIL) || \
+                            ((FLAG)  == SDIO_FLAG_DCRCFAIL) || \
+                            ((FLAG)  == SDIO_FLAG_CTIMEOUT) || \
+                            ((FLAG)  == SDIO_FLAG_DTIMEOUT) || \
+                            ((FLAG)  == SDIO_FLAG_TXUNDERR) || \
+                            ((FLAG)  == SDIO_FLAG_RXOVERR) || \
+                            ((FLAG)  == SDIO_FLAG_CMDREND) || \
+                            ((FLAG)  == SDIO_FLAG_CMDSENT) || \
+                            ((FLAG)  == SDIO_FLAG_DATAEND) || \
+                            ((FLAG)  == SDIO_FLAG_STBITERR) || \
+                            ((FLAG)  == SDIO_FLAG_DBCKEND) || \
+                            ((FLAG)  == SDIO_FLAG_CMDACT) || \
+                            ((FLAG)  == SDIO_FLAG_TXACT) || \
+                            ((FLAG)  == SDIO_FLAG_RXACT) || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOHE) || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOHF) || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOF) || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOF) || \
+                            ((FLAG)  == SDIO_FLAG_TXFIFOE) || \
+                            ((FLAG)  == SDIO_FLAG_RXFIFOE) || \
+                            ((FLAG)  == SDIO_FLAG_TXDAVL) || \
+                            ((FLAG)  == SDIO_FLAG_RXDAVL) || \
+                            ((FLAG)  == SDIO_FLAG_SDIOIT) || \
+                            ((FLAG)  == SDIO_FLAG_CEATAEND))
+
+#define IS_SDIO_CLEAR_FLAG(FLAG) ((((FLAG) & (uint32_t)0xFF3FF800) == 0x00) && ((FLAG) != (uint32_t)0x00))
+
+#define IS_SDIO_GET_IT(IT) (((IT)  == SDIO_IT_CCRCFAIL) || \
+                            ((IT)  == SDIO_IT_DCRCFAIL) || \
+                            ((IT)  == SDIO_IT_CTIMEOUT) || \
+                            ((IT)  == SDIO_IT_DTIMEOUT) || \
+                            ((IT)  == SDIO_IT_TXUNDERR) || \
+                            ((IT)  == SDIO_IT_RXOVERR) || \
+                            ((IT)  == SDIO_IT_CMDREND) || \
+                            ((IT)  == SDIO_IT_CMDSENT) || \
+                            ((IT)  == SDIO_IT_DATAEND) || \
+                            ((IT)  == SDIO_IT_STBITERR) || \
+                            ((IT)  == SDIO_IT_DBCKEND) || \
+                            ((IT)  == SDIO_IT_CMDACT) || \
+                            ((IT)  == SDIO_IT_TXACT) || \
+                            ((IT)  == SDIO_IT_RXACT) || \
+                            ((IT)  == SDIO_IT_TXFIFOHE) || \
+                            ((IT)  == SDIO_IT_RXFIFOHF) || \
+                            ((IT)  == SDIO_IT_TXFIFOF) || \
+                            ((IT)  == SDIO_IT_RXFIFOF) || \
+                            ((IT)  == SDIO_IT_TXFIFOE) || \
+                            ((IT)  == SDIO_IT_RXFIFOE) || \
+                            ((IT)  == SDIO_IT_TXDAVL) || \
+                            ((IT)  == SDIO_IT_RXDAVL) || \
+                            ((IT)  == SDIO_IT_SDIOIT) || \
+                            ((IT)  == SDIO_IT_CEATAEND))
+
+#define IS_SDIO_CLEAR_IT(IT) ((((IT) & (uint32_t)0xFF3FF800) == 0x00) && ((IT) != (uint32_t)0x00))
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Read_Wait_Mode 
+  * @{
+  */
+
+#define SDIO_ReadWaitMode_CLK               ((uint32_t)0x00000000)
+#define SDIO_ReadWaitMode_DATA2             ((uint32_t)0x00000001)
+#define IS_SDIO_READWAIT_MODE(MODE) (((MODE) == SDIO_ReadWaitMode_CLK) || \
+                                     ((MODE) == SDIO_ReadWaitMode_DATA2))
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+/*  Function used to set the SDIO configuration to the default reset state ****/
+void SDIO_DeInit(void);
+
+/* Initialization and Configuration functions *********************************/
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct);
+void SDIO_ClockCmd(FunctionalState NewState);
+void SDIO_SetPowerState(uint32_t SDIO_PowerState);
+uint32_t SDIO_GetPowerState(void);
+
+/* Command path state machine (CPSM) management functions *********************/
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct);
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct);
+uint8_t SDIO_GetCommandResponse(void);
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP);
+
+/* Data path state machine (DPSM) management functions ************************/
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct);
+uint32_t SDIO_GetDataCounter(void);
+uint32_t SDIO_ReadData(void);
+void SDIO_WriteData(uint32_t Data);
+uint32_t SDIO_GetFIFOCount(void);
+
+/* SDIO IO Cards mode management functions ************************************/
+void SDIO_StartSDIOReadWait(FunctionalState NewState);
+void SDIO_StopSDIOReadWait(FunctionalState NewState);
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode);
+void SDIO_SetSDIOOperation(FunctionalState NewState);
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState);
+
+/* CE-ATA mode management functions *******************************************/
+void SDIO_CommandCompletionCmd(FunctionalState NewState);
+void SDIO_CEATAITCmd(FunctionalState NewState);
+void SDIO_SendCEATACmd(FunctionalState NewState);
+
+/* DMA transfers management functions *****************************************/
+void SDIO_DMACmd(FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState);
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG);
+void SDIO_ClearFlag(uint32_t SDIO_FLAG);
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT);
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_SDIO_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h
new file mode 100644
index 0000000000..9787f01d0f
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_spi.h
@@ -0,0 +1,537 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_spi.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the SPI 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************  
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_SPI_H
+#define __STM32F4xx_SPI_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SPI
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  SPI Init structure definition  
+  */
+
+typedef struct
+{
+  uint16_t SPI_Direction;           /*!< Specifies the SPI unidirectional or bidirectional data mode.
+                                         This parameter can be a value of @ref SPI_data_direction */
+
+  uint16_t SPI_Mode;                /*!< Specifies the SPI operating mode.
+                                         This parameter can be a value of @ref SPI_mode */
+
+  uint16_t SPI_DataSize;            /*!< Specifies the SPI data size.
+                                         This parameter can be a value of @ref SPI_data_size */
+
+  uint16_t SPI_CPOL;                /*!< Specifies the serial clock steady state.
+                                         This parameter can be a value of @ref SPI_Clock_Polarity */
+
+  uint16_t SPI_CPHA;                /*!< Specifies the clock active edge for the bit capture.
+                                         This parameter can be a value of @ref SPI_Clock_Phase */
+
+  uint16_t SPI_NSS;                 /*!< Specifies whether the NSS signal is managed by
+                                         hardware (NSS pin) or by software using the SSI bit.
+                                         This parameter can be a value of @ref SPI_Slave_Select_management */
+ 
+  uint16_t SPI_BaudRatePrescaler;   /*!< Specifies the Baud Rate prescaler value which will be
+                                         used to configure the transmit and receive SCK clock.
+                                         This parameter can be a value of @ref SPI_BaudRate_Prescaler
+                                         @note The communication clock is derived from the master
+                                               clock. The slave clock does not need to be set. */
+
+  uint16_t SPI_FirstBit;            /*!< Specifies whether data transfers start from MSB or LSB bit.
+                                         This parameter can be a value of @ref SPI_MSB_LSB_transmission */
+
+  uint16_t SPI_CRCPolynomial;       /*!< Specifies the polynomial used for the CRC calculation. */
+}SPI_InitTypeDef;
+
+/** 
+  * @brief  I2S Init structure definition  
+  */
+
+typedef struct
+{
+
+  uint16_t I2S_Mode;         /*!< Specifies the I2S operating mode.
+                                  This parameter can be a value of @ref I2S_Mode */
+
+  uint16_t I2S_Standard;     /*!< Specifies the standard used for the I2S communication.
+                                  This parameter can be a value of @ref I2S_Standard */
+
+  uint16_t I2S_DataFormat;   /*!< Specifies the data format for the I2S communication.
+                                  This parameter can be a value of @ref I2S_Data_Format */
+
+  uint16_t I2S_MCLKOutput;   /*!< Specifies whether the I2S MCLK output is enabled or not.
+                                  This parameter can be a value of @ref I2S_MCLK_Output */
+
+  uint32_t I2S_AudioFreq;    /*!< Specifies the frequency selected for the I2S communication.
+                                  This parameter can be a value of @ref I2S_Audio_Frequency */
+
+  uint16_t I2S_CPOL;         /*!< Specifies the idle state of the I2S clock.
+                                  This parameter can be a value of @ref I2S_Clock_Polarity */
+}I2S_InitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup SPI_Exported_Constants
+  * @{
+  */
+
+#define IS_SPI_ALL_PERIPH(PERIPH) (((PERIPH) == SPI1) || \
+                                   ((PERIPH) == SPI2) || \
+                                   ((PERIPH) == SPI3))
+
+#define IS_SPI_ALL_PERIPH_EXT(PERIPH) (((PERIPH) == SPI1) || \
+                                       ((PERIPH) == SPI2) || \
+                                       ((PERIPH) == SPI3) || \
+                                       ((PERIPH) == I2S2ext) || \
+                                       ((PERIPH) == I2S3ext))
+
+#define IS_SPI_23_PERIPH(PERIPH)  (((PERIPH) == SPI2) || \
+                                   ((PERIPH) == SPI3))
+
+#define IS_SPI_23_PERIPH_EXT(PERIPH)  (((PERIPH) == SPI2) || \
+                                       ((PERIPH) == SPI3) || \
+                                       ((PERIPH) == I2S2ext) || \
+                                       ((PERIPH) == I2S3ext))
+
+#define IS_I2S_EXT_PERIPH(PERIPH)  (((PERIPH) == I2S2ext) || \
+                                    ((PERIPH) == I2S2ext))
+
+
+/** @defgroup SPI_data_direction 
+  * @{
+  */
+  
+#define SPI_Direction_2Lines_FullDuplex ((uint16_t)0x0000)
+#define SPI_Direction_2Lines_RxOnly     ((uint16_t)0x0400)
+#define SPI_Direction_1Line_Rx          ((uint16_t)0x8000)
+#define SPI_Direction_1Line_Tx          ((uint16_t)0xC000)
+#define IS_SPI_DIRECTION_MODE(MODE) (((MODE) == SPI_Direction_2Lines_FullDuplex) || \
+                                     ((MODE) == SPI_Direction_2Lines_RxOnly) || \
+                                     ((MODE) == SPI_Direction_1Line_Rx) || \
+                                     ((MODE) == SPI_Direction_1Line_Tx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_mode 
+  * @{
+  */
+
+#define SPI_Mode_Master                 ((uint16_t)0x0104)
+#define SPI_Mode_Slave                  ((uint16_t)0x0000)
+#define IS_SPI_MODE(MODE) (((MODE) == SPI_Mode_Master) || \
+                           ((MODE) == SPI_Mode_Slave))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_data_size 
+  * @{
+  */
+
+#define SPI_DataSize_16b                ((uint16_t)0x0800)
+#define SPI_DataSize_8b                 ((uint16_t)0x0000)
+#define IS_SPI_DATASIZE(DATASIZE) (((DATASIZE) == SPI_DataSize_16b) || \
+                                   ((DATASIZE) == SPI_DataSize_8b))
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_Clock_Polarity 
+  * @{
+  */
+
+#define SPI_CPOL_Low                    ((uint16_t)0x0000)
+#define SPI_CPOL_High                   ((uint16_t)0x0002)
+#define IS_SPI_CPOL(CPOL) (((CPOL) == SPI_CPOL_Low) || \
+                           ((CPOL) == SPI_CPOL_High))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Clock_Phase 
+  * @{
+  */
+
+#define SPI_CPHA_1Edge                  ((uint16_t)0x0000)
+#define SPI_CPHA_2Edge                  ((uint16_t)0x0001)
+#define IS_SPI_CPHA(CPHA) (((CPHA) == SPI_CPHA_1Edge) || \
+                           ((CPHA) == SPI_CPHA_2Edge))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Slave_Select_management 
+  * @{
+  */
+
+#define SPI_NSS_Soft                    ((uint16_t)0x0200)
+#define SPI_NSS_Hard                    ((uint16_t)0x0000)
+#define IS_SPI_NSS(NSS) (((NSS) == SPI_NSS_Soft) || \
+                         ((NSS) == SPI_NSS_Hard))
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_BaudRate_Prescaler 
+  * @{
+  */
+
+#define SPI_BaudRatePrescaler_2         ((uint16_t)0x0000)
+#define SPI_BaudRatePrescaler_4         ((uint16_t)0x0008)
+#define SPI_BaudRatePrescaler_8         ((uint16_t)0x0010)
+#define SPI_BaudRatePrescaler_16        ((uint16_t)0x0018)
+#define SPI_BaudRatePrescaler_32        ((uint16_t)0x0020)
+#define SPI_BaudRatePrescaler_64        ((uint16_t)0x0028)
+#define SPI_BaudRatePrescaler_128       ((uint16_t)0x0030)
+#define SPI_BaudRatePrescaler_256       ((uint16_t)0x0038)
+#define IS_SPI_BAUDRATE_PRESCALER(PRESCALER) (((PRESCALER) == SPI_BaudRatePrescaler_2) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_4) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_8) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_16) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_32) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_64) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_128) || \
+                                              ((PRESCALER) == SPI_BaudRatePrescaler_256))
+/**
+  * @}
+  */ 
+
+/** @defgroup SPI_MSB_LSB_transmission 
+  * @{
+  */
+
+#define SPI_FirstBit_MSB                ((uint16_t)0x0000)
+#define SPI_FirstBit_LSB                ((uint16_t)0x0080)
+#define IS_SPI_FIRST_BIT(BIT) (((BIT) == SPI_FirstBit_MSB) || \
+                               ((BIT) == SPI_FirstBit_LSB))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Mode 
+  * @{
+  */
+
+#define I2S_Mode_SlaveTx                ((uint16_t)0x0000)
+#define I2S_Mode_SlaveRx                ((uint16_t)0x0100)
+#define I2S_Mode_MasterTx               ((uint16_t)0x0200)
+#define I2S_Mode_MasterRx               ((uint16_t)0x0300)
+#define IS_I2S_MODE(MODE) (((MODE) == I2S_Mode_SlaveTx) || \
+                           ((MODE) == I2S_Mode_SlaveRx) || \
+                           ((MODE) == I2S_Mode_MasterTx)|| \
+                           ((MODE) == I2S_Mode_MasterRx))
+/**
+  * @}
+  */
+  
+
+/** @defgroup SPI_I2S_Standard 
+  * @{
+  */
+
+#define I2S_Standard_Phillips           ((uint16_t)0x0000)
+#define I2S_Standard_MSB                ((uint16_t)0x0010)
+#define I2S_Standard_LSB                ((uint16_t)0x0020)
+#define I2S_Standard_PCMShort           ((uint16_t)0x0030)
+#define I2S_Standard_PCMLong            ((uint16_t)0x00B0)
+#define IS_I2S_STANDARD(STANDARD) (((STANDARD) == I2S_Standard_Phillips) || \
+                                   ((STANDARD) == I2S_Standard_MSB) || \
+                                   ((STANDARD) == I2S_Standard_LSB) || \
+                                   ((STANDARD) == I2S_Standard_PCMShort) || \
+                                   ((STANDARD) == I2S_Standard_PCMLong))
+/**
+  * @}
+  */
+  
+/** @defgroup SPI_I2S_Data_Format 
+  * @{
+  */
+
+#define I2S_DataFormat_16b              ((uint16_t)0x0000)
+#define I2S_DataFormat_16bextended      ((uint16_t)0x0001)
+#define I2S_DataFormat_24b              ((uint16_t)0x0003)
+#define I2S_DataFormat_32b              ((uint16_t)0x0005)
+#define IS_I2S_DATA_FORMAT(FORMAT) (((FORMAT) == I2S_DataFormat_16b) || \
+                                    ((FORMAT) == I2S_DataFormat_16bextended) || \
+                                    ((FORMAT) == I2S_DataFormat_24b) || \
+                                    ((FORMAT) == I2S_DataFormat_32b))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_MCLK_Output 
+  * @{
+  */
+
+#define I2S_MCLKOutput_Enable           ((uint16_t)0x0200)
+#define I2S_MCLKOutput_Disable          ((uint16_t)0x0000)
+#define IS_I2S_MCLK_OUTPUT(OUTPUT) (((OUTPUT) == I2S_MCLKOutput_Enable) || \
+                                    ((OUTPUT) == I2S_MCLKOutput_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Audio_Frequency 
+  * @{
+  */
+
+#define I2S_AudioFreq_192k               ((uint32_t)192000)
+#define I2S_AudioFreq_96k                ((uint32_t)96000)
+#define I2S_AudioFreq_48k                ((uint32_t)48000)
+#define I2S_AudioFreq_44k                ((uint32_t)44100)
+#define I2S_AudioFreq_32k                ((uint32_t)32000)
+#define I2S_AudioFreq_22k                ((uint32_t)22050)
+#define I2S_AudioFreq_16k                ((uint32_t)16000)
+#define I2S_AudioFreq_11k                ((uint32_t)11025)
+#define I2S_AudioFreq_8k                 ((uint32_t)8000)
+#define I2S_AudioFreq_Default            ((uint32_t)2)
+
+#define IS_I2S_AUDIO_FREQ(FREQ) ((((FREQ) >= I2S_AudioFreq_8k) && \
+                                 ((FREQ) <= I2S_AudioFreq_192k)) || \
+                                 ((FREQ) == I2S_AudioFreq_Default))
+/**
+  * @}
+  */
+            
+/** @defgroup SPI_I2S_Clock_Polarity 
+  * @{
+  */
+
+#define I2S_CPOL_Low                    ((uint16_t)0x0000)
+#define I2S_CPOL_High                   ((uint16_t)0x0008)
+#define IS_I2S_CPOL(CPOL) (((CPOL) == I2S_CPOL_Low) || \
+                           ((CPOL) == I2S_CPOL_High))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_DMA_transfer_requests 
+  * @{
+  */
+
+#define SPI_I2S_DMAReq_Tx               ((uint16_t)0x0002)
+#define SPI_I2S_DMAReq_Rx               ((uint16_t)0x0001)
+#define IS_SPI_I2S_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFFFC) == 0x00) && ((DMAREQ) != 0x00))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_NSS_internal_software_management 
+  * @{
+  */
+
+#define SPI_NSSInternalSoft_Set         ((uint16_t)0x0100)
+#define SPI_NSSInternalSoft_Reset       ((uint16_t)0xFEFF)
+#define IS_SPI_NSS_INTERNAL(INTERNAL) (((INTERNAL) == SPI_NSSInternalSoft_Set) || \
+                                       ((INTERNAL) == SPI_NSSInternalSoft_Reset))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_Transmit_Receive 
+  * @{
+  */
+
+#define SPI_CRC_Tx                      ((uint8_t)0x00)
+#define SPI_CRC_Rx                      ((uint8_t)0x01)
+#define IS_SPI_CRC(CRC) (((CRC) == SPI_CRC_Tx) || ((CRC) == SPI_CRC_Rx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_direction_transmit_receive 
+  * @{
+  */
+
+#define SPI_Direction_Rx                ((uint16_t)0xBFFF)
+#define SPI_Direction_Tx                ((uint16_t)0x4000)
+#define IS_SPI_DIRECTION(DIRECTION) (((DIRECTION) == SPI_Direction_Rx) || \
+                                     ((DIRECTION) == SPI_Direction_Tx))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_interrupts_definition 
+  * @{
+  */
+
+#define SPI_I2S_IT_TXE                  ((uint8_t)0x71)
+#define SPI_I2S_IT_RXNE                 ((uint8_t)0x60)
+#define SPI_I2S_IT_ERR                  ((uint8_t)0x50)
+#define I2S_IT_UDR                      ((uint8_t)0x53)
+#define SPI_I2S_IT_TIFRFE               ((uint8_t)0x58)
+
+#define IS_SPI_I2S_CONFIG_IT(IT) (((IT) == SPI_I2S_IT_TXE) || \
+                                  ((IT) == SPI_I2S_IT_RXNE) || \
+                                  ((IT) == SPI_I2S_IT_ERR))
+
+#define SPI_I2S_IT_OVR                  ((uint8_t)0x56)
+#define SPI_IT_MODF                     ((uint8_t)0x55)
+#define SPI_IT_CRCERR                   ((uint8_t)0x54)
+
+#define IS_SPI_I2S_CLEAR_IT(IT) (((IT) == SPI_IT_CRCERR))
+
+#define IS_SPI_I2S_GET_IT(IT) (((IT) == SPI_I2S_IT_RXNE)|| ((IT) == SPI_I2S_IT_TXE) || \
+                               ((IT) == SPI_IT_CRCERR)  || ((IT) == SPI_IT_MODF) || \
+                               ((IT) == SPI_I2S_IT_OVR) || ((IT) == I2S_IT_UDR) ||\
+                               ((IT) == SPI_I2S_IT_TIFRFE))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_flags_definition 
+  * @{
+  */
+
+#define SPI_I2S_FLAG_RXNE               ((uint16_t)0x0001)
+#define SPI_I2S_FLAG_TXE                ((uint16_t)0x0002)
+#define I2S_FLAG_CHSIDE                 ((uint16_t)0x0004)
+#define I2S_FLAG_UDR                    ((uint16_t)0x0008)
+#define SPI_FLAG_CRCERR                 ((uint16_t)0x0010)
+#define SPI_FLAG_MODF                   ((uint16_t)0x0020)
+#define SPI_I2S_FLAG_OVR                ((uint16_t)0x0040)
+#define SPI_I2S_FLAG_BSY                ((uint16_t)0x0080)
+#define SPI_I2S_FLAG_TIFRFE             ((uint16_t)0x0100)
+
+#define IS_SPI_I2S_CLEAR_FLAG(FLAG) (((FLAG) == SPI_FLAG_CRCERR))
+#define IS_SPI_I2S_GET_FLAG(FLAG) (((FLAG) == SPI_I2S_FLAG_BSY) || ((FLAG) == SPI_I2S_FLAG_OVR) || \
+                                   ((FLAG) == SPI_FLAG_MODF) || ((FLAG) == SPI_FLAG_CRCERR) || \
+                                   ((FLAG) == I2S_FLAG_UDR) || ((FLAG) == I2S_FLAG_CHSIDE) || \
+                                   ((FLAG) == SPI_I2S_FLAG_TXE) || ((FLAG) == SPI_I2S_FLAG_RXNE)|| \
+                                   ((FLAG) == SPI_I2S_FLAG_TIFRFE))
+/**
+  * @}
+  */
+
+/** @defgroup SPI_CRC_polynomial 
+  * @{
+  */
+
+#define IS_SPI_CRC_POLYNOMIAL(POLYNOMIAL) ((POLYNOMIAL) >= 0x1)
+/**
+  * @}
+  */
+
+/** @defgroup SPI_I2S_Legacy 
+  * @{
+  */
+
+#define SPI_DMAReq_Tx                SPI_I2S_DMAReq_Tx
+#define SPI_DMAReq_Rx                SPI_I2S_DMAReq_Rx
+#define SPI_IT_TXE                   SPI_I2S_IT_TXE
+#define SPI_IT_RXNE                  SPI_I2S_IT_RXNE
+#define SPI_IT_ERR                   SPI_I2S_IT_ERR
+#define SPI_IT_OVR                   SPI_I2S_IT_OVR
+#define SPI_FLAG_RXNE                SPI_I2S_FLAG_RXNE
+#define SPI_FLAG_TXE                 SPI_I2S_FLAG_TXE
+#define SPI_FLAG_OVR                 SPI_I2S_FLAG_OVR
+#define SPI_FLAG_BSY                 SPI_I2S_FLAG_BSY
+#define SPI_DeInit                   SPI_I2S_DeInit
+#define SPI_ITConfig                 SPI_I2S_ITConfig
+#define SPI_DMACmd                   SPI_I2S_DMACmd
+#define SPI_SendData                 SPI_I2S_SendData
+#define SPI_ReceiveData              SPI_I2S_ReceiveData
+#define SPI_GetFlagStatus            SPI_I2S_GetFlagStatus
+#define SPI_ClearFlag                SPI_I2S_ClearFlag
+#define SPI_GetITStatus              SPI_I2S_GetITStatus
+#define SPI_ClearITPendingBit        SPI_I2S_ClearITPendingBit
+/**
+  * @}
+  */
+  
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/*  Function used to set the SPI configuration to the default reset state *****/ 
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx);
+
+/* Initialization and Configuration functions *********************************/
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct);
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct);
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct);
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct);
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize);
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction);
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft);
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState);
+
+void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct);
+
+/* Data transfers functions ***************************************************/ 
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data);
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx);
+
+/* Hardware CRC Calculation functions *****************************************/
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState);
+void SPI_TransmitCRC(SPI_TypeDef* SPIx);
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC);
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx);
+
+/* DMA transfers management functions *****************************************/
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_SPI_H */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h
new file mode 100644
index 0000000000..b5299dbc2f
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_syscfg.h
@@ -0,0 +1,173 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_syscfg.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the SYSCFG firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_SYSCFG_H
+#define __STM32F4xx_SYSCFG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup SYSCFG
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+  
+/** @defgroup SYSCFG_Exported_Constants 
+  * @{
+  */ 
+
+/** @defgroup SYSCFG_EXTI_Port_Sources 
+  * @{
+  */ 
+#define EXTI_PortSourceGPIOA       ((uint8_t)0x00)
+#define EXTI_PortSourceGPIOB       ((uint8_t)0x01)
+#define EXTI_PortSourceGPIOC       ((uint8_t)0x02)
+#define EXTI_PortSourceGPIOD       ((uint8_t)0x03)
+#define EXTI_PortSourceGPIOE       ((uint8_t)0x04)
+#define EXTI_PortSourceGPIOF       ((uint8_t)0x05)
+#define EXTI_PortSourceGPIOG       ((uint8_t)0x06)
+#define EXTI_PortSourceGPIOH       ((uint8_t)0x07)
+#define EXTI_PortSourceGPIOI       ((uint8_t)0x08)
+                                      
+#define IS_EXTI_PORT_SOURCE(PORTSOURCE) (((PORTSOURCE) == EXTI_PortSourceGPIOA) || \
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOB) || \
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOC) || \
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOD) || \
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOE) || \
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOF) || \
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOG) || \
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOH) || \
+                                        ((PORTSOURCE) == EXTI_PortSourceGPIOI)) 
+/**
+  * @}
+  */ 
+
+
+/** @defgroup SYSCFG_EXTI_Pin_Sources 
+  * @{
+  */ 
+#define EXTI_PinSource0            ((uint8_t)0x00)
+#define EXTI_PinSource1            ((uint8_t)0x01)
+#define EXTI_PinSource2            ((uint8_t)0x02)
+#define EXTI_PinSource3            ((uint8_t)0x03)
+#define EXTI_PinSource4            ((uint8_t)0x04)
+#define EXTI_PinSource5            ((uint8_t)0x05)
+#define EXTI_PinSource6            ((uint8_t)0x06)
+#define EXTI_PinSource7            ((uint8_t)0x07)
+#define EXTI_PinSource8            ((uint8_t)0x08)
+#define EXTI_PinSource9            ((uint8_t)0x09)
+#define EXTI_PinSource10           ((uint8_t)0x0A)
+#define EXTI_PinSource11           ((uint8_t)0x0B)
+#define EXTI_PinSource12           ((uint8_t)0x0C)
+#define EXTI_PinSource13           ((uint8_t)0x0D)
+#define EXTI_PinSource14           ((uint8_t)0x0E)
+#define EXTI_PinSource15           ((uint8_t)0x0F)
+#define IS_EXTI_PIN_SOURCE(PINSOURCE) (((PINSOURCE) == EXTI_PinSource0) || \
+                                       ((PINSOURCE) == EXTI_PinSource1) || \
+                                       ((PINSOURCE) == EXTI_PinSource2) || \
+                                       ((PINSOURCE) == EXTI_PinSource3) || \
+                                       ((PINSOURCE) == EXTI_PinSource4) || \
+                                       ((PINSOURCE) == EXTI_PinSource5) || \
+                                       ((PINSOURCE) == EXTI_PinSource6) || \
+                                       ((PINSOURCE) == EXTI_PinSource7) || \
+                                       ((PINSOURCE) == EXTI_PinSource8) || \
+                                       ((PINSOURCE) == EXTI_PinSource9) || \
+                                       ((PINSOURCE) == EXTI_PinSource10) || \
+                                       ((PINSOURCE) == EXTI_PinSource11) || \
+                                       ((PINSOURCE) == EXTI_PinSource12) || \
+                                       ((PINSOURCE) == EXTI_PinSource13) || \
+                                       ((PINSOURCE) == EXTI_PinSource14) || \
+                                       ((PINSOURCE) == EXTI_PinSource15))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup SYSCFG_Memory_Remap_Config 
+  * @{
+  */ 
+#define SYSCFG_MemoryRemap_Flash       ((uint8_t)0x00)
+#define SYSCFG_MemoryRemap_SystemFlash ((uint8_t)0x01)
+#define SYSCFG_MemoryRemap_FSMC        ((uint8_t)0x02)
+#define SYSCFG_MemoryRemap_SRAM        ((uint8_t)0x03)
+   
+#define IS_SYSCFG_MEMORY_REMAP_CONFING(REMAP) (((REMAP) == SYSCFG_MemoryRemap_Flash) || \
+                                                     ((REMAP) == SYSCFG_MemoryRemap_SystemFlash) || \
+                                                     ((REMAP) == SYSCFG_MemoryRemap_SRAM) || \
+                                                     ((REMAP) == SYSCFG_MemoryRemap_FSMC))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup SYSCFG_ETHERNET_Media_Interface 
+  * @{
+  */ 
+#define SYSCFG_ETH_MediaInterface_MII    ((uint32_t)0x00000000) 
+#define SYSCFG_ETH_MediaInterface_RMII   ((uint32_t)0x00000001)                                       
+
+#define IS_SYSCFG_ETH_MEDIA_INTERFACE(INTERFACE) (((INTERFACE) == SYSCFG_ETH_MediaInterface_MII) || \
+                                                ((INTERFACE) == SYSCFG_ETH_MediaInterface_RMII))
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+ 
+void SYSCFG_DeInit(void);
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap);
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex);
+void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface); 
+void SYSCFG_CompensationCellCmd(FunctionalState NewState); 
+FlagStatus SYSCFG_GetCompensationCellStatus(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_SYSCFG_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h
new file mode 100644
index 0000000000..3798fc9e0a
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_tim.h
@@ -0,0 +1,1144 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_tim.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the TIM firmware 
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_TIM_H
+#define __STM32F4xx_TIM_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup TIM
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+
+/** 
+  * @brief  TIM Time Base Init structure definition  
+  * @note   This structure is used with all TIMx except for TIM6 and TIM7.  
+  */
+
+typedef struct
+{
+  uint16_t TIM_Prescaler;         /*!< Specifies the prescaler value used to divide the TIM clock.
+                                       This parameter can be a number between 0x0000 and 0xFFFF */
+
+  uint16_t TIM_CounterMode;       /*!< Specifies the counter mode.
+                                       This parameter can be a value of @ref TIM_Counter_Mode */
+
+  uint32_t TIM_Period;            /*!< Specifies the period value to be loaded into the active
+                                       Auto-Reload Register at the next update event.
+                                       This parameter must be a number between 0x0000 and 0xFFFF.  */ 
+
+  uint16_t TIM_ClockDivision;     /*!< Specifies the clock division.
+                                      This parameter can be a value of @ref TIM_Clock_Division_CKD */
+
+  uint8_t TIM_RepetitionCounter;  /*!< Specifies the repetition counter value. Each time the RCR downcounter
+                                       reaches zero, an update event is generated and counting restarts
+                                       from the RCR value (N).
+                                       This means in PWM mode that (N+1) corresponds to:
+                                          - the number of PWM periods in edge-aligned mode
+                                          - the number of half PWM period in center-aligned mode
+                                       This parameter must be a number between 0x00 and 0xFF. 
+                                       @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_TimeBaseInitTypeDef; 
+
+/** 
+  * @brief  TIM Output Compare Init structure definition  
+  */
+
+typedef struct
+{
+  uint16_t TIM_OCMode;        /*!< Specifies the TIM mode.
+                                   This parameter can be a value of @ref TIM_Output_Compare_and_PWM_modes */
+
+  uint16_t TIM_OutputState;   /*!< Specifies the TIM Output Compare state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_State */
+
+  uint16_t TIM_OutputNState;  /*!< Specifies the TIM complementary Output Compare state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_State
+                                   @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint32_t TIM_Pulse;         /*!< Specifies the pulse value to be loaded into the Capture Compare Register. 
+                                   This parameter can be a number between 0x0000 and 0xFFFF */
+
+  uint16_t TIM_OCPolarity;    /*!< Specifies the output polarity.
+                                   This parameter can be a value of @ref TIM_Output_Compare_Polarity */
+
+  uint16_t TIM_OCNPolarity;   /*!< Specifies the complementary output polarity.
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_Polarity
+                                   @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint16_t TIM_OCIdleState;   /*!< Specifies the TIM Output Compare pin state during Idle state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_Idle_State
+                                   @note This parameter is valid only for TIM1 and TIM8. */
+
+  uint16_t TIM_OCNIdleState;  /*!< Specifies the TIM Output Compare pin state during Idle state.
+                                   This parameter can be a value of @ref TIM_Output_Compare_N_Idle_State
+                                   @note This parameter is valid only for TIM1 and TIM8. */
+} TIM_OCInitTypeDef;
+
+/** 
+  * @brief  TIM Input Capture Init structure definition  
+  */
+
+typedef struct
+{
+
+  uint16_t TIM_Channel;      /*!< Specifies the TIM channel.
+                                  This parameter can be a value of @ref TIM_Channel */
+
+  uint16_t TIM_ICPolarity;   /*!< Specifies the active edge of the input signal.
+                                  This parameter can be a value of @ref TIM_Input_Capture_Polarity */
+
+  uint16_t TIM_ICSelection;  /*!< Specifies the input.
+                                  This parameter can be a value of @ref TIM_Input_Capture_Selection */
+
+  uint16_t TIM_ICPrescaler;  /*!< Specifies the Input Capture Prescaler.
+                                  This parameter can be a value of @ref TIM_Input_Capture_Prescaler */
+
+  uint16_t TIM_ICFilter;     /*!< Specifies the input capture filter.
+                                  This parameter can be a number between 0x0 and 0xF */
+} TIM_ICInitTypeDef;
+
+/** 
+  * @brief  BDTR structure definition 
+  * @note   This structure is used only with TIM1 and TIM8.    
+  */
+
+typedef struct
+{
+
+  uint16_t TIM_OSSRState;        /*!< Specifies the Off-State selection used in Run mode.
+                                      This parameter can be a value of @ref TIM_OSSR_Off_State_Selection_for_Run_mode_state */
+
+  uint16_t TIM_OSSIState;        /*!< Specifies the Off-State used in Idle state.
+                                      This parameter can be a value of @ref TIM_OSSI_Off_State_Selection_for_Idle_mode_state */
+
+  uint16_t TIM_LOCKLevel;        /*!< Specifies the LOCK level parameters.
+                                      This parameter can be a value of @ref TIM_Lock_level */ 
+
+  uint16_t TIM_DeadTime;         /*!< Specifies the delay time between the switching-off and the
+                                      switching-on of the outputs.
+                                      This parameter can be a number between 0x00 and 0xFF  */
+
+  uint16_t TIM_Break;            /*!< Specifies whether the TIM Break input is enabled or not. 
+                                      This parameter can be a value of @ref TIM_Break_Input_enable_disable */
+
+  uint16_t TIM_BreakPolarity;    /*!< Specifies the TIM Break Input pin polarity.
+                                      This parameter can be a value of @ref TIM_Break_Polarity */
+
+  uint16_t TIM_AutomaticOutput;  /*!< Specifies whether the TIM Automatic Output feature is enabled or not. 
+                                      This parameter can be a value of @ref TIM_AOE_Bit_Set_Reset */
+} TIM_BDTRInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup TIM_Exported_constants 
+  * @{
+  */
+
+#define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                   ((PERIPH) == TIM2) || \
+                                   ((PERIPH) == TIM3) || \
+                                   ((PERIPH) == TIM4) || \
+                                   ((PERIPH) == TIM5) || \
+                                   ((PERIPH) == TIM6) || \
+                                   ((PERIPH) == TIM7) || \
+                                   ((PERIPH) == TIM8) || \
+                                   ((PERIPH) == TIM9) || \
+                                   ((PERIPH) == TIM10) || \
+                                   ((PERIPH) == TIM11) || \
+                                   ((PERIPH) == TIM12) || \
+                                   (((PERIPH) == TIM13) || \
+                                   ((PERIPH) == TIM14)))
+/* LIST1: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9, TIM10, TIM11, TIM12, TIM13 and TIM14 */                                         
+#define IS_TIM_LIST1_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM4) || \
+                                     ((PERIPH) == TIM5) || \
+                                     ((PERIPH) == TIM8) || \
+                                     ((PERIPH) == TIM9) || \
+                                     ((PERIPH) == TIM10) || \
+                                     ((PERIPH) == TIM11) || \
+                                     ((PERIPH) == TIM12) || \
+                                     ((PERIPH) == TIM13) || \
+                                     ((PERIPH) == TIM14))
+                                     
+/* LIST2: TIM1, TIM2, TIM3, TIM4, TIM5, TIM8, TIM9 and TIM12 */
+#define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM4) || \
+                                     ((PERIPH) == TIM5) || \
+                                     ((PERIPH) == TIM8) || \
+                                     ((PERIPH) == TIM9) || \
+                                     ((PERIPH) == TIM12))
+/* LIST3: TIM1, TIM2, TIM3, TIM4, TIM5 and TIM8 */
+#define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM4) || \
+                                     ((PERIPH) == TIM5) || \
+                                     ((PERIPH) == TIM8))
+/* LIST4: TIM1 and TIM8 */
+#define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM8))
+/* LIST5: TIM1, TIM2, TIM3, TIM4, TIM5, TIM6, TIM7 and TIM8 */
+#define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
+                                     ((PERIPH) == TIM2) || \
+                                     ((PERIPH) == TIM3) || \
+                                     ((PERIPH) == TIM4) || \
+                                     ((PERIPH) == TIM5) || \
+                                     ((PERIPH) == TIM6) || \
+                                     ((PERIPH) == TIM7) || \
+                                     ((PERIPH) == TIM8))
+/* LIST6: TIM2, TIM5 and TIM11 */                               
+#define IS_TIM_LIST6_PERIPH(TIMx)(((TIMx) == TIM2) || \
+                                 ((TIMx) == TIM5) || \
+                                 ((TIMx) == TIM11))
+
+/** @defgroup TIM_Output_Compare_and_PWM_modes 
+  * @{
+  */
+
+#define TIM_OCMode_Timing                  ((uint16_t)0x0000)
+#define TIM_OCMode_Active                  ((uint16_t)0x0010)
+#define TIM_OCMode_Inactive                ((uint16_t)0x0020)
+#define TIM_OCMode_Toggle                  ((uint16_t)0x0030)
+#define TIM_OCMode_PWM1                    ((uint16_t)0x0060)
+#define TIM_OCMode_PWM2                    ((uint16_t)0x0070)
+#define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
+                              ((MODE) == TIM_OCMode_Active) || \
+                              ((MODE) == TIM_OCMode_Inactive) || \
+                              ((MODE) == TIM_OCMode_Toggle)|| \
+                              ((MODE) == TIM_OCMode_PWM1) || \
+                              ((MODE) == TIM_OCMode_PWM2))
+#define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
+                          ((MODE) == TIM_OCMode_Active) || \
+                          ((MODE) == TIM_OCMode_Inactive) || \
+                          ((MODE) == TIM_OCMode_Toggle)|| \
+                          ((MODE) == TIM_OCMode_PWM1) || \
+                          ((MODE) == TIM_OCMode_PWM2) ||	\
+                          ((MODE) == TIM_ForcedAction_Active) || \
+                          ((MODE) == TIM_ForcedAction_InActive))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_One_Pulse_Mode 
+  * @{
+  */
+
+#define TIM_OPMode_Single                  ((uint16_t)0x0008)
+#define TIM_OPMode_Repetitive              ((uint16_t)0x0000)
+#define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
+                               ((MODE) == TIM_OPMode_Repetitive))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Channel 
+  * @{
+  */
+
+#define TIM_Channel_1                      ((uint16_t)0x0000)
+#define TIM_Channel_2                      ((uint16_t)0x0004)
+#define TIM_Channel_3                      ((uint16_t)0x0008)
+#define TIM_Channel_4                      ((uint16_t)0x000C)
+                                 
+#define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+                                 ((CHANNEL) == TIM_Channel_2) || \
+                                 ((CHANNEL) == TIM_Channel_3) || \
+                                 ((CHANNEL) == TIM_Channel_4))
+                                 
+#define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+                                      ((CHANNEL) == TIM_Channel_2))
+#define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
+                                               ((CHANNEL) == TIM_Channel_2) || \
+                                               ((CHANNEL) == TIM_Channel_3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Clock_Division_CKD 
+  * @{
+  */
+
+#define TIM_CKD_DIV1                       ((uint16_t)0x0000)
+#define TIM_CKD_DIV2                       ((uint16_t)0x0100)
+#define TIM_CKD_DIV4                       ((uint16_t)0x0200)
+#define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
+                             ((DIV) == TIM_CKD_DIV2) || \
+                             ((DIV) == TIM_CKD_DIV4))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Counter_Mode 
+  * @{
+  */
+
+#define TIM_CounterMode_Up                 ((uint16_t)0x0000)
+#define TIM_CounterMode_Down               ((uint16_t)0x0010)
+#define TIM_CounterMode_CenterAligned1     ((uint16_t)0x0020)
+#define TIM_CounterMode_CenterAligned2     ((uint16_t)0x0040)
+#define TIM_CounterMode_CenterAligned3     ((uint16_t)0x0060)
+#define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) ||  \
+                                   ((MODE) == TIM_CounterMode_Down) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned1) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned2) || \
+                                   ((MODE) == TIM_CounterMode_CenterAligned3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Polarity 
+  * @{
+  */
+
+#define TIM_OCPolarity_High                ((uint16_t)0x0000)
+#define TIM_OCPolarity_Low                 ((uint16_t)0x0002)
+#define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
+                                      ((POLARITY) == TIM_OCPolarity_Low))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_N_Polarity 
+  * @{
+  */
+  
+#define TIM_OCNPolarity_High               ((uint16_t)0x0000)
+#define TIM_OCNPolarity_Low                ((uint16_t)0x0008)
+#define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
+                                       ((POLARITY) == TIM_OCNPolarity_Low))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Output_Compare_State 
+  * @{
+  */
+
+#define TIM_OutputState_Disable            ((uint16_t)0x0000)
+#define TIM_OutputState_Enable             ((uint16_t)0x0001)
+#define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
+                                    ((STATE) == TIM_OutputState_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_N_State
+  * @{
+  */
+
+#define TIM_OutputNState_Disable           ((uint16_t)0x0000)
+#define TIM_OutputNState_Enable            ((uint16_t)0x0004)
+#define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
+                                     ((STATE) == TIM_OutputNState_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Capture_Compare_State
+  * @{
+  */
+
+#define TIM_CCx_Enable                      ((uint16_t)0x0001)
+#define TIM_CCx_Disable                     ((uint16_t)0x0000)
+#define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
+                         ((CCX) == TIM_CCx_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Capture_Compare_N_State
+  * @{
+  */
+
+#define TIM_CCxN_Enable                     ((uint16_t)0x0004)
+#define TIM_CCxN_Disable                    ((uint16_t)0x0000)
+#define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
+                           ((CCXN) == TIM_CCxN_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Break_Input_enable_disable 
+  * @{
+  */
+
+#define TIM_Break_Enable                   ((uint16_t)0x1000)
+#define TIM_Break_Disable                  ((uint16_t)0x0000)
+#define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
+                                   ((STATE) == TIM_Break_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Break_Polarity 
+  * @{
+  */
+
+#define TIM_BreakPolarity_Low              ((uint16_t)0x0000)
+#define TIM_BreakPolarity_High             ((uint16_t)0x2000)
+#define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
+                                         ((POLARITY) == TIM_BreakPolarity_High))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_AOE_Bit_Set_Reset 
+  * @{
+  */
+
+#define TIM_AutomaticOutput_Enable         ((uint16_t)0x4000)
+#define TIM_AutomaticOutput_Disable        ((uint16_t)0x0000)
+#define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
+                                              ((STATE) == TIM_AutomaticOutput_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Lock_level
+  * @{
+  */
+
+#define TIM_LOCKLevel_OFF                  ((uint16_t)0x0000)
+#define TIM_LOCKLevel_1                    ((uint16_t)0x0100)
+#define TIM_LOCKLevel_2                    ((uint16_t)0x0200)
+#define TIM_LOCKLevel_3                    ((uint16_t)0x0300)
+#define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
+                                  ((LEVEL) == TIM_LOCKLevel_1) || \
+                                  ((LEVEL) == TIM_LOCKLevel_2) || \
+                                  ((LEVEL) == TIM_LOCKLevel_3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_OSSI_Off_State_Selection_for_Idle_mode_state 
+  * @{
+  */
+
+#define TIM_OSSIState_Enable               ((uint16_t)0x0400)
+#define TIM_OSSIState_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
+                                  ((STATE) == TIM_OSSIState_Disable))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_OSSR_Off_State_Selection_for_Run_mode_state
+  * @{
+  */
+
+#define TIM_OSSRState_Enable               ((uint16_t)0x0800)
+#define TIM_OSSRState_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
+                                  ((STATE) == TIM_OSSRState_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Idle_State 
+  * @{
+  */
+
+#define TIM_OCIdleState_Set                ((uint16_t)0x0100)
+#define TIM_OCIdleState_Reset              ((uint16_t)0x0000)
+#define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
+                                    ((STATE) == TIM_OCIdleState_Reset))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_N_Idle_State 
+  * @{
+  */
+
+#define TIM_OCNIdleState_Set               ((uint16_t)0x0200)
+#define TIM_OCNIdleState_Reset             ((uint16_t)0x0000)
+#define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
+                                     ((STATE) == TIM_OCNIdleState_Reset))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Input_Capture_Polarity 
+  * @{
+  */
+
+#define  TIM_ICPolarity_Rising             ((uint16_t)0x0000)
+#define  TIM_ICPolarity_Falling            ((uint16_t)0x0002)
+#define  TIM_ICPolarity_BothEdge           ((uint16_t)0x000A)
+#define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
+                                      ((POLARITY) == TIM_ICPolarity_Falling)|| \
+                                      ((POLARITY) == TIM_ICPolarity_BothEdge))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Input_Capture_Selection 
+  * @{
+  */
+
+#define TIM_ICSelection_DirectTI           ((uint16_t)0x0001) /*!< TIM Input 1, 2, 3 or 4 is selected to be 
+                                                                   connected to IC1, IC2, IC3 or IC4, respectively */
+#define TIM_ICSelection_IndirectTI         ((uint16_t)0x0002) /*!< TIM Input 1, 2, 3 or 4 is selected to be
+                                                                   connected to IC2, IC1, IC4 or IC3, respectively. */
+#define TIM_ICSelection_TRC                ((uint16_t)0x0003) /*!< TIM Input 1, 2, 3 or 4 is selected to be connected to TRC. */
+#define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
+                                        ((SELECTION) == TIM_ICSelection_IndirectTI) || \
+                                        ((SELECTION) == TIM_ICSelection_TRC))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Input_Capture_Prescaler 
+  * @{
+  */
+
+#define TIM_ICPSC_DIV1                     ((uint16_t)0x0000) /*!< Capture performed each time an edge is detected on the capture input. */
+#define TIM_ICPSC_DIV2                     ((uint16_t)0x0004) /*!< Capture performed once every 2 events. */
+#define TIM_ICPSC_DIV4                     ((uint16_t)0x0008) /*!< Capture performed once every 4 events. */
+#define TIM_ICPSC_DIV8                     ((uint16_t)0x000C) /*!< Capture performed once every 8 events. */
+#define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV2) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV4) || \
+                                        ((PRESCALER) == TIM_ICPSC_DIV8))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_interrupt_sources 
+  * @{
+  */
+
+#define TIM_IT_Update                      ((uint16_t)0x0001)
+#define TIM_IT_CC1                         ((uint16_t)0x0002)
+#define TIM_IT_CC2                         ((uint16_t)0x0004)
+#define TIM_IT_CC3                         ((uint16_t)0x0008)
+#define TIM_IT_CC4                         ((uint16_t)0x0010)
+#define TIM_IT_COM                         ((uint16_t)0x0020)
+#define TIM_IT_Trigger                     ((uint16_t)0x0040)
+#define TIM_IT_Break                       ((uint16_t)0x0080)
+#define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
+
+#define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
+                           ((IT) == TIM_IT_CC1) || \
+                           ((IT) == TIM_IT_CC2) || \
+                           ((IT) == TIM_IT_CC3) || \
+                           ((IT) == TIM_IT_CC4) || \
+                           ((IT) == TIM_IT_COM) || \
+                           ((IT) == TIM_IT_Trigger) || \
+                           ((IT) == TIM_IT_Break))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_DMA_Base_address 
+  * @{
+  */
+
+#define TIM_DMABase_CR1                    ((uint16_t)0x0000)
+#define TIM_DMABase_CR2                    ((uint16_t)0x0001)
+#define TIM_DMABase_SMCR                   ((uint16_t)0x0002)
+#define TIM_DMABase_DIER                   ((uint16_t)0x0003)
+#define TIM_DMABase_SR                     ((uint16_t)0x0004)
+#define TIM_DMABase_EGR                    ((uint16_t)0x0005)
+#define TIM_DMABase_CCMR1                  ((uint16_t)0x0006)
+#define TIM_DMABase_CCMR2                  ((uint16_t)0x0007)
+#define TIM_DMABase_CCER                   ((uint16_t)0x0008)
+#define TIM_DMABase_CNT                    ((uint16_t)0x0009)
+#define TIM_DMABase_PSC                    ((uint16_t)0x000A)
+#define TIM_DMABase_ARR                    ((uint16_t)0x000B)
+#define TIM_DMABase_RCR                    ((uint16_t)0x000C)
+#define TIM_DMABase_CCR1                   ((uint16_t)0x000D)
+#define TIM_DMABase_CCR2                   ((uint16_t)0x000E)
+#define TIM_DMABase_CCR3                   ((uint16_t)0x000F)
+#define TIM_DMABase_CCR4                   ((uint16_t)0x0010)
+#define TIM_DMABase_BDTR                   ((uint16_t)0x0011)
+#define TIM_DMABase_DCR                    ((uint16_t)0x0012)
+#define TIM_DMABase_OR                     ((uint16_t)0x0013)
+#define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
+                               ((BASE) == TIM_DMABase_CR2) || \
+                               ((BASE) == TIM_DMABase_SMCR) || \
+                               ((BASE) == TIM_DMABase_DIER) || \
+                               ((BASE) == TIM_DMABase_SR) || \
+                               ((BASE) == TIM_DMABase_EGR) || \
+                               ((BASE) == TIM_DMABase_CCMR1) || \
+                               ((BASE) == TIM_DMABase_CCMR2) || \
+                               ((BASE) == TIM_DMABase_CCER) || \
+                               ((BASE) == TIM_DMABase_CNT) || \
+                               ((BASE) == TIM_DMABase_PSC) || \
+                               ((BASE) == TIM_DMABase_ARR) || \
+                               ((BASE) == TIM_DMABase_RCR) || \
+                               ((BASE) == TIM_DMABase_CCR1) || \
+                               ((BASE) == TIM_DMABase_CCR2) || \
+                               ((BASE) == TIM_DMABase_CCR3) || \
+                               ((BASE) == TIM_DMABase_CCR4) || \
+                               ((BASE) == TIM_DMABase_BDTR) || \
+                               ((BASE) == TIM_DMABase_DCR) || \
+                               ((BASE) == TIM_DMABase_OR))                     
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_DMA_Burst_Length 
+  * @{
+  */
+
+#define TIM_DMABurstLength_1Transfer           ((uint16_t)0x0000)
+#define TIM_DMABurstLength_2Transfers          ((uint16_t)0x0100)
+#define TIM_DMABurstLength_3Transfers          ((uint16_t)0x0200)
+#define TIM_DMABurstLength_4Transfers          ((uint16_t)0x0300)
+#define TIM_DMABurstLength_5Transfers          ((uint16_t)0x0400)
+#define TIM_DMABurstLength_6Transfers          ((uint16_t)0x0500)
+#define TIM_DMABurstLength_7Transfers          ((uint16_t)0x0600)
+#define TIM_DMABurstLength_8Transfers          ((uint16_t)0x0700)
+#define TIM_DMABurstLength_9Transfers          ((uint16_t)0x0800)
+#define TIM_DMABurstLength_10Transfers         ((uint16_t)0x0900)
+#define TIM_DMABurstLength_11Transfers         ((uint16_t)0x0A00)
+#define TIM_DMABurstLength_12Transfers         ((uint16_t)0x0B00)
+#define TIM_DMABurstLength_13Transfers         ((uint16_t)0x0C00)
+#define TIM_DMABurstLength_14Transfers         ((uint16_t)0x0D00)
+#define TIM_DMABurstLength_15Transfers         ((uint16_t)0x0E00)
+#define TIM_DMABurstLength_16Transfers         ((uint16_t)0x0F00)
+#define TIM_DMABurstLength_17Transfers         ((uint16_t)0x1000)
+#define TIM_DMABurstLength_18Transfers         ((uint16_t)0x1100)
+#define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
+                                   ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
+                                   ((LENGTH) == TIM_DMABurstLength_18Transfers))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_DMA_sources 
+  * @{
+  */
+
+#define TIM_DMA_Update                     ((uint16_t)0x0100)
+#define TIM_DMA_CC1                        ((uint16_t)0x0200)
+#define TIM_DMA_CC2                        ((uint16_t)0x0400)
+#define TIM_DMA_CC3                        ((uint16_t)0x0800)
+#define TIM_DMA_CC4                        ((uint16_t)0x1000)
+#define TIM_DMA_COM                        ((uint16_t)0x2000)
+#define TIM_DMA_Trigger                    ((uint16_t)0x4000)
+#define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_External_Trigger_Prescaler 
+  * @{
+  */
+
+#define TIM_ExtTRGPSC_OFF                  ((uint16_t)0x0000)
+#define TIM_ExtTRGPSC_DIV2                 ((uint16_t)0x1000)
+#define TIM_ExtTRGPSC_DIV4                 ((uint16_t)0x2000)
+#define TIM_ExtTRGPSC_DIV8                 ((uint16_t)0x3000)
+#define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
+                                         ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Internal_Trigger_Selection 
+  * @{
+  */
+
+#define TIM_TS_ITR0                        ((uint16_t)0x0000)
+#define TIM_TS_ITR1                        ((uint16_t)0x0010)
+#define TIM_TS_ITR2                        ((uint16_t)0x0020)
+#define TIM_TS_ITR3                        ((uint16_t)0x0030)
+#define TIM_TS_TI1F_ED                     ((uint16_t)0x0040)
+#define TIM_TS_TI1FP1                      ((uint16_t)0x0050)
+#define TIM_TS_TI2FP2                      ((uint16_t)0x0060)
+#define TIM_TS_ETRF                        ((uint16_t)0x0070)
+#define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+                                             ((SELECTION) == TIM_TS_ITR1) || \
+                                             ((SELECTION) == TIM_TS_ITR2) || \
+                                             ((SELECTION) == TIM_TS_ITR3) || \
+                                             ((SELECTION) == TIM_TS_TI1F_ED) || \
+                                             ((SELECTION) == TIM_TS_TI1FP1) || \
+                                             ((SELECTION) == TIM_TS_TI2FP2) || \
+                                             ((SELECTION) == TIM_TS_ETRF))
+#define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
+                                                      ((SELECTION) == TIM_TS_ITR1) || \
+                                                      ((SELECTION) == TIM_TS_ITR2) || \
+                                                      ((SELECTION) == TIM_TS_ITR3))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_TIx_External_Clock_Source 
+  * @{
+  */
+
+#define TIM_TIxExternalCLK1Source_TI1      ((uint16_t)0x0050)
+#define TIM_TIxExternalCLK1Source_TI2      ((uint16_t)0x0060)
+#define TIM_TIxExternalCLK1Source_TI1ED    ((uint16_t)0x0040)
+
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_External_Trigger_Polarity 
+  * @{
+  */ 
+#define TIM_ExtTRGPolarity_Inverted        ((uint16_t)0x8000)
+#define TIM_ExtTRGPolarity_NonInverted     ((uint16_t)0x0000)
+#define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
+                                       ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Prescaler_Reload_Mode 
+  * @{
+  */
+
+#define TIM_PSCReloadMode_Update           ((uint16_t)0x0000)
+#define TIM_PSCReloadMode_Immediate        ((uint16_t)0x0001)
+#define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
+                                         ((RELOAD) == TIM_PSCReloadMode_Immediate))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Forced_Action 
+  * @{
+  */
+
+#define TIM_ForcedAction_Active            ((uint16_t)0x0050)
+#define TIM_ForcedAction_InActive          ((uint16_t)0x0040)
+#define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
+                                      ((ACTION) == TIM_ForcedAction_InActive))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Encoder_Mode 
+  * @{
+  */
+
+#define TIM_EncoderMode_TI1                ((uint16_t)0x0001)
+#define TIM_EncoderMode_TI2                ((uint16_t)0x0002)
+#define TIM_EncoderMode_TI12               ((uint16_t)0x0003)
+#define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
+                                   ((MODE) == TIM_EncoderMode_TI2) || \
+                                   ((MODE) == TIM_EncoderMode_TI12))
+/**
+  * @}
+  */ 
+
+
+/** @defgroup TIM_Event_Source 
+  * @{
+  */
+
+#define TIM_EventSource_Update             ((uint16_t)0x0001)
+#define TIM_EventSource_CC1                ((uint16_t)0x0002)
+#define TIM_EventSource_CC2                ((uint16_t)0x0004)
+#define TIM_EventSource_CC3                ((uint16_t)0x0008)
+#define TIM_EventSource_CC4                ((uint16_t)0x0010)
+#define TIM_EventSource_COM                ((uint16_t)0x0020)
+#define TIM_EventSource_Trigger            ((uint16_t)0x0040)
+#define TIM_EventSource_Break              ((uint16_t)0x0080)
+#define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))                                          
+  
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Update_Source 
+  * @{
+  */
+
+#define TIM_UpdateSource_Global            ((uint16_t)0x0000) /*!< Source of update is the counter overflow/underflow
+                                                                   or the setting of UG bit, or an update generation
+                                                                   through the slave mode controller. */
+#define TIM_UpdateSource_Regular           ((uint16_t)0x0001) /*!< Source of update is counter overflow/underflow. */
+#define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
+                                      ((SOURCE) == TIM_UpdateSource_Regular))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Preload_State 
+  * @{
+  */
+
+#define TIM_OCPreload_Enable               ((uint16_t)0x0008)
+#define TIM_OCPreload_Disable              ((uint16_t)0x0000)
+#define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
+                                       ((STATE) == TIM_OCPreload_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Fast_State 
+  * @{
+  */
+
+#define TIM_OCFast_Enable                  ((uint16_t)0x0004)
+#define TIM_OCFast_Disable                 ((uint16_t)0x0000)
+#define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
+                                    ((STATE) == TIM_OCFast_Disable))
+                                     
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Output_Compare_Clear_State 
+  * @{
+  */
+
+#define TIM_OCClear_Enable                 ((uint16_t)0x0080)
+#define TIM_OCClear_Disable                ((uint16_t)0x0000)
+#define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
+                                     ((STATE) == TIM_OCClear_Disable))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Trigger_Output_Source 
+  * @{
+  */
+
+#define TIM_TRGOSource_Reset               ((uint16_t)0x0000)
+#define TIM_TRGOSource_Enable              ((uint16_t)0x0010)
+#define TIM_TRGOSource_Update              ((uint16_t)0x0020)
+#define TIM_TRGOSource_OC1                 ((uint16_t)0x0030)
+#define TIM_TRGOSource_OC1Ref              ((uint16_t)0x0040)
+#define TIM_TRGOSource_OC2Ref              ((uint16_t)0x0050)
+#define TIM_TRGOSource_OC3Ref              ((uint16_t)0x0060)
+#define TIM_TRGOSource_OC4Ref              ((uint16_t)0x0070)
+#define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
+                                    ((SOURCE) == TIM_TRGOSource_Enable) || \
+                                    ((SOURCE) == TIM_TRGOSource_Update) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC1) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
+                                    ((SOURCE) == TIM_TRGOSource_OC4Ref))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Slave_Mode 
+  * @{
+  */
+
+#define TIM_SlaveMode_Reset                ((uint16_t)0x0004)
+#define TIM_SlaveMode_Gated                ((uint16_t)0x0005)
+#define TIM_SlaveMode_Trigger              ((uint16_t)0x0006)
+#define TIM_SlaveMode_External1            ((uint16_t)0x0007)
+#define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
+                                 ((MODE) == TIM_SlaveMode_Gated) || \
+                                 ((MODE) == TIM_SlaveMode_Trigger) || \
+                                 ((MODE) == TIM_SlaveMode_External1))
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Master_Slave_Mode 
+  * @{
+  */
+
+#define TIM_MasterSlaveMode_Enable         ((uint16_t)0x0080)
+#define TIM_MasterSlaveMode_Disable        ((uint16_t)0x0000)
+#define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
+                                 ((STATE) == TIM_MasterSlaveMode_Disable))
+/**
+  * @}
+  */ 
+/** @defgroup TIM_Remap 
+  * @{
+  */
+
+#define TIM2_TIM8_TRGO                     ((uint16_t)0x0000)
+#define TIM2_ETH_PTP                       ((uint16_t)0x0400)
+#define TIM2_USBFS_SOF                     ((uint16_t)0x0800)
+#define TIM2_USBHS_SOF                     ((uint16_t)0x0C00)
+
+#define TIM5_GPIO                          ((uint16_t)0x0000)
+#define TIM5_LSI                           ((uint16_t)0x0040)
+#define TIM5_LSE                           ((uint16_t)0x0080)
+#define TIM5_RTC                           ((uint16_t)0x00C0)
+
+#define TIM11_GPIO                         ((uint16_t)0x0000)
+#define TIM11_HSE                          ((uint16_t)0x0002)
+
+#define IS_TIM_REMAP(TIM_REMAP)	 (((TIM_REMAP) == TIM2_TIM8_TRGO)||\
+                                  ((TIM_REMAP) == TIM2_ETH_PTP)||\
+                                  ((TIM_REMAP) == TIM2_USBFS_SOF)||\
+                                  ((TIM_REMAP) == TIM2_USBHS_SOF)||\
+                                  ((TIM_REMAP) == TIM5_GPIO)||\
+                                  ((TIM_REMAP) == TIM5_LSI)||\
+                                  ((TIM_REMAP) == TIM5_LSE)||\
+                                  ((TIM_REMAP) == TIM5_RTC)||\
+                                  ((TIM_REMAP) == TIM11_GPIO)||\
+                                  ((TIM_REMAP) == TIM11_HSE))
+
+/**
+  * @}
+  */ 
+/** @defgroup TIM_Flags 
+  * @{
+  */
+
+#define TIM_FLAG_Update                    ((uint16_t)0x0001)
+#define TIM_FLAG_CC1                       ((uint16_t)0x0002)
+#define TIM_FLAG_CC2                       ((uint16_t)0x0004)
+#define TIM_FLAG_CC3                       ((uint16_t)0x0008)
+#define TIM_FLAG_CC4                       ((uint16_t)0x0010)
+#define TIM_FLAG_COM                       ((uint16_t)0x0020)
+#define TIM_FLAG_Trigger                   ((uint16_t)0x0040)
+#define TIM_FLAG_Break                     ((uint16_t)0x0080)
+#define TIM_FLAG_CC1OF                     ((uint16_t)0x0200)
+#define TIM_FLAG_CC2OF                     ((uint16_t)0x0400)
+#define TIM_FLAG_CC3OF                     ((uint16_t)0x0800)
+#define TIM_FLAG_CC4OF                     ((uint16_t)0x1000)
+#define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
+                               ((FLAG) == TIM_FLAG_CC1) || \
+                               ((FLAG) == TIM_FLAG_CC2) || \
+                               ((FLAG) == TIM_FLAG_CC3) || \
+                               ((FLAG) == TIM_FLAG_CC4) || \
+                               ((FLAG) == TIM_FLAG_COM) || \
+                               ((FLAG) == TIM_FLAG_Trigger) || \
+                               ((FLAG) == TIM_FLAG_Break) || \
+                               ((FLAG) == TIM_FLAG_CC1OF) || \
+                               ((FLAG) == TIM_FLAG_CC2OF) || \
+                               ((FLAG) == TIM_FLAG_CC3OF) || \
+                               ((FLAG) == TIM_FLAG_CC4OF))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Input_Capture_Filer_Value 
+  * @{
+  */
+
+#define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF) 
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_External_Trigger_Filter 
+  * @{
+  */
+
+#define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
+/**
+  * @}
+  */ 
+
+/** @defgroup TIM_Legacy 
+  * @{
+  */
+
+#define TIM_DMABurstLength_1Byte           TIM_DMABurstLength_1Transfer
+#define TIM_DMABurstLength_2Bytes          TIM_DMABurstLength_2Transfers
+#define TIM_DMABurstLength_3Bytes          TIM_DMABurstLength_3Transfers
+#define TIM_DMABurstLength_4Bytes          TIM_DMABurstLength_4Transfers
+#define TIM_DMABurstLength_5Bytes          TIM_DMABurstLength_5Transfers
+#define TIM_DMABurstLength_6Bytes          TIM_DMABurstLength_6Transfers
+#define TIM_DMABurstLength_7Bytes          TIM_DMABurstLength_7Transfers
+#define TIM_DMABurstLength_8Bytes          TIM_DMABurstLength_8Transfers
+#define TIM_DMABurstLength_9Bytes          TIM_DMABurstLength_9Transfers
+#define TIM_DMABurstLength_10Bytes         TIM_DMABurstLength_10Transfers
+#define TIM_DMABurstLength_11Bytes         TIM_DMABurstLength_11Transfers
+#define TIM_DMABurstLength_12Bytes         TIM_DMABurstLength_12Transfers
+#define TIM_DMABurstLength_13Bytes         TIM_DMABurstLength_13Transfers
+#define TIM_DMABurstLength_14Bytes         TIM_DMABurstLength_14Transfers
+#define TIM_DMABurstLength_15Bytes         TIM_DMABurstLength_15Transfers
+#define TIM_DMABurstLength_16Bytes         TIM_DMABurstLength_16Transfers
+#define TIM_DMABurstLength_17Bytes         TIM_DMABurstLength_17Transfers
+#define TIM_DMABurstLength_18Bytes         TIM_DMABurstLength_18Transfers
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/ 
+
+/* TimeBase management ********************************************************/
+void TIM_DeInit(TIM_TypeDef* TIMx);
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Output Compare management **************************************************/
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
+
+/* Input Capture management ***************************************************/
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
+
+/* Advanced-control timers (TIM1 and TIM8) specific features ******************/
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Interrupts, DMA and flags management ***************************************/
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Clocks management **********************************************************/
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter);
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                             uint16_t ExtTRGFilter);
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
+
+/* Synchronization management *************************************************/
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                   uint16_t ExtTRGFilter);
+
+/* Specific interface management **********************************************/   
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
+
+/* Specific remapping management **********************************************/
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /*__STM32F4xx_TIM_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h
new file mode 100644
index 0000000000..18b3b2332c
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_usart.h
@@ -0,0 +1,412 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_usart.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the USART 
+  *          firmware library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************  
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_USART_H
+#define __STM32F4xx_USART_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup USART
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/ 
+
+/** 
+  * @brief  USART Init Structure definition  
+  */ 
+  
+typedef struct
+{
+  uint32_t USART_BaudRate;            /*!< This member configures the USART communication baud rate.
+                                           The baud rate is computed using the following formula:
+                                            - IntegerDivider = ((PCLKx) / (8 * (OVR8+1) * (USART_InitStruct->USART_BaudRate)))
+                                            - FractionalDivider = ((IntegerDivider - ((u32) IntegerDivider)) * 8 * (OVR8+1)) + 0.5 
+                                           Where OVR8 is the "oversampling by 8 mode" configuration bit in the CR1 register. */
+
+  uint16_t USART_WordLength;          /*!< Specifies the number of data bits transmitted or received in a frame.
+                                           This parameter can be a value of @ref USART_Word_Length */
+
+  uint16_t USART_StopBits;            /*!< Specifies the number of stop bits transmitted.
+                                           This parameter can be a value of @ref USART_Stop_Bits */
+
+  uint16_t USART_Parity;              /*!< Specifies the parity mode.
+                                           This parameter can be a value of @ref USART_Parity
+                                           @note When parity is enabled, the computed parity is inserted
+                                                 at the MSB position of the transmitted data (9th bit when
+                                                 the word length is set to 9 data bits; 8th bit when the
+                                                 word length is set to 8 data bits). */
+ 
+  uint16_t USART_Mode;                /*!< Specifies wether the Receive or Transmit mode is enabled or disabled.
+                                           This parameter can be a value of @ref USART_Mode */
+
+  uint16_t USART_HardwareFlowControl; /*!< Specifies wether the hardware flow control mode is enabled
+                                           or disabled.
+                                           This parameter can be a value of @ref USART_Hardware_Flow_Control */
+} USART_InitTypeDef;
+
+/** 
+  * @brief  USART Clock Init Structure definition  
+  */ 
+  
+typedef struct
+{
+
+  uint16_t USART_Clock;   /*!< Specifies whether the USART clock is enabled or disabled.
+                               This parameter can be a value of @ref USART_Clock */
+
+  uint16_t USART_CPOL;    /*!< Specifies the steady state of the serial clock.
+                               This parameter can be a value of @ref USART_Clock_Polarity */
+
+  uint16_t USART_CPHA;    /*!< Specifies the clock transition on which the bit capture is made.
+                               This parameter can be a value of @ref USART_Clock_Phase */
+
+  uint16_t USART_LastBit; /*!< Specifies whether the clock pulse corresponding to the last transmitted
+                               data bit (MSB) has to be output on the SCLK pin in synchronous mode.
+                               This parameter can be a value of @ref USART_Last_Bit */
+} USART_ClockInitTypeDef;
+
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup USART_Exported_Constants
+  * @{
+  */ 
+  
+#define IS_USART_ALL_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+                                     ((PERIPH) == USART2) || \
+                                     ((PERIPH) == USART3) || \
+                                     ((PERIPH) == UART4)  || \
+                                     ((PERIPH) == UART5)  || \
+                                     ((PERIPH) == USART6))
+
+#define IS_USART_1236_PERIPH(PERIPH) (((PERIPH) == USART1) || \
+                                      ((PERIPH) == USART2) || \
+                                      ((PERIPH) == USART3) || \
+                                      ((PERIPH) == USART6))
+
+/** @defgroup USART_Word_Length 
+  * @{
+  */ 
+  
+#define USART_WordLength_8b                  ((uint16_t)0x0000)
+#define USART_WordLength_9b                  ((uint16_t)0x1000)
+                                    
+#define IS_USART_WORD_LENGTH(LENGTH) (((LENGTH) == USART_WordLength_8b) || \
+                                      ((LENGTH) == USART_WordLength_9b))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Stop_Bits 
+  * @{
+  */ 
+  
+#define USART_StopBits_1                     ((uint16_t)0x0000)
+#define USART_StopBits_0_5                   ((uint16_t)0x1000)
+#define USART_StopBits_2                     ((uint16_t)0x2000)
+#define USART_StopBits_1_5                   ((uint16_t)0x3000)
+#define IS_USART_STOPBITS(STOPBITS) (((STOPBITS) == USART_StopBits_1) || \
+                                     ((STOPBITS) == USART_StopBits_0_5) || \
+                                     ((STOPBITS) == USART_StopBits_2) || \
+                                     ((STOPBITS) == USART_StopBits_1_5))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Parity 
+  * @{
+  */ 
+  
+#define USART_Parity_No                      ((uint16_t)0x0000)
+#define USART_Parity_Even                    ((uint16_t)0x0400)
+#define USART_Parity_Odd                     ((uint16_t)0x0600) 
+#define IS_USART_PARITY(PARITY) (((PARITY) == USART_Parity_No) || \
+                                 ((PARITY) == USART_Parity_Even) || \
+                                 ((PARITY) == USART_Parity_Odd))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Mode 
+  * @{
+  */ 
+  
+#define USART_Mode_Rx                        ((uint16_t)0x0004)
+#define USART_Mode_Tx                        ((uint16_t)0x0008)
+#define IS_USART_MODE(MODE) ((((MODE) & (uint16_t)0xFFF3) == 0x00) && ((MODE) != (uint16_t)0x00))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Hardware_Flow_Control 
+  * @{
+  */ 
+#define USART_HardwareFlowControl_None       ((uint16_t)0x0000)
+#define USART_HardwareFlowControl_RTS        ((uint16_t)0x0100)
+#define USART_HardwareFlowControl_CTS        ((uint16_t)0x0200)
+#define USART_HardwareFlowControl_RTS_CTS    ((uint16_t)0x0300)
+#define IS_USART_HARDWARE_FLOW_CONTROL(CONTROL)\
+                              (((CONTROL) == USART_HardwareFlowControl_None) || \
+                               ((CONTROL) == USART_HardwareFlowControl_RTS) || \
+                               ((CONTROL) == USART_HardwareFlowControl_CTS) || \
+                               ((CONTROL) == USART_HardwareFlowControl_RTS_CTS))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock 
+  * @{
+  */ 
+#define USART_Clock_Disable                  ((uint16_t)0x0000)
+#define USART_Clock_Enable                   ((uint16_t)0x0800)
+#define IS_USART_CLOCK(CLOCK) (((CLOCK) == USART_Clock_Disable) || \
+                               ((CLOCK) == USART_Clock_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock_Polarity 
+  * @{
+  */
+  
+#define USART_CPOL_Low                       ((uint16_t)0x0000)
+#define USART_CPOL_High                      ((uint16_t)0x0400)
+#define IS_USART_CPOL(CPOL) (((CPOL) == USART_CPOL_Low) || ((CPOL) == USART_CPOL_High))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Clock_Phase
+  * @{
+  */
+
+#define USART_CPHA_1Edge                     ((uint16_t)0x0000)
+#define USART_CPHA_2Edge                     ((uint16_t)0x0200)
+#define IS_USART_CPHA(CPHA) (((CPHA) == USART_CPHA_1Edge) || ((CPHA) == USART_CPHA_2Edge))
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Last_Bit
+  * @{
+  */
+
+#define USART_LastBit_Disable                ((uint16_t)0x0000)
+#define USART_LastBit_Enable                 ((uint16_t)0x0100)
+#define IS_USART_LASTBIT(LASTBIT) (((LASTBIT) == USART_LastBit_Disable) || \
+                                   ((LASTBIT) == USART_LastBit_Enable))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Interrupt_definition 
+  * @{
+  */
+  
+#define USART_IT_PE                          ((uint16_t)0x0028)
+#define USART_IT_TXE                         ((uint16_t)0x0727)
+#define USART_IT_TC                          ((uint16_t)0x0626)
+#define USART_IT_RXNE                        ((uint16_t)0x0525)
+#define USART_IT_IDLE                        ((uint16_t)0x0424)
+#define USART_IT_LBD                         ((uint16_t)0x0846)
+#define USART_IT_CTS                         ((uint16_t)0x096A)
+#define USART_IT_ERR                         ((uint16_t)0x0060)
+#define USART_IT_ORE                         ((uint16_t)0x0360)
+#define USART_IT_NE                          ((uint16_t)0x0260)
+#define USART_IT_FE                          ((uint16_t)0x0160)
+#define IS_USART_CONFIG_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+                                ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                                ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+                                ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ERR))
+#define IS_USART_GET_IT(IT) (((IT) == USART_IT_PE) || ((IT) == USART_IT_TXE) || \
+                             ((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                             ((IT) == USART_IT_IDLE) || ((IT) == USART_IT_LBD) || \
+                             ((IT) == USART_IT_CTS) || ((IT) == USART_IT_ORE) || \
+                             ((IT) == USART_IT_NE) || ((IT) == USART_IT_FE))
+#define IS_USART_CLEAR_IT(IT) (((IT) == USART_IT_TC) || ((IT) == USART_IT_RXNE) || \
+                               ((IT) == USART_IT_LBD) || ((IT) == USART_IT_CTS))
+/**
+  * @}
+  */
+
+/** @defgroup USART_DMA_Requests 
+  * @{
+  */
+
+#define USART_DMAReq_Tx                      ((uint16_t)0x0080)
+#define USART_DMAReq_Rx                      ((uint16_t)0x0040)
+#define IS_USART_DMAREQ(DMAREQ) ((((DMAREQ) & (uint16_t)0xFF3F) == 0x00) && ((DMAREQ) != (uint16_t)0x00))
+
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_WakeUp_methods
+  * @{
+  */
+
+#define USART_WakeUp_IdleLine                ((uint16_t)0x0000)
+#define USART_WakeUp_AddressMark             ((uint16_t)0x0800)
+#define IS_USART_WAKEUP(WAKEUP) (((WAKEUP) == USART_WakeUp_IdleLine) || \
+                                 ((WAKEUP) == USART_WakeUp_AddressMark))
+/**
+  * @}
+  */
+
+/** @defgroup USART_LIN_Break_Detection_Length 
+  * @{
+  */
+  
+#define USART_LINBreakDetectLength_10b      ((uint16_t)0x0000)
+#define USART_LINBreakDetectLength_11b      ((uint16_t)0x0020)
+#define IS_USART_LIN_BREAK_DETECT_LENGTH(LENGTH) \
+                               (((LENGTH) == USART_LINBreakDetectLength_10b) || \
+                                ((LENGTH) == USART_LINBreakDetectLength_11b))
+/**
+  * @}
+  */
+
+/** @defgroup USART_IrDA_Low_Power 
+  * @{
+  */
+
+#define USART_IrDAMode_LowPower              ((uint16_t)0x0004)
+#define USART_IrDAMode_Normal                ((uint16_t)0x0000)
+#define IS_USART_IRDA_MODE(MODE) (((MODE) == USART_IrDAMode_LowPower) || \
+                                  ((MODE) == USART_IrDAMode_Normal))
+/**
+  * @}
+  */ 
+
+/** @defgroup USART_Flags 
+  * @{
+  */
+
+#define USART_FLAG_CTS                       ((uint16_t)0x0200)
+#define USART_FLAG_LBD                       ((uint16_t)0x0100)
+#define USART_FLAG_TXE                       ((uint16_t)0x0080)
+#define USART_FLAG_TC                        ((uint16_t)0x0040)
+#define USART_FLAG_RXNE                      ((uint16_t)0x0020)
+#define USART_FLAG_IDLE                      ((uint16_t)0x0010)
+#define USART_FLAG_ORE                       ((uint16_t)0x0008)
+#define USART_FLAG_NE                        ((uint16_t)0x0004)
+#define USART_FLAG_FE                        ((uint16_t)0x0002)
+#define USART_FLAG_PE                        ((uint16_t)0x0001)
+#define IS_USART_FLAG(FLAG) (((FLAG) == USART_FLAG_PE) || ((FLAG) == USART_FLAG_TXE) || \
+                             ((FLAG) == USART_FLAG_TC) || ((FLAG) == USART_FLAG_RXNE) || \
+                             ((FLAG) == USART_FLAG_IDLE) || ((FLAG) == USART_FLAG_LBD) || \
+                             ((FLAG) == USART_FLAG_CTS) || ((FLAG) == USART_FLAG_ORE) || \
+                             ((FLAG) == USART_FLAG_NE) || ((FLAG) == USART_FLAG_FE))
+                              
+#define IS_USART_CLEAR_FLAG(FLAG) ((((FLAG) & (uint16_t)0xFC9F) == 0x00) && ((FLAG) != (uint16_t)0x00))
+
+#define IS_USART_BAUDRATE(BAUDRATE) (((BAUDRATE) > 0) && ((BAUDRATE) < 7500001))
+#define IS_USART_ADDRESS(ADDRESS) ((ADDRESS) <= 0xF)
+#define IS_USART_DATA(DATA) ((DATA) <= 0x1FF)
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/  
+
+/*  Function used to set the USART configuration to the default reset state ***/ 
+void USART_DeInit(USART_TypeDef* USARTx);
+
+/* Initialization and Configuration functions *********************************/
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct);
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct);
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct);
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler);
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* Data transfers functions ***************************************************/ 
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data);
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx);
+
+/* Multi-Processor Communication functions ************************************/
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address);
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp);
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* LIN mode functions *********************************************************/
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength);
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SendBreak(USART_TypeDef* USARTx);
+
+/* Half-duplex mode function **************************************************/
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* Smartcard mode functions ***************************************************/
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState);
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime);
+
+/* IrDA mode functions ********************************************************/
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode);
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState);
+
+/* DMA transfers management functions *****************************************/
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+
+/* Interrupts and flags management functions **********************************/
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_USART_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h
new file mode 100644
index 0000000000..04345b4621
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/inc/stm32f4xx_wwdg.h
@@ -0,0 +1,105 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_wwdg.h
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file contains all the functions prototypes for the WWDG firmware
+  *          library.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_WWDG_H
+#define __STM32F4xx_WWDG_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @addtogroup WWDG
+  * @{
+  */ 
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/** @defgroup WWDG_Exported_Constants
+  * @{
+  */ 
+  
+/** @defgroup WWDG_Prescaler 
+  * @{
+  */
+  
+#define WWDG_Prescaler_1    ((uint32_t)0x00000000)
+#define WWDG_Prescaler_2    ((uint32_t)0x00000080)
+#define WWDG_Prescaler_4    ((uint32_t)0x00000100)
+#define WWDG_Prescaler_8    ((uint32_t)0x00000180)
+#define IS_WWDG_PRESCALER(PRESCALER) (((PRESCALER) == WWDG_Prescaler_1) || \
+                                      ((PRESCALER) == WWDG_Prescaler_2) || \
+                                      ((PRESCALER) == WWDG_Prescaler_4) || \
+                                      ((PRESCALER) == WWDG_Prescaler_8))
+#define IS_WWDG_WINDOW_VALUE(VALUE) ((VALUE) <= 0x7F)
+#define IS_WWDG_COUNTER(COUNTER) (((COUNTER) >= 0x40) && ((COUNTER) <= 0x7F))
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions --------------------------------------------------------*/
+  
+/*  Function used to set the WWDG configuration to the default reset state ****/  
+void WWDG_DeInit(void);
+
+/* Prescaler, Refresh window and Counter configuration functions **************/
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler);
+void WWDG_SetWindowValue(uint8_t WindowValue);
+void WWDG_EnableIT(void);
+void WWDG_SetCounter(uint8_t Counter);
+
+/* WWDG activation function ***************************************************/
+void WWDG_Enable(uint8_t Counter);
+
+/* Interrupts and flags management functions **********************************/
+FlagStatus WWDG_GetFlagStatus(void);
+void WWDG_ClearFlag(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_WWDG_H */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c
new file mode 100644
index 0000000000..173c48183d
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/misc.c
@@ -0,0 +1,243 @@
+/**
+  ******************************************************************************
+  * @file    misc.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides all the miscellaneous firmware functions (add-on
+  *          to CMSIS functions).
+  *          
+  *  @verbatim   
+  *                               
+  *          ===================================================================      
+  *                        How to configure Interrupts using driver 
+  *          ===================================================================      
+  * 
+  *            This section provide functions allowing to configure the NVIC interrupts (IRQ).
+  *            The Cortex-M4 exceptions are managed by CMSIS functions.
+  *
+  *            1. Configure the NVIC Priority Grouping using NVIC_PriorityGroupConfig()
+  *                function according to the following table.
+ 
+  *  The table below gives the allowed values of the pre-emption priority and subpriority according
+  *  to the Priority Grouping configuration performed by NVIC_PriorityGroupConfig function
+  *    ==========================================================================================================================
+  *      NVIC_PriorityGroup   | NVIC_IRQChannelPreemptionPriority | NVIC_IRQChannelSubPriority  |       Description
+  *    ==========================================================================================================================
+  *     NVIC_PriorityGroup_0  |                0                  |            0-15             | 0 bits for pre-emption priority
+  *                           |                                   |                             | 4 bits for subpriority
+  *    --------------------------------------------------------------------------------------------------------------------------
+  *     NVIC_PriorityGroup_1  |                0-1                |            0-7              | 1 bits for pre-emption priority
+  *                           |                                   |                             | 3 bits for subpriority
+  *    --------------------------------------------------------------------------------------------------------------------------    
+  *     NVIC_PriorityGroup_2  |                0-3                |            0-3              | 2 bits for pre-emption priority
+  *                           |                                   |                             | 2 bits for subpriority
+  *    --------------------------------------------------------------------------------------------------------------------------    
+  *     NVIC_PriorityGroup_3  |                0-7                |            0-1              | 3 bits for pre-emption priority
+  *                           |                                   |                             | 1 bits for subpriority
+  *    --------------------------------------------------------------------------------------------------------------------------    
+  *     NVIC_PriorityGroup_4  |                0-15               |            0                | 4 bits for pre-emption priority
+  *                           |                                   |                             | 0 bits for subpriority                       
+  *    ==========================================================================================================================     
+  *
+  *            2. Enable and Configure the priority of the selected IRQ Channels using NVIC_Init()  
+  *
+  * @note  When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 
+  *        The pending IRQ priority will be managed only by the subpriority.
+  *
+  * @note  IRQ priority order (sorted by highest to lowest priority):
+  *         - Lowest pre-emption priority
+  *         - Lowest subpriority
+  *         - Lowest hardware priority (IRQ number)
+  *
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "misc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup MISC 
+  * @brief MISC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define AIRCR_VECTKEY_MASK    ((uint32_t)0x05FA0000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup MISC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Configures the priority grouping: pre-emption priority and subpriority.
+  * @param  NVIC_PriorityGroup: specifies the priority grouping bits length. 
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_PriorityGroup_0: 0 bits for pre-emption priority
+  *                                4 bits for subpriority
+  *     @arg NVIC_PriorityGroup_1: 1 bits for pre-emption priority
+  *                                3 bits for subpriority
+  *     @arg NVIC_PriorityGroup_2: 2 bits for pre-emption priority
+  *                                2 bits for subpriority
+  *     @arg NVIC_PriorityGroup_3: 3 bits for pre-emption priority
+  *                                1 bits for subpriority
+  *     @arg NVIC_PriorityGroup_4: 4 bits for pre-emption priority
+  *                                0 bits for subpriority
+  * @note   When the NVIC_PriorityGroup_0 is selected, IRQ pre-emption is no more possible. 
+  *         The pending IRQ priority will be managed only by the subpriority. 
+  * @retval None
+  */
+void NVIC_PriorityGroupConfig(uint32_t NVIC_PriorityGroup)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_PRIORITY_GROUP(NVIC_PriorityGroup));
+  
+  /* Set the PRIGROUP[10:8] bits according to NVIC_PriorityGroup value */
+  SCB->AIRCR = AIRCR_VECTKEY_MASK | NVIC_PriorityGroup;
+}
+
+/**
+  * @brief  Initializes the NVIC peripheral according to the specified
+  *         parameters in the NVIC_InitStruct.
+  * @note   To configure interrupts priority correctly, the NVIC_PriorityGroupConfig()
+  *         function should be called before. 
+  * @param  NVIC_InitStruct: pointer to a NVIC_InitTypeDef structure that contains
+  *         the configuration information for the specified NVIC peripheral.
+  * @retval None
+  */
+void NVIC_Init(NVIC_InitTypeDef* NVIC_InitStruct)
+{
+  uint8_t tmppriority = 0x00, tmppre = 0x00, tmpsub = 0x0F;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NVIC_InitStruct->NVIC_IRQChannelCmd));
+  assert_param(IS_NVIC_PREEMPTION_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority));  
+  assert_param(IS_NVIC_SUB_PRIORITY(NVIC_InitStruct->NVIC_IRQChannelSubPriority));
+    
+  if (NVIC_InitStruct->NVIC_IRQChannelCmd != DISABLE)
+  {
+    /* Compute the Corresponding IRQ Priority --------------------------------*/    
+    tmppriority = (0x700 - ((SCB->AIRCR) & (uint32_t)0x700))>> 0x08;
+    tmppre = (0x4 - tmppriority);
+    tmpsub = tmpsub >> tmppriority;
+
+    tmppriority = NVIC_InitStruct->NVIC_IRQChannelPreemptionPriority << tmppre;
+    tmppriority |=  (uint8_t)(NVIC_InitStruct->NVIC_IRQChannelSubPriority & tmpsub);
+        
+    tmppriority = tmppriority << 0x04;
+        
+    NVIC->IP[NVIC_InitStruct->NVIC_IRQChannel] = tmppriority;
+    
+    /* Enable the Selected IRQ Channels --------------------------------------*/
+    NVIC->ISER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+  else
+  {
+    /* Disable the Selected IRQ Channels -------------------------------------*/
+    NVIC->ICER[NVIC_InitStruct->NVIC_IRQChannel >> 0x05] =
+      (uint32_t)0x01 << (NVIC_InitStruct->NVIC_IRQChannel & (uint8_t)0x1F);
+  }
+}
+
+/**
+  * @brief  Sets the vector table location and Offset.
+  * @param  NVIC_VectTab: specifies if the vector table is in RAM or FLASH memory.
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_VectTab_RAM: Vector Table in internal SRAM.
+  *     @arg NVIC_VectTab_FLASH: Vector Table in internal FLASH.
+  * @param  Offset: Vector Table base offset field. This value must be a multiple of 0x200.
+  * @retval None
+  */
+void NVIC_SetVectorTable(uint32_t NVIC_VectTab, uint32_t Offset)
+{ 
+  /* Check the parameters */
+  assert_param(IS_NVIC_VECTTAB(NVIC_VectTab));
+  assert_param(IS_NVIC_OFFSET(Offset));  
+   
+  SCB->VTOR = NVIC_VectTab | (Offset & (uint32_t)0x1FFFFF80);
+}
+
+/**
+  * @brief  Selects the condition for the system to enter low power mode.
+  * @param  LowPowerMode: Specifies the new mode for the system to enter low power mode.
+  *   This parameter can be one of the following values:
+  *     @arg NVIC_LP_SEVONPEND: Low Power SEV on Pend.
+  *     @arg NVIC_LP_SLEEPDEEP: Low Power DEEPSLEEP request.
+  *     @arg NVIC_LP_SLEEPONEXIT: Low Power Sleep on Exit.
+  * @param  NewState: new state of LP condition. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void NVIC_SystemLPConfig(uint8_t LowPowerMode, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_NVIC_LP(LowPowerMode));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));  
+  
+  if (NewState != DISABLE)
+  {
+    SCB->SCR |= LowPowerMode;
+  }
+  else
+  {
+    SCB->SCR &= (uint32_t)(~(uint32_t)LowPowerMode);
+  }
+}
+
+/**
+  * @brief  Configures the SysTick clock source.
+  * @param  SysTick_CLKSource: specifies the SysTick clock source.
+  *   This parameter can be one of the following values:
+  *     @arg SysTick_CLKSource_HCLK_Div8: AHB clock divided by 8 selected as SysTick clock source.
+  *     @arg SysTick_CLKSource_HCLK: AHB clock selected as SysTick clock source.
+  * @retval None
+  */
+void SysTick_CLKSourceConfig(uint32_t SysTick_CLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSTICK_CLK_SOURCE(SysTick_CLKSource));
+  if (SysTick_CLKSource == SysTick_CLKSource_HCLK)
+  {
+    SysTick->CTRL |= SysTick_CLKSource_HCLK;
+  }
+  else
+  {
+    SysTick->CTRL &= SysTick_CLKSource_HCLK_Div8;
+  }
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c
new file mode 100644
index 0000000000..d9c9f52555
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_adc.c
@@ -0,0 +1,1742 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_adc.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Analog to Digital Convertor (ADC) peripheral:
+  *           - Initialization and Configuration (in addition to ADC multi mode 
+  *             selection)
+  *           - Analog Watchdog configuration
+  *           - Temperature Sensor & Vrefint (Voltage Reference internal) & VBAT
+  *             management 
+  *           - Regular Channels Configuration
+  *           - Regular Channels DMA Configuration
+  *           - Injected channels Configuration
+  *           - Interrupts and flags management
+  *         
+  *  @verbatim
+  *
+  *          ===================================================================
+  *                                   How to use this driver
+  *          ===================================================================
+
+  *          1.  Enable the ADC interface clock using 
+  *                  RCC_APB2PeriphClockCmd(RCC_APB2Periph_ADCx, ENABLE); 
+  *     
+  *          2. ADC pins configuration
+  *               - Enable the clock for the ADC GPIOs using the following function:
+  *                   RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);   
+  *                - Configure these ADC pins in analog mode using GPIO_Init();  
+  *
+  *          3. Configure the ADC Prescaler, conversion resolution and data 
+  *              alignment using the ADC_Init() function.
+  *          4. Activate the ADC peripheral using ADC_Cmd() function.
+  *
+  *          Regular channels group configuration
+  *          ====================================    
+  *            - To configure the ADC regular channels group features, use 
+  *              ADC_Init() and ADC_RegularChannelConfig() functions.
+  *            - To activate the continuous mode, use the ADC_continuousModeCmd()
+  *              function.
+  *            - To configurate and activate the Discontinuous mode, use the 
+  *              ADC_DiscModeChannelCountConfig() and ADC_DiscModeCmd() functions.
+  *            - To read the ADC converted values, use the ADC_GetConversionValue()
+  *              function.
+  *
+  *          Multi mode ADCs Regular channels configuration
+  *          ===============================================
+  *            - Refer to "Regular channels group configuration" description to
+  *              configure the ADC1, ADC2 and ADC3 regular channels.        
+  *            - Select the Multi mode ADC regular channels features (dual or 
+  *              triple mode) using ADC_CommonInit() function and configure 
+  *              the DMA mode using ADC_MultiModeDMARequestAfterLastTransferCmd() 
+  *              functions.        
+  *            - Read the ADCs converted values using the 
+  *              ADC_GetMultiModeConversionValue() function.
+  *
+  *          DMA for Regular channels group features configuration
+  *          ====================================================== 
+  *           - To enable the DMA mode for regular channels group, use the 
+  *             ADC_DMACmd() function.
+  *           - To enable the generation of DMA requests continuously at the end
+  *             of the last DMA transfer, use the ADC_DMARequestAfterLastTransferCmd() 
+  *             function.
+  *
+  *          Injected channels group configuration
+  *          =====================================    
+  *            - To configure the ADC Injected channels group features, use 
+  *              ADC_InjectedChannelConfig() and  ADC_InjectedSequencerLengthConfig()
+  *              functions.
+  *            - To activate the continuous mode, use the ADC_continuousModeCmd()
+  *              function.
+  *            - To activate the Injected Discontinuous mode, use the 
+  *              ADC_InjectedDiscModeCmd() function.  
+  *            - To activate the AutoInjected mode, use the ADC_AutoInjectedConvCmd() 
+  *              function.        
+  *            - To read the ADC converted values, use the ADC_GetInjectedConversionValue() 
+  *              function.
+  *
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************  
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_adc.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup ADC 
+  * @brief ADC driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/ 
+
+/* ADC DISCNUM mask */
+#define CR1_DISCNUM_RESET         ((uint32_t)0xFFFF1FFF)
+
+/* ADC AWDCH mask */
+#define CR1_AWDCH_RESET           ((uint32_t)0xFFFFFFE0)   
+
+/* ADC Analog watchdog enable mode mask */
+#define CR1_AWDMode_RESET         ((uint32_t)0xFF3FFDFF)   
+
+/* CR1 register Mask */
+#define CR1_CLEAR_MASK            ((uint32_t)0xFCFFFEFF)
+
+/* ADC EXTEN mask */
+#define CR2_EXTEN_RESET           ((uint32_t)0xCFFFFFFF)  
+
+/* ADC JEXTEN mask */
+#define CR2_JEXTEN_RESET          ((uint32_t)0xFFCFFFFF)  
+
+/* ADC JEXTSEL mask */
+#define CR2_JEXTSEL_RESET         ((uint32_t)0xFFF0FFFF)  
+
+/* CR2 register Mask */
+#define CR2_CLEAR_MASK            ((uint32_t)0xC0FFF7FD)
+
+/* ADC SQx mask */
+#define SQR3_SQ_SET               ((uint32_t)0x0000001F)  
+#define SQR2_SQ_SET               ((uint32_t)0x0000001F)  
+#define SQR1_SQ_SET               ((uint32_t)0x0000001F)  
+
+/* ADC L Mask */
+#define SQR1_L_RESET              ((uint32_t)0xFF0FFFFF) 
+
+/* ADC JSQx mask */
+#define JSQR_JSQ_SET              ((uint32_t)0x0000001F) 
+
+/* ADC JL mask */
+#define JSQR_JL_SET               ((uint32_t)0x00300000) 
+#define JSQR_JL_RESET             ((uint32_t)0xFFCFFFFF) 
+
+/* ADC SMPx mask */
+#define SMPR1_SMP_SET             ((uint32_t)0x00000007)  
+#define SMPR2_SMP_SET             ((uint32_t)0x00000007) 
+
+/* ADC JDRx registers offset */
+#define JDR_OFFSET                ((uint8_t)0x28) 
+
+/* ADC CDR register base address */
+#define CDR_ADDRESS               ((uint32_t)0x40012308)   
+
+/* ADC CCR register Mask */
+#define CR_CLEAR_MASK             ((uint32_t)0xFFFC30E0)  
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup ADC_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup ADC_Group1 Initialization and Configuration functions
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+                      Initialization and Configuration functions
+ ===============================================================================  
+  This section provides functions allowing to:
+   - Initialize and configure the ADC Prescaler
+   - ADC Conversion Resolution (12bit..6bit)
+   - Scan Conversion Mode (multichannels or one channel) for regular group
+   - ADC Continuous Conversion Mode (Continuous or Single conversion) for 
+     regular group
+   - External trigger Edge and source of regular group, 
+   - Converted data alignment (left or right)
+   - The number of ADC conversions that will be done using the sequencer for 
+     regular channel group
+   - Multi ADC mode selection
+   - Direct memory access mode selection for multi ADC mode  
+   - Delay between 2 sampling phases (used in dual or triple interleaved modes)
+   - Enable or disable the ADC peripheral
+   
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes all ADCs peripherals registers to their default reset 
+  *         values.
+  * @param  None
+  * @retval None
+  */
+void ADC_DeInit(void)
+{
+  /* Enable all ADCs reset state */
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, ENABLE);
+  
+  /* Release all ADCs from reset state */
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_ADC, DISABLE);
+}
+
+/**
+  * @brief  Initializes the ADCx peripheral according to the specified parameters 
+  *         in the ADC_InitStruct.
+  * @note   This function is used to configure the global features of the ADC ( 
+  *         Resolution and Data Alignment), however, the rest of the configuration
+  *         parameters are specific to the regular channels group (scan mode 
+  *         activation, continuous mode activation, External trigger source and 
+  *         edge, number of conversion in the regular channels group sequencer).  
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure that contains
+  *         the configuration information for the specified ADC peripheral.
+  * @retval None
+  */
+void ADC_Init(ADC_TypeDef* ADCx, ADC_InitTypeDef* ADC_InitStruct)
+{
+  uint32_t tmpreg1 = 0;
+  uint8_t tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_RESOLUTION(ADC_InitStruct->ADC_Resolution)); 
+  assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ScanConvMode));
+  assert_param(IS_FUNCTIONAL_STATE(ADC_InitStruct->ADC_ContinuousConvMode)); 
+  assert_param(IS_ADC_EXT_TRIG_EDGE(ADC_InitStruct->ADC_ExternalTrigConvEdge)); 
+  assert_param(IS_ADC_EXT_TRIG(ADC_InitStruct->ADC_ExternalTrigConv));    
+  assert_param(IS_ADC_DATA_ALIGN(ADC_InitStruct->ADC_DataAlign)); 
+  assert_param(IS_ADC_REGULAR_LENGTH(ADC_InitStruct->ADC_NbrOfConversion));
+  
+  /*---------------------------- ADCx CR1 Configuration -----------------*/
+  /* Get the ADCx CR1 value */
+  tmpreg1 = ADCx->CR1;
+  
+  /* Clear RES and SCAN bits */
+  tmpreg1 &= CR1_CLEAR_MASK;
+  
+  /* Configure ADCx: scan conversion mode and resolution */
+  /* Set SCAN bit according to ADC_ScanConvMode value */
+  /* Set RES bit according to ADC_Resolution value */ 
+  tmpreg1 |= (uint32_t)(((uint32_t)ADC_InitStruct->ADC_ScanConvMode << 8) | \
+                                   ADC_InitStruct->ADC_Resolution);
+  /* Write to ADCx CR1 */
+  ADCx->CR1 = tmpreg1;
+  /*---------------------------- ADCx CR2 Configuration -----------------*/
+  /* Get the ADCx CR2 value */
+  tmpreg1 = ADCx->CR2;
+  
+  /* Clear CONT, ALIGN, EXTEN and EXTSEL bits */
+  tmpreg1 &= CR2_CLEAR_MASK;
+  
+  /* Configure ADCx: external trigger event and edge, data alignment and 
+     continuous conversion mode */
+  /* Set ALIGN bit according to ADC_DataAlign value */
+  /* Set EXTEN bits according to ADC_ExternalTrigConvEdge value */ 
+  /* Set EXTSEL bits according to ADC_ExternalTrigConv value */
+  /* Set CONT bit according to ADC_ContinuousConvMode value */
+  tmpreg1 |= (uint32_t)(ADC_InitStruct->ADC_DataAlign | \
+                        ADC_InitStruct->ADC_ExternalTrigConv | 
+                        ADC_InitStruct->ADC_ExternalTrigConvEdge | \
+                        ((uint32_t)ADC_InitStruct->ADC_ContinuousConvMode << 1));
+                        
+  /* Write to ADCx CR2 */
+  ADCx->CR2 = tmpreg1;
+  /*---------------------------- ADCx SQR1 Configuration -----------------*/
+  /* Get the ADCx SQR1 value */
+  tmpreg1 = ADCx->SQR1;
+  
+  /* Clear L bits */
+  tmpreg1 &= SQR1_L_RESET;
+  
+  /* Configure ADCx: regular channel sequence length */
+  /* Set L bits according to ADC_NbrOfConversion value */
+  tmpreg2 |= (uint8_t)(ADC_InitStruct->ADC_NbrOfConversion - (uint8_t)1);
+  tmpreg1 |= ((uint32_t)tmpreg2 << 20);
+  
+  /* Write to ADCx SQR1 */
+  ADCx->SQR1 = tmpreg1;
+}
+
+/**
+  * @brief  Fills each ADC_InitStruct member with its default value.
+  * @note   This function is used to initialize the global features of the ADC ( 
+  *         Resolution and Data Alignment), however, the rest of the configuration
+  *         parameters are specific to the regular channels group (scan mode 
+  *         activation, continuous mode activation, External trigger source and 
+  *         edge, number of conversion in the regular channels group sequencer).  
+  * @param  ADC_InitStruct: pointer to an ADC_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void ADC_StructInit(ADC_InitTypeDef* ADC_InitStruct)
+{
+  /* Initialize the ADC_Mode member */
+  ADC_InitStruct->ADC_Resolution = ADC_Resolution_12b;
+
+  /* initialize the ADC_ScanConvMode member */
+  ADC_InitStruct->ADC_ScanConvMode = DISABLE;
+
+  /* Initialize the ADC_ContinuousConvMode member */
+  ADC_InitStruct->ADC_ContinuousConvMode = DISABLE;
+
+  /* Initialize the ADC_ExternalTrigConvEdge member */
+  ADC_InitStruct->ADC_ExternalTrigConvEdge = ADC_ExternalTrigConvEdge_None;
+
+  /* Initialize the ADC_ExternalTrigConv member */
+  ADC_InitStruct->ADC_ExternalTrigConv = ADC_ExternalTrigConv_T1_CC1;
+
+  /* Initialize the ADC_DataAlign member */
+  ADC_InitStruct->ADC_DataAlign = ADC_DataAlign_Right;
+
+  /* Initialize the ADC_NbrOfConversion member */
+  ADC_InitStruct->ADC_NbrOfConversion = 1;
+}
+
+/**
+  * @brief  Initializes the ADCs peripherals according to the specified parameters 
+  *         in the ADC_CommonInitStruct.
+  * @param  ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure 
+  *         that contains the configuration information for  All ADCs peripherals.
+  * @retval None
+  */
+void ADC_CommonInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
+{
+  uint32_t tmpreg1 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_MODE(ADC_CommonInitStruct->ADC_Mode));
+  assert_param(IS_ADC_PRESCALER(ADC_CommonInitStruct->ADC_Prescaler));
+  assert_param(IS_ADC_DMA_ACCESS_MODE(ADC_CommonInitStruct->ADC_DMAAccessMode));
+  assert_param(IS_ADC_SAMPLING_DELAY(ADC_CommonInitStruct->ADC_TwoSamplingDelay));
+  /*---------------------------- ADC CCR Configuration -----------------*/
+  /* Get the ADC CCR value */
+  tmpreg1 = ADC->CCR;
+  
+  /* Clear MULTI, DELAY, DMA and ADCPRE bits */
+  tmpreg1 &= CR_CLEAR_MASK;
+  
+  /* Configure ADCx: Multi mode, Delay between two sampling time, ADC prescaler,
+     and DMA access mode for multimode */
+  /* Set MULTI bits according to ADC_Mode value */
+  /* Set ADCPRE bits according to ADC_Prescaler value */
+  /* Set DMA bits according to ADC_DMAAccessMode value */
+  /* Set DELAY bits according to ADC_TwoSamplingDelay value */    
+  tmpreg1 |= (uint32_t)(ADC_CommonInitStruct->ADC_Mode | 
+                        ADC_CommonInitStruct->ADC_Prescaler | 
+                        ADC_CommonInitStruct->ADC_DMAAccessMode | 
+                        ADC_CommonInitStruct->ADC_TwoSamplingDelay);
+                        
+  /* Write to ADC CCR */
+  ADC->CCR = tmpreg1;
+}
+
+/**
+  * @brief  Fills each ADC_CommonInitStruct member with its default value.
+  * @param  ADC_CommonInitStruct: pointer to an ADC_CommonInitTypeDef structure
+  *         which will be initialized.
+  * @retval None
+  */
+void ADC_CommonStructInit(ADC_CommonInitTypeDef* ADC_CommonInitStruct)
+{
+  /* Initialize the ADC_Mode member */
+  ADC_CommonInitStruct->ADC_Mode = ADC_Mode_Independent;
+
+  /* initialize the ADC_Prescaler member */
+  ADC_CommonInitStruct->ADC_Prescaler = ADC_Prescaler_Div2;
+
+  /* Initialize the ADC_DMAAccessMode member */
+  ADC_CommonInitStruct->ADC_DMAAccessMode = ADC_DMAAccessMode_Disabled;
+
+  /* Initialize the ADC_TwoSamplingDelay member */
+  ADC_CommonInitStruct->ADC_TwoSamplingDelay = ADC_TwoSamplingDelay_5Cycles;
+}
+
+/**
+  * @brief  Enables or disables the specified ADC peripheral.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the ADCx peripheral. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_Cmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the ADON bit to wake up the ADC from power down mode */
+    ADCx->CR2 |= (uint32_t)ADC_CR2_ADON;
+  }
+  else
+  {
+    /* Disable the selected ADC peripheral */
+    ADCx->CR2 &= (uint32_t)(~ADC_CR2_ADON);
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group2 Analog Watchdog configuration functions
+ *  @brief    Analog Watchdog configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                    Analog Watchdog configuration functions
+ ===============================================================================  
+
+  This section provides functions allowing to configure the Analog Watchdog
+  (AWD) feature in the ADC.
+  
+  A typical configuration Analog Watchdog is done following these steps :
+   1. the ADC guarded channel(s) is (are) selected using the 
+      ADC_AnalogWatchdogSingleChannelConfig() function.
+   2. The Analog watchdog lower and higher threshold are configured using the  
+     ADC_AnalogWatchdogThresholdsConfig() function.
+   3. The Analog watchdog is enabled and configured to enable the check, on one
+      or more channels, using the  ADC_AnalogWatchdogCmd() function.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Enables or disables the analog watchdog on single/all regular or 
+  *         injected channels
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_AnalogWatchdog: the ADC analog watchdog configuration.
+  *         This parameter can be one of the following values:
+  *            @arg ADC_AnalogWatchdog_SingleRegEnable: Analog watchdog on a single regular channel
+  *            @arg ADC_AnalogWatchdog_SingleInjecEnable: Analog watchdog on a single injected channel
+  *            @arg ADC_AnalogWatchdog_SingleRegOrInjecEnable: Analog watchdog on a single regular or injected channel
+  *            @arg ADC_AnalogWatchdog_AllRegEnable: Analog watchdog on all regular channel
+  *            @arg ADC_AnalogWatchdog_AllInjecEnable: Analog watchdog on all injected channel
+  *            @arg ADC_AnalogWatchdog_AllRegAllInjecEnable: Analog watchdog on all regular and injected channels
+  *            @arg ADC_AnalogWatchdog_None: No channel guarded by the analog watchdog
+  * @retval None	  
+  */
+void ADC_AnalogWatchdogCmd(ADC_TypeDef* ADCx, uint32_t ADC_AnalogWatchdog)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_ANALOG_WATCHDOG(ADC_AnalogWatchdog));
+  
+  /* Get the old register value */
+  tmpreg = ADCx->CR1;
+  
+  /* Clear AWDEN, JAWDEN and AWDSGL bits */
+  tmpreg &= CR1_AWDMode_RESET;
+  
+  /* Set the analog watchdog enable mode */
+  tmpreg |= ADC_AnalogWatchdog;
+  
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg;
+}
+
+/**
+  * @brief  Configures the high and low thresholds of the analog watchdog.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  HighThreshold: the ADC analog watchdog High threshold value.
+  *          This parameter must be a 12-bit value.
+  * @param  LowThreshold:  the ADC analog watchdog Low threshold value.
+  *          This parameter must be a 12-bit value.
+  * @retval None
+  */
+void ADC_AnalogWatchdogThresholdsConfig(ADC_TypeDef* ADCx, uint16_t HighThreshold,
+                                        uint16_t LowThreshold)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_THRESHOLD(HighThreshold));
+  assert_param(IS_ADC_THRESHOLD(LowThreshold));
+  
+  /* Set the ADCx high threshold */
+  ADCx->HTR = HighThreshold;
+  
+  /* Set the ADCx low threshold */
+  ADCx->LTR = LowThreshold;
+}
+
+/**
+  * @brief  Configures the analog watchdog guarded single channel
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure for the analog watchdog. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_Channel_0: ADC Channel0 selected
+  *            @arg ADC_Channel_1: ADC Channel1 selected
+  *            @arg ADC_Channel_2: ADC Channel2 selected
+  *            @arg ADC_Channel_3: ADC Channel3 selected
+  *            @arg ADC_Channel_4: ADC Channel4 selected
+  *            @arg ADC_Channel_5: ADC Channel5 selected
+  *            @arg ADC_Channel_6: ADC Channel6 selected
+  *            @arg ADC_Channel_7: ADC Channel7 selected
+  *            @arg ADC_Channel_8: ADC Channel8 selected
+  *            @arg ADC_Channel_9: ADC Channel9 selected
+  *            @arg ADC_Channel_10: ADC Channel10 selected
+  *            @arg ADC_Channel_11: ADC Channel11 selected
+  *            @arg ADC_Channel_12: ADC Channel12 selected
+  *            @arg ADC_Channel_13: ADC Channel13 selected
+  *            @arg ADC_Channel_14: ADC Channel14 selected
+  *            @arg ADC_Channel_15: ADC Channel15 selected
+  *            @arg ADC_Channel_16: ADC Channel16 selected
+  *            @arg ADC_Channel_17: ADC Channel17 selected
+  *            @arg ADC_Channel_18: ADC Channel18 selected
+  * @retval None
+  */
+void ADC_AnalogWatchdogSingleChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  
+  /* Get the old register value */
+  tmpreg = ADCx->CR1;
+  
+  /* Clear the Analog watchdog channel select bits */
+  tmpreg &= CR1_AWDCH_RESET;
+  
+  /* Set the Analog watchdog channel */
+  tmpreg |= ADC_Channel;
+  
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg;
+}
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group3 Temperature Sensor, Vrefint (Voltage Reference internal) 
+ *            and VBAT (Voltage BATtery) management functions
+ *  @brief   Temperature Sensor, Vrefint and VBAT management functions 
+ *
+@verbatim   
+ ===============================================================================
+               Temperature Sensor, Vrefint and VBAT management functions
+ ===============================================================================  
+
+  This section provides functions allowing to enable/ disable the internal 
+  connections between the ADC and the Temperature Sensor, the Vrefint and the
+  Vbat sources.
+     
+  A typical configuration to get the Temperature sensor and Vrefint channels 
+  voltages is done following these steps :
+   1. Enable the internal connection of Temperature sensor and Vrefint sources 
+      with the ADC channels using ADC_TempSensorVrefintCmd() function. 
+   2. Select the ADC_Channel_TempSensor and/or ADC_Channel_Vrefint using 
+      ADC_RegularChannelConfig() or  ADC_InjectedChannelConfig() functions 
+   3. Get the voltage values, using ADC_GetConversionValue() or  
+      ADC_GetInjectedConversionValue().
+
+  A typical configuration to get the VBAT channel voltage is done following 
+  these steps :
+   1. Enable the internal connection of VBAT source with the ADC channel using 
+      ADC_VBATCmd() function. 
+   2. Select the ADC_Channel_Vbat using ADC_RegularChannelConfig() or  
+      ADC_InjectedChannelConfig() functions 
+   3. Get the voltage value, using ADC_GetConversionValue() or  
+      ADC_GetInjectedConversionValue().
+ 
+@endverbatim
+  * @{
+  */
+  
+  
+/**
+  * @brief  Enables or disables the temperature sensor and Vrefint channels.
+  * @param  NewState: new state of the temperature sensor and Vrefint channels.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_TempSensorVrefintCmd(FunctionalState NewState)                
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the temperature sensor and Vrefint channel*/
+    ADC->CCR |= (uint32_t)ADC_CCR_TSVREFE;
+  }
+  else
+  {
+    /* Disable the temperature sensor and Vrefint channel*/
+    ADC->CCR &= (uint32_t)(~ADC_CCR_TSVREFE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the VBAT (Voltage Battery) channel.
+  * @param  NewState: new state of the VBAT channel.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_VBATCmd(FunctionalState NewState)                             
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the VBAT channel*/
+    ADC->CCR |= (uint32_t)ADC_CCR_VBATE;
+  }
+  else
+  {
+    /* Disable the VBAT channel*/
+    ADC->CCR &= (uint32_t)(~ADC_CCR_VBATE);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group4 Regular Channels Configuration functions
+ *  @brief   Regular Channels Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                  Regular Channels Configuration functions
+ ===============================================================================  
+
+  This section provides functions allowing to manage the ADC's regular channels,
+  it is composed of 2 sub sections : 
+  
+  1. Configuration and management functions for regular channels: This subsection 
+     provides functions allowing to configure the ADC regular channels :    
+          - Configure the rank in the regular group sequencer for each channel
+          - Configure the sampling time for each channel
+          - select the conversion Trigger for regular channels
+          - select the desired EOC event behavior configuration
+          - Activate the continuous Mode  (*)
+          - Activate the Discontinuous Mode 
+     Please Note that the following features for regular channels are configurated
+     using the ADC_Init() function : 
+          - scan mode activation 
+          - continuous mode activation (**) 
+          - External trigger source  
+          - External trigger edge 
+          - number of conversion in the regular channels group sequencer.
+     
+     @note (*) and (**) are performing the same configuration
+     
+  2. Get the conversion data: This subsection provides an important function in 
+     the ADC peripheral since it returns the converted data of the current 
+     regular channel. When the Conversion value is read, the EOC Flag is 
+     automatically cleared.
+     
+     @note For multi ADC mode, the last ADC1, ADC2 and ADC3 regular conversions 
+           results data (in the selected multi mode) can be returned in the same 
+           time using ADC_GetMultiModeConversionValue() function. 
+       
+  
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Configures for the selected ADC regular channel its corresponding
+  *         rank in the sequencer and its sample time.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_Channel_0: ADC Channel0 selected
+  *            @arg ADC_Channel_1: ADC Channel1 selected
+  *            @arg ADC_Channel_2: ADC Channel2 selected
+  *            @arg ADC_Channel_3: ADC Channel3 selected
+  *            @arg ADC_Channel_4: ADC Channel4 selected
+  *            @arg ADC_Channel_5: ADC Channel5 selected
+  *            @arg ADC_Channel_6: ADC Channel6 selected
+  *            @arg ADC_Channel_7: ADC Channel7 selected
+  *            @arg ADC_Channel_8: ADC Channel8 selected
+  *            @arg ADC_Channel_9: ADC Channel9 selected
+  *            @arg ADC_Channel_10: ADC Channel10 selected
+  *            @arg ADC_Channel_11: ADC Channel11 selected
+  *            @arg ADC_Channel_12: ADC Channel12 selected
+  *            @arg ADC_Channel_13: ADC Channel13 selected
+  *            @arg ADC_Channel_14: ADC Channel14 selected
+  *            @arg ADC_Channel_15: ADC Channel15 selected
+  *            @arg ADC_Channel_16: ADC Channel16 selected
+  *            @arg ADC_Channel_17: ADC Channel17 selected
+  *            @arg ADC_Channel_18: ADC Channel18 selected                       
+  * @param  Rank: The rank in the regular group sequencer.
+  *          This parameter must be between 1 to 16.
+  * @param  ADC_SampleTime: The sample time value to be set for the selected channel. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
+  *            @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
+  *            @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
+  *            @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles	
+  *            @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles	
+  *            @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles	
+  *            @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles	
+  *            @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles	
+  * @retval None
+  */
+void ADC_RegularChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  assert_param(IS_ADC_REGULAR_RANK(Rank));
+  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+  
+  /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
+  if (ADC_Channel > ADC_Channel_9)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR1;
+    
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR1_SMP_SET << (3 * (ADC_Channel - 10));
+    
+    /* Clear the old sample time */
+    tmpreg1 &= ~tmpreg2;
+    
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * (ADC_Channel - 10));
+    
+    /* Set the new sample time */
+    tmpreg1 |= tmpreg2;
+    
+    /* Store the new register value */
+    ADCx->SMPR1 = tmpreg1;
+  }
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR2;
+    
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
+    
+    /* Clear the old sample time */
+    tmpreg1 &= ~tmpreg2;
+    
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+    
+    /* Set the new sample time */
+    tmpreg1 |= tmpreg2;
+    
+    /* Store the new register value */
+    ADCx->SMPR2 = tmpreg1;
+  }
+  /* For Rank 1 to 6 */
+  if (Rank < 7)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR3;
+    
+    /* Calculate the mask to clear */
+    tmpreg2 = SQR3_SQ_SET << (5 * (Rank - 1));
+    
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 1));
+    
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    
+    /* Store the new register value */
+    ADCx->SQR3 = tmpreg1;
+  }
+  /* For Rank 7 to 12 */
+  else if (Rank < 13)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR2;
+    
+    /* Calculate the mask to clear */
+    tmpreg2 = SQR2_SQ_SET << (5 * (Rank - 7));
+    
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 7));
+    
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    
+    /* Store the new register value */
+    ADCx->SQR2 = tmpreg1;
+  }
+  /* For Rank 13 to 16 */
+  else
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SQR1;
+    
+    /* Calculate the mask to clear */
+    tmpreg2 = SQR1_SQ_SET << (5 * (Rank - 13));
+    
+    /* Clear the old SQx bits for the selected rank */
+    tmpreg1 &= ~tmpreg2;
+    
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_Channel << (5 * (Rank - 13));
+    
+    /* Set the SQx bits for the selected rank */
+    tmpreg1 |= tmpreg2;
+    
+    /* Store the new register value */
+    ADCx->SQR1 = tmpreg1;
+  }
+}
+
+/**
+  * @brief  Enables the selected ADC software start conversion of the regular channels.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval None
+  */
+void ADC_SoftwareStartConv(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  
+  /* Enable the selected ADC conversion for regular group */
+  ADCx->CR2 |= (uint32_t)ADC_CR2_SWSTART;
+}
+
+/**
+  * @brief  Gets the selected ADC Software start regular conversion Status.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The new state of ADC software start conversion (SET or RESET).
+  */
+FlagStatus ADC_GetSoftwareStartConvStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  
+  /* Check the status of SWSTART bit */
+  if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
+  {
+    /* SWSTART bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SWSTART bit is reset */
+    bitstatus = RESET;
+  }
+  
+  /* Return the SWSTART bit status */
+  return  bitstatus;
+}
+
+
+/**
+  * @brief  Enables or disables the EOC on each regular channel conversion
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC EOC flag rising
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_EOCOnEachRegularChannelCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC EOC rising on each regular channel conversion */
+    ADCx->CR2 |= (uint32_t)ADC_CR2_EOCS;
+  }
+  else
+  {
+    /* Disable the selected ADC EOC rising on each regular channel conversion */
+    ADCx->CR2 &= (uint32_t)(~ADC_CR2_EOCS);
+  }
+}
+
+/**
+  * @brief  Enables or disables the ADC continuous conversion mode 
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC continuous conversion mode
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ContinuousModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC continuous conversion mode */
+    ADCx->CR2 |= (uint32_t)ADC_CR2_CONT;
+  }
+  else
+  {
+    /* Disable the selected ADC continuous conversion mode */
+    ADCx->CR2 &= (uint32_t)(~ADC_CR2_CONT);
+  }
+}
+
+/**
+  * @brief  Configures the discontinuous mode for the selected ADC regular group 
+  *         channel.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  Number: specifies the discontinuous mode regular channel count value.
+  *          This number must be between 1 and 8.
+  * @retval None
+  */
+void ADC_DiscModeChannelCountConfig(ADC_TypeDef* ADCx, uint8_t Number)
+{
+  uint32_t tmpreg1 = 0;
+  uint32_t tmpreg2 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_REGULAR_DISC_NUMBER(Number));
+  
+  /* Get the old register value */
+  tmpreg1 = ADCx->CR1;
+  
+  /* Clear the old discontinuous mode channel count */
+  tmpreg1 &= CR1_DISCNUM_RESET;
+  
+  /* Set the discontinuous mode channel count */
+  tmpreg2 = Number - 1;
+  tmpreg1 |= tmpreg2 << 13;
+  
+  /* Store the new register value */
+  ADCx->CR1 = tmpreg1;
+}
+
+/**
+  * @brief  Enables or disables the discontinuous mode on regular group channel 
+  *         for the specified ADC
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC discontinuous mode on 
+  *         regular group channel.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_DiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC regular discontinuous mode */
+    ADCx->CR1 |= (uint32_t)ADC_CR1_DISCEN;
+  }
+  else
+  {
+    /* Disable the selected ADC regular discontinuous mode */
+    ADCx->CR1 &= (uint32_t)(~ADC_CR1_DISCEN);
+  }
+}
+
+/**
+  * @brief  Returns the last ADCx conversion result data for regular channel.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The Data conversion value.
+  */
+uint16_t ADC_GetConversionValue(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  
+  /* Return the selected ADC conversion value */
+  return (uint16_t) ADCx->DR;
+}
+
+/**
+  * @brief  Returns the last ADC1, ADC2 and ADC3 regular conversions results 
+  *         data in the selected multi mode.
+  * @param  None  
+  * @retval The Data conversion value.
+  * @note   In dual mode, the value returned by this function is as following
+  *           Data[15:0] : these bits contain the regular data of ADC1.
+  *           Data[31:16]: these bits contain the regular data of ADC2.
+  * @note   In triple mode, the value returned by this function is as following
+  *           Data[15:0] : these bits contain alternatively the regular data of ADC1, ADC3 and ADC2.
+  *           Data[31:16]: these bits contain alternatively the regular data of ADC2, ADC1 and ADC3.           
+  */
+uint32_t ADC_GetMultiModeConversionValue(void)
+{
+  /* Return the multi mode conversion value */
+  return (*(__IO uint32_t *) CDR_ADDRESS);
+}
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group5 Regular Channels DMA Configuration functions
+ *  @brief   Regular Channels DMA Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                   Regular Channels DMA Configuration functions
+ ===============================================================================  
+
+  This section provides functions allowing to configure the DMA for ADC regular 
+  channels.
+  Since converted regular channel values are stored into a unique data register, 
+  it is useful to use DMA for conversion of more than one regular channel. This 
+  avoids the loss of the data already stored in the ADC Data register. 
+  
+  When the DMA mode is enabled (using the ADC_DMACmd() function), after each
+  conversion of a regular channel, a DMA request is generated.
+  
+  Depending on the "DMA disable selection for Independent ADC mode" 
+  configuration (using the ADC_DMARequestAfterLastTransferCmd() function), 
+  at the end of the last DMA transfer, two possibilities are allowed:
+  - No new DMA request is issued to the DMA controller (feature DISABLED) 
+  - Requests can continue to be generated (feature ENABLED).
+  
+  Depending on the "DMA disable selection for multi ADC mode" configuration 
+  (using the void ADC_MultiModeDMARequestAfterLastTransferCmd() function), 
+  at the end of the last DMA transfer, two possibilities are allowed:
+  - No new DMA request is issued to the DMA controller (feature DISABLED) 
+  - Requests can continue to be generated (feature ENABLED).
+
+@endverbatim
+  * @{
+  */
+  
+ /**
+  * @brief  Enables or disables the specified ADC DMA request.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC DMA transfer.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_DMACmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC DMA request */
+    ADCx->CR2 |= (uint32_t)ADC_CR2_DMA;
+  }
+  else
+  {
+    /* Disable the selected ADC DMA request */
+    ADCx->CR2 &= (uint32_t)(~ADC_CR2_DMA);
+  }
+}
+
+/**
+  * @brief  Enables or disables the ADC DMA request after last transfer (Single-ADC mode)  
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC DMA request after last transfer.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_DMARequestAfterLastTransferCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC DMA request after last transfer */
+    ADCx->CR2 |= (uint32_t)ADC_CR2_DDS;
+  }
+  else
+  {
+    /* Disable the selected ADC DMA request after last transfer */
+    ADCx->CR2 &= (uint32_t)(~ADC_CR2_DDS);
+  }
+}
+
+/**
+  * @brief  Enables or disables the ADC DMA request after last transfer in multi ADC mode       
+  * @param  NewState: new state of the selected ADC DMA request after last transfer.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   if Enabled, DMA requests are issued as long as data are converted and 
+  *         DMA mode for multi ADC mode (selected using ADC_CommonInit() function 
+  *         by ADC_CommonInitStruct.ADC_DMAAccessMode structure member) is 
+  *          ADC_DMAAccessMode_1, ADC_DMAAccessMode_2 or ADC_DMAAccessMode_3.     
+  * @retval None
+  */
+void ADC_MultiModeDMARequestAfterLastTransferCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC DMA request after last transfer */
+    ADC->CCR |= (uint32_t)ADC_CCR_DDS;
+  }
+  else
+  {
+    /* Disable the selected ADC DMA request after last transfer */
+    ADC->CCR &= (uint32_t)(~ADC_CCR_DDS);
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group6 Injected channels Configuration functions
+ *  @brief   Injected channels Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                     Injected channels Configuration functions
+ ===============================================================================  
+
+  This section provide functions allowing to configure the ADC Injected channels,
+  it is composed of 2 sub sections : 
+    
+  1. Configuration functions for Injected channels: This subsection provides 
+     functions allowing to configure the ADC injected channels :    
+    - Configure the rank in the injected group sequencer for each channel
+    - Configure the sampling time for each channel    
+    - Activate the Auto injected Mode  
+    - Activate the Discontinuous Mode 
+    - scan mode activation  
+    - External/software trigger source   
+    - External trigger edge 
+    - injected channels sequencer.
+    
+   2. Get the Specified Injected channel conversion data: This subsection 
+      provides an important function in the ADC peripheral since it returns the 
+      converted data of the specific injected channel.
+
+@endverbatim
+  * @{
+  */ 
+/**
+  * @brief  Configures for the selected ADC injected channel its corresponding
+  *         rank in the sequencer and its sample time.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_Channel: the ADC channel to configure. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_Channel_0: ADC Channel0 selected
+  *            @arg ADC_Channel_1: ADC Channel1 selected
+  *            @arg ADC_Channel_2: ADC Channel2 selected
+  *            @arg ADC_Channel_3: ADC Channel3 selected
+  *            @arg ADC_Channel_4: ADC Channel4 selected
+  *            @arg ADC_Channel_5: ADC Channel5 selected
+  *            @arg ADC_Channel_6: ADC Channel6 selected
+  *            @arg ADC_Channel_7: ADC Channel7 selected
+  *            @arg ADC_Channel_8: ADC Channel8 selected
+  *            @arg ADC_Channel_9: ADC Channel9 selected
+  *            @arg ADC_Channel_10: ADC Channel10 selected
+  *            @arg ADC_Channel_11: ADC Channel11 selected
+  *            @arg ADC_Channel_12: ADC Channel12 selected
+  *            @arg ADC_Channel_13: ADC Channel13 selected
+  *            @arg ADC_Channel_14: ADC Channel14 selected
+  *            @arg ADC_Channel_15: ADC Channel15 selected
+  *            @arg ADC_Channel_16: ADC Channel16 selected
+  *            @arg ADC_Channel_17: ADC Channel17 selected
+  *            @arg ADC_Channel_18: ADC Channel18 selected                       
+  * @param  Rank: The rank in the injected group sequencer. 
+  *          This parameter must be between 1 to 4.
+  * @param  ADC_SampleTime: The sample time value to be set for the selected channel. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_SampleTime_3Cycles: Sample time equal to 3 cycles
+  *            @arg ADC_SampleTime_15Cycles: Sample time equal to 15 cycles
+  *            @arg ADC_SampleTime_28Cycles: Sample time equal to 28 cycles
+  *            @arg ADC_SampleTime_56Cycles: Sample time equal to 56 cycles	
+  *            @arg ADC_SampleTime_84Cycles: Sample time equal to 84 cycles	
+  *            @arg ADC_SampleTime_112Cycles: Sample time equal to 112 cycles	
+  *            @arg ADC_SampleTime_144Cycles: Sample time equal to 144 cycles	
+  *            @arg ADC_SampleTime_480Cycles: Sample time equal to 480 cycles	
+  * @retval None
+  */
+void ADC_InjectedChannelConfig(ADC_TypeDef* ADCx, uint8_t ADC_Channel, uint8_t Rank, uint8_t ADC_SampleTime)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0, tmpreg3 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CHANNEL(ADC_Channel));
+  assert_param(IS_ADC_INJECTED_RANK(Rank));
+  assert_param(IS_ADC_SAMPLE_TIME(ADC_SampleTime));
+  /* if ADC_Channel_10 ... ADC_Channel_18 is selected */
+  if (ADC_Channel > ADC_Channel_9)
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR1;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR1_SMP_SET << (3*(ADC_Channel - 10));
+    /* Clear the old sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3*(ADC_Channel - 10));
+    /* Set the new sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR1 = tmpreg1;
+  }
+  else /* ADC_Channel include in ADC_Channel_[0..9] */
+  {
+    /* Get the old register value */
+    tmpreg1 = ADCx->SMPR2;
+    /* Calculate the mask to clear */
+    tmpreg2 = SMPR2_SMP_SET << (3 * ADC_Channel);
+    /* Clear the old sample time */
+    tmpreg1 &= ~tmpreg2;
+    /* Calculate the mask to set */
+    tmpreg2 = (uint32_t)ADC_SampleTime << (3 * ADC_Channel);
+    /* Set the new sample time */
+    tmpreg1 |= tmpreg2;
+    /* Store the new register value */
+    ADCx->SMPR2 = tmpreg1;
+  }
+  /* Rank configuration */
+  /* Get the old register value */
+  tmpreg1 = ADCx->JSQR;
+  /* Get JL value: Number = JL+1 */
+  tmpreg3 =  (tmpreg1 & JSQR_JL_SET)>> 20;
+  /* Calculate the mask to clear: ((Rank-1)+(4-JL-1)) */
+  tmpreg2 = JSQR_JSQ_SET << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+  /* Clear the old JSQx bits for the selected rank */
+  tmpreg1 &= ~tmpreg2;
+  /* Calculate the mask to set: ((Rank-1)+(4-JL-1)) */
+  tmpreg2 = (uint32_t)ADC_Channel << (5 * (uint8_t)((Rank + 3) - (tmpreg3 + 1)));
+  /* Set the JSQx bits for the selected rank */
+  tmpreg1 |= tmpreg2;
+  /* Store the new register value */
+  ADCx->JSQR = tmpreg1;
+}
+
+/**
+  * @brief  Configures the sequencer length for injected channels
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  Length: The sequencer length. 
+  *          This parameter must be a number between 1 to 4.
+  * @retval None
+  */
+void ADC_InjectedSequencerLengthConfig(ADC_TypeDef* ADCx, uint8_t Length)
+{
+  uint32_t tmpreg1 = 0;
+  uint32_t tmpreg2 = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_LENGTH(Length));
+  
+  /* Get the old register value */
+  tmpreg1 = ADCx->JSQR;
+  
+  /* Clear the old injected sequence length JL bits */
+  tmpreg1 &= JSQR_JL_RESET;
+  
+  /* Set the injected sequence length JL bits */
+  tmpreg2 = Length - 1; 
+  tmpreg1 |= tmpreg2 << 20;
+  
+  /* Store the new register value */
+  ADCx->JSQR = tmpreg1;
+}
+
+/**
+  * @brief  Set the injected channels conversion value offset
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_InjectedChannel: the ADC injected channel to set its offset. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_InjectedChannel_1: Injected Channel1 selected
+  *            @arg ADC_InjectedChannel_2: Injected Channel2 selected
+  *            @arg ADC_InjectedChannel_3: Injected Channel3 selected
+  *            @arg ADC_InjectedChannel_4: Injected Channel4 selected
+  * @param  Offset: the offset value for the selected ADC injected channel
+  *          This parameter must be a 12bit value.
+  * @retval None
+  */
+void ADC_SetInjectedOffset(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel, uint16_t Offset)
+{
+    __IO uint32_t tmp = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+  assert_param(IS_ADC_OFFSET(Offset));
+  
+  tmp = (uint32_t)ADCx;
+  tmp += ADC_InjectedChannel;
+  
+  /* Set the selected injected channel data offset */
+ *(__IO uint32_t *) tmp = (uint32_t)Offset;
+}
+
+ /**
+  * @brief  Configures the ADCx external trigger for injected channels conversion.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_ExternalTrigInjecConv: specifies the ADC trigger to start injected conversion.
+  *          This parameter can be one of the following values:                    
+  *            @arg ADC_ExternalTrigInjecConv_T1_CC4: Timer1 capture compare4 selected 
+  *            @arg ADC_ExternalTrigInjecConv_T1_TRGO: Timer1 TRGO event selected 
+  *            @arg ADC_ExternalTrigInjecConv_T2_CC1: Timer2 capture compare1 selected 
+  *            @arg ADC_ExternalTrigInjecConv_T2_TRGO: Timer2 TRGO event selected 
+  *            @arg ADC_ExternalTrigInjecConv_T3_CC2: Timer3 capture compare2 selected 
+  *            @arg ADC_ExternalTrigInjecConv_T3_CC4: Timer3 capture compare4 selected 
+  *            @arg ADC_ExternalTrigInjecConv_T4_CC1: Timer4 capture compare1 selected                       
+  *            @arg ADC_ExternalTrigInjecConv_T4_CC2: Timer4 capture compare2 selected 
+  *            @arg ADC_ExternalTrigInjecConv_T4_CC3: Timer4 capture compare3 selected                        
+  *            @arg ADC_ExternalTrigInjecConv_T4_TRGO: Timer4 TRGO event selected 
+  *            @arg ADC_ExternalTrigInjecConv_T5_CC4: Timer5 capture compare4 selected                        
+  *            @arg ADC_ExternalTrigInjecConv_T5_TRGO: Timer5 TRGO event selected                        
+  *            @arg ADC_ExternalTrigInjecConv_T8_CC2: Timer8 capture compare2 selected
+  *            @arg ADC_ExternalTrigInjecConv_T8_CC3: Timer8 capture compare3 selected                        
+  *            @arg ADC_ExternalTrigInjecConv_T8_CC4: Timer8 capture compare4 selected 
+  *            @arg ADC_ExternalTrigInjecConv_Ext_IT15: External interrupt line 15 event selected                          
+  * @retval None
+  */
+void ADC_ExternalTrigInjectedConvConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConv)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_EXT_INJEC_TRIG(ADC_ExternalTrigInjecConv));
+  
+  /* Get the old register value */
+  tmpreg = ADCx->CR2;
+  
+  /* Clear the old external event selection for injected group */
+  tmpreg &= CR2_JEXTSEL_RESET;
+  
+  /* Set the external event selection for injected group */
+  tmpreg |= ADC_ExternalTrigInjecConv;
+  
+  /* Store the new register value */
+  ADCx->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Configures the ADCx external trigger edge for injected channels conversion.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_ExternalTrigInjecConvEdge: specifies the ADC external trigger edge
+  *         to start injected conversion. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_ExternalTrigInjecConvEdge_None: external trigger disabled for 
+  *                                                     injected conversion
+  *            @arg ADC_ExternalTrigInjecConvEdge_Rising: detection on rising edge
+  *            @arg ADC_ExternalTrigInjecConvEdge_Falling: detection on falling edge
+  *            @arg ADC_ExternalTrigInjecConvEdge_RisingFalling: detection on both rising 
+  *                                                               and falling edge
+  * @retval None
+  */
+void ADC_ExternalTrigInjectedConvEdgeConfig(ADC_TypeDef* ADCx, uint32_t ADC_ExternalTrigInjecConvEdge)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_EXT_INJEC_TRIG_EDGE(ADC_ExternalTrigInjecConvEdge));
+  /* Get the old register value */
+  tmpreg = ADCx->CR2;
+  /* Clear the old external trigger edge for injected group */
+  tmpreg &= CR2_JEXTEN_RESET;
+  /* Set the new external trigger edge for injected group */
+  tmpreg |= ADC_ExternalTrigInjecConvEdge;
+  /* Store the new register value */
+  ADCx->CR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables the selected ADC software start conversion of the injected channels.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval None
+  */
+void ADC_SoftwareStartInjectedConv(ADC_TypeDef* ADCx)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  /* Enable the selected ADC conversion for injected group */
+  ADCx->CR2 |= (uint32_t)ADC_CR2_JSWSTART;
+}
+
+/**
+  * @brief  Gets the selected ADC Software start injected conversion Status.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @retval The new state of ADC software start injected conversion (SET or RESET).
+  */
+FlagStatus ADC_GetSoftwareStartInjectedConvCmdStatus(ADC_TypeDef* ADCx)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  
+  /* Check the status of JSWSTART bit */
+  if ((ADCx->CR2 & ADC_CR2_JSWSTART) != (uint32_t)RESET)
+  {
+    /* JSWSTART bit is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* JSWSTART bit is reset */
+    bitstatus = RESET;
+  }
+  /* Return the JSWSTART bit status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Enables or disables the selected ADC automatic injected group 
+  *         conversion after regular one.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC auto injected conversion
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_AutoInjectedConvCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC automatic injected group conversion */
+    ADCx->CR1 |= (uint32_t)ADC_CR1_JAUTO;
+  }
+  else
+  {
+    /* Disable the selected ADC automatic injected group conversion */
+    ADCx->CR1 &= (uint32_t)(~ADC_CR1_JAUTO);
+  }
+}
+
+/**
+  * @brief  Enables or disables the discontinuous mode for injected group 
+  *         channel for the specified ADC
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  NewState: new state of the selected ADC discontinuous mode on injected
+  *         group channel.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_InjectedDiscModeCmd(ADC_TypeDef* ADCx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC injected discontinuous mode */
+    ADCx->CR1 |= (uint32_t)ADC_CR1_JDISCEN;
+  }
+  else
+  {
+    /* Disable the selected ADC injected discontinuous mode */
+    ADCx->CR1 &= (uint32_t)(~ADC_CR1_JDISCEN);
+  }
+}
+
+/**
+  * @brief  Returns the ADC injected channel conversion result
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_InjectedChannel: the converted ADC injected channel.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_InjectedChannel_1: Injected Channel1 selected
+  *            @arg ADC_InjectedChannel_2: Injected Channel2 selected
+  *            @arg ADC_InjectedChannel_3: Injected Channel3 selected
+  *            @arg ADC_InjectedChannel_4: Injected Channel4 selected
+  * @retval The Data conversion value.
+  */
+uint16_t ADC_GetInjectedConversionValue(ADC_TypeDef* ADCx, uint8_t ADC_InjectedChannel)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_INJECTED_CHANNEL(ADC_InjectedChannel));
+
+  tmp = (uint32_t)ADCx;
+  tmp += ADC_InjectedChannel + JDR_OFFSET;
+  
+  /* Returns the selected injected channel conversion data value */
+  return (uint16_t) (*(__IO uint32_t*)  tmp); 
+}
+/**
+  * @}
+  */
+
+/** @defgroup ADC_Group7 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+                   Interrupts and flags management functions
+ ===============================================================================  
+
+  This section provides functions allowing to configure the ADC Interrupts and 
+  to get the status and clear flags and Interrupts pending bits.
+  
+  Each ADC provides 4 Interrupts sources and 6 Flags which can be divided into 
+  3 groups:
+  
+  I. Flags and Interrupts for ADC regular channels
+  =================================================
+  Flags :
+  ---------- 
+     1. ADC_FLAG_OVR : Overrun detection when regular converted data are lost
+
+     2. ADC_FLAG_EOC : Regular channel end of conversion ==> to indicate (depending 
+              on EOCS bit, managed by ADC_EOCOnEachRegularChannelCmd() ) the end of:
+               ==> a regular CHANNEL conversion 
+               ==> sequence of regular GROUP conversions .
+
+     3. ADC_FLAG_STRT: Regular channel start ==> to indicate when regular CHANNEL 
+              conversion starts.
+
+  Interrupts :
+  ------------
+     1. ADC_IT_OVR : specifies the interrupt source for Overrun detection event.  
+     2. ADC_IT_EOC : specifies the interrupt source for Regular channel end of 
+                     conversion event.
+  
+  
+  II. Flags and Interrupts for ADC Injected channels
+  =================================================
+  Flags :
+  ---------- 
+     1. ADC_FLAG_JEOC : Injected channel end of conversion ==> to indicate at 
+               the end of injected GROUP conversion  
+              
+     2. ADC_FLAG_JSTRT: Injected channel start ==> to indicate hardware when 
+               injected GROUP conversion starts.
+
+  Interrupts :
+  ------------
+     1. ADC_IT_JEOC : specifies the interrupt source for Injected channel end of 
+                      conversion event.     
+
+  III. General Flags and Interrupts for the ADC
+  ================================================= 
+  Flags :
+  ---------- 
+     1. ADC_FLAG_AWD: Analog watchdog ==> to indicate if the converted voltage 
+              crosses the programmed thresholds values.
+              
+  Interrupts :
+  ------------
+     1. ADC_IT_AWD : specifies the interrupt source for Analog watchdog event. 
+
+  
+  The user should identify which mode will be used in his application to manage 
+  the ADC controller events: Polling mode or Interrupt mode.
+  
+  In the Polling Mode it is advised to use the following functions:
+      - ADC_GetFlagStatus() : to check if flags events occur. 
+      - ADC_ClearFlag()     : to clear the flags events.
+      
+  In the Interrupt Mode it is advised to use the following functions:
+     - ADC_ITConfig()          : to enable or disable the interrupt source.
+     - ADC_GetITStatus()       : to check if Interrupt occurs.
+     - ADC_ClearITPendingBit() : to clear the Interrupt pending Bit 
+                                 (corresponding Flag). 
+@endverbatim
+  * @{
+  */ 
+/**
+  * @brief  Enables or disables the specified ADC interrupts.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt sources to be enabled or disabled. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_IT_EOC: End of conversion interrupt mask
+  *            @arg ADC_IT_AWD: Analog watchdog interrupt mask
+  *            @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+  *            @arg ADC_IT_OVR: Overrun interrupt enable                       
+  * @param  NewState: new state of the specified ADC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void ADC_ITConfig(ADC_TypeDef* ADCx, uint16_t ADC_IT, FunctionalState NewState)  
+{
+  uint32_t itmask = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_ADC_IT(ADC_IT)); 
+
+  /* Get the ADC IT index */
+  itmask = (uint8_t)ADC_IT;
+  itmask = (uint32_t)0x01 << itmask;    
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected ADC interrupts */
+    ADCx->CR1 |= itmask;
+  }
+  else
+  {
+    /* Disable the selected ADC interrupts */
+    ADCx->CR1 &= (~(uint32_t)itmask);
+  }
+}
+
+/**
+  * @brief  Checks whether the specified ADC flag is set or not.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_FLAG: specifies the flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_FLAG_AWD: Analog watchdog flag
+  *            @arg ADC_FLAG_EOC: End of conversion flag
+  *            @arg ADC_FLAG_JEOC: End of injected group conversion flag
+  *            @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
+  *            @arg ADC_FLAG_STRT: Start of regular group conversion flag
+  *            @arg ADC_FLAG_OVR: Overrun flag                                                 
+  * @retval The new state of ADC_FLAG (SET or RESET).
+  */
+FlagStatus ADC_GetFlagStatus(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_GET_FLAG(ADC_FLAG));
+
+  /* Check the status of the specified ADC flag */
+  if ((ADCx->SR & ADC_FLAG) != (uint8_t)RESET)
+  {
+    /* ADC_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* ADC_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the ADC_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the ADCx's pending flags.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_FLAG: specifies the flag to clear. 
+  *          This parameter can be any combination of the following values:
+  *            @arg ADC_FLAG_AWD: Analog watchdog flag
+  *            @arg ADC_FLAG_EOC: End of conversion flag
+  *            @arg ADC_FLAG_JEOC: End of injected group conversion flag
+  *            @arg ADC_FLAG_JSTRT: Start of injected group conversion flag
+  *            @arg ADC_FLAG_STRT: Start of regular group conversion flag
+  *            @arg ADC_FLAG_OVR: Overrun flag                          
+  * @retval None
+  */
+void ADC_ClearFlag(ADC_TypeDef* ADCx, uint8_t ADC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_CLEAR_FLAG(ADC_FLAG));
+
+  /* Clear the selected ADC flags */
+  ADCx->SR = ~(uint32_t)ADC_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified ADC interrupt has occurred or not.
+  * @param  ADCx:   where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg ADC_IT_EOC: End of conversion interrupt mask
+  *            @arg ADC_IT_AWD: Analog watchdog interrupt mask
+  *            @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+  *            @arg ADC_IT_OVR: Overrun interrupt mask                        
+  * @retval The new state of ADC_IT (SET or RESET).
+  */
+ITStatus ADC_GetITStatus(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t itmask = 0, enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_IT(ADC_IT));
+
+  /* Get the ADC IT index */
+  itmask = ADC_IT >> 8;
+
+  /* Get the ADC_IT enable bit status */
+  enablestatus = (ADCx->CR1 & ((uint32_t)0x01 << (uint8_t)ADC_IT)) ;
+
+  /* Check the status of the specified ADC interrupt */
+  if (((ADCx->SR & itmask) != (uint32_t)RESET) && enablestatus)
+  {
+    /* ADC_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* ADC_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the ADC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the ADCx's interrupt pending bits.
+  * @param  ADCx: where x can be 1, 2 or 3 to select the ADC peripheral.
+  * @param  ADC_IT: specifies the ADC interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg ADC_IT_EOC: End of conversion interrupt mask
+  *            @arg ADC_IT_AWD: Analog watchdog interrupt mask
+  *            @arg ADC_IT_JEOC: End of injected conversion interrupt mask
+  *            @arg ADC_IT_OVR: Overrun interrupt mask                         
+  * @retval None
+  */
+void ADC_ClearITPendingBit(ADC_TypeDef* ADCx, uint16_t ADC_IT)
+{
+  uint8_t itmask = 0;
+  /* Check the parameters */
+  assert_param(IS_ADC_ALL_PERIPH(ADCx));
+  assert_param(IS_ADC_IT(ADC_IT)); 
+  /* Get the ADC IT index */
+  itmask = (uint8_t)(ADC_IT >> 8);
+  /* Clear the selected ADC interrupt pending bits */
+  ADCx->SR = ~(uint32_t)itmask;
+}                    
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c
new file mode 100644
index 0000000000..2661c6645b
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_can.c
@@ -0,0 +1,1698 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_can.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Controller area network (CAN) peripheral:           
+  *           - Initialization and Configuration 
+  *           - CAN Frames Transmission 
+  *           - CAN Frames Reception    
+  *           - Operation modes switch  
+  *           - Error management          
+  *           - Interrupts and flags        
+  *         
+  *  @verbatim
+  *                               
+  *          ===================================================================      
+  *                                   How to use this driver
+  *          ===================================================================
+                
+  *          1.  Enable the CAN controller interface clock using 
+  *                  RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN1, ENABLE); for CAN1 
+  *              and RCC_APB1PeriphClockCmd(RCC_APB1Periph_CAN2, ENABLE); for CAN2
+  *  @note   In case you are using CAN2 only, you have to enable the CAN1 clock.
+  *     
+  *          2. CAN pins configuration
+  *               - Enable the clock for the CAN GPIOs using the following function:
+  *                   RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);   
+  *               - Connect the involved CAN pins to AF9 using the following function 
+  *                   GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_CANx); 
+  *                - Configure these CAN pins in alternate function mode by calling
+  *                  the function  GPIO_Init();
+  *    
+  *          3.  Initialise and configure the CAN using CAN_Init() and 
+  *               CAN_FilterInit() functions.   
+  *               
+  *          4.  Transmit the desired CAN frame using CAN_Transmit() function.
+  *         
+  *          5.  Check the transmission of a CAN frame using CAN_TransmitStatus()
+  *              function.
+  *               
+  *          6.  Cancel the transmission of a CAN frame using CAN_CancelTransmit()
+  *              function.  
+  *            
+  *          7.  Receive a CAN frame using CAN_Recieve() function.
+  *         
+  *          8.  Release the receive FIFOs using CAN_FIFORelease() function.
+  *               
+  *          9. Return the number of pending received frames using 
+  *              CAN_MessagePending() function.            
+  *                   
+  *          10. To control CAN events you can use one of the following two methods:
+  *               - Check on CAN flags using the CAN_GetFlagStatus() function.  
+  *               - Use CAN interrupts through the function CAN_ITConfig() at 
+  *                 initialization phase and CAN_GetITStatus() function into 
+  *                 interrupt routines to check if the event has occurred or not.
+  *             After checking on a flag you should clear it using CAN_ClearFlag()
+  *             function. And after checking on an interrupt event you should 
+  *             clear it using CAN_ClearITPendingBit() function.            
+  *               
+  *              
+  *  @endverbatim
+  *         
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************  
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_can.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CAN 
+  * @brief CAN driver modules
+  * @{
+  */ 
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* CAN Master Control Register bits */
+#define MCR_DBF           ((uint32_t)0x00010000) /* software master reset */
+
+/* CAN Mailbox Transmit Request */
+#define TMIDxR_TXRQ       ((uint32_t)0x00000001) /* Transmit mailbox request */
+
+/* CAN Filter Master Register bits */
+#define FMR_FINIT         ((uint32_t)0x00000001) /* Filter init mode */
+
+/* Time out for INAK bit */
+#define INAK_TIMEOUT      ((uint32_t)0x0000FFFF)
+/* Time out for SLAK bit */
+#define SLAK_TIMEOUT      ((uint32_t)0x0000FFFF)
+
+/* Flags in TSR register */
+#define CAN_FLAGS_TSR     ((uint32_t)0x08000000) 
+/* Flags in RF1R register */
+#define CAN_FLAGS_RF1R    ((uint32_t)0x04000000) 
+/* Flags in RF0R register */
+#define CAN_FLAGS_RF0R    ((uint32_t)0x02000000) 
+/* Flags in MSR register */
+#define CAN_FLAGS_MSR     ((uint32_t)0x01000000) 
+/* Flags in ESR register */
+#define CAN_FLAGS_ESR     ((uint32_t)0x00F00000) 
+
+/* Mailboxes definition */
+#define CAN_TXMAILBOX_0   ((uint8_t)0x00)
+#define CAN_TXMAILBOX_1   ((uint8_t)0x01)
+#define CAN_TXMAILBOX_2   ((uint8_t)0x02) 
+
+#define CAN_MODE_MASK     ((uint32_t) 0x00000003)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit);
+
+/** @defgroup CAN_Private_Functions
+  * @{
+  */
+
+/** @defgroup CAN_Group1 Initialization and Configuration functions
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+                      Initialization and Configuration functions
+ ===============================================================================  
+  This section provides functions allowing to 
+   - Initialize the CAN peripherals : Prescaler, operating mode, the maximum number 
+     of time quanta to perform resynchronization, the number of time quanta in
+     Bit Segment 1 and 2 and many other modes. 
+     Refer to  @ref CAN_InitTypeDef  for more details.
+   - Configures the CAN reception filter.                                      
+   - Select the start bank filter for slave CAN.
+   - Enables or disables the Debug Freeze mode for CAN
+   - Enables or disables the CAN Time Trigger Operation communication mode
+   
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Deinitializes the CAN peripheral registers to their default reset values.
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
+  * @retval None.
+  */
+void CAN_DeInit(CAN_TypeDef* CANx)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+ 
+  if (CANx == CAN1)
+  {
+    /* Enable CAN1 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, ENABLE);
+    /* Release CAN1 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN1, DISABLE);
+  }
+  else
+  {  
+    /* Enable CAN2 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, ENABLE);
+    /* Release CAN2 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_CAN2, DISABLE);
+  }
+}
+
+/**
+  * @brief  Initializes the CAN peripheral according to the specified
+  *         parameters in the CAN_InitStruct.
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
+  * @param  CAN_InitStruct: pointer to a CAN_InitTypeDef structure that contains
+  *         the configuration information for the CAN peripheral.
+  * @retval Constant indicates initialization succeed which will be 
+  *         CAN_InitStatus_Failed or CAN_InitStatus_Success.
+  */
+uint8_t CAN_Init(CAN_TypeDef* CANx, CAN_InitTypeDef* CAN_InitStruct)
+{
+  uint8_t InitStatus = CAN_InitStatus_Failed;
+  uint32_t wait_ack = 0x00000000;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TTCM));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_ABOM));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_AWUM));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_NART));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_RFLM));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_InitStruct->CAN_TXFP));
+  assert_param(IS_CAN_MODE(CAN_InitStruct->CAN_Mode));
+  assert_param(IS_CAN_SJW(CAN_InitStruct->CAN_SJW));
+  assert_param(IS_CAN_BS1(CAN_InitStruct->CAN_BS1));
+  assert_param(IS_CAN_BS2(CAN_InitStruct->CAN_BS2));
+  assert_param(IS_CAN_PRESCALER(CAN_InitStruct->CAN_Prescaler));
+
+  /* Exit from sleep mode */
+  CANx->MCR &= (~(uint32_t)CAN_MCR_SLEEP);
+
+  /* Request initialisation */
+  CANx->MCR |= CAN_MCR_INRQ ;
+
+  /* Wait the acknowledge */
+  while (((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
+  {
+    wait_ack++;
+  }
+
+  /* Check acknowledge */
+  if ((CANx->MSR & CAN_MSR_INAK) != CAN_MSR_INAK)
+  {
+    InitStatus = CAN_InitStatus_Failed;
+  }
+  else 
+  {
+    /* Set the time triggered communication mode */
+    if (CAN_InitStruct->CAN_TTCM == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_TTCM;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_TTCM;
+    }
+
+    /* Set the automatic bus-off management */
+    if (CAN_InitStruct->CAN_ABOM == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_ABOM;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_ABOM;
+    }
+
+    /* Set the automatic wake-up mode */
+    if (CAN_InitStruct->CAN_AWUM == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_AWUM;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_AWUM;
+    }
+
+    /* Set the no automatic retransmission */
+    if (CAN_InitStruct->CAN_NART == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_NART;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_NART;
+    }
+
+    /* Set the receive FIFO locked mode */
+    if (CAN_InitStruct->CAN_RFLM == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_RFLM;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_RFLM;
+    }
+
+    /* Set the transmit FIFO priority */
+    if (CAN_InitStruct->CAN_TXFP == ENABLE)
+    {
+      CANx->MCR |= CAN_MCR_TXFP;
+    }
+    else
+    {
+      CANx->MCR &= ~(uint32_t)CAN_MCR_TXFP;
+    }
+
+    /* Set the bit timing register */
+    CANx->BTR = (uint32_t)((uint32_t)CAN_InitStruct->CAN_Mode << 30) | \
+                ((uint32_t)CAN_InitStruct->CAN_SJW << 24) | \
+                ((uint32_t)CAN_InitStruct->CAN_BS1 << 16) | \
+                ((uint32_t)CAN_InitStruct->CAN_BS2 << 20) | \
+               ((uint32_t)CAN_InitStruct->CAN_Prescaler - 1);
+
+    /* Request leave initialisation */
+    CANx->MCR &= ~(uint32_t)CAN_MCR_INRQ;
+
+   /* Wait the acknowledge */
+   wait_ack = 0;
+
+   while (((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK) && (wait_ack != INAK_TIMEOUT))
+   {
+     wait_ack++;
+   }
+
+    /* ...and check acknowledged */
+    if ((CANx->MSR & CAN_MSR_INAK) == CAN_MSR_INAK)
+    {
+      InitStatus = CAN_InitStatus_Failed;
+    }
+    else
+    {
+      InitStatus = CAN_InitStatus_Success ;
+    }
+  }
+
+  /* At this step, return the status of initialization */
+  return InitStatus;
+}
+
+/**
+  * @brief  Configures the CAN reception filter according to the specified
+  *         parameters in the CAN_FilterInitStruct.
+  * @param  CAN_FilterInitStruct: pointer to a CAN_FilterInitTypeDef structure that
+  *         contains the configuration information.
+  * @retval None
+  */
+void CAN_FilterInit(CAN_FilterInitTypeDef* CAN_FilterInitStruct)
+{
+  uint32_t filter_number_bit_pos = 0;
+  /* Check the parameters */
+  assert_param(IS_CAN_FILTER_NUMBER(CAN_FilterInitStruct->CAN_FilterNumber));
+  assert_param(IS_CAN_FILTER_MODE(CAN_FilterInitStruct->CAN_FilterMode));
+  assert_param(IS_CAN_FILTER_SCALE(CAN_FilterInitStruct->CAN_FilterScale));
+  assert_param(IS_CAN_FILTER_FIFO(CAN_FilterInitStruct->CAN_FilterFIFOAssignment));
+  assert_param(IS_FUNCTIONAL_STATE(CAN_FilterInitStruct->CAN_FilterActivation));
+
+  filter_number_bit_pos = ((uint32_t)1) << CAN_FilterInitStruct->CAN_FilterNumber;
+
+  /* Initialisation mode for the filter */
+  CAN1->FMR |= FMR_FINIT;
+
+  /* Filter Deactivation */
+  CAN1->FA1R &= ~(uint32_t)filter_number_bit_pos;
+
+  /* Filter Scale */
+  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_16bit)
+  {
+    /* 16-bit scale for the filter */
+    CAN1->FS1R &= ~(uint32_t)filter_number_bit_pos;
+
+    /* First 16-bit identifier and First 16-bit mask */
+    /* Or First 16-bit identifier and Second 16-bit identifier */
+    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = 
+       ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow) << 16) |
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+
+    /* Second 16-bit identifier and Second 16-bit mask */
+    /* Or Third 16-bit identifier and Fourth 16-bit identifier */
+    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = 
+       ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh);
+  }
+
+  if (CAN_FilterInitStruct->CAN_FilterScale == CAN_FilterScale_32bit)
+  {
+    /* 32-bit scale for the filter */
+    CAN1->FS1R |= filter_number_bit_pos;
+    /* 32-bit identifier or First 32-bit identifier */
+    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR1 = 
+       ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterIdLow);
+    /* 32-bit mask or Second 32-bit identifier */
+    CAN1->sFilterRegister[CAN_FilterInitStruct->CAN_FilterNumber].FR2 = 
+       ((0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdHigh) << 16) |
+        (0x0000FFFF & (uint32_t)CAN_FilterInitStruct->CAN_FilterMaskIdLow);
+  }
+
+  /* Filter Mode */
+  if (CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdMask)
+  {
+    /*Id/Mask mode for the filter*/
+    CAN1->FM1R &= ~(uint32_t)filter_number_bit_pos;
+  }
+  else /* CAN_FilterInitStruct->CAN_FilterMode == CAN_FilterMode_IdList */
+  {
+    /*Identifier list mode for the filter*/
+    CAN1->FM1R |= (uint32_t)filter_number_bit_pos;
+  }
+
+  /* Filter FIFO assignment */
+  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO0)
+  {
+    /* FIFO 0 assignation for the filter */
+    CAN1->FFA1R &= ~(uint32_t)filter_number_bit_pos;
+  }
+
+  if (CAN_FilterInitStruct->CAN_FilterFIFOAssignment == CAN_Filter_FIFO1)
+  {
+    /* FIFO 1 assignation for the filter */
+    CAN1->FFA1R |= (uint32_t)filter_number_bit_pos;
+  }
+  
+  /* Filter activation */
+  if (CAN_FilterInitStruct->CAN_FilterActivation == ENABLE)
+  {
+    CAN1->FA1R |= filter_number_bit_pos;
+  }
+
+  /* Leave the initialisation mode for the filter */
+  CAN1->FMR &= ~FMR_FINIT;
+}
+
+/**
+  * @brief  Fills each CAN_InitStruct member with its default value.
+  * @param  CAN_InitStruct: pointer to a CAN_InitTypeDef structure which ill be initialized.
+  * @retval None
+  */
+void CAN_StructInit(CAN_InitTypeDef* CAN_InitStruct)
+{
+  /* Reset CAN init structure parameters values */
+  
+  /* Initialize the time triggered communication mode */
+  CAN_InitStruct->CAN_TTCM = DISABLE;
+  
+  /* Initialize the automatic bus-off management */
+  CAN_InitStruct->CAN_ABOM = DISABLE;
+  
+  /* Initialize the automatic wake-up mode */
+  CAN_InitStruct->CAN_AWUM = DISABLE;
+  
+  /* Initialize the no automatic retransmission */
+  CAN_InitStruct->CAN_NART = DISABLE;
+  
+  /* Initialize the receive FIFO locked mode */
+  CAN_InitStruct->CAN_RFLM = DISABLE;
+  
+  /* Initialize the transmit FIFO priority */
+  CAN_InitStruct->CAN_TXFP = DISABLE;
+  
+  /* Initialize the CAN_Mode member */
+  CAN_InitStruct->CAN_Mode = CAN_Mode_Normal;
+  
+  /* Initialize the CAN_SJW member */
+  CAN_InitStruct->CAN_SJW = CAN_SJW_1tq;
+  
+  /* Initialize the CAN_BS1 member */
+  CAN_InitStruct->CAN_BS1 = CAN_BS1_4tq;
+  
+  /* Initialize the CAN_BS2 member */
+  CAN_InitStruct->CAN_BS2 = CAN_BS2_3tq;
+  
+  /* Initialize the CAN_Prescaler member */
+  CAN_InitStruct->CAN_Prescaler = 1;
+}
+
+/**
+  * @brief  Select the start bank filter for slave CAN.
+  * @param  CAN_BankNumber: Select the start slave bank filter from 1..27.
+  * @retval None
+  */
+void CAN_SlaveStartBank(uint8_t CAN_BankNumber) 
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_BANKNUMBER(CAN_BankNumber));
+  
+  /* Enter Initialisation mode for the filter */
+  CAN1->FMR |= FMR_FINIT;
+  
+  /* Select the start slave bank */
+  CAN1->FMR &= (uint32_t)0xFFFFC0F1 ;
+  CAN1->FMR |= (uint32_t)(CAN_BankNumber)<<8;
+  
+  /* Leave Initialisation mode for the filter */
+  CAN1->FMR &= ~FMR_FINIT;
+}
+
+/**
+  * @brief  Enables or disables the DBG Freeze for CAN.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  NewState: new state of the CAN peripheral. 
+  *          This parameter can be: ENABLE (CAN reception/transmission is frozen
+  *          during debug. Reception FIFOs can still be accessed/controlled normally) 
+  *          or DISABLE (CAN is working during debug).
+  * @retval None
+  */
+void CAN_DBGFreeze(CAN_TypeDef* CANx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable Debug Freeze  */
+    CANx->MCR |= MCR_DBF;
+  }
+  else
+  {
+    /* Disable Debug Freeze */
+    CANx->MCR &= ~MCR_DBF;
+  }
+}
+
+
+/**
+  * @brief  Enables or disables the CAN Time TriggerOperation communication mode.
+  * @note   DLC must be programmed as 8 in order Time Stamp (2 bytes) to be 
+  *         sent over the CAN bus.  
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  NewState: Mode new state. This parameter can be: ENABLE or DISABLE.
+  *         When enabled, Time stamp (TIME[15:0]) value is  sent in the last two
+  *         data bytes of the 8-byte message: TIME[7:0] in data byte 6 and TIME[15:8] 
+  *         in data byte 7. 
+  * @retval None
+  */
+void CAN_TTComModeCmd(CAN_TypeDef* CANx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the TTCM mode */
+    CANx->MCR |= CAN_MCR_TTCM;
+
+    /* Set TGT bits */
+    CANx->sTxMailBox[0].TDTR |= ((uint32_t)CAN_TDT0R_TGT);
+    CANx->sTxMailBox[1].TDTR |= ((uint32_t)CAN_TDT1R_TGT);
+    CANx->sTxMailBox[2].TDTR |= ((uint32_t)CAN_TDT2R_TGT);
+  }
+  else
+  {
+    /* Disable the TTCM mode */
+    CANx->MCR &= (uint32_t)(~(uint32_t)CAN_MCR_TTCM);
+
+    /* Reset TGT bits */
+    CANx->sTxMailBox[0].TDTR &= ((uint32_t)~CAN_TDT0R_TGT);
+    CANx->sTxMailBox[1].TDTR &= ((uint32_t)~CAN_TDT1R_TGT);
+    CANx->sTxMailBox[2].TDTR &= ((uint32_t)~CAN_TDT2R_TGT);
+  }
+}
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_Group2 CAN Frames Transmission functions
+ *  @brief    CAN Frames Transmission functions 
+ *
+@verbatim    
+ ===============================================================================
+                      CAN Frames Transmission functions
+ ===============================================================================  
+  This section provides functions allowing to 
+   - Initiate and transmit a CAN frame message (if there is an empty mailbox).
+   - Check the transmission status of a CAN Frame
+   - Cancel a transmit request
+   
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initiates and transmits a CAN frame message.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  TxMessage: pointer to a structure which contains CAN Id, CAN DLC and CAN data.
+  * @retval The number of the mailbox that is used for transmission or
+  *         CAN_TxStatus_NoMailBox if there is no empty mailbox.
+  */
+uint8_t CAN_Transmit(CAN_TypeDef* CANx, CanTxMsg* TxMessage)
+{
+  uint8_t transmit_mailbox = 0;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_IDTYPE(TxMessage->IDE));
+  assert_param(IS_CAN_RTR(TxMessage->RTR));
+  assert_param(IS_CAN_DLC(TxMessage->DLC));
+
+  /* Select one empty transmit mailbox */
+  if ((CANx->TSR&CAN_TSR_TME0) == CAN_TSR_TME0)
+  {
+    transmit_mailbox = 0;
+  }
+  else if ((CANx->TSR&CAN_TSR_TME1) == CAN_TSR_TME1)
+  {
+    transmit_mailbox = 1;
+  }
+  else if ((CANx->TSR&CAN_TSR_TME2) == CAN_TSR_TME2)
+  {
+    transmit_mailbox = 2;
+  }
+  else
+  {
+    transmit_mailbox = CAN_TxStatus_NoMailBox;
+  }
+
+  if (transmit_mailbox != CAN_TxStatus_NoMailBox)
+  {
+    /* Set up the Id */
+    CANx->sTxMailBox[transmit_mailbox].TIR &= TMIDxR_TXRQ;
+    if (TxMessage->IDE == CAN_Id_Standard)
+    {
+      assert_param(IS_CAN_STDID(TxMessage->StdId));  
+      CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->StdId << 21) | \
+                                                  TxMessage->RTR);
+    }
+    else
+    {
+      assert_param(IS_CAN_EXTID(TxMessage->ExtId));
+      CANx->sTxMailBox[transmit_mailbox].TIR |= ((TxMessage->ExtId << 3) | \
+                                                  TxMessage->IDE | \
+                                                  TxMessage->RTR);
+    }
+    
+    /* Set up the DLC */
+    TxMessage->DLC &= (uint8_t)0x0000000F;
+    CANx->sTxMailBox[transmit_mailbox].TDTR &= (uint32_t)0xFFFFFFF0;
+    CANx->sTxMailBox[transmit_mailbox].TDTR |= TxMessage->DLC;
+
+    /* Set up the data field */
+    CANx->sTxMailBox[transmit_mailbox].TDLR = (((uint32_t)TxMessage->Data[3] << 24) | 
+                                             ((uint32_t)TxMessage->Data[2] << 16) |
+                                             ((uint32_t)TxMessage->Data[1] << 8) | 
+                                             ((uint32_t)TxMessage->Data[0]));
+    CANx->sTxMailBox[transmit_mailbox].TDHR = (((uint32_t)TxMessage->Data[7] << 24) | 
+                                             ((uint32_t)TxMessage->Data[6] << 16) |
+                                             ((uint32_t)TxMessage->Data[5] << 8) |
+                                             ((uint32_t)TxMessage->Data[4]));
+    /* Request transmission */
+    CANx->sTxMailBox[transmit_mailbox].TIR |= TMIDxR_TXRQ;
+  }
+  return transmit_mailbox;
+}
+
+/**
+  * @brief  Checks the transmission status of a CAN Frame.
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
+  * @param  TransmitMailbox: the number of the mailbox that is used for transmission.
+  * @retval CAN_TxStatus_Ok if the CAN driver transmits the message, 
+  *         CAN_TxStatus_Failed in an other case.
+  */
+uint8_t CAN_TransmitStatus(CAN_TypeDef* CANx, uint8_t TransmitMailbox)
+{
+  uint32_t state = 0;
+
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_TRANSMITMAILBOX(TransmitMailbox));
+ 
+  switch (TransmitMailbox)
+  {
+    case (CAN_TXMAILBOX_0): 
+      state =   CANx->TSR &  (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0);
+      break;
+    case (CAN_TXMAILBOX_1): 
+      state =   CANx->TSR &  (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1);
+      break;
+    case (CAN_TXMAILBOX_2): 
+      state =   CANx->TSR &  (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2);
+      break;
+    default:
+      state = CAN_TxStatus_Failed;
+      break;
+  }
+  switch (state)
+  {
+      /* transmit pending  */
+    case (0x0): state = CAN_TxStatus_Pending;
+      break;
+      /* transmit failed  */
+     case (CAN_TSR_RQCP0 | CAN_TSR_TME0): state = CAN_TxStatus_Failed;
+      break;
+     case (CAN_TSR_RQCP1 | CAN_TSR_TME1): state = CAN_TxStatus_Failed;
+      break;
+     case (CAN_TSR_RQCP2 | CAN_TSR_TME2): state = CAN_TxStatus_Failed;
+      break;
+      /* transmit succeeded  */
+    case (CAN_TSR_RQCP0 | CAN_TSR_TXOK0 | CAN_TSR_TME0):state = CAN_TxStatus_Ok;
+      break;
+    case (CAN_TSR_RQCP1 | CAN_TSR_TXOK1 | CAN_TSR_TME1):state = CAN_TxStatus_Ok;
+      break;
+    case (CAN_TSR_RQCP2 | CAN_TSR_TXOK2 | CAN_TSR_TME2):state = CAN_TxStatus_Ok;
+      break;
+    default: state = CAN_TxStatus_Failed;
+      break;
+  }
+  return (uint8_t) state;
+}
+
+/**
+  * @brief  Cancels a transmit request.
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
+  * @param  Mailbox: Mailbox number.
+  * @retval None
+  */
+void CAN_CancelTransmit(CAN_TypeDef* CANx, uint8_t Mailbox)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_TRANSMITMAILBOX(Mailbox));
+  /* abort transmission */
+  switch (Mailbox)
+  {
+    case (CAN_TXMAILBOX_0): CANx->TSR |= CAN_TSR_ABRQ0;
+      break;
+    case (CAN_TXMAILBOX_1): CANx->TSR |= CAN_TSR_ABRQ1;
+      break;
+    case (CAN_TXMAILBOX_2): CANx->TSR |= CAN_TSR_ABRQ2;
+      break;
+    default:
+      break;
+  }
+}
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_Group3 CAN Frames Reception functions
+ *  @brief    CAN Frames Reception functions 
+ *
+@verbatim    
+ ===============================================================================
+                      CAN Frames Reception functions
+ ===============================================================================  
+  This section provides functions allowing to 
+   -  Receive a correct CAN frame
+   -  Release a specified receive FIFO (2 FIFOs are available)
+   -  Return the number of the pending received CAN frames
+   
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Receives a correct CAN frame.
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
+  * @param  FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+  * @param  RxMessage: pointer to a structure receive frame which contains CAN Id,
+  *         CAN DLC, CAN data and FMI number.
+  * @retval None
+  */
+void CAN_Receive(CAN_TypeDef* CANx, uint8_t FIFONumber, CanRxMsg* RxMessage)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_FIFO(FIFONumber));
+  /* Get the Id */
+  RxMessage->IDE = (uint8_t)0x04 & CANx->sFIFOMailBox[FIFONumber].RIR;
+  if (RxMessage->IDE == CAN_Id_Standard)
+  {
+    RxMessage->StdId = (uint32_t)0x000007FF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 21);
+  }
+  else
+  {
+    RxMessage->ExtId = (uint32_t)0x1FFFFFFF & (CANx->sFIFOMailBox[FIFONumber].RIR >> 3);
+  }
+  
+  RxMessage->RTR = (uint8_t)0x02 & CANx->sFIFOMailBox[FIFONumber].RIR;
+  /* Get the DLC */
+  RxMessage->DLC = (uint8_t)0x0F & CANx->sFIFOMailBox[FIFONumber].RDTR;
+  /* Get the FMI */
+  RxMessage->FMI = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDTR >> 8);
+  /* Get the data field */
+  RxMessage->Data[0] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDLR;
+  RxMessage->Data[1] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 8);
+  RxMessage->Data[2] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 16);
+  RxMessage->Data[3] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDLR >> 24);
+  RxMessage->Data[4] = (uint8_t)0xFF & CANx->sFIFOMailBox[FIFONumber].RDHR;
+  RxMessage->Data[5] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 8);
+  RxMessage->Data[6] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 16);
+  RxMessage->Data[7] = (uint8_t)0xFF & (CANx->sFIFOMailBox[FIFONumber].RDHR >> 24);
+  /* Release the FIFO */
+  /* Release FIFO0 */
+  if (FIFONumber == CAN_FIFO0)
+  {
+    CANx->RF0R |= CAN_RF0R_RFOM0;
+  }
+  /* Release FIFO1 */
+  else /* FIFONumber == CAN_FIFO1 */
+  {
+    CANx->RF1R |= CAN_RF1R_RFOM1;
+  }
+}
+
+/**
+  * @brief  Releases the specified receive FIFO.
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
+  * @param  FIFONumber: FIFO to release, CAN_FIFO0 or CAN_FIFO1.
+  * @retval None
+  */
+void CAN_FIFORelease(CAN_TypeDef* CANx, uint8_t FIFONumber)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_FIFO(FIFONumber));
+  /* Release FIFO0 */
+  if (FIFONumber == CAN_FIFO0)
+  {
+    CANx->RF0R |= CAN_RF0R_RFOM0;
+  }
+  /* Release FIFO1 */
+  else /* FIFONumber == CAN_FIFO1 */
+  {
+    CANx->RF1R |= CAN_RF1R_RFOM1;
+  }
+}
+
+/**
+  * @brief  Returns the number of pending received messages.
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
+  * @param  FIFONumber: Receive FIFO number, CAN_FIFO0 or CAN_FIFO1.
+  * @retval NbMessage : which is the number of pending message.
+  */
+uint8_t CAN_MessagePending(CAN_TypeDef* CANx, uint8_t FIFONumber)
+{
+  uint8_t message_pending=0;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_FIFO(FIFONumber));
+  if (FIFONumber == CAN_FIFO0)
+  {
+    message_pending = (uint8_t)(CANx->RF0R&(uint32_t)0x03);
+  }
+  else if (FIFONumber == CAN_FIFO1)
+  {
+    message_pending = (uint8_t)(CANx->RF1R&(uint32_t)0x03);
+  }
+  else
+  {
+    message_pending = 0;
+  }
+  return message_pending;
+}
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_Group4 CAN Operation modes functions
+ *  @brief    CAN Operation modes functions 
+ *
+@verbatim    
+ ===============================================================================
+                      CAN Operation modes functions
+ ===============================================================================  
+  This section provides functions allowing to select the CAN Operation modes
+  - sleep mode
+  - normal mode 
+  - initialization mode
+   
+@endverbatim
+  * @{
+  */
+  
+  
+/**
+  * @brief  Selects the CAN Operation mode.
+  * @param  CAN_OperatingMode: CAN Operating Mode.
+  *         This parameter can be one of @ref CAN_OperatingMode_TypeDef enumeration.
+  * @retval status of the requested mode which can be 
+  *         - CAN_ModeStatus_Failed:  CAN failed entering the specific mode 
+  *         - CAN_ModeStatus_Success: CAN Succeed entering the specific mode 
+  */
+uint8_t CAN_OperatingModeRequest(CAN_TypeDef* CANx, uint8_t CAN_OperatingMode)
+{
+  uint8_t status = CAN_ModeStatus_Failed;
+  
+  /* Timeout for INAK or also for SLAK bits*/
+  uint32_t timeout = INAK_TIMEOUT; 
+
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_OPERATING_MODE(CAN_OperatingMode));
+
+  if (CAN_OperatingMode == CAN_OperatingMode_Initialization)
+  {
+    /* Request initialisation */
+    CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_SLEEP)) | CAN_MCR_INRQ);
+
+    /* Wait the acknowledge */
+    while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK) && (timeout != 0))
+    {
+      timeout--;
+    }
+    if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_INAK)
+    {
+      status = CAN_ModeStatus_Failed;
+    }
+    else
+    {
+      status = CAN_ModeStatus_Success;
+    }
+  }
+  else  if (CAN_OperatingMode == CAN_OperatingMode_Normal)
+  {
+    /* Request leave initialisation and sleep mode  and enter Normal mode */
+    CANx->MCR &= (uint32_t)(~(CAN_MCR_SLEEP|CAN_MCR_INRQ));
+
+    /* Wait the acknowledge */
+    while (((CANx->MSR & CAN_MODE_MASK) != 0) && (timeout!=0))
+    {
+      timeout--;
+    }
+    if ((CANx->MSR & CAN_MODE_MASK) != 0)
+    {
+      status = CAN_ModeStatus_Failed;
+    }
+    else
+    {
+      status = CAN_ModeStatus_Success;
+    }
+  }
+  else  if (CAN_OperatingMode == CAN_OperatingMode_Sleep)
+  {
+    /* Request Sleep mode */
+    CANx->MCR = (uint32_t)((CANx->MCR & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+
+    /* Wait the acknowledge */
+    while (((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK) && (timeout!=0))
+    {
+      timeout--;
+    }
+    if ((CANx->MSR & CAN_MODE_MASK) != CAN_MSR_SLAK)
+    {
+      status = CAN_ModeStatus_Failed;
+    }
+    else
+    {
+      status = CAN_ModeStatus_Success;
+    }
+  }
+  else
+  {
+    status = CAN_ModeStatus_Failed;
+  }
+
+  return  (uint8_t) status;
+}
+
+/**
+  * @brief  Enters the Sleep (low power) mode.
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
+  * @retval CAN_Sleep_Ok if sleep entered, CAN_Sleep_Failed otherwise.
+  */
+uint8_t CAN_Sleep(CAN_TypeDef* CANx)
+{
+  uint8_t sleepstatus = CAN_Sleep_Failed;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+    
+  /* Request Sleep mode */
+   CANx->MCR = (((CANx->MCR) & (uint32_t)(~(uint32_t)CAN_MCR_INRQ)) | CAN_MCR_SLEEP);
+   
+  /* Sleep mode status */
+  if ((CANx->MSR & (CAN_MSR_SLAK|CAN_MSR_INAK)) == CAN_MSR_SLAK)
+  {
+    /* Sleep mode not entered */
+    sleepstatus =  CAN_Sleep_Ok;
+  }
+  /* return sleep mode status */
+   return (uint8_t)sleepstatus;
+}
+
+/**
+  * @brief  Wakes up the CAN peripheral from sleep mode .
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
+  * @retval CAN_WakeUp_Ok if sleep mode left, CAN_WakeUp_Failed otherwise.
+  */
+uint8_t CAN_WakeUp(CAN_TypeDef* CANx)
+{
+  uint32_t wait_slak = SLAK_TIMEOUT;
+  uint8_t wakeupstatus = CAN_WakeUp_Failed;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+    
+  /* Wake up request */
+  CANx->MCR &= ~(uint32_t)CAN_MCR_SLEEP;
+    
+  /* Sleep mode status */
+  while(((CANx->MSR & CAN_MSR_SLAK) == CAN_MSR_SLAK)&&(wait_slak!=0x00))
+  {
+   wait_slak--;
+  }
+  if((CANx->MSR & CAN_MSR_SLAK) != CAN_MSR_SLAK)
+  {
+   /* wake up done : Sleep mode exited */
+    wakeupstatus = CAN_WakeUp_Ok;
+  }
+  /* return wakeup status */
+  return (uint8_t)wakeupstatus;
+}
+/**
+  * @}
+  */
+
+
+/** @defgroup CAN_Group5 CAN Bus Error management functions
+ *  @brief    CAN Bus Error management functions 
+ *
+@verbatim    
+ ===============================================================================
+                      CAN Bus Error management functions
+ ===============================================================================  
+  This section provides functions allowing to 
+   -  Return the CANx's last error code (LEC)
+   -  Return the CANx Receive Error Counter (REC)
+   -  Return the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+   
+   @note If TEC is greater than 255, The CAN is in bus-off state.
+   @note if REC or TEC are greater than 96, an Error warning flag occurs.
+   @note if REC or TEC are greater than 127, an Error Passive Flag occurs.
+                        
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Returns the CANx's last error code (LEC).
+  * @param  CANx: where x can be 1 or 2 to select the CAN peripheral.
+  * @retval Error code: 
+  *          - CAN_ERRORCODE_NoErr: No Error  
+  *          - CAN_ERRORCODE_StuffErr: Stuff Error
+  *          - CAN_ERRORCODE_FormErr: Form Error
+  *          - CAN_ERRORCODE_ACKErr : Acknowledgment Error
+  *          - CAN_ERRORCODE_BitRecessiveErr: Bit Recessive Error
+  *          - CAN_ERRORCODE_BitDominantErr: Bit Dominant Error
+  *          - CAN_ERRORCODE_CRCErr: CRC Error
+  *          - CAN_ERRORCODE_SoftwareSetErr: Software Set Error  
+  */
+uint8_t CAN_GetLastErrorCode(CAN_TypeDef* CANx)
+{
+  uint8_t errorcode=0;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  
+  /* Get the error code*/
+  errorcode = (((uint8_t)CANx->ESR) & (uint8_t)CAN_ESR_LEC);
+  
+  /* Return the error code*/
+  return errorcode;
+}
+
+/**
+  * @brief  Returns the CANx Receive Error Counter (REC).
+  * @note   In case of an error during reception, this counter is incremented 
+  *         by 1 or by 8 depending on the error condition as defined by the CAN 
+  *         standard. After every successful reception, the counter is 
+  *         decremented by 1 or reset to 120 if its value was higher than 128. 
+  *         When the counter value exceeds 127, the CAN controller enters the 
+  *         error passive state.  
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.  
+  * @retval CAN Receive Error Counter. 
+  */
+uint8_t CAN_GetReceiveErrorCounter(CAN_TypeDef* CANx)
+{
+  uint8_t counter=0;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  
+  /* Get the Receive Error Counter*/
+  counter = (uint8_t)((CANx->ESR & CAN_ESR_REC)>> 24);
+  
+  /* Return the Receive Error Counter*/
+  return counter;
+}
+
+
+/**
+  * @brief  Returns the LSB of the 9-bit CANx Transmit Error Counter(TEC).
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @retval LSB of the 9-bit CAN Transmit Error Counter. 
+  */
+uint8_t CAN_GetLSBTransmitErrorCounter(CAN_TypeDef* CANx)
+{
+  uint8_t counter=0;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  
+  /* Get the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+  counter = (uint8_t)((CANx->ESR & CAN_ESR_TEC)>> 16);
+  
+  /* Return the LSB of the 9-bit CANx Transmit Error Counter(TEC) */
+  return counter;
+}
+/**
+  * @}
+  */
+
+/** @defgroup CAN_Group6 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+                   Interrupts and flags management functions
+ ===============================================================================  
+
+  This section provides functions allowing to configure the CAN Interrupts and 
+  to get the status and clear flags and Interrupts pending bits.
+  
+  The CAN provides 14 Interrupts sources and 15 Flags:
+
+  ===============  
+      Flags :
+  ===============
+  The 15 flags can be divided on 4 groups: 
+
+   A. Transmit Flags
+  -----------------------
+        CAN_FLAG_RQCP0, 
+        CAN_FLAG_RQCP1, 
+        CAN_FLAG_RQCP2  : Request completed MailBoxes 0, 1 and 2  Flags
+                          Set when when the last request (transmit or abort) has 
+                          been performed. 
+
+  B. Receive Flags
+  -----------------------
+
+        CAN_FLAG_FMP0,
+        CAN_FLAG_FMP1   : FIFO 0 and 1 Message Pending Flags 
+                          set to signal that messages are pending in the receive 
+                          FIFO.
+                          These Flags are cleared only by hardware. 
+
+        CAN_FLAG_FF0,
+        CAN_FLAG_FF1    : FIFO 0 and 1 Full Flags
+                          set when three messages are stored in the selected 
+                          FIFO.                        
+
+        CAN_FLAG_FOV0              
+        CAN_FLAG_FOV1   : FIFO 0 and 1 Overrun Flags
+                          set when a new message has been received and passed 
+                          the filter while the FIFO was full.         
+
+  C. Operating Mode Flags
+  ----------------------- 
+        CAN_FLAG_WKU    : Wake up Flag
+                          set to signal that a SOF bit has been detected while 
+                          the CAN hardware was in Sleep mode. 
+        
+        CAN_FLAG_SLAK   : Sleep acknowledge Flag
+                          Set to signal that the CAN has entered Sleep Mode. 
+    
+  D. Error Flags
+  ----------------------- 
+        CAN_FLAG_EWG    : Error Warning Flag
+                          Set when the warning limit has been reached (Receive 
+                          Error Counter or Transmit Error Counter greater than 96). 
+                          This Flag is cleared only by hardware.
+                            
+        CAN_FLAG_EPV    : Error Passive Flag
+                          Set when the Error Passive limit has been reached 
+                          (Receive Error Counter or Transmit Error Counter 
+                          greater than 127).
+                          This Flag is cleared only by hardware.
+                             
+        CAN_FLAG_BOF    : Bus-Off Flag
+                          set when CAN enters the bus-off state. The bus-off 
+                          state is entered on TEC overflow, greater than 255.
+                          This Flag is cleared only by hardware.
+                                   
+        CAN_FLAG_LEC    : Last error code Flag
+                          set If a message has been transferred (reception or
+                          transmission) with error, and the error code is hold.              
+                          
+  ===============  
+   Interrupts :
+  ===============
+  The 14 interrupts can be divided on 4 groups: 
+  
+   A. Transmit interrupt
+  -----------------------   
+          CAN_IT_TME   :  Transmit mailbox empty Interrupt
+                          if enabled, this interrupt source is pending when 
+                          no transmit request are pending for Tx mailboxes.      
+
+   B. Receive Interrupts
+  -----------------------          
+        CAN_IT_FMP0,
+        CAN_IT_FMP1    :  FIFO 0 and FIFO1 message pending Interrupts
+                          if enabled, these interrupt sources are pending when 
+                          messages are pending in the receive FIFO.
+                          The corresponding interrupt pending bits are cleared 
+                          only by hardware.
+                
+        CAN_IT_FF0,              
+        CAN_IT_FF1     :  FIFO 0 and FIFO1 full Interrupts
+                          if enabled, these interrupt sources are pending when
+                          three messages are stored in the selected FIFO.
+        
+        CAN_IT_FOV0,        
+        CAN_IT_FOV1    :  FIFO 0 and FIFO1 overrun Interrupts        
+                          if enabled, these interrupt sources are pending when
+                          a new message has been received and passed the filter
+                          while the FIFO was full.
+
+   C. Operating Mode Interrupts
+  -------------------------------          
+        CAN_IT_WKU     :  Wake-up Interrupt
+                          if enabled, this interrupt source is pending when 
+                          a SOF bit has been detected while the CAN hardware was 
+                          in Sleep mode.
+                                  
+        CAN_IT_SLK     :  Sleep acknowledge Interrupt
+                          if enabled, this interrupt source is pending when 
+                          the CAN has entered Sleep Mode.       
+
+   D. Error Interrupts 
+  -----------------------         
+        CAN_IT_EWG     :  Error warning Interrupt 
+                          if enabled, this interrupt source is pending when
+                          the warning limit has been reached (Receive Error 
+                          Counter or Transmit Error Counter=96). 
+                               
+        CAN_IT_EPV     :  Error passive Interrupt        
+                          if enabled, this interrupt source is pending when
+                          the Error Passive limit has been reached (Receive 
+                          Error Counter or Transmit Error Counter>127).
+                          
+        CAN_IT_BOF     :  Bus-off Interrupt
+                          if enabled, this interrupt source is pending when
+                          CAN enters the bus-off state. The bus-off state is 
+                          entered on TEC overflow, greater than 255.
+                          This Flag is cleared only by hardware.
+                                  
+        CAN_IT_LEC     :  Last error code Interrupt        
+                          if enabled, this interrupt source is pending  when
+                          a message has been transferred (reception or
+                          transmission) with error, and the error code is hold.
+                          
+        CAN_IT_ERR     :  Error Interrupt
+                          if enabled, this interrupt source is pending when 
+                          an error condition is pending.      
+                      
+
+  Managing the CAN controller events :
+  ------------------------------------ 
+  The user should identify which mode will be used in his application to manage 
+  the CAN controller events: Polling mode or Interrupt mode.
+  
+  1.  In the Polling Mode it is advised to use the following functions:
+      - CAN_GetFlagStatus() : to check if flags events occur. 
+      - CAN_ClearFlag()     : to clear the flags events.
+  
+
+  
+  2.  In the Interrupt Mode it is advised to use the following functions:
+      - CAN_ITConfig()       : to enable or disable the interrupt source.
+      - CAN_GetITStatus()    : to check if Interrupt occurs.
+      - CAN_ClearITPendingBit() : to clear the Interrupt pending Bit (corresponding Flag).
+      @note  This function has no impact on CAN_IT_FMP0 and CAN_IT_FMP1 Interrupts 
+             pending bits since there are cleared only by hardware. 
+  
+@endverbatim
+  * @{
+  */ 
+/**
+  * @brief  Enables or disables the specified CANx interrupts.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  CAN_IT: specifies the CAN interrupt sources to be enabled or disabled.
+  *          This parameter can be: 
+  *            @arg CAN_IT_TME: Transmit mailbox empty Interrupt 
+  *            @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt 
+  *            @arg CAN_IT_FF0: FIFO 0 full Interrupt
+  *            @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
+  *            @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt 
+  *            @arg CAN_IT_FF1: FIFO 1 full Interrupt
+  *            @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
+  *            @arg CAN_IT_WKU: Wake-up Interrupt
+  *            @arg CAN_IT_SLK: Sleep acknowledge Interrupt  
+  *            @arg CAN_IT_EWG: Error warning Interrupt
+  *            @arg CAN_IT_EPV: Error passive Interrupt
+  *            @arg CAN_IT_BOF: Bus-off Interrupt  
+  *            @arg CAN_IT_LEC: Last error code Interrupt
+  *            @arg CAN_IT_ERR: Error Interrupt
+  * @param  NewState: new state of the CAN interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CAN_ITConfig(CAN_TypeDef* CANx, uint32_t CAN_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_IT(CAN_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected CANx interrupt */
+    CANx->IER |= CAN_IT;
+  }
+  else
+  {
+    /* Disable the selected CANx interrupt */
+    CANx->IER &= ~CAN_IT;
+  }
+}
+/**
+  * @brief  Checks whether the specified CAN flag is set or not.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  CAN_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
+  *            @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
+  *            @arg CAN_FLAG_RQCP2: Request MailBox2 Flag
+  *            @arg CAN_FLAG_FMP0: FIFO 0 Message Pending Flag   
+  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag       
+  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag 
+  *            @arg CAN_FLAG_FMP1: FIFO 1 Message Pending Flag   
+  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag        
+  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag     
+  *            @arg CAN_FLAG_WKU: Wake up Flag
+  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag 
+  *            @arg CAN_FLAG_EWG: Error Warning Flag
+  *            @arg CAN_FLAG_EPV: Error Passive Flag  
+  *            @arg CAN_FLAG_BOF: Bus-Off Flag    
+  *            @arg CAN_FLAG_LEC: Last error code Flag      
+  * @retval The new state of CAN_FLAG (SET or RESET).
+  */
+FlagStatus CAN_GetFlagStatus(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_GET_FLAG(CAN_FLAG));
+  
+
+  if((CAN_FLAG & CAN_FLAGS_ESR) != (uint32_t)RESET)
+  { 
+    /* Check the status of the specified CAN flag */
+    if ((CANx->ESR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    { 
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  else if((CAN_FLAG & CAN_FLAGS_MSR) != (uint32_t)RESET)
+  { 
+    /* Check the status of the specified CAN flag */
+    if ((CANx->MSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    { 
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  else if((CAN_FLAG & CAN_FLAGS_TSR) != (uint32_t)RESET)
+  { 
+    /* Check the status of the specified CAN flag */
+    if ((CANx->TSR & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    { 
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  else if((CAN_FLAG & CAN_FLAGS_RF0R) != (uint32_t)RESET)
+  { 
+    /* Check the status of the specified CAN flag */
+    if ((CANx->RF0R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    { 
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  else /* If(CAN_FLAG & CAN_FLAGS_RF1R != (uint32_t)RESET) */
+  { 
+    /* Check the status of the specified CAN flag */
+    if ((uint32_t)(CANx->RF1R & (CAN_FLAG & 0x000FFFFF)) != (uint32_t)RESET)
+    { 
+      /* CAN_FLAG is set */
+      bitstatus = SET;
+    }
+    else
+    { 
+      /* CAN_FLAG is reset */
+      bitstatus = RESET;
+    }
+  }
+  /* Return the CAN_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the CAN's pending flags.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  CAN_FLAG: specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg CAN_FLAG_RQCP0: Request MailBox0 Flag
+  *            @arg CAN_FLAG_RQCP1: Request MailBox1 Flag
+  *            @arg CAN_FLAG_RQCP2: Request MailBox2 Flag 
+  *            @arg CAN_FLAG_FF0: FIFO 0 Full Flag       
+  *            @arg CAN_FLAG_FOV0: FIFO 0 Overrun Flag  
+  *            @arg CAN_FLAG_FF1: FIFO 1 Full Flag        
+  *            @arg CAN_FLAG_FOV1: FIFO 1 Overrun Flag     
+  *            @arg CAN_FLAG_WKU: Wake up Flag
+  *            @arg CAN_FLAG_SLAK: Sleep acknowledge Flag    
+  *            @arg CAN_FLAG_LEC: Last error code Flag        
+  * @retval None
+  */
+void CAN_ClearFlag(CAN_TypeDef* CANx, uint32_t CAN_FLAG)
+{
+  uint32_t flagtmp=0;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_CLEAR_FLAG(CAN_FLAG));
+  
+  if (CAN_FLAG == CAN_FLAG_LEC) /* ESR register */
+  {
+    /* Clear the selected CAN flags */
+    CANx->ESR = (uint32_t)RESET;
+  }
+  else /* MSR or TSR or RF0R or RF1R */
+  {
+    flagtmp = CAN_FLAG & 0x000FFFFF;
+
+    if ((CAN_FLAG & CAN_FLAGS_RF0R)!=(uint32_t)RESET)
+    {
+      /* Receive Flags */
+      CANx->RF0R = (uint32_t)(flagtmp);
+    }
+    else if ((CAN_FLAG & CAN_FLAGS_RF1R)!=(uint32_t)RESET)
+    {
+      /* Receive Flags */
+      CANx->RF1R = (uint32_t)(flagtmp);
+    }
+    else if ((CAN_FLAG & CAN_FLAGS_TSR)!=(uint32_t)RESET)
+    {
+      /* Transmit Flags */
+      CANx->TSR = (uint32_t)(flagtmp);
+    }
+    else /* If((CAN_FLAG & CAN_FLAGS_MSR)!=(uint32_t)RESET) */
+    {
+      /* Operating mode Flags */
+      CANx->MSR = (uint32_t)(flagtmp);
+    }
+  }
+}
+
+/**
+  * @brief  Checks whether the specified CANx interrupt has occurred or not.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  CAN_IT: specifies the CAN interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg CAN_IT_TME: Transmit mailbox empty Interrupt 
+  *            @arg CAN_IT_FMP0: FIFO 0 message pending Interrupt 
+  *            @arg CAN_IT_FF0: FIFO 0 full Interrupt
+  *            @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
+  *            @arg CAN_IT_FMP1: FIFO 1 message pending Interrupt 
+  *            @arg CAN_IT_FF1: FIFO 1 full Interrupt
+  *            @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
+  *            @arg CAN_IT_WKU: Wake-up Interrupt
+  *            @arg CAN_IT_SLK: Sleep acknowledge Interrupt  
+  *            @arg CAN_IT_EWG: Error warning Interrupt
+  *            @arg CAN_IT_EPV: Error passive Interrupt
+  *            @arg CAN_IT_BOF: Bus-off Interrupt  
+  *            @arg CAN_IT_LEC: Last error code Interrupt
+  *            @arg CAN_IT_ERR: Error Interrupt
+  * @retval The current state of CAN_IT (SET or RESET).
+  */
+ITStatus CAN_GetITStatus(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+  ITStatus itstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_IT(CAN_IT));
+  
+  /* check the interrupt enable bit */
+ if((CANx->IER & CAN_IT) != RESET)
+ {
+   /* in case the Interrupt is enabled, .... */
+    switch (CAN_IT)
+    {
+      case CAN_IT_TME:
+        /* Check CAN_TSR_RQCPx bits */
+        itstatus = CheckITStatus(CANx->TSR, CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2);  
+        break;
+      case CAN_IT_FMP0:
+        /* Check CAN_RF0R_FMP0 bit */
+        itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FMP0);  
+        break;
+      case CAN_IT_FF0:
+        /* Check CAN_RF0R_FULL0 bit */
+        itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FULL0);  
+        break;
+      case CAN_IT_FOV0:
+        /* Check CAN_RF0R_FOVR0 bit */
+        itstatus = CheckITStatus(CANx->RF0R, CAN_RF0R_FOVR0);  
+        break;
+      case CAN_IT_FMP1:
+        /* Check CAN_RF1R_FMP1 bit */
+        itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FMP1);  
+        break;
+      case CAN_IT_FF1:
+        /* Check CAN_RF1R_FULL1 bit */
+        itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FULL1);  
+        break;
+      case CAN_IT_FOV1:
+        /* Check CAN_RF1R_FOVR1 bit */
+        itstatus = CheckITStatus(CANx->RF1R, CAN_RF1R_FOVR1);  
+        break;
+      case CAN_IT_WKU:
+        /* Check CAN_MSR_WKUI bit */
+        itstatus = CheckITStatus(CANx->MSR, CAN_MSR_WKUI);  
+        break;
+      case CAN_IT_SLK:
+        /* Check CAN_MSR_SLAKI bit */
+        itstatus = CheckITStatus(CANx->MSR, CAN_MSR_SLAKI);  
+        break;
+      case CAN_IT_EWG:
+        /* Check CAN_ESR_EWGF bit */
+        itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EWGF);  
+        break;
+      case CAN_IT_EPV:
+        /* Check CAN_ESR_EPVF bit */
+        itstatus = CheckITStatus(CANx->ESR, CAN_ESR_EPVF);  
+        break;
+      case CAN_IT_BOF:
+        /* Check CAN_ESR_BOFF bit */
+        itstatus = CheckITStatus(CANx->ESR, CAN_ESR_BOFF);  
+        break;
+      case CAN_IT_LEC:
+        /* Check CAN_ESR_LEC bit */
+        itstatus = CheckITStatus(CANx->ESR, CAN_ESR_LEC);  
+        break;
+      case CAN_IT_ERR:
+        /* Check CAN_MSR_ERRI bit */ 
+        itstatus = CheckITStatus(CANx->MSR, CAN_MSR_ERRI); 
+        break;
+      default:
+        /* in case of error, return RESET */
+        itstatus = RESET;
+        break;
+    }
+  }
+  else
+  {
+   /* in case the Interrupt is not enabled, return RESET */
+    itstatus  = RESET;
+  }
+  
+  /* Return the CAN_IT status */
+  return  itstatus;
+}
+
+/**
+  * @brief  Clears the CANx's interrupt pending bits.
+  * @param  CANx: where x can be 1 or 2 to to select the CAN peripheral.
+  * @param  CAN_IT: specifies the interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg CAN_IT_TME: Transmit mailbox empty Interrupt
+  *            @arg CAN_IT_FF0: FIFO 0 full Interrupt
+  *            @arg CAN_IT_FOV0: FIFO 0 overrun Interrupt
+  *            @arg CAN_IT_FF1: FIFO 1 full Interrupt
+  *            @arg CAN_IT_FOV1: FIFO 1 overrun Interrupt
+  *            @arg CAN_IT_WKU: Wake-up Interrupt
+  *            @arg CAN_IT_SLK: Sleep acknowledge Interrupt  
+  *            @arg CAN_IT_EWG: Error warning Interrupt
+  *            @arg CAN_IT_EPV: Error passive Interrupt
+  *            @arg CAN_IT_BOF: Bus-off Interrupt  
+  *            @arg CAN_IT_LEC: Last error code Interrupt
+  *            @arg CAN_IT_ERR: Error Interrupt 
+  * @retval None
+  */
+void CAN_ClearITPendingBit(CAN_TypeDef* CANx, uint32_t CAN_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_CAN_ALL_PERIPH(CANx));
+  assert_param(IS_CAN_CLEAR_IT(CAN_IT));
+
+  switch (CAN_IT)
+  {
+    case CAN_IT_TME:
+      /* Clear CAN_TSR_RQCPx (rc_w1)*/
+      CANx->TSR = CAN_TSR_RQCP0|CAN_TSR_RQCP1|CAN_TSR_RQCP2;  
+      break;
+    case CAN_IT_FF0:
+      /* Clear CAN_RF0R_FULL0 (rc_w1)*/
+      CANx->RF0R = CAN_RF0R_FULL0; 
+      break;
+    case CAN_IT_FOV0:
+      /* Clear CAN_RF0R_FOVR0 (rc_w1)*/
+      CANx->RF0R = CAN_RF0R_FOVR0; 
+      break;
+    case CAN_IT_FF1:
+      /* Clear CAN_RF1R_FULL1 (rc_w1)*/
+      CANx->RF1R = CAN_RF1R_FULL1;  
+      break;
+    case CAN_IT_FOV1:
+      /* Clear CAN_RF1R_FOVR1 (rc_w1)*/
+      CANx->RF1R = CAN_RF1R_FOVR1; 
+      break;
+    case CAN_IT_WKU:
+      /* Clear CAN_MSR_WKUI (rc_w1)*/
+      CANx->MSR = CAN_MSR_WKUI;  
+      break;
+    case CAN_IT_SLK:
+      /* Clear CAN_MSR_SLAKI (rc_w1)*/ 
+      CANx->MSR = CAN_MSR_SLAKI;   
+      break;
+    case CAN_IT_EWG:
+      /* Clear CAN_MSR_ERRI (rc_w1) */
+      CANx->MSR = CAN_MSR_ERRI;
+       /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/ 
+      break;
+    case CAN_IT_EPV:
+      /* Clear CAN_MSR_ERRI (rc_w1) */
+      CANx->MSR = CAN_MSR_ERRI; 
+       /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
+      break;
+    case CAN_IT_BOF:
+      /* Clear CAN_MSR_ERRI (rc_w1) */ 
+      CANx->MSR = CAN_MSR_ERRI; 
+       /* @note the corresponding Flag is cleared by hardware depending on the CAN Bus status*/
+       break;
+    case CAN_IT_LEC:
+      /*  Clear LEC bits */
+      CANx->ESR = RESET; 
+      /* Clear CAN_MSR_ERRI (rc_w1) */
+      CANx->MSR = CAN_MSR_ERRI; 
+      break;
+    case CAN_IT_ERR:
+      /*Clear LEC bits */
+      CANx->ESR = RESET; 
+      /* Clear CAN_MSR_ERRI (rc_w1) */
+      CANx->MSR = CAN_MSR_ERRI; 
+       /* @note BOFF, EPVF and EWGF Flags are cleared by hardware depending on the CAN Bus status*/
+       break;
+    default:
+       break;
+   }
+}
+ /**
+  * @}
+  */
+
+/**
+  * @brief  Checks whether the CAN interrupt has occurred or not.
+  * @param  CAN_Reg: specifies the CAN interrupt register to check.
+  * @param  It_Bit: specifies the interrupt source bit to check.
+  * @retval The new state of the CAN Interrupt (SET or RESET).
+  */
+static ITStatus CheckITStatus(uint32_t CAN_Reg, uint32_t It_Bit)
+{
+  ITStatus pendingbitstatus = RESET;
+  
+  if ((CAN_Reg & It_Bit) != (uint32_t)RESET)
+  {
+    /* CAN_IT is set */
+    pendingbitstatus = SET;
+  }
+  else
+  {
+    /* CAN_IT is reset */
+    pendingbitstatus = RESET;
+  }
+  return pendingbitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c
new file mode 100644
index 0000000000..40058ae2cb
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_crc.c
@@ -0,0 +1,127 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_crc.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides all the CRC firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_crc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CRC 
+  * @brief CRC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CRC_Private_Functions
+  * @{
+  */
+
+/**
+  * @brief  Resets the CRC Data register (DR).
+  * @param  None
+  * @retval None
+  */
+void CRC_ResetDR(void)
+{
+  /* Reset CRC generator */
+  CRC->CR = CRC_CR_RESET;
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given data word(32-bit).
+  * @param  Data: data word(32-bit) to compute its CRC
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalcCRC(uint32_t Data)
+{
+  CRC->DR = Data;
+  
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Computes the 32-bit CRC of a given buffer of data word(32-bit).
+  * @param  pBuffer: pointer to the buffer containing the data to be computed
+  * @param  BufferLength: length of the buffer to be computed					
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_CalcBlockCRC(uint32_t pBuffer[], uint32_t BufferLength)
+{
+  uint32_t index = 0;
+  
+  for(index = 0; index < BufferLength; index++)
+  {
+    CRC->DR = pBuffer[index];
+  }
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Returns the current CRC value.
+  * @param  None
+  * @retval 32-bit CRC
+  */
+uint32_t CRC_GetCRC(void)
+{
+  return (CRC->DR);
+}
+
+/**
+  * @brief  Stores a 8-bit data in the Independent Data(ID) register.
+  * @param  IDValue: 8-bit value to be stored in the ID register 					
+  * @retval None
+  */
+void CRC_SetIDRegister(uint8_t IDValue)
+{
+  CRC->IDR = IDValue;
+}
+
+/**
+  * @brief  Returns the 8-bit data stored in the Independent Data(ID) register
+  * @param  None
+  * @retval 8-bit value of the ID register 
+  */
+uint8_t CRC_GetIDRegister(void)
+{
+  return (CRC->IDR);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c
new file mode 100644
index 0000000000..aa1002ad07
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp.c
@@ -0,0 +1,850 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_cryp.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the  Cryptographic processor (CRYP) peripheral:           
+  *           - Initialization and Configuration functions
+  *           - Data treatment functions 
+  *           - Context swapping functions     
+  *           - DMA interface function       
+  *           - Interrupts and flags management       
+  *
+  *  @verbatim
+  *                               
+  *          ===================================================================      
+  *                                 How to use this driver
+  *          =================================================================== 
+  *          1. Enable the CRYP controller clock using 
+  *              RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
+  *
+  *          2. Initialise the CRYP using CRYP_Init(), CRYP_KeyInit() and if 
+  *             needed CRYP_IVInit(). 
+  *
+  *          3. Flush the IN and OUT FIFOs by using CRYP_FIFOFlush() function.
+  *
+  *          4. Enable the CRYP controller using the CRYP_Cmd() function. 
+  *
+  *          5. If using DMA for Data input and output transfer, 
+  *             Activate the needed DMA Requests using CRYP_DMACmd() function 
+  
+  *          6. If DMA is not used for data transfer, use CRYP_DataIn() and 
+  *             CRYP_DataOut() functions to enter data to IN FIFO and get result
+  *             from OUT FIFO.
+  *
+  *          7. To control CRYP events you can use one of the following 
+  *              two methods:
+  *               - Check on CRYP flags using the CRYP_GetFlagStatus() function.  
+  *               - Use CRYP interrupts through the function CRYP_ITConfig() at 
+  *                 initialization phase and CRYP_GetITStatus() function into 
+  *                 interrupt routines in processing phase.
+  *       
+  *          8. Save and restore Cryptographic processor context using  
+  *             CRYP_SaveContext() and CRYP_RestoreContext() functions.     
+  *
+  *
+  *          ===================================================================  
+  *                Procedure to perform an encryption or a decryption
+  *          ===================================================================  
+  *
+  *      Initialization
+  *      ===============  
+  *     1. Initialize the peripheral using CRYP_Init(), CRYP_KeyInit() and 
+  *        CRYP_IVInit functions:
+  *        - Configure the key size (128-, 192- or 256-bit, in the AES only) 
+  *        - Enter the symmetric key 
+  *        - Configure the data type
+  *        - In case of decryption in AES-ECB or AES-CBC, you must prepare 
+  *          the key: configure the key preparation mode. Then Enable the CRYP 
+  *          peripheral using CRYP_Cmd() function: the BUSY flag is set. 
+  *          Wait until BUSY flag is reset : the key is prepared for decryption
+  *       - Configure the algorithm and chaining (the DES/TDES in ECB/CBC, the 
+  *          AES in ECB/CBC/CTR) 
+  *       - Configure the direction (encryption/decryption).
+  *       - Write the initialization vectors (in CBC or CTR modes only)
+  *
+  *    2. Flush the IN and OUT FIFOs using the CRYP_FIFOFlush() function
+  *
+  *
+  *    Basic Processing mode (polling mode) 
+  *    ====================================  
+  *    1. Enable the cryptographic processor using CRYP_Cmd() function.
+  *
+  *    2. Write the first blocks in the input FIFO (2 to 8 words) using 
+  *       CRYP_DataIn() function.
+  *
+  *    3. Repeat the following sequence until the complete message has been 
+  *       processed:
+  *
+  *       a) Wait for flag CRYP_FLAG_OFNE occurs (using CRYP_GetFlagStatus() 
+  *          function), then read the OUT-FIFO using CRYP_DataOut() function
+  *          (1 block or until the FIFO is empty)
+  *
+  *       b) Wait for flag CRYP_FLAG_IFNF occurs, (using CRYP_GetFlagStatus() 
+  *          function then write the IN FIFO using CRYP_DataIn() function 
+  *          (1 block or until the FIFO is full)
+  *
+  *    4. At the end of the processing, CRYP_FLAG_BUSY flag will be reset and 
+  *        both FIFOs are empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is 
+  *        reset). You can disable the peripheral using CRYP_Cmd() function.
+  *
+  *    Interrupts Processing mode 
+  *    ===========================
+  *    In this mode, Processing is done when the data are transferred by the 
+  *    CPU during interrupts.
+  *
+  *    1. Enable the interrupts CRYP_IT_INI and CRYP_IT_OUTI using 
+  *       CRYP_ITConfig() function.
+  *
+  *    2. Enable the cryptographic processor using CRYP_Cmd() function.
+  *
+  *    3. In the CRYP_IT_INI interrupt handler : load the input message into the 
+  *       IN FIFO using CRYP_DataIn() function . You can load 2 or 4 words at a 
+  *       time, or load data until the IN FIFO is full. When the last word of
+  *       the message has been entered into the IN FIFO, disable the CRYP_IT_INI 
+  *       interrupt (using CRYP_ITConfig() function).
+  *
+  *    4. In the CRYP_IT_OUTI interrupt handler : read the output message from 
+  *       the OUT FIFO using CRYP_DataOut() function. You can read 1 block (2 or 
+  *       4 words) at a time or read data until the FIFO is empty.
+  *       When the last word has been read, INIM=0, BUSY=0 and both FIFOs are 
+  *       empty (CRYP_FLAG_IFEM is set and CRYP_FLAG_OFNE is reset). 
+  *       You can disable the CRYP_IT_OUTI interrupt (using CRYP_ITConfig() 
+  *       function) and you can disable the peripheral using CRYP_Cmd() function.
+  *
+  *    DMA Processing mode 
+  *    ====================
+  *    In this mode, Processing is done when the DMA is used to transfer the 
+  *    data from/to the memory.
+  *
+  *    1. Configure the DMA controller to transfer the input data from the 
+  *       memory using DMA_Init() function. 
+  *       The transfer length is the length of the message. 
+  *       As message padding is not managed by the peripheral, the message 
+  *       length must be an entire number of blocks. The data are transferred 
+  *       in burst mode. The burst length is 4 words in the AES and 2 or 4 
+  *       words in the DES/TDES. The DMA should be configured to set an 
+  *       interrupt on transfer completion of the output data to indicate that 
+  *       the processing is finished. 
+  *       Refer to DMA peripheral driver for more details.  
+  *
+  *    2. Enable the cryptographic processor using CRYP_Cmd() function. 
+  *       Enable the DMA requests CRYP_DMAReq_DataIN and CRYP_DMAReq_DataOUT 
+  *       using CRYP_DMACmd() function.
+  *
+  *    3. All the transfers and processing are managed by the DMA and the 
+  *       cryptographic processor. The DMA transfer complete interrupt indicates 
+  *       that the processing is complete. Both FIFOs are normally empty and 
+  *       CRYP_FLAG_BUSY flag is reset.
+  *
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************  
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_cryp.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CRYP 
+  * @brief CRYP driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define FLAG_MASK     ((uint8_t)0x20)
+#define MAX_TIMEOUT   ((uint16_t)0xFFFF)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CRYP_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup CRYP_Group1 Initialization and Configuration functions
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+                      Initialization and Configuration functions
+ ===============================================================================  
+  This section provides functions allowing to 
+   - Initialize the cryptographic Processor using CRYP_Init() function 
+      -  Encrypt or Decrypt 
+      -  mode : TDES-ECB, TDES-CBC, 
+                DES-ECB, DES-CBC, 
+                AES-ECB, AES-CBC, AES-CTR, AES-Key 
+      - DataType :  32-bit data, 16-bit data, bit data or bit-string
+      - Key Size (only in AES modes)
+   - Configure the Encrypt or Decrypt Key using CRYP_KeyInit() function 
+   - Configure the Initialization Vectors(IV) for CBC and CTR modes using 
+     CRYP_IVInit() function.  
+   - Flushes the IN and OUT FIFOs : using CRYP_FIFOFlush() function.                         
+   - Enable or disable the CRYP Processor using CRYP_Cmd() function 
+    
+   
+@endverbatim
+  * @{
+  */
+/**
+  * @brief  Deinitializes the CRYP peripheral registers to their default reset values
+  * @param  None
+  * @retval None
+  */
+void CRYP_DeInit(void)
+{
+  /* Enable CRYP reset state */
+  RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, ENABLE);
+
+  /* Release CRYP from reset state */
+  RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_CRYP, DISABLE);
+}
+
+/**
+  * @brief  Initializes the CRYP peripheral according to the specified parameters
+  *         in the CRYP_InitStruct.
+  * @param  CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure that contains
+  *         the configuration information for the CRYP peripheral.
+  * @retval None
+  */
+void CRYP_Init(CRYP_InitTypeDef* CRYP_InitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_CRYP_ALGOMODE(CRYP_InitStruct->CRYP_AlgoMode));
+  assert_param(IS_CRYP_DATATYPE(CRYP_InitStruct->CRYP_DataType));
+  assert_param(IS_CRYP_ALGODIR(CRYP_InitStruct->CRYP_AlgoDir));
+
+  /* Select Algorithm mode*/  
+  CRYP->CR &= ~CRYP_CR_ALGOMODE;
+  CRYP->CR |= CRYP_InitStruct->CRYP_AlgoMode;
+
+  /* Select dataType */ 
+  CRYP->CR &= ~CRYP_CR_DATATYPE;
+  CRYP->CR |= CRYP_InitStruct->CRYP_DataType;
+
+  /* select Key size (used only with AES algorithm) */
+  if ((CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_ECB) ||
+      (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CBC) ||
+      (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_CTR) ||
+      (CRYP_InitStruct->CRYP_AlgoMode == CRYP_AlgoMode_AES_Key))
+  {
+    assert_param(IS_CRYP_KEYSIZE(CRYP_InitStruct->CRYP_KeySize));
+    CRYP->CR &= ~CRYP_CR_KEYSIZE;
+    CRYP->CR |= CRYP_InitStruct->CRYP_KeySize; /* Key size and value must be 
+                                                  configured once the key has 
+                                                  been prepared */
+  }
+
+  /* Select data Direction */ 
+  CRYP->CR &= ~CRYP_CR_ALGODIR;
+  CRYP->CR |= CRYP_InitStruct->CRYP_AlgoDir;
+}
+
+/**
+  * @brief  Fills each CRYP_InitStruct member with its default value.
+  * @param  CRYP_InitStruct: pointer to a CRYP_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void CRYP_StructInit(CRYP_InitTypeDef* CRYP_InitStruct)
+{
+  /* Initialize the CRYP_AlgoDir member */
+  CRYP_InitStruct->CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
+
+  /* initialize the CRYP_AlgoMode member */
+  CRYP_InitStruct->CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB;
+
+  /* initialize the CRYP_DataType member */
+  CRYP_InitStruct->CRYP_DataType = CRYP_DataType_32b;
+  
+  /* Initialize the CRYP_KeySize member */
+  CRYP_InitStruct->CRYP_KeySize = CRYP_KeySize_128b;
+}
+
+/**
+  * @brief  Initializes the CRYP Keys according to the specified parameters in
+  *         the CRYP_KeyInitStruct.
+  * @param  CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that
+  *         contains the configuration information for the CRYP Keys.
+  * @retval None
+  */
+void CRYP_KeyInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
+{
+  /* Key Initialisation */
+  CRYP->K0LR = CRYP_KeyInitStruct->CRYP_Key0Left;
+  CRYP->K0RR = CRYP_KeyInitStruct->CRYP_Key0Right;
+  CRYP->K1LR = CRYP_KeyInitStruct->CRYP_Key1Left;
+  CRYP->K1RR = CRYP_KeyInitStruct->CRYP_Key1Right;
+  CRYP->K2LR = CRYP_KeyInitStruct->CRYP_Key2Left;
+  CRYP->K2RR = CRYP_KeyInitStruct->CRYP_Key2Right;
+  CRYP->K3LR = CRYP_KeyInitStruct->CRYP_Key3Left;
+  CRYP->K3RR = CRYP_KeyInitStruct->CRYP_Key3Right;
+}
+
+/**
+  * @brief  Fills each CRYP_KeyInitStruct member with its default value.
+  * @param  CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure 
+  *         which will be initialized.
+  * @retval None
+  */
+void CRYP_KeyStructInit(CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
+{
+  CRYP_KeyInitStruct->CRYP_Key0Left  = 0;
+  CRYP_KeyInitStruct->CRYP_Key0Right = 0;
+  CRYP_KeyInitStruct->CRYP_Key1Left  = 0;
+  CRYP_KeyInitStruct->CRYP_Key1Right = 0;
+  CRYP_KeyInitStruct->CRYP_Key2Left  = 0;
+  CRYP_KeyInitStruct->CRYP_Key2Right = 0;
+  CRYP_KeyInitStruct->CRYP_Key3Left  = 0;
+  CRYP_KeyInitStruct->CRYP_Key3Right = 0;
+}
+/**
+  * @brief  Initializes the CRYP Initialization Vectors(IV) according to the
+  *         specified parameters in the CRYP_IVInitStruct.
+  * @param  CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef structure that contains
+  *         the configuration information for the CRYP Initialization Vectors(IV).
+  * @retval None
+  */
+void CRYP_IVInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct)
+{
+  CRYP->IV0LR = CRYP_IVInitStruct->CRYP_IV0Left;
+  CRYP->IV0RR = CRYP_IVInitStruct->CRYP_IV0Right;
+  CRYP->IV1LR = CRYP_IVInitStruct->CRYP_IV1Left;
+  CRYP->IV1RR = CRYP_IVInitStruct->CRYP_IV1Right;
+}
+
+/**
+  * @brief  Fills each CRYP_IVInitStruct member with its default value.
+  * @param  CRYP_IVInitStruct: pointer to a CRYP_IVInitTypeDef Initialization 
+  *         Vectors(IV) structure which will be initialized.
+  * @retval None
+  */
+void CRYP_IVStructInit(CRYP_IVInitTypeDef* CRYP_IVInitStruct)
+{
+  CRYP_IVInitStruct->CRYP_IV0Left  = 0;
+  CRYP_IVInitStruct->CRYP_IV0Right = 0;
+  CRYP_IVInitStruct->CRYP_IV1Left  = 0;
+  CRYP_IVInitStruct->CRYP_IV1Right = 0;
+}
+
+/**
+  * @brief  Flushes the IN and OUT FIFOs (that is read and write pointers of the 
+  *         FIFOs are reset)
+  * @note   The FIFOs must be flushed only when BUSY flag is reset.  
+  * @param  None
+  * @retval None
+  */
+void CRYP_FIFOFlush(void)
+{
+  /* Reset the read and write pointers of the FIFOs */
+  CRYP->CR |= CRYP_CR_FFLUSH;
+}
+
+/**
+  * @brief  Enables or disables the CRYP peripheral.
+  * @param  NewState: new state of the CRYP peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CRYP_Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Cryptographic processor */
+    CRYP->CR |= CRYP_CR_CRYPEN;
+  }
+  else
+  {
+    /* Disable the Cryptographic processor */
+    CRYP->CR &= ~CRYP_CR_CRYPEN;
+  }
+}
+/**
+  * @}
+  */
+  
+/** @defgroup CRYP_Group2 CRYP Data processing functions
+ *  @brief    CRYP Data processing functions
+ *
+@verbatim    
+ ===============================================================================
+                      CRYP Data processing functions
+ ===============================================================================  
+  This section provides functions allowing the encryption and decryption 
+  operations: 
+  - Enter data to be treated in the IN FIFO : using CRYP_DataIn() function.
+  - Get the data result from the OUT FIFO : using CRYP_DataOut() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Writes data in the Data Input register (DIN).
+  * @note   After the DIN register has been read once or several times, 
+  *         the FIFO must be flushed (using CRYP_FIFOFlush() function).  
+  * @param  Data: data to write in Data Input register
+  * @retval None
+  */
+void CRYP_DataIn(uint32_t Data)
+{
+  CRYP->DR = Data;
+}
+
+/**
+  * @brief  Returns the last data entered into the output FIFO.
+  * @param  None
+  * @retval Last data entered into the output FIFO.
+  */
+uint32_t CRYP_DataOut(void)
+{
+  return CRYP->DOUT;
+}
+/**
+  * @}
+  */
+  
+/** @defgroup CRYP_Group3 Context swapping functions
+ *  @brief   Context swapping functions
+ *
+@verbatim   
+ ===============================================================================
+                             Context swapping functions
+ ===============================================================================  
+
+  This section provides functions allowing to save and store CRYP Context
+
+  It is possible to interrupt an encryption/ decryption/ key generation process 
+  to perform another processing with a higher priority, and to complete the 
+  interrupted process later on, when the higher-priority task is complete. To do 
+  so, the context of the interrupted task must be saved from the CRYP registers 
+  to memory, and then be restored from memory to the CRYP registers.
+   
+  1. To save the current context, use CRYP_SaveContext() function
+  2. To restore the saved context, use CRYP_RestoreContext() function 
+
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Saves the CRYP peripheral Context. 
+  * @note   This function stops DMA transfer before to save the context. After 
+  *         restoring the context, you have to enable the DMA again (if the DMA
+  *         was previously used).
+  * @param  CRYP_ContextSave: pointer to a CRYP_Context structure that contains
+  *         the repository for current context.
+  * @param  CRYP_KeyInitStruct: pointer to a CRYP_KeyInitTypeDef structure that 
+  *         contains the configuration information for the CRYP Keys.  
+  * @retval None
+  */
+ErrorStatus CRYP_SaveContext(CRYP_Context* CRYP_ContextSave,
+                             CRYP_KeyInitTypeDef* CRYP_KeyInitStruct)
+{
+  __IO uint32_t timeout = 0;
+  uint32_t ckeckmask = 0, bitstatus;    
+  ErrorStatus status = ERROR;
+
+  /* Stop DMA transfers on the IN FIFO by clearing the DIEN bit in the CRYP_DMACR */
+  CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DIEN;
+    
+  /* Wait until both the IN and OUT FIFOs are empty  
+    (IFEM=1 and OFNE=0 in the CRYP_SR register) and the 
+     BUSY bit is cleared. */
+
+  if ((CRYP->CR & (uint32_t)(CRYP_CR_ALGOMODE_TDES_ECB | CRYP_CR_ALGOMODE_TDES_CBC)) != (uint32_t)0 )/* TDES */
+  { 
+    ckeckmask =  CRYP_SR_IFEM | CRYP_SR_BUSY ;
+  }
+  else /* AES or DES */
+  {
+    ckeckmask =  CRYP_SR_IFEM | CRYP_SR_BUSY | CRYP_SR_OFNE;
+  }           
+   
+  do 
+  {
+    bitstatus = CRYP->SR & ckeckmask;
+    timeout++;
+  }
+  while ((timeout != MAX_TIMEOUT) && (bitstatus != CRYP_SR_IFEM));
+     
+  if ((CRYP->SR & ckeckmask) != CRYP_SR_IFEM)
+  {
+    status = ERROR;
+  }
+  else
+  {      
+    /* Stop DMA transfers on the OUT FIFO by 
+       - writing the DOEN bit to 0 in the CRYP_DMACR register 
+       - and clear the CRYPEN bit. */
+
+    CRYP->DMACR &= ~(uint32_t)CRYP_DMACR_DOEN;
+    CRYP->CR &= ~(uint32_t)CRYP_CR_CRYPEN;
+
+    /* Save the current configuration (bits [9:2] in the CRYP_CR register) */
+    CRYP_ContextSave->CR_bits9to2  = CRYP->CR & (CRYP_CR_KEYSIZE  | 
+                                                 CRYP_CR_DATATYPE | 
+                                                 CRYP_CR_ALGOMODE |
+                                                 CRYP_CR_ALGODIR); 
+
+    /* and, if not in ECB mode, the initialization vectors. */
+    CRYP_ContextSave->CRYP_IV0LR = CRYP->IV0LR;
+    CRYP_ContextSave->CRYP_IV0RR = CRYP->IV0RR;
+    CRYP_ContextSave->CRYP_IV1LR = CRYP->IV1LR;
+    CRYP_ContextSave->CRYP_IV1RR = CRYP->IV1RR;
+
+    /* save The key value */
+    CRYP_ContextSave->CRYP_K0LR = CRYP_KeyInitStruct->CRYP_Key0Left; 
+    CRYP_ContextSave->CRYP_K0RR = CRYP_KeyInitStruct->CRYP_Key0Right; 
+    CRYP_ContextSave->CRYP_K1LR = CRYP_KeyInitStruct->CRYP_Key1Left; 
+    CRYP_ContextSave->CRYP_K1RR = CRYP_KeyInitStruct->CRYP_Key1Right; 
+    CRYP_ContextSave->CRYP_K2LR = CRYP_KeyInitStruct->CRYP_Key2Left; 
+    CRYP_ContextSave->CRYP_K2RR = CRYP_KeyInitStruct->CRYP_Key2Right; 
+    CRYP_ContextSave->CRYP_K3LR = CRYP_KeyInitStruct->CRYP_Key3Left; 
+    CRYP_ContextSave->CRYP_K3RR = CRYP_KeyInitStruct->CRYP_Key3Right; 
+
+   /* When needed, save the DMA status (pointers for IN and OUT messages, 
+      number of remaining bytes, etc.) */
+     
+    status = SUCCESS;
+  }
+
+   return status;
+}
+
+/**
+  * @brief  Restores the CRYP peripheral Context.
+  * @note   Since teh DMA transfer is stopped in CRYP_SaveContext() function,
+  *         after restoring the context, you have to enable the DMA again (if the
+  *         DMA was previously used).  
+  * @param  CRYP_ContextRestore: pointer to a CRYP_Context structure that contains
+  *         the repository for saved context.
+  * @note   The data that were saved during context saving must be rewrited into
+  *         the IN FIFO.
+  * @retval None
+  */
+void CRYP_RestoreContext(CRYP_Context* CRYP_ContextRestore)  
+{
+
+  /* Configure the processor with the saved configuration */
+  CRYP->CR = CRYP_ContextRestore->CR_bits9to2;
+
+  /* restore The key value */
+  CRYP->K0LR = CRYP_ContextRestore->CRYP_K0LR; 
+  CRYP->K0RR = CRYP_ContextRestore->CRYP_K0RR;
+  CRYP->K1LR = CRYP_ContextRestore->CRYP_K1LR;
+  CRYP->K1RR = CRYP_ContextRestore->CRYP_K1RR;
+  CRYP->K2LR = CRYP_ContextRestore->CRYP_K2LR;
+  CRYP->K2RR = CRYP_ContextRestore->CRYP_K2RR;
+  CRYP->K3LR = CRYP_ContextRestore->CRYP_K3LR;
+  CRYP->K3RR = CRYP_ContextRestore->CRYP_K3RR;
+
+  /* and the initialization vectors. */
+  CRYP->IV0LR = CRYP_ContextRestore->CRYP_IV0LR;
+  CRYP->IV0RR = CRYP_ContextRestore->CRYP_IV0RR;
+  CRYP->IV1LR = CRYP_ContextRestore->CRYP_IV1LR;
+  CRYP->IV1RR = CRYP_ContextRestore->CRYP_IV1RR;
+
+  /* Enable the cryptographic processor */
+  CRYP->CR |= CRYP_CR_CRYPEN;
+}
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Group4 CRYP's DMA interface Configuration function
+ *  @brief   CRYP's DMA interface Configuration function 
+ *
+@verbatim   
+ ===============================================================================
+                   CRYP's DMA interface Configuration function
+ ===============================================================================  
+
+  This section provides functions allowing to configure the DMA interface for 
+  CRYP data input and output transfer.
+   
+  When the DMA mode is enabled (using the CRYP_DMACmd() function), data can be 
+  transferred:
+  - From memory to the CRYP IN FIFO using the DMA peripheral by enabling 
+    the CRYP_DMAReq_DataIN request.
+  - From the CRYP OUT FIFO to the memory using the DMA peripheral by enabling 
+    the CRYP_DMAReq_DataOUT request.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the CRYP DMA interface.
+  * @param  CRYP_DMAReq: specifies the CRYP DMA transfer request to be enabled or disabled.
+  *           This parameter can be any combination of the following values:
+  *            @arg CRYP_DMAReq_DataOUT: DMA for outgoing(Tx) data transfer
+  *            @arg CRYP_DMAReq_DataIN: DMA for incoming(Rx) data transfer
+  * @param  NewState: new state of the selected CRYP DMA transfer request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CRYP_DMACmd(uint8_t CRYP_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CRYP_DMAREQ(CRYP_DMAReq));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected CRYP DMA request */
+    CRYP->DMACR |= CRYP_DMAReq;
+  }
+  else
+  {
+    /* Disable the selected CRYP DMA request */
+    CRYP->DMACR &= (uint8_t)~CRYP_DMAReq;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup CRYP_Group5 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+                   Interrupts and flags management functions
+ ===============================================================================  
+
+  This section provides functions allowing to configure the CRYP Interrupts and 
+  to get the status and Interrupts pending bits.
+
+  The CRYP provides 2 Interrupts sources and 7 Flags:
+
+  Flags :
+  ------- 
+                          
+     1. CRYP_FLAG_IFEM :  Set when Input FIFO is empty.
+                          This Flag is cleared only by hardware.
+      
+     2. CRYP_FLAG_IFNF :  Set when Input FIFO is not full.
+                          This Flag is cleared only by hardware.
+
+
+     3. CRYP_FLAG_INRIS  : Set when Input FIFO Raw interrupt is pending 
+                           it gives the raw interrupt state prior to masking 
+                           of the input FIFO service interrupt.
+                           This Flag is cleared only by hardware.
+     
+     4. CRYP_FLAG_OFNE   : Set when Output FIFO not empty.
+                           This Flag is cleared only by hardware.
+        
+     5. CRYP_FLAG_OFFU   : Set when Output FIFO is full.
+                           This Flag is cleared only by hardware.
+                           
+     6. CRYP_FLAG_OUTRIS : Set when Output FIFO Raw interrupt is pending 
+                           it gives the raw interrupt state prior to masking 
+                           of the output FIFO service interrupt.
+                           This Flag is cleared only by hardware.
+                               
+     7. CRYP_FLAG_BUSY   : Set when the CRYP core is currently processing a 
+                           block of data or a key preparation (for AES 
+                           decryption).
+                           This Flag is cleared only by hardware.
+                           To clear it, the CRYP core must be disabled and the 
+                           last processing has completed. 
+
+  Interrupts :
+  ------------
+
+   1. CRYP_IT_INI   : The input FIFO service interrupt is asserted when there 
+                      are less than 4 words in the input FIFO.
+                      This interrupt is associated to CRYP_FLAG_INRIS flag.
+
+                @note This interrupt is cleared by performing write operations 
+                      to the input FIFO until it holds 4 or more words. The 
+                      input FIFO service interrupt INMIS is enabled with the 
+                      CRYP enable bit. Consequently, when CRYP is disabled, the 
+                      INMIS signal is low even if the input FIFO is empty.
+
+
+
+   2. CRYP_IT_OUTI  : The output FIFO service interrupt is asserted when there 
+                      is one or more (32-bit word) data items in the output FIFO.
+                      This interrupt is associated to CRYP_FLAG_OUTRIS flag.
+
+                @note This interrupt is cleared by reading data from the output 
+                      FIFO until there is no valid (32-bit) word left (that is, 
+                      the interrupt follows the state of the OFNE (output FIFO 
+                      not empty) flag).
+
+
+  Managing the CRYP controller events :
+  ------------------------------------ 
+  The user should identify which mode will be used in his application to manage 
+  the CRYP controller events: Polling mode or Interrupt mode.
+
+  1.  In the Polling Mode it is advised to use the following functions:
+      - CRYP_GetFlagStatus() : to check if flags events occur. 
+
+  @note  The CRYPT flags do not need to be cleared since they are cleared as 
+         soon as the associated event are reset.   
+
+
+  2.  In the Interrupt Mode it is advised to use the following functions:
+      - CRYP_ITConfig()       : to enable or disable the interrupt source.
+      - CRYP_GetITStatus()    : to check if Interrupt occurs.
+
+  @note  The CRYPT interrupts have no pending bits, the interrupt is cleared as 
+         soon as the associated event is reset. 
+
+@endverbatim
+  * @{
+  */ 
+
+/**
+  * @brief  Enables or disables the specified CRYP interrupts.
+  * @param  CRYP_IT: specifies the CRYP interrupt source to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg CRYP_IT_INI: Input FIFO interrupt
+  *            @arg CRYP_IT_OUTI: Output FIFO interrupt
+  * @param  NewState: new state of the specified CRYP interrupt.
+  *           This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void CRYP_ITConfig(uint8_t CRYP_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_CRYP_CONFIG_IT(CRYP_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected CRYP interrupt */
+    CRYP->IMSCR |= CRYP_IT;
+  }
+  else
+  {
+    /* Disable the selected CRYP interrupt */
+    CRYP->IMSCR &= (uint8_t)~CRYP_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified CRYP interrupt has occurred or not.
+  * @note   This function checks the status of the masked interrupt (i.e the 
+  *         interrupt should be previously enabled).     
+  * @param  CRYP_IT: specifies the CRYP (masked) interrupt source to check.
+  *           This parameter can be one of the following values:
+  *            @arg CRYP_IT_INI: Input FIFO interrupt
+  *            @arg CRYP_IT_OUTI: Output FIFO interrupt
+  * @retval The new state of CRYP_IT (SET or RESET).
+  */
+ITStatus CRYP_GetITStatus(uint8_t CRYP_IT)
+{
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_CRYP_GET_IT(CRYP_IT));
+
+  /* Check the status of the specified CRYP interrupt */
+  if ((CRYP->MISR &  CRYP_IT) != (uint8_t)RESET)
+  {
+    /* CRYP_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CRYP_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the CRYP_IT status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Checks whether the specified CRYP flag is set or not.
+  * @param  CRYP_FLAG: specifies the CRYP flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg CRYP_FLAG_IFEM: Input FIFO Empty flag.
+  *            @arg CRYP_FLAG_IFNF: Input FIFO Not Full flag.
+  *            @arg CRYP_FLAG_OFNE: Output FIFO Not Empty flag.
+  *            @arg CRYP_FLAG_OFFU: Output FIFO Full flag.
+  *            @arg CRYP_FLAG_BUSY: Busy flag.
+  *            @arg CRYP_FLAG_OUTRIS: Output FIFO raw interrupt flag.
+  *            @arg CRYP_FLAG_INRIS: Input FIFO raw interrupt flag.
+  * @retval The new state of CRYP_FLAG (SET or RESET).
+  */
+FlagStatus CRYP_GetFlagStatus(uint8_t CRYP_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tempreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_CRYP_GET_FLAG(CRYP_FLAG));
+
+  /* check if the FLAG is in RISR register */
+  if ((CRYP_FLAG & FLAG_MASK) != 0x00) 
+  {
+    tempreg = CRYP->RISR;
+  }
+  else  /* The FLAG is in SR register */
+  {
+    tempreg = CRYP->SR;
+  }
+
+
+  /* Check the status of the specified CRYP flag */
+  if ((tempreg & CRYP_FLAG ) != (uint8_t)RESET)
+  {
+    /* CRYP_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* CRYP_FLAG is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the CRYP_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c
new file mode 100644
index 0000000000..442040c37d
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_cryp_aes.c
@@ -0,0 +1,638 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_cryp_aes.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides high level functions to encrypt and decrypt an 
+  *          input message using AES in ECB/CBC/CTR modes.
+  *          It uses the stm32f4xx_cryp.c/.h drivers to access the STM32F4xx CRYP
+  *          peripheral.
+  *
+  *  @verbatim
+  *
+  *          ===================================================================
+  *                                   How to use this driver
+  *          ===================================================================
+  *          1. Enable The CRYP controller clock using 
+  *            RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_CRYP, ENABLE); function.
+  *
+  *          2. Encrypt and decrypt using AES in ECB Mode using CRYP_AES_ECB()
+  *             function.
+  *
+  *          3. Encrypt and decrypt using AES in CBC Mode using CRYP_AES_CBC()
+  *             function.
+  *
+  *          4. Encrypt and decrypt using AES in CTR Mode using CRYP_AES_CTR()
+  *             function.
+  *
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************  
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_cryp.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CRYP 
+  * @brief CRYP driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define AESBUSY_TIMEOUT    ((uint32_t) 0x00010000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup CRYP_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup CRYP_Group6 High Level AES functions
+ *  @brief   High Level AES functions 
+ *
+@verbatim   
+ ===============================================================================
+                          High Level AES functions
+ ===============================================================================
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Encrypt and decrypt using AES in ECB Mode
+  * @param  Mode: encryption or decryption Mode.
+  *          This parameter can be one of the following values:
+  *            @arg MODE_ENCRYPT: Encryption
+  *            @arg MODE_DECRYPT: Decryption
+  * @param  Key: Key used for AES algorithm.
+  * @param  Keysize: length of the Key, must be a 128, 192 or 256.
+  * @param  Input: pointer to the Input buffer.
+  * @param  Ilength: length of the Input buffer, must be a multiple of 16.
+  * @param  Output: pointer to the returned buffer.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Operation done
+  *          - ERROR: Operation failed
+  */
+ErrorStatus CRYP_AES_ECB(uint8_t Mode, uint8_t* Key, uint16_t Keysize,
+                         uint8_t* Input, uint32_t Ilength, uint8_t* Output)
+{
+  CRYP_InitTypeDef AES_CRYP_InitStructure;
+  CRYP_KeyInitTypeDef AES_CRYP_KeyInitStructure;
+  __IO uint32_t counter = 0;
+  uint32_t busystatus = 0;
+  ErrorStatus status = SUCCESS;
+  uint32_t keyaddr    = (uint32_t)Key;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+  uint32_t i = 0;
+
+  /* Crypto structures initialisation*/
+  CRYP_KeyStructInit(&AES_CRYP_KeyInitStructure);
+
+  switch(Keysize)
+  {
+    case 128:
+    AES_CRYP_InitStructure.CRYP_KeySize = CRYP_KeySize_128b;
+    AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
+    break;
+    case 192:
+    AES_CRYP_InitStructure.CRYP_KeySize  = CRYP_KeySize_192b;
+    AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
+    break;
+    case 256:
+    AES_CRYP_InitStructure.CRYP_KeySize  = CRYP_KeySize_256b;
+    AES_CRYP_KeyInitStructure.CRYP_Key0Left = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    AES_CRYP_KeyInitStructure.CRYP_Key0Right= __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    AES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    AES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    AES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    AES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    AES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
+    keyaddr+=4;
+    AES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
+    break;
+    default:
+    break;
+  }
+
+  /*------------------ AES Decryption ------------------*/
+  if(Mode == MODE_DECRYPT) /* AES decryption */
+  {
+    /* Flush IN/OUT FIFOs */
+    CRYP_FIFOFlush();
+
+    /* Crypto Init for Key preparation for decryption process */
+    AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
+    AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_Key;
+    AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_32b;
+    CRYP_Init(&AES_CRYP_InitStructure);
+
+    /* Key Initialisation */
+    CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
+
+    /* Enable Crypto processor */
+    CRYP_Cmd(ENABLE);
+
+    /* wait until the Busy flag is RESET */
+    do
+    {
+      busystatus = CRYP_GetFlagStatus(CRYP_FLAG_BUSY);
+      counter++;
+    }while ((counter != AESBUSY_TIMEOUT) && (busystatus != RESET));
+
+    if (busystatus != RESET)
+   {
+       status = ERROR;
+    }
+    else
+    {
+      /* Crypto Init for decryption process */  
+      AES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
+    }
+  }
+  /*------------------ AES Encryption ------------------*/
+  else /* AES encryption */
+  {
+
+    CRYP_KeyInit(&AES_CRYP_KeyInitStructure);
+
+    /* Crypto Init for Encryption process */
+    AES_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Encrypt;
+  }
+
+  AES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_AES_ECB;
+  AES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
+  CRYP_Init(&AES_CRYP_InitStructure);
+
+  /* Flush IN/OUT FIFOs */
+  CRYP_FIFOFlush();
+
+  /* Enable Crypto processor */
+  CRYP_Cmd(ENABLE);
+
+  for(i=0; ((i
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_cryp.h"
+
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CRYP 
+  * @brief CRYP driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define DESBUSY_TIMEOUT    ((uint32_t) 0x00010000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/** @defgroup CRYP_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup CRYP_Group8 High Level DES functions
+ *  @brief   High Level DES functions 
+ *
+@verbatim   
+ ===============================================================================
+                          High Level DES functions
+ ===============================================================================
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Encrypt and decrypt using DES in ECB Mode
+  * @param  Mode: encryption or decryption Mode.
+  *           This parameter can be one of the following values:
+  *            @arg MODE_ENCRYPT: Encryption
+  *            @arg MODE_DECRYPT: Decryption
+  * @param  Key: Key used for DES algorithm.
+  * @param  Ilength: length of the Input buffer, must be a multiple of 8.
+  * @param  Input: pointer to the Input buffer.
+  * @param  Output: pointer to the returned buffer.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Operation done
+  *          - ERROR: Operation failed
+  */
+ErrorStatus CRYP_DES_ECB(uint8_t Mode, uint8_t Key[8], uint8_t *Input, 
+                         uint32_t Ilength, uint8_t *Output)
+{
+  CRYP_InitTypeDef DES_CRYP_InitStructure;
+  CRYP_KeyInitTypeDef DES_CRYP_KeyInitStructure;
+  __IO uint32_t counter = 0;
+  uint32_t busystatus = 0;
+  ErrorStatus status = SUCCESS;
+  uint32_t keyaddr    = (uint32_t)Key;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+  uint32_t i = 0;
+
+  /* Crypto structures initialisation*/
+  CRYP_KeyStructInit(&DES_CRYP_KeyInitStructure);
+
+  /* Crypto Init for Encryption process */
+  if( Mode == MODE_ENCRYPT ) /* DES encryption */
+  {
+     DES_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Encrypt;
+  }
+  else/* if( Mode == MODE_DECRYPT )*/ /* DES decryption */
+  {      
+     DES_CRYP_InitStructure.CRYP_AlgoDir  = CRYP_AlgoDir_Decrypt;
+  }
+
+  DES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_DES_ECB;
+  DES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
+  CRYP_Init(&DES_CRYP_InitStructure);
+
+  /* Key Initialisation */
+  DES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  DES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
+  CRYP_KeyInit(& DES_CRYP_KeyInitStructure);
+
+  /* Flush IN/OUT FIFO */
+  CRYP_FIFOFlush();
+
+  /* Enable Crypto processor */
+  CRYP_Cmd(ENABLE);
+
+  for(i=0; ((i
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_cryp.h"
+
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup CRYP 
+  * @brief CRYP driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define TDESBUSY_TIMEOUT    ((uint32_t) 0x00010000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/** @defgroup CRYP_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup CRYP_Group7 High Level TDES functions
+ *  @brief   High Level TDES functions 
+ *
+@verbatim   
+ ===============================================================================
+                          High Level TDES functions
+ ===============================================================================
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Encrypt and decrypt using TDES in ECB Mode
+  * @param  Mode: encryption or decryption Mode.
+  *           This parameter can be one of the following values:
+  *            @arg MODE_ENCRYPT: Encryption
+  *            @arg MODE_DECRYPT: Decryption
+  * @param  Key: Key used for TDES algorithm.
+  * @param  Ilength: length of the Input buffer, must be a multiple of 8.
+  * @param  Input: pointer to the Input buffer.
+  * @param  Output: pointer to the returned buffer.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: Operation done
+  *          - ERROR: Operation failed
+  */
+ErrorStatus CRYP_TDES_ECB(uint8_t Mode, uint8_t Key[24], uint8_t *Input, 
+                          uint32_t Ilength, uint8_t *Output)
+{
+  CRYP_InitTypeDef TDES_CRYP_InitStructure;
+  CRYP_KeyInitTypeDef TDES_CRYP_KeyInitStructure;
+  __IO uint32_t counter = 0;
+  uint32_t busystatus = 0;
+  ErrorStatus status = SUCCESS;
+  uint32_t keyaddr    = (uint32_t)Key;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+  uint32_t i = 0;
+
+  /* Crypto structures initialisation*/
+  CRYP_KeyStructInit(&TDES_CRYP_KeyInitStructure);
+
+  /* Crypto Init for Encryption process */
+  if(Mode == MODE_ENCRYPT) /* TDES encryption */
+  {
+     TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Encrypt;
+  }
+  else /*if(Mode == MODE_DECRYPT)*/ /* TDES decryption */
+  {
+     TDES_CRYP_InitStructure.CRYP_AlgoDir = CRYP_AlgoDir_Decrypt;
+  }
+
+  TDES_CRYP_InitStructure.CRYP_AlgoMode = CRYP_AlgoMode_TDES_ECB;
+  TDES_CRYP_InitStructure.CRYP_DataType = CRYP_DataType_8b;
+  CRYP_Init(&TDES_CRYP_InitStructure);
+
+  /* Key Initialisation */
+  TDES_CRYP_KeyInitStructure.CRYP_Key1Left = __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  TDES_CRYP_KeyInitStructure.CRYP_Key1Right= __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  TDES_CRYP_KeyInitStructure.CRYP_Key2Left = __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  TDES_CRYP_KeyInitStructure.CRYP_Key2Right= __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  TDES_CRYP_KeyInitStructure.CRYP_Key3Left = __REV(*(uint32_t*)(keyaddr));
+  keyaddr+=4;
+  TDES_CRYP_KeyInitStructure.CRYP_Key3Right= __REV(*(uint32_t*)(keyaddr));
+  CRYP_KeyInit(& TDES_CRYP_KeyInitStructure);
+
+  /* Flush IN/OUT FIFO */
+  CRYP_FIFOFlush();
+
+  /* Enable Crypto processor */
+  CRYP_Cmd(ENABLE);
+
+  for(i=0; ((i
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************  
+  */ 
+
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_dac.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DAC 
+  * @brief DAC driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* CR register Mask */
+#define CR_CLEAR_MASK              ((uint32_t)0x00000FFE)
+
+/* DAC Dual Channels SWTRIG masks */
+#define DUAL_SWTRIG_SET            ((uint32_t)0x00000003)
+#define DUAL_SWTRIG_RESET          ((uint32_t)0xFFFFFFFC)
+
+/* DHR registers offsets */
+#define DHR12R1_OFFSET             ((uint32_t)0x00000008)
+#define DHR12R2_OFFSET             ((uint32_t)0x00000014)
+#define DHR12RD_OFFSET             ((uint32_t)0x00000020)
+
+/* DOR register offset */
+#define DOR_OFFSET                 ((uint32_t)0x0000002C)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DAC_Private_Functions
+  * @{
+  */
+
+/** @defgroup DAC_Group1 DAC channels configuration
+ *  @brief   DAC channels configuration: trigger, output buffer, data format 
+ *
+@verbatim   
+ ===============================================================================
+          DAC channels configuration: trigger, output buffer, data format
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the DAC peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void DAC_DeInit(void)
+{
+  /* Enable DAC reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, ENABLE);
+  /* Release DAC from reset state */
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_DAC, DISABLE);
+}
+
+/**
+  * @brief  Initializes the DAC peripheral according to the specified parameters
+  *         in the DAC_InitStruct.
+  * @param  DAC_Channel: the selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure that contains
+  *         the configuration information for the  specified DAC channel.
+  * @retval None
+  */
+void DAC_Init(uint32_t DAC_Channel, DAC_InitTypeDef* DAC_InitStruct)
+{
+  uint32_t tmpreg1 = 0, tmpreg2 = 0;
+
+  /* Check the DAC parameters */
+  assert_param(IS_DAC_TRIGGER(DAC_InitStruct->DAC_Trigger));
+  assert_param(IS_DAC_GENERATE_WAVE(DAC_InitStruct->DAC_WaveGeneration));
+  assert_param(IS_DAC_LFSR_UNMASK_TRIANGLE_AMPLITUDE(DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude));
+  assert_param(IS_DAC_OUTPUT_BUFFER_STATE(DAC_InitStruct->DAC_OutputBuffer));
+
+/*---------------------------- DAC CR Configuration --------------------------*/
+  /* Get the DAC CR value */
+  tmpreg1 = DAC->CR;
+  /* Clear BOFFx, TENx, TSELx, WAVEx and MAMPx bits */
+  tmpreg1 &= ~(CR_CLEAR_MASK << DAC_Channel);
+  /* Configure for the selected DAC channel: buffer output, trigger, 
+     wave generation, mask/amplitude for wave generation */
+  /* Set TSELx and TENx bits according to DAC_Trigger value */
+  /* Set WAVEx bits according to DAC_WaveGeneration value */
+  /* Set MAMPx bits according to DAC_LFSRUnmask_TriangleAmplitude value */ 
+  /* Set BOFFx bit according to DAC_OutputBuffer value */   
+  tmpreg2 = (DAC_InitStruct->DAC_Trigger | DAC_InitStruct->DAC_WaveGeneration |
+             DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude | \
+             DAC_InitStruct->DAC_OutputBuffer);
+  /* Calculate CR register value depending on DAC_Channel */
+  tmpreg1 |= tmpreg2 << DAC_Channel;
+  /* Write to DAC CR */
+  DAC->CR = tmpreg1;
+}
+
+/**
+  * @brief  Fills each DAC_InitStruct member with its default value.
+  * @param  DAC_InitStruct: pointer to a DAC_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void DAC_StructInit(DAC_InitTypeDef* DAC_InitStruct)
+{
+/*--------------- Reset DAC init structure parameters values -----------------*/
+  /* Initialize the DAC_Trigger member */
+  DAC_InitStruct->DAC_Trigger = DAC_Trigger_None;
+  /* Initialize the DAC_WaveGeneration member */
+  DAC_InitStruct->DAC_WaveGeneration = DAC_WaveGeneration_None;
+  /* Initialize the DAC_LFSRUnmask_TriangleAmplitude member */
+  DAC_InitStruct->DAC_LFSRUnmask_TriangleAmplitude = DAC_LFSRUnmask_Bit0;
+  /* Initialize the DAC_OutputBuffer member */
+  DAC_InitStruct->DAC_OutputBuffer = DAC_OutputBuffer_Enable;
+}
+
+/**
+  * @brief  Enables or disables the specified DAC channel.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the DAC channel. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When the DAC channel is enabled the trigger source can no more be modified.
+  * @retval None
+  */
+void DAC_Cmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel */
+    DAC->CR |= (DAC_CR_EN1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC channel */
+    DAC->CR &= (~(DAC_CR_EN1 << DAC_Channel));
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel software trigger.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the selected DAC channel software trigger.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_SoftwareTriggerCmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for the selected DAC channel */
+    DAC->SWTRIGR |= (uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4);
+  }
+  else
+  {
+    /* Disable software trigger for the selected DAC channel */
+    DAC->SWTRIGR &= ~((uint32_t)DAC_SWTRIGR_SWTRIG1 << (DAC_Channel >> 4));
+  }
+}
+
+/**
+  * @brief  Enables or disables simultaneously the two DAC channels software triggers.
+  * @param  NewState: new state of the DAC channels software triggers.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DAC_DualSoftwareTriggerCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable software trigger for both DAC channels */
+    DAC->SWTRIGR |= DUAL_SWTRIG_SET;
+  }
+  else
+  {
+    /* Disable software trigger for both DAC channels */
+    DAC->SWTRIGR &= DUAL_SWTRIG_RESET;
+  }
+}
+
+/**
+  * @brief  Enables or disables the selected DAC channel wave generation.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_Wave: specifies the wave type to enable or disable.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Wave_Noise: noise wave generation
+  *            @arg DAC_Wave_Triangle: triangle wave generation
+  * @param  NewState: new state of the selected DAC channel wave generation.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void DAC_WaveGenerationCmd(uint32_t DAC_Channel, uint32_t DAC_Wave, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_WAVE(DAC_Wave)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected wave generation for the selected DAC channel */
+    DAC->CR |= DAC_Wave << DAC_Channel;
+  }
+  else
+  {
+    /* Disable the selected wave generation for the selected DAC channel */
+    DAC->CR &= ~(DAC_Wave << DAC_Channel);
+  }
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel1.
+  * @param  DAC_Align: Specifies the data alignment for DAC channel1.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data: Data to be loaded in the selected data holding register.
+  * @retval None
+  */
+void DAC_SetChannel1Data(uint32_t DAC_Align, uint16_t Data)
+{  
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+  
+  tmp = (uint32_t)DAC_BASE; 
+  tmp += DHR12R1_OFFSET + DAC_Align;
+
+  /* Set the DAC channel1 selected data holding register */
+  *(__IO uint32_t *) tmp = Data;
+}
+
+/**
+  * @brief  Set the specified data holding register value for DAC channel2.
+  * @param  DAC_Align: Specifies the data alignment for DAC channel2.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data: Data to be loaded in the selected data holding register.
+  * @retval None
+  */
+void DAC_SetChannel2Data(uint32_t DAC_Align, uint16_t Data)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data));
+  
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DHR12R2_OFFSET + DAC_Align;
+
+  /* Set the DAC channel2 selected data holding register */
+  *(__IO uint32_t *)tmp = Data;
+}
+
+/**
+  * @brief  Set the specified data holding register value for dual channel DAC.
+  * @param  DAC_Align: Specifies the data alignment for dual channel DAC.
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Align_8b_R: 8bit right data alignment selected
+  *            @arg DAC_Align_12b_L: 12bit left data alignment selected
+  *            @arg DAC_Align_12b_R: 12bit right data alignment selected
+  * @param  Data2: Data for DAC Channel2 to be loaded in the selected data holding register.
+  * @param  Data1: Data for DAC Channel1 to be loaded in the selected data  holding register.
+  * @note   In dual mode, a unique register access is required to write in both
+  *          DAC channels at the same time.
+  * @retval None
+  */
+void DAC_SetDualChannelData(uint32_t DAC_Align, uint16_t Data2, uint16_t Data1)
+{
+  uint32_t data = 0, tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_ALIGN(DAC_Align));
+  assert_param(IS_DAC_DATA(Data1));
+  assert_param(IS_DAC_DATA(Data2));
+  
+  /* Calculate and set dual DAC data holding register value */
+  if (DAC_Align == DAC_Align_8b_R)
+  {
+    data = ((uint32_t)Data2 << 8) | Data1; 
+  }
+  else
+  {
+    data = ((uint32_t)Data2 << 16) | Data1;
+  }
+  
+  tmp = (uint32_t)DAC_BASE;
+  tmp += DHR12RD_OFFSET + DAC_Align;
+
+  /* Set the dual DAC selected data holding register */
+  *(__IO uint32_t *)tmp = data;
+}
+
+/**
+  * @brief  Returns the last data output value of the selected DAC channel.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @retval The selected DAC channel data output value.
+  */
+uint16_t DAC_GetDataOutputValue(uint32_t DAC_Channel)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  
+  tmp = (uint32_t) DAC_BASE ;
+  tmp += DOR_OFFSET + ((uint32_t)DAC_Channel >> 2);
+  
+  /* Returns the DAC channel data output register value */
+  return (uint16_t) (*(__IO uint32_t*) tmp);
+}
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Group2 DMA management functions
+ *  @brief   DMA management functions
+ *
+@verbatim   
+ ===============================================================================
+                          DMA management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified DAC channel DMA request.
+  * @note   When enabled DMA1 is generated when an external trigger (EXTI Line9,
+  *         TIM2, TIM4, TIM5, TIM6, TIM7 or TIM8  but not a software trigger) occurs.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  NewState: new state of the selected DAC channel DMA request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   The DAC channel1 is mapped on DMA1 Stream 5 channel7 which must be
+  *          already configured.
+  * @note   The DAC channel2 is mapped on DMA1 Stream 6 channel7 which must be
+  *          already configured.    
+  * @retval None
+  */
+void DAC_DMACmd(uint32_t DAC_Channel, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC channel DMA request */
+    DAC->CR |= (DAC_CR_DMAEN1 << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC channel DMA request */
+    DAC->CR &= (~(DAC_CR_DMAEN1 << DAC_Channel));
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup DAC_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+                   Interrupts and flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified DAC interrupts.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt sources to be enabled or disabled. 
+  *          This parameter can be the following values:
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).
+  * @param  NewState: new state of the specified DAC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */ 
+void DAC_ITConfig(uint32_t DAC_Channel, uint32_t DAC_IT, FunctionalState NewState)  
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_DAC_IT(DAC_IT)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DAC interrupts */
+    DAC->CR |=  (DAC_IT << DAC_Channel);
+  }
+  else
+  {
+    /* Disable the selected DAC interrupts */
+    DAC->CR &= (~(uint32_t)(DAC_IT << DAC_Channel));
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DAC flag is set or not.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_FLAG: specifies the flag to check. 
+  *          This parameter can be only of the following value:
+  *            @arg DAC_FLAG_DMAUDR: DMA underrun flag
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).
+  * @retval The new state of DAC_FLAG (SET or RESET).
+  */
+FlagStatus DAC_GetFlagStatus(uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+  /* Check the status of the specified DAC flag */
+  if ((DAC->SR & (DAC_FLAG << DAC_Channel)) != (uint8_t)RESET)
+  {
+    /* DAC_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DAC_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DAC_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DAC channel's pending flags.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_FLAG: specifies the flag to clear. 
+  *          This parameter can be of the following value:
+  *            @arg DAC_FLAG_DMAUDR: DMA underrun flag 
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).                           
+  * @retval None
+  */
+void DAC_ClearFlag(uint32_t DAC_Channel, uint32_t DAC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_FLAG(DAC_FLAG));
+
+  /* Clear the selected DAC flags */
+  DAC->SR = (DAC_FLAG << DAC_Channel);
+}
+
+/**
+  * @brief  Checks whether the specified DAC interrupt has occurred or not.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt source to check. 
+  *          This parameter can be the following values:
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).
+  * @retval The new state of DAC_IT (SET or RESET).
+  */
+ITStatus DAC_GetITStatus(uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_IT(DAC_IT));
+
+  /* Get the DAC_IT enable bit status */
+  enablestatus = (DAC->CR & (DAC_IT << DAC_Channel)) ;
+  
+  /* Check the status of the specified DAC interrupt */
+  if (((DAC->SR & (DAC_IT << DAC_Channel)) != (uint32_t)RESET) && enablestatus)
+  {
+    /* DAC_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DAC_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the DAC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DAC channel's interrupt pending bits.
+  * @param  DAC_Channel: The selected DAC channel. 
+  *          This parameter can be one of the following values:
+  *            @arg DAC_Channel_1: DAC Channel1 selected
+  *            @arg DAC_Channel_2: DAC Channel2 selected
+  * @param  DAC_IT: specifies the DAC interrupt pending bit to clear.
+  *          This parameter can be the following values:
+  *            @arg DAC_IT_DMAUDR: DMA underrun interrupt mask                         
+  * @note   The DMA underrun occurs when a second external trigger arrives before the 
+  *         acknowledgement for the first external trigger is received (first request).                           
+  * @retval None
+  */
+void DAC_ClearITPendingBit(uint32_t DAC_Channel, uint32_t DAC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_DAC_CHANNEL(DAC_Channel));
+  assert_param(IS_DAC_IT(DAC_IT)); 
+
+  /* Clear the selected DAC interrupt pending bits */
+  DAC->SR = (DAC_IT << DAC_Channel);
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c
new file mode 100644
index 0000000000..65553dd1d8
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dbgmcu.c
@@ -0,0 +1,174 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dbgmcu.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides all the DBGMCU firmware functions.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_dbgmcu.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DBGMCU 
+  * @brief DBGMCU driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define IDCODE_DEVID_MASK    ((uint32_t)0x00000FFF)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DBGMCU_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  Returns the device revision identifier.
+  * @param  None
+  * @retval Device revision identifier
+  */
+uint32_t DBGMCU_GetREVID(void)
+{
+   return(DBGMCU->IDCODE >> 16);
+}
+
+/**
+  * @brief  Returns the device identifier.
+  * @param  None
+  * @retval Device identifier
+  */
+uint32_t DBGMCU_GetDEVID(void)
+{
+   return(DBGMCU->IDCODE & IDCODE_DEVID_MASK);
+}
+
+/**
+  * @brief  Configures low power mode behavior when the MCU is in Debug mode.
+  * @param  DBGMCU_Periph: specifies the low power mode.
+  *   This parameter can be any combination of the following values:
+  *     @arg DBGMCU_SLEEP: Keep debugger connection during SLEEP mode              
+  *     @arg DBGMCU_STOP: Keep debugger connection during STOP mode               
+  *     @arg DBGMCU_STANDBY: Keep debugger connection during STANDBY mode        
+  * @param  NewState: new state of the specified low power mode in Debug mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DBGMCU_Config(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    DBGMCU->CR |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->CR &= ~DBGMCU_Periph;
+  }
+}
+
+/**
+  * @brief  Configures APB1 peripheral behavior when the MCU is in Debug mode.
+  * @param  DBGMCU_Periph: specifies the APB1 peripheral.
+  *   This parameter can be any combination of the following values:        
+  *     @arg DBGMCU_TIM2_STOP: TIM2 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM3_STOP: TIM3 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM4_STOP: TIM4 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM5_STOP: TIM5 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM6_STOP: TIM6 counter stopped when Core is halted          
+  *     @arg DBGMCU_TIM7_STOP: TIM7 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM12_STOP: TIM12 counter stopped when Core is halted  
+  *     @arg DBGMCU_TIM13_STOP: TIM13 counter stopped when Core is halted  
+  *     @arg DBGMCU_TIM14_STOP: TIM14 counter stopped when Core is halted 
+  *     @arg DBGMCU_RTC_STOP: RTC Calendar and Wakeup counter stopped when Core is halted.                                                                                
+  *     @arg DBGMCU_WWDG_STOP: Debug WWDG stopped when Core is halted
+  *     @arg DBGMCU_IWDG_STOP: Debug IWDG stopped when Core is halted        
+  *     @arg DBGMCU_I2C1_SMBUS_TIMEOUT: I2C1 SMBUS timeout mode stopped when Core is halted
+  *     @arg DBGMCU_I2C2_SMBUS_TIMEOUT: I2C2 SMBUS timeout mode stopped when Core is halted
+  *     @arg DBGMCU_I2C3_SMBUS_TIMEOUT: I2C3 SMBUS timeout mode stopped when Core is halted
+  *     @arg DBGMCU_CAN2_STOP: Debug CAN1 stopped when Core is halted           
+  *     @arg DBGMCU_CAN1_STOP: Debug CAN2 stopped when Core is halted        
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DBGMCU_APB1PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_APB1PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    DBGMCU->APB1FZ |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->APB1FZ &= ~DBGMCU_Periph;
+  }
+}
+
+/**
+  * @brief  Configures APB2 peripheral behavior when the MCU is in Debug mode.
+  * @param  DBGMCU_Periph: specifies the APB2 peripheral.
+  *   This parameter can be any combination of the following values:       
+  *     @arg DBGMCU_TIM1_STOP: TIM1 counter stopped when Core is halted                
+  *     @arg DBGMCU_TIM8_STOP: TIM8 counter stopped when Core is halted
+  *     @arg DBGMCU_TIM9_STOP: TIM9 counter stopped when Core is halted   
+  *     @arg DBGMCU_TIM10_STOP: TIM10 counter stopped when Core is halted   
+  *     @arg DBGMCU_TIM11_STOP: TIM11 counter stopped when Core is halted                                                                                  
+  * @param  NewState: new state of the specified peripheral in Debug mode.
+  *   This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DBGMCU_APB2PeriphConfig(uint32_t DBGMCU_Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DBGMCU_APB2PERIPH(DBGMCU_Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    DBGMCU->APB2FZ |= DBGMCU_Periph;
+  }
+  else
+  {
+    DBGMCU->APB2FZ &= ~DBGMCU_Periph;
+  }
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c
new file mode 100644
index 0000000000..afef61858e
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dcmi.c
@@ -0,0 +1,534 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dcmi.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the DCMI peripheral:           
+  *           - Initialization and Configuration
+  *           - Image capture functions  
+  *           - Interrupts and flags management
+  *
+  *  @verbatim  
+  *  
+  *        
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================  
+  *         
+  *         The sequence below describes how to use this driver to capture image
+  *         from a camera module connected to the DCMI Interface.
+  *         This sequence does not take into account the configuration of the  
+  *         camera module, which should be made before to configure and enable
+  *         the DCMI to capture images.
+  *           
+  *          1. Enable the clock for the DCMI and associated GPIOs using the following functions:
+  *                 RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_DCMI, ENABLE);
+  *                 RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+  *
+  *          2. DCMI pins configuration 
+  *             - Connect the involved DCMI pins to AF13 using the following function 
+  *                 GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_DCMI); 
+  *             - Configure these DCMI pins in alternate function mode by calling the function
+  *                 GPIO_Init();
+  *    
+  *          3. Declare a DCMI_InitTypeDef structure, for example:
+  *                 DCMI_InitTypeDef  DCMI_InitStructure;
+  *             and fill the DCMI_InitStructure variable with the allowed values
+  *             of the structure member.
+  *  
+  *          4. Initialize the DCMI interface by calling the function
+  *                 DCMI_Init(&DCMI_InitStructure); 
+  *  
+  *          5. Configure the DMA2_Stream1 channel1 to transfer Data from DCMI DR
+  *             register to the destination memory buffer.
+  *  
+  *          6. Enable DCMI interface using the function
+  *                 DCMI_Cmd(ENABLE);
+  *                 
+  *         7. Start the image capture using the function
+  *                 DCMI_CaptureCmd(ENABLE);
+  *                 
+  *         8. At this stage the DCMI interface waits for the first start of frame,
+  *            then a DMA request is generated continuously/once (depending on the
+  *            mode used, Continuous/Snapshot) to transfer the received data into
+  *            the destination memory. 
+  *   
+  *  @note  If you need to capture only a rectangular window from the received
+  *         image, you have to use the DCMI_CROPConfig() function to configure 
+  *         the coordinates and size of the window to be captured, then enable 
+  *         the Crop feature using DCMI_CROPCmd(ENABLE);  
+  *         In this case, the Crop configuration should be made before to enable
+  *         and start the DCMI interface. 
+  *        
+  *  @endverbatim   
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_dcmi.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DCMI 
+  * @brief DCMI driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup DCMI_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup DCMI_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                  Initialization and Configuration functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the DCMI registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void DCMI_DeInit(void)
+{
+  DCMI->CR = 0x0;
+  DCMI->IER = 0x0;
+  DCMI->ICR = 0x1F;
+  DCMI->ESCR = 0x0;
+  DCMI->ESUR = 0x0;
+  DCMI->CWSTRTR = 0x0;
+  DCMI->CWSIZER = 0x0;
+}
+
+/**
+  * @brief  Initializes the DCMI according to the specified parameters in the DCMI_InitStruct.
+  * @param  DCMI_InitStruct: pointer to a DCMI_InitTypeDef structure that contains 
+  *         the configuration information for the DCMI.
+  * @retval None
+  */
+void DCMI_Init(DCMI_InitTypeDef* DCMI_InitStruct)
+{
+  uint32_t temp = 0x0;
+  
+  /* Check the parameters */
+  assert_param(IS_DCMI_CAPTURE_MODE(DCMI_InitStruct->DCMI_CaptureMode));
+  assert_param(IS_DCMI_SYNCHRO(DCMI_InitStruct->DCMI_SynchroMode));
+  assert_param(IS_DCMI_PCKPOLARITY(DCMI_InitStruct->DCMI_PCKPolarity));
+  assert_param(IS_DCMI_VSPOLARITY(DCMI_InitStruct->DCMI_VSPolarity));
+  assert_param(IS_DCMI_HSPOLARITY(DCMI_InitStruct->DCMI_HSPolarity));
+  assert_param(IS_DCMI_CAPTURE_RATE(DCMI_InitStruct->DCMI_CaptureRate));
+  assert_param(IS_DCMI_EXTENDED_DATA(DCMI_InitStruct->DCMI_ExtendedDataMode));
+
+  /* The DCMI configuration registers should be programmed correctly before 
+  enabling the CR_ENABLE Bit and the CR_CAPTURE Bit */
+  DCMI->CR &= ~(DCMI_CR_ENABLE | DCMI_CR_CAPTURE);
+   
+  /* Reset the old DCMI configuration */
+  temp = DCMI->CR;
+  
+  temp &= ~((uint32_t)DCMI_CR_CM     | DCMI_CR_ESS   | DCMI_CR_PCKPOL |
+                      DCMI_CR_HSPOL  | DCMI_CR_VSPOL | DCMI_CR_FCRC_0 | 
+                      DCMI_CR_FCRC_1 | DCMI_CR_EDM_0 | DCMI_CR_EDM_1); 
+                  
+  /* Sets the new configuration of the DCMI peripheral */
+  temp |= ((uint32_t)DCMI_InitStruct->DCMI_CaptureMode |
+                     DCMI_InitStruct->DCMI_SynchroMode |
+                     DCMI_InitStruct->DCMI_PCKPolarity |
+                     DCMI_InitStruct->DCMI_VSPolarity |
+                     DCMI_InitStruct->DCMI_HSPolarity |
+                     DCMI_InitStruct->DCMI_CaptureRate |
+                     DCMI_InitStruct->DCMI_ExtendedDataMode);
+
+  DCMI->CR = temp;                              
+}
+
+/**
+  * @brief  Fills each DCMI_InitStruct member with its default value.
+  * @param  DCMI_InitStruct : pointer to a DCMI_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void DCMI_StructInit(DCMI_InitTypeDef* DCMI_InitStruct)
+{
+  /* Set the default configuration */
+  DCMI_InitStruct->DCMI_CaptureMode = DCMI_CaptureMode_Continuous;
+  DCMI_InitStruct->DCMI_SynchroMode = DCMI_SynchroMode_Hardware;
+  DCMI_InitStruct->DCMI_PCKPolarity = DCMI_PCKPolarity_Falling;
+  DCMI_InitStruct->DCMI_VSPolarity = DCMI_VSPolarity_Low;
+  DCMI_InitStruct->DCMI_HSPolarity = DCMI_HSPolarity_Low;
+  DCMI_InitStruct->DCMI_CaptureRate = DCMI_CaptureRate_All_Frame;
+  DCMI_InitStruct->DCMI_ExtendedDataMode = DCMI_ExtendedDataMode_8b;
+}
+
+/**
+  * @brief  Initializes the DCMI peripheral CROP mode according to the specified
+  *         parameters in the DCMI_CROPInitStruct.
+  * @note   This function should be called before to enable and start the DCMI interface.   
+  * @param  DCMI_CROPInitStruct:  pointer to a DCMI_CROPInitTypeDef structure that 
+  *         contains the configuration information for the DCMI peripheral CROP mode.
+  * @retval None
+  */
+void DCMI_CROPConfig(DCMI_CROPInitTypeDef* DCMI_CROPInitStruct)
+{  
+  /* Sets the CROP window coordinates */
+  DCMI->CWSTRTR = (uint32_t)((uint32_t)DCMI_CROPInitStruct->DCMI_HorizontalOffsetCount |
+                  ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalStartLine << 16));
+
+  /* Sets the CROP window size */
+  DCMI->CWSIZER = (uint32_t)(DCMI_CROPInitStruct->DCMI_CaptureCount |
+                  ((uint32_t)DCMI_CROPInitStruct->DCMI_VerticalLineCount << 16));
+}
+
+/**
+  * @brief  Enables or disables the DCMI Crop feature.
+  * @note   This function should be called before to enable and start the DCMI interface.
+  * @param  NewState: new state of the DCMI Crop feature. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DCMI_CROPCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+    
+  if (NewState != DISABLE)
+  {
+    /* Enable the DCMI Crop feature */
+    DCMI->CR |= (uint32_t)DCMI_CR_CROP;
+  }
+  else
+  {
+    /* Disable the DCMI Crop feature */
+    DCMI->CR &= ~(uint32_t)DCMI_CR_CROP;
+  }
+}
+
+/**
+  * @brief  Sets the embedded synchronization codes
+  * @param  DCMI_CodesInitTypeDef: pointer to a DCMI_CodesInitTypeDef structure that
+  *         contains the embedded synchronization codes for the DCMI peripheral.
+  * @retval None
+  */
+void DCMI_SetEmbeddedSynchroCodes(DCMI_CodesInitTypeDef* DCMI_CodesInitStruct)
+{
+  DCMI->ESCR = (uint32_t)(DCMI_CodesInitStruct->DCMI_FrameStartCode |
+                          ((uint32_t)DCMI_CodesInitStruct->DCMI_LineStartCode << 8)|
+                          ((uint32_t)DCMI_CodesInitStruct->DCMI_LineEndCode << 16)|
+                          ((uint32_t)DCMI_CodesInitStruct->DCMI_FrameEndCode << 24));
+}
+
+/**
+  * @brief  Enables or disables the DCMI JPEG format.
+  * @note   The Crop and Embedded Synchronization features cannot be used in this mode.  
+  * @param  NewState: new state of the DCMI JPEG format. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DCMI_JPEGCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+ 
+  if (NewState != DISABLE)
+  {
+    /* Enable the DCMI JPEG format */
+    DCMI->CR |= (uint32_t)DCMI_CR_JPEG;
+  }
+  else
+  {
+    /* Disable the DCMI JPEG format */
+    DCMI->CR &= ~(uint32_t)DCMI_CR_JPEG;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Group2 Image capture functions
+ *  @brief   Image capture functions
+ *
+@verbatim   
+ ===============================================================================
+                                 Image capture functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Enables or disables the DCMI interface.
+  * @param  NewState: new state of the DCMI interface. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DCMI_Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the DCMI by setting ENABLE bit */
+    DCMI->CR |= (uint32_t)DCMI_CR_ENABLE;
+  }
+  else
+  {
+    /* Disable the DCMI by clearing ENABLE bit */
+    DCMI->CR &= ~(uint32_t)DCMI_CR_ENABLE;
+  }
+}
+
+/**
+  * @brief  Enables or disables the DCMI Capture.
+  * @param  NewState: new state of the DCMI capture. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DCMI_CaptureCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+    
+  if (NewState != DISABLE)
+  {
+    /* Enable the DCMI Capture */
+    DCMI->CR |= (uint32_t)DCMI_CR_CAPTURE;
+  }
+  else
+  {
+    /* Disable the DCMI Capture */
+    DCMI->CR &= ~(uint32_t)DCMI_CR_CAPTURE;
+  }
+}
+
+/**
+  * @brief  Reads the data stored in the DR register.
+  * @param  None 
+  * @retval Data register value
+  */
+uint32_t DCMI_ReadData(void)
+{
+  return DCMI->DR;
+}
+/**
+  * @}
+  */
+
+/** @defgroup DCMI_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+                  Interrupts and flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the DCMI interface interrupts.
+  * @param  DCMI_IT: specifies the DCMI interrupt sources to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+  *            @arg DCMI_IT_OVF: Overflow interrupt mask
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+  *            @arg DCMI_IT_LINE: Line interrupt mask
+  * @param  NewState: new state of the specified DCMI interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DCMI_ITConfig(uint16_t DCMI_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DCMI_CONFIG_IT(DCMI_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the Interrupt sources */
+    DCMI->IER |= DCMI_IT;
+  }
+  else
+  {
+    /* Disable the Interrupt sources */
+    DCMI->IER &= (uint16_t)(~DCMI_IT);
+  }  
+}
+
+/**
+  * @brief  Checks whether the  DCMI interface flag is set or not.
+  * @param  DCMI_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask
+  *            @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask
+  *            @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask
+  *            @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask
+  *            @arg DCMI_FLAG_LINERI: Line Raw flag mask
+  *            @arg DCMI_FLAG_FRAMEMI: Frame capture complete Masked flag mask
+  *            @arg DCMI_FLAG_OVFMI: Overflow Masked flag mask
+  *            @arg DCMI_FLAG_ERRMI: Synchronization error Masked flag mask
+  *            @arg DCMI_FLAG_VSYNCMI: VSYNC Masked flag mask
+  *            @arg DCMI_FLAG_LINEMI: Line Masked flag mask
+  *            @arg DCMI_FLAG_HSYNC: HSYNC flag mask
+  *            @arg DCMI_FLAG_VSYNC: VSYNC flag mask
+  *            @arg DCMI_FLAG_FNE: Fifo not empty flag mask
+  * @retval The new state of DCMI_FLAG (SET or RESET).
+  */
+FlagStatus DCMI_GetFlagStatus(uint16_t DCMI_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t dcmireg, tempreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DCMI_GET_FLAG(DCMI_FLAG));
+  
+  /* Get the DCMI register index */
+  dcmireg = (((uint16_t)DCMI_FLAG) >> 12);
+  
+  if (dcmireg == 0x01) /* The FLAG is in RISR register */
+  {
+    tempreg= DCMI->RISR;
+  }
+  else if (dcmireg == 0x02) /* The FLAG is in SR register */
+  {
+    tempreg = DCMI->SR;
+  }
+  else /* The FLAG is in MISR register */
+  {
+    tempreg = DCMI->MISR;
+  }
+  
+  if ((tempreg & DCMI_FLAG) != (uint16_t)RESET )
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the DCMI_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DCMI's pending flags.
+  * @param  DCMI_FLAG: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DCMI_FLAG_FRAMERI: Frame capture complete Raw flag mask
+  *            @arg DCMI_FLAG_OVFRI: Overflow Raw flag mask
+  *            @arg DCMI_FLAG_ERRRI: Synchronization error Raw flag mask
+  *            @arg DCMI_FLAG_VSYNCRI: VSYNC Raw flag mask
+  *            @arg DCMI_FLAG_LINERI: Line Raw flag mask
+  * @retval None
+  */
+void DCMI_ClearFlag(uint16_t DCMI_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_DCMI_CLEAR_FLAG(DCMI_FLAG));
+  
+  /* Clear the flag by writing in the ICR register 1 in the corresponding 
+  Flag position*/
+  
+  DCMI->ICR = DCMI_FLAG;
+}
+
+/**
+  * @brief  Checks whether the DCMI interrupt has occurred or not.
+  * @param  DCMI_IT: specifies the DCMI interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+  *            @arg DCMI_IT_OVF: Overflow interrupt mask
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+  *            @arg DCMI_IT_LINE: Line interrupt mask
+  * @retval The new state of DCMI_IT (SET or RESET).
+  */
+ITStatus DCMI_GetITStatus(uint16_t DCMI_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t itstatus = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DCMI_GET_IT(DCMI_IT));
+  
+  itstatus = DCMI->MISR & DCMI_IT; /* Only masked interrupts are checked */
+  
+  if ((itstatus != (uint16_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the DCMI's interrupt pending bits.
+  * @param  DCMI_IT: specifies the DCMI interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DCMI_IT_FRAME: Frame capture complete interrupt mask
+  *            @arg DCMI_IT_OVF: Overflow interrupt mask
+  *            @arg DCMI_IT_ERR: Synchronization error interrupt mask
+  *            @arg DCMI_IT_VSYNC: VSYNC interrupt mask
+  *            @arg DCMI_IT_LINE: Line interrupt mask
+  * @retval None
+  */
+void DCMI_ClearITPendingBit(uint16_t DCMI_IT)
+{
+  /* Clear the interrupt pending Bit by writing in the ICR register 1 in the 
+  corresponding pending Bit position*/
+  
+  DCMI->ICR = DCMI_IT;
+}
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c
new file mode 100644
index 0000000000..4b0c6540bd
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_dma.c
@@ -0,0 +1,1283 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_dma.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Direct Memory Access controller (DMA):           
+  *           - Initialization and Configuration
+  *           - Data Counter
+  *           - Double Buffer mode configuration and command  
+  *           - Interrupts and flags management
+  *           
+  *  @verbatim
+  *      
+  *          ===================================================================      
+  *                                 How to use this driver
+  *          =================================================================== 
+  *          1. Enable The DMA controller clock using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA1, ENABLE)
+  *             function for DMA1 or using RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_DMA2, ENABLE)
+  *             function for DMA2.
+  *
+  *          2. Enable and configure the peripheral to be connected to the DMA Stream
+  *             (except for internal SRAM / FLASH memories: no initialization is 
+  *             necessary). 
+  *        
+  *          3. For a given Stream, program the required configuration through following parameters:   
+  *             Source and Destination addresses, Transfer Direction, Transfer size, Source and Destination 
+  *             data formats, Circular or Normal mode, Stream Priority level, Source and Destination 
+  *             Incrementation mode, FIFO mode and its Threshold (if needed), Burst mode for Source and/or 
+  *             Destination (if needed) using the DMA_Init() function.
+  *             To avoid filling un-nesecessary fields, you can call DMA_StructInit() function
+  *             to initialize a given structure with default values (reset values), the modify
+  *             only necessary fields (ie. Source and Destination addresses, Transfer size and Data Formats).
+  *
+  *          4. Enable the NVIC and the corresponding interrupt(s) using the function 
+  *             DMA_ITConfig() if you need to use DMA interrupts. 
+  *
+  *          5. Optionally, if the Circular mode is enabled, you can use the Double buffer mode by configuring 
+  *             the second Memory address and the first Memory to be used through the function 
+  *             DMA_DoubleBufferModeConfig(). Then enable the Double buffer mode through the function
+  *             DMA_DoubleBufferModeCmd(). These operations must be done before step 6.
+  *    
+  *          6. Enable the DMA stream using the DMA_Cmd() function. 
+  *                
+  *          7. Activate the needed Stream Request using PPP_DMACmd() function for
+  *             any PPP peripheral except internal SRAM and FLASH (ie. SPI, USART ...)
+  *             The function allowing this operation is provided in each PPP peripheral
+  *             driver (ie. SPI_DMACmd for SPI peripheral).
+  *             Once the Stream is enabled, it is not possible to modify its configuration
+  *             unless the stream is stopped and disabled.
+  *             After enabling the Stream, it is advised to monitor the EN bit status using
+  *             the function DMA_GetCmdStatus(). In case of configuration errors or bus errors
+  *             this bit will remain reset and all transfers on this Stream will remain on hold.      
+  *
+  *          8. Optionally, you can configure the number of data to be transferred
+  *             when the Stream is disabled (ie. after each Transfer Complete event
+  *             or when a Transfer Error occurs) using the function DMA_SetCurrDataCounter().
+  *             And you can get the number of remaining data to be transferred using 
+  *             the function DMA_GetCurrDataCounter() at run time (when the DMA Stream is
+  *             enabled and running).  
+  *                   
+  *          9. To control DMA events you can use one of the following 
+  *              two methods:
+  *               a- Check on DMA Stream flags using the function DMA_GetFlagStatus().  
+  *               b- Use DMA interrupts through the function DMA_ITConfig() at initialization
+  *                  phase and DMA_GetITStatus() function into interrupt routines in
+  *                  communication phase.  
+  *              After checking on a flag you should clear it using DMA_ClearFlag()
+  *              function. And after checking on an interrupt event you should 
+  *              clear it using DMA_ClearITPendingBit() function.    
+  *              
+  *          10. Optionally, if Circular mode and Double Buffer mode are enabled, you can modify
+  *              the Memory Addresses using the function DMA_MemoryTargetConfig(). Make sure that
+  *              the Memory Address to be modified is not the one currently in use by DMA Stream.
+  *              This condition can be monitored using the function DMA_GetCurrentMemoryTarget().
+  *              
+  *          11. Optionally, Pause-Resume operations may be performed:
+  *              The DMA_Cmd() function may be used to perform Pause-Resume operation. When a 
+  *              transfer is ongoing, calling this function to disable the Stream will cause the 
+  *              transfer to be paused. All configuration registers and the number of remaining 
+  *              data will be preserved. When calling again this function to re-enable the Stream, 
+  *              the transfer will be resumed from the point where it was paused.          
+  *                 
+  * @note   Memory-to-Memory transfer is possible by setting the address of the memory into
+  *         the Peripheral registers. In this mode, Circular mode and Double Buffer mode
+  *         are not allowed.
+  *  
+  * @note   The FIFO is used mainly to reduce bus usage and to allow data packing/unpacking: it is
+  *         possible to set different Data Sizes for the Peripheral and the Memory (ie. you can set
+  *         Half-Word data size for the peripheral to access its data register and set Word data size
+  *         for the Memory to gain in access time. Each two Half-words will be packed and written in
+  *         a single access to a Word in the Memory).
+  *    
+  * @note  When FIFO is disabled, it is not allowed to configure different Data Sizes for Source
+  *        and Destination. In this case the Peripheral Data Size will be applied to both Source
+  *        and Destination.               
+  *
+  *  @endverbatim
+  *                                  
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************  
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_dma.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup DMA 
+  * @brief DMA driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Masks Definition */
+#define TRANSFER_IT_ENABLE_MASK (uint32_t)(DMA_SxCR_TCIE | DMA_SxCR_HTIE | \
+                                           DMA_SxCR_TEIE | DMA_SxCR_DMEIE)
+
+#define DMA_Stream0_IT_MASK     (uint32_t)(DMA_LISR_FEIF0 | DMA_LISR_DMEIF0 | \
+                                           DMA_LISR_TEIF0 | DMA_LISR_HTIF0 | \
+                                           DMA_LISR_TCIF0)
+
+#define DMA_Stream1_IT_MASK     (uint32_t)(DMA_Stream0_IT_MASK << 6)
+#define DMA_Stream2_IT_MASK     (uint32_t)(DMA_Stream0_IT_MASK << 16)
+#define DMA_Stream3_IT_MASK     (uint32_t)(DMA_Stream0_IT_MASK << 22)
+#define DMA_Stream4_IT_MASK     (uint32_t)(DMA_Stream0_IT_MASK | (uint32_t)0x20000000)
+#define DMA_Stream5_IT_MASK     (uint32_t)(DMA_Stream1_IT_MASK | (uint32_t)0x20000000)
+#define DMA_Stream6_IT_MASK     (uint32_t)(DMA_Stream2_IT_MASK | (uint32_t)0x20000000)
+#define DMA_Stream7_IT_MASK     (uint32_t)(DMA_Stream3_IT_MASK | (uint32_t)0x20000000)
+#define TRANSFER_IT_MASK        (uint32_t)0x0F3C0F3C
+#define HIGH_ISR_MASK           (uint32_t)0x20000000
+#define RESERVED_MASK           (uint32_t)0x0F7D0F7D  
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+
+/** @defgroup DMA_Private_Functions
+  * @{
+  */
+
+/** @defgroup DMA_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions
+ *
+@verbatim   
+ ===============================================================================
+                 Initialization and Configuration functions
+ ===============================================================================  
+
+  This subsection provides functions allowing to initialize the DMA Stream source
+  and destination addresses, incrementation and data sizes, transfer direction, 
+  buffer size, circular/normal mode selection, memory-to-memory mode selection 
+  and Stream priority value.
+  
+  The DMA_Init() function follows the DMA configuration procedures as described in
+  reference manual (RM0090) except the first point: waiting on EN bit to be reset.
+  This condition should be checked by user application using the function DMA_GetCmdStatus()
+  before calling the DMA_Init() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitialize the DMAy Streamx registers to their default reset values.
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+  *         to 7 to select the DMA Stream.
+  * @retval None
+  */
+void DMA_DeInit(DMA_Stream_TypeDef* DMAy_Streamx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+
+  /* Disable the selected DMAy Streamx */
+  DMAy_Streamx->CR &= ~((uint32_t)DMA_SxCR_EN);
+
+  /* Reset DMAy Streamx control register */
+  DMAy_Streamx->CR  = 0;
+  
+  /* Reset DMAy Streamx Number of Data to Transfer register */
+  DMAy_Streamx->NDTR = 0;
+  
+  /* Reset DMAy Streamx peripheral address register */
+  DMAy_Streamx->PAR  = 0;
+  
+  /* Reset DMAy Streamx memory 0 address register */
+  DMAy_Streamx->M0AR = 0;
+
+  /* Reset DMAy Streamx memory 1 address register */
+  DMAy_Streamx->M1AR = 0;
+
+  /* Reset DMAy Streamx FIFO control register */
+  DMAy_Streamx->FCR = (uint32_t)0x00000021; 
+
+  /* Reset interrupt pending bits for the selected stream */
+  if (DMAy_Streamx == DMA1_Stream0)
+  {
+    /* Reset interrupt pending bits for DMA1 Stream0 */
+    DMA1->LIFCR = DMA_Stream0_IT_MASK;
+  }
+  else if (DMAy_Streamx == DMA1_Stream1)
+  {
+    /* Reset interrupt pending bits for DMA1 Stream1 */
+    DMA1->LIFCR = DMA_Stream1_IT_MASK;
+  }
+  else if (DMAy_Streamx == DMA1_Stream2)
+  {
+    /* Reset interrupt pending bits for DMA1 Stream2 */
+    DMA1->LIFCR = DMA_Stream2_IT_MASK;
+  }
+  else if (DMAy_Streamx == DMA1_Stream3)
+  {
+    /* Reset interrupt pending bits for DMA1 Stream3 */
+    DMA1->LIFCR = DMA_Stream3_IT_MASK;
+  }
+  else if (DMAy_Streamx == DMA1_Stream4)
+  {
+    /* Reset interrupt pending bits for DMA1 Stream4 */
+    DMA1->HIFCR = DMA_Stream4_IT_MASK;
+  }
+  else if (DMAy_Streamx == DMA1_Stream5)
+  {
+    /* Reset interrupt pending bits for DMA1 Stream5 */
+    DMA1->HIFCR = DMA_Stream5_IT_MASK;
+  }
+  else if (DMAy_Streamx == DMA1_Stream6)
+  {
+    /* Reset interrupt pending bits for DMA1 Stream6 */
+    DMA1->HIFCR = (uint32_t)DMA_Stream6_IT_MASK;
+  }
+  else if (DMAy_Streamx == DMA1_Stream7)
+  {
+    /* Reset interrupt pending bits for DMA1 Stream7 */
+    DMA1->HIFCR = DMA_Stream7_IT_MASK;
+  }
+  else if (DMAy_Streamx == DMA2_Stream0)
+  {
+    /* Reset interrupt pending bits for DMA2 Stream0 */
+    DMA2->LIFCR = DMA_Stream0_IT_MASK;
+  }
+  else if (DMAy_Streamx == DMA2_Stream1)
+  {
+    /* Reset interrupt pending bits for DMA2 Stream1 */
+    DMA2->LIFCR = DMA_Stream1_IT_MASK;
+  }
+  else if (DMAy_Streamx == DMA2_Stream2)
+  {
+    /* Reset interrupt pending bits for DMA2 Stream2 */
+    DMA2->LIFCR = DMA_Stream2_IT_MASK;
+  }
+  else if (DMAy_Streamx == DMA2_Stream3)
+  {
+    /* Reset interrupt pending bits for DMA2 Stream3 */
+    DMA2->LIFCR = DMA_Stream3_IT_MASK;
+  }
+  else if (DMAy_Streamx == DMA2_Stream4)
+  {
+    /* Reset interrupt pending bits for DMA2 Stream4 */
+    DMA2->HIFCR = DMA_Stream4_IT_MASK;
+  }
+  else if (DMAy_Streamx == DMA2_Stream5)
+  {
+    /* Reset interrupt pending bits for DMA2 Stream5 */
+    DMA2->HIFCR = DMA_Stream5_IT_MASK;
+  }
+  else if (DMAy_Streamx == DMA2_Stream6)
+  {
+    /* Reset interrupt pending bits for DMA2 Stream6 */
+    DMA2->HIFCR = DMA_Stream6_IT_MASK;
+  }
+  else 
+  {
+    if (DMAy_Streamx == DMA2_Stream7)
+    {
+      /* Reset interrupt pending bits for DMA2 Stream7 */
+      DMA2->HIFCR = DMA_Stream7_IT_MASK;
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the DMAy Streamx according to the specified parameters in 
+  *         the DMA_InitStruct structure.
+  * @note   Before calling this function, it is recommended to check that the Stream 
+  *         is actually disabled using the function DMA_GetCmdStatus().  
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+  *         to 7 to select the DMA Stream.
+  * @param  DMA_InitStruct: pointer to a DMA_InitTypeDef structure that contains
+  *         the configuration information for the specified DMA Stream.  
+  * @retval None
+  */
+void DMA_Init(DMA_Stream_TypeDef* DMAy_Streamx, DMA_InitTypeDef* DMA_InitStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+  assert_param(IS_DMA_CHANNEL(DMA_InitStruct->DMA_Channel));
+  assert_param(IS_DMA_DIRECTION(DMA_InitStruct->DMA_DIR));
+  assert_param(IS_DMA_BUFFER_SIZE(DMA_InitStruct->DMA_BufferSize));
+  assert_param(IS_DMA_PERIPHERAL_INC_STATE(DMA_InitStruct->DMA_PeripheralInc));
+  assert_param(IS_DMA_MEMORY_INC_STATE(DMA_InitStruct->DMA_MemoryInc));
+  assert_param(IS_DMA_PERIPHERAL_DATA_SIZE(DMA_InitStruct->DMA_PeripheralDataSize));
+  assert_param(IS_DMA_MEMORY_DATA_SIZE(DMA_InitStruct->DMA_MemoryDataSize));
+  assert_param(IS_DMA_MODE(DMA_InitStruct->DMA_Mode));
+  assert_param(IS_DMA_PRIORITY(DMA_InitStruct->DMA_Priority));
+  assert_param(IS_DMA_FIFO_MODE_STATE(DMA_InitStruct->DMA_FIFOMode));
+  assert_param(IS_DMA_FIFO_THRESHOLD(DMA_InitStruct->DMA_FIFOThreshold));
+  assert_param(IS_DMA_MEMORY_BURST(DMA_InitStruct->DMA_MemoryBurst));
+  assert_param(IS_DMA_PERIPHERAL_BURST(DMA_InitStruct->DMA_PeripheralBurst));
+
+  /*------------------------- DMAy Streamx CR Configuration ------------------*/
+  /* Get the DMAy_Streamx CR value */
+  tmpreg = DMAy_Streamx->CR;
+
+  /* Clear CHSEL, MBURST, PBURST, PL, MSIZE, PSIZE, MINC, PINC, CIRC and DIR bits */
+  tmpreg &= ((uint32_t)~(DMA_SxCR_CHSEL | DMA_SxCR_MBURST | DMA_SxCR_PBURST | \
+                         DMA_SxCR_PL | DMA_SxCR_MSIZE | DMA_SxCR_PSIZE | \
+                         DMA_SxCR_MINC | DMA_SxCR_PINC | DMA_SxCR_CIRC | \
+                         DMA_SxCR_DIR));
+
+  /* Configure DMAy Streamx: */
+  /* Set CHSEL bits according to DMA_CHSEL value */
+  /* Set DIR bits according to DMA_DIR value */
+  /* Set PINC bit according to DMA_PeripheralInc value */
+  /* Set MINC bit according to DMA_MemoryInc value */
+  /* Set PSIZE bits according to DMA_PeripheralDataSize value */
+  /* Set MSIZE bits according to DMA_MemoryDataSize value */
+  /* Set CIRC bit according to DMA_Mode value */
+  /* Set PL bits according to DMA_Priority value */
+  /* Set MBURST bits according to DMA_MemoryBurst value */
+  /* Set PBURST bits according to DMA_PeripheralBurst value */
+  tmpreg |= DMA_InitStruct->DMA_Channel | DMA_InitStruct->DMA_DIR |
+            DMA_InitStruct->DMA_PeripheralInc | DMA_InitStruct->DMA_MemoryInc |
+            DMA_InitStruct->DMA_PeripheralDataSize | DMA_InitStruct->DMA_MemoryDataSize |
+            DMA_InitStruct->DMA_Mode | DMA_InitStruct->DMA_Priority |
+            DMA_InitStruct->DMA_MemoryBurst | DMA_InitStruct->DMA_PeripheralBurst;
+
+  /* Write to DMAy Streamx CR register */
+  DMAy_Streamx->CR = tmpreg;
+
+  /*------------------------- DMAy Streamx FCR Configuration -----------------*/
+  /* Get the DMAy_Streamx FCR value */
+  tmpreg = DMAy_Streamx->FCR;
+
+  /* Clear DMDIS and FTH bits */
+  tmpreg &= (uint32_t)~(DMA_SxFCR_DMDIS | DMA_SxFCR_FTH);
+
+  /* Configure DMAy Streamx FIFO: 
+    Set DMDIS bits according to DMA_FIFOMode value 
+    Set FTH bits according to DMA_FIFOThreshold value */
+  tmpreg |= DMA_InitStruct->DMA_FIFOMode | DMA_InitStruct->DMA_FIFOThreshold;
+
+  /* Write to DMAy Streamx CR */
+  DMAy_Streamx->FCR = tmpreg;
+
+  /*------------------------- DMAy Streamx NDTR Configuration ----------------*/
+  /* Write to DMAy Streamx NDTR register */
+  DMAy_Streamx->NDTR = DMA_InitStruct->DMA_BufferSize;
+
+  /*------------------------- DMAy Streamx PAR Configuration -----------------*/
+  /* Write to DMAy Streamx PAR */
+  DMAy_Streamx->PAR = DMA_InitStruct->DMA_PeripheralBaseAddr;
+
+  /*------------------------- DMAy Streamx M0AR Configuration ----------------*/
+  /* Write to DMAy Streamx M0AR */
+  DMAy_Streamx->M0AR = DMA_InitStruct->DMA_Memory0BaseAddr;
+}
+
+/**
+  * @brief  Fills each DMA_InitStruct member with its default value.
+  * @param  DMA_InitStruct : pointer to a DMA_InitTypeDef structure which will 
+  *         be initialized.
+  * @retval None
+  */
+void DMA_StructInit(DMA_InitTypeDef* DMA_InitStruct)
+{
+  /*-------------- Reset DMA init structure parameters values ----------------*/
+  /* Initialize the DMA_Channel member */
+  DMA_InitStruct->DMA_Channel = 0;
+
+  /* Initialize the DMA_PeripheralBaseAddr member */
+  DMA_InitStruct->DMA_PeripheralBaseAddr = 0;
+
+  /* Initialize the DMA_Memory0BaseAddr member */
+  DMA_InitStruct->DMA_Memory0BaseAddr = 0;
+
+  /* Initialize the DMA_DIR member */
+  DMA_InitStruct->DMA_DIR = DMA_DIR_PeripheralToMemory;
+
+  /* Initialize the DMA_BufferSize member */
+  DMA_InitStruct->DMA_BufferSize = 0;
+
+  /* Initialize the DMA_PeripheralInc member */
+  DMA_InitStruct->DMA_PeripheralInc = DMA_PeripheralInc_Disable;
+
+  /* Initialize the DMA_MemoryInc member */
+  DMA_InitStruct->DMA_MemoryInc = DMA_MemoryInc_Disable;
+
+  /* Initialize the DMA_PeripheralDataSize member */
+  DMA_InitStruct->DMA_PeripheralDataSize = DMA_PeripheralDataSize_Byte;
+
+  /* Initialize the DMA_MemoryDataSize member */
+  DMA_InitStruct->DMA_MemoryDataSize = DMA_MemoryDataSize_Byte;
+
+  /* Initialize the DMA_Mode member */
+  DMA_InitStruct->DMA_Mode = DMA_Mode_Normal;
+
+  /* Initialize the DMA_Priority member */
+  DMA_InitStruct->DMA_Priority = DMA_Priority_Low;
+
+  /* Initialize the DMA_FIFOMode member */
+  DMA_InitStruct->DMA_FIFOMode = DMA_FIFOMode_Disable;
+
+  /* Initialize the DMA_FIFOThreshold member */
+  DMA_InitStruct->DMA_FIFOThreshold = DMA_FIFOThreshold_1QuarterFull;
+
+  /* Initialize the DMA_MemoryBurst member */
+  DMA_InitStruct->DMA_MemoryBurst = DMA_MemoryBurst_Single;
+
+  /* Initialize the DMA_PeripheralBurst member */
+  DMA_InitStruct->DMA_PeripheralBurst = DMA_PeripheralBurst_Single;
+}
+
+/**
+  * @brief  Enables or disables the specified DMAy Streamx.
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+  *         to 7 to select the DMA Stream.
+  * @param  NewState: new state of the DMAy Streamx. 
+  *          This parameter can be: ENABLE or DISABLE.
+  *
+  * @note  This function may be used to perform Pause-Resume operation. When a
+  *        transfer is ongoing, calling this function to disable the Stream will
+  *        cause the transfer to be paused. All configuration registers and the
+  *        number of remaining data will be preserved. When calling again this
+  *        function to re-enable the Stream, the transfer will be resumed from
+  *        the point where it was paused.          
+  *    
+  * @note  After configuring the DMA Stream (DMA_Init() function) and enabling the
+  *        stream, it is recommended to check (or wait until) the DMA Stream is
+  *        effectively enabled. A Stream may remain disabled if a configuration 
+  *        parameter is wrong.
+  *        After disabling a DMA Stream, it is also recommended to check (or wait
+  *        until) the DMA Stream is effectively disabled. If a Stream is disabled 
+  *        while a data transfer is ongoing, the current data will be transferred
+  *        and the Stream will be effectively disabled only after the transfer of
+  *        this single data is finished.            
+  *    
+  * @retval None
+  */
+void DMA_Cmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected DMAy Streamx by setting EN bit */
+    DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_EN;
+  }
+  else
+  {
+    /* Disable the selected DMAy Streamx by clearing EN bit */
+    DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_EN;
+  }
+}
+
+/**
+  * @brief  Configures, when the PINC (Peripheral Increment address mode) bit is
+  *         set, if the peripheral address should be incremented with the data 
+  *         size (configured with PSIZE bits) or by a fixed offset equal to 4
+  *         (32-bit aligned addresses).
+  *   
+  * @note   This function has no effect if the Peripheral Increment mode is disabled.
+  *     
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+  *          to 7 to select the DMA Stream.
+  * @param  DMA_Pincos: specifies the Peripheral increment offset size.
+  *          This parameter can be one of the following values:
+  *            @arg DMA_PINCOS_Psize: Peripheral address increment is done  
+  *                                   accordingly to PSIZE parameter.
+  *            @arg DMA_PINCOS_WordAligned: Peripheral address increment offset is 
+  *                                         fixed to 4 (32-bit aligned addresses). 
+  * @retval None
+  */
+void DMA_PeriphIncOffsetSizeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_Pincos)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+  assert_param(IS_DMA_PINCOS_SIZE(DMA_Pincos));
+
+  /* Check the needed Peripheral increment offset */
+  if(DMA_Pincos != DMA_PINCOS_Psize)
+  {
+    /* Configure DMA_SxCR_PINCOS bit with the input parameter */
+    DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PINCOS;     
+  }
+  else
+  {
+    /* Clear the PINCOS bit: Peripheral address incremented according to PSIZE */
+    DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PINCOS;    
+  }
+}
+
+/**
+  * @brief  Configures, when the DMAy Streamx is disabled, the flow controller for
+  *         the next transactions (Peripheral or Memory).
+  *       
+  * @note   Before enabling this feature, check if the used peripheral supports 
+  *         the Flow Controller mode or not.    
+  *  
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+  *          to 7 to select the DMA Stream.
+  * @param  DMA_FlowCtrl: specifies the DMA flow controller.
+  *          This parameter can be one of the following values:
+  *            @arg DMA_FlowCtrl_Memory: DMAy_Streamx transactions flow controller is 
+  *                                      the DMA controller.
+  *            @arg DMA_FlowCtrl_Peripheral: DMAy_Streamx transactions flow controller 
+  *                                          is the peripheral.    
+  * @retval None
+  */
+void DMA_FlowControllerConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FlowCtrl)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+  assert_param(IS_DMA_FLOW_CTRL(DMA_FlowCtrl));
+
+  /* Check the needed flow controller  */
+  if(DMA_FlowCtrl != DMA_FlowCtrl_Memory)
+  {
+    /* Configure DMA_SxCR_PFCTRL bit with the input parameter */
+    DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_PFCTRL;   
+  }
+  else
+  {
+    /* Clear the PFCTRL bit: Memory is the flow controller */
+    DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_PFCTRL;    
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Group2 Data Counter functions
+ *  @brief   Data Counter functions 
+ *
+@verbatim   
+ ===============================================================================
+                           Data Counter functions
+ ===============================================================================  
+
+  This subsection provides function allowing to configure and read the buffer size
+  (number of data to be transferred). 
+
+  The DMA data counter can be written only when the DMA Stream is disabled 
+  (ie. after transfer complete event).
+
+  The following function can be used to write the Stream data counter value:
+    - void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter);
+
+@note It is advised to use this function rather than DMA_Init() in situations where
+      only the Data buffer needs to be reloaded.
+
+@note If the Source and Destination Data Sizes are different, then the value written in
+      data counter, expressing the number of transfers, is relative to the number of 
+      transfers from the Peripheral point of view.
+      ie. If Memory data size is Word, Peripheral data size is Half-Words, then the value
+      to be configured in the data counter is the number of Half-Words to be transferred
+      from/to the peripheral.
+
+  The DMA data counter can be read to indicate the number of remaining transfers for
+  the relative DMA Stream. This counter is decremented at the end of each data 
+  transfer and when the transfer is complete: 
+   - If Normal mode is selected: the counter is set to 0.
+   - If Circular mode is selected: the counter is reloaded with the initial value
+     (configured before enabling the DMA Stream)
+   
+  The following function can be used to read the Stream data counter value:
+     - uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx);
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Writes the number of data units to be transferred on the DMAy Streamx.
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+  *          to 7 to select the DMA Stream.
+  * @param  Counter: Number of data units to be transferred (from 0 to 65535) 
+  *          Number of data items depends only on the Peripheral data format.
+  *            
+  * @note   If Peripheral data format is Bytes: number of data units is equal 
+  *         to total number of bytes to be transferred.
+  *           
+  * @note   If Peripheral data format is Half-Word: number of data units is  
+  *         equal to total number of bytes to be transferred / 2.
+  *           
+  * @note   If Peripheral data format is Word: number of data units is equal 
+  *         to total  number of bytes to be transferred / 4.
+  *      
+  * @note   In Memory-to-Memory transfer mode, the memory buffer pointed by 
+  *         DMAy_SxPAR register is considered as Peripheral.
+  *      
+  * @retval The number of remaining data units in the current DMAy Streamx transfer.
+  */
+void DMA_SetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx, uint16_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+
+  /* Write the number of data units to be transferred */
+  DMAy_Streamx->NDTR = (uint16_t)Counter;
+}
+
+/**
+  * @brief  Returns the number of remaining data units in the current DMAy Streamx transfer.
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+  *          to 7 to select the DMA Stream.
+  * @retval The number of remaining data units in the current DMAy Streamx transfer.
+  */
+uint16_t DMA_GetCurrDataCounter(DMA_Stream_TypeDef* DMAy_Streamx)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+
+  /* Return the number of remaining data units for DMAy Streamx */
+  return ((uint16_t)(DMAy_Streamx->NDTR));
+}
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Group3 Double Buffer mode functions
+ *  @brief   Double Buffer mode functions 
+ *
+@verbatim   
+ ===============================================================================
+                         Double Buffer mode functions
+ ===============================================================================  
+
+  This subsection provides function allowing to configure and control the double 
+  buffer mode parameters.
+  
+  The Double Buffer mode can be used only when Circular mode is enabled.
+  The Double Buffer mode cannot be used when transferring data from Memory to Memory.
+  
+  The Double Buffer mode allows to set two different Memory addresses from/to which
+  the DMA controller will access alternatively (after completing transfer to/from target
+  memory 0, it will start transfer to/from target memory 1).
+  This allows to reduce software overhead for double buffering and reduce the CPU
+  access time.
+
+  Two functions must be called before calling the DMA_Init() function:
+   - void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
+                                uint32_t DMA_CurrentMemory);
+   - void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState);
+   
+  DMA_DoubleBufferModeConfig() is called to configure the Memory 1 base address and the first
+  Memory target from/to which the transfer will start after enabling the DMA Stream.
+  Then DMA_DoubleBufferModeCmd() must be called to enable the Double Buffer mode (or disable 
+  it when it should not be used).
+  
+   
+  Two functions can be called dynamically when the transfer is ongoing (or when the DMA Stream is 
+  stopped) to modify on of the target Memories addresses or to check wich Memory target is currently
+   used:
+    - void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
+                            uint32_t DMA_MemoryTarget);
+    - uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx);
+
+  DMA_MemoryTargetConfig() can be called to modify the base address of one of the two target Memories.
+  The Memory of which the base address will be modified must not be currently be used by the DMA Stream
+  (ie. if the DMA Stream is currently transferring from Memory 1 then you can only modify base address
+  of target Memory 0 and vice versa).
+  To check this condition, it is recommended to use the function DMA_GetCurrentMemoryTarget() which
+  returns the index of the Memory target currently in use by the DMA Stream.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Configures, when the DMAy Streamx is disabled, the double buffer mode 
+  *         and the current memory target.
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+  *          to 7 to select the DMA Stream.
+  * @param  Memory1BaseAddr: the base address of the second buffer (Memory 1)  
+  * @param  DMA_CurrentMemory: specifies which memory will be first buffer for
+  *         the transactions when the Stream will be enabled. 
+  *          This parameter can be one of the following values:
+  *            @arg DMA_Memory_0: Memory 0 is the current buffer.
+  *            @arg DMA_Memory_1: Memory 1 is the current buffer.  
+  *       
+  * @note   Memory0BaseAddr is set by the DMA structure configuration in DMA_Init().
+  *   
+  * @retval None
+  */
+void DMA_DoubleBufferModeConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t Memory1BaseAddr,
+                                uint32_t DMA_CurrentMemory)
+{  
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+  assert_param(IS_DMA_CURRENT_MEM(DMA_CurrentMemory));
+
+  if (DMA_CurrentMemory != DMA_Memory_0)
+  {
+    /* Set Memory 1 as current memory address */
+    DMAy_Streamx->CR |= (uint32_t)(DMA_SxCR_CT);    
+  }
+  else
+  {
+    /* Set Memory 0 as current memory address */
+    DMAy_Streamx->CR &= ~(uint32_t)(DMA_SxCR_CT);    
+  }
+
+  /* Write to DMAy Streamx M1AR */
+  DMAy_Streamx->M1AR = Memory1BaseAddr;
+}
+
+/**
+  * @brief  Enables or disables the double buffer mode for the selected DMA stream.
+  * @note   This function can be called only when the DMA Stream is disabled.  
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+  *          to 7 to select the DMA Stream.
+  * @param  NewState: new state of the DMAy Streamx double buffer mode. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DMA_DoubleBufferModeCmd(DMA_Stream_TypeDef* DMAy_Streamx, FunctionalState NewState)
+{  
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Configure the Double Buffer mode */
+  if (NewState != DISABLE)
+  {
+    /* Enable the Double buffer mode */
+    DMAy_Streamx->CR |= (uint32_t)DMA_SxCR_DBM;
+  }
+  else
+  {
+    /* Disable the Double buffer mode */
+    DMAy_Streamx->CR &= ~(uint32_t)DMA_SxCR_DBM;
+  }
+}
+
+/**
+  * @brief  Configures the Memory address for the next buffer transfer in double
+  *         buffer mode (for dynamic use). This function can be called when the
+  *         DMA Stream is enabled and when the transfer is ongoing.  
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+  *          to 7 to select the DMA Stream.
+  * @param  MemoryBaseAddr: The base address of the target memory buffer
+  * @param  DMA_MemoryTarget: Next memory target to be used. 
+  *         This parameter can be one of the following values:
+  *            @arg DMA_Memory_0: To use the memory address 0
+  *            @arg DMA_Memory_1: To use the memory address 1
+  * 
+  * @note    It is not allowed to modify the Base Address of a target Memory when
+  *          this target is involved in the current transfer. ie. If the DMA Stream
+  *          is currently transferring to/from Memory 1, then it not possible to
+  *          modify Base address of Memory 1, but it is possible to modify Base
+  *          address of Memory 0.
+  *          To know which Memory is currently used, you can use the function
+  *          DMA_GetCurrentMemoryTarget().             
+  *  
+  * @retval None
+  */
+void DMA_MemoryTargetConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t MemoryBaseAddr,
+                           uint32_t DMA_MemoryTarget)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+  assert_param(IS_DMA_CURRENT_MEM(DMA_MemoryTarget));
+    
+  /* Check the Memory target to be configured */
+  if (DMA_MemoryTarget != DMA_Memory_0)
+  {
+    /* Write to DMAy Streamx M1AR */
+    DMAy_Streamx->M1AR = MemoryBaseAddr;    
+  }  
+  else
+  {
+    /* Write to DMAy Streamx M0AR */
+    DMAy_Streamx->M0AR = MemoryBaseAddr;  
+  }
+}
+
+/**
+  * @brief  Returns the current memory target used by double buffer transfer.
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+  *          to 7 to select the DMA Stream.
+  * @retval The memory target number: 0 for Memory0 or 1 for Memory1. 
+  */
+uint32_t DMA_GetCurrentMemoryTarget(DMA_Stream_TypeDef* DMAy_Streamx)
+{
+  uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+
+  /* Get the current memory target */
+  if ((DMAy_Streamx->CR & DMA_SxCR_CT) != 0)
+  {
+    /* Current memory buffer used is Memory 1 */
+    tmp = 1;
+  }  
+  else
+  {
+    /* Current memory buffer used is Memory 0 */
+    tmp = 0;    
+  }
+  return tmp;
+}
+/**
+  * @}
+  */
+
+/** @defgroup DMA_Group4 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                  Interrupts and flags management functions
+ ===============================================================================  
+
+  This subsection provides functions allowing to
+   - Check the DMA enable status
+   - Check the FIFO status 
+   - Configure the DMA Interrupts sources and check or clear the flags or pending bits status.   
+   
+ 1. DMA Enable status:
+   After configuring the DMA Stream (DMA_Init() function) and enabling the stream,
+   it is recommended to check (or wait until) the DMA Stream is effectively enabled.
+   A Stream may remain disabled if a configuration parameter is wrong.
+   After disabling a DMA Stream, it is also recommended to check (or wait until) the DMA
+   Stream is effectively disabled. If a Stream is disabled while a data transfer is ongoing, 
+   the current data will be transferred and the Stream will be effectively disabled only after
+   this data transfer completion.
+   To monitor this state it is possible to use the following function:
+     - FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx); 
+ 
+ 2. FIFO Status:
+   It is possible to monitor the FIFO status when a transfer is ongoing using the following 
+   function:
+     - uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx); 
+ 
+ 3. DMA Interrupts and Flags:
+  The user should identify which mode will be used in his application to manage the
+  DMA controller events: Polling mode or Interrupt mode. 
+    
+  Polling Mode
+  =============
+    Each DMA stream can be managed through 4 event Flags:
+    (x : DMA Stream number )
+       1. DMA_FLAG_FEIFx  : to indicate that a FIFO Mode Transfer Error event occurred.
+       2. DMA_FLAG_DMEIFx : to indicate that a Direct Mode Transfer Error event occurred.
+       3. DMA_FLAG_TEIFx  : to indicate that a Transfer Error event occurred.
+       4. DMA_FLAG_HTIFx  : to indicate that a Half-Transfer Complete event occurred.
+       5. DMA_FLAG_TCIFx  : to indicate that a Transfer Complete event occurred .       
+
+   In this Mode it is advised to use the following functions:
+      - FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
+      - void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG);
+
+  Interrupt Mode
+  ===============
+    Each DMA Stream can be managed through 4 Interrupts:
+
+    Interrupt Source
+    ----------------
+       1. DMA_IT_FEIFx  : specifies the interrupt source for the  FIFO Mode Transfer Error event.
+       2. DMA_IT_DMEIFx : specifies the interrupt source for the Direct Mode Transfer Error event.
+       3. DMA_IT_TEIFx  : specifies the interrupt source for the Transfer Error event.
+       4. DMA_IT_HTIFx  : specifies the interrupt source for the Half-Transfer Complete event.
+       5. DMA_IT_TCIFx  : specifies the interrupt source for the a Transfer Complete event. 
+     
+  In this Mode it is advised to use the following functions:
+     - void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState);
+     - ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
+     - void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT);
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the status of EN bit for the specified DMAy Streamx.
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+  *          to 7 to select the DMA Stream.
+  *   
+  * @note    After configuring the DMA Stream (DMA_Init() function) and enabling
+  *          the stream, it is recommended to check (or wait until) the DMA Stream
+  *          is effectively enabled. A Stream may remain disabled if a configuration
+  *          parameter is wrong.
+  *          After disabling a DMA Stream, it is also recommended to check (or wait 
+  *          until) the DMA Stream is effectively disabled. If a Stream is disabled
+  *          while a data transfer is ongoing, the current data will be transferred
+  *          and the Stream will be effectively disabled only after the transfer
+  *          of this single data is finished.  
+  *      
+  * @retval Current state of the DMAy Streamx (ENABLE or DISABLE).
+  */
+FunctionalState DMA_GetCmdStatus(DMA_Stream_TypeDef* DMAy_Streamx)
+{
+  FunctionalState state = DISABLE;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+
+  if ((DMAy_Streamx->CR & (uint32_t)DMA_SxCR_EN) != 0)
+  {
+    /* The selected DMAy Streamx EN bit is set (DMA is still transferring) */
+    state = ENABLE;
+  }
+  else
+  {
+    /* The selected DMAy Streamx EN bit is cleared (DMA is disabled and 
+        all transfers are complete) */
+    state = DISABLE;
+  }
+  return state;
+}
+
+/**
+  * @brief  Returns the current DMAy Streamx FIFO filled level.
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0 
+  *         to 7 to select the DMA Stream.
+  * @retval The FIFO filling state.
+  *           - DMA_FIFOStatus_Less1QuarterFull: when FIFO is less than 1 quarter-full 
+  *                                               and not empty.
+  *           - DMA_FIFOStatus_1QuarterFull: if more than 1 quarter-full.
+  *           - DMA_FIFOStatus_HalfFull: if more than 1 half-full.
+  *           - DMA_FIFOStatus_3QuartersFull: if more than 3 quarters-full.
+  *           - DMA_FIFOStatus_Empty: when FIFO is empty
+  *           - DMA_FIFOStatus_Full: when FIFO is full
+  */
+uint32_t DMA_GetFIFOStatus(DMA_Stream_TypeDef* DMAy_Streamx)
+{
+  uint32_t tmpreg = 0;
+ 
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+  
+  /* Get the FIFO level bits */
+  tmpreg = (uint32_t)((DMAy_Streamx->FCR & DMA_SxFCR_FS));
+  
+  return tmpreg;
+}
+
+/**
+  * @brief  Checks whether the specified DMAy Streamx flag is set or not.
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+  *          to 7 to select the DMA Stream.
+  * @param  DMA_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg DMA_FLAG_TCIFx:  Streamx transfer complete flag
+  *            @arg DMA_FLAG_HTIFx:  Streamx half transfer complete flag
+  *            @arg DMA_FLAG_TEIFx:  Streamx transfer error flag
+  *            @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag
+  *            @arg DMA_FLAG_FEIFx:  Streamx FIFO error flag
+  *         Where x can be 0 to 7 to select the DMA Stream.
+  * @retval The new state of DMA_FLAG (SET or RESET).
+  */
+FlagStatus DMA_GetFlagStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  DMA_TypeDef* DMAy;
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+  assert_param(IS_DMA_GET_FLAG(DMA_FLAG));
+
+  /* Determine the DMA to which belongs the stream */
+  if (DMAy_Streamx < DMA2_Stream0)
+  {
+    /* DMAy_Streamx belongs to DMA1 */
+    DMAy = DMA1; 
+  } 
+  else 
+  {
+    /* DMAy_Streamx belongs to DMA2 */
+    DMAy = DMA2; 
+  }
+
+  /* Check if the flag is in HISR or LISR */
+  if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
+  {
+    /* Get DMAy HISR register value */
+    tmpreg = DMAy->HISR;
+  }
+  else
+  {
+    /* Get DMAy LISR register value */
+    tmpreg = DMAy->LISR;
+  }   
+ 
+  /* Mask the reserved bits */
+  tmpreg &= (uint32_t)RESERVED_MASK;
+
+  /* Check the status of the specified DMA flag */
+  if ((tmpreg & DMA_FLAG) != (uint32_t)RESET)
+  {
+    /* DMA_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DMA_FLAG is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the DMA_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DMAy Streamx's pending flags.
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+  *          to 7 to select the DMA Stream.
+  * @param  DMA_FLAG: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_FLAG_TCIFx:  Streamx transfer complete flag
+  *            @arg DMA_FLAG_HTIFx:  Streamx half transfer complete flag
+  *            @arg DMA_FLAG_TEIFx:  Streamx transfer error flag
+  *            @arg DMA_FLAG_DMEIFx: Streamx direct mode error flag
+  *            @arg DMA_FLAG_FEIFx:  Streamx FIFO error flag
+  *         Where x can be 0 to 7 to select the DMA Stream.   
+  * @retval None
+  */
+void DMA_ClearFlag(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_FLAG)
+{
+  DMA_TypeDef* DMAy;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+  assert_param(IS_DMA_CLEAR_FLAG(DMA_FLAG));
+
+  /* Determine the DMA to which belongs the stream */
+  if (DMAy_Streamx < DMA2_Stream0)
+  {
+    /* DMAy_Streamx belongs to DMA1 */
+    DMAy = DMA1; 
+  } 
+  else 
+  {
+    /* DMAy_Streamx belongs to DMA2 */
+    DMAy = DMA2; 
+  }
+
+  /* Check if LIFCR or HIFCR register is targeted */
+  if ((DMA_FLAG & HIGH_ISR_MASK) != (uint32_t)RESET)
+  {
+    /* Set DMAy HIFCR register clear flag bits */
+    DMAy->HIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
+  }
+  else 
+  {
+    /* Set DMAy LIFCR register clear flag bits */
+    DMAy->LIFCR = (uint32_t)(DMA_FLAG & RESERVED_MASK);
+  }    
+}
+
+/**
+  * @brief  Enables or disables the specified DMAy Streamx interrupts.
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+  *          to 7 to select the DMA Stream.
+  * @param DMA_IT: specifies the DMA interrupt sources to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TC:  Transfer complete interrupt mask
+  *            @arg DMA_IT_HT:  Half transfer complete interrupt mask
+  *            @arg DMA_IT_TE:  Transfer error interrupt mask
+  *            @arg DMA_IT_FE:  FIFO error interrupt mask
+  * @param  NewState: new state of the specified DMA interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void DMA_ITConfig(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+  assert_param(IS_DMA_CONFIG_IT(DMA_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Check if the DMA_IT parameter contains a FIFO interrupt */
+  if ((DMA_IT & DMA_IT_FE) != 0)
+  {
+    if (NewState != DISABLE)
+    {
+      /* Enable the selected DMA FIFO interrupts */
+      DMAy_Streamx->FCR |= (uint32_t)DMA_IT_FE;
+    }    
+    else 
+    {
+      /* Disable the selected DMA FIFO interrupts */
+      DMAy_Streamx->FCR &= ~(uint32_t)DMA_IT_FE;  
+    }
+  }
+
+  /* Check if the DMA_IT parameter contains a Transfer interrupt */
+  if (DMA_IT != DMA_IT_FE)
+  {
+    if (NewState != DISABLE)
+    {
+      /* Enable the selected DMA transfer interrupts */
+      DMAy_Streamx->CR |= (uint32_t)(DMA_IT  & TRANSFER_IT_ENABLE_MASK);
+    }
+    else
+    {
+      /* Disable the selected DMA transfer interrupts */
+      DMAy_Streamx->CR &= ~(uint32_t)(DMA_IT & TRANSFER_IT_ENABLE_MASK);
+    }    
+  }
+}
+
+/**
+  * @brief  Checks whether the specified DMAy Streamx interrupt has occurred or not.
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+  *          to 7 to select the DMA Stream.
+  * @param  DMA_IT: specifies the DMA interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg DMA_IT_TCIFx:  Streamx transfer complete interrupt
+  *            @arg DMA_IT_HTIFx:  Streamx half transfer complete interrupt
+  *            @arg DMA_IT_TEIFx:  Streamx transfer error interrupt
+  *            @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt
+  *            @arg DMA_IT_FEIFx:  Streamx FIFO error interrupt
+  *         Where x can be 0 to 7 to select the DMA Stream.
+  * @retval The new state of DMA_IT (SET or RESET).
+  */
+ITStatus DMA_GetITStatus(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
+{
+  ITStatus bitstatus = RESET;
+  DMA_TypeDef* DMAy;
+  uint32_t tmpreg = 0, enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+  assert_param(IS_DMA_GET_IT(DMA_IT));
+ 
+  /* Determine the DMA to which belongs the stream */
+  if (DMAy_Streamx < DMA2_Stream0)
+  {
+    /* DMAy_Streamx belongs to DMA1 */
+    DMAy = DMA1; 
+  } 
+  else 
+  {
+    /* DMAy_Streamx belongs to DMA2 */
+    DMAy = DMA2; 
+  }
+
+  /* Check if the interrupt enable bit is in the CR or FCR register */
+  if ((DMA_IT & TRANSFER_IT_MASK) != (uint32_t)RESET)
+  {
+    /* Get the interrupt enable position mask in CR register */
+    tmpreg = (uint32_t)((DMA_IT >> 11) & TRANSFER_IT_ENABLE_MASK);   
+    
+    /* Check the enable bit in CR register */
+    enablestatus = (uint32_t)(DMAy_Streamx->CR & tmpreg);
+  }
+  else 
+  {
+    /* Check the enable bit in FCR register */
+    enablestatus = (uint32_t)(DMAy_Streamx->FCR & DMA_IT_FE); 
+  }
+ 
+  /* Check if the interrupt pending flag is in LISR or HISR */
+  if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
+  {
+    /* Get DMAy HISR register value */
+    tmpreg = DMAy->HISR ;
+  }
+  else
+  {
+    /* Get DMAy LISR register value */
+    tmpreg = DMAy->LISR ;
+  } 
+
+  /* mask all reserved bits */
+  tmpreg &= (uint32_t)RESERVED_MASK;
+
+  /* Check the status of the specified DMA interrupt */
+  if (((tmpreg & DMA_IT) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+  {
+    /* DMA_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* DMA_IT is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the DMA_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the DMAy Streamx's interrupt pending bits.
+  * @param  DMAy_Streamx: where y can be 1 or 2 to select the DMA and x can be 0
+  *          to 7 to select the DMA Stream.
+  * @param  DMA_IT: specifies the DMA interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg DMA_IT_TCIFx:  Streamx transfer complete interrupt
+  *            @arg DMA_IT_HTIFx:  Streamx half transfer complete interrupt
+  *            @arg DMA_IT_TEIFx:  Streamx transfer error interrupt
+  *            @arg DMA_IT_DMEIFx: Streamx direct mode error interrupt
+  *            @arg DMA_IT_FEIFx:  Streamx FIFO error interrupt
+  *         Where x can be 0 to 7 to select the DMA Stream.
+  * @retval None
+  */
+void DMA_ClearITPendingBit(DMA_Stream_TypeDef* DMAy_Streamx, uint32_t DMA_IT)
+{
+  DMA_TypeDef* DMAy;
+
+  /* Check the parameters */
+  assert_param(IS_DMA_ALL_PERIPH(DMAy_Streamx));
+  assert_param(IS_DMA_CLEAR_IT(DMA_IT));
+
+  /* Determine the DMA to which belongs the stream */
+  if (DMAy_Streamx < DMA2_Stream0)
+  {
+    /* DMAy_Streamx belongs to DMA1 */
+    DMAy = DMA1; 
+  } 
+  else 
+  {
+    /* DMAy_Streamx belongs to DMA2 */
+    DMAy = DMA2; 
+  }
+
+  /* Check if LIFCR or HIFCR register is targeted */
+  if ((DMA_IT & HIGH_ISR_MASK) != (uint32_t)RESET)
+  {
+    /* Set DMAy HIFCR register clear interrupt bits */
+    DMAy->HIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
+  }
+  else 
+  {
+    /* Set DMAy LIFCR register clear interrupt bits */
+    DMAy->LIFCR = (uint32_t)(DMA_IT & RESERVED_MASK);
+  }   
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c
new file mode 100644
index 0000000000..6fceea7e92
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_exti.c
@@ -0,0 +1,306 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_exti.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the EXTI peripheral:           
+  *           - Initialization and Configuration
+  *           - Interrupts and flags management
+  *
+  *  @verbatim  
+  *  
+  *          ===================================================================
+  *                                     EXTI features
+  *          ===================================================================
+  *    
+  *          External interrupt/event lines are mapped as following:
+  *            1- All available GPIO pins are connected to the 16 external 
+  *               interrupt/event lines from EXTI0 to EXTI15.
+  *            2- EXTI line 16 is connected to the PVD Output
+  *            3- EXTI line 17 is connected to the RTC Alarm event
+  *            4- EXTI line 18 is connected to the USB OTG FS Wakeup from suspend event                                    
+  *            5- EXTI line 19 is connected to the Ethernet Wakeup event
+  *            6- EXTI line 20 is connected to the USB OTG HS (configured in FS) Wakeup event 
+  *            7- EXTI line 21 is connected to the RTC Tamper and Time Stamp events                                               
+  *            8- EXTI line 22 is connected to the RTC Wakeup event
+  *        
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================  
+  *              
+  *          In order to use an I/O pin as an external interrupt source, follow
+  *          steps below:
+  *            1- Configure the I/O in input mode using GPIO_Init()
+  *            2- Select the input source pin for the EXTI line using SYSCFG_EXTILineConfig()
+  *            3- Select the mode(interrupt, event) and configure the trigger 
+  *               selection (Rising, falling or both) using EXTI_Init()
+  *            4- Configure NVIC IRQ channel mapped to the EXTI line using NVIC_Init()
+  *   
+  *  @note  SYSCFG APB clock must be enabled to get write access to SYSCFG_EXTICRx
+  *         registers using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+  *          
+  *  @endverbatim                  
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_exti.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup EXTI 
+  * @brief EXTI driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#define EXTI_LINENONE    ((uint32_t)0x00000)  /* No interrupt selected */
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup EXTI_Private_Functions
+  * @{
+  */
+
+/** @defgroup EXTI_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                  Initialization and Configuration functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the EXTI peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void EXTI_DeInit(void)
+{
+  EXTI->IMR = 0x00000000;
+  EXTI->EMR = 0x00000000;
+  EXTI->RTSR = 0x00000000;
+  EXTI->FTSR = 0x00000000;
+  EXTI->PR = 0x007FFFFF;
+}
+
+/**
+  * @brief  Initializes the EXTI peripheral according to the specified
+  *         parameters in the EXTI_InitStruct.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure
+  *         that contains the configuration information for the EXTI peripheral.
+  * @retval None
+  */
+void EXTI_Init(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+  uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_MODE(EXTI_InitStruct->EXTI_Mode));
+  assert_param(IS_EXTI_TRIGGER(EXTI_InitStruct->EXTI_Trigger));
+  assert_param(IS_EXTI_LINE(EXTI_InitStruct->EXTI_Line));  
+  assert_param(IS_FUNCTIONAL_STATE(EXTI_InitStruct->EXTI_LineCmd));
+
+  tmp = (uint32_t)EXTI_BASE;
+     
+  if (EXTI_InitStruct->EXTI_LineCmd != DISABLE)
+  {
+    /* Clear EXTI line configuration */
+    EXTI->IMR &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->EMR &= ~EXTI_InitStruct->EXTI_Line;
+    
+    tmp += EXTI_InitStruct->EXTI_Mode;
+
+    *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+
+    /* Clear Rising Falling edge configuration */
+    EXTI->RTSR &= ~EXTI_InitStruct->EXTI_Line;
+    EXTI->FTSR &= ~EXTI_InitStruct->EXTI_Line;
+    
+    /* Select the trigger for the selected external interrupts */
+    if (EXTI_InitStruct->EXTI_Trigger == EXTI_Trigger_Rising_Falling)
+    {
+      /* Rising Falling edge */
+      EXTI->RTSR |= EXTI_InitStruct->EXTI_Line;
+      EXTI->FTSR |= EXTI_InitStruct->EXTI_Line;
+    }
+    else
+    {
+      tmp = (uint32_t)EXTI_BASE;
+      tmp += EXTI_InitStruct->EXTI_Trigger;
+
+      *(__IO uint32_t *) tmp |= EXTI_InitStruct->EXTI_Line;
+    }
+  }
+  else
+  {
+    tmp += EXTI_InitStruct->EXTI_Mode;
+
+    /* Disable the selected external lines */
+    *(__IO uint32_t *) tmp &= ~EXTI_InitStruct->EXTI_Line;
+  }
+}
+
+/**
+  * @brief  Fills each EXTI_InitStruct member with its reset value.
+  * @param  EXTI_InitStruct: pointer to a EXTI_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void EXTI_StructInit(EXTI_InitTypeDef* EXTI_InitStruct)
+{
+  EXTI_InitStruct->EXTI_Line = EXTI_LINENONE;
+  EXTI_InitStruct->EXTI_Mode = EXTI_Mode_Interrupt;
+  EXTI_InitStruct->EXTI_Trigger = EXTI_Trigger_Falling;
+  EXTI_InitStruct->EXTI_LineCmd = DISABLE;
+}
+
+/**
+  * @brief  Generates a Software interrupt on selected EXTI line.
+  * @param  EXTI_Line: specifies the EXTI line on which the software interrupt
+  *         will be generated.
+  *         This parameter can be any combination of EXTI_Linex where x can be (0..22)
+  * @retval None
+  */
+void EXTI_GenerateSWInterrupt(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+  
+  EXTI->SWIER |= EXTI_Line;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup EXTI_Group2 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                  Interrupts and flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified EXTI line flag is set or not.
+  * @param  EXTI_Line: specifies the EXTI line flag to check.
+  *          This parameter can be EXTI_Linex where x can be(0..22)
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+FlagStatus EXTI_GetFlagStatus(uint32_t EXTI_Line)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+  
+  if ((EXTI->PR & EXTI_Line) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the EXTI's line pending flags.
+  * @param  EXTI_Line: specifies the EXTI lines flags to clear.
+  *          This parameter can be any combination of EXTI_Linex where x can be (0..22)
+  * @retval None
+  */
+void EXTI_ClearFlag(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+  
+  EXTI->PR = EXTI_Line;
+}
+
+/**
+  * @brief  Checks whether the specified EXTI line is asserted or not.
+  * @param  EXTI_Line: specifies the EXTI line to check.
+  *          This parameter can be EXTI_Linex where x can be(0..22)
+  * @retval The new state of EXTI_Line (SET or RESET).
+  */
+ITStatus EXTI_GetITStatus(uint32_t EXTI_Line)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+  /* Check the parameters */
+  assert_param(IS_GET_EXTI_LINE(EXTI_Line));
+  
+  enablestatus =  EXTI->IMR & EXTI_Line;
+  if (((EXTI->PR & EXTI_Line) != (uint32_t)RESET) && (enablestatus != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the EXTI's line pending bits.
+  * @param  EXTI_Line: specifies the EXTI lines to clear.
+  *          This parameter can be any combination of EXTI_Linex where x can be (0..22)
+  * @retval None
+  */
+void EXTI_ClearITPendingBit(uint32_t EXTI_Line)
+{
+  /* Check the parameters */
+  assert_param(IS_EXTI_LINE(EXTI_Line));
+  
+  EXTI->PR = EXTI_Line;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c
new file mode 100644
index 0000000000..91319f3ed7
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_flash.c
@@ -0,0 +1,1054 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_flash.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the FLASH peripheral:
+  *            - FLASH Interface configuration
+  *            - FLASH Memory Programming
+  *            - Option Bytes Programming
+  *            - Interrupts and flags management
+  *  
+  *  @verbatim
+  *  
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *                           
+  *          This driver provides functions to configure and program the FLASH 
+  *          memory of all STM32F4xx devices.
+  *          These functions are split in 4 groups:
+  * 
+  *           1. FLASH Interface configuration functions: this group includes the
+  *              management of the following features:
+  *                    - Set the latency
+  *                    - Enable/Disable the prefetch buffer
+  *                    - Enable/Disable the Instruction cache and the Data cache
+  *                    - Reset the Instruction cache and the Data cache
+  *  
+  *           2. FLASH Memory Programming functions: this group includes all needed
+  *              functions to erase and program the main memory:
+  *                    - Lock and Unlock the FLASH interface
+  *                    - Erase function: Erase sector, erase all sectors
+  *                    - Program functions: byte, half word, word and double word
+  *  
+  *           3. Option Bytes Programming functions: this group includes all needed
+  *              functions to manage the Option Bytes:
+  *                    - Set/Reset the write protection
+  *                    - Set the Read protection Level
+  *                    - Set the BOR level
+  *                    - Program the user Option Bytes
+  *                    - Launch the Option Bytes loader
+  *  
+  *           4. Interrupts and flags management functions: this group 
+  *              includes all needed functions to:
+  *                    - Enable/Disable the FLASH interrupt sources
+  *                    - Get flags status
+  *                    - Clear flags
+  *                    - Get FLASH operation status
+  *                    - Wait for last FLASH operation
+  * 
+  *  @endverbatim
+  *                      
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_flash.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup FLASH 
+  * @brief FLASH driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/ 
+#define SECTOR_MASK               ((uint32_t)0xFFFFFF07)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup FLASH_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup FLASH_Group1 FLASH Interface configuration functions
+  *  @brief   FLASH Interface configuration functions 
+ *
+
+@verbatim   
+ ===============================================================================
+                       FLASH Interface configuration functions
+ ===============================================================================
+
+   This group includes the following functions:
+    - void FLASH_SetLatency(uint32_t FLASH_Latency)
+       To correctly read data from FLASH memory, the number of wait states (LATENCY) 
+       must be correctly programmed according to the frequency of the CPU clock 
+      (HCLK) and the supply voltage of the device.
+ +-------------------------------------------------------------------------------------+     
+ | Latency       |                HCLK clock frequency (MHz)                           |
+ |               |---------------------------------------------------------------------|     
+ |               | voltage range  | voltage range  | voltage range   | voltage range   |
+ |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
+ |---------------|----------------|----------------|-----------------|-----------------|              
+ |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 18   |0 < HCLK <= 16   |
+ |---------------|----------------|----------------|-----------------|-----------------|   
+ |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36  |16 < HCLK <= 32  | 
+ |---------------|----------------|----------------|-----------------|-----------------|   
+ |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54  |32 < HCLK <= 48  |
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72  |48 < HCLK <= 64  |
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |4WS(5CPU cycle)|      NA        |96 < HCLK <= 120|72 < HCLK <= 90  |64 < HCLK <= 80  |
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |5WS(6CPU cycle)|      NA        |      NA        |90 < HCLK <= 108 |80 < HCLK <= 96  | 
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |6WS(7CPU cycle)|      NA        |      NA        |108 < HCLK <= 120|96 < HCLK <= 112 | 
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |7WS(8CPU cycle)|      NA        |      NA        |     NA          |112 < HCLK <= 120| 
+ |***************|****************|****************|*****************|*****************|*****************************+
+ |               | voltage range  | voltage range  | voltage range   | voltage range   | voltage range 2.7 V - 3.6 V |
+ |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   | with External Vpp = 9V      |
+ |---------------|----------------|----------------|-----------------|-----------------|-----------------------------| 
+ |Max Parallelism|      x32       |               x16                |       x8        |          x64                |              
+ |---------------|----------------|----------------|-----------------|-----------------|-----------------------------|   
+ |PSIZE[1:0]     |      10        |               01                 |       00        |           11                |
+ +-------------------------------------------------------------------------------------------------------------------+  
+    
+    - void FLASH_PrefetchBufferCmd(FunctionalState NewState)
+    - void FLASH_InstructionCacheCmd(FunctionalState NewState)
+    - void FLASH_DataCacheCmd(FunctionalState NewState)
+    - void FLASH_InstructionCacheReset(void)
+    - void FLASH_DataCacheReset(void)
+   
+   The unlock sequence is not needed for these functions.
+ 
+@endverbatim
+  * @{
+  */
+ 
+/**
+  * @brief  Sets the code latency value.
+  * @param  FLASH_Latency: specifies the FLASH Latency value.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_Latency_0: FLASH Zero Latency cycle
+  *            @arg FLASH_Latency_1: FLASH One Latency cycle
+  *            @arg FLASH_Latency_2: FLASH Two Latency cycles
+  *            @arg FLASH_Latency_3: FLASH Three Latency cycles
+  *            @arg FLASH_Latency_4: FLASH Four Latency cycles 
+  *            @arg FLASH_Latency_5: FLASH Five Latency cycles 
+  *            @arg FLASH_Latency_6: FLASH Six Latency cycles
+  *            @arg FLASH_Latency_7: FLASH Seven Latency cycles      
+  * @retval None
+  */
+void FLASH_SetLatency(uint32_t FLASH_Latency)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_LATENCY(FLASH_Latency));
+  
+  /* Perform Byte access to FLASH_ACR[8:0] to set the Latency value */
+  *(__IO uint8_t *)ACR_BYTE0_ADDRESS = (uint8_t)FLASH_Latency;
+}
+
+/**
+  * @brief  Enables or disables the Prefetch Buffer.
+  * @param  NewState: new state of the Prefetch Buffer.
+  *          This parameter  can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FLASH_PrefetchBufferCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  /* Enable or disable the Prefetch Buffer */
+  if(NewState != DISABLE)
+  {
+    FLASH->ACR |= FLASH_ACR_PRFTEN;
+  }
+  else
+  {
+    FLASH->ACR &= (~FLASH_ACR_PRFTEN);
+  }
+}
+
+/**
+  * @brief  Enables or disables the Instruction Cache feature.
+  * @param  NewState: new state of the Instruction Cache.
+  *          This parameter  can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FLASH_InstructionCacheCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if(NewState != DISABLE)
+  {
+    FLASH->ACR |= FLASH_ACR_ICEN;
+  }
+  else
+  {
+    FLASH->ACR &= (~FLASH_ACR_ICEN);
+  }
+}
+
+/**
+  * @brief  Enables or disables the Data Cache feature.
+  * @param  NewState: new state of the Data Cache.
+  *          This parameter  can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FLASH_DataCacheCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if(NewState != DISABLE)
+  {
+    FLASH->ACR |= FLASH_ACR_DCEN;
+  }
+  else
+  {
+    FLASH->ACR &= (~FLASH_ACR_DCEN);
+  }
+}
+
+/**
+  * @brief  Resets the Instruction Cache.
+  * @note   This function must be used only when the Instruction Cache is disabled.  
+  * @param  None
+  * @retval None
+  */
+void FLASH_InstructionCacheReset(void)
+{
+  FLASH->ACR |= FLASH_ACR_ICRST;
+}
+
+/**
+  * @brief  Resets the Data Cache.
+  * @note   This function must be used only when the Data Cache is disabled.  
+  * @param  None
+  * @retval None
+  */
+void FLASH_DataCacheReset(void)
+{
+  FLASH->ACR |= FLASH_ACR_DCRST;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Group2 FLASH Memory Programming functions
+ *  @brief   FLASH Memory Programming functions
+ *
+@verbatim   
+ ===============================================================================
+                      FLASH Memory Programming functions
+ ===============================================================================   
+
+   This group includes the following functions:
+    - void FLASH_Unlock(void)
+    - void FLASH_Lock(void)
+    - FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
+    - FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
+    - FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
+    - FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+    - FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
+    - FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
+   
+   Any operation of erase or program should follow these steps:
+   1. Call the FLASH_Unlock() function to enable the FLASH control register access
+
+   2. Call the desired function to erase sector(s) or program data
+
+   3. Call the FLASH_Lock() function to disable the FLASH control register access
+      (recommended to protect the FLASH memory against possible unwanted operation)
+    
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlocks the FLASH control register access
+  * @param  None
+  * @retval None
+  */
+void FLASH_Unlock(void)
+{
+  if((FLASH->CR & FLASH_CR_LOCK) != RESET)
+  {
+    /* Authorize the FLASH Registers access */
+    FLASH->KEYR = FLASH_KEY1;
+    FLASH->KEYR = FLASH_KEY2;
+  }  
+}
+
+/**
+  * @brief  Locks the FLASH control register access
+  * @param  None
+  * @retval None
+  */
+void FLASH_Lock(void)
+{
+  /* Set the LOCK Bit to lock the FLASH Registers access */
+  FLASH->CR |= FLASH_CR_LOCK;
+}
+
+/**
+  * @brief  Erases a specified FLASH Sector.
+  *   
+  * @param  FLASH_Sector: The Sector number to be erased.
+  *          This parameter can be a value between FLASH_Sector_0 and FLASH_Sector_11
+  *    
+  * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
+  *          This parameter can be one of the following values:
+  *            @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, 
+  *                                  the operation will be done by byte (8-bit) 
+  *            @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
+  *                                  the operation will be done by half word (16-bit)
+  *            @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
+  *                                  the operation will be done by word (32-bit)
+  *            @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
+  *                                  the operation will be done by double word (64-bit)
+  *       
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
+  *                       FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+  */
+FLASH_Status FLASH_EraseSector(uint32_t FLASH_Sector, uint8_t VoltageRange)
+{
+  uint32_t tmp_psize = 0x0;
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_SECTOR(FLASH_Sector));
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+  
+  if(VoltageRange == VoltageRange_1)
+  {
+     tmp_psize = FLASH_PSIZE_BYTE;
+  }
+  else if(VoltageRange == VoltageRange_2)
+  {
+    tmp_psize = FLASH_PSIZE_HALF_WORD;
+  }
+  else if(VoltageRange == VoltageRange_3)
+  {
+    tmp_psize = FLASH_PSIZE_WORD;
+  }
+  else
+  {
+    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
+  }
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation();
+  
+  if(status == FLASH_COMPLETE)
+  { 
+    /* if the previous operation is completed, proceed to erase the sector */
+    FLASH->CR &= CR_PSIZE_MASK;
+    FLASH->CR |= tmp_psize;
+    FLASH->CR &= SECTOR_MASK;
+    FLASH->CR |= FLASH_CR_SER | FLASH_Sector;
+    FLASH->CR |= FLASH_CR_STRT;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation();
+    
+    /* if the erase operation is completed, disable the SER Bit */
+    FLASH->CR &= (~FLASH_CR_SER);
+    FLASH->CR &= SECTOR_MASK; 
+  }
+  /* Return the Erase Status */
+  return status;
+}
+
+/**
+  * @brief  Erases all FLASH Sectors.
+  *    
+  * @param  VoltageRange: The device voltage range which defines the erase parallelism.  
+  *          This parameter can be one of the following values:
+  *            @arg VoltageRange_1: when the device voltage range is 1.8V to 2.1V, 
+  *                                  the operation will be done by byte (8-bit) 
+  *            @arg VoltageRange_2: when the device voltage range is 2.1V to 2.7V,
+  *                                  the operation will be done by half word (16-bit)
+  *            @arg VoltageRange_3: when the device voltage range is 2.7V to 3.6V,
+  *                                  the operation will be done by word (32-bit)
+  *            @arg VoltageRange_4: when the device voltage range is 2.7V to 3.6V + External Vpp, 
+  *                                  the operation will be done by double word (64-bit)
+  *       
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
+  *                       FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+  */
+FLASH_Status FLASH_EraseAllSectors(uint8_t VoltageRange)
+{
+  uint32_t tmp_psize = 0x0;
+  FLASH_Status status = FLASH_COMPLETE;
+  
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation();
+  assert_param(IS_VOLTAGERANGE(VoltageRange));
+  
+  if(VoltageRange == VoltageRange_1)
+  {
+     tmp_psize = FLASH_PSIZE_BYTE;
+  }
+  else if(VoltageRange == VoltageRange_2)
+  {
+    tmp_psize = FLASH_PSIZE_HALF_WORD;
+  }
+  else if(VoltageRange == VoltageRange_3)
+  {
+    tmp_psize = FLASH_PSIZE_WORD;
+  }
+  else
+  {
+    tmp_psize = FLASH_PSIZE_DOUBLE_WORD;
+  }  
+  if(status == FLASH_COMPLETE)
+  {
+    /* if the previous operation is completed, proceed to erase all sectors */
+     FLASH->CR &= CR_PSIZE_MASK;
+     FLASH->CR |= tmp_psize;
+     FLASH->CR |= FLASH_CR_MER;
+     FLASH->CR |= FLASH_CR_STRT;
+    
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation();
+
+    /* if the erase operation is completed, disable the MER Bit */
+    FLASH->CR &= (~FLASH_CR_MER);
+
+  }   
+  /* Return the Erase Status */
+  return status;
+}
+
+/**
+  * @brief  Programs a double word (64-bit) at a specified address.
+  * @note   This function must be used when the device voltage range is from
+  *         2.7V to 3.6V and an External Vpp is present.           
+  * @param  Address: specifies the address to be programmed.
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
+  *                       FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+  */
+FLASH_Status FLASH_ProgramDoubleWord(uint32_t Address, uint64_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation();
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* if the previous operation is completed, proceed to program the new data */
+    FLASH->CR &= CR_PSIZE_MASK;
+    FLASH->CR |= FLASH_PSIZE_DOUBLE_WORD;
+    FLASH->CR |= FLASH_CR_PG;
+  
+    *(__IO uint64_t*)Address = Data;
+        
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation();
+
+    /* if the program operation is completed, disable the PG Bit */
+    FLASH->CR &= (~FLASH_CR_PG);
+  } 
+  /* Return the Program Status */
+  return status;
+}
+
+/**
+  * @brief  Programs a word (32-bit) at a specified address.
+  * @param  Address: specifies the address to be programmed.
+  *         This parameter can be any address in Program memory zone or in OTP zone.  
+  * @note   This function must be used when the device voltage range is from 2.7V to 3.6V. 
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
+  *                       FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+  */
+FLASH_Status FLASH_ProgramWord(uint32_t Address, uint32_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation();
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* if the previous operation is completed, proceed to program the new data */
+    FLASH->CR &= CR_PSIZE_MASK;
+    FLASH->CR |= FLASH_PSIZE_WORD;
+    FLASH->CR |= FLASH_CR_PG;
+  
+    *(__IO uint32_t*)Address = Data;
+        
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation();
+
+    /* if the program operation is completed, disable the PG Bit */
+    FLASH->CR &= (~FLASH_CR_PG);
+  } 
+  /* Return the Program Status */
+  return status;
+}
+
+/**
+  * @brief  Programs a half word (16-bit) at a specified address. 
+  * @note   This function must be used when the device voltage range is from 2.1V to 3.6V.               
+  * @param  Address: specifies the address to be programmed.
+  *         This parameter can be any address in Program memory zone or in OTP zone.  
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
+  *                       FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+  */
+FLASH_Status FLASH_ProgramHalfWord(uint32_t Address, uint16_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation();
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* if the previous operation is completed, proceed to program the new data */
+    FLASH->CR &= CR_PSIZE_MASK;
+    FLASH->CR |= FLASH_PSIZE_HALF_WORD;
+    FLASH->CR |= FLASH_CR_PG;
+  
+    *(__IO uint16_t*)Address = Data;
+        
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation();
+
+    /* if the program operation is completed, disable the PG Bit */
+    FLASH->CR &= (~FLASH_CR_PG);
+  } 
+  /* Return the Program Status */
+  return status;
+}
+
+/**
+  * @brief  Programs a byte (8-bit) at a specified address.
+  * @note   This function can be used within all the device supply voltage ranges.               
+  * @param  Address: specifies the address to be programmed.
+  *         This parameter can be any address in Program memory zone or in OTP zone.  
+  * @param  Data: specifies the data to be programmed.
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
+  *                       FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+  */
+FLASH_Status FLASH_ProgramByte(uint32_t Address, uint8_t Data)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Check the parameters */
+  assert_param(IS_FLASH_ADDRESS(Address));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation();
+  
+  if(status == FLASH_COMPLETE)
+  {
+    /* if the previous operation is completed, proceed to program the new data */
+    FLASH->CR &= CR_PSIZE_MASK;
+    FLASH->CR |= FLASH_PSIZE_BYTE;
+    FLASH->CR |= FLASH_CR_PG;
+  
+    *(__IO uint8_t*)Address = Data;
+        
+    /* Wait for last operation to be completed */
+    status = FLASH_WaitForLastOperation();
+
+    /* if the program operation is completed, disable the PG Bit */
+    FLASH->CR &= (~FLASH_CR_PG);
+  } 
+
+  /* Return the Program Status */
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Group3 Option Bytes Programming functions
+ *  @brief   Option Bytes Programming functions 
+ *
+@verbatim   
+ ===============================================================================
+                        Option Bytes Programming functions
+ ===============================================================================  
+ 
+   This group includes the following functions:
+   - void FLASH_OB_Unlock(void)
+   - void FLASH_OB_Lock(void)
+   - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
+   - void FLASH_OB_RDPConfig(uint8_t OB_RDP)
+   - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
+   - void FLASH_OB_BORConfig(uint8_t OB_BOR)
+   - FLASH_Status FLASH_ProgramOTP(uint32_t Address, uint32_t Data)							
+   - FLASH_Status FLASH_OB_Launch(void)
+   - uint32_t FLASH_OB_GetUser(void)						
+   - uint8_t FLASH_OB_GetWRP(void)						
+   - uint8_t FLASH_OB_GetRDP(void)							
+   - uint8_t FLASH_OB_GetBOR(void)
+   
+   Any operation of erase or program should follow these steps:
+   1. Call the FLASH_OB_Unlock() function to enable the FLASH option control register access
+
+   2. Call one or several functions to program the desired Option Bytes:
+      - void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState) => to Enable/Disable 
+        the desired sector write protection
+      - void FLASH_OB_RDPConfig(uint8_t OB_RDP) => to set the desired read Protection Level
+      - void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY) => to configure 
+        the user Option Bytes.
+      - void FLASH_OB_BORConfig(uint8_t OB_BOR) => to set the BOR Level 			 
+
+   3. Once all needed Option Bytes to be programmed are correctly written, call the
+      FLASH_OB_Launch() function to launch the Option Bytes programming process.
+     
+     @note When changing the IWDG mode from HW to SW or from SW to HW, a system 
+           reset is needed to make the change effective.  
+
+   4. Call the FLASH_OB_Lock() function to disable the FLASH option control register
+      access (recommended to protect the Option Bytes against possible unwanted operations)
+    
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Unlocks the FLASH Option Control Registers access.
+  * @param  None
+  * @retval None
+  */
+void FLASH_OB_Unlock(void)
+{
+  if((FLASH->OPTCR & FLASH_OPTCR_OPTLOCK) != RESET)
+  {
+    /* Authorizes the Option Byte register programming */
+    FLASH->OPTKEYR = FLASH_OPT_KEY1;
+    FLASH->OPTKEYR = FLASH_OPT_KEY2;
+  }  
+}
+
+/**
+  * @brief  Locks the FLASH Option Control Registers access.
+  * @param  None
+  * @retval None
+  */
+void FLASH_OB_Lock(void)
+{
+  /* Set the OPTLOCK Bit to lock the FLASH Option Byte Registers access */
+  FLASH->OPTCR |= FLASH_OPTCR_OPTLOCK;
+}
+
+/**
+  * @brief  Enables or disables the write protection of the desired sectors
+  * @param  OB_WRP: specifies the sector(s) to be write protected or unprotected.
+  *          This parameter can be one of the following values:
+  *            @arg OB_WRP: A value between OB_WRP_Sector0 and OB_WRP_Sector11                      
+  *            @arg OB_WRP_Sector_All
+  * @param  Newstate: new state of the Write Protection.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None  
+  */
+void FLASH_OB_WRPConfig(uint32_t OB_WRP, FunctionalState NewState)
+{ 
+  FLASH_Status status = FLASH_COMPLETE;
+  
+  /* Check the parameters */
+  assert_param(IS_OB_WRP(OB_WRP));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+    
+  status = FLASH_WaitForLastOperation();
+
+  if(status == FLASH_COMPLETE)
+  { 
+    if(NewState != DISABLE)
+    {
+      *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS &= (~OB_WRP);
+    }
+    else
+    {
+      *(__IO uint16_t*)OPTCR_BYTE2_ADDRESS |= (uint16_t)OB_WRP;
+    }
+  }
+}
+
+/**
+  * @brief  Sets the read protection level.
+  * @param  OB_RDP: specifies the read protection level.
+  *          This parameter can be one of the following values:
+  *            @arg OB_RDP_Level_0: No protection
+  *            @arg OB_RDP_Level_1: Read protection of the memory
+  *            @arg OB_RDP_Level_2: Full chip protection
+  *   
+  * !!!Warning!!! When enabling OB_RDP level 2 it's no more possible to go back to level 1 or 0
+  *    
+  * @retval None
+  */
+void FLASH_OB_RDPConfig(uint8_t OB_RDP)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Check the parameters */
+  assert_param(IS_OB_RDP(OB_RDP));
+
+  status = FLASH_WaitForLastOperation();
+
+  if(status == FLASH_COMPLETE)
+  {
+    *(__IO uint8_t*)OPTCR_BYTE1_ADDRESS = OB_RDP;
+
+  }
+}
+
+/**
+  * @brief  Programs the FLASH User Option Byte: IWDG_SW / RST_STOP / RST_STDBY.    
+  * @param  OB_IWDG: Selects the IWDG mode
+  *          This parameter can be one of the following values:
+  *            @arg OB_IWDG_SW: Software IWDG selected
+  *            @arg OB_IWDG_HW: Hardware IWDG selected
+  * @param  OB_STOP: Reset event when entering STOP mode.
+  *          This parameter  can be one of the following values:
+  *            @arg OB_STOP_NoRST: No reset generated when entering in STOP
+  *            @arg OB_STOP_RST: Reset generated when entering in STOP
+  * @param  OB_STDBY: Reset event when entering Standby mode.
+  *          This parameter  can be one of the following values:
+  *            @arg OB_STDBY_NoRST: No reset generated when entering in STANDBY
+  *            @arg OB_STDBY_RST: Reset generated when entering in STANDBY
+  * @retval None
+  */
+void FLASH_OB_UserConfig(uint8_t OB_IWDG, uint8_t OB_STOP, uint8_t OB_STDBY)
+{
+  uint8_t optiontmp = 0xFF;
+  FLASH_Status status = FLASH_COMPLETE; 
+
+  /* Check the parameters */
+  assert_param(IS_OB_IWDG_SOURCE(OB_IWDG));
+  assert_param(IS_OB_STOP_SOURCE(OB_STOP));
+  assert_param(IS_OB_STDBY_SOURCE(OB_STDBY));
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation();
+  
+  if(status == FLASH_COMPLETE)
+  { 
+    /* Mask OPTLOCK, OPTSTRT and BOR_LEV bits */
+    optiontmp =  (uint8_t)((*(__IO uint8_t *)OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0F); 
+
+    /* Update User Option Byte */
+    *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS = OB_IWDG | (uint8_t)(OB_STDBY | (uint8_t)(OB_STOP | ((uint8_t)optiontmp))); 
+  }  
+}
+
+/**
+  * @brief  Sets the BOR Level. 
+  * @param  OB_BOR: specifies the Option Bytes BOR Reset Level.
+  *          This parameter can be one of the following values:
+  *            @arg OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
+  *            @arg OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
+  *            @arg OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
+  *            @arg OB_BOR_OFF: Supply voltage ranges from 1.62 to 2.1 V
+  * @retval None
+  */
+void FLASH_OB_BORConfig(uint8_t OB_BOR)
+{
+  /* Check the parameters */
+  assert_param(IS_OB_BOR(OB_BOR));
+
+  /* Set the BOR Level */
+  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS &= (~FLASH_OPTCR_BOR_LEV);
+  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= OB_BOR;
+
+}
+
+/**
+  * @brief  Launch the option byte loading.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
+  *                       FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+  */
+FLASH_Status FLASH_OB_Launch(void)
+{
+  FLASH_Status status = FLASH_COMPLETE;
+
+  /* Set the OPTSTRT bit in OPTCR register */
+  *(__IO uint8_t *)OPTCR_BYTE0_ADDRESS |= FLASH_OPTCR_OPTSTRT;
+
+  /* Wait for last operation to be completed */
+  status = FLASH_WaitForLastOperation();
+
+  return status;
+}
+
+/**
+  * @brief  Returns the FLASH User Option Bytes values.
+  * @param  None
+  * @retval The FLASH User Option Bytes values: IWDG_SW(Bit0), RST_STOP(Bit1)
+  *         and RST_STDBY(Bit2).
+  */
+uint8_t FLASH_OB_GetUser(void)
+{
+  /* Return the User Option Byte */
+  return (uint8_t)(FLASH->OPTCR >> 5);
+}
+
+/**
+  * @brief  Returns the FLASH Write Protection Option Bytes value.
+  * @param  None
+  * @retval The FLASH Write Protection  Option Bytes value
+  */
+uint16_t FLASH_OB_GetWRP(void)
+{
+  /* Return the FLASH write protection Register value */
+  return (*(__IO uint16_t *)(OPTCR_BYTE2_ADDRESS));
+}
+
+/**
+  * @brief  Returns the FLASH Read Protection level.
+  * @param  None
+  * @retval FLASH ReadOut Protection Status:
+  *           - SET, when OB_RDP_Level_1 or OB_RDP_Level_2 is set
+  *           - RESET, when OB_RDP_Level_0 is set
+  */
+FlagStatus FLASH_OB_GetRDP(void)
+{
+  FlagStatus readstatus = RESET;
+
+  if ((*(__IO uint8_t*)(OPTCR_BYTE1_ADDRESS) != (uint8_t)OB_RDP_Level_0))
+  {
+    readstatus = SET;
+  }
+  else
+  {
+    readstatus = RESET;
+  }
+  return readstatus;
+}
+
+/**
+  * @brief  Returns the FLASH BOR level.
+  * @param  None
+  * @retval The FLASH BOR level:
+  *           - OB_BOR_LEVEL3: Supply voltage ranges from 2.7 to 3.6 V
+  *           - OB_BOR_LEVEL2: Supply voltage ranges from 2.4 to 2.7 V
+  *           - OB_BOR_LEVEL1: Supply voltage ranges from 2.1 to 2.4 V
+  *           - OB_BOR_OFF   : Supply voltage ranges from 1.62 to 2.1 V  
+  */
+uint8_t FLASH_OB_GetBOR(void)
+{
+  /* Return the FLASH BOR level */
+  return (uint8_t)(*(__IO uint8_t *)(OPTCR_BYTE0_ADDRESS) & (uint8_t)0x0C);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup FLASH_Group4 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+                  Interrupts and flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified FLASH interrupts.
+  * @param  FLASH_IT: specifies the FLASH interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg FLASH_IT_ERR: FLASH Error Interrupt
+  *            @arg FLASH_IT_EOP: FLASH end of operation Interrupt
+  * @retval None 
+  */
+void FLASH_ITConfig(uint32_t FLASH_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_IT(FLASH_IT)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if(NewState != DISABLE)
+  {
+    /* Enable the interrupt sources */
+    FLASH->CR |= FLASH_IT;
+  }
+  else
+  {
+    /* Disable the interrupt sources */
+    FLASH->CR &= ~(uint32_t)FLASH_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified FLASH flag is set or not.
+  * @param  FLASH_FLAG: specifies the FLASH flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg FLASH_FLAG_EOP: FLASH End of Operation flag 
+  *            @arg FLASH_FLAG_OPERR: FLASH operation Error flag 
+  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 
+  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag
+  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
+  *            @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
+  *            @arg FLASH_FLAG_BSY: FLASH Busy flag
+  * @retval The new state of FLASH_FLAG (SET or RESET).
+  */
+FlagStatus FLASH_GetFlagStatus(uint32_t FLASH_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_FLASH_GET_FLAG(FLASH_FLAG));
+
+  if((FLASH->SR & FLASH_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the new state of FLASH_FLAG (SET or RESET) */
+  return bitstatus; 
+}
+
+/**
+  * @brief  Clears the FLASH's pending flags.
+  * @param  FLASH_FLAG: specifies the FLASH flags to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg FLASH_FLAG_EOP: FLASH End of Operation flag 
+  *            @arg FLASH_FLAG_OPERR: FLASH operation Error flag 
+  *            @arg FLASH_FLAG_WRPERR: FLASH Write protected error flag 
+  *            @arg FLASH_FLAG_PGAERR: FLASH Programming Alignment error flag 
+  *            @arg FLASH_FLAG_PGPERR: FLASH Programming Parallelism error flag
+  *            @arg FLASH_FLAG_PGSERR: FLASH Programming Sequence error flag
+  * @retval None
+  */
+void FLASH_ClearFlag(uint32_t FLASH_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_FLASH_CLEAR_FLAG(FLASH_FLAG));
+  
+  /* Clear the flags */
+  FLASH->SR = FLASH_FLAG;
+}
+
+/**
+  * @brief  Returns the FLASH Status.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
+  *                       FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+  */
+FLASH_Status FLASH_GetStatus(void)
+{
+  FLASH_Status flashstatus = FLASH_COMPLETE;
+  
+  if((FLASH->SR & FLASH_FLAG_BSY) == FLASH_FLAG_BSY) 
+  {
+    flashstatus = FLASH_BUSY;
+  }
+  else 
+  {  
+    if((FLASH->SR & FLASH_FLAG_WRPERR) != (uint32_t)0x00)
+    { 
+      flashstatus = FLASH_ERROR_WRP;
+    }
+    else 
+    {
+      if((FLASH->SR & (uint32_t)0xEF) != (uint32_t)0x00)
+      {
+        flashstatus = FLASH_ERROR_PROGRAM; 
+      }
+      else
+      {
+        if((FLASH->SR & FLASH_FLAG_OPERR) != (uint32_t)0x00)
+        {
+          flashstatus = FLASH_ERROR_OPERATION;
+        }
+        else
+        {
+          flashstatus = FLASH_COMPLETE;
+        }
+      }
+    }
+  }
+  /* Return the FLASH Status */
+  return flashstatus;
+}
+
+/**
+  * @brief  Waits for a FLASH operation to complete.
+  * @param  None
+  * @retval FLASH Status: The returned value can be: FLASH_BUSY, FLASH_ERROR_PROGRAM,
+  *                       FLASH_ERROR_WRP, FLASH_ERROR_OPERATION or FLASH_COMPLETE.
+  */
+FLASH_Status FLASH_WaitForLastOperation(void)
+{ 
+  __IO FLASH_Status status = FLASH_COMPLETE;
+   
+  /* Check for the FLASH Status */
+  status = FLASH_GetStatus();
+
+  /* Wait for the FLASH operation to complete by polling on BUSY flag to be reset.
+     Even if the FLASH operation fails, the BUSY flag will be reset and an error
+     flag will be set */
+  while(status == FLASH_BUSY)
+  {
+    status = FLASH_GetStatus();
+  }
+  /* Return the operation status */
+  return status;
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c
new file mode 100644
index 0000000000..6967b37041
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_fsmc.c
@@ -0,0 +1,982 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_fsmc.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+ * @brief    This file provides firmware functions to manage the following 
+  *          functionalities of the FSMC peripheral:           
+  *           - Interface with SRAM, PSRAM, NOR and OneNAND memories
+  *           - Interface with NAND memories
+  *           - Interface with 16-bit PC Card compatible memories  
+  *           - Interrupts and flags management   
+  *           
+  ******************************************************************************
+
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_fsmc.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup FSMC 
+  * @brief FSMC driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* --------------------- FSMC registers bit mask ---------------------------- */
+/* FSMC BCRx Mask */
+#define BCR_MBKEN_SET          ((uint32_t)0x00000001)
+#define BCR_MBKEN_RESET        ((uint32_t)0x000FFFFE)
+#define BCR_FACCEN_SET         ((uint32_t)0x00000040)
+
+/* FSMC PCRx Mask */
+#define PCR_PBKEN_SET          ((uint32_t)0x00000004)
+#define PCR_PBKEN_RESET        ((uint32_t)0x000FFFFB)
+#define PCR_ECCEN_SET          ((uint32_t)0x00000040)
+#define PCR_ECCEN_RESET        ((uint32_t)0x000FFFBF)
+#define PCR_MEMORYTYPE_NAND    ((uint32_t)0x00000008)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup FSMC_Private_Functions
+  * @{
+  */
+
+/** @defgroup FSMC_Group1 NOR/SRAM Controller functions
+ *  @brief   NOR/SRAM Controller functions 
+ *
+@verbatim   
+ ===============================================================================
+                    NOR/SRAM Controller functions
+ ===============================================================================  
+
+ The following sequence should be followed to configure the FSMC to interface with
+ SRAM, PSRAM, NOR or OneNAND memory connected to the NOR/SRAM Bank:
+ 
+   1. Enable the clock for the FSMC and associated GPIOs using the following functions:
+          RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
+          RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+
+   2. FSMC pins configuration 
+       - Connect the involved FSMC pins to AF12 using the following function 
+          GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); 
+       - Configure these FSMC pins in alternate function mode by calling the function
+          GPIO_Init();    
+       
+   3. Declare a FSMC_NORSRAMInitTypeDef structure, for example:
+          FSMC_NORSRAMInitTypeDef  FSMC_NORSRAMInitStructure;
+      and fill the FSMC_NORSRAMInitStructure variable with the allowed values of
+      the structure member.
+      
+   4. Initialize the NOR/SRAM Controller by calling the function
+          FSMC_NORSRAMInit(&FSMC_NORSRAMInitStructure); 
+
+   5. Then enable the NOR/SRAM Bank, for example:
+          FSMC_NORSRAMCmd(FSMC_Bank1_NORSRAM2, ENABLE);  
+
+   6. At this stage you can read/write from/to the memory connected to the NOR/SRAM Bank. 
+   
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the FSMC NOR/SRAM Banks registers to their default 
+  *   reset values.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *          This parameter can be one of the following values:
+  *            @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  
+  *            @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 
+  *            @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 
+  *            @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 
+  * @retval None
+  */
+void FSMC_NORSRAMDeInit(uint32_t FSMC_Bank)
+{
+  /* Check the parameter */
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
+  
+  /* FSMC_Bank1_NORSRAM1 */
+  if(FSMC_Bank == FSMC_Bank1_NORSRAM1)
+  {
+    FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030DB;    
+  }
+  /* FSMC_Bank1_NORSRAM2,  FSMC_Bank1_NORSRAM3 or FSMC_Bank1_NORSRAM4 */
+  else
+  {   
+    FSMC_Bank1->BTCR[FSMC_Bank] = 0x000030D2; 
+  }
+  FSMC_Bank1->BTCR[FSMC_Bank + 1] = 0x0FFFFFFF;
+  FSMC_Bank1E->BWTR[FSMC_Bank] = 0x0FFFFFFF;  
+}
+
+/**
+  * @brief  Initializes the FSMC NOR/SRAM Banks according to the specified
+  *         parameters in the FSMC_NORSRAMInitStruct.
+  * @param  FSMC_NORSRAMInitStruct : pointer to a FSMC_NORSRAMInitTypeDef structure
+  *         that contains the configuration information for the FSMC NOR/SRAM 
+  *         specified Banks.                       
+  * @retval None
+  */
+void FSMC_NORSRAMInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_NORSRAMInitStruct->FSMC_Bank));
+  assert_param(IS_FSMC_MUX(FSMC_NORSRAMInitStruct->FSMC_DataAddressMux));
+  assert_param(IS_FSMC_MEMORY(FSMC_NORSRAMInitStruct->FSMC_MemoryType));
+  assert_param(IS_FSMC_MEMORY_WIDTH(FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth));
+  assert_param(IS_FSMC_BURSTMODE(FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode));
+  assert_param(IS_FSMC_ASYNWAIT(FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait));
+  assert_param(IS_FSMC_WAIT_POLARITY(FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity));
+  assert_param(IS_FSMC_WRAP_MODE(FSMC_NORSRAMInitStruct->FSMC_WrapMode));
+  assert_param(IS_FSMC_WAIT_SIGNAL_ACTIVE(FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive));
+  assert_param(IS_FSMC_WRITE_OPERATION(FSMC_NORSRAMInitStruct->FSMC_WriteOperation));
+  assert_param(IS_FSMC_WAITE_SIGNAL(FSMC_NORSRAMInitStruct->FSMC_WaitSignal));
+  assert_param(IS_FSMC_EXTENDED_MODE(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode));
+  assert_param(IS_FSMC_WRITE_BURST(FSMC_NORSRAMInitStruct->FSMC_WriteBurst));  
+  assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime));
+  assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime));
+  assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime));
+  assert_param(IS_FSMC_TURNAROUND_TIME(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration));
+  assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision));
+  assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency));
+  assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode)); 
+  
+  /* Bank1 NOR/SRAM control register configuration */ 
+  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 
+            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_DataAddressMux |
+            FSMC_NORSRAMInitStruct->FSMC_MemoryType |
+            FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth |
+            FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode |
+            FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait |
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity |
+            FSMC_NORSRAMInitStruct->FSMC_WrapMode |
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive |
+            FSMC_NORSRAMInitStruct->FSMC_WriteOperation |
+            FSMC_NORSRAMInitStruct->FSMC_WaitSignal |
+            FSMC_NORSRAMInitStruct->FSMC_ExtendedMode |
+            FSMC_NORSRAMInitStruct->FSMC_WriteBurst;
+  if(FSMC_NORSRAMInitStruct->FSMC_MemoryType == FSMC_MemoryType_NOR)
+  {
+    FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank] |= (uint32_t)BCR_FACCEN_SET;
+  }
+  /* Bank1 NOR/SRAM timing register configuration */
+  FSMC_Bank1->BTCR[FSMC_NORSRAMInitStruct->FSMC_Bank+1] = 
+            (uint32_t)FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime << 4) |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime << 8) |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration << 16) |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision << 20) |
+            (FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency << 24) |
+             FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode;
+            
+    
+  /* Bank1 NOR/SRAM timing register for write configuration, if extended mode is used */
+  if(FSMC_NORSRAMInitStruct->FSMC_ExtendedMode == FSMC_ExtendedMode_Enable)
+  {
+    assert_param(IS_FSMC_ADDRESS_SETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime));
+    assert_param(IS_FSMC_ADDRESS_HOLD_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime));
+    assert_param(IS_FSMC_DATASETUP_TIME(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime));
+    assert_param(IS_FSMC_CLK_DIV(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision));
+    assert_param(IS_FSMC_DATA_LATENCY(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency));
+    assert_param(IS_FSMC_ACCESS_MODE(FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode));
+    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 
+              (uint32_t)FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime |
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime << 4 )|
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime << 8) |
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision << 20) |
+              (FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency << 24) |
+               FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode;
+  }
+  else
+  {
+    FSMC_Bank1E->BWTR[FSMC_NORSRAMInitStruct->FSMC_Bank] = 0x0FFFFFFF;
+  }
+}
+
+/**
+  * @brief  Fills each FSMC_NORSRAMInitStruct member with its default value.
+  * @param  FSMC_NORSRAMInitStruct: pointer to a FSMC_NORSRAMInitTypeDef structure 
+  *         which will be initialized.
+  * @retval None
+  */
+void FSMC_NORSRAMStructInit(FSMC_NORSRAMInitTypeDef* FSMC_NORSRAMInitStruct)
+{  
+  /* Reset NOR/SRAM Init structure parameters values */
+  FSMC_NORSRAMInitStruct->FSMC_Bank = FSMC_Bank1_NORSRAM1;
+  FSMC_NORSRAMInitStruct->FSMC_DataAddressMux = FSMC_DataAddressMux_Enable;
+  FSMC_NORSRAMInitStruct->FSMC_MemoryType = FSMC_MemoryType_SRAM;
+  FSMC_NORSRAMInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+  FSMC_NORSRAMInitStruct->FSMC_BurstAccessMode = FSMC_BurstAccessMode_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_AsynchronousWait = FSMC_AsynchronousWait_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignalPolarity = FSMC_WaitSignalPolarity_Low;
+  FSMC_NORSRAMInitStruct->FSMC_WrapMode = FSMC_WrapMode_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignalActive = FSMC_WaitSignalActive_BeforeWaitState;
+  FSMC_NORSRAMInitStruct->FSMC_WriteOperation = FSMC_WriteOperation_Enable;
+  FSMC_NORSRAMInitStruct->FSMC_WaitSignal = FSMC_WaitSignal_Enable;
+  FSMC_NORSRAMInitStruct->FSMC_ExtendedMode = FSMC_ExtendedMode_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_WriteBurst = FSMC_WriteBurst_Disable;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressSetupTime = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AddressHoldTime = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataSetupTime = 0xFF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_CLKDivision = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_DataLatency = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_ReadWriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A; 
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressSetupTime = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AddressHoldTime = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataSetupTime = 0xFF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_BusTurnAroundDuration = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_CLKDivision = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_DataLatency = 0xF;
+  FSMC_NORSRAMInitStruct->FSMC_WriteTimingStruct->FSMC_AccessMode = FSMC_AccessMode_A;
+}
+
+/**
+  * @brief  Enables or disables the specified NOR/SRAM Memory Bank.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *          This parameter can be one of the following values:
+  *            @arg FSMC_Bank1_NORSRAM1: FSMC Bank1 NOR/SRAM1  
+  *            @arg FSMC_Bank1_NORSRAM2: FSMC Bank1 NOR/SRAM2 
+  *            @arg FSMC_Bank1_NORSRAM3: FSMC Bank1 NOR/SRAM3 
+  *            @arg FSMC_Bank1_NORSRAM4: FSMC Bank1 NOR/SRAM4 
+  * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FSMC_NORSRAMCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+  assert_param(IS_FSMC_NORSRAM_BANK(FSMC_Bank));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected NOR/SRAM Bank by setting the PBKEN bit in the BCRx register */
+    FSMC_Bank1->BTCR[FSMC_Bank] |= BCR_MBKEN_SET;
+  }
+  else
+  {
+    /* Disable the selected NOR/SRAM Bank by clearing the PBKEN bit in the BCRx register */
+    FSMC_Bank1->BTCR[FSMC_Bank] &= BCR_MBKEN_RESET;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Group2 NAND Controller functions
+ *  @brief   NAND Controller functions 
+ *
+@verbatim   
+ ===============================================================================
+                    NAND Controller functions
+ ===============================================================================  
+
+ The following sequence should be followed to configure the FSMC to interface with
+ 8-bit or 16-bit NAND memory connected to the NAND Bank:
+ 
+   1. Enable the clock for the FSMC and associated GPIOs using the following functions:
+          RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
+          RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+
+   2. FSMC pins configuration 
+       - Connect the involved FSMC pins to AF12 using the following function 
+          GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); 
+       - Configure these FSMC pins in alternate function mode by calling the function
+          GPIO_Init();    
+       
+   3. Declare a FSMC_NANDInitTypeDef structure, for example:
+          FSMC_NANDInitTypeDef  FSMC_NANDInitStructure;
+      and fill the FSMC_NANDInitStructure variable with the allowed values of
+      the structure member.
+      
+   4. Initialize the NAND Controller by calling the function
+          FSMC_NANDInit(&FSMC_NANDInitStructure); 
+
+   5. Then enable the NAND Bank, for example:
+          FSMC_NANDCmd(FSMC_Bank3_NAND, ENABLE);  
+
+   6. At this stage you can read/write from/to the memory connected to the NAND Bank. 
+   
+@note To enable the Error Correction Code (ECC), you have to use the function
+          FSMC_NANDECCCmd(FSMC_Bank3_NAND, ENABLE);  
+      and to get the current ECC value you have to use the function
+          ECCval = FSMC_GetECC(FSMC_Bank3_NAND); 
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Deinitializes the FSMC NAND Banks registers to their default reset values.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *          This parameter can be one of the following values:
+  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND 
+  * @retval None
+  */
+void FSMC_NANDDeInit(uint32_t FSMC_Bank)
+{
+  /* Check the parameter */
+  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+  
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    /* Set the FSMC_Bank2 registers to their reset values */
+    FSMC_Bank2->PCR2 = 0x00000018;
+    FSMC_Bank2->SR2 = 0x00000040;
+    FSMC_Bank2->PMEM2 = 0xFCFCFCFC;
+    FSMC_Bank2->PATT2 = 0xFCFCFCFC;  
+  }
+  /* FSMC_Bank3_NAND */  
+  else
+  {
+    /* Set the FSMC_Bank3 registers to their reset values */
+    FSMC_Bank3->PCR3 = 0x00000018;
+    FSMC_Bank3->SR3 = 0x00000040;
+    FSMC_Bank3->PMEM3 = 0xFCFCFCFC;
+    FSMC_Bank3->PATT3 = 0xFCFCFCFC; 
+  }  
+}
+
+/**
+  * @brief  Initializes the FSMC NAND Banks according to the specified parameters
+  *         in the FSMC_NANDInitStruct.
+  * @param  FSMC_NANDInitStruct : pointer to a FSMC_NANDInitTypeDef structure that
+  *         contains the configuration information for the FSMC NAND specified Banks.                       
+  * @retval None
+  */
+void FSMC_NANDInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
+{
+  uint32_t tmppcr = 0x00000000, tmppmem = 0x00000000, tmppatt = 0x00000000; 
+    
+  /* Check the parameters */
+  assert_param( IS_FSMC_NAND_BANK(FSMC_NANDInitStruct->FSMC_Bank));
+  assert_param( IS_FSMC_WAIT_FEATURE(FSMC_NANDInitStruct->FSMC_Waitfeature));
+  assert_param( IS_FSMC_MEMORY_WIDTH(FSMC_NANDInitStruct->FSMC_MemoryDataWidth));
+  assert_param( IS_FSMC_ECC_STATE(FSMC_NANDInitStruct->FSMC_ECC));
+  assert_param( IS_FSMC_ECCPAGE_SIZE(FSMC_NANDInitStruct->FSMC_ECCPageSize));
+  assert_param( IS_FSMC_TCLR_TIME(FSMC_NANDInitStruct->FSMC_TCLRSetupTime));
+  assert_param( IS_FSMC_TAR_TIME(FSMC_NANDInitStruct->FSMC_TARSetupTime));
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
+  
+  /* Set the tmppcr value according to FSMC_NANDInitStruct parameters */
+  tmppcr = (uint32_t)FSMC_NANDInitStruct->FSMC_Waitfeature |
+            PCR_MEMORYTYPE_NAND |
+            FSMC_NANDInitStruct->FSMC_MemoryDataWidth |
+            FSMC_NANDInitStruct->FSMC_ECC |
+            FSMC_NANDInitStruct->FSMC_ECCPageSize |
+            (FSMC_NANDInitStruct->FSMC_TCLRSetupTime << 9 )|
+            (FSMC_NANDInitStruct->FSMC_TARSetupTime << 13);
+            
+  /* Set tmppmem value according to FSMC_CommonSpaceTimingStructure parameters */
+  tmppmem = (uint32_t)FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
+            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+            (FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
+            
+  /* Set tmppatt value according to FSMC_AttributeSpaceTimingStructure parameters */
+  tmppatt = (uint32_t)FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
+            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+            (FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);
+  
+  if(FSMC_NANDInitStruct->FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    /* FSMC_Bank2_NAND registers configuration */
+    FSMC_Bank2->PCR2 = tmppcr;
+    FSMC_Bank2->PMEM2 = tmppmem;
+    FSMC_Bank2->PATT2 = tmppatt;
+  }
+  else
+  {
+    /* FSMC_Bank3_NAND registers configuration */
+    FSMC_Bank3->PCR3 = tmppcr;
+    FSMC_Bank3->PMEM3 = tmppmem;
+    FSMC_Bank3->PATT3 = tmppatt;
+  }
+}
+
+
+/**
+  * @brief  Fills each FSMC_NANDInitStruct member with its default value.
+  * @param  FSMC_NANDInitStruct: pointer to a FSMC_NANDInitTypeDef structure which
+  *         will be initialized.
+  * @retval None
+  */
+void FSMC_NANDStructInit(FSMC_NANDInitTypeDef* FSMC_NANDInitStruct)
+{ 
+  /* Reset NAND Init structure parameters values */
+  FSMC_NANDInitStruct->FSMC_Bank = FSMC_Bank2_NAND;
+  FSMC_NANDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
+  FSMC_NANDInitStruct->FSMC_MemoryDataWidth = FSMC_MemoryDataWidth_8b;
+  FSMC_NANDInitStruct->FSMC_ECC = FSMC_ECC_Disable;
+  FSMC_NANDInitStruct->FSMC_ECCPageSize = FSMC_ECCPageSize_256Bytes;
+  FSMC_NANDInitStruct->FSMC_TCLRSetupTime = 0x0;
+  FSMC_NANDInitStruct->FSMC_TARSetupTime = 0x0;
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+  FSMC_NANDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;	  
+}
+
+/**
+  * @brief  Enables or disables the specified NAND Memory Bank.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *          This parameter can be one of the following values:
+  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  * @param  NewState: new state of the FSMC_Bank. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FSMC_NANDCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected NAND Bank by setting the PBKEN bit in the PCRx register */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      FSMC_Bank2->PCR2 |= PCR_PBKEN_SET;
+    }
+    else
+    {
+      FSMC_Bank3->PCR3 |= PCR_PBKEN_SET;
+    }
+  }
+  else
+  {
+    /* Disable the selected NAND Bank by clearing the PBKEN bit in the PCRx register */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      FSMC_Bank2->PCR2 &= PCR_PBKEN_RESET;
+    }
+    else
+    {
+      FSMC_Bank3->PCR3 &= PCR_PBKEN_RESET;
+    }
+  }
+}
+/**
+  * @brief  Enables or disables the FSMC NAND ECC feature.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *          This parameter can be one of the following values:
+  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  * @param  NewState: new state of the FSMC NAND ECC feature.  
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FSMC_NANDECCCmd(uint32_t FSMC_Bank, FunctionalState NewState)
+{
+  assert_param(IS_FSMC_NAND_BANK(FSMC_Bank));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected NAND Bank ECC function by setting the ECCEN bit in the PCRx register */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      FSMC_Bank2->PCR2 |= PCR_ECCEN_SET;
+    }
+    else
+    {
+      FSMC_Bank3->PCR3 |= PCR_ECCEN_SET;
+    }
+  }
+  else
+  {
+    /* Disable the selected NAND Bank ECC function by clearing the ECCEN bit in the PCRx register */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      FSMC_Bank2->PCR2 &= PCR_ECCEN_RESET;
+    }
+    else
+    {
+      FSMC_Bank3->PCR3 &= PCR_ECCEN_RESET;
+    }
+  }
+}
+
+/**
+  * @brief  Returns the error correction code register value.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *          This parameter can be one of the following values:
+  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  * @retval The Error Correction Code (ECC) value.
+  */
+uint32_t FSMC_GetECC(uint32_t FSMC_Bank)
+{
+  uint32_t eccval = 0x00000000;
+  
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    /* Get the ECCR2 register value */
+    eccval = FSMC_Bank2->ECCR2;
+  }
+  else
+  {
+    /* Get the ECCR3 register value */
+    eccval = FSMC_Bank3->ECCR3;
+  }
+  /* Return the error correction code value */
+  return(eccval);
+}
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Group3 PCCARD Controller functions
+ *  @brief   PCCARD Controller functions 
+ *
+@verbatim   
+ ===============================================================================
+                    PCCARD Controller functions
+ ===============================================================================  
+
+ The following sequence should be followed to configure the FSMC to interface with
+ 16-bit PC Card compatible memory connected to the PCCARD Bank:
+ 
+   1. Enable the clock for the FSMC and associated GPIOs using the following functions:
+          RCC_AHB3PeriphClockCmd(RCC_AHB3Periph_FSMC, ENABLE);
+          RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+
+   2. FSMC pins configuration 
+       - Connect the involved FSMC pins to AF12 using the following function 
+          GPIO_PinAFConfig(GPIOx, GPIO_PinSourcex, GPIO_AF_FSMC); 
+       - Configure these FSMC pins in alternate function mode by calling the function
+          GPIO_Init();    
+       
+   3. Declare a FSMC_PCCARDInitTypeDef structure, for example:
+          FSMC_PCCARDInitTypeDef  FSMC_PCCARDInitStructure;
+      and fill the FSMC_PCCARDInitStructure variable with the allowed values of
+      the structure member.
+      
+   4. Initialize the PCCARD Controller by calling the function
+          FSMC_PCCARDInit(&FSMC_PCCARDInitStructure); 
+
+   5. Then enable the PCCARD Bank:
+          FSMC_PCCARDCmd(ENABLE);  
+
+   6. At this stage you can read/write from/to the memory connected to the PCCARD Bank. 
+ 
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the FSMC PCCARD Bank registers to their default reset values.
+  * @param  None                       
+  * @retval None
+  */
+void FSMC_PCCARDDeInit(void)
+{
+  /* Set the FSMC_Bank4 registers to their reset values */
+  FSMC_Bank4->PCR4 = 0x00000018; 
+  FSMC_Bank4->SR4 = 0x00000000;	
+  FSMC_Bank4->PMEM4 = 0xFCFCFCFC;
+  FSMC_Bank4->PATT4 = 0xFCFCFCFC;
+  FSMC_Bank4->PIO4 = 0xFCFCFCFC;
+}
+
+/**
+  * @brief  Initializes the FSMC PCCARD Bank according to the specified parameters
+  *         in the FSMC_PCCARDInitStruct.
+  * @param  FSMC_PCCARDInitStruct : pointer to a FSMC_PCCARDInitTypeDef structure
+  *         that contains the configuration information for the FSMC PCCARD Bank.                       
+  * @retval None
+  */
+void FSMC_PCCARDInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_WAIT_FEATURE(FSMC_PCCARDInitStruct->FSMC_Waitfeature));
+  assert_param(IS_FSMC_TCLR_TIME(FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime));
+  assert_param(IS_FSMC_TAR_TIME(FSMC_PCCARDInitStruct->FSMC_TARSetupTime));
+ 
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime));
+  
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime));
+  assert_param(IS_FSMC_SETUP_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime));
+  assert_param(IS_FSMC_WAIT_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime));
+  assert_param(IS_FSMC_HOLD_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime));
+  assert_param(IS_FSMC_HIZ_TIME(FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime));
+  
+  /* Set the PCR4 register value according to FSMC_PCCARDInitStruct parameters */
+  FSMC_Bank4->PCR4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_Waitfeature |
+                     FSMC_MemoryDataWidth_16b |  
+                     (FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime << 9) |
+                     (FSMC_PCCARDInitStruct->FSMC_TARSetupTime << 13);
+            
+  /* Set PMEM4 register value according to FSMC_CommonSpaceTimingStructure parameters */
+  FSMC_Bank4->PMEM4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime |
+                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+                      (FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime << 24); 
+            
+  /* Set PATT4 register value according to FSMC_AttributeSpaceTimingStructure parameters */
+  FSMC_Bank4->PATT4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime |
+                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+                      (FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime << 24);	
+            
+  /* Set PIO4 register value according to FSMC_IOSpaceTimingStructure parameters */
+  FSMC_Bank4->PIO4 = (uint32_t)FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime |
+                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime << 8) |
+                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime << 16)|
+                     (FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime << 24);             
+}
+
+/**
+  * @brief  Fills each FSMC_PCCARDInitStruct member with its default value.
+  * @param  FSMC_PCCARDInitStruct: pointer to a FSMC_PCCARDInitTypeDef structure
+  *         which will be initialized.
+  * @retval None
+  */
+void FSMC_PCCARDStructInit(FSMC_PCCARDInitTypeDef* FSMC_PCCARDInitStruct)
+{
+  /* Reset PCCARD Init structure parameters values */
+  FSMC_PCCARDInitStruct->FSMC_Waitfeature = FSMC_Waitfeature_Disable;
+  FSMC_PCCARDInitStruct->FSMC_TCLRSetupTime = 0x0;
+  FSMC_PCCARDInitStruct->FSMC_TARSetupTime = 0x0;
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_CommonSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_AttributeSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;	
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_SetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_WaitSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HoldSetupTime = 0xFC;
+  FSMC_PCCARDInitStruct->FSMC_IOSpaceTimingStruct->FSMC_HiZSetupTime = 0xFC;
+}
+
+/**
+  * @brief  Enables or disables the PCCARD Memory Bank.
+  * @param  NewState: new state of the PCCARD Memory Bank.  
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FSMC_PCCARDCmd(FunctionalState NewState)
+{
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the PCCARD Bank by setting the PBKEN bit in the PCR4 register */
+    FSMC_Bank4->PCR4 |= PCR_PBKEN_SET;
+  }
+  else
+  {
+    /* Disable the PCCARD Bank by clearing the PBKEN bit in the PCR4 register */
+    FSMC_Bank4->PCR4 &= PCR_PBKEN_RESET;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup FSMC_Group4  Interrupts and flags management functions
+ *  @brief    Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+                     Interrupts and flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified FSMC interrupts.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *          This parameter can be one of the following values:
+  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  *            @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+  * @param  FSMC_IT: specifies the FSMC interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
+  *            @arg FSMC_IT_Level: Level edge detection interrupt.
+  *            @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
+  * @param  NewState: new state of the specified FSMC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void FSMC_ITConfig(uint32_t FSMC_Bank, uint32_t FSMC_IT, FunctionalState NewState)
+{
+  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+  assert_param(IS_FSMC_IT(FSMC_IT));	
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected FSMC_Bank2 interrupts */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      FSMC_Bank2->SR2 |= FSMC_IT;
+    }
+    /* Enable the selected FSMC_Bank3 interrupts */
+    else if (FSMC_Bank == FSMC_Bank3_NAND)
+    {
+      FSMC_Bank3->SR3 |= FSMC_IT;
+    }
+    /* Enable the selected FSMC_Bank4 interrupts */
+    else
+    {
+      FSMC_Bank4->SR4 |= FSMC_IT;    
+    }
+  }
+  else
+  {
+    /* Disable the selected FSMC_Bank2 interrupts */
+    if(FSMC_Bank == FSMC_Bank2_NAND)
+    {
+      
+      FSMC_Bank2->SR2 &= (uint32_t)~FSMC_IT;
+    }
+    /* Disable the selected FSMC_Bank3 interrupts */
+    else if (FSMC_Bank == FSMC_Bank3_NAND)
+    {
+      FSMC_Bank3->SR3 &= (uint32_t)~FSMC_IT;
+    }
+    /* Disable the selected FSMC_Bank4 interrupts */
+    else
+    {
+      FSMC_Bank4->SR4 &= (uint32_t)~FSMC_IT;    
+    }
+  }
+}
+
+/**
+  * @brief  Checks whether the specified FSMC flag is set or not.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *          This parameter can be one of the following values:
+  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  *            @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+  * @param  FSMC_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag.
+  *            @arg FSMC_FLAG_Level: Level detection Flag.
+  *            @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag.
+  *            @arg FSMC_FLAG_FEMPT: Fifo empty Flag. 
+  * @retval The new state of FSMC_FLAG (SET or RESET).
+  */
+FlagStatus FSMC_GetFlagStatus(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpsr = 0x00000000;
+  
+  /* Check the parameters */
+  assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
+  assert_param(IS_FSMC_GET_FLAG(FSMC_FLAG));
+  
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    tmpsr = FSMC_Bank2->SR2;
+  }  
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
+  {
+    tmpsr = FSMC_Bank3->SR3;
+  }
+  /* FSMC_Bank4_PCCARD*/
+  else
+  {
+    tmpsr = FSMC_Bank4->SR4;
+  } 
+  
+  /* Get the flag status */
+  if ((tmpsr & FSMC_FLAG) != (uint16_t)RESET )
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the FSMC's pending flags.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *          This parameter can be one of the following values:
+  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  *            @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+  * @param  FSMC_FLAG: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg FSMC_FLAG_RisingEdge: Rising edge detection Flag.
+  *            @arg FSMC_FLAG_Level: Level detection Flag.
+  *            @arg FSMC_FLAG_FallingEdge: Falling edge detection Flag.
+  * @retval None
+  */
+void FSMC_ClearFlag(uint32_t FSMC_Bank, uint32_t FSMC_FLAG)
+{
+ /* Check the parameters */
+  assert_param(IS_FSMC_GETFLAG_BANK(FSMC_Bank));
+  assert_param(IS_FSMC_CLEAR_FLAG(FSMC_FLAG)) ;
+    
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    FSMC_Bank2->SR2 &= ~FSMC_FLAG; 
+  }  
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
+  {
+    FSMC_Bank3->SR3 &= ~FSMC_FLAG;
+  }
+  /* FSMC_Bank4_PCCARD*/
+  else
+  {
+    FSMC_Bank4->SR4 &= ~FSMC_FLAG;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified FSMC interrupt has occurred or not.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *          This parameter can be one of the following values:
+  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  *            @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+  * @param  FSMC_IT: specifies the FSMC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
+  *            @arg FSMC_IT_Level: Level edge detection interrupt.
+  *            @arg FSMC_IT_FallingEdge: Falling edge detection interrupt. 
+  * @retval The new state of FSMC_IT (SET or RESET).
+  */
+ITStatus FSMC_GetITStatus(uint32_t FSMC_Bank, uint32_t FSMC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpsr = 0x0, itstatus = 0x0, itenable = 0x0; 
+  
+  /* Check the parameters */
+  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+  assert_param(IS_FSMC_GET_IT(FSMC_IT));
+  
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    tmpsr = FSMC_Bank2->SR2;
+  }  
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
+  {
+    tmpsr = FSMC_Bank3->SR3;
+  }
+  /* FSMC_Bank4_PCCARD*/
+  else
+  {
+    tmpsr = FSMC_Bank4->SR4;
+  } 
+  
+  itstatus = tmpsr & FSMC_IT;
+  
+  itenable = tmpsr & (FSMC_IT >> 3);
+  if ((itstatus != (uint32_t)RESET)  && (itenable != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus; 
+}
+
+/**
+  * @brief  Clears the FSMC's interrupt pending bits.
+  * @param  FSMC_Bank: specifies the FSMC Bank to be used
+  *          This parameter can be one of the following values:
+  *            @arg FSMC_Bank2_NAND: FSMC Bank2 NAND 
+  *            @arg FSMC_Bank3_NAND: FSMC Bank3 NAND
+  *            @arg FSMC_Bank4_PCCARD: FSMC Bank4 PCCARD
+  * @param  FSMC_IT: specifies the interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg FSMC_IT_RisingEdge: Rising edge detection interrupt. 
+  *            @arg FSMC_IT_Level: Level edge detection interrupt.
+  *            @arg FSMC_IT_FallingEdge: Falling edge detection interrupt.
+  * @retval None
+  */
+void FSMC_ClearITPendingBit(uint32_t FSMC_Bank, uint32_t FSMC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_FSMC_IT_BANK(FSMC_Bank));
+  assert_param(IS_FSMC_IT(FSMC_IT));
+    
+  if(FSMC_Bank == FSMC_Bank2_NAND)
+  {
+    FSMC_Bank2->SR2 &= ~(FSMC_IT >> 3); 
+  }  
+  else if(FSMC_Bank == FSMC_Bank3_NAND)
+  {
+    FSMC_Bank3->SR3 &= ~(FSMC_IT >> 3);
+  }
+  /* FSMC_Bank4_PCCARD*/
+  else
+  {
+    FSMC_Bank4->SR4 &= ~(FSMC_IT >> 3);
+  }
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c
new file mode 100644
index 0000000000..81ae41ccfb
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_gpio.c
@@ -0,0 +1,561 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_gpio.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the GPIO peripheral:           
+  *           - Initialization and Configuration
+  *           - GPIO Read and Write
+  *           - GPIO Alternate functions configuration
+  * 
+  *  @verbatim
+  *
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================       
+  *           1. Enable the GPIO AHB clock using the following function
+  *                RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOx, ENABLE);
+  *             
+  *           2. Configure the GPIO pin(s) using GPIO_Init()
+  *              Four possible configuration are available for each pin:
+  *                - Input: Floating, Pull-up, Pull-down.
+  *                - Output: Push-Pull (Pull-up, Pull-down or no Pull)
+  *                          Open Drain (Pull-up, Pull-down or no Pull).
+  *                  In output mode, the speed is configurable: 2 MHz, 25 MHz,
+  *                  50 MHz or 100 MHz.
+  *                - Alternate Function: Push-Pull (Pull-up, Pull-down or no Pull)
+  *                                      Open Drain (Pull-up, Pull-down or no Pull).
+  *                - Analog: required mode when a pin is to be used as ADC channel
+  *                          or DAC output.
+  * 
+  *          3- Peripherals alternate function:
+  *              - For ADC and DAC, configure the desired pin in analog mode using 
+  *                  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AN;
+  *              - For other peripherals (TIM, USART...):
+  *                 - Connect the pin to the desired peripherals' Alternate 
+  *                   Function (AF) using GPIO_PinAFConfig() function
+  *                 - Configure the desired pin in alternate function mode using
+  *                   GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+  *                 - Select the type, pull-up/pull-down and output speed via 
+  *                   GPIO_PuPd, GPIO_OType and GPIO_Speed members
+  *                 - Call GPIO_Init() function
+  *        
+  *          4. To get the level of a pin configured in input mode use GPIO_ReadInputDataBit()
+  *          
+  *          5. To set/reset the level of a pin configured in output mode use
+  *             GPIO_SetBits()/GPIO_ResetBits()
+  *               
+  *          6. During and just after reset, the alternate functions are not 
+  *             active and the GPIO pins are configured in input floating mode
+  *             (except JTAG pins).
+  *
+  *          7. The LSE oscillator pins OSC32_IN and OSC32_OUT can be used as 
+  *             general-purpose (PC14 and PC15, respectively) when the LSE
+  *             oscillator is off. The LSE has priority over the GPIO function.
+  *
+  *          8. The HSE oscillator pins OSC_IN/OSC_OUT can be used as 
+  *             general-purpose PH0 and PH1, respectively, when the HSE 
+  *             oscillator is off. The HSE has priority over the GPIO function.
+  *             
+  *  @endverbatim        
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_gpio.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup GPIO 
+  * @brief GPIO driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup GPIO_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup GPIO_Group1 Initialization and Configuration
+ *  @brief   Initialization and Configuration
+ *
+@verbatim   
+ ===============================================================================
+                        Initialization and Configuration
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the GPIOx peripheral registers to their default reset values.
+  * @note   By default, The GPIO pins are configured in input floating mode (except JTAG pins).
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @retval None
+  */
+void GPIO_DeInit(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  if (GPIOx == GPIOA)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOA, DISABLE);
+  }
+  else if (GPIOx == GPIOB)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOB, DISABLE);
+  }
+  else if (GPIOx == GPIOC)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOC, DISABLE);
+  }
+  else if (GPIOx == GPIOD)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOD, DISABLE);
+  }
+  else if (GPIOx == GPIOE)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOE, DISABLE);
+  }
+  else if (GPIOx == GPIOF)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOF, DISABLE);
+  }
+  else if (GPIOx == GPIOG)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOG, DISABLE);
+  }
+  else if (GPIOx == GPIOH)
+  {
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, ENABLE);
+    RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOH, DISABLE);
+  }
+  else
+  {
+    if (GPIOx == GPIOI)
+    {
+      RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, ENABLE);
+      RCC_AHB1PeriphResetCmd(RCC_AHB1Periph_GPIOI, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the GPIOx peripheral according to the specified parameters in the GPIO_InitStruct.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @param  GPIO_InitStruct: pointer to a GPIO_InitTypeDef structure that contains
+  *         the configuration information for the specified GPIO peripheral.
+  * @retval None
+  */
+void GPIO_Init(GPIO_TypeDef* GPIOx, GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  uint32_t pinpos = 0x00, pos = 0x00 , currentpin = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_InitStruct->GPIO_Pin));
+  assert_param(IS_GPIO_MODE(GPIO_InitStruct->GPIO_Mode));
+  assert_param(IS_GPIO_PUPD(GPIO_InitStruct->GPIO_PuPd));
+
+  /* -------------------------Configure the port pins---------------- */
+  /*-- GPIO Mode Configuration --*/
+  for (pinpos = 0x00; pinpos < 0x10; pinpos++)
+  {
+    pos = ((uint32_t)0x01) << pinpos;
+    /* Get the port pins position */
+    currentpin = (GPIO_InitStruct->GPIO_Pin) & pos;
+
+    if (currentpin == pos)
+    {
+      GPIOx->MODER  &= ~(GPIO_MODER_MODER0 << (pinpos * 2));
+      GPIOx->MODER |= (((uint32_t)GPIO_InitStruct->GPIO_Mode) << (pinpos * 2));
+
+      if ((GPIO_InitStruct->GPIO_Mode == GPIO_Mode_OUT) || (GPIO_InitStruct->GPIO_Mode == GPIO_Mode_AF))
+      {
+        /* Check Speed mode parameters */
+        assert_param(IS_GPIO_SPEED(GPIO_InitStruct->GPIO_Speed));
+
+        /* Speed mode configuration */
+        GPIOx->OSPEEDR &= ~(GPIO_OSPEEDER_OSPEEDR0 << (pinpos * 2));
+        GPIOx->OSPEEDR |= ((uint32_t)(GPIO_InitStruct->GPIO_Speed) << (pinpos * 2));
+
+        /* Check Output mode parameters */
+        assert_param(IS_GPIO_OTYPE(GPIO_InitStruct->GPIO_OType));
+
+        /* Output mode configuration*/
+        GPIOx->OTYPER  &= ~((GPIO_OTYPER_OT_0) << ((uint16_t)pinpos)) ;
+        GPIOx->OTYPER |= (uint16_t)(((uint16_t)GPIO_InitStruct->GPIO_OType) << ((uint16_t)pinpos));
+      }
+
+      /* Pull-up Pull down resistor configuration*/
+      GPIOx->PUPDR &= ~(GPIO_PUPDR_PUPDR0 << ((uint16_t)pinpos * 2));
+      GPIOx->PUPDR |= (((uint32_t)GPIO_InitStruct->GPIO_PuPd) << (pinpos * 2));
+    }
+  }
+}
+
+/**
+  * @brief  Fills each GPIO_InitStruct member with its default value.
+  * @param  GPIO_InitStruct : pointer to a GPIO_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void GPIO_StructInit(GPIO_InitTypeDef* GPIO_InitStruct)
+{
+  /* Reset GPIO init structure parameters values */
+  GPIO_InitStruct->GPIO_Pin  = GPIO_Pin_All;
+  GPIO_InitStruct->GPIO_Mode = GPIO_Mode_IN;
+  GPIO_InitStruct->GPIO_Speed = GPIO_Speed_2MHz;
+  GPIO_InitStruct->GPIO_OType = GPIO_OType_PP;
+  GPIO_InitStruct->GPIO_PuPd = GPIO_PuPd_NOPULL;
+}
+
+/**
+  * @brief  Locks GPIO Pins configuration registers.
+  * @note   The locked registers are GPIOx_MODER, GPIOx_OTYPER, GPIOx_OSPEEDR,
+  *         GPIOx_PUPDR, GPIOx_AFRL and GPIOx_AFRH.
+  * @note   The configuration of the locked GPIO pins can no longer be modified
+  *         until the next reset.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be locked.
+  *          This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_PinLockConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  __IO uint32_t tmp = 0x00010000;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  tmp |= GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LCKR = tmp;
+  /* Reset LCKK bit */
+  GPIOx->LCKR =  GPIO_Pin;
+  /* Set LCKK bit */
+  GPIOx->LCKR = tmp;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LCKR;
+  /* Read LCKK bit*/
+  tmp = GPIOx->LCKR;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Group2 GPIO Read and Write
+ *  @brief   GPIO Read and Write
+ *
+@verbatim   
+ ===============================================================================
+                              GPIO Read and Write
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Reads the specified input port pin.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to read.
+  *         This parameter can be GPIO_Pin_x where x can be (0..15).
+  * @retval The input port pin value.
+  */
+uint8_t GPIO_ReadInputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->IDR & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified GPIO input data port.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @retval GPIO input data port value.
+  */
+uint16_t GPIO_ReadInputData(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  return ((uint16_t)GPIOx->IDR);
+}
+
+/**
+  * @brief  Reads the specified output data port bit.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to read.
+  *          This parameter can be GPIO_Pin_x where x can be (0..15).
+  * @retval The output port pin value.
+  */
+uint8_t GPIO_ReadOutputDataBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  uint8_t bitstatus = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+
+  if ((GPIOx->ODR & GPIO_Pin) != (uint32_t)Bit_RESET)
+  {
+    bitstatus = (uint8_t)Bit_SET;
+  }
+  else
+  {
+    bitstatus = (uint8_t)Bit_RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Reads the specified GPIO output data port.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @retval GPIO output data port value.
+  */
+uint16_t GPIO_ReadOutputData(GPIO_TypeDef* GPIOx)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  return ((uint16_t)GPIOx->ODR);
+}
+
+/**
+  * @brief  Sets the selected data port bits.
+  * @note   This functions uses GPIOx_BSRR register to allow atomic read/modify 
+  *         accesses. In this way, there is no risk of an IRQ occurring between
+  *         the read and the modify access.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  *          This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_SetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  GPIOx->BSRRL = GPIO_Pin;
+}
+
+/**
+  * @brief  Clears the selected data port bits.
+  * @note   This functions uses GPIOx_BSRR register to allow atomic read/modify 
+  *         accesses. In this way, there is no risk of an IRQ occurring between
+  *         the read and the modify access.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bits to be written.
+  *          This parameter can be any combination of GPIO_Pin_x where x can be (0..15).
+  * @retval None
+  */
+void GPIO_ResetBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN(GPIO_Pin));
+
+  GPIOx->BSRRH = GPIO_Pin;
+}
+
+/**
+  * @brief  Sets or clears the selected data port bit.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @param  GPIO_Pin: specifies the port bit to be written.
+  *          This parameter can be one of GPIO_Pin_x where x can be (0..15).
+  * @param  BitVal: specifies the value to be written to the selected bit.
+  *          This parameter can be one of the BitAction enum values:
+  *            @arg Bit_RESET: to clear the port pin
+  *            @arg Bit_SET: to set the port pin
+  * @retval None
+  */
+void GPIO_WriteBit(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin, BitAction BitVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GET_GPIO_PIN(GPIO_Pin));
+  assert_param(IS_GPIO_BIT_ACTION(BitVal));
+
+  if (BitVal != Bit_RESET)
+  {
+    GPIOx->BSRRL = GPIO_Pin;
+  }
+  else
+  {
+    GPIOx->BSRRH = GPIO_Pin ;
+  }
+}
+
+/**
+  * @brief  Writes data to the specified GPIO data port.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @param  PortVal: specifies the value to be written to the port output data register.
+  * @retval None
+  */
+void GPIO_Write(GPIO_TypeDef* GPIOx, uint16_t PortVal)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  GPIOx->ODR = PortVal;
+}
+
+/**
+  * @brief  Toggles the specified GPIO pins..
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @param  GPIO_Pin: Specifies the pins to be toggled.
+  * @retval None
+  */
+void GPIO_ToggleBits(GPIO_TypeDef* GPIOx, uint16_t GPIO_Pin)
+{
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+
+  GPIOx->ODR ^= GPIO_Pin;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup GPIO_Group3 GPIO Alternate functions configuration function
+ *  @brief   GPIO Alternate functions configuration function
+ *
+@verbatim   
+ ===============================================================================
+               GPIO Alternate functions configuration function
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Changes the mapping of the specified pin.
+  * @param  GPIOx: where x can be (A..I) to select the GPIO peripheral.
+  * @param  GPIO_PinSource: specifies the pin for the Alternate function.
+  *         This parameter can be GPIO_PinSourcex where x can be (0..15).
+  * @param  GPIO_AFSelection: selects the pin to used as Alternate function.
+  *          This parameter can be one of the following values:
+  *            @arg GPIO_AF_RTC_50Hz: Connect RTC_50Hz pin to AF0 (default after reset) 
+  *            @arg GPIO_AF_MCO: Connect MCO pin (MCO1 and MCO2) to AF0 (default after reset) 
+  *            @arg GPIO_AF_TAMPER: Connect TAMPER pins (TAMPER_1 and TAMPER_2) to AF0 (default after reset) 
+  *            @arg GPIO_AF_SWJ: Connect SWJ pins (SWD and JTAG)to AF0 (default after reset) 
+  *            @arg GPIO_AF_TRACE: Connect TRACE pins to AF0 (default after reset)
+  *            @arg GPIO_AF_TIM1: Connect TIM1 pins to AF1
+  *            @arg GPIO_AF_TIM2: Connect TIM2 pins to AF1
+  *            @arg GPIO_AF_TIM3: Connect TIM3 pins to AF2
+  *            @arg GPIO_AF_TIM4: Connect TIM4 pins to AF2
+  *            @arg GPIO_AF_TIM5: Connect TIM5 pins to AF2
+  *            @arg GPIO_AF_TIM8: Connect TIM8 pins to AF3
+  *            @arg GPIO_AF_TIM9: Connect TIM9 pins to AF3
+  *            @arg GPIO_AF_TIM10: Connect TIM10 pins to AF3
+  *            @arg GPIO_AF_TIM11: Connect TIM11 pins to AF3
+  *            @arg GPIO_AF_I2C1: Connect I2C1 pins to AF4
+  *            @arg GPIO_AF_I2C2: Connect I2C2 pins to AF4
+  *            @arg GPIO_AF_I2C3: Connect I2C3 pins to AF4
+  *            @arg GPIO_AF_SPI1: Connect SPI1 pins to AF5
+  *            @arg GPIO_AF_SPI2: Connect SPI2/I2S2 pins to AF5
+  *            @arg GPIO_AF_SPI3: Connect SPI3/I2S3 pins to AF6
+  *            @arg GPIO_AF_I2S3ext: Connect I2S3ext pins to AF7
+  *            @arg GPIO_AF_USART1: Connect USART1 pins to AF7
+  *            @arg GPIO_AF_USART2: Connect USART2 pins to AF7
+  *            @arg GPIO_AF_USART3: Connect USART3 pins to AF7
+  *            @arg GPIO_AF_UART4: Connect UART4 pins to AF8
+  *            @arg GPIO_AF_UART5: Connect UART5 pins to AF8
+  *            @arg GPIO_AF_USART6: Connect USART6 pins to AF8
+  *            @arg GPIO_AF_CAN1: Connect CAN1 pins to AF9
+  *            @arg GPIO_AF_CAN2: Connect CAN2 pins to AF9
+  *            @arg GPIO_AF_TIM12: Connect TIM12 pins to AF9
+  *            @arg GPIO_AF_TIM13: Connect TIM13 pins to AF9
+  *            @arg GPIO_AF_TIM14: Connect TIM14 pins to AF9
+  *            @arg GPIO_AF_OTG_FS: Connect OTG_FS pins to AF10
+  *            @arg GPIO_AF_OTG_HS: Connect OTG_HS pins to AF10
+  *            @arg GPIO_AF_ETH: Connect ETHERNET pins to AF11
+  *            @arg GPIO_AF_FSMC: Connect FSMC pins to AF12
+  *            @arg GPIO_AF_OTG_HS_FS: Connect OTG HS (configured in FS) pins to AF12
+  *            @arg GPIO_AF_SDIO: Connect SDIO pins to AF12
+  *            @arg GPIO_AF_DCMI: Connect DCMI pins to AF13
+  *            @arg GPIO_AF_EVENTOUT: Connect EVENTOUT pins to AF15
+  * @retval None
+  */
+void GPIO_PinAFConfig(GPIO_TypeDef* GPIOx, uint16_t GPIO_PinSource, uint8_t GPIO_AF)
+{
+  uint32_t temp = 0x00;
+  uint32_t temp_2 = 0x00;
+  
+  /* Check the parameters */
+  assert_param(IS_GPIO_ALL_PERIPH(GPIOx));
+  assert_param(IS_GPIO_PIN_SOURCE(GPIO_PinSource));
+  assert_param(IS_GPIO_AF(GPIO_AF));
+  
+  temp = ((uint32_t)(GPIO_AF) << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
+  GPIOx->AFR[GPIO_PinSource >> 0x03] &= ~((uint32_t)0xF << ((uint32_t)((uint32_t)GPIO_PinSource & (uint32_t)0x07) * 4)) ;
+  temp_2 = GPIOx->AFR[GPIO_PinSource >> 0x03] | temp;
+  GPIOx->AFR[GPIO_PinSource >> 0x03] = temp_2;
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c
new file mode 100644
index 0000000000..74ac51cde8
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash.c
@@ -0,0 +1,700 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hash.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the HASH / HMAC Processor (HASH) peripheral:           
+  *           - Initialization and Configuration functions
+  *           - Message Digest generation functions
+  *           - context swapping functions   
+  *           - DMA interface function       
+  *           - Interrupts and flags management       
+  *         
+  *  @verbatim
+  *                               
+  *          ===================================================================      
+  *                                   How to use this driver
+  *          ===================================================================
+  *          HASH operation : 
+  *          ----------------                   
+  *         1. Enable the HASH controller clock using 
+  *            RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE) function.
+  *           
+  *         2. Initialise the HASH using HASH_Init() function. 
+  *               
+  *         3 . Reset the HASH processor core, so that the HASH will be ready 
+  *             to compute he message digest of a new message by using 
+  *             HASH_Reset() function.
+  *
+  *         4. Enable the HASH controller using the HASH_Cmd() function. 
+  *                
+  *         5. if using DMA for Data input transfer, Activate the DMA Request 
+  *            using HASH_DMACmd() function 
+  *                    
+  *         6. if DMA is not used for data transfer, use HASH_DataIn() function 
+  *            to enter data to IN FIFO.
+  *             
+  *          
+  *         7. Configure the Number of valid bits in last word of the message 
+  *            using HASH_SetLastWordValidBitsNbr() function.
+  *             
+  *         8. if the message length is not an exact multiple of 512 bits, 
+  *            then the function HASH_StartDigest() must be called to 
+  *            launch the computation of the final digest.     
+  *             
+  *         9. Once computed, the digest can be read using HASH_GetDigest() 
+  *            function.         
+  *                   
+  *        10. To control HASH events you can use one of the following 
+  *              two methods:
+  *               a- Check on HASH flags using the HASH_GetFlagStatus() function.  
+  *               b- Use HASH interrupts through the function HASH_ITConfig() at 
+  *                  initialization phase and HASH_GetITStatus() function into 
+  *                  interrupt routines in hashing phase.
+  *          After checking on a flag you should clear it using HASH_ClearFlag()
+  *          function. And after checking on an interrupt event you should 
+  *          clear it using HASH_ClearITPendingBit() function.     
+  *                     
+  *        11. Save and restore hash processor context using 
+  *            HASH_SaveContext() and HASH_RestoreContext() functions.     
+  *              
+  *
+  *            
+  *          HMAC operation : 
+  *          ----------------  
+  *          The HMAC algorithm is used for message authentication, by 
+  *          irreversibly binding the message being processed to a key chosen 
+  *          by the user. 
+  *          For HMAC specifications, refer to "HMAC: keyed-hashing for message 
+  *          authentication, H. Krawczyk, M. Bellare, R. Canetti, February 1997"
+  *          
+  *          Basically, the HMAC algorithm consists of two nested hash operations:
+  *          HMAC(message) = Hash[((key | pad) XOR 0x5C) | Hash(((key | pad) XOR 0x36) | message)]
+  *          where:
+  *          - "pad" is a sequence of zeroes needed to extend the key to the 
+  *                  length of the underlying hash function data block (that is 
+  *                  512 bits for both the SHA-1 and MD5 hash algorithms)
+  *          - "|"   represents the concatenation operator 
+  *          
+  *         
+  *         To compute the HMAC, four different phases are required:
+  *                    
+  *         1.  Initialise the HASH using HASH_Init() function to do HMAC 
+  *             operation. 
+  *                
+  *         2.  The key (to be used for the inner hash function) is then given 
+  *             to the core. This operation follows the same mechanism as the 
+  *             one used to send the message in the hash operation (that is, 
+  *             by HASH_DataIn() function and, finally, 
+  *             HASH_StartDigest() function.
+  *          
+  *         3.  Once the last word has been entered and computation has started, 
+  *             the hash processor elaborates the key. It is then ready to 
+  *             accept the message text using the same mechanism as the one 
+  *             used to send the message in the hash operation.
+  *       
+  *         4.  After the first hash round, the hash processor returns "ready" 
+  *             to indicate that it is ready to receive the key to be used for 
+  *             the outer hash function (normally, this key is the same as the 
+  *             one used for the inner hash function). When the last word of 
+  *             the key is entered and computation starts, the HMAC result is 
+  *             made available using HASH_GetDigest() function.
+  *               
+  *              
+  *  @endverbatim
+  *         
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************  
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hash.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup HASH 
+  * @brief HASH driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/ 
+
+/** @defgroup HASH_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup HASH_Group1 Initialization and Configuration functions
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+                      Initialization and Configuration functions
+ ===============================================================================  
+  This section provides functions allowing to 
+   - Initialize the HASH peripheral
+   - Configure the HASH Processor 
+      - MD5/SHA1, 
+      - HASH/HMAC, 
+      - datatype 
+      - HMAC Key (if mode = HMAC)
+   - Reset the HASH Processor 
+   
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Deinitializes the HASH peripheral registers to their default reset values
+  * @param  None
+  * @retval None
+  */
+void HASH_DeInit(void)
+{
+  /* Enable HASH reset state */
+  RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, ENABLE);
+  /* Release HASH from reset state */
+  RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_HASH, DISABLE);
+}
+
+/**
+  * @brief  Initializes the HASH peripheral according to the specified parameters
+  *         in the HASH_InitStruct structure.
+  * @note   the hash processor is reset when calling this function so that the
+  *         HASH will be ready to compute the message digest of a new message.
+  *         There is no need to call HASH_Reset() function.           
+  * @param  HASH_InitStruct: pointer to a HASH_InitTypeDef structure that contains
+  *         the configuration information for the HASH peripheral.
+  * @note   The field HASH_HMACKeyType in HASH_InitTypeDef must be filled only 
+  *          if the algorithm mode is HMAC.       
+  * @retval None
+  */
+void HASH_Init(HASH_InitTypeDef* HASH_InitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_HASH_ALGOSELECTION(HASH_InitStruct->HASH_AlgoSelection));
+  assert_param(IS_HASH_DATATYPE(HASH_InitStruct->HASH_DataType));
+  assert_param(IS_HASH_ALGOMODE(HASH_InitStruct->HASH_AlgoMode));
+  
+  /* Configure the Algorithm used, algorithm mode and the datatype */
+  HASH->CR &= ~ (HASH_CR_ALGO | HASH_CR_DATATYPE | HASH_CR_MODE);
+  HASH->CR |= (HASH_InitStruct->HASH_AlgoSelection | \
+               HASH_InitStruct->HASH_DataType | \
+               HASH_InitStruct->HASH_AlgoMode);
+  
+  /* if algorithm mode is HMAC, set the Key */  
+  if(HASH_InitStruct->HASH_AlgoMode == HASH_AlgoMode_HMAC) 
+  {
+    assert_param(IS_HASH_HMAC_KEYTYPE(HASH_InitStruct->HASH_HMACKeyType));
+    HASH->CR &= ~HASH_CR_LKEY;
+    HASH->CR |= HASH_InitStruct->HASH_HMACKeyType;
+  }
+
+  /* Reset the HASH processor core, so that the HASH will be ready to compute 
+     the message digest of a new message */
+  HASH->CR |= HASH_CR_INIT;  
+}
+
+/**
+  * @brief  Fills each HASH_InitStruct member with its default value.
+  * @param  HASH_InitStruct : pointer to a HASH_InitTypeDef structure which will
+  *          be initialized.  
+  *  @note  The default values set are : Processor mode is HASH, Algorithm selected is SHA1,
+  *          Data type selected is 32b and HMAC Key Type is short key.  
+  * @retval None
+  */
+void HASH_StructInit(HASH_InitTypeDef* HASH_InitStruct)
+{
+  /* Initialize the HASH_AlgoSelection member */
+  HASH_InitStruct->HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
+
+  /* Initialize the HASH_AlgoMode member */
+  HASH_InitStruct->HASH_AlgoMode = HASH_AlgoMode_HASH;
+
+  /* Initialize the HASH_DataType member */
+  HASH_InitStruct->HASH_DataType = HASH_DataType_32b;
+
+  /* Initialize the HASH_HMACKeyType member */
+  HASH_InitStruct->HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
+}
+
+/**
+  * @brief  Resets the HASH processor core, so that the HASH will be ready
+  *         to compute the message digest of a new message.
+  * @note   Calling this function will clear the HASH_SR_DCIS (Digest calculation 
+  *         completion interrupt status) bit corresponding to HASH_IT_DCI 
+  *         interrupt and HASH_FLAG_DCIS flag. 
+  * @param  None
+  * @retval None
+  */
+void HASH_Reset(void)
+{
+  /* Reset the HASH processor core */
+  HASH->CR |= HASH_CR_INIT;
+}
+/**
+  * @}
+  */
+ 
+/** @defgroup HASH_Group2 Message Digest generation functions
+ *  @brief    Message Digest generation functions
+ *
+@verbatim    
+ ===============================================================================
+                      Message Digest generation functions
+ ===============================================================================  
+  This section provides functions allowing the generation of message digest: 
+  - Push data in the IN FIFO : using HASH_DataIn()
+  - Get the number of words set in IN FIFO, use HASH_GetInFIFOWordsNbr()  
+  - set the last word valid bits number using HASH_SetLastWordValidBitsNbr() 
+  - start digest calculation : using HASH_StartDigest()
+  - Get the Digest message : using HASH_GetDigest()
+ 
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Configure the Number of valid bits in last word of the message
+  * @param  ValidNumber: Number of valid bits in last word of the message.
+  *           This parameter must be a number between 0 and 0x1F.
+  *             - 0x00: All 32 bits of the last data written are valid
+  *             - 0x01: Only bit [0] of the last data written is valid
+  *             - 0x02: Only bits[1:0] of the last data written are valid
+  *             - 0x03: Only bits[2:0] of the last data written are valid
+  *             - ...
+  *             - 0x1F: Only bits[30:0] of the last data written are valid    
+  * @note   The Number of valid bits must be set before to start the message 
+  *         digest competition (in Hash and HMAC) and key treatment(in HMAC).    
+  * @retval None
+  */
+void HASH_SetLastWordValidBitsNbr(uint16_t ValidNumber)
+{
+  /* Check the parameters */
+  assert_param(IS_HASH_VALIDBITSNUMBER(ValidNumber));
+  
+  /* Configure the Number of valid bits in last word of the message */
+  HASH->STR &= ~(HASH_STR_NBW);
+  HASH->STR |= ValidNumber;
+}
+
+/**
+  * @brief  Writes data in the Data Input FIFO
+  * @param  Data: new data of the message to be processed.
+  * @retval None
+  */
+void HASH_DataIn(uint32_t Data)
+{
+  /* Write in the DIN register a new data */
+  HASH->DIN = Data;
+}
+
+/**
+  * @brief  Returns the number of words already pushed into the IN FIFO.
+  * @param  None
+  * @retval The value of words already pushed into the IN FIFO.
+  */
+uint8_t HASH_GetInFIFOWordsNbr(void)
+{
+  /* Return the value of NBW bits */
+  return ((HASH->CR & HASH_CR_NBW) >> 8);
+}
+
+/**
+  * @brief  Provides the message digest result.
+  * @note   In MD5 mode, Data[4] filed of HASH_MsgDigest structure is not used
+  *         and is read as zero.  
+  * @param  HASH_MessageDigest: pointer to a HASH_MsgDigest structure which will 
+  *         hold the message digest result 
+  * @retval None
+  */
+void HASH_GetDigest(HASH_MsgDigest* HASH_MessageDigest)
+{
+  /* Get the data field */
+  HASH_MessageDigest->Data[0] = HASH->HR[0];
+  HASH_MessageDigest->Data[1] = HASH->HR[1];
+  HASH_MessageDigest->Data[2] = HASH->HR[2];
+  HASH_MessageDigest->Data[3] = HASH->HR[3];
+  HASH_MessageDigest->Data[4] = HASH->HR[4];
+}
+
+/**
+  * @brief  Starts the message padding and calculation of the final message     
+  * @param  None
+  * @retval None
+  */
+void HASH_StartDigest(void)
+{
+  /* Start the Digest calculation */
+  HASH->STR |= HASH_STR_DCAL;
+}
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Group3 Context swapping functions
+ *  @brief   Context swapping functions
+ *
+@verbatim   
+ ===============================================================================
+                             Context swapping functions
+ ===============================================================================  
+
+  This section provides functions allowing to save and store HASH Context
+  
+  It is possible to interrupt a HASH/HMAC process to perform another processing 
+  with a higher priority, and to complete the interrupted process later on, when 
+  the higher priority task is complete. To do so, the context of the interrupted 
+  task must be saved from the HASH registers to memory, and then be restored 
+  from memory to the HASH registers.
+  
+  1. To save the current context, use HASH_SaveContext() function
+  2. To restore the saved context, use HASH_RestoreContext() function 
+  
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Save the Hash peripheral Context. 
+  * @note   The context can be saved only when no block is currently being 
+  *         processed. So user must wait for DINIS = 1 (the last block has been 
+  *         processed and the input FIFO is empty) or NBW != 0 (the FIFO is not 
+  *         full and no processing is ongoing).   
+  * @param  HASH_ContextSave: pointer to a HASH_Context structure that contains
+  *         the repository for current context.
+  * @retval None
+  */
+void HASH_SaveContext(HASH_Context* HASH_ContextSave)
+{
+  uint8_t i = 0;
+  
+  /* save context registers */
+  HASH_ContextSave->HASH_IMR = HASH->IMR;  
+  HASH_ContextSave->HASH_STR = HASH->STR;      
+  HASH_ContextSave->HASH_CR  = HASH->CR;     
+  for(i=0; i<=50;i++)
+  {
+     HASH_ContextSave->HASH_CSR[i] = HASH->CSR[i];
+  }   
+}
+
+/**
+  * @brief  Restore the Hash peripheral Context.  
+  * @note   After calling this function, user can restart the processing from the
+  *         point where it has been interrupted.  
+  * @param  HASH_ContextRestore: pointer to a HASH_Context structure that contains
+  *         the repository for saved context.
+  * @retval None
+  */
+void HASH_RestoreContext(HASH_Context* HASH_ContextRestore)  
+{
+  uint8_t i = 0;
+  
+  /* restore context registers */
+  HASH->IMR = HASH_ContextRestore->HASH_IMR;   
+  HASH->STR = HASH_ContextRestore->HASH_STR;     
+  HASH->CR = HASH_ContextRestore->HASH_CR;
+  
+  /* Initialize the hash processor */
+  HASH->CR |= HASH_CR_INIT; 
+  
+   /* continue restoring context registers */     
+  for(i=0; i<=50;i++)
+  {
+     HASH->CSR[i] = HASH_ContextRestore->HASH_CSR[i];
+  }   
+}
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Group4 HASH's DMA interface Configuration function
+ *  @brief   HASH's DMA interface Configuration function 
+ *
+@verbatim   
+ ===============================================================================
+                   HASH's DMA interface Configuration function
+ ===============================================================================  
+
+  This section provides functions allowing to configure the DMA interface for 
+  HASH/ HMAC data input transfer.
+   
+  When the DMA mode is enabled (using the HASH_DMACmd() function), data can be 
+  sent to the IN FIFO using the DMA peripheral.
+
+
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Enables or disables the HASH DMA interface.
+  * @note   The DMA is disabled by hardware after the end of transfer.
+  * @param  NewState: new state of the selected HASH DMA transfer request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void HASH_DMACmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the HASH DMA request */
+    HASH->CR |= HASH_CR_DMAE;
+  }
+  else
+  {
+    /* Disable the HASH DMA request */
+    HASH->CR &= ~HASH_CR_DMAE;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup HASH_Group5 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+                   Interrupts and flags management functions
+ ===============================================================================  
+
+  This section provides functions allowing to configure the HASH Interrupts and 
+  to get the status and clear flags and Interrupts pending bits.
+  
+  The HASH provides 2 Interrupts sources and 5 Flags:
+  
+  Flags :
+  ---------- 
+     1. HASH_FLAG_DINIS : set when 16 locations are free in the Data IN FIFO 
+                          which means that a  new block (512 bit) can be entered 
+                          into the input buffer.
+                          
+     2. HASH_FLAG_DCIS :  set when Digest calculation is complete
+      
+     3. HASH_FLAG_DMAS :  set when HASH's DMA interface is enabled (DMAE=1) or 
+                          a transfer is ongoing.
+                          This Flag is cleared only by hardware.
+                           
+     4. HASH_FLAG_BUSY :  set when The hash core is processing a block of data
+                          This Flag is cleared only by hardware. 
+                           
+     5. HASH_FLAG_DINNE : set when Data IN FIFO is not empty which means that 
+                          the Data IN FIFO contains at least one word of data.
+                          This Flag is cleared only by hardware.
+     
+  Interrupts :
+  ------------
+    
+   1. HASH_IT_DINI  : if enabled, this interrupt source is pending when 16 
+                      locations are free in the Data IN FIFO  which means that 
+                      a new block (512 bit) can be entered into the input buffer.
+                      This interrupt source is cleared using 
+                      HASH_ClearITPendingBit(HASH_IT_DINI) function.
+   
+   2. HASH_IT_DCI   : if enabled, this interrupt source is pending when Digest 
+                      calculation is complete.
+                      This interrupt source is cleared using 
+                      HASH_ClearITPendingBit(HASH_IT_DCI) function.
+
+  Managing the HASH controller events :
+  ------------------------------------ 
+  The user should identify which mode will be used in his application to manage 
+  the HASH controller events: Polling mode or Interrupt mode.
+  
+  1.  In the Polling Mode it is advised to use the following functions:
+      - HASH_GetFlagStatus() : to check if flags events occur. 
+      - HASH_ClearFlag()     : to clear the flags events.
+    
+  2.  In the Interrupt Mode it is advised to use the following functions:
+      - HASH_ITConfig()       : to enable or disable the interrupt source.
+      - HASH_GetITStatus()    : to check if Interrupt occurs.
+      - HASH_ClearITPendingBit() : to clear the Interrupt pending Bit 
+                                (corresponding Flag). 
+
+@endverbatim
+  * @{
+  */ 
+  
+/**
+  * @brief  Enables or disables the specified HASH interrupts.
+  * @param  HASH_IT: specifies the HASH interrupt source to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg HASH_IT_DINI: Data Input interrupt
+  *            @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
+  * @param  NewState: new state of the specified HASH interrupt.
+  *           This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void HASH_ITConfig(uint8_t HASH_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_HASH_IT(HASH_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected HASH interrupt */
+    HASH->IMR |= HASH_IT;
+  }
+  else
+  {
+    /* Disable the selected HASH interrupt */
+    HASH->IMR &= (uint8_t) ~HASH_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified HASH flag is set or not.
+  * @param  HASH_FLAG: specifies the HASH flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg HASH_FLAG_DINIS: Data input interrupt status flag
+  *            @arg HASH_FLAG_DCIS: Digest calculation completion interrupt status flag
+  *            @arg HASH_FLAG_BUSY: Busy flag
+  *            @arg HASH_FLAG_DMAS: DMAS Status flag
+  *            @arg HASH_FLAG_DINNE: Data Input register (DIN) not empty status flag
+  * @retval The new state of HASH_FLAG (SET or RESET)
+  */
+FlagStatus HASH_GetFlagStatus(uint16_t HASH_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tempreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_HASH_GET_FLAG(HASH_FLAG));
+
+  /* check if the FLAG is in CR register */
+  if ((HASH_FLAG & HASH_FLAG_DINNE) != (uint16_t)RESET ) 
+  {
+    tempreg = HASH->CR;
+  }
+  else /* The FLAG is in SR register */
+  {
+    tempreg = HASH->SR;
+  }
+
+  /* Check the status of the specified HASH flag */
+  if ((tempreg & HASH_FLAG) != (uint16_t)RESET)
+  {
+    /* HASH is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* HASH_FLAG is reset */
+    bitstatus = RESET;
+  }
+
+  /* Return the HASH_FLAG status */
+  return  bitstatus;
+}
+/**
+  * @brief  Clears the HASH flags.
+  * @param  HASH_FLAG: specifies the flag to clear. 
+  *          This parameter can be any combination of the following values:
+  *            @arg HASH_FLAG_DINIS: Data Input Flag
+  *            @arg HASH_FLAG_DCIS: Digest Calculation Completion Flag                       
+  * @retval None
+  */
+void HASH_ClearFlag(uint16_t HASH_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_HASH_CLEAR_FLAG(HASH_FLAG));
+  
+  /* Clear the selected HASH flags */
+  HASH->SR = ~(uint32_t)HASH_FLAG;
+}
+/**
+  * @brief  Checks whether the specified HASH interrupt has occurred or not.
+  * @param  HASH_IT: specifies the HASH interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg HASH_IT_DINI: Data Input interrupt
+  *            @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
+  * @retval The new state of HASH_IT (SET or RESET).
+  */
+ITStatus HASH_GetITStatus(uint8_t HASH_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_HASH_GET_IT(HASH_IT));  
+
+
+  /* Check the status of the specified HASH interrupt */
+  tmpreg =  HASH->SR;
+
+  if (((HASH->IMR & tmpreg) & HASH_IT) != RESET)
+  {
+    /* HASH_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* HASH_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the HASH_IT status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the HASH interrupt pending bit(s).
+  * @param  HASH_IT: specifies the HASH interrupt pending bit(s) to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg HASH_IT_DINI: Data Input interrupt
+  *            @arg HASH_IT_DCI: Digest Calculation Completion Interrupt
+  * @retval None
+  */
+void HASH_ClearITPendingBit(uint8_t HASH_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_HASH_IT(HASH_IT));
+
+  /* Clear the selected HASH interrupt pending bit */
+  HASH->SR = (uint8_t)~HASH_IT;
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c
new file mode 100644
index 0000000000..fb7e6856f7
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_hash_md5.c
@@ -0,0 +1,314 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_hash_md5.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides high level functions to compute the HASH MD5 and
+  *          HMAC MD5 Digest of an input message.
+  *          It uses the stm32f4xx_hash.c/.h drivers to access the STM32F4xx HASH
+  *          peripheral.
+  *
+  *  @verbatim
+  *    
+  *          ===================================================================
+  *                                   How to use this driver
+  *          ===================================================================
+  *          1. Enable The HASH controller clock using 
+  *            RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_HASH, ENABLE); function.
+  *
+  *          2. Calculate the HASH MD5 Digest using HASH_MD5() function.
+  *
+  *          3. Calculate the HMAC MD5 Digest using HMAC_MD5() function.
+  *
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hash.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup HASH 
+  * @brief HASH driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define MD5BUSY_TIMEOUT    ((uint32_t) 0x00010000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HASH_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup HASH_Group7 High Level MD5 functions
+ *  @brief   High Level MD5 Hash and HMAC functions 
+ *
+@verbatim   
+ ===============================================================================
+                          High Level MD5 Hash and HMAC functions
+ ===============================================================================
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Compute the HASH MD5 digest.
+  * @param  Input: pointer to the Input buffer to be treated.
+  * @param  Ilen: length of the Input buffer.
+  * @param  Output: the returned digest
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: digest computation done
+  *          - ERROR: digest computation failed
+  */
+ErrorStatus HASH_MD5(uint8_t *Input, uint32_t Ilen, uint8_t Output[16])
+{
+  HASH_InitTypeDef MD5_HASH_InitStructure;
+  HASH_MsgDigest MD5_MessageDigest;
+  __IO uint16_t nbvalidbitsdata = 0;
+  uint32_t i = 0;
+  __IO uint32_t counter = 0;
+  uint32_t busystatus = 0;
+  ErrorStatus status = SUCCESS;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+
+
+  /* Number of valid bits in last word of the Input data */
+  nbvalidbitsdata = 8 * (Ilen % 4);
+
+  /* HASH peripheral initialization */
+  HASH_DeInit();
+
+  /* HASH Configuration */
+  MD5_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_MD5;
+  MD5_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH;
+  MD5_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
+  HASH_Init(&MD5_HASH_InitStructure);
+
+  /* Configure the number of valid bits in last word of the data */
+  HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
+
+  /* Write the Input block in the IN FIFO */
+  for(i=0; i 64)
+  {
+    /* HMAC long Key */
+    MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey;
+  }
+  else
+  {
+    /* HMAC short Key */
+    MD5_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
+  }
+  HASH_Init(&MD5_HASH_InitStructure);
+
+  /* Configure the number of valid bits in last word of the Key */
+  HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
+
+  /* Write the Key */
+  for(i=0; i
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_hash.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup HASH 
+  * @brief HASH driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+#define SHA1BUSY_TIMEOUT    ((uint32_t) 0x00010000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup HASH_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup HASH_Group6 High Level SHA1 functions
+ *  @brief   High Level SHA1 Hash and HMAC functions 
+ *
+@verbatim   
+ ===============================================================================
+                          High Level SHA1 Hash and HMAC functions
+ ===============================================================================
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Compute the HASH SHA1 digest.
+  * @param  Input: pointer to the Input buffer to be treated.
+  * @param  Ilen: length of the Input buffer.
+  * @param  Output: the returned digest
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: digest computation done
+  *          - ERROR: digest computation failed
+  */
+ErrorStatus HASH_SHA1(uint8_t *Input, uint32_t Ilen, uint8_t Output[20])
+{
+  HASH_InitTypeDef SHA1_HASH_InitStructure;
+  HASH_MsgDigest SHA1_MessageDigest;
+  __IO uint16_t nbvalidbitsdata = 0;
+  uint32_t i = 0;
+  __IO uint32_t counter = 0;
+  uint32_t busystatus = 0;
+  ErrorStatus status = SUCCESS;
+  uint32_t inputaddr  = (uint32_t)Input;
+  uint32_t outputaddr = (uint32_t)Output;
+
+  /* Number of valid bits in last word of the Input data */
+  nbvalidbitsdata = 8 * (Ilen % 4);
+
+  /* HASH peripheral initialization */
+  HASH_DeInit();
+
+  /* HASH Configuration */
+  SHA1_HASH_InitStructure.HASH_AlgoSelection = HASH_AlgoSelection_SHA1;
+  SHA1_HASH_InitStructure.HASH_AlgoMode = HASH_AlgoMode_HASH;
+  SHA1_HASH_InitStructure.HASH_DataType = HASH_DataType_8b;
+  HASH_Init(&SHA1_HASH_InitStructure);
+
+  /* Configure the number of valid bits in last word of the data */
+  HASH_SetLastWordValidBitsNbr(nbvalidbitsdata);
+
+  /* Write the Input block in the IN FIFO */
+  for(i=0; i 64)
+  {
+    /* HMAC long Key */
+    SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_LongKey;
+  }
+  else
+  {
+    /* HMAC short Key */
+    SHA1_HASH_InitStructure.HASH_HMACKeyType = HASH_HMACKeyType_ShortKey;
+  }
+  HASH_Init(&SHA1_HASH_InitStructure);
+
+  /* Configure the number of valid bits in last word of the Key */
+  HASH_SetLastWordValidBitsNbr(nbvalidbitskey);
+
+  /* Write the Key */
+  for(i=0; iGPIO_Mode = GPIO_Mode_AF
+  *                 - Select the type, pull-up/pull-down and output speed via 
+  *                   GPIO_PuPd, GPIO_OType and GPIO_Speed members
+  *                 - Call GPIO_Init() function
+  *                 Recommended configuration is Push-Pull, Pull-up, Open-Drain.
+  *                 Add an external pull up if necessary (typically 4.7 KOhm).      
+  *        
+  *          4. Program the Mode, duty cycle , Own address, Ack, Speed and Acknowledged
+  *             Address using the I2C_Init() function.
+  *
+  *          5. Optionally you can enable/configure the following parameters without
+  *             re-initialization (i.e there is no need to call again I2C_Init() function):
+  *              - Enable the acknowledge feature using I2C_AcknowledgeConfig() function
+  *              - Enable the dual addressing mode using I2C_DualAddressCmd() function
+  *              - Enable the general call using the I2C_GeneralCallCmd() function
+  *              - Enable the clock stretching using I2C_StretchClockCmd() function
+  *              - Enable the fast mode duty cycle using the I2C_FastModeDutyCycleConfig()
+  *                function.
+  *              - Configure the NACK position for Master Receiver mode in case of 
+  *                2 bytes reception using the function I2C_NACKPositionConfig().  
+  *              - Enable the PEC Calculation using I2C_CalculatePEC() function
+  *              - For SMBus Mode: 
+  *                   - Enable the Address Resolution Protocol (ARP) using I2C_ARPCmd() function
+  *                   - Configure the SMBusAlert pin using I2C_SMBusAlertConfig() function
+  *
+  *          6. Enable the NVIC and the corresponding interrupt using the function 
+  *             I2C_ITConfig() if you need to use interrupt mode. 
+  *
+  *          7. When using the DMA mode 
+  *                   - Configure the DMA using DMA_Init() function
+  *                   - Active the needed channel Request using I2C_DMACmd() or
+  *                     I2C_DMALastTransferCmd() function.
+  *              @note When using DMA mode, I2C interrupts may be used at the same time to
+  *                    control the communication flow (Start/Stop/Ack... events and errors).
+  * 
+  *          8. Enable the I2C using the I2C_Cmd() function.
+  * 
+  *          9. Enable the DMA using the DMA_Cmd() function when using DMA mode in the 
+  *             transfers. 
+  *
+  *  @endverbatim
+  *  
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************  
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_i2c.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup I2C 
+  * @brief I2C driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+#define CR1_CLEAR_MASK    ((uint16_t)0xFBF5)      /*I2C_ClockSpeed));
+  assert_param(IS_I2C_MODE(I2C_InitStruct->I2C_Mode));
+  assert_param(IS_I2C_DUTY_CYCLE(I2C_InitStruct->I2C_DutyCycle));
+  assert_param(IS_I2C_OWN_ADDRESS1(I2C_InitStruct->I2C_OwnAddress1));
+  assert_param(IS_I2C_ACK_STATE(I2C_InitStruct->I2C_Ack));
+  assert_param(IS_I2C_ACKNOWLEDGE_ADDRESS(I2C_InitStruct->I2C_AcknowledgedAddress));
+
+/*---------------------------- I2Cx CR2 Configuration ------------------------*/
+  /* Get the I2Cx CR2 value */
+  tmpreg = I2Cx->CR2;
+  /* Clear frequency FREQ[5:0] bits */
+  tmpreg &= (uint16_t)~((uint16_t)I2C_CR2_FREQ);
+  /* Get pclk1 frequency value */
+  RCC_GetClocksFreq(&rcc_clocks);
+  pclk1 = rcc_clocks.PCLK1_Frequency;
+  /* Set frequency bits depending on pclk1 value */
+  freqrange = (uint16_t)(pclk1 / 1000000);
+  tmpreg |= freqrange;
+  /* Write to I2Cx CR2 */
+  I2Cx->CR2 = tmpreg;
+
+/*---------------------------- I2Cx CCR Configuration ------------------------*/
+  /* Disable the selected I2C peripheral to configure TRISE */
+  I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);
+  /* Reset tmpreg value */
+  /* Clear F/S, DUTY and CCR[11:0] bits */
+  tmpreg = 0;
+
+  /* Configure speed in standard mode */
+  if (I2C_InitStruct->I2C_ClockSpeed <= 100000)
+  {
+    /* Standard mode speed calculate */
+    result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed << 1));
+    /* Test if CCR value is under 0x4*/
+    if (result < 0x04)
+    {
+      /* Set minimum allowed value */
+      result = 0x04;  
+    }
+    /* Set speed value for standard mode */
+    tmpreg |= result;	  
+    /* Set Maximum Rise Time for standard mode */
+    I2Cx->TRISE = freqrange + 1; 
+  }
+  /* Configure speed in fast mode */
+  /* To use the I2C at 400 KHz (in fast mode), the PCLK1 frequency (I2C peripheral
+     input clock) must be a multiple of 10 MHz */
+  else /*(I2C_InitStruct->I2C_ClockSpeed <= 400000)*/
+  {
+    if (I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_2)
+    {
+      /* Fast mode speed calculate: Tlow/Thigh = 2 */
+      result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 3));
+    }
+    else /*I2C_InitStruct->I2C_DutyCycle == I2C_DutyCycle_16_9*/
+    {
+      /* Fast mode speed calculate: Tlow/Thigh = 16/9 */
+      result = (uint16_t)(pclk1 / (I2C_InitStruct->I2C_ClockSpeed * 25));
+      /* Set DUTY bit */
+      result |= I2C_DutyCycle_16_9;
+    }
+
+    /* Test if CCR value is under 0x1*/
+    if ((result & I2C_CCR_CCR) == 0)
+    {
+      /* Set minimum allowed value */
+      result |= (uint16_t)0x0001;  
+    }
+    /* Set speed value and set F/S bit for fast mode */
+    tmpreg |= (uint16_t)(result | I2C_CCR_FS);
+    /* Set Maximum Rise Time for fast mode */
+    I2Cx->TRISE = (uint16_t)(((freqrange * (uint16_t)300) / (uint16_t)1000) + (uint16_t)1);  
+  }
+
+  /* Write to I2Cx CCR */
+  I2Cx->CCR = tmpreg;
+  /* Enable the selected I2C peripheral */
+  I2Cx->CR1 |= I2C_CR1_PE;
+
+/*---------------------------- I2Cx CR1 Configuration ------------------------*/
+  /* Get the I2Cx CR1 value */
+  tmpreg = I2Cx->CR1;
+  /* Clear ACK, SMBTYPE and  SMBUS bits */
+  tmpreg &= CR1_CLEAR_MASK;
+  /* Configure I2Cx: mode and acknowledgement */
+  /* Set SMBTYPE and SMBUS bits according to I2C_Mode value */
+  /* Set ACK bit according to I2C_Ack value */
+  tmpreg |= (uint16_t)((uint32_t)I2C_InitStruct->I2C_Mode | I2C_InitStruct->I2C_Ack);
+  /* Write to I2Cx CR1 */
+  I2Cx->CR1 = tmpreg;
+
+/*---------------------------- I2Cx OAR1 Configuration -----------------------*/
+  /* Set I2Cx Own Address1 and acknowledged address */
+  I2Cx->OAR1 = (I2C_InitStruct->I2C_AcknowledgedAddress | I2C_InitStruct->I2C_OwnAddress1);
+}
+
+/**
+  * @brief  Fills each I2C_InitStruct member with its default value.
+  * @param  I2C_InitStruct: pointer to an I2C_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void I2C_StructInit(I2C_InitTypeDef* I2C_InitStruct)
+{
+/*---------------- Reset I2C init structure parameters values ----------------*/
+  /* initialize the I2C_ClockSpeed member */
+  I2C_InitStruct->I2C_ClockSpeed = 5000;
+  /* Initialize the I2C_Mode member */
+  I2C_InitStruct->I2C_Mode = I2C_Mode_I2C;
+  /* Initialize the I2C_DutyCycle member */
+  I2C_InitStruct->I2C_DutyCycle = I2C_DutyCycle_2;
+  /* Initialize the I2C_OwnAddress1 member */
+  I2C_InitStruct->I2C_OwnAddress1 = 0;
+  /* Initialize the I2C_Ack member */
+  I2C_InitStruct->I2C_Ack = I2C_Ack_Disable;
+  /* Initialize the I2C_AcknowledgedAddress member */
+  I2C_InitStruct->I2C_AcknowledgedAddress = I2C_AcknowledgedAddress_7bit;
+}
+
+/**
+  * @brief  Enables or disables the specified I2C peripheral.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx peripheral. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_Cmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C peripheral */
+    I2Cx->CR1 |= I2C_CR1_PE;
+  }
+  else
+  {
+    /* Disable the selected I2C peripheral */
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PE);
+  }
+}
+
+/**
+  * @brief  Generates I2Cx communication START condition.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C START condition generation.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void I2C_GenerateSTART(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Generate a START condition */
+    I2Cx->CR1 |= I2C_CR1_START;
+  }
+  else
+  {
+    /* Disable the START condition generation */
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_START);
+  }
+}
+
+/**
+  * @brief  Generates I2Cx communication STOP condition.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C STOP condition generation.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void I2C_GenerateSTOP(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Generate a STOP condition */
+    I2Cx->CR1 |= I2C_CR1_STOP;
+  }
+  else
+  {
+    /* Disable the STOP condition generation */
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_STOP);
+  }
+}
+
+/**
+  * @brief  Transmits the address byte to select the slave device.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  Address: specifies the slave address which will be transmitted
+  * @param  I2C_Direction: specifies whether the I2C device will be a Transmitter
+  *         or a Receiver. 
+  *          This parameter can be one of the following values
+  *            @arg I2C_Direction_Transmitter: Transmitter mode
+  *            @arg I2C_Direction_Receiver: Receiver mode
+  * @retval None.
+  */
+void I2C_Send7bitAddress(I2C_TypeDef* I2Cx, uint8_t Address, uint8_t I2C_Direction)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_DIRECTION(I2C_Direction));
+  /* Test on the direction to set/reset the read/write bit */
+  if (I2C_Direction != I2C_Direction_Transmitter)
+  {
+    /* Set the address bit0 for read */
+    Address |= I2C_OAR1_ADD0;
+  }
+  else
+  {
+    /* Reset the address bit0 for write */
+    Address &= (uint8_t)~((uint8_t)I2C_OAR1_ADD0);
+  }
+  /* Send the address */
+  I2Cx->DR = Address;
+}
+
+/**
+  * @brief  Enables or disables the specified I2C acknowledge feature.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C Acknowledgement.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None.
+  */
+void I2C_AcknowledgeConfig(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the acknowledgement */
+    I2Cx->CR1 |= I2C_CR1_ACK;
+  }
+  else
+  {
+    /* Disable the acknowledgement */
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ACK);
+  }
+}
+
+/**
+  * @brief  Configures the specified I2C own address2.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  Address: specifies the 7bit I2C own address2.
+  * @retval None.
+  */
+void I2C_OwnAddress2Config(I2C_TypeDef* I2Cx, uint8_t Address)
+{
+  uint16_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Get the old register value */
+  tmpreg = I2Cx->OAR2;
+
+  /* Reset I2Cx Own address2 bit [7:1] */
+  tmpreg &= (uint16_t)~((uint16_t)I2C_OAR2_ADD2);
+
+  /* Set I2Cx Own address2 */
+  tmpreg |= (uint16_t)((uint16_t)Address & (uint16_t)0x00FE);
+
+  /* Store the new register value */
+  I2Cx->OAR2 = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the specified I2C dual addressing mode.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C dual addressing mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DualAddressCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable dual addressing mode */
+    I2Cx->OAR2 |= I2C_OAR2_ENDUAL;
+  }
+  else
+  {
+    /* Disable dual addressing mode */
+    I2Cx->OAR2 &= (uint16_t)~((uint16_t)I2C_OAR2_ENDUAL);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C general call feature.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C General call.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_GeneralCallCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable generall call */
+    I2Cx->CR1 |= I2C_CR1_ENGC;
+  }
+  else
+  {
+    /* Disable generall call */
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENGC);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C software reset.
+  * @note   When software reset is enabled, the I2C IOs are released (this can
+  *         be useful to recover from bus errors).  
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C software reset.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_SoftwareResetCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Peripheral under reset */
+    I2Cx->CR1 |= I2C_CR1_SWRST;
+  }
+  else
+  {
+    /* Peripheral not under reset */
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_SWRST);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C Clock stretching.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx Clock stretching.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_StretchClockCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState == DISABLE)
+  {
+    /* Enable the selected I2C Clock stretching */
+    I2Cx->CR1 |= I2C_CR1_NOSTRETCH;
+  }
+  else
+  {
+    /* Disable the selected I2C Clock stretching */
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_NOSTRETCH);
+  }
+}
+
+/**
+  * @brief  Selects the specified I2C fast mode duty cycle.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_DutyCycle: specifies the fast mode duty cycle.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_DutyCycle_2: I2C fast mode Tlow/Thigh = 2
+  *            @arg I2C_DutyCycle_16_9: I2C fast mode Tlow/Thigh = 16/9
+  * @retval None
+  */
+void I2C_FastModeDutyCycleConfig(I2C_TypeDef* I2Cx, uint16_t I2C_DutyCycle)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_DUTY_CYCLE(I2C_DutyCycle));
+  if (I2C_DutyCycle != I2C_DutyCycle_16_9)
+  {
+    /* I2C fast mode Tlow/Thigh=2 */
+    I2Cx->CCR &= I2C_DutyCycle_2;
+  }
+  else
+  {
+    /* I2C fast mode Tlow/Thigh=16/9 */
+    I2Cx->CCR |= I2C_DutyCycle_16_9;
+  }
+}
+
+/**
+  * @brief  Selects the specified I2C NACK position in master receiver mode.
+  * @note   This function is useful in I2C Master Receiver mode when the number
+  *         of data to be received is equal to 2. In this case, this function 
+  *         should be called (with parameter I2C_NACKPosition_Next) before data 
+  *         reception starts,as described in the 2-byte reception procedure 
+  *         recommended in Reference Manual in Section: Master receiver.                
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_NACKPosition: specifies the NACK position. 
+  *          This parameter can be one of the following values:
+  *            @arg I2C_NACKPosition_Next: indicates that the next byte will be the last
+  *                                        received byte.  
+  *            @arg I2C_NACKPosition_Current: indicates that current byte is the last 
+  *                                           received byte.
+  *            
+  * @note    This function configures the same bit (POS) as I2C_PECPositionConfig() 
+  *          but is intended to be used in I2C mode while I2C_PECPositionConfig() 
+  *          is intended to used in SMBUS mode. 
+  *            
+  * @retval None
+  */
+void I2C_NACKPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_NACKPosition)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_NACK_POSITION(I2C_NACKPosition));
+  
+  /* Check the input parameter */
+  if (I2C_NACKPosition == I2C_NACKPosition_Next)
+  {
+    /* Next byte in shift register is the last received byte */
+    I2Cx->CR1 |= I2C_NACKPosition_Next;
+  }
+  else
+  {
+    /* Current byte in shift register is the last received byte */
+    I2Cx->CR1 &= I2C_NACKPosition_Current;
+  }
+}
+
+/**
+  * @brief  Drives the SMBusAlert pin high or low for the specified I2C.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_SMBusAlert: specifies SMBAlert pin level. 
+  *          This parameter can be one of the following values:
+  *            @arg I2C_SMBusAlert_Low: SMBAlert pin driven low
+  *            @arg I2C_SMBusAlert_High: SMBAlert pin driven high
+  * @retval None
+  */
+void I2C_SMBusAlertConfig(I2C_TypeDef* I2Cx, uint16_t I2C_SMBusAlert)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_SMBUS_ALERT(I2C_SMBusAlert));
+  if (I2C_SMBusAlert == I2C_SMBusAlert_Low)
+  {
+    /* Drive the SMBusAlert pin Low */
+    I2Cx->CR1 |= I2C_SMBusAlert_Low;
+  }
+  else
+  {
+    /* Drive the SMBusAlert pin High  */
+    I2Cx->CR1 &= I2C_SMBusAlert_High;
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified I2C ARP.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx ARP. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ARPCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C ARP */
+    I2Cx->CR1 |= I2C_CR1_ENARP;
+  }
+  else
+  {
+    /* Disable the selected I2C ARP */
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENARP);
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Group2 Data transfers functions
+ *  @brief   Data transfers functions 
+ *
+@verbatim   
+ ===============================================================================
+                        Data transfers functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sends a data byte through the I2Cx peripheral.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  Data: Byte to be transmitted..
+  * @retval None
+  */
+void I2C_SendData(I2C_TypeDef* I2Cx, uint8_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  /* Write in the DR register the data to be sent */
+  I2Cx->DR = Data;
+}
+
+/**
+  * @brief  Returns the most recent received data by the I2Cx peripheral.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @retval The value of the received data.
+  */
+uint8_t I2C_ReceiveData(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  /* Return the data in the DR register */
+  return (uint8_t)I2Cx->DR;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Group3 PEC management functions
+ *  @brief   PEC management functions 
+ *
+@verbatim   
+ ===============================================================================
+                         PEC management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified I2C PEC transfer.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C PEC transmission.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_TransmitPEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C PEC transmission */
+    I2Cx->CR1 |= I2C_CR1_PEC;
+  }
+  else
+  {
+    /* Disable the selected I2C PEC transmission */
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_PEC);
+  }
+}
+
+/**
+  * @brief  Selects the specified I2C PEC position.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_PECPosition: specifies the PEC position. 
+  *          This parameter can be one of the following values:
+  *            @arg I2C_PECPosition_Next: indicates that the next byte is PEC
+  *            @arg I2C_PECPosition_Current: indicates that current byte is PEC
+  *       
+  * @note    This function configures the same bit (POS) as I2C_NACKPositionConfig()
+  *          but is intended to be used in SMBUS mode while I2C_NACKPositionConfig() 
+  *          is intended to used in I2C mode.
+  *                
+  * @retval None
+  */
+void I2C_PECPositionConfig(I2C_TypeDef* I2Cx, uint16_t I2C_PECPosition)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_PEC_POSITION(I2C_PECPosition));
+  if (I2C_PECPosition == I2C_PECPosition_Next)
+  {
+    /* Next byte in shift register is PEC */
+    I2Cx->CR1 |= I2C_PECPosition_Next;
+  }
+  else
+  {
+    /* Current byte in shift register is PEC */
+    I2Cx->CR1 &= I2C_PECPosition_Current;
+  }
+}
+
+/**
+  * @brief  Enables or disables the PEC value calculation of the transferred bytes.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2Cx PEC value calculation.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_CalculatePEC(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C PEC calculation */
+    I2Cx->CR1 |= I2C_CR1_ENPEC;
+  }
+  else
+  {
+    /* Disable the selected I2C PEC calculation */
+    I2Cx->CR1 &= (uint16_t)~((uint16_t)I2C_CR1_ENPEC);
+  }
+}
+
+/**
+  * @brief  Returns the PEC value for the specified I2C.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @retval The PEC value.
+  */
+uint8_t I2C_GetPEC(I2C_TypeDef* I2Cx)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  /* Return the selected I2C PEC value */
+  return ((I2Cx->SR2) >> 8);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Group4 DMA transfers management functions
+ *  @brief   DMA transfers management functions 
+ *
+@verbatim   
+ ===============================================================================
+                         DMA transfers management functions
+ ===============================================================================  
+  This section provides functions allowing to configure the I2C DMA channels 
+  requests.
+  
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified I2C DMA requests.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C DMA transfer.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DMACmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C DMA requests */
+    I2Cx->CR2 |= I2C_CR2_DMAEN;
+  }
+  else
+  {
+    /* Disable the selected I2C DMA requests */
+    I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_DMAEN);
+  }
+}
+
+/**
+  * @brief  Specifies that the next DMA transfer is the last one.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  NewState: new state of the I2C DMA last transfer.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_DMALastTransferCmd(I2C_TypeDef* I2Cx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Next DMA transfer is the last transfer */
+    I2Cx->CR2 |= I2C_CR2_LAST;
+  }
+  else
+  {
+    /* Next DMA transfer is not the last transfer */
+    I2Cx->CR2 &= (uint16_t)~((uint16_t)I2C_CR2_LAST);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup I2C_Group5 Interrupts events and flags management functions
+ *  @brief   Interrupts, events and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+                Interrupts, events and flags management functions
+ ===============================================================================  
+  This section provides functions allowing to configure the I2C Interrupts 
+  sources and check or clear the flags or pending bits status.
+  The user should identify which mode will be used in his application to manage 
+  the communication: Polling mode, Interrupt mode or DMA mode. 
+
+ ===============================================================================
+                          I2C State Monitoring Functions                    
+ ===============================================================================   
+  This I2C driver provides three different ways for I2C state monitoring
+  depending on the application requirements and constraints:
+         
+   
+     1. Basic state monitoring (Using I2C_CheckEvent() function)
+     -----------------------------------------------------------
+        It compares the status registers (SR1 and SR2) content to a given event
+        (can be the combination of one or more flags).
+        It returns SUCCESS if the current status includes the given flags 
+        and returns ERROR if one or more flags are missing in the current status.
+
+          - When to use
+             - This function is suitable for most applications as well as for startup 
+               activity since the events are fully described in the product reference 
+               manual (RM0090).
+             - It is also suitable for users who need to define their own events.
+
+          - Limitations
+             - If an error occurs (ie. error flags are set besides to the monitored 
+               flags), the I2C_CheckEvent() function may return SUCCESS despite 
+               the communication hold or corrupted real state. 
+               In this case, it is advised to use error interrupts to monitor 
+               the error events and handle them in the interrupt IRQ handler.
+         
+     @note 
+         For error management, it is advised to use the following functions:
+           - I2C_ITConfig() to configure and enable the error interrupts (I2C_IT_ERR).
+           - I2Cx_ER_IRQHandler() which is called when the error interrupt occurs.
+             Where x is the peripheral instance (I2C1, I2C2 ...)
+           - I2C_GetFlagStatus() or I2C_GetITStatus()  to be called into the 
+             I2Cx_ER_IRQHandler() function in order to determine which error occurred.
+           - I2C_ClearFlag() or I2C_ClearITPendingBit() and/or I2C_SoftwareResetCmd() 
+             and/or I2C_GenerateStop() in order to clear the error flag and source 
+             and return to correct  communication status.
+             
+ 
+     2. Advanced state monitoring (Using the function I2C_GetLastEvent())
+     -------------------------------------------------------------------- 
+        Using the function I2C_GetLastEvent() which returns the image of both status 
+        registers in a single word (uint32_t) (Status Register 2 value is shifted left 
+        by 16 bits and concatenated to Status Register 1).
+
+          - When to use
+             - This function is suitable for the same applications above but it 
+               allows to overcome the mentioned limitation of I2C_GetFlagStatus() 
+               function.
+             - The returned value could be compared to events already defined in 
+               the library (stm32f4xx_i2c.h) or to custom values defined by user.
+               This function is suitable when multiple flags are monitored at the 
+               same time.
+             - At the opposite of I2C_CheckEvent() function, this function allows 
+               user to choose when an event is accepted (when all events flags are 
+               set and no other flags are set or just when the needed flags are set 
+               like I2C_CheckEvent() function.
+
+          - Limitations
+             - User may need to define his own events.
+             - Same remark concerning the error management is applicable for this 
+               function if user decides to check only regular communication flags 
+               (and ignores error flags).
+      
+ 
+     3. Flag-based state monitoring (Using the function I2C_GetFlagStatus())
+     -----------------------------------------------------------------------
+     
+      Using the function I2C_GetFlagStatus() which simply returns the status of 
+      one single flag (ie. I2C_FLAG_RXNE ...). 
+
+          - When to use
+             - This function could be used for specific applications or in debug 
+               phase.
+             - It is suitable when only one flag checking is needed (most I2C 
+               events are monitored through multiple flags).
+          - Limitations: 
+             - When calling this function, the Status register is accessed. 
+               Some flags are cleared when the status register is accessed. 
+               So checking the status of one Flag, may clear other ones.
+             - Function may need to be called twice or more in order to monitor 
+               one single event.
+ 
+   For detailed description of Events, please refer to section I2C_Events in 
+   stm32f4xx_i2c.h file.
+       
+@endverbatim
+  * @{
+  */
+   
+/**
+  * @brief  Reads the specified I2C register and returns its value.
+  * @param  I2C_Register: specifies the register to read.
+  *          This parameter can be one of the following values:
+  *            @arg I2C_Register_CR1:  CR1 register.
+  *            @arg I2C_Register_CR2:   CR2 register.
+  *            @arg I2C_Register_OAR1:  OAR1 register.
+  *            @arg I2C_Register_OAR2:  OAR2 register.
+  *            @arg I2C_Register_DR:    DR register.
+  *            @arg I2C_Register_SR1:   SR1 register.
+  *            @arg I2C_Register_SR2:   SR2 register.
+  *            @arg I2C_Register_CCR:   CCR register.
+  *            @arg I2C_Register_TRISE: TRISE register.
+  * @retval The value of the read register.
+  */
+uint16_t I2C_ReadRegister(I2C_TypeDef* I2Cx, uint8_t I2C_Register)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_REGISTER(I2C_Register));
+
+  tmp = (uint32_t) I2Cx;
+  tmp += I2C_Register;
+
+  /* Return the selected register value */
+  return (*(__IO uint16_t *) tmp);
+}
+
+/**
+  * @brief  Enables or disables the specified I2C interrupts.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the I2C interrupts sources to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg I2C_IT_BUF: Buffer interrupt mask
+  *            @arg I2C_IT_EVT: Event interrupt mask
+  *            @arg I2C_IT_ERR: Error interrupt mask
+  * @param  NewState: new state of the specified I2C interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2C_ITConfig(I2C_TypeDef* I2Cx, uint16_t I2C_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_I2C_CONFIG_IT(I2C_IT));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected I2C interrupts */
+    I2Cx->CR2 |= I2C_IT;
+  }
+  else
+  {
+    /* Disable the selected I2C interrupts */
+    I2Cx->CR2 &= (uint16_t)~I2C_IT;
+  }
+}
+
+/*
+ ===============================================================================
+                          1. Basic state monitoring                    
+ ===============================================================================  
+ */
+
+/**
+  * @brief  Checks whether the last I2Cx Event is equal to the one passed
+  *         as parameter.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_EVENT: specifies the event to be checked. 
+  *          This parameter can be one of the following values:
+  *            @arg I2C_EVENT_SLAVE_TRANSMITTER_ADDRESS_MATCHED: EV1
+  *            @arg I2C_EVENT_SLAVE_RECEIVER_ADDRESS_MATCHED: EV1
+  *            @arg I2C_EVENT_SLAVE_TRANSMITTER_SECONDADDRESS_MATCHED: EV1
+  *            @arg I2C_EVENT_SLAVE_RECEIVER_SECONDADDRESS_MATCHED: EV1
+  *            @arg I2C_EVENT_SLAVE_GENERALCALLADDRESS_MATCHED: EV1
+  *            @arg I2C_EVENT_SLAVE_BYTE_RECEIVED: EV2
+  *            @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_DUALF): EV2
+  *            @arg (I2C_EVENT_SLAVE_BYTE_RECEIVED | I2C_FLAG_GENCALL): EV2
+  *            @arg I2C_EVENT_SLAVE_BYTE_TRANSMITTED: EV3
+  *            @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_DUALF): EV3
+  *            @arg (I2C_EVENT_SLAVE_BYTE_TRANSMITTED | I2C_FLAG_GENCALL): EV3
+  *            @arg I2C_EVENT_SLAVE_ACK_FAILURE: EV3_2
+  *            @arg I2C_EVENT_SLAVE_STOP_DETECTED: EV4
+  *            @arg I2C_EVENT_MASTER_MODE_SELECT: EV5
+  *            @arg I2C_EVENT_MASTER_TRANSMITTER_MODE_SELECTED: EV6     
+  *            @arg I2C_EVENT_MASTER_RECEIVER_MODE_SELECTED: EV6
+  *            @arg I2C_EVENT_MASTER_BYTE_RECEIVED: EV7
+  *            @arg I2C_EVENT_MASTER_BYTE_TRANSMITTING: EV8
+  *            @arg I2C_EVENT_MASTER_BYTE_TRANSMITTED: EV8_2
+  *            @arg I2C_EVENT_MASTER_MODE_ADDRESS10: EV9
+  *     
+  * @note   For detailed description of Events, please refer to section I2C_Events
+  *         in stm32f4xx_i2c.h file.
+  *    
+  * @retval An ErrorStatus enumeration value:
+  *           - SUCCESS: Last event is equal to the I2C_EVENT
+  *           - ERROR: Last event is different from the I2C_EVENT
+  */
+ErrorStatus I2C_CheckEvent(I2C_TypeDef* I2Cx, uint32_t I2C_EVENT)
+{
+  uint32_t lastevent = 0;
+  uint32_t flag1 = 0, flag2 = 0;
+  ErrorStatus status = ERROR;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_EVENT(I2C_EVENT));
+
+  /* Read the I2Cx status register */
+  flag1 = I2Cx->SR1;
+  flag2 = I2Cx->SR2;
+  flag2 = flag2 << 16;
+
+  /* Get the last event value from I2C status register */
+  lastevent = (flag1 | flag2) & FLAG_MASK;
+
+  /* Check whether the last event contains the I2C_EVENT */
+  if ((lastevent & I2C_EVENT) == I2C_EVENT)
+  {
+    /* SUCCESS: last event is equal to I2C_EVENT */
+    status = SUCCESS;
+  }
+  else
+  {
+    /* ERROR: last event is different from I2C_EVENT */
+    status = ERROR;
+  }
+  /* Return status */
+  return status;
+}
+
+/*
+ ===============================================================================
+                          2. Advanced state monitoring                   
+ ===============================================================================  
+ */
+
+/**
+  * @brief  Returns the last I2Cx Event.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  *     
+  * @note   For detailed description of Events, please refer to section I2C_Events
+  *         in stm32f4xx_i2c.h file.
+  *    
+  * @retval The last event
+  */
+uint32_t I2C_GetLastEvent(I2C_TypeDef* I2Cx)
+{
+  uint32_t lastevent = 0;
+  uint32_t flag1 = 0, flag2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+
+  /* Read the I2Cx status register */
+  flag1 = I2Cx->SR1;
+  flag2 = I2Cx->SR2;
+  flag2 = flag2 << 16;
+
+  /* Get the last event value from I2C status register */
+  lastevent = (flag1 | flag2) & FLAG_MASK;
+
+  /* Return status */
+  return lastevent;
+}
+
+/*
+ ===============================================================================
+                          3. Flag-based state monitoring                   
+ ===============================================================================  
+ */
+
+/**
+  * @brief  Checks whether the specified I2C flag is set or not.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_FLAG: specifies the flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg I2C_FLAG_DUALF: Dual flag (Slave mode)
+  *            @arg I2C_FLAG_SMBHOST: SMBus host header (Slave mode)
+  *            @arg I2C_FLAG_SMBDEFAULT: SMBus default header (Slave mode)
+  *            @arg I2C_FLAG_GENCALL: General call header flag (Slave mode)
+  *            @arg I2C_FLAG_TRA: Transmitter/Receiver flag
+  *            @arg I2C_FLAG_BUSY: Bus busy flag
+  *            @arg I2C_FLAG_MSL: Master/Slave flag
+  *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+  *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+  *            @arg I2C_FLAG_PECERR: PEC error in reception flag
+  *            @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+  *            @arg I2C_FLAG_AF: Acknowledge failure flag
+  *            @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+  *            @arg I2C_FLAG_BERR: Bus error flag
+  *            @arg I2C_FLAG_TXE: Data register empty flag (Transmitter)
+  *            @arg I2C_FLAG_RXNE: Data register not empty (Receiver) flag
+  *            @arg I2C_FLAG_STOPF: Stop detection flag (Slave mode)
+  *            @arg I2C_FLAG_ADD10: 10-bit header sent flag (Master mode)
+  *            @arg I2C_FLAG_BTF: Byte transfer finished flag
+  *            @arg I2C_FLAG_ADDR: Address sent flag (Master mode) "ADSL"
+  *                                Address matched flag (Slave mode)"ENDAD"
+  *            @arg I2C_FLAG_SB: Start bit flag (Master mode)
+  * @retval The new state of I2C_FLAG (SET or RESET).
+  */
+FlagStatus I2C_GetFlagStatus(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  __IO uint32_t i2creg = 0, i2cxbase = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_GET_FLAG(I2C_FLAG));
+
+  /* Get the I2Cx peripheral base address */
+  i2cxbase = (uint32_t)I2Cx;
+  
+  /* Read flag register index */
+  i2creg = I2C_FLAG >> 28;
+  
+  /* Get bit[23:0] of the flag */
+  I2C_FLAG &= FLAG_MASK;
+  
+  if(i2creg != 0)
+  {
+    /* Get the I2Cx SR1 register address */
+    i2cxbase += 0x14;
+  }
+  else
+  {
+    /* Flag in I2Cx SR2 Register */
+    I2C_FLAG = (uint32_t)(I2C_FLAG >> 16);
+    /* Get the I2Cx SR2 register address */
+    i2cxbase += 0x18;
+  }
+  
+  if(((*(__IO uint32_t *)i2cxbase) & I2C_FLAG) != (uint32_t)RESET)
+  {
+    /* I2C_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* I2C_FLAG is reset */
+    bitstatus = RESET;
+  }
+  
+  /* Return the I2C_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the I2Cx's pending flags.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_FLAG: specifies the flag to clear. 
+  *          This parameter can be any combination of the following values:
+  *            @arg I2C_FLAG_SMBALERT: SMBus Alert flag
+  *            @arg I2C_FLAG_TIMEOUT: Timeout or Tlow error flag
+  *            @arg I2C_FLAG_PECERR: PEC error in reception flag
+  *            @arg I2C_FLAG_OVR: Overrun/Underrun flag (Slave mode)
+  *            @arg I2C_FLAG_AF: Acknowledge failure flag
+  *            @arg I2C_FLAG_ARLO: Arbitration lost flag (Master mode)
+  *            @arg I2C_FLAG_BERR: Bus error flag
+  *   
+  * @note   STOPF (STOP detection) is cleared by software sequence: a read operation 
+  *          to I2C_SR1 register (I2C_GetFlagStatus()) followed by a write operation 
+  *          to I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
+  * @note   ADD10 (10-bit header sent) is cleared by software sequence: a read 
+  *          operation to I2C_SR1 (I2C_GetFlagStatus()) followed by writing the 
+  *          second byte of the address in DR register.
+  * @note   BTF (Byte Transfer Finished) is cleared by software sequence: a read 
+  *          operation to I2C_SR1 register (I2C_GetFlagStatus()) followed by a 
+  *          read/write to I2C_DR register (I2C_SendData()).
+  * @note   ADDR (Address sent) is cleared by software sequence: a read operation to 
+  *          I2C_SR1 register (I2C_GetFlagStatus()) followed by a read operation to 
+  *          I2C_SR2 register ((void)(I2Cx->SR2)).
+  * @note   SB (Start Bit) is cleared software sequence: a read operation to I2C_SR1
+  *          register (I2C_GetFlagStatus()) followed by a write operation to I2C_DR
+  *          register (I2C_SendData()).
+  *  
+  * @retval None
+  */
+void I2C_ClearFlag(I2C_TypeDef* I2Cx, uint32_t I2C_FLAG)
+{
+  uint32_t flagpos = 0;
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLEAR_FLAG(I2C_FLAG));
+  /* Get the I2C flag position */
+  flagpos = I2C_FLAG & FLAG_MASK;
+  /* Clear the selected I2C flag */
+  I2Cx->SR1 = (uint16_t)~flagpos;
+}
+
+/**
+  * @brief  Checks whether the specified I2C interrupt has occurred or not.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg I2C_IT_SMBALERT: SMBus Alert flag
+  *            @arg I2C_IT_TIMEOUT: Timeout or Tlow error flag
+  *            @arg I2C_IT_PECERR: PEC error in reception flag
+  *            @arg I2C_IT_OVR: Overrun/Underrun flag (Slave mode)
+  *            @arg I2C_IT_AF: Acknowledge failure flag
+  *            @arg I2C_IT_ARLO: Arbitration lost flag (Master mode)
+  *            @arg I2C_IT_BERR: Bus error flag
+  *            @arg I2C_IT_TXE: Data register empty flag (Transmitter)
+  *            @arg I2C_IT_RXNE: Data register not empty (Receiver) flag
+  *            @arg I2C_IT_STOPF: Stop detection flag (Slave mode)
+  *            @arg I2C_IT_ADD10: 10-bit header sent flag (Master mode)
+  *            @arg I2C_IT_BTF: Byte transfer finished flag
+  *            @arg I2C_IT_ADDR: Address sent flag (Master mode) "ADSL"
+  *                              Address matched flag (Slave mode)"ENDAD"
+  *            @arg I2C_IT_SB: Start bit flag (Master mode)
+  * @retval The new state of I2C_IT (SET or RESET).
+  */
+ITStatus I2C_GetITStatus(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_GET_IT(I2C_IT));
+
+  /* Check if the interrupt source is enabled or not */
+  enablestatus = (uint32_t)(((I2C_IT & ITEN_MASK) >> 16) & (I2Cx->CR2)) ;
+  
+  /* Get bit[23:0] of the flag */
+  I2C_IT &= FLAG_MASK;
+
+  /* Check the status of the specified I2C flag */
+  if (((I2Cx->SR1 & I2C_IT) != (uint32_t)RESET) && enablestatus)
+  {
+    /* I2C_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* I2C_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the I2C_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the I2Cx's interrupt pending bits.
+  * @param  I2Cx: where x can be 1, 2 or 3 to select the I2C peripheral.
+  * @param  I2C_IT: specifies the interrupt pending bit to clear. 
+  *          This parameter can be any combination of the following values:
+  *            @arg I2C_IT_SMBALERT: SMBus Alert interrupt
+  *            @arg I2C_IT_TIMEOUT: Timeout or Tlow error interrupt
+  *            @arg I2C_IT_PECERR: PEC error in reception  interrupt
+  *            @arg I2C_IT_OVR: Overrun/Underrun interrupt (Slave mode)
+  *            @arg I2C_IT_AF: Acknowledge failure interrupt
+  *            @arg I2C_IT_ARLO: Arbitration lost interrupt (Master mode)
+  *            @arg I2C_IT_BERR: Bus error interrupt
+  * 
+  * @note   STOPF (STOP detection) is cleared by software sequence: a read operation 
+  *          to I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to 
+  *          I2C_CR1 register (I2C_Cmd() to re-enable the I2C peripheral).
+  * @note   ADD10 (10-bit header sent) is cleared by software sequence: a read 
+  *          operation to I2C_SR1 (I2C_GetITStatus()) followed by writing the second 
+  *          byte of the address in I2C_DR register.
+  * @note   BTF (Byte Transfer Finished) is cleared by software sequence: a read 
+  *          operation to I2C_SR1 register (I2C_GetITStatus()) followed by a 
+  *          read/write to I2C_DR register (I2C_SendData()).
+  * @note   ADDR (Address sent) is cleared by software sequence: a read operation to 
+  *          I2C_SR1 register (I2C_GetITStatus()) followed by a read operation to 
+  *          I2C_SR2 register ((void)(I2Cx->SR2)).
+  * @note   SB (Start Bit) is cleared by software sequence: a read operation to 
+  *          I2C_SR1 register (I2C_GetITStatus()) followed by a write operation to 
+  *          I2C_DR register (I2C_SendData()).
+  * @retval None
+  */
+void I2C_ClearITPendingBit(I2C_TypeDef* I2Cx, uint32_t I2C_IT)
+{
+  uint32_t flagpos = 0;
+  /* Check the parameters */
+  assert_param(IS_I2C_ALL_PERIPH(I2Cx));
+  assert_param(IS_I2C_CLEAR_IT(I2C_IT));
+
+  /* Get the I2C flag position */
+  flagpos = I2C_IT & FLAG_MASK;
+
+  /* Clear the selected I2C flag */
+  I2Cx->SR1 = (uint16_t)~flagpos;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c
new file mode 100644
index 0000000000..c28d32d963
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_iwdg.c
@@ -0,0 +1,263 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_iwdg.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Independent watchdog (IWDG) peripheral:           
+  *           - Prescaler and Counter configuration
+  *           - IWDG activation
+  *           - Flag management
+  *
+  *  @verbatim  
+  *  
+  *          ===================================================================
+  *                                     IWDG features
+  *          ===================================================================
+  *    
+  *          The IWDG can be started by either software or hardware (configurable
+  *          through option byte).
+  *            
+  *          The IWDG is clocked by its own dedicated low-speed clock (LSI) and
+  *          thus stays active even if the main clock fails.
+  *          Once the IWDG is started, the LSI is forced ON and cannot be disabled
+  *          (LSI cannot be disabled too), and the counter starts counting down from 
+  *          the reset value of 0xFFF. When it reaches the end of count value (0x000)
+  *          a system reset is generated.
+  *          The IWDG counter should be reloaded at regular intervals to prevent
+  *          an MCU reset.
+  *                           
+  *          The IWDG is implemented in the VDD voltage domain that is still functional
+  *          in STOP and STANDBY mode (IWDG reset can wake-up from STANDBY).          
+  *            
+  *          IWDGRST flag in RCC_CSR register can be used to inform when a IWDG
+  *          reset occurs.
+  *            
+  *          Min-max timeout value @32KHz (LSI): ~125us / ~32.7s
+  *          The IWDG timeout may vary due to LSI frequency dispersion. STM32F4xx
+  *          devices provide the capability to measure the LSI frequency (LSI clock
+  *          connected internally to TIM5 CH4 input capture). The measured value
+  *          can be used to have an IWDG timeout with an acceptable accuracy. 
+  *          For more information, please refer to the STM32F4xx Reference manual
+  *          
+  *                            
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *          1. Enable write access to IWDG_PR and IWDG_RLR registers using
+  *             IWDG_WriteAccessCmd(IWDG_WriteAccess_Enable) function
+  *               
+  *          2. Configure the IWDG prescaler using IWDG_SetPrescaler() function
+  *            
+  *          3. Configure the IWDG counter value using IWDG_SetReload() function.
+  *             This value will be loaded in the IWDG counter each time the counter
+  *             is reloaded, then the IWDG will start counting down from this value.
+  *            
+  *          4. Start the IWDG using IWDG_Enable() function, when the IWDG is used
+  *             in software mode (no need to enable the LSI, it will be enabled
+  *             by hardware)
+  *             
+  *          5. Then the application program must reload the IWDG counter at regular
+  *             intervals during normal operation to prevent an MCU reset, using
+  *             IWDG_ReloadCounter() function.      
+  *          
+  *  @endverbatim
+  *    
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_iwdg.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup IWDG 
+  * @brief IWDG driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* KR register bit mask */
+#define KR_KEY_RELOAD    ((uint16_t)0xAAAA)
+#define KR_KEY_ENABLE    ((uint16_t)0xCCCC)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup IWDG_Private_Functions
+  * @{
+  */
+
+/** @defgroup IWDG_Group1 Prescaler and Counter configuration functions
+ *  @brief   Prescaler and Counter configuration functions
+ *
+@verbatim   
+ ===============================================================================
+                  Prescaler and Counter configuration functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables write access to IWDG_PR and IWDG_RLR registers.
+  * @param  IWDG_WriteAccess: new state of write access to IWDG_PR and IWDG_RLR registers.
+  *          This parameter can be one of the following values:
+  *            @arg IWDG_WriteAccess_Enable: Enable write access to IWDG_PR and IWDG_RLR registers
+  *            @arg IWDG_WriteAccess_Disable: Disable write access to IWDG_PR and IWDG_RLR registers
+  * @retval None
+  */
+void IWDG_WriteAccessCmd(uint16_t IWDG_WriteAccess)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_WRITE_ACCESS(IWDG_WriteAccess));
+  IWDG->KR = IWDG_WriteAccess;
+}
+
+/**
+  * @brief  Sets IWDG Prescaler value.
+  * @param  IWDG_Prescaler: specifies the IWDG Prescaler value.
+  *          This parameter can be one of the following values:
+  *            @arg IWDG_Prescaler_4: IWDG prescaler set to 4
+  *            @arg IWDG_Prescaler_8: IWDG prescaler set to 8
+  *            @arg IWDG_Prescaler_16: IWDG prescaler set to 16
+  *            @arg IWDG_Prescaler_32: IWDG prescaler set to 32
+  *            @arg IWDG_Prescaler_64: IWDG prescaler set to 64
+  *            @arg IWDG_Prescaler_128: IWDG prescaler set to 128
+  *            @arg IWDG_Prescaler_256: IWDG prescaler set to 256
+  * @retval None
+  */
+void IWDG_SetPrescaler(uint8_t IWDG_Prescaler)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_PRESCALER(IWDG_Prescaler));
+  IWDG->PR = IWDG_Prescaler;
+}
+
+/**
+  * @brief  Sets IWDG Reload value.
+  * @param  Reload: specifies the IWDG Reload value.
+  *          This parameter must be a number between 0 and 0x0FFF.
+  * @retval None
+  */
+void IWDG_SetReload(uint16_t Reload)
+{
+  /* Check the parameters */
+  assert_param(IS_IWDG_RELOAD(Reload));
+  IWDG->RLR = Reload;
+}
+
+/**
+  * @brief  Reloads IWDG counter with value defined in the reload register
+  *         (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_ReloadCounter(void)
+{
+  IWDG->KR = KR_KEY_RELOAD;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Group2 IWDG activation function
+ *  @brief   IWDG activation function 
+ *
+@verbatim   
+ ===============================================================================
+                          IWDG activation function
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables IWDG (write access to IWDG_PR and IWDG_RLR registers disabled).
+  * @param  None
+  * @retval None
+  */
+void IWDG_Enable(void)
+{
+  IWDG->KR = KR_KEY_ENABLE;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup IWDG_Group3 Flag management function 
+ *  @brief  Flag management function  
+ *
+@verbatim   
+ ===============================================================================
+                            Flag management function 
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified IWDG flag is set or not.
+  * @param  IWDG_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg IWDG_FLAG_PVU: Prescaler Value Update on going
+  *            @arg IWDG_FLAG_RVU: Reload Value Update on going
+  * @retval The new state of IWDG_FLAG (SET or RESET).
+  */
+FlagStatus IWDG_GetFlagStatus(uint16_t IWDG_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_IWDG_FLAG(IWDG_FLAG));
+  if ((IWDG->SR & IWDG_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c
new file mode 100644
index 0000000000..c81ad8f716
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_pwr.c
@@ -0,0 +1,638 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_pwr.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Power Controller (PWR) peripheral:           
+  *           - Backup Domain Access
+  *           - PVD configuration
+  *           - WakeUp pin configuration
+  *           - Backup Regulator configuration
+  *           - Performance Mode and FLASH Power Down configuration functions
+  *           - Low Power modes configuration
+  *           - Flags management
+  *               
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_pwr.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup PWR 
+  * @brief PWR driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* --------- PWR registers bit address in the alias region ---------- */
+#define PWR_OFFSET               (PWR_BASE - PERIPH_BASE)
+
+/* --- CR Register ---*/
+
+/* Alias word address of DBP bit */
+#define CR_OFFSET                (PWR_OFFSET + 0x00)
+#define DBP_BitNumber            0x08
+#define CR_DBP_BB                (PERIPH_BB_BASE + (CR_OFFSET * 32) + (DBP_BitNumber * 4))
+
+/* Alias word address of PVDE bit */
+#define PVDE_BitNumber           0x04
+#define CR_PVDE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PVDE_BitNumber * 4))
+
+/* Alias word address of FPDS bit */
+#define FPDS_BitNumber           0x09
+#define CR_FPDS_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (FPDS_BitNumber * 4))
+
+/* Alias word address of PMODE bit */
+#define PMODE_BitNumber           0x0E
+#define CR_PMODE_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PMODE_BitNumber * 4))
+
+
+/* --- CSR Register ---*/
+
+/* Alias word address of EWUP bit */
+#define CSR_OFFSET               (PWR_OFFSET + 0x04)
+#define EWUP_BitNumber           0x08
+#define CSR_EWUP_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (EWUP_BitNumber * 4))
+
+/* Alias word address of BRE bit */
+#define BRE_BitNumber            0x09
+#define CSR_BRE_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (BRE_BitNumber * 4))
+
+/* ------------------ PWR registers bit mask ------------------------ */
+
+/* CR register bit mask */
+#define CR_DS_MASK               ((uint32_t)0xFFFFFFFC)
+#define CR_PLS_MASK              ((uint32_t)0xFFFFFF1F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup PWR_Private_Functions
+  * @{
+  */
+
+/** @defgroup PWR_Group1 Backup Domain Access function 
+ *  @brief   Backup Domain Access function  
+ *
+@verbatim   
+ ===============================================================================
+                            Backup Domain Access function 
+ ===============================================================================  
+
+  After reset, the backup domain (RTC registers, RTC backup data 
+  registers and backup SRAM) is protected against possible unwanted 
+  write accesses. 
+  To enable access to the RTC Domain and RTC registers, proceed as follows:
+    - Enable the Power Controller (PWR) APB1 interface clock using the
+      RCC_APB1PeriphClockCmd() function.
+    - Enable access to RTC domain using the PWR_BackupAccessCmd() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the PWR peripheral registers to their default reset values.     
+  * @param  None
+  * @retval None
+  */
+void PWR_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_PWR, DISABLE);
+}
+
+/**
+  * @brief  Enables or disables access to the backup domain (RTC registers, RTC 
+  *         backup data registers and backup SRAM).
+  * @note   If the HSE divided by 2, 3, ..31 is used as the RTC clock, the 
+  *         Backup Domain Access should be kept enabled.
+  * @param  NewState: new state of the access to the backup domain.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_BackupAccessCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CR_DBP_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group2 PVD configuration functions
+ *  @brief   PVD configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                           PVD configuration functions
+ ===============================================================================  
+
+ - The PVD is used to monitor the VDD power supply by comparing it to a threshold
+   selected by the PVD Level (PLS[2:0] bits in the PWR_CR).
+ - A PVDO flag is available to indicate if VDD/VDDA is higher or lower than the 
+   PVD threshold. This event is internally connected to the EXTI line16
+   and can generate an interrupt if enabled through the EXTI registers.
+ - The PVD is stopped in Standby mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the voltage threshold detected by the Power Voltage Detector(PVD).
+  * @param  PWR_PVDLevel: specifies the PVD detection level
+  *          This parameter can be one of the following values:
+  *            @arg PWR_PVDLevel_0: PVD detection level set to 2.0V
+  *            @arg PWR_PVDLevel_1: PVD detection level set to 2.2V
+  *            @arg PWR_PVDLevel_2: PVD detection level set to 2.3V
+  *            @arg PWR_PVDLevel_3: PVD detection level set to 2.5V
+  *            @arg PWR_PVDLevel_4: PVD detection level set to 2.7V
+  *            @arg PWR_PVDLevel_5: PVD detection level set to 2.8V
+  *            @arg PWR_PVDLevel_6: PVD detection level set to 2.9V
+  *            @arg PWR_PVDLevel_7: PVD detection level set to 3.0V
+  * @note   Refer to the electrical characteristics of you device datasheet for more details. 
+  * @retval None
+  */
+void PWR_PVDLevelConfig(uint32_t PWR_PVDLevel)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_PWR_PVD_LEVEL(PWR_PVDLevel));
+  
+  tmpreg = PWR->CR;
+  
+  /* Clear PLS[7:5] bits */
+  tmpreg &= CR_PLS_MASK;
+  
+  /* Set PLS[7:5] bits according to PWR_PVDLevel value */
+  tmpreg |= PWR_PVDLevel;
+  
+  /* Store the new value */
+  PWR->CR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Power Voltage Detector(PVD).
+  * @param  NewState: new state of the PVD.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_PVDCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CR_PVDE_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group3 WakeUp pin configuration functions
+ *  @brief   WakeUp pin configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                    WakeUp pin configuration functions
+ ===============================================================================  
+
+ - WakeUp pin is used to wakeup the system from Standby mode. This pin is 
+   forced in input pull down configuration and is active on rising edges.
+ - There is only one WakeUp pin: WakeUp Pin 1 on PA.00.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the WakeUp Pin functionality.
+  * @param  NewState: new state of the WakeUp Pin functionality.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_WakeUpPinCmd(FunctionalState NewState)
+{
+  /* Check the parameters */  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CSR_EWUP_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group4 Backup Regulator configuration functions
+ *  @brief   Backup Regulator configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                    Backup Regulator configuration functions
+ ===============================================================================  
+
+ - The backup domain includes 4 Kbytes of backup SRAM accessible only from the 
+   CPU, and address in 32-bit, 16-bit or 8-bit mode. Its content is retained 
+   even in Standby or VBAT mode when the low power backup regulator is enabled. 
+   It can be considered as an internal EEPROM when VBAT is always present.
+   You can use the PWR_BackupRegulatorCmd() function to enable the low power
+   backup regulator and use the PWR_GetFlagStatus(PWR_FLAG_BRR) to check if it is
+   ready or not. 
+
+ - When the backup domain is supplied by VDD (analog switch connected to VDD) 
+   the backup SRAM is powered from VDD which replaces the VBAT power supply to 
+   save battery life.
+
+ - The backup SRAM is not mass erased by an tamper event. It is read protected 
+   to prevent confidential data, such as cryptographic private key, from being 
+   accessed. The backup SRAM can be erased only through the Flash interface when
+   a protection level change from level 1 to level 0 is requested. 
+   Refer to the description of Read protection (RDP) in the Flash programming manual.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the Backup Regulator.
+  * @param  NewState: new state of the Backup Regulator.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_BackupRegulatorCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CSR_BRE_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group5 Performance Mode and FLASH Power Down configuration functions
+ *  @brief   Performance Mode and FLASH Power Down configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+           Performance Mode and FLASH Power Down configuration functions
+ ===============================================================================  
+
+ - By setting the PMODE bit in the PWR_CR register by using the PWR_HighPerformanceModeCmd()
+   function, the high performance mode is selected and the high voltage regulator 
+   minimum value should be around 1.2V.
+   When reset, the low performance mode is selected and the low voltage regulator 
+   minimum value should be around 1.08V.
+
+ - By setting the FPDS bit in the PWR_CR register by using the PWR_FlashPowerDownCmd()
+   function, the Flash memory also enters power down mode when the device enters 
+   Stop mode. When the Flash memory is in power down mode, an additional startup 
+   delay is incurred when waking up from Stop mode.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the high performance mode.
+  * @param  NewState: new state of the performance mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_HighPerformanceModeCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CR_PMODE_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the Flash Power Down in STOP mode.
+  * @param  NewState: new state of the Flash power mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void PWR_FlashPowerDownCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CR_FPDS_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group6 Low Power modes configuration functions
+ *  @brief   Low Power modes configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                    Low Power modes configuration functions
+ ===============================================================================  
+
+  The devices feature 3 low-power modes:
+   - Sleep mode: Cortex-M4 core stopped, peripherals kept running.
+   - Stop mode: all clocks are stopped, regulator running, regulator in low power mode
+   - Standby mode: 1.2V domain powered off.
+   
+   Sleep mode
+   ===========
+    - Entry:
+      - The Sleep mode is entered by using the __WFI() or __WFE() functions.
+    - Exit:
+      - Any peripheral interrupt acknowledged by the nested vectored interrupt 
+        controller (NVIC) can wake up the device from Sleep mode.
+
+   Stop mode
+   ==========
+   In Stop mode, all clocks in the 1.2V domain are stopped, the PLL, the HSI,
+   and the HSE RC oscillators are disabled. Internal SRAM and register contents 
+   are preserved.
+   The voltage regulator can be configured either in normal or low-power mode.
+   To minimize the consumption In Stop mode, FLASH can be powered off before 
+   entering the Stop mode. It can be switched on again by software after exiting 
+   the Stop mode using the PWR_FlashPowerDownCmd() function. 
+   
+    - Entry:
+      - The Stop mode is entered using the PWR_EnterSTOPMode(PWR_Regulator_LowPower,) 
+        function with regulator in LowPower or with Regulator ON.
+    - Exit:
+      - Any EXTI Line (Internal or External) configured in Interrupt/Event mode.
+      
+   Standby mode
+   ============
+   The Standby mode allows to achieve the lowest power consumption. It is based 
+   on the Cortex-M4 deepsleep mode, with the voltage regulator disabled. 
+   The 1.2V domain is consequently powered off. The PLL, the HSI oscillator and 
+   the HSE oscillator are also switched off. SRAM and register contents are lost 
+   except for the RTC registers, RTC backup registers, backup SRAM and Standby 
+   circuitry.
+   
+   The voltage regulator is OFF.
+      
+    - Entry:
+      - The Standby mode is entered using the PWR_EnterSTANDBYMode() function.
+    - Exit:
+      - WKUP pin rising edge, RTC alarm (Alarm A and Alarm B), RTC wakeup,
+        tamper event, time-stamp event, external reset in NRST pin, IWDG reset.              
+
+   Auto-wakeup (AWU) from low-power mode
+   =====================================
+   The MCU can be woken up from low-power mode by an RTC Alarm event, an RTC 
+   Wakeup event, a tamper event, a time-stamp event, or a comparator event, 
+   without depending on an external interrupt (Auto-wakeup mode).
+
+   - RTC auto-wakeup (AWU) from the Stop mode
+     ----------------------------------------
+     
+     - To wake up from the Stop mode with an RTC alarm event, it is necessary to:
+       - Configure the EXTI Line 17 to be sensitive to rising edges (Interrupt 
+         or Event modes) using the EXTI_Init() function.
+       - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
+       - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() 
+         and RTC_AlarmCmd() functions.
+     - To wake up from the Stop mode with an RTC Tamper or time stamp event, it 
+       is necessary to:
+       - Configure the EXTI Line 21 to be sensitive to rising edges (Interrupt 
+         or Event modes) using the EXTI_Init() function.
+       - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() 
+         function
+       - Configure the RTC to detect the tamper or time stamp event using the
+         RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
+         functions.
+     - To wake up from the Stop mode with an RTC WakeUp event, it is necessary to:
+       - Configure the EXTI Line 22 to be sensitive to rising edges (Interrupt 
+         or Event modes) using the EXTI_Init() function.
+       - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
+       - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), 
+         RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
+
+   - RTC auto-wakeup (AWU) from the Standby mode
+     -------------------------------------------
+     - To wake up from the Standby mode with an RTC alarm event, it is necessary to:
+       - Enable the RTC Alarm Interrupt using the RTC_ITConfig() function
+       - Configure the RTC to generate the RTC alarm using the RTC_SetAlarm() 
+         and RTC_AlarmCmd() functions.
+     - To wake up from the Standby mode with an RTC Tamper or time stamp event, it 
+       is necessary to:
+       - Enable the RTC Tamper or time stamp Interrupt using the RTC_ITConfig() 
+         function
+       - Configure the RTC to detect the tamper or time stamp event using the
+         RTC_TimeStampConfig(), RTC_TamperTriggerConfig() and RTC_TamperCmd()
+         functions.
+     - To wake up from the Standby mode with an RTC WakeUp event, it is necessary to:
+       - Enable the RTC WakeUp Interrupt using the RTC_ITConfig() function
+       - Configure the RTC to generate the RTC WakeUp event using the RTC_WakeUpClockConfig(), 
+         RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enters STOP mode.
+  *   
+  * @note   In Stop mode, all I/O pins keep the same state as in Run mode.
+  * @note   When exiting Stop mode by issuing an interrupt or a wakeup event, 
+  *         the HSI RC oscillator is selected as system clock.
+  * @note   When the voltage regulator operates in low power mode, an additional 
+  *         startup delay is incurred when waking up from Stop mode. 
+  *         By keeping the internal regulator ON during Stop mode, the consumption 
+  *         is higher although the startup time is reduced.           
+  *     
+  * @param  PWR_Regulator: specifies the regulator state in STOP mode.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_Regulator_ON: STOP mode with regulator ON
+  *            @arg PWR_Regulator_LowPower: STOP mode with regulator in low power mode
+  * @param  PWR_STOPEntry: specifies if STOP mode in entered with WFI or WFE instruction.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_STOPEntry_WFI: enter STOP mode with WFI instruction
+  *            @arg PWR_STOPEntry_WFE: enter STOP mode with WFE instruction
+  * @retval None
+  */
+void PWR_EnterSTOPMode(uint32_t PWR_Regulator, uint8_t PWR_STOPEntry)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_PWR_REGULATOR(PWR_Regulator));
+  assert_param(IS_PWR_STOP_ENTRY(PWR_STOPEntry));
+  
+  /* Select the regulator state in STOP mode ---------------------------------*/
+  tmpreg = PWR->CR;
+  /* Clear PDDS and LPDSR bits */
+  tmpreg &= CR_DS_MASK;
+  
+  /* Set LPDSR bit according to PWR_Regulator value */
+  tmpreg |= PWR_Regulator;
+  
+  /* Store the new value */
+  PWR->CR = tmpreg;
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+  
+  /* Select STOP mode entry --------------------------------------------------*/
+  if(PWR_STOPEntry == PWR_STOPEntry_WFI)
+  {   
+    /* Request Wait For Interrupt */
+    __WFI();
+  }
+  else
+  {
+    /* Request Wait For Event */
+    __WFE();
+  }
+  /* Reset SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR &= (uint32_t)~((uint32_t)SCB_SCR_SLEEPDEEP_Msk);  
+}
+
+/**
+  * @brief  Enters STANDBY mode.
+  * @note   In Standby mode, all I/O pins are high impedance except for:
+  *          - Reset pad (still available) 
+  *          - RTC_AF1 pin (PC13) if configured for tamper, time-stamp, RTC 
+  *            Alarm out, or RTC clock calibration out.
+  *          - RTC_AF2 pin (PI8) if configured for tamper or time-stamp.  
+  *          - WKUP pin 1 (PA0) if enabled.       
+  * @param  None
+  * @retval None
+  */
+void PWR_EnterSTANDBYMode(void)
+{
+  /* Clear Wakeup flag */
+  PWR->CR |= PWR_CR_CWUF;
+  
+  /* Select STANDBY mode */
+  PWR->CR |= PWR_CR_PDDS;
+  
+  /* Set SLEEPDEEP bit of Cortex System Control Register */
+  SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
+  
+/* This option is used to ensure that store operations are completed */
+#if defined ( __CC_ARM   )
+  __force_stores();
+#endif
+  /* Request Wait For Interrupt */
+  __WFI();
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup PWR_Group7 Flags management functions
+ *  @brief   Flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                           Flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the specified PWR flag is set or not.
+  * @param  PWR_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WU: Wake Up flag. This flag indicates that a wakeup event 
+  *                  was received from the WKUP pin or from the RTC alarm (Alarm A 
+  *                  or Alarm B), RTC Tamper event, RTC TimeStamp event or RTC Wakeup.
+  *                  An additional wakeup event is detected if the WKUP pin is enabled 
+  *                  (by setting the EWUP bit) when the WKUP pin level is already high.  
+  *            @arg PWR_FLAG_SB: StandBy flag. This flag indicates that the system was
+  *                  resumed from StandBy mode.    
+  *            @arg PWR_FLAG_PVDO: PVD Output. This flag is valid only if PVD is enabled 
+  *                  by the PWR_PVDCmd() function. The PVD is stopped by Standby mode 
+  *                  For this reason, this bit is equal to 0 after Standby or reset
+  *                  until the PVDE bit is set.
+  *            @arg PWR_FLAG_BRR: Backup regulator ready flag. This bit is not reset 
+  *                  when the device wakes up from Standby mode or by a system reset 
+  *                  or power reset.  
+  *            @arg PWR_FLAG_REGRDY: Main regulator ready flag. 
+  * @retval The new state of PWR_FLAG (SET or RESET).
+  */
+FlagStatus PWR_GetFlagStatus(uint32_t PWR_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_PWR_GET_FLAG(PWR_FLAG));
+  
+  if ((PWR->CSR & PWR_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the PWR's pending flags.
+  * @param  PWR_FLAG: specifies the flag to clear.
+  *          This parameter can be one of the following values:
+  *            @arg PWR_FLAG_WU: Wake Up flag
+  *            @arg PWR_FLAG_SB: StandBy flag
+  * @retval None
+  */
+void PWR_ClearFlag(uint32_t PWR_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_PWR_CLEAR_FLAG(PWR_FLAG));
+         
+  PWR->CR |=  PWR_FLAG << 2;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c
new file mode 100644
index 0000000000..657ffcc125
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rcc.c
@@ -0,0 +1,1811 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_rcc.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Reset and clock control (RCC) peripheral:           
+  *           - Internal/external clocks, PLL, CSS and MCO configuration
+  *           - System, AHB and APB busses clocks configuration
+  *           - Peripheral clocks configuration
+  *           - Interrupts and flags management
+  *
+  *  @verbatim
+  *               
+  *          ===================================================================
+  *                               RCC specific features
+  *          ===================================================================
+  *    
+  *          After reset the device is running from Internal High Speed oscillator 
+  *          (HSI 16MHz) with Flash 0 wait state, Flash prefetch buffer, D-Cache 
+  *          and I-Cache are disabled, and all peripherals are off except internal
+  *          SRAM, Flash and JTAG.
+  *           - There is no prescaler on High speed (AHB) and Low speed (APB) busses;
+  *             all peripherals mapped on these busses are running at HSI speed.
+  *       	  - The clock for all peripherals is switched off, except the SRAM and FLASH.
+  *           - All GPIOs are in input floating state, except the JTAG pins which
+  *             are assigned to be used for debug purpose.
+  *        
+  *          Once the device started from reset, the user application has to:        
+  *           - Configure the clock source to be used to drive the System clock
+  *             (if the application needs higher frequency/performance)
+  *           - Configure the System clock frequency and Flash settings  
+  *           - Configure the AHB and APB busses prescalers
+  *           - Enable the clock for the peripheral(s) to be used
+  *           - Configure the clock source(s) for peripherals which clocks are not
+  *             derived from the System clock (I2S, RTC, ADC, USB OTG FS/SDIO/RNG)      
+  *                        
+  *  @endverbatim
+  *    
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup RCC 
+  * @brief RCC driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define RCC_OFFSET                (RCC_BASE - PERIPH_BASE)
+/* --- CR Register ---*/
+/* Alias word address of HSION bit */
+#define CR_OFFSET                 (RCC_OFFSET + 0x00)
+#define HSION_BitNumber           0x00
+#define CR_HSION_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (HSION_BitNumber * 4))
+/* Alias word address of CSSON bit */
+#define CSSON_BitNumber           0x13
+#define CR_CSSON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (CSSON_BitNumber * 4))
+/* Alias word address of PLLON bit */
+#define PLLON_BitNumber           0x18
+#define CR_PLLON_BB               (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLON_BitNumber * 4))
+/* Alias word address of PLLI2SON bit */
+#define PLLI2SON_BitNumber        0x1A
+#define CR_PLLI2SON_BB            (PERIPH_BB_BASE + (CR_OFFSET * 32) + (PLLI2SON_BitNumber * 4))
+
+/* --- CFGR Register ---*/
+/* Alias word address of I2SSRC bit */
+#define CFGR_OFFSET               (RCC_OFFSET + 0x08)
+#define I2SSRC_BitNumber          0x17
+#define CFGR_I2SSRC_BB            (PERIPH_BB_BASE + (CFGR_OFFSET * 32) + (I2SSRC_BitNumber * 4))
+
+/* --- BDCR Register ---*/
+/* Alias word address of RTCEN bit */
+#define BDCR_OFFSET               (RCC_OFFSET + 0x70)
+#define RTCEN_BitNumber           0x0F
+#define BDCR_RTCEN_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (RTCEN_BitNumber * 4))
+/* Alias word address of BDRST bit */
+#define BDRST_BitNumber           0x10
+#define BDCR_BDRST_BB             (PERIPH_BB_BASE + (BDCR_OFFSET * 32) + (BDRST_BitNumber * 4))
+/* --- CSR Register ---*/
+/* Alias word address of LSION bit */
+#define CSR_OFFSET                (RCC_OFFSET + 0x74)
+#define LSION_BitNumber           0x00
+#define CSR_LSION_BB              (PERIPH_BB_BASE + (CSR_OFFSET * 32) + (LSION_BitNumber * 4))
+/* ---------------------- RCC registers bit mask ------------------------ */
+/* CFGR register bit mask */
+#define CFGR_MCO2_RESET_MASK      ((uint32_t)0x07FFFFFF)
+#define CFGR_MCO1_RESET_MASK      ((uint32_t)0xF89FFFFF)
+
+/* RCC Flag Mask */
+#define FLAG_MASK                 ((uint8_t)0x1F)
+
+/* CR register byte 3 (Bits[23:16]) base address */
+#define CR_BYTE3_ADDRESS          ((uint32_t)0x40023802)
+
+/* CIR register byte 2 (Bits[15:8]) base address */
+#define CIR_BYTE2_ADDRESS         ((uint32_t)(RCC_BASE + 0x0C + 0x01))
+
+/* CIR register byte 3 (Bits[23:16]) base address */
+#define CIR_BYTE3_ADDRESS         ((uint32_t)(RCC_BASE + 0x0C + 0x02))
+
+/* BDCR register base address */
+#define BDCR_ADDRESS              (PERIPH_BASE + BDCR_OFFSET)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+static __I uint8_t APBAHBPrescTable[16] = {0, 0, 0, 0, 1, 2, 3, 4, 1, 2, 3, 4, 6, 7, 8, 9};
+
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RCC_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup RCC_Group1 Internal and external clocks, PLL, CSS and MCO configuration functions
+ *  @brief   Internal and external clocks, PLL, CSS and MCO configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+      Internal/external clocks, PLL, CSS and MCO configuration functions
+ ===============================================================================  
+
+  This section provide functions allowing to configure the internal/external clocks,
+  PLLs, CSS and MCO pins.
+  
+  1. HSI (high-speed internal), 16 MHz factory-trimmed RC used directly or through
+     the PLL as System clock source.
+
+  2. LSI (low-speed internal), 32 KHz low consumption RC used as IWDG and/or RTC
+     clock source.
+
+  3. HSE (high-speed external), 4 to 26 MHz crystal oscillator used directly or
+     through the PLL as System clock source. Can be used also as RTC clock source.
+
+  4. LSE (low-speed external), 32 KHz oscillator used as RTC clock source.   
+
+  5. PLL (clocked by HSI or HSE), featuring two different output clocks:
+      - The first output is used to generate the high speed system clock (up to 120 MHz)
+      - The second output is used to generate the clock for the USB OTG FS (48 MHz),
+        the random analog generator (<=48 MHz) and the SDIO (<= 48 MHz).
+
+  6. PLLI2S (clocked by HSI or HSE), used to generate an accurate clock to achieve 
+     high-quality audio performance on the I2S interface.
+  
+  7. CSS (Clock security system), once enable and if a HSE clock failure occurs 
+     (HSE used directly or through PLL as System clock source), the System clock
+     is automatically switched to HSI and an interrupt is generated if enabled. 
+     The interrupt is linked to the Cortex-M4 NMI (Non-Maskable Interrupt) 
+     exception vector.   
+
+  8. MCO1 (microcontroller clock output), used to output HSI, LSE, HSE or PLL
+     clock (through a configurable prescaler) on PA8 pin.
+
+  9. MCO2 (microcontroller clock output), used to output HSE, PLL, SYSCLK or PLLI2S
+     clock (through a configurable prescaler) on PC9 pin.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Resets the RCC clock configuration to the default reset state.
+  * @note   The default reset state of the clock configuration is given below:
+  *            - HSI ON and used as system clock source
+  *            - HSE, PLL and PLLI2S OFF
+  *            - AHB, APB1 and APB2 prescaler set to 1.
+  *            - CSS, MCO1 and MCO2 OFF
+  *            - All interrupts disabled
+  * @note   This function doesn't modify the configuration of the
+  *            - Peripheral clocks
+  *            - LSI, LSE and RTC clocks 
+  * @param  None
+  * @retval None
+  */
+void RCC_DeInit(void)
+{
+  /* Set HSION bit */
+  RCC->CR |= (uint32_t)0x00000001;
+
+  /* Reset CFGR register */
+  RCC->CFGR = 0x00000000;
+
+  /* Reset HSEON, CSSON and PLLON bits */
+  RCC->CR &= (uint32_t)0xFEF6FFFF;
+
+  /* Reset PLLCFGR register */
+  RCC->PLLCFGR = 0x24003010;
+
+  /* Reset HSEBYP bit */
+  RCC->CR &= (uint32_t)0xFFFBFFFF;
+
+  /* Disable all interrupts */
+  RCC->CIR = 0x00000000;
+}
+
+/**
+  * @brief  Configures the External High Speed oscillator (HSE).
+  * @note   After enabling the HSE (RCC_HSE_ON or RCC_HSE_Bypass), the application
+  *         software should wait on HSERDY flag to be set indicating that HSE clock
+  *         is stable and can be used to clock the PLL and/or system clock.
+  * @note   HSE state can not be changed if it is used directly or through the
+  *         PLL as system clock. In this case, you have to select another source
+  *         of the system clock then change the HSE state (ex. disable it).
+  * @note   The HSE is stopped by hardware when entering STOP and STANDBY modes.  
+  * @note   This function reset the CSSON bit, so if the Clock security system(CSS)
+  *         was previously enabled you have to enable it again after calling this
+  *         function.    
+  * @param  RCC_HSE: specifies the new state of the HSE.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_HSE_OFF: turn OFF the HSE oscillator, HSERDY flag goes low after
+  *                              6 HSE oscillator clock cycles.
+  *            @arg RCC_HSE_ON: turn ON the HSE oscillator
+  *            @arg RCC_HSE_Bypass: HSE oscillator bypassed with external clock
+  * @retval None
+  */
+void RCC_HSEConfig(uint8_t RCC_HSE)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_HSE(RCC_HSE));
+
+  /* Reset HSEON and HSEBYP bits before configuring the HSE ------------------*/
+  *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE_OFF;
+
+  /* Set the new HSE configuration -------------------------------------------*/
+  *(__IO uint8_t *) CR_BYTE3_ADDRESS = RCC_HSE;
+}
+
+/**
+  * @brief  Waits for HSE start-up.
+  * @note   This functions waits on HSERDY flag to be set and return SUCCESS if 
+  *         this flag is set, otherwise returns ERROR if the timeout is reached 
+  *         and this flag is not set. The timeout value is defined by the constant
+  *         HSE_STARTUP_TIMEOUT in stm32f4xx.h file. You can tailor it depending
+  *         on the HSE crystal used in your application. 
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: HSE oscillator is stable and ready to use
+  *          - ERROR: HSE oscillator not yet ready
+  */
+ErrorStatus RCC_WaitForHSEStartUp(void)
+{
+  __IO uint32_t startupcounter = 0;
+  ErrorStatus status = ERROR;
+  FlagStatus hsestatus = RESET;
+  /* Wait till HSE is ready and if Time out is reached exit */
+  do
+  {
+    hsestatus = RCC_GetFlagStatus(RCC_FLAG_HSERDY);
+    startupcounter++;
+  } while((startupcounter != HSE_STARTUP_TIMEOUT) && (hsestatus == RESET));
+
+  if (RCC_GetFlagStatus(RCC_FLAG_HSERDY) != RESET)
+  {
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }
+  return (status);
+}
+
+/**
+  * @brief  Adjusts the Internal High Speed oscillator (HSI) calibration value.
+  * @note   The calibration is used to compensate for the variations in voltage
+  *         and temperature that influence the frequency of the internal HSI RC.
+  * @param  HSICalibrationValue: specifies the calibration trimming value.
+  *         This parameter must be a number between 0 and 0x1F.
+  * @retval None
+  */
+void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_RCC_CALIBRATION_VALUE(HSICalibrationValue));
+
+  tmpreg = RCC->CR;
+
+  /* Clear HSITRIM[4:0] bits */
+  tmpreg &= ~RCC_CR_HSITRIM;
+
+  /* Set the HSITRIM[4:0] bits according to HSICalibrationValue value */
+  tmpreg |= (uint32_t)HSICalibrationValue << 3;
+
+  /* Store the new value */
+  RCC->CR = tmpreg;
+}
+
+/**
+  * @brief  Enables or disables the Internal High Speed oscillator (HSI).
+  * @note   The HSI is stopped by hardware when entering STOP and STANDBY modes.
+  *         It is used (enabled by hardware) as system clock source after startup
+  *         from Reset, wakeup from STOP and STANDBY mode, or in case of failure
+  *         of the HSE used directly or indirectly as system clock (if the Clock
+  *         Security System CSS is enabled).             
+  * @note   HSI can not be stopped if it is used as system clock source. In this case,
+  *         you have to select another source of the system clock then stop the HSI.  
+  * @note   After enabling the HSI, the application software should wait on HSIRDY
+  *         flag to be set indicating that HSI clock is stable and can be used as
+  *         system clock source.  
+  * @param  NewState: new state of the HSI.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When the HSI is stopped, HSIRDY flag goes low after 6 HSI oscillator
+  *         clock cycles.  
+  * @retval None
+  */
+void RCC_HSICmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CR_HSION_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Configures the External Low Speed oscillator (LSE).
+  * @note   As the LSE is in the Backup domain and write access is denied to
+  *         this domain after reset, you have to enable write access using 
+  *         PWR_BackupAccessCmd(ENABLE) function before to configure the LSE
+  *         (to be done once after reset).  
+  * @note   After enabling the LSE (RCC_LSE_ON or RCC_LSE_Bypass), the application
+  *         software should wait on LSERDY flag to be set indicating that LSE clock
+  *         is stable and can be used to clock the RTC.
+  * @param  RCC_LSE: specifies the new state of the LSE.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_LSE_OFF: turn OFF the LSE oscillator, LSERDY flag goes low after
+  *                              6 LSE oscillator clock cycles.
+  *            @arg RCC_LSE_ON: turn ON the LSE oscillator
+  *            @arg RCC_LSE_Bypass: LSE oscillator bypassed with external clock
+  * @retval None
+  */
+void RCC_LSEConfig(uint8_t RCC_LSE)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_LSE(RCC_LSE));
+
+  /* Reset LSEON and LSEBYP bits before configuring the LSE ------------------*/
+  /* Reset LSEON bit */
+  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
+
+  /* Reset LSEBYP bit */
+  *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_OFF;
+
+  /* Configure LSE (RCC_LSE_OFF is already covered by the code section above) */
+  switch (RCC_LSE)
+  {
+    case RCC_LSE_ON:
+      /* Set LSEON bit */
+      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_ON;
+      break;
+    case RCC_LSE_Bypass:
+      /* Set LSEBYP and LSEON bits */
+      *(__IO uint8_t *) BDCR_ADDRESS = RCC_LSE_Bypass | RCC_LSE_ON;
+      break;
+    default:
+      break;
+  }
+}
+
+/**
+  * @brief  Enables or disables the Internal Low Speed oscillator (LSI).
+  * @note   After enabling the LSI, the application software should wait on 
+  *         LSIRDY flag to be set indicating that LSI clock is stable and can
+  *         be used to clock the IWDG and/or the RTC.
+  * @note   LSI can not be disabled if the IWDG is running.  
+  * @param  NewState: new state of the LSI.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @note   When the LSI is stopped, LSIRDY flag goes low after 6 LSI oscillator
+  *         clock cycles. 
+  * @retval None
+  */
+void RCC_LSICmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CSR_LSION_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Configures the main PLL clock source, multiplication and division factors.
+  * @note   This function must be used only when the main PLL is disabled.
+  *  
+  * @param  RCC_PLLSource: specifies the PLL entry clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_PLLSource_HSI: HSI oscillator clock selected as PLL clock entry
+  *            @arg RCC_PLLSource_HSE: HSE oscillator clock selected as PLL clock entry
+  * @note   This clock source (RCC_PLLSource) is common for the main PLL and PLLI2S.  
+  *  
+  * @param  PLLM: specifies the division factor for PLL VCO input clock
+  *          This parameter must be a number between 0 and 63.
+  * @note   You have to set the PLLM parameter correctly to ensure that the VCO input
+  *         frequency ranges from 1 to 2 MHz. It is recommended to select a frequency
+  *         of 2 MHz to limit PLL jitter.
+  *  
+  * @param  PLLN: specifies the multiplication factor for PLL VCO output clock
+  *          This parameter must be a number between 192 and 432.
+  * @note   You have to set the PLLN parameter correctly to ensure that the VCO
+  *         output frequency is between 192 and 432 MHz.
+  *   
+  * @param  PLLP: specifies the division factor for main system clock (SYSCLK)
+  *          This parameter must be a number in the range {2, 4, 6, or 8}.
+  * @note   You have to set the PLLP parameter correctly to not exceed 120 MHz on
+  *         the System clock frequency.
+  *  
+  * @param  PLLQ: specifies the division factor for OTG FS, SDIO and RNG clocks
+  *          This parameter must be a number between 4 and 15.
+  * @note   If the USB OTG FS is used in your application, you have to set the
+  *         PLLQ parameter correctly to have 48 MHz clock for the USB. However,
+  *         the SDIO and RNG need a frequency lower than or equal to 48 MHz to work
+  *         correctly.
+  *   
+  * @retval None
+  */
+void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t PLLM, uint32_t PLLN, uint32_t PLLP, uint32_t PLLQ)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_PLL_SOURCE(RCC_PLLSource));
+  assert_param(IS_RCC_PLLM_VALUE(PLLM));
+  assert_param(IS_RCC_PLLN_VALUE(PLLN));
+  assert_param(IS_RCC_PLLP_VALUE(PLLP));
+  assert_param(IS_RCC_PLLQ_VALUE(PLLQ));
+
+  RCC->PLLCFGR = PLLM | (PLLN << 6) | (((PLLP >> 1) -1) << 16) | (RCC_PLLSource) |
+                 (PLLQ << 24);
+}
+
+/**
+  * @brief  Enables or disables the main PLL.
+  * @note   After enabling the main PLL, the application software should wait on 
+  *         PLLRDY flag to be set indicating that PLL clock is stable and can
+  *         be used as system clock source.
+  * @note   The main PLL can not be disabled if it is used as system clock source
+  * @note   The main PLL is disabled by hardware when entering STOP and STANDBY modes.
+  * @param  NewState: new state of the main PLL. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_PLLCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CR_PLLON_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Configures the PLLI2S clock multiplication and division factors.
+  *   
+  * @note   PLLI2S is available only in Silicon RevisionB and RevisionY.    
+  * @note   This function must be used only when the PLLI2S is disabled.
+  * @note   PLLI2S clock source is common with the main PLL (configured in 
+  *         RCC_PLLConfig function )  
+  *             
+  * @param  PLLI2SN: specifies the multiplication factor for PLLI2S VCO output clock
+  *          This parameter must be a number between 192 and 432.
+  * @note   You have to set the PLLI2SN parameter correctly to ensure that the VCO 
+  *         output frequency is between 192 and 432 MHz.
+  *    
+  * @param  PLLI2SR: specifies the division factor for I2S clock
+  *          This parameter must be a number between 2 and 7.
+  * @note   You have to set the PLLI2SR parameter correctly to not exceed 192 MHz
+  *         on the I2S clock frequency.
+  *   
+  * @retval None
+  */
+void RCC_PLLI2SConfig(uint32_t PLLI2SN, uint32_t PLLI2SR)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_PLLI2SN_VALUE(PLLI2SN));
+  assert_param(IS_RCC_PLLI2SR_VALUE(PLLI2SR));
+
+  RCC->PLLI2SCFGR = (PLLI2SN << 6) | (PLLI2SR << 28);
+}
+
+/**
+  * @brief  Enables or disables the PLLI2S.
+  * @note   PLLI2S is available only in RevisionB and RevisionY 
+  * @note   The PLLI2S is disabled by hardware when entering STOP and STANDBY modes.  
+  * @param  NewState: new state of the PLLI2S. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_PLLI2SCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CR_PLLI2SON_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the Clock Security System.
+  * @note   If a failure is detected on the HSE oscillator clock, this oscillator
+  *         is automatically disabled and an interrupt is generated to inform the
+  *         software about the failure (Clock Security System Interrupt, CSSI),
+  *         allowing the MCU to perform rescue operations. The CSSI is linked to 
+  *         the Cortex-M4 NMI (Non-Maskable Interrupt) exception vector.  
+  * @param  NewState: new state of the Clock Security System.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_ClockSecuritySystemCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) CR_CSSON_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Selects the clock source to output on MCO1 pin(PA8).
+  * @note   PA8 should be configured in alternate function mode.
+  * @param  RCC_MCO1Source: specifies the clock source to output.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1Source_HSI: HSI clock selected as MCO1 source
+  *            @arg RCC_MCO1Source_LSE: LSE clock selected as MCO1 source
+  *            @arg RCC_MCO1Source_HSE: HSE clock selected as MCO1 source
+  *            @arg RCC_MCO1Source_PLLCLK: main PLL clock selected as MCO1 source
+  * @param  RCC_MCO1Div: specifies the MCO1 prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO1Div_1: no division applied to MCO1 clock
+  *            @arg RCC_MCO1Div_2: division by 2 applied to MCO1 clock
+  *            @arg RCC_MCO1Div_3: division by 3 applied to MCO1 clock
+  *            @arg RCC_MCO1Div_4: division by 4 applied to MCO1 clock
+  *            @arg RCC_MCO1Div_5: division by 5 applied to MCO1 clock
+  * @retval None
+  */
+void RCC_MCO1Config(uint32_t RCC_MCO1Source, uint32_t RCC_MCO1Div)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_MCO1SOURCE(RCC_MCO1Source));
+  assert_param(IS_RCC_MCO1DIV(RCC_MCO1Div));  
+
+  tmpreg = RCC->CFGR;
+
+  /* Clear MCO1[1:0] and MCO1PRE[2:0] bits */
+  tmpreg &= CFGR_MCO1_RESET_MASK;
+
+  /* Select MCO1 clock source and prescaler */
+  tmpreg |= RCC_MCO1Source | RCC_MCO1Div;
+
+  /* Store the new value */
+  RCC->CFGR = tmpreg;  
+}
+
+/**
+  * @brief  Selects the clock source to output on MCO2 pin(PC9).
+  * @note   PC9 should be configured in alternate function mode.
+  * @param  RCC_MCO2Source: specifies the clock source to output.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO2Source_SYSCLK: System clock (SYSCLK) selected as MCO2 source
+  *            @arg RCC_MCO2Source_PLLI2SCLK: PLLI2S clock selected as MCO2 source
+  *            @arg RCC_MCO2Source_HSE: HSE clock selected as MCO2 source
+  *            @arg RCC_MCO2Source_PLLCLK: main PLL clock selected as MCO2 source
+  * @param  RCC_MCO2Div: specifies the MCO2 prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_MCO2Div_1: no division applied to MCO2 clock
+  *            @arg RCC_MCO2Div_2: division by 2 applied to MCO2 clock
+  *            @arg RCC_MCO2Div_3: division by 3 applied to MCO2 clock
+  *            @arg RCC_MCO2Div_4: division by 4 applied to MCO2 clock
+  *            @arg RCC_MCO2Div_5: division by 5 applied to MCO2 clock
+  * @retval None
+  */
+void RCC_MCO2Config(uint32_t RCC_MCO2Source, uint32_t RCC_MCO2Div)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_MCO2SOURCE(RCC_MCO2Source));
+  assert_param(IS_RCC_MCO2DIV(RCC_MCO2Div));
+  
+  tmpreg = RCC->CFGR;
+  
+  /* Clear MCO2 and MCO2PRE[2:0] bits */
+  tmpreg &= CFGR_MCO2_RESET_MASK;
+
+  /* Select MCO2 clock source and prescaler */
+  tmpreg |= RCC_MCO2Source | RCC_MCO2Div;
+
+  /* Store the new value */
+  RCC->CFGR = tmpreg;  
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Group2 System AHB and APB busses clocks configuration functions
+ *  @brief   System, AHB and APB busses clocks configuration functions
+ *
+@verbatim   
+ ===============================================================================
+             System, AHB and APB busses clocks configuration functions
+ ===============================================================================  
+
+  This section provide functions allowing to configure the System, AHB, APB1 and 
+  APB2 busses clocks.
+  
+  1. Several clock sources can be used to drive the System clock (SYSCLK): HSI,
+     HSE and PLL.
+     The AHB clock (HCLK) is derived from System clock through configurable prescaler
+     and used to clock the CPU, memory and peripherals mapped on AHB bus (DMA, GPIO...).
+     APB1 (PCLK1) and APB2 (PCLK2) clocks are derived from AHB clock through 
+     configurable prescalers and used to clock the peripherals mapped on these busses.
+     You can use "RCC_GetClocksFreq()" function to retrieve the frequencies of these clocks.  
+
+@note All the peripheral clocks are derived from the System clock (SYSCLK) except:
+       - I2S: the I2S clock can be derived either from a specific PLL (PLLI2S) or
+          from an external clock mapped on the I2S_CKIN pin. 
+          You have to use RCC_I2SCLKConfig() function to configure this clock. 
+       - RTC: the RTC clock can be derived either from the LSI, LSE or HSE clock
+          divided by 2 to 31. You have to use RCC_RTCCLKConfig() and RCC_RTCCLKCmd()
+          functions to configure this clock. 
+       - USB OTG FS, SDIO and RTC: USB OTG FS require a frequency equal to 48 MHz
+          to work correctly, while the SDIO require a frequency equal or lower than
+          to 48. This clock is derived of the main PLL through PLLQ divider.
+       - IWDG clock which is always the LSI clock.
+       
+  2. The maximum frequency of the SYSCLK and HCLK is 120 MHz, PCLK2 60 MHz and PCLK1 30 MHz.
+     Depending on the device voltage range, the maximum frequency should be 
+     adapted accordingly:
+ +-------------------------------------------------------------------------------------+     
+ | Latency       |                HCLK clock frequency (MHz)                           |
+ |               |---------------------------------------------------------------------|     
+ |               | voltage range  | voltage range  | voltage range   | voltage range   |
+ |               | 2.7 V - 3.6 V  | 2.4 V - 2.7 V  | 2.1 V - 2.4 V   | 1.8 V - 2.1 V   |
+ |---------------|----------------|----------------|-----------------|-----------------|              
+ |0WS(1CPU cycle)|0 < HCLK <= 30  |0 < HCLK <= 24  |0 < HCLK <= 18   |0 < HCLK <= 16   |
+ |---------------|----------------|----------------|-----------------|-----------------|   
+ |1WS(2CPU cycle)|30 < HCLK <= 60 |24 < HCLK <= 48 |18 < HCLK <= 36  |16 < HCLK <= 32  | 
+ |---------------|----------------|----------------|-----------------|-----------------|   
+ |2WS(3CPU cycle)|60 < HCLK <= 90 |48 < HCLK <= 72 |36 < HCLK <= 54  |32 < HCLK <= 48  |
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |3WS(4CPU cycle)|90 < HCLK <= 120|72 < HCLK <= 96 |54 < HCLK <= 72  |48 < HCLK <= 64  |
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |4WS(5CPU cycle)|      NA        |96 < HCLK <= 120|72 < HCLK <= 90  |64 < HCLK <= 80  |
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |5WS(6CPU cycle)|      NA        |      NA        |90 < HCLK <= 108 |80 < HCLK <= 96  | 
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |6WS(7CPU cycle)|      NA        |      NA        |108 < HCLK <= 120|96 < HCLK <= 112 | 
+ |---------------|----------------|----------------|-----------------|-----------------| 
+ |7WS(8CPU cycle)|      NA        |     NA         |     NA          |112 < HCLK <= 120| 
+ +-------------------------------------------------------------------------------------+    
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the system clock (SYSCLK).
+  * @note   The HSI is used (enabled by hardware) as system clock source after
+  *         startup from Reset, wake-up from STOP and STANDBY mode, or in case
+  *         of failure of the HSE used directly or indirectly as system clock
+  *         (if the Clock Security System CSS is enabled).
+  * @note   A switch from one clock source to another occurs only if the target
+  *         clock source is ready (clock stable after startup delay or PLL locked). 
+  *         If a clock source which is not yet ready is selected, the switch will
+  *         occur when the clock source will be ready. 
+  *         You can use RCC_GetSYSCLKSource() function to know which clock is
+  *         currently used as system clock source. 
+  * @param  RCC_SYSCLKSource: specifies the clock source used as system clock.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_SYSCLKSource_HSI:    HSI selected as system clock source
+  *            @arg RCC_SYSCLKSource_HSE:    HSE selected as system clock source
+  *            @arg RCC_SYSCLKSource_PLLCLK: PLL selected as system clock source
+  * @retval None
+  */
+void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_SYSCLK_SOURCE(RCC_SYSCLKSource));
+
+  tmpreg = RCC->CFGR;
+
+  /* Clear SW[1:0] bits */
+  tmpreg &= ~RCC_CFGR_SW;
+
+  /* Set SW[1:0] bits according to RCC_SYSCLKSource value */
+  tmpreg |= RCC_SYSCLKSource;
+
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Returns the clock source used as system clock.
+  * @param  None
+  * @retval The clock source used as system clock. The returned value can be one
+  *         of the following:
+  *              - 0x00: HSI used as system clock
+  *              - 0x04: HSE used as system clock
+  *              - 0x08: PLL used as system clock
+  */
+uint8_t RCC_GetSYSCLKSource(void)
+{
+  return ((uint8_t)(RCC->CFGR & RCC_CFGR_SWS));
+}
+
+/**
+  * @brief  Configures the AHB clock (HCLK).
+  * @note   Depending on the device voltage range, the software has to set correctly
+  *         these bits to ensure that HCLK not exceed the maximum allowed frequency
+  *         (for more details refer to section above
+  *           "CPU, AHB and APB busses clocks configuration functions")
+  * @param  RCC_SYSCLK: defines the AHB clock divider. This clock is derived from 
+  *         the system clock (SYSCLK).
+  *          This parameter can be one of the following values:
+  *            @arg RCC_SYSCLK_Div1: AHB clock = SYSCLK
+  *            @arg RCC_SYSCLK_Div2: AHB clock = SYSCLK/2
+  *            @arg RCC_SYSCLK_Div4: AHB clock = SYSCLK/4
+  *            @arg RCC_SYSCLK_Div8: AHB clock = SYSCLK/8
+  *            @arg RCC_SYSCLK_Div16: AHB clock = SYSCLK/16
+  *            @arg RCC_SYSCLK_Div64: AHB clock = SYSCLK/64
+  *            @arg RCC_SYSCLK_Div128: AHB clock = SYSCLK/128
+  *            @arg RCC_SYSCLK_Div256: AHB clock = SYSCLK/256
+  *            @arg RCC_SYSCLK_Div512: AHB clock = SYSCLK/512
+  * @retval None
+  */
+void RCC_HCLKConfig(uint32_t RCC_SYSCLK)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RCC_HCLK(RCC_SYSCLK));
+
+  tmpreg = RCC->CFGR;
+
+  /* Clear HPRE[3:0] bits */
+  tmpreg &= ~RCC_CFGR_HPRE;
+
+  /* Set HPRE[3:0] bits according to RCC_SYSCLK value */
+  tmpreg |= RCC_SYSCLK;
+
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+
+/**
+  * @brief  Configures the Low Speed APB clock (PCLK1).
+  * @param  RCC_HCLK: defines the APB1 clock divider. This clock is derived from 
+  *         the AHB clock (HCLK).
+  *          This parameter can be one of the following values:
+  *            @arg RCC_HCLK_Div1:  APB1 clock = HCLK
+  *            @arg RCC_HCLK_Div2:  APB1 clock = HCLK/2
+  *            @arg RCC_HCLK_Div4:  APB1 clock = HCLK/4
+  *            @arg RCC_HCLK_Div8:  APB1 clock = HCLK/8
+  *            @arg RCC_HCLK_Div16: APB1 clock = HCLK/16
+  * @retval None
+  */
+void RCC_PCLK1Config(uint32_t RCC_HCLK)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PCLK(RCC_HCLK));
+
+  tmpreg = RCC->CFGR;
+
+  /* Clear PPRE1[2:0] bits */
+  tmpreg &= ~RCC_CFGR_PPRE1;
+
+  /* Set PPRE1[2:0] bits according to RCC_HCLK value */
+  tmpreg |= RCC_HCLK;
+
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Configures the High Speed APB clock (PCLK2).
+  * @param  RCC_HCLK: defines the APB2 clock divider. This clock is derived from 
+  *         the AHB clock (HCLK).
+  *          This parameter can be one of the following values:
+  *            @arg RCC_HCLK_Div1:  APB2 clock = HCLK
+  *            @arg RCC_HCLK_Div2:  APB2 clock = HCLK/2
+  *            @arg RCC_HCLK_Div4:  APB2 clock = HCLK/4
+  *            @arg RCC_HCLK_Div8:  APB2 clock = HCLK/8
+  *            @arg RCC_HCLK_Div16: APB2 clock = HCLK/16
+  * @retval None
+  */
+void RCC_PCLK2Config(uint32_t RCC_HCLK)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_PCLK(RCC_HCLK));
+
+  tmpreg = RCC->CFGR;
+
+  /* Clear PPRE2[2:0] bits */
+  tmpreg &= ~RCC_CFGR_PPRE2;
+
+  /* Set PPRE2[2:0] bits according to RCC_HCLK value */
+  tmpreg |= RCC_HCLK << 3;
+
+  /* Store the new value */
+  RCC->CFGR = tmpreg;
+}
+
+/**
+  * @brief  Returns the frequencies of different on chip clocks; SYSCLK, HCLK, 
+  *         PCLK1 and PCLK2.       
+  * 
+  * @note   The system frequency computed by this function is not the real 
+  *         frequency in the chip. It is calculated based on the predefined 
+  *         constant and the selected clock source:
+  * @note     If SYSCLK source is HSI, function returns values based on HSI_VALUE(*)
+  * @note     If SYSCLK source is HSE, function returns values based on HSE_VALUE(**)
+  * @note     If SYSCLK source is PLL, function returns values based on HSE_VALUE(**) 
+  *           or HSI_VALUE(*) multiplied/divided by the PLL factors.         
+  * @note     (*) HSI_VALUE is a constant defined in stm32f4xx.h file (default value
+  *               16 MHz) but the real value may vary depending on the variations
+  *               in voltage and temperature.
+  * @note     (**) HSE_VALUE is a constant defined in stm32f4xx.h file (default value
+  *                25 MHz), user has to ensure that HSE_VALUE is same as the real
+  *                frequency of the crystal used. Otherwise, this function may
+  *                have wrong result.
+  *                
+  * @note   The result of this function could be not correct when using fractional
+  *         value for HSE crystal.
+  *   
+  * @param  RCC_Clocks: pointer to a RCC_ClocksTypeDef structure which will hold
+  *          the clocks frequencies.
+  *     
+  * @note   This function can be used by the user application to compute the 
+  *         baudrate for the communication peripherals or configure other parameters.
+  * @note   Each time SYSCLK, HCLK, PCLK1 and/or PCLK2 clock changes, this function
+  *         must be called to update the structure's field. Otherwise, any
+  *         configuration based on this function will be incorrect.
+  *    
+  * @retval None
+  */
+void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks)
+{
+  uint32_t tmp = 0, presc = 0, pllvco = 0, pllp = 2, pllsource = 0, pllm = 2;
+
+  /* Get SYSCLK source -------------------------------------------------------*/
+  tmp = RCC->CFGR & RCC_CFGR_SWS;
+
+  switch (tmp)
+  {
+    case 0x00:  /* HSI used as system clock source */
+      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+      break;
+    case 0x04:  /* HSE used as system clock  source */
+      RCC_Clocks->SYSCLK_Frequency = HSE_VALUE;
+      break;
+    case 0x08:  /* PLL used as system clock  source */
+
+      /* PLL_VCO = (HSE_VALUE or HSI_VALUE / PLLM) * PLLN
+         SYSCLK = PLL_VCO / PLLP
+         */    
+      pllsource = (RCC->PLLCFGR & RCC_PLLCFGR_PLLSRC) >> 22;
+      pllm = RCC->PLLCFGR & RCC_PLLCFGR_PLLM;
+      
+      if (pllsource != 0)
+      {
+        /* HSE used as PLL clock source */
+        pllvco = (HSE_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);
+      }
+      else
+      {
+        /* HSI used as PLL clock source */
+        pllvco = (HSI_VALUE / pllm) * ((RCC->PLLCFGR & RCC_PLLCFGR_PLLN) >> 6);      
+      }
+
+      pllp = (((RCC->PLLCFGR & RCC_PLLCFGR_PLLP) >>16) + 1 ) *2;
+      RCC_Clocks->SYSCLK_Frequency = pllvco/pllp;
+      break;
+    default:
+      RCC_Clocks->SYSCLK_Frequency = HSI_VALUE;
+      break;
+  }
+  /* Compute HCLK, PCLK1 and PCLK2 clocks frequencies ------------------------*/
+
+  /* Get HCLK prescaler */
+  tmp = RCC->CFGR & RCC_CFGR_HPRE;
+  tmp = tmp >> 4;
+  presc = APBAHBPrescTable[tmp];
+  /* HCLK clock frequency */
+  RCC_Clocks->HCLK_Frequency = RCC_Clocks->SYSCLK_Frequency >> presc;
+
+  /* Get PCLK1 prescaler */
+  tmp = RCC->CFGR & RCC_CFGR_PPRE1;
+  tmp = tmp >> 10;
+  presc = APBAHBPrescTable[tmp];
+  /* PCLK1 clock frequency */
+  RCC_Clocks->PCLK1_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+
+  /* Get PCLK2 prescaler */
+  tmp = RCC->CFGR & RCC_CFGR_PPRE2;
+  tmp = tmp >> 13;
+  presc = APBAHBPrescTable[tmp];
+  /* PCLK2 clock frequency */
+  RCC_Clocks->PCLK2_Frequency = RCC_Clocks->HCLK_Frequency >> presc;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Group3 Peripheral clocks configuration functions
+ *  @brief   Peripheral clocks configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                   Peripheral clocks configuration functions
+ ===============================================================================  
+
+  This section provide functions allowing to configure the Peripheral clocks. 
+  
+  1. The RTC clock which is derived from the LSI, LSE or HSE clock divided by 2 to 31.
+     
+  2. After restart from Reset or wakeup from STANDBY, all peripherals are off
+     except internal SRAM, Flash and JTAG. Before to start using a peripheral you
+     have to enable its interface clock. You can do this using RCC_AHBPeriphClockCmd()
+     , RCC_APB2PeriphClockCmd() and RCC_APB1PeriphClockCmd() functions.
+
+  3. To reset the peripherals configuration (to the default state after device reset)
+     you can use RCC_AHBPeriphResetCmd(), RCC_APB2PeriphResetCmd() and 
+     RCC_APB1PeriphResetCmd() functions.
+     
+  4. To further reduce power consumption in SLEEP mode the peripheral clocks can
+     be disabled prior to executing the WFI or WFE instructions. You can do this
+     using RCC_AHBPeriphClockLPModeCmd(), RCC_APB2PeriphClockLPModeCmd() and
+     RCC_APB1PeriphClockLPModeCmd() functions.  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the RTC clock (RTCCLK).
+  * @note   As the RTC clock configuration bits are in the Backup domain and write
+  *         access is denied to this domain after reset, you have to enable write
+  *         access using PWR_BackupAccessCmd(ENABLE) function before to configure
+  *         the RTC clock source (to be done once after reset).    
+  * @note   Once the RTC clock is configured it can't be changed unless the  
+  *         Backup domain is reset using RCC_BackupResetCmd() function, or by
+  *         a Power On Reset (POR).
+  *    
+  * @param  RCC_RTCCLKSource: specifies the RTC clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_RTCCLKSource_LSE: LSE selected as RTC clock
+  *            @arg RCC_RTCCLKSource_LSI: LSI selected as RTC clock
+  *            @arg RCC_RTCCLKSource_HSE_Divx: HSE clock divided by x selected
+  *                                            as RTC clock, where x:[2,31]
+  *  
+  * @note   If the LSE or LSI is used as RTC clock source, the RTC continues to
+  *         work in STOP and STANDBY modes, and can be used as wakeup source.
+  *         However, when the HSE clock is used as RTC clock source, the RTC
+  *         cannot be used in STOP and STANDBY modes.    
+  * @note   The maximum input clock frequency for RTC is 1MHz (when using HSE as
+  *         RTC clock source).
+  *  
+  * @retval None
+  */
+void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_RTCCLK_SOURCE(RCC_RTCCLKSource));
+
+  if ((RCC_RTCCLKSource & 0x00000300) == 0x00000300)
+  { /* If HSE is selected as RTC clock source, configure HSE division factor for RTC clock */
+    tmpreg = RCC->CFGR;
+
+    /* Clear RTCPRE[4:0] bits */
+    tmpreg &= ~RCC_CFGR_RTCPRE;
+
+    /* Configure HSE division factor for RTC clock */
+    tmpreg |= (RCC_RTCCLKSource & 0xFFFFCFF);
+
+    /* Store the new value */
+    RCC->CFGR = tmpreg;
+  }
+    
+  /* Select the RTC clock source */
+  RCC->BDCR |= (RCC_RTCCLKSource & 0x00000FFF);
+}
+
+/**
+  * @brief  Enables or disables the RTC clock.
+  * @note   This function must be used only after the RTC clock source was selected
+  *         using the RCC_RTCCLKConfig function.
+  * @param  NewState: new state of the RTC clock. This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_RTCCLKCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) BDCR_RTCEN_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Forces or releases the Backup domain reset.
+  * @note   This function resets the RTC peripheral (including the backup registers)
+  *         and the RTC clock source selection in RCC_CSR register.
+  * @note   The BKPSRAM is not affected by this reset.    
+  * @param  NewState: new state of the Backup domain reset.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_BackupResetCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  *(__IO uint32_t *) BDCR_BDRST_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Configures the I2S clock source (I2SCLK).
+  *
+  * @note   This function must be called before enabling the I2S APB clock.
+  * @note   This function applies only to Silicon RevisionB and RevisionY.
+  *
+  * @param  RCC_I2SCLKSource: specifies the I2S clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_I2S2CLKSource_PLLI2S: PLLI2S clock used as I2S clock source
+  *            @arg RCC_I2S2CLKSource_Ext: External clock mapped on the I2S_CKIN pin
+  *                                        used as I2S clock source
+  * @retval None
+  */
+void RCC_I2SCLKConfig(uint32_t RCC_I2SCLKSource)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_I2SCLK_SOURCE(RCC_I2SCLKSource));
+
+  *(__IO uint32_t *) CFGR_I2SSRC_BB = RCC_I2SCLKSource;
+}
+
+/**
+  * @brief  Enables or disables the AHB1 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.   
+  * @param  RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
+  *          This parameter can be any combination of the following values:
+  *            @arg RCC_AHB1Periph_GPIOA:       GPIOA clock
+  *            @arg RCC_AHB1Periph_GPIOB:       GPIOB clock 
+  *            @arg RCC_AHB1Periph_GPIOC:       GPIOC clock
+  *            @arg RCC_AHB1Periph_GPIOD:       GPIOD clock
+  *            @arg RCC_AHB1Periph_GPIOE:       GPIOE clock
+  *            @arg RCC_AHB1Periph_GPIOF:       GPIOF clock
+  *            @arg RCC_AHB1Periph_GPIOG:       GPIOG clock
+  *            @arg RCC_AHB1Periph_GPIOG:       GPIOG clock
+  *            @arg RCC_AHB1Periph_GPIOI:       GPIOI clock
+  *            @arg RCC_AHB1Periph_CRC:         CRC clock
+  *            @arg RCC_AHB1Periph_BKPSRAM:     BKPSRAM interface clock
+  *            @arg RCC_AHB1Periph_DMA1:        DMA1 clock
+  *            @arg RCC_AHB1Periph_DMA2:        DMA2 clock
+  *            @arg RCC_AHB1Periph_ETH_MAC:     Ethernet MAC clock
+  *            @arg RCC_AHB1Periph_ETH_MAC_Tx:  Ethernet Transmission clock
+  *            @arg RCC_AHB1Periph_ETH_MAC_Rx:  Ethernet Reception clock
+  *            @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
+  *            @arg RCC_AHB1Periph_OTG_HS:      USB OTG HS clock
+  *            @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_AHB1PeriphClockCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_AHB1_CLOCK_PERIPH(RCC_AHB1Periph));
+
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    RCC->AHB1ENR |= RCC_AHB1Periph;
+  }
+  else
+  {
+    RCC->AHB1ENR &= ~RCC_AHB1Periph;
+  }
+}
+
+/**
+  * @brief  Enables or disables the AHB2 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it. 
+  * @param  RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
+  *          This parameter can be any combination of the following values:
+  *            @arg RCC_AHB2Periph_DCMI:   DCMI clock
+  *            @arg RCC_AHB2Periph_CRYP:   CRYP clock
+  *            @arg RCC_AHB2Periph_HASH:   HASH clock
+  *            @arg RCC_AHB2Periph_RNG:    RNG clock
+  *            @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_AHB2PeriphClockCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->AHB2ENR |= RCC_AHB2Periph;
+  }
+  else
+  {
+    RCC->AHB2ENR &= ~RCC_AHB2Periph;
+  }
+}
+
+/**
+  * @brief  Enables or disables the AHB3 peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it. 
+  * @param  RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
+  *          This parameter must be: RCC_AHB3Periph_FSMC
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_AHB3PeriphClockCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->AHB3ENR |= RCC_AHB3Periph;
+  }
+  else
+  {
+    RCC->AHB3ENR &= ~RCC_AHB3Periph;
+  }
+}
+
+/**
+  * @brief  Enables or disables the Low Speed APB (APB1) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it. 
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
+  *          This parameter can be any combination of the following values:
+  *            @arg RCC_APB1Periph_TIM2:   TIM2 clock
+  *            @arg RCC_APB1Periph_TIM3:   TIM3 clock
+  *            @arg RCC_APB1Periph_TIM4:   TIM4 clock
+  *            @arg RCC_APB1Periph_TIM5:   TIM5 clock
+  *            @arg RCC_APB1Periph_TIM6:   TIM6 clock
+  *            @arg RCC_APB1Periph_TIM7:   TIM7 clock
+  *            @arg RCC_APB1Periph_TIM12:  TIM12 clock
+  *            @arg RCC_APB1Periph_TIM13:  TIM13 clock
+  *            @arg RCC_APB1Periph_TIM14:  TIM14 clock
+  *            @arg RCC_APB1Periph_WWDG:   WWDG clock
+  *            @arg RCC_APB1Periph_SPI2:   SPI2 clock
+  *            @arg RCC_APB1Periph_SPI3:   SPI3 clock
+  *            @arg RCC_APB1Periph_USART2: USART2 clock
+  *            @arg RCC_APB1Periph_USART3: USART3 clock
+  *            @arg RCC_APB1Periph_UART4:  UART4 clock
+  *            @arg RCC_APB1Periph_UART5:  UART5 clock
+  *            @arg RCC_APB1Periph_I2C1:   I2C1 clock
+  *            @arg RCC_APB1Periph_I2C2:   I2C2 clock
+  *            @arg RCC_APB1Periph_I2C3:   I2C3 clock
+  *            @arg RCC_APB1Periph_CAN1:   CAN1 clock
+  *            @arg RCC_APB1Periph_CAN2:   CAN2 clock
+  *            @arg RCC_APB1Periph_PWR:    PWR clock
+  *            @arg RCC_APB1Periph_DAC:    DAC clock
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB1ENR |= RCC_APB1Periph;
+  }
+  else
+  {
+    RCC->APB1ENR &= ~RCC_APB1Periph;
+  }
+}
+
+/**
+  * @brief  Enables or disables the High Speed APB (APB2) peripheral clock.
+  * @note   After reset, the peripheral clock (used for registers read/write access)
+  *         is disabled and the application software has to enable this clock before 
+  *         using it.
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
+  *          This parameter can be any combination of the following values:
+  *            @arg RCC_APB2Periph_TIM1:   TIM1 clock
+  *            @arg RCC_APB2Periph_TIM8:   TIM8 clock
+  *            @arg RCC_APB2Periph_USART1: USART1 clock
+  *            @arg RCC_APB2Periph_USART6: USART6 clock
+  *            @arg RCC_APB2Periph_ADC1:   ADC1 clock
+  *            @arg RCC_APB2Periph_ADC2:   ADC2 clock
+  *            @arg RCC_APB2Periph_ADC3:   ADC3 clock
+  *            @arg RCC_APB2Periph_SDIO:   SDIO clock
+  *            @arg RCC_APB2Periph_SPI1:   SPI1 clock
+  *            @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
+  *            @arg RCC_APB2Periph_TIM9:   TIM9 clock
+  *            @arg RCC_APB2Periph_TIM10:  TIM10 clock
+  *            @arg RCC_APB2Periph_TIM11:  TIM11 clock
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->APB2ENR |= RCC_APB2Periph;
+  }
+  else
+  {
+    RCC->APB2ENR &= ~RCC_APB2Periph;
+  }
+}
+
+/**
+  * @brief  Forces or releases AHB1 peripheral reset.
+  * @param  RCC_AHB1Periph: specifies the AHB1 peripheral to reset.
+  *          This parameter can be any combination of the following values:
+  *            @arg RCC_AHB1Periph_GPIOA:   GPIOA clock
+  *            @arg RCC_AHB1Periph_GPIOB:   GPIOB clock 
+  *            @arg RCC_AHB1Periph_GPIOC:   GPIOC clock
+  *            @arg RCC_AHB1Periph_GPIOD:   GPIOD clock
+  *            @arg RCC_AHB1Periph_GPIOE:   GPIOE clock
+  *            @arg RCC_AHB1Periph_GPIOF:   GPIOF clock
+  *            @arg RCC_AHB1Periph_GPIOG:   GPIOG clock
+  *            @arg RCC_AHB1Periph_GPIOG:   GPIOG clock
+  *            @arg RCC_AHB1Periph_GPIOI:   GPIOI clock
+  *            @arg RCC_AHB1Periph_CRC:     CRC clock
+  *            @arg RCC_AHB1Periph_DMA1:    DMA1 clock
+  *            @arg RCC_AHB1Periph_DMA2:    DMA2 clock
+  *            @arg RCC_AHB1Periph_ETH_MAC: Ethernet MAC clock
+  *            @arg RCC_AHB1Periph_OTG_HS:  USB OTG HS clock
+  *                  
+  * @param  NewState: new state of the specified peripheral reset.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_AHB1PeriphResetCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_AHB1_RESET_PERIPH(RCC_AHB1Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->AHB1RSTR |= RCC_AHB1Periph;
+  }
+  else
+  {
+    RCC->AHB1RSTR &= ~RCC_AHB1Periph;
+  }
+}
+
+/**
+  * @brief  Forces or releases AHB2 peripheral reset.
+  * @param  RCC_AHB2Periph: specifies the AHB2 peripheral to reset.
+  *          This parameter can be any combination of the following values:
+  *            @arg RCC_AHB2Periph_DCMI:   DCMI clock
+  *            @arg RCC_AHB2Periph_CRYP:   CRYP clock
+  *            @arg RCC_AHB2Periph_HASH:   HASH clock
+  *            @arg RCC_AHB2Periph_RNG:    RNG clock
+  *            @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock
+  * @param  NewState: new state of the specified peripheral reset.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_AHB2PeriphResetCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->AHB2RSTR |= RCC_AHB2Periph;
+  }
+  else
+  {
+    RCC->AHB2RSTR &= ~RCC_AHB2Periph;
+  }
+}
+
+/**
+  * @brief  Forces or releases AHB3 peripheral reset.
+  * @param  RCC_AHB3Periph: specifies the AHB3 peripheral to reset.
+  *          This parameter must be: RCC_AHB3Periph_FSMC
+  * @param  NewState: new state of the specified peripheral reset.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_AHB3PeriphResetCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    RCC->AHB3RSTR |= RCC_AHB3Periph;
+  }
+  else
+  {
+    RCC->AHB3RSTR &= ~RCC_AHB3Periph;
+  }
+}
+
+/**
+  * @brief  Forces or releases Low Speed APB (APB1) peripheral reset.
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to reset.
+  *          This parameter can be any combination of the following values:
+  *            @arg RCC_APB1Periph_TIM2:   TIM2 clock
+  *            @arg RCC_APB1Periph_TIM3:   TIM3 clock
+  *            @arg RCC_APB1Periph_TIM4:   TIM4 clock
+  *            @arg RCC_APB1Periph_TIM5:   TIM5 clock
+  *            @arg RCC_APB1Periph_TIM6:   TIM6 clock
+  *            @arg RCC_APB1Periph_TIM7:   TIM7 clock
+  *            @arg RCC_APB1Periph_TIM12:  TIM12 clock
+  *            @arg RCC_APB1Periph_TIM13:  TIM13 clock
+  *            @arg RCC_APB1Periph_TIM14:  TIM14 clock
+  *            @arg RCC_APB1Periph_WWDG:   WWDG clock
+  *            @arg RCC_APB1Periph_SPI2:   SPI2 clock
+  *            @arg RCC_APB1Periph_SPI3:   SPI3 clock
+  *            @arg RCC_APB1Periph_USART2: USART2 clock
+  *            @arg RCC_APB1Periph_USART3: USART3 clock
+  *            @arg RCC_APB1Periph_UART4:  UART4 clock
+  *            @arg RCC_APB1Periph_UART5:  UART5 clock
+  *            @arg RCC_APB1Periph_I2C1:   I2C1 clock
+  *            @arg RCC_APB1Periph_I2C2:   I2C2 clock
+  *            @arg RCC_APB1Periph_I2C3:   I2C3 clock
+  *            @arg RCC_APB1Periph_CAN1:   CAN1 clock
+  *            @arg RCC_APB1Periph_CAN2:   CAN2 clock
+  *            @arg RCC_APB1Periph_PWR:    PWR clock
+  *            @arg RCC_APB1Periph_DAC:    DAC clock
+  * @param  NewState: new state of the specified peripheral reset.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    RCC->APB1RSTR |= RCC_APB1Periph;
+  }
+  else
+  {
+    RCC->APB1RSTR &= ~RCC_APB1Periph;
+  }
+}
+
+/**
+  * @brief  Forces or releases High Speed APB (APB2) peripheral reset.
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to reset.
+  *          This parameter can be any combination of the following values:
+  *            @arg RCC_APB2Periph_TIM1:   TIM1 clock
+  *            @arg RCC_APB2Periph_TIM8:   TIM8 clock
+  *            @arg RCC_APB2Periph_USART1: USART1 clock
+  *            @arg RCC_APB2Periph_USART6: USART6 clock
+  *            @arg RCC_APB2Periph_ADC1:   ADC1 clock
+  *            @arg RCC_APB2Periph_ADC2:   ADC2 clock
+  *            @arg RCC_APB2Periph_ADC3:   ADC3 clock
+  *            @arg RCC_APB2Periph_SDIO:   SDIO clock
+  *            @arg RCC_APB2Periph_SPI1:   SPI1 clock
+  *            @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
+  *            @arg RCC_APB2Periph_TIM9:   TIM9 clock
+  *            @arg RCC_APB2Periph_TIM10:  TIM10 clock
+  *            @arg RCC_APB2Periph_TIM11:  TIM11 clock
+  * @param  NewState: new state of the specified peripheral reset.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB2_RESET_PERIPH(RCC_APB2Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    RCC->APB2RSTR |= RCC_APB2Periph;
+  }
+  else
+  {
+    RCC->APB2RSTR &= ~RCC_APB2Periph;
+  }
+}
+
+/**
+  * @brief  Enables or disables the AHB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @param  RCC_AHBPeriph: specifies the AHB1 peripheral to gates its clock.
+  *          This parameter can be any combination of the following values:
+  *            @arg RCC_AHB1Periph_GPIOA:       GPIOA clock
+  *            @arg RCC_AHB1Periph_GPIOB:       GPIOB clock 
+  *            @arg RCC_AHB1Periph_GPIOC:       GPIOC clock
+  *            @arg RCC_AHB1Periph_GPIOD:       GPIOD clock
+  *            @arg RCC_AHB1Periph_GPIOE:       GPIOE clock
+  *            @arg RCC_AHB1Periph_GPIOF:       GPIOF clock
+  *            @arg RCC_AHB1Periph_GPIOG:       GPIOG clock
+  *            @arg RCC_AHB1Periph_GPIOG:       GPIOG clock
+  *            @arg RCC_AHB1Periph_GPIOI:       GPIOI clock
+  *            @arg RCC_AHB1Periph_CRC:         CRC clock
+  *            @arg RCC_AHB1Periph_BKPSRAM:     BKPSRAM interface clock
+  *            @arg RCC_AHB1Periph_DMA1:        DMA1 clock
+  *            @arg RCC_AHB1Periph_DMA2:        DMA2 clock
+  *            @arg RCC_AHB1Periph_ETH_MAC:     Ethernet MAC clock
+  *            @arg RCC_AHB1Periph_ETH_MAC_Tx:  Ethernet Transmission clock
+  *            @arg RCC_AHB1Periph_ETH_MAC_Rx:  Ethernet Reception clock
+  *            @arg RCC_AHB1Periph_ETH_MAC_PTP: Ethernet PTP clock
+  *            @arg RCC_AHB1Periph_OTG_HS:      USB OTG HS clock
+  *            @arg RCC_AHB1Periph_OTG_HS_ULPI: USB OTG HS ULPI clock
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_AHB1PeriphClockLPModeCmd(uint32_t RCC_AHB1Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_AHB1_LPMODE_PERIPH(RCC_AHB1Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    RCC->AHB1LPENR |= RCC_AHB1Periph;
+  }
+  else
+  {
+    RCC->AHB1LPENR &= ~RCC_AHB1Periph;
+  }
+}
+
+/**
+  * @brief  Enables or disables the AHB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *           power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @param  RCC_AHBPeriph: specifies the AHB2 peripheral to gates its clock.
+  *          This parameter can be any combination of the following values:
+  *            @arg RCC_AHB2Periph_DCMI:   DCMI clock
+  *            @arg RCC_AHB2Periph_CRYP:   CRYP clock
+  *            @arg RCC_AHB2Periph_HASH:   HASH clock
+  *            @arg RCC_AHB2Periph_RNG:    RNG clock
+  *            @arg RCC_AHB2Periph_OTG_FS: USB OTG FS clock  
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_AHB2PeriphClockLPModeCmd(uint32_t RCC_AHB2Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_AHB2_PERIPH(RCC_AHB2Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    RCC->AHB2LPENR |= RCC_AHB2Periph;
+  }
+  else
+  {
+    RCC->AHB2LPENR &= ~RCC_AHB2Periph;
+  }
+}
+
+/**
+  * @brief  Enables or disables the AHB3 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @param  RCC_AHBPeriph: specifies the AHB3 peripheral to gates its clock.
+  *          This parameter must be: RCC_AHB3Periph_FSMC
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_AHB3PeriphClockLPModeCmd(uint32_t RCC_AHB3Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_AHB3_PERIPH(RCC_AHB3Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    RCC->AHB3LPENR |= RCC_AHB3Periph;
+  }
+  else
+  {
+    RCC->AHB3LPENR &= ~RCC_AHB3Periph;
+  }
+}
+
+/**
+  * @brief  Enables or disables the APB1 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @param  RCC_APB1Periph: specifies the APB1 peripheral to gates its clock.
+  *          This parameter can be any combination of the following values:
+  *            @arg RCC_APB1Periph_TIM2:   TIM2 clock
+  *            @arg RCC_APB1Periph_TIM3:   TIM3 clock
+  *            @arg RCC_APB1Periph_TIM4:   TIM4 clock
+  *            @arg RCC_APB1Periph_TIM5:   TIM5 clock
+  *            @arg RCC_APB1Periph_TIM6:   TIM6 clock
+  *            @arg RCC_APB1Periph_TIM7:   TIM7 clock
+  *            @arg RCC_APB1Periph_TIM12:  TIM12 clock
+  *            @arg RCC_APB1Periph_TIM13:  TIM13 clock
+  *            @arg RCC_APB1Periph_TIM14:  TIM14 clock
+  *            @arg RCC_APB1Periph_WWDG:   WWDG clock
+  *            @arg RCC_APB1Periph_SPI2:   SPI2 clock
+  *            @arg RCC_APB1Periph_SPI3:   SPI3 clock
+  *            @arg RCC_APB1Periph_USART2: USART2 clock
+  *            @arg RCC_APB1Periph_USART3: USART3 clock
+  *            @arg RCC_APB1Periph_UART4:  UART4 clock
+  *            @arg RCC_APB1Periph_UART5:  UART5 clock
+  *            @arg RCC_APB1Periph_I2C1:   I2C1 clock
+  *            @arg RCC_APB1Periph_I2C2:   I2C2 clock
+  *            @arg RCC_APB1Periph_I2C3:   I2C3 clock
+  *            @arg RCC_APB1Periph_CAN1:   CAN1 clock
+  *            @arg RCC_APB1Periph_CAN2:   CAN2 clock
+  *            @arg RCC_APB1Periph_PWR:    PWR clock
+  *            @arg RCC_APB1Periph_DAC:    DAC clock
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB1PeriphClockLPModeCmd(uint32_t RCC_APB1Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB1_PERIPH(RCC_APB1Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    RCC->APB1LPENR |= RCC_APB1Periph;
+  }
+  else
+  {
+    RCC->APB1LPENR &= ~RCC_APB1Periph;
+  }
+}
+
+/**
+  * @brief  Enables or disables the APB2 peripheral clock during Low Power (Sleep) mode.
+  * @note   Peripheral clock gating in SLEEP mode can be used to further reduce
+  *         power consumption.
+  * @note   After wakeup from SLEEP mode, the peripheral clock is enabled again.
+  * @note   By default, all peripheral clocks are enabled during SLEEP mode.
+  * @param  RCC_APB2Periph: specifies the APB2 peripheral to gates its clock.
+  *          This parameter can be any combination of the following values:
+  *            @arg RCC_APB2Periph_TIM1:   TIM1 clock
+  *            @arg RCC_APB2Periph_TIM8:   TIM8 clock
+  *            @arg RCC_APB2Periph_USART1: USART1 clock
+  *            @arg RCC_APB2Periph_USART6: USART6 clock
+  *            @arg RCC_APB2Periph_ADC1:   ADC1 clock
+  *            @arg RCC_APB2Periph_ADC2:   ADC2 clock
+  *            @arg RCC_APB2Periph_ADC3:   ADC3 clock
+  *            @arg RCC_APB2Periph_SDIO:   SDIO clock
+  *            @arg RCC_APB2Periph_SPI1:   SPI1 clock
+  *            @arg RCC_APB2Periph_SYSCFG: SYSCFG clock
+  *            @arg RCC_APB2Periph_TIM9:   TIM9 clock
+  *            @arg RCC_APB2Periph_TIM10:  TIM10 clock
+  *            @arg RCC_APB2Periph_TIM11:  TIM11 clock
+  * @param  NewState: new state of the specified peripheral clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_APB2PeriphClockLPModeCmd(uint32_t RCC_APB2Periph, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_APB2_PERIPH(RCC_APB2Periph));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    RCC->APB2LPENR |= RCC_APB2Periph;
+  }
+  else
+  {
+    RCC->APB2LPENR &= ~RCC_APB2Periph;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RCC_Group4 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                   Interrupts and flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified RCC interrupts.
+  * @param  RCC_IT: specifies the RCC interrupt sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt  
+  * @param  NewState: new state of the specified RCC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_IT(RCC_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Perform Byte access to RCC_CIR[14:8] bits to enable the selected interrupts */
+    *(__IO uint8_t *) CIR_BYTE2_ADDRESS |= RCC_IT;
+  }
+  else
+  {
+    /* Perform Byte access to RCC_CIR[14:8] bits to disable the selected interrupts */
+    *(__IO uint8_t *) CIR_BYTE2_ADDRESS &= (uint8_t)~RCC_IT;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified RCC flag is set or not.
+  * @param  RCC_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_FLAG_HSIRDY: HSI oscillator clock ready
+  *            @arg RCC_FLAG_HSERDY: HSE oscillator clock ready
+  *            @arg RCC_FLAG_PLLRDY: main PLL clock ready
+  *            @arg RCC_FLAG_PLLI2SRDY: PLLI2S clock ready
+  *            @arg RCC_FLAG_LSERDY: LSE oscillator clock ready
+  *            @arg RCC_FLAG_LSIRDY: LSI oscillator clock ready
+  *            @arg RCC_FLAG_BORRST: POR/PDR or BOR reset
+  *            @arg RCC_FLAG_PINRST: Pin reset
+  *            @arg RCC_FLAG_PORRST: POR/PDR reset
+  *            @arg RCC_FLAG_SFTRST: Software reset
+  *            @arg RCC_FLAG_IWDGRST: Independent Watchdog reset
+  *            @arg RCC_FLAG_WWDGRST: Window Watchdog reset
+  *            @arg RCC_FLAG_LPWRRST: Low Power reset
+  * @retval The new state of RCC_FLAG (SET or RESET).
+  */
+FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG)
+{
+  uint32_t tmp = 0;
+  uint32_t statusreg = 0;
+  FlagStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_FLAG(RCC_FLAG));
+
+  /* Get the RCC register index */
+  tmp = RCC_FLAG >> 5;
+  if (tmp == 1)               /* The flag to check is in CR register */
+  {
+    statusreg = RCC->CR;
+  }
+  else if (tmp == 2)          /* The flag to check is in BDCR register */
+  {
+    statusreg = RCC->BDCR;
+  }
+  else                       /* The flag to check is in CSR register */
+  {
+    statusreg = RCC->CSR;
+  }
+
+  /* Get the flag position */
+  tmp = RCC_FLAG & FLAG_MASK;
+  if ((statusreg & ((uint32_t)1 << tmp)) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the flag status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RCC reset flags.
+  *         The reset flags are: RCC_FLAG_PINRST, RCC_FLAG_PORRST,  RCC_FLAG_SFTRST,
+  *         RCC_FLAG_IWDGRST, RCC_FLAG_WWDGRST, RCC_FLAG_LPWRRST
+  * @param  None
+  * @retval None
+  */
+void RCC_ClearFlag(void)
+{
+  /* Set RMVF bit to clear the reset flags */
+  RCC->CSR |= RCC_CSR_RMVF;
+}
+
+/**
+  * @brief  Checks whether the specified RCC interrupt has occurred or not.
+  * @param  RCC_IT: specifies the RCC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt  
+  *            @arg RCC_IT_CSS: Clock Security System interrupt
+  * @retval The new state of RCC_IT (SET or RESET).
+  */
+ITStatus RCC_GetITStatus(uint8_t RCC_IT)
+{
+  ITStatus bitstatus = RESET;
+
+  /* Check the parameters */
+  assert_param(IS_RCC_GET_IT(RCC_IT));
+
+  /* Check the status of the specified RCC interrupt */
+  if ((RCC->CIR & RCC_IT) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  /* Return the RCC_IT status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the RCC's interrupt pending bits.
+  * @param  RCC_IT: specifies the interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg RCC_IT_LSIRDY: LSI ready interrupt
+  *            @arg RCC_IT_LSERDY: LSE ready interrupt
+  *            @arg RCC_IT_HSIRDY: HSI ready interrupt
+  *            @arg RCC_IT_HSERDY: HSE ready interrupt
+  *            @arg RCC_IT_PLLRDY: main PLL ready interrupt
+  *            @arg RCC_IT_PLLI2SRDY: PLLI2S ready interrupt  
+  *            @arg RCC_IT_CSS: Clock Security System interrupt
+  * @retval None
+  */
+void RCC_ClearITPendingBit(uint8_t RCC_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_RCC_CLEAR_IT(RCC_IT));
+
+  /* Perform Byte access to RCC_CIR[23:16] bits to clear the selected interrupt
+     pending bits */
+  *(__IO uint8_t *) CIR_BYTE3_ADDRESS = RCC_IT;
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c
new file mode 100644
index 0000000000..7db1466e0b
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rng.c
@@ -0,0 +1,399 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_rng.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+    * @brief This file provides firmware functions to manage the following 
+  *          functionalities of the Random Number Generator (RNG) peripheral:           
+  *           - Initialization and Configuration 
+  *           - Get 32 bit Random number      
+  *           - Interrupts and flags management       
+  *         
+  *  @verbatim
+  *                               
+  *          ===================================================================      
+  *                                   How to use this driver
+  *          ===================================================================          
+  *          1. Enable The RNG controller clock using 
+  *            RCC_AHB2PeriphClockCmd(RCC_AHB2Periph_RNG, ENABLE) function.
+  *              
+  *          2. Activate the RNG peripheral using RNG_Cmd() function.
+  *          
+  *          3. Wait until the 32 bit Random number Generator contains a valid 
+  *            random data (using polling/interrupt mode). For more details, 
+  *            refer to "Interrupts and flags management functions" module 
+  *            description.
+  *           
+  *          4. Get the 32 bit Random number using RNG_GetRandomNumber() function
+  *          
+  *          5. To get another 32 bit Random number, go to step 3.       
+  *
+  *         
+  *              
+  *  @endverbatim
+  *         
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************  
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_rng.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup RNG 
+  * @brief RNG driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RNG_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup RNG_Group1 Initialization and Configuration functions
+ *  @brief    Initialization and Configuration functions 
+ *
+@verbatim    
+ ===============================================================================
+                      Initialization and Configuration functions
+ ===============================================================================  
+  This section provides functions allowing to 
+   - Initialize the RNG peripheral
+   - Enable or disable the RNG peripheral
+   
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the RNG peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void RNG_DeInit(void)
+{
+  /* Enable RNG reset state */
+  RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, ENABLE);
+
+  /* Release RNG from reset state */
+  RCC_AHB2PeriphResetCmd(RCC_AHB2Periph_RNG, DISABLE);
+}
+
+/**
+  * @brief  Enables or disables the RNG peripheral.
+  * @param  NewState: new state of the RNG peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RNG_Cmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the RNG */
+    RNG->CR |= RNG_CR_RNGEN;
+  }
+  else
+  {
+    /* Disable the RNG */
+    RNG->CR &= ~RNG_CR_RNGEN;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup RNG_Group2 Get 32 bit Random number function
+ *  @brief    Get 32 bit Random number function 
+ *
+
+@verbatim    
+ ===============================================================================
+                      Get 32 bit Random number function
+ ===============================================================================  
+  This section provides a function allowing to get the 32 bit Random number  
+  
+  @note  Before to call this function you have to wait till DRDY flag is set,
+         using RNG_GetFlagStatus(RNG_FLAG_DRDY) function. 
+   
+@endverbatim
+  * @{
+  */
+
+
+/**
+  * @brief  Returns a 32-bit random number.
+  *   
+  * @note   Before to call this function you have to wait till DRDY (data ready)
+  *         flag is set, using RNG_GetFlagStatus(RNG_FLAG_DRDY) function.
+  * @note   Each time the the Random number data is read (using RNG_GetRandomNumber()
+  *         function), the RNG_FLAG_DRDY flag is automatically cleared.
+  * @note   In the case of a seed error, the generation of random numbers is 
+  *         interrupted for as long as the SECS bit is '1'. If a number is 
+  *         available in the RNG_DR register, it must not be used because it may 
+  *         not have enough entropy. In this case, it is recommended to clear the 
+  *         SEIS bit(using RNG_ClearFlag(RNG_FLAG_SECS) function), then disable 
+  *         and enable the RNG peripheral (using RNG_Cmd() function) to 
+  *         reinitialize and restart the RNG.
+  * @note   In the case of a clock error, the RNG is no more able to generate 
+  *         random numbers because the PLL48CLK clock is not correct. User have 
+  *         to check that the clock controller is correctly configured to provide
+  *         the RNG clock and clear the CEIS bit (using RNG_ClearFlag(RNG_FLAG_CECS) 
+  *         function) . The clock error has no impact on the previously generated 
+  *         random numbers, and the RNG_DR register contents can be used.
+  *         
+  * @param  None
+  * @retval 32-bit random number.
+  */
+uint32_t RNG_GetRandomNumber(void)
+{
+  /* Return the 32 bit random number from the DR register */
+  return RNG->DR;
+}
+
+
+/**
+  * @}
+  */
+
+/** @defgroup RNG_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+ *
+@verbatim   
+ ===============================================================================
+                   Interrupts and flags management functions
+ ===============================================================================  
+
+  This section provides functions allowing to configure the RNG Interrupts and 
+  to get the status and clear flags and Interrupts pending bits.
+  
+  The RNG provides 3 Interrupts sources and 3 Flags:
+  
+  Flags :
+  ---------- 
+     1. RNG_FLAG_DRDY :  In the case of the RNG_DR register contains valid 
+                         random data. it is cleared by reading the valid data 
+                         (using RNG_GetRandomNumber() function).
+
+     2. RNG_FLAG_CECS : In the case of a seed error detection. 
+      
+     3. RNG_FLAG_SECS : In the case of a clock error detection.
+              
+
+  Interrupts :
+  ------------
+   if enabled, an RNG interrupt is pending :
+    
+   1.  In the case of the RNG_DR register contains valid random data. 
+       This interrupt source is cleared once the RNG_DR register has been read 
+       (using RNG_GetRandomNumber() function) until a new valid value is 
+       computed. 
+   
+   or 
+   2. In the case of a seed error : One of the following faulty sequences has 
+      been detected:
+      - More than 64 consecutive bits at the same value (0 or 1)
+      - More than 32 consecutive alternance of 0 and 1 (0101010101...01)
+      This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_SEI)
+      function.
+   
+   or
+   3. In the case of a clock error : the PLL48CLK (RNG peripheral clock source) 
+      was not correctly detected (fPLL48CLK< fHCLK/16).
+      This interrupt source is cleared using RNG_ClearITPendingBit(RNG_IT_CEI)
+      function.
+      @note In this case, User have to check that the clock controller is 
+            correctly configured to provide the RNG clock. 
+
+  Managing the RNG controller events :
+  ------------------------------------ 
+  The user should identify which mode will be used in his application to manage 
+  the RNG controller events: Polling mode or Interrupt mode.
+  
+  1.  In the Polling Mode it is advised to use the following functions:
+      - RNG_GetFlagStatus() : to check if flags events occur. 
+      - RNG_ClearFlag()     : to clear the flags events.
+  
+  @note RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag(). it is cleared only 
+        by reading the Random number data.      
+  
+  2.  In the Interrupt Mode it is advised to use the following functions:
+      - RNG_ITConfig()       : to enable or disable the interrupt source.
+      - RNG_GetITStatus()    : to check if Interrupt occurs.
+      - RNG_ClearITPendingBit() : to clear the Interrupt pending Bit 
+                                (corresponding Flag). 
+  
+
+@endverbatim
+  * @{
+  */ 
+
+/**
+  * @brief  Enables or disables the RNG interrupt.
+  * @note   The RNG provides 3 interrupt sources,
+  *           - Computed data is ready event (DRDY), and           
+  *           - Seed error Interrupt (SEI) and 
+  *           - Clock error Interrupt (CEI), 
+  *         all these interrupts sources are enabled by setting the IE bit in 
+  *         CR register. However, each interrupt have its specific status bit
+  *         (see RNG_GetITStatus() function) and clear bit except the DRDY event
+  *         (see RNG_ClearITPendingBit() function).
+  * @param  NewState: new state of the RNG interrupt.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RNG_ITConfig(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the RNG interrupt */
+    RNG->CR |= RNG_CR_IE;
+  }
+  else
+  {
+    /* Disable the RNG interrupt */
+    RNG->CR &= ~RNG_CR_IE;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified RNG flag is set or not.
+  * @param  RNG_FLAG: specifies the RNG flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg RNG_FLAG_DRDY: Data Ready flag.
+  *            @arg RNG_FLAG_CECS: Clock Error Current flag.
+  *            @arg RNG_FLAG_SECS: Seed Error Current flag.
+  * @retval The new state of RNG_FLAG (SET or RESET).
+  */
+FlagStatus RNG_GetFlagStatus(uint8_t RNG_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_RNG_GET_FLAG(RNG_FLAG));
+
+  /* Check the status of the specified RNG flag */
+  if ((RNG->SR & RNG_FLAG) != (uint8_t)RESET)
+  {
+    /* RNG_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* RNG_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the RNG_FLAG status */
+  return  bitstatus;
+}
+
+
+/**
+  * @brief  Clears the RNG flags.
+  * @param  RNG_FLAG: specifies the flag to clear. 
+  *          This parameter can be any combination of the following values:
+  *            @arg RNG_FLAG_CECS: Clock Error Current flag.
+  *            @arg RNG_FLAG_SECS: Seed Error Current flag.
+  * @note   RNG_FLAG_DRDY can not be cleared by RNG_ClearFlag() function. 
+  *         This flag is cleared only by reading the Random number data (using 
+  *         RNG_GetRandomNumber() function).                           
+  * @retval None
+  */
+void RNG_ClearFlag(uint8_t RNG_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_RNG_CLEAR_FLAG(RNG_FLAG));
+  /* Clear the selected RNG flags */
+  RNG->SR = ~(uint32_t)(((uint32_t)RNG_FLAG) << 4);
+}
+
+/**
+  * @brief  Checks whether the specified RNG interrupt has occurred or not.
+  * @param  RNG_IT: specifies the RNG interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg RNG_IT_CEI: Clock Error Interrupt.
+  *            @arg RNG_IT_SEI: Seed Error Interrupt.                   
+  * @retval The new state of RNG_IT (SET or RESET).
+  */
+ITStatus RNG_GetITStatus(uint8_t RNG_IT)
+{
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_RNG_GET_IT(RNG_IT));
+
+  /* Check the status of the specified RNG interrupt */
+  if ((RNG->SR & RNG_IT) != (uint8_t)RESET)
+  {
+    /* RNG_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* RNG_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the RNG_IT status */
+  return bitstatus;
+}
+
+
+/**
+  * @brief  Clears the RNG interrupt pending bit(s).
+  * @param  RNG_IT: specifies the RNG interrupt pending bit(s) to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg RNG_IT_CEI: Clock Error Interrupt.
+  *            @arg RNG_IT_SEI: Seed Error Interrupt.
+  * @retval None
+  */
+void RNG_ClearITPendingBit(uint8_t RNG_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_RNG_IT(RNG_IT));
+
+  /* Clear the selected RNG interrupt pending bit */
+  RNG->SR = (uint8_t)~RNG_IT;
+}
+/**
+  * @}
+  */ 
+  
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+
+/**
+  * @}
+  */ 
+
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c
new file mode 100644
index 0000000000..1bf5dcbbec
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_rtc.c
@@ -0,0 +1,2733 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_rtc.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Real-Time Clock (RTC) peripheral:
+  *           - Initialization
+  *           - Calendar (Time and Date) configuration
+  *           - Alarms (Alarm A and Alarm B) configuration
+  *           - WakeUp Timer configuration
+  *           - Daylight Saving configuration
+  *           - Output pin Configuration
+  *           - Coarse digital Calibration configuration
+  *           - Smooth digital Calibration configuration
+  *           - TimeStamp configuration
+  *           - Tampers configuration
+  *           - Backup Data Registers configuration
+  *           - Shift control synchronisation    
+  *           - RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration
+  *           - Interrupts and flags management
+  *
+  *  @verbatim
+  *
+  *          ===================================================================
+  *                               Backup Domain Operating Condition
+  *          ===================================================================
+  *          The real-time clock (RTC), the RTC backup registers, and the backup 
+  *          SRAM (BKP SRAM) can be powered from the VBAT voltage when the main 
+  *          VDD supply is powered off.
+  *          To retain the content of the RTC backup registers, backup SRAM, 
+  *          and supply the RTC when VDD is turned off, VBAT pin can be connected 
+  *          to an optional standby voltage supplied by a battery or by another 
+  *          source.
+  *
+  *          To allow the RTC to operate even when the main digital supply (VDD) 
+  *          is turned off, the VBAT pin powers the following blocks:
+  *            1 - The RTC
+  *            2 - The LSE oscillator
+  *            3 - The backup SRAM when the low power backup regulator is enabled
+  *            4 - PC13 to PC15 I/Os, plus PI8 I/O (when available)
+  *
+  *          When the backup domain is supplied by VDD (analog switch connected 
+  *          to VDD), the following functions are available:
+  *            1 - PC14 and PC15 can be used as either GPIO or LSE pins
+  *            2 - PC13 can be used as a GPIO or as the RTC_AF1 pin
+  *            3 - PI8 can be used as a GPIO or as the RTC_AF2 pin
+  *
+  *          When the backup domain is supplied by VBAT (analog switch connected 
+  *          to VBAT because VDD is not present), the following functions are available:
+  *            1 - PC14 and PC15 can be used as LSE pins only
+  *            2 - PC13 can be used as the RTC_AF1 pin 
+  *            3 - PI8 can be used as the RTC_AF2 pin
+  *
+  *          ===================================================================
+  *                                    Backup Domain Reset
+  *          ===================================================================
+  *          The backup domain reset sets all RTC registers and the RCC_BDCR 
+  *          register to their reset values. The BKPSRAM is not affected by this
+  *          reset. The only way of resetting the BKPSRAM is through the Flash 
+  *          interface by requesting a protection level change from 1 to 0.
+  *          A backup domain reset is generated when one of the following events
+  *          occurs:
+  *            1 - Software reset, triggered by setting the BDRST bit in the 
+  *                RCC Backup domain control register (RCC_BDCR). You can use the
+  *                RCC_BackupResetCmd().
+  *            2 - VDD or VBAT power on, if both supplies have previously been
+  *                powered off.
+  *
+  *          ===================================================================
+  *                                   Backup Domain Access
+  *          ===================================================================
+  *          After reset, the backup domain (RTC registers, RTC backup data 
+  *          registers and backup SRAM) is protected against possible unwanted 
+  *          write accesses. 
+  *          To enable access to the RTC Domain and RTC registers, proceed as follows:
+  *            - Enable the Power Controller (PWR) APB1 interface clock using the
+  *              RCC_APB1PeriphClockCmd() function.
+  *            - Enable access to RTC domain using the PWR_BackupAccessCmd() function.
+  *            - Select the RTC clock source using the RCC_RTCCLKConfig() function.
+  *            - Enable RTC Clock using the RCC_RTCCLKCmd() function.
+  *
+  *          ===================================================================
+  *                                   RTC Driver: how to use it
+  *          ===================================================================
+  *            - Enable the RTC domain access (see description in the section above)
+  *            - Configure the RTC Prescaler (Asynchronous and Synchronous) and
+  *              RTC hour format using the RTC_Init() function.
+  *
+  *          Time and Date configuration
+  *          ===========================
+  *            - To configure the RTC Calendar (Time and Date) use the RTC_SetTime()
+  *              and RTC_SetDate() functions.
+  *            - To read the RTC Calendar, use the RTC_GetTime() and RTC_GetDate()
+  *              functions.
+  *            - Use the RTC_DayLightSavingConfig() function to add or sub one
+  *              hour to the RTC Calendar.    
+  *
+  *          Alarm configuration
+  *          ===================
+  *            - To configure the RTC Alarm use the RTC_SetAlarm() function.
+  *            - Enable the selected RTC Alarm using the RTC_AlarmCmd() function
+  *            - To read the RTC Alarm, use the RTC_GetAlarm() function.
+  *            - To read the RTC alarm SubSecond, use the RTC_GetAlarmSubSecond() function.
+  *
+  *          RTC Wakeup configuration
+  *          ========================
+  *            - Configure the RTC Wakeup Clock source use the RTC_WakeUpClockConfig()
+  *              function.
+  *            - Configure the RTC WakeUp Counter using the RTC_SetWakeUpCounter() 
+  *              function  
+  *            - Enable the RTC WakeUp using the RTC_WakeUpCmd() function  
+  *            - To read the RTC WakeUp Counter register, use the RTC_GetWakeUpCounter() 
+  *              function.
+  *
+  *          Outputs configuration
+  *          =====================
+  *          The RTC has 2 different outputs:
+  *            - AFO_ALARM: this output is used to manage the RTC Alarm A, Alarm B
+  *              and WaKeUp signals.          
+  *              To output the selected RTC signal on RTC_AF1 pin, use the 
+  *              RTC_OutputConfig() function.                
+  *            - AFO_CALIB: this output is 512Hz signal or 1Hz .  
+  *              To output the RTC Clock on RTC_AF1 pin, use the RTC_CalibOutputCmd()
+  *              function.
+  *
+  *          Smooth digital Calibration configuration
+  *          =================================    
+  *            - Configure the RTC Original Digital Calibration Value and the corresponding
+  *              calibration cycle period (32s,16s and 8s) using the RTC_SmoothCalibConfig() 
+  *              function.
+  *
+  *          Coarse digital Calibration configuration
+  *          =================================
+  *            - Configure the RTC Coarse Calibration Value and the corresponding
+  *              sign using the RTC_CoarseCalibConfig() function.
+  *            - Enable the RTC Coarse Calibration using the RTC_CoarseCalibCmd() 
+  *              function  
+  *
+  *          TimeStamp configuration
+  *          =======================
+  *            - Configure the RTC_AF1 trigger and enables the RTC TimeStamp 
+  *              using the RTC_TimeStampCmd() function.
+  *            - To read the RTC TimeStamp Time and Date register, use the 
+  *              RTC_GetTimeStamp() function.
+  *            - To read the RTC TimeStamp SubSecond register, use the 
+  *              RTC_GetTimeStampSubSecond() function.
+  *            - The TAMPER1 alternate function can be mapped either to RTC_AF1(PC13)
+  *              or RTC_AF2 (PI8) depending on the value of TAMP1INSEL bit in 
+  *              RTC_TAFCR register. You can use the  RTC_TamperPinSelection()
+  *              function to select the corresponding pin.     
+  *
+  *          Tamper configuration
+  *          ====================
+  *            - Enable the RTC Tamper using the RTC_TamperCmd() function.
+  *             - Configure the Tamper filter count using RTC_TamperFilterConfig()
+  *              function. 
+  *            - Configure the RTC Tamper trigger Edge or Level according to the Tamper 
+  *              filter (if equal to 0 Edge else Level) value using the RTC_TamperConfig() function.
+  *            - Configure the Tamper sampling frequency using RTC_TamperSamplingFreqConfig()
+  *              function.
+  *            - Configure the Tamper precharge or discharge duration using 
+  *              RTC_TamperPinsPrechargeDuration() function.
+  *            - Enable the Tamper Pull-UP using RTC_TamperPullUpDisableCmd() function.
+  *            - Enable the Time stamp on Tamper detection event using  
+  *              RTC_TSOnTamperDetecCmd() function.
+  *            - The TIMESTAMP alternate function can be mapped to either RTC_AF1 
+  *              or RTC_AF2 depending on the value of the TSINSEL bit in the 
+  *              RTC_TAFCR register. You can use the  RTC_TimeStampPinSelection()
+  *              function to select the corresponding pin. 
+  *
+  *          Backup Data Registers configuration
+  *          ===================================
+  *            - To write to the RTC Backup Data registers, use the RTC_WriteBackupRegister()
+  *              function.  
+  *            - To read the RTC Backup Data registers, use the RTC_ReadBackupRegister()
+  *              function.
+  * 
+  *          ===================================================================
+  *                                  RTC and low power modes
+  *          ===================================================================
+  *           The MCU can be woken up from a low power mode by an RTC alternate 
+  *           function.
+  *           The RTC alternate functions are the RTC alarms (Alarm A and Alarm B), 
+  *           RTC wakeup, RTC tamper event detection and RTC time stamp event detection.
+  *           These RTC alternate functions can wake up the system from the Stop 
+  *           and Standby lowpower modes.
+  *           The system can also wake up from low power modes without depending 
+  *           on an external interrupt (Auto-wakeup mode), by using the RTC alarm 
+  *           or the RTC wakeup events.
+  *           The RTC provides a programmable time base for waking up from the 
+  *           Stop or Standby mode at regular intervals.
+  *           Wakeup from STOP and Standby modes is possible only when the RTC 
+  *           clock source is LSE or LSI.
+  *
+  *          ===================================================================
+  *                            Selection of RTC_AF1 alternate functions
+  *          ===================================================================
+  *          The RTC_AF1 pin (PC13) can be used for the following purposes:
+  *            - AFO_ALARM output
+  *            - AFO_CALIB output
+  *            - AFI_TAMPER
+  *            - AFI_TIMESTAMP
+  *
+  * +-------------------------------------------------------------------------------------------------------------+
+  * |     Pin         |AFO_ALARM |AFO_CALIB |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL |   TSINSEL    |ALARMOUTTYPE  |
+  * |  configuration  | ENABLED  | ENABLED  |  ENABLED  |   ENABLED    |TAMPER1 pin |TIMESTAMP pin |  AFO_ALARM   |
+  * |  and function   |          |          |           |              | selection  |  selection   |Configuration |
+  * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
+  * |   Alarm out     |          |          |           |              |    Don't   |     Don't    |              |
+  * |   output OD     |     1    |Don't care|Don't care | Don't care   |    care    |     care     |      0       |
+  * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
+  * |   Alarm out     |          |          |           |              |    Don't   |     Don't    |              |
+  * |   output PP     |     1    |Don't care|Don't care | Don't care   |    care    |     care     |      1       |
+  * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
+  * | Calibration out |          |          |           |              |    Don't   |     Don't    |              |
+  * |   output PP     |     0    |    1     |Don't care | Don't care   |    care    |     care     |  Don't care  |
+  * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
+  * |  TAMPER input   |          |          |           |              |            |     Don't    |              |
+  * |   floating      |     0    |    0     |     1     |      0       |      0     |     care     |  Don't care  |
+  * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
+  * |  TIMESTAMP and  |          |          |           |              |            |              |              |
+  * |  TAMPER input   |     0    |    0     |     1     |      1       |      0     |      0       |  Don't care  |
+  * |   floating      |          |          |           |              |            |              |              |
+  * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
+  * | TIMESTAMP input |          |          |           |              |    Don't   |              |              |
+  * |    floating     |     0    |    0     |     0     |      1       |    care    |      0       |  Don't care  |
+  * |-----------------|----------|----------|-----------|--------------|------------|--------------|--------------|
+  * |  Standard GPIO  |     0    |    0     |     0     |      0       | Don't care |  Don't care  |  Don't care  |
+  * +-------------------------------------------------------------------------------------------------------------+
+  *
+  *
+  *          ===================================================================
+  *                            Selection of RTC_AF2 alternate functions
+  *          ===================================================================
+  *          The RTC_AF2 pin (PI8) can be used for the following purposes:
+  *            - AFI_TAMPER
+  *            - AFI_TIMESTAMP
+  *
+  * +---------------------------------------------------------------------------------------+
+  * |     Pin         |AFI_TAMPER |AFI_TIMESTAMP | TAMP1INSEL |   TSINSEL    |ALARMOUTTYPE  |
+  * |  configuration  |  ENABLED  |   ENABLED    |TAMPER1 pin |TIMESTAMP pin |  AFO_ALARM   |
+  * |  and function   |           |              | selection  |  selection   |Configuration |
+  * |-----------------|-----------|--------------|------------|--------------|--------------|
+  * |  TAMPER input   |           |              |            |     Don't    |              |
+  * |   floating      |     1     |      0       |      1     |     care     |  Don't care  |
+  * |-----------------|-----------|--------------|------------|--------------|--------------|
+  * |  TIMESTAMP and  |           |              |            |              |              |
+  * |  TAMPER input   |     1     |      1       |      1     |      1       |  Don't care  |
+  * |   floating      |           |              |            |              |              |
+  * |-----------------|-----------|--------------|------------|--------------|--------------|
+  * | TIMESTAMP input |           |              |    Don't   |              |              |
+  * |    floating     |     0     |      1       |    care    |      1       |  Don't care  |
+  * |-----------------|-----------|--------------|------------|--------------|--------------|
+  * |  Standard GPIO  |     0     |      0       | Don't care |  Don't care  |  Don't care  |
+  * +---------------------------------------------------------------------------------------+
+  * 
+  *
+  *  @endverbatim
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_rtc.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup RTC 
+  * @brief RTC driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* Masks Definition */
+#define RTC_TR_RESERVED_MASK    ((uint32_t)0x007F7F7F)
+#define RTC_DR_RESERVED_MASK    ((uint32_t)0x00FFFF3F) 
+#define RTC_INIT_MASK           ((uint32_t)0xFFFFFFFF)  
+#define RTC_RSF_MASK            ((uint32_t)0xFFFFFF5F)
+#define RTC_FLAGS_MASK          ((uint32_t)(RTC_FLAG_TSOVF | RTC_FLAG_TSF | RTC_FLAG_WUTF | \
+                                            RTC_FLAG_ALRBF | RTC_FLAG_ALRAF | RTC_FLAG_INITF | \
+                                            RTC_FLAG_RSF | RTC_FLAG_INITS | RTC_FLAG_WUTWF | \
+                                            RTC_FLAG_ALRBWF | RTC_FLAG_ALRAWF | RTC_FLAG_TAMP1F ))
+
+#define INITMODE_TIMEOUT         ((uint32_t) 0x00010000)
+#define SYNCHRO_TIMEOUT          ((uint32_t) 0x00020000)
+#define RECALPF_TIMEOUT          ((uint32_t) 0x00020000)
+#define SHPF_TIMEOUT             ((uint32_t) 0x00001000)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static uint8_t RTC_ByteToBcd2(uint8_t Value);
+static uint8_t RTC_Bcd2ToByte(uint8_t Value);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup RTC_Private_Functions
+  * @{
+  */ 
+
+/** @defgroup RTC_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                 Initialization and Configuration functions
+ ===============================================================================
+
+  This section provide functions allowing to initialize and configure the RTC
+  Prescaler (Synchronous and Asynchronous), RTC Hour format, disable RTC registers
+  Write protection, enter and exit the RTC initialization mode, RTC registers
+  synchronization check and reference clock detection enable.
+  
+  1. The RTC Prescaler is programmed to generate the RTC 1Hz time base. It is
+     split into 2 programmable prescalers to minimize power consumption.
+     - A 7-bit asynchronous prescaler and A 13-bit synchronous prescaler.
+     - When both prescalers are used, it is recommended to configure the asynchronous
+       prescaler to a high value to minimize consumption.
+
+  2. All RTC registers are Write protected. Writing to the RTC registers
+     is enabled by writing a key into the Write Protection register, RTC_WPR.
+
+  3. To Configure the RTC Calendar, user application should enter initialization
+     mode. In this mode, the calendar counter is stopped and its value can be 
+     updated. When the initialization sequence is complete, the calendar restarts 
+     counting after 4 RTCCLK cycles.
+
+  4. To read the calendar through the shadow registers after Calendar initialization,
+     calendar update or after wakeup from low power modes the software must first 
+     clear the RSF flag. The software must then wait until it is set again before 
+     reading the calendar, which means that the calendar registers have been 
+     correctly copied into the RTC_TR and RTC_DR shadow registers.
+     The RTC_WaitForSynchro() function implements the above software sequence 
+     (RSF clear and RSF check).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the RTC registers to their default reset values.
+  * @note   This function doesn't reset the RTC Clock source and RTC Backup Data
+  *         registers.       
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are deinitialized
+  *          - ERROR: RTC registers are not deinitialized
+  */
+ErrorStatus RTC_DeInit(void)
+{
+  __IO uint32_t wutcounter = 0x00;
+  uint32_t wutwfstatus = 0x00;
+  ErrorStatus status = ERROR;
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  }  
+  else
+  {
+    /* Reset TR, DR and CR registers */
+    RTC->TR = (uint32_t)0x00000000;
+    RTC->DR = (uint32_t)0x00002101;
+    /* Reset All CR bits except CR[2:0] */
+    RTC->CR &= (uint32_t)0x00000007;
+  
+    /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+    do
+    {
+      wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
+      wutcounter++;  
+    } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+    
+    if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      /* Reset all RTC CR register bits */
+      RTC->CR &= (uint32_t)0x00000000;
+      RTC->WUTR = (uint32_t)0x0000FFFF;
+      RTC->PRER = (uint32_t)0x007F00FF;
+      RTC->CALIBR = (uint32_t)0x00000000;
+      RTC->ALRMAR = (uint32_t)0x00000000;        
+      RTC->ALRMBR = (uint32_t)0x00000000;
+      
+      /* Reset ISR register and exit initialization mode */
+      RTC->ISR = (uint32_t)0x00000000;
+      
+      /* Reset Tamper and alternate functions configuration register */
+      RTC->TAFCR = 0x00000000;
+  
+      if(RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;      
+      }
+    }
+  }
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;  
+  
+  return status;
+}
+
+/**
+  * @brief  Initializes the RTC registers according to the specified parameters 
+  *         in RTC_InitStruct.
+  * @param  RTC_InitStruct: pointer to a RTC_InitTypeDef structure that contains 
+  *         the configuration information for the RTC peripheral.
+  * @note   The RTC Prescaler register is write protected and can be written in 
+  *         initialization mode only.  
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are initialized
+  *          - ERROR: RTC registers are not initialized  
+  */
+ErrorStatus RTC_Init(RTC_InitTypeDef* RTC_InitStruct)
+{
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_HOUR_FORMAT(RTC_InitStruct->RTC_HourFormat));
+  assert_param(IS_RTC_ASYNCH_PREDIV(RTC_InitStruct->RTC_AsynchPrediv));
+  assert_param(IS_RTC_SYNCH_PREDIV(RTC_InitStruct->RTC_SynchPrediv));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {
+    /* Clear RTC CR FMT Bit */
+    RTC->CR &= ((uint32_t)~(RTC_CR_FMT));
+    /* Set RTC_CR register */
+    RTC->CR |=  ((uint32_t)(RTC_InitStruct->RTC_HourFormat));
+  
+    /* Configure the RTC PRER */
+    RTC->PRER = (uint32_t)(RTC_InitStruct->RTC_SynchPrediv);
+    RTC->PRER |= (uint32_t)(RTC_InitStruct->RTC_AsynchPrediv << 16);
+
+    /* Exit Initialization mode */
+    RTC_ExitInitMode();
+
+    status = SUCCESS;    
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+  
+  return status;
+}
+
+/**
+  * @brief  Fills each RTC_InitStruct member with its default value.
+  * @param  RTC_InitStruct: pointer to a RTC_InitTypeDef structure which will be 
+  *         initialized.
+  * @retval None
+  */
+void RTC_StructInit(RTC_InitTypeDef* RTC_InitStruct)
+{
+  /* Initialize the RTC_HourFormat member */
+  RTC_InitStruct->RTC_HourFormat = RTC_HourFormat_24;
+    
+  /* Initialize the RTC_AsynchPrediv member */
+  RTC_InitStruct->RTC_AsynchPrediv = (uint32_t)0x7F;
+
+  /* Initialize the RTC_SynchPrediv member */
+  RTC_InitStruct->RTC_SynchPrediv = (uint32_t)0xFF; 
+}
+
+/**
+  * @brief  Enables or disables the RTC registers write protection.
+  * @note   All the RTC registers are write protected except for RTC_ISR[13:8], 
+  *         RTC_TAFCR and RTC_BKPxR.
+  * @note   Writing a wrong key reactivates the write protection.
+  * @note   The protection mechanism is not affected by system reset.  
+  * @param  NewState: new state of the write protection.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_WriteProtectionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+    
+  if (NewState != DISABLE)
+  {
+    /* Enable the write protection for RTC registers */
+    RTC->WPR = 0xFF;   
+  }
+  else
+  {
+    /* Disable the write protection for RTC registers */
+    RTC->WPR = 0xCA;
+    RTC->WPR = 0x53;    
+  }
+}
+
+/**
+  * @brief  Enters the RTC Initialization mode.
+  * @note   The RTC Initialization mode is write protected, use the 
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function.    
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC is in Init mode
+  *          - ERROR: RTC is not in Init mode  
+  */
+ErrorStatus RTC_EnterInitMode(void)
+{
+  __IO uint32_t initcounter = 0x00;
+  ErrorStatus status = ERROR;
+  uint32_t initstatus = 0x00;
+     
+  /* Check if the Initialization mode is set */
+  if ((RTC->ISR & RTC_ISR_INITF) == (uint32_t)RESET)
+  {
+    /* Set the Initialization mode */
+    RTC->ISR = (uint32_t)RTC_INIT_MASK;
+    
+    /* Wait till RTC is in INIT state and if Time out is reached exit */
+    do
+    {
+      initstatus = RTC->ISR & RTC_ISR_INITF;
+      initcounter++;  
+    } while((initcounter != INITMODE_TIMEOUT) && (initstatus == 0x00));
+    
+    if ((RTC->ISR & RTC_ISR_INITF) != RESET)
+    {
+      status = SUCCESS;
+    }
+    else
+    {
+      status = ERROR;
+    }        
+  }
+  else
+  {
+    status = SUCCESS;  
+  } 
+    
+  return (status);  
+}
+
+/**
+  * @brief  Exits the RTC Initialization mode.
+  * @note   When the initialization sequence is complete, the calendar restarts 
+  *         counting after 4 RTCCLK cycles.  
+  * @note   The RTC Initialization mode is write protected, use the 
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function.      
+  * @param  None
+  * @retval None
+  */
+void RTC_ExitInitMode(void)
+{ 
+  /* Exit Initialization mode */
+  RTC->ISR &= (uint32_t)~RTC_ISR_INIT;  
+}
+
+/**
+  * @brief  Waits until the RTC Time and Date registers (RTC_TR and RTC_DR) are 
+  *         synchronized with RTC APB clock.
+  * @note   The RTC Resynchronization mode is write protected, use the 
+  *         RTC_WriteProtectionCmd(DISABLE) before calling this function. 
+  * @note   To read the calendar through the shadow registers after Calendar 
+  *         initialization, calendar update or after wakeup from low power modes 
+  *         the software must first clear the RSF flag. 
+  *         The software must then wait until it is set again before reading 
+  *         the calendar, which means that the calendar registers have been 
+  *         correctly copied into the RTC_TR and RTC_DR shadow registers.   
+  * @param  None
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC registers are synchronised
+  *          - ERROR: RTC registers are not synchronised
+  */
+ErrorStatus RTC_WaitForSynchro(void)
+{
+  __IO uint32_t synchrocounter = 0;
+  ErrorStatus status = ERROR;
+  uint32_t synchrostatus = 0x00;
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+    
+  /* Clear RSF flag */
+  RTC->ISR &= (uint32_t)RTC_RSF_MASK;
+    
+  /* Wait the registers to be synchronised */
+  do
+  {
+    synchrostatus = RTC->ISR & RTC_ISR_RSF;
+    synchrocounter++;  
+  } while((synchrocounter != SYNCHRO_TIMEOUT) && (synchrostatus == 0x00));
+    
+  if ((RTC->ISR & RTC_ISR_RSF) != RESET)
+  {
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }        
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+    
+  return (status); 
+}
+
+/**
+  * @brief  Enables or disables the RTC reference clock detection.
+  * @param  NewState: new state of the RTC reference clock.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC reference clock detection is enabled
+  *          - ERROR: RTC reference clock detection is disabled  
+  */
+ErrorStatus RTC_RefClockCmd(FunctionalState NewState)
+{ 
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+    
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {  
+    if (NewState != DISABLE)
+    {
+      /* Enable the RTC reference clock detection */
+      RTC->CR |= RTC_CR_REFCKON;   
+    }
+    else
+    {
+      /* Disable the RTC reference clock detection */
+      RTC->CR &= ~RTC_CR_REFCKON;    
+    }
+    /* Exit Initialization mode */
+    RTC_ExitInitMode();
+    
+    status = SUCCESS;
+  }
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;  
+  
+  return status; 
+}
+
+/**
+  * @brief  Enables or Disables the Bypass Shadow feature.
+  * @note   When the Bypass Shadow is enabled the calendar value are taken 
+  *         directly from the Calendar counter.
+  * @param  NewState: new state of the Bypass Shadow feature.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+*/
+void RTC_BypassShadowCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  if (NewState != DISABLE)
+  {
+    /* Set the BYPSHAD bit */
+    RTC->CR |= (uint8_t)RTC_CR_BYPSHAD;
+  }
+  else
+  {
+    /* Reset the BYPSHAD bit */
+    RTC->CR &= (uint8_t)~RTC_CR_BYPSHAD;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group2 Time and Date configuration functions
+ *  @brief   Time and Date configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                   Time and Date configuration functions
+ ===============================================================================  
+
+  This section provide functions allowing to program and read the RTC Calendar
+  (Time and Date).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set the RTC current time.
+  * @param  RTC_Format: specifies the format of the entered parameters.
+  *          This parameter can be  one of the following values:
+  *            @arg RTC_Format_BIN:  Binary data format 
+  *            @arg RTC_Format_BCD:  BCD data format
+  * @param  RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that contains 
+  *                        the time configuration information for the RTC.     
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Time register is configured
+  *          - ERROR: RTC Time register is not configured
+  */
+ErrorStatus RTC_SetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  uint32_t tmpreg = 0;
+  ErrorStatus status = ERROR;
+    
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      assert_param(IS_RTC_HOUR12(RTC_TimeStruct->RTC_Hours));
+      assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12));
+    } 
+    else
+    {
+      RTC_TimeStruct->RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_TimeStruct->RTC_Hours));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_TimeStruct->RTC_Minutes));
+    assert_param(IS_RTC_SECONDS(RTC_TimeStruct->RTC_Seconds));
+  }
+  else
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
+      assert_param(IS_RTC_HOUR12(tmpreg));
+      assert_param(IS_RTC_H12(RTC_TimeStruct->RTC_H12)); 
+    } 
+    else
+    {
+      RTC_TimeStruct->RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours)));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes)));
+    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds)));
+  }
+  
+  /* Check the input parameters format */
+  if (RTC_Format != RTC_Format_BIN)
+  {
+    tmpreg = (((uint32_t)(RTC_TimeStruct->RTC_Hours) << 16) | \
+             ((uint32_t)(RTC_TimeStruct->RTC_Minutes) << 8) | \
+             ((uint32_t)RTC_TimeStruct->RTC_Seconds) | \
+             ((uint32_t)(RTC_TimeStruct->RTC_H12) << 16)); 
+  }  
+  else
+  {
+    tmpreg = (uint32_t)(((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Hours) << 16) | \
+                   ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Minutes) << 8) | \
+                   ((uint32_t)RTC_ByteToBcd2(RTC_TimeStruct->RTC_Seconds)) | \
+                   (((uint32_t)RTC_TimeStruct->RTC_H12) << 16));
+  }  
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {
+    /* Set the RTC_TR register */
+    RTC->TR = (uint32_t)(tmpreg & RTC_TR_RESERVED_MASK);
+
+    /* Exit Initialization mode */
+    RTC_ExitInitMode(); 
+
+    if(RTC_WaitForSynchro() == ERROR)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+    
+  return status;
+}
+
+/**
+  * @brief  Fills each RTC_TimeStruct member with its default value
+  *         (Time = 00h:00min:00sec).
+  * @param  RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure which will be 
+  *         initialized.
+  * @retval None
+  */
+void RTC_TimeStructInit(RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  /* Time = 00h:00min:00sec */
+  RTC_TimeStruct->RTC_H12 = RTC_H12_AM;
+  RTC_TimeStruct->RTC_Hours = 0;
+  RTC_TimeStruct->RTC_Minutes = 0;
+  RTC_TimeStruct->RTC_Seconds = 0; 
+}
+
+/**
+  * @brief  Get the RTC current Time.
+  * @param  RTC_Format: specifies the format of the returned parameters.
+  *          This parameter can be  one of the following values:
+  *            @arg RTC_Format_BIN:  Binary data format 
+  *            @arg RTC_Format_BCD:  BCD data format
+  * @param  RTC_TimeStruct: pointer to a RTC_TimeTypeDef structure that will 
+  *                        contain the returned current time configuration.     
+  * @retval None
+  */
+void RTC_GetTime(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_TimeStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  /* Get the RTC_TR register */
+  tmpreg = (uint32_t)(RTC->TR & RTC_TR_RESERVED_MASK); 
+  
+  /* Fill the structure fields with the read parameters */
+  RTC_TimeStruct->RTC_Hours = (uint8_t)((tmpreg & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+  RTC_TimeStruct->RTC_Minutes = (uint8_t)((tmpreg & (RTC_TR_MNT | RTC_TR_MNU)) >>8);
+  RTC_TimeStruct->RTC_Seconds = (uint8_t)(tmpreg & (RTC_TR_ST | RTC_TR_SU));
+  RTC_TimeStruct->RTC_H12 = (uint8_t)((tmpreg & (RTC_TR_PM)) >> 16);  
+
+  /* Check the input parameters format */
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Convert the structure parameters to Binary format */
+    RTC_TimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Hours);
+    RTC_TimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Minutes);
+    RTC_TimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_TimeStruct->RTC_Seconds);   
+  }
+}
+
+/**
+  * @brief  Gets the RTC current Calendar Subseconds value.
+  * @note   This function freeze the Time and Date registers after reading the 
+  *         SSR register.
+  * @param  None
+  * @retval RTC current Calendar Subseconds value.
+  */
+uint32_t RTC_GetSubSecond(void)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Get subseconds values from the correspondent registers*/
+  tmpreg = (uint32_t)(RTC->SSR);
+  
+  /* Read DR register to unfroze calendar registers */
+  (void) (RTC->DR);
+  
+  return (tmpreg);
+}
+
+/**
+  * @brief  Set the RTC current date.
+  * @param  RTC_Format: specifies the format of the entered parameters.
+  *          This parameter can be  one of the following values:
+  *            @arg RTC_Format_BIN:  Binary data format 
+  *            @arg RTC_Format_BCD:  BCD data format
+  * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure that contains 
+  *                         the date configuration information for the RTC.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Date register is configured
+  *          - ERROR: RTC Date register is not configured
+  */
+ErrorStatus RTC_SetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
+{
+  uint32_t tmpreg = 0;
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  if ((RTC_Format == RTC_Format_BIN) && ((RTC_DateStruct->RTC_Month & 0x10) == 0x10))
+  {
+    RTC_DateStruct->RTC_Month = (RTC_DateStruct->RTC_Month & (uint32_t)~(0x10)) + 0x0A;
+  }  
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    assert_param(IS_RTC_YEAR(RTC_DateStruct->RTC_Year));
+    assert_param(IS_RTC_MONTH(RTC_DateStruct->RTC_Month));
+    assert_param(IS_RTC_DATE(RTC_DateStruct->RTC_Date));
+  }
+  else
+  {
+    assert_param(IS_RTC_YEAR(RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year)));
+    tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
+    assert_param(IS_RTC_MONTH(tmpreg));
+    tmpreg = RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
+    assert_param(IS_RTC_DATE(tmpreg));
+  }
+  assert_param(IS_RTC_WEEKDAY(RTC_DateStruct->RTC_WeekDay));
+
+  /* Check the input parameters format */
+  if (RTC_Format != RTC_Format_BIN)
+  {
+    tmpreg = ((((uint32_t)RTC_DateStruct->RTC_Year) << 16) | \
+              (((uint32_t)RTC_DateStruct->RTC_Month) << 8) | \
+              ((uint32_t)RTC_DateStruct->RTC_Date) | \
+              (((uint32_t)RTC_DateStruct->RTC_WeekDay) << 13)); 
+  }  
+  else
+  {
+    tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Year) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Month) << 8) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_DateStruct->RTC_Date)) | \
+              ((uint32_t)RTC_DateStruct->RTC_WeekDay << 13));
+  }
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {
+    /* Set the RTC_DR register */
+    RTC->DR = (uint32_t)(tmpreg & RTC_DR_RESERVED_MASK);
+
+    /* Exit Initialization mode */
+    RTC_ExitInitMode(); 
+
+    if(RTC_WaitForSynchro() == ERROR)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      status = SUCCESS;
+    }
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;   
+  
+  return status;
+}
+
+/**
+  * @brief  Fills each RTC_DateStruct member with its default value
+  *         (Monday, January 01 xx00).
+  * @param  RTC_DateStruct: pointer to a RTC_DateTypeDef structure which will be 
+  *         initialized.
+  * @retval None
+  */
+void RTC_DateStructInit(RTC_DateTypeDef* RTC_DateStruct)
+{
+  /* Monday, January 01 xx00 */
+  RTC_DateStruct->RTC_WeekDay = RTC_Weekday_Monday;
+  RTC_DateStruct->RTC_Date = 1;
+  RTC_DateStruct->RTC_Month = RTC_Month_January;
+  RTC_DateStruct->RTC_Year = 0;
+}
+
+/**
+  * @brief  Get the RTC current date. 
+  * @param  RTC_Format: specifies the format of the returned parameters.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Format_BIN: Binary data format 
+  *            @arg RTC_Format_BCD: BCD data format
+  * @param RTC_DateStruct: pointer to a RTC_DateTypeDef structure that will 
+  *                        contain the returned current date configuration.     
+  * @retval None
+  */
+void RTC_GetDate(uint32_t RTC_Format, RTC_DateTypeDef* RTC_DateStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  
+  /* Get the RTC_TR register */
+  tmpreg = (uint32_t)(RTC->DR & RTC_DR_RESERVED_MASK); 
+
+  /* Fill the structure fields with the read parameters */
+  RTC_DateStruct->RTC_Year = (uint8_t)((tmpreg & (RTC_DR_YT | RTC_DR_YU)) >> 16);
+  RTC_DateStruct->RTC_Month = (uint8_t)((tmpreg & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+  RTC_DateStruct->RTC_Date = (uint8_t)(tmpreg & (RTC_DR_DT | RTC_DR_DU));
+  RTC_DateStruct->RTC_WeekDay = (uint8_t)((tmpreg & (RTC_DR_WDU)) >> 13);  
+
+  /* Check the input parameters format */
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Convert the structure parameters to Binary format */
+    RTC_DateStruct->RTC_Year = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Year);
+    RTC_DateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Month);
+    RTC_DateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_DateStruct->RTC_Date);
+    RTC_DateStruct->RTC_WeekDay = (uint8_t)(RTC_DateStruct->RTC_WeekDay);   
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group3 Alarms configuration functions
+ *  @brief   Alarms (Alarm A and Alarm B) configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+              Alarms (Alarm A and Alarm B) configuration functions
+ ===============================================================================  
+
+  This section provide functions allowing to program and read the RTC Alarms.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Set the specified RTC Alarm.
+  * @note   The Alarm register can only be written when the corresponding Alarm
+  *         is disabled (Use the RTC_AlarmCmd(DISABLE)).    
+  * @param  RTC_Format: specifies the format of the returned parameters.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Format_BIN: Binary data format 
+  *            @arg RTC_Format_BCD: BCD data format
+  * @param  RTC_Alarm: specifies the alarm to be configured.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Alarm_A: to select Alarm A
+  *            @arg RTC_Alarm_B: to select Alarm B  
+  * @param  RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that 
+  *                          contains the alarm configuration parameters.     
+  * @retval None
+  */
+void RTC_SetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  assert_param(IS_RTC_ALARM(RTC_Alarm));
+  assert_param(IS_ALARM_MASK(RTC_AlarmStruct->RTC_AlarmMask));
+  assert_param(IS_RTC_ALARM_DATE_WEEKDAY_SEL(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel));
+
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      assert_param(IS_RTC_HOUR12(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
+      assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
+    } 
+    else
+    {
+      RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours));
+    }
+    assert_param(IS_RTC_MINUTES(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes));
+    assert_param(IS_RTC_SECONDS(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds));
+    
+    if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
+    {
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
+    }
+    else
+    {
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(RTC_AlarmStruct->RTC_AlarmDateWeekDay));
+    }
+  }
+  else
+  {
+    if ((RTC->CR & RTC_CR_FMT) != (uint32_t)RESET)
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours);
+      assert_param(IS_RTC_HOUR12(tmpreg));
+      assert_param(IS_RTC_H12(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12));
+    } 
+    else
+    {
+      RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = 0x00;
+      assert_param(IS_RTC_HOUR24(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours)));
+    }
+    
+    assert_param(IS_RTC_MINUTES(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes)));
+    assert_param(IS_RTC_SECONDS(RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)));
+    
+    if(RTC_AlarmStruct->RTC_AlarmDateWeekDaySel == RTC_AlarmDateWeekDaySel_Date)
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_DATE(tmpreg));    
+    }
+    else
+    {
+      tmpreg = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+      assert_param(IS_RTC_ALARM_DATE_WEEKDAY_WEEKDAY(tmpreg));      
+    }    
+  }
+
+  /* Check the input parameters format */
+  if (RTC_Format != RTC_Format_BIN)
+  {
+    tmpreg = (((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); 
+  }  
+  else
+  {
+    tmpreg = (((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes) << 8) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds)) | \
+              ((uint32_t)(RTC_AlarmStruct->RTC_AlarmTime.RTC_H12) << 16) | \
+              ((uint32_t)RTC_ByteToBcd2(RTC_AlarmStruct->RTC_AlarmDateWeekDay) << 24) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmDateWeekDaySel) | \
+              ((uint32_t)RTC_AlarmStruct->RTC_AlarmMask)); 
+  } 
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Configure the Alarm register */
+  if (RTC_Alarm == RTC_Alarm_A)
+  {
+    RTC->ALRMAR = (uint32_t)tmpreg;
+  }
+  else
+  {
+    RTC->ALRMBR = (uint32_t)tmpreg;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;   
+}
+
+/**
+  * @brief  Fills each RTC_AlarmStruct member with its default value
+  *         (Time = 00h:00mn:00sec / Date = 1st day of the month/Mask =
+  *         all fields are masked).
+  * @param  RTC_AlarmStruct: pointer to a @ref RTC_AlarmTypeDef structure which
+  *         will be initialized.
+  * @retval None
+  */
+void RTC_AlarmStructInit(RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  /* Alarm Time Settings : Time = 00h:00mn:00sec */
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = RTC_H12_AM;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = 0;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = 0;
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = 0;
+
+  /* Alarm Date Settings : Date = 1st day of the month */
+  RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = RTC_AlarmDateWeekDaySel_Date;
+  RTC_AlarmStruct->RTC_AlarmDateWeekDay = 1;
+
+  /* Alarm Masks Settings : Mask =  all fields are not masked */
+  RTC_AlarmStruct->RTC_AlarmMask = RTC_AlarmMask_None;
+}
+
+/**
+  * @brief  Get the RTC Alarm value and masks.
+  * @param  RTC_Format: specifies the format of the output parameters.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Format_BIN: Binary data format 
+  *            @arg RTC_Format_BCD: BCD data format
+  * @param  RTC_Alarm: specifies the alarm to be read.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Alarm_A: to select Alarm A
+  *            @arg RTC_Alarm_B: to select Alarm B  
+  * @param  RTC_AlarmStruct: pointer to a RTC_AlarmTypeDef structure that will 
+  *                          contains the output alarm configuration values.     
+  * @retval None
+  */
+void RTC_GetAlarm(uint32_t RTC_Format, uint32_t RTC_Alarm, RTC_AlarmTypeDef* RTC_AlarmStruct)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+  assert_param(IS_RTC_ALARM(RTC_Alarm)); 
+
+  /* Get the RTC_ALRMxR register */
+  if (RTC_Alarm == RTC_Alarm_A)
+  {
+    tmpreg = (uint32_t)(RTC->ALRMAR);
+  }
+  else
+  {
+    tmpreg = (uint32_t)(RTC->ALRMBR);
+  }
+
+  /* Fill the structure with the read parameters */
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = (uint32_t)((tmpreg & (RTC_ALRMAR_HT | \
+                                                     RTC_ALRMAR_HU)) >> 16);
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = (uint32_t)((tmpreg & (RTC_ALRMAR_MNT | \
+                                                     RTC_ALRMAR_MNU)) >> 8);
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = (uint32_t)(tmpreg & (RTC_ALRMAR_ST | \
+                                                     RTC_ALRMAR_SU));
+  RTC_AlarmStruct->RTC_AlarmTime.RTC_H12 = (uint32_t)((tmpreg & RTC_ALRMAR_PM) >> 16);
+  RTC_AlarmStruct->RTC_AlarmDateWeekDay = (uint32_t)((tmpreg & (RTC_ALRMAR_DT | RTC_ALRMAR_DU)) >> 24);
+  RTC_AlarmStruct->RTC_AlarmDateWeekDaySel = (uint32_t)(tmpreg & RTC_ALRMAR_WDSEL);
+  RTC_AlarmStruct->RTC_AlarmMask = (uint32_t)(tmpreg & RTC_AlarmMask_All);
+
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Hours = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+                                                        RTC_AlarmTime.RTC_Hours);
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Minutes = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+                                                        RTC_AlarmTime.RTC_Minutes);
+    RTC_AlarmStruct->RTC_AlarmTime.RTC_Seconds = RTC_Bcd2ToByte(RTC_AlarmStruct-> \
+                                                        RTC_AlarmTime.RTC_Seconds);
+    RTC_AlarmStruct->RTC_AlarmDateWeekDay = RTC_Bcd2ToByte(RTC_AlarmStruct->RTC_AlarmDateWeekDay);
+  }  
+}
+
+/**
+  * @brief  Enables or disables the specified RTC Alarm.
+  * @param  RTC_Alarm: specifies the alarm to be configured.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_Alarm_A: to select Alarm A
+  *            @arg RTC_Alarm_B: to select Alarm B  
+  * @param  NewState: new state of the specified alarm.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Alarm is enabled/disabled
+  *          - ERROR: RTC Alarm is not enabled/disabled  
+  */
+ErrorStatus RTC_AlarmCmd(uint32_t RTC_Alarm, FunctionalState NewState)
+{
+  __IO uint32_t alarmcounter = 0x00;
+  uint32_t alarmstatus = 0x00;
+  ErrorStatus status = ERROR;
+    
+  /* Check the parameters */
+  assert_param(IS_RTC_CMD_ALARM(RTC_Alarm));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Configure the Alarm state */
+  if (NewState != DISABLE)
+  {
+    RTC->CR |= (uint32_t)RTC_Alarm;
+
+    status = SUCCESS;    
+  }
+  else
+  { 
+    /* Disable the Alarm in RTC_CR register */
+    RTC->CR &= (uint32_t)~RTC_Alarm;
+   
+    /* Wait till RTC ALRxWF flag is set and if Time out is reached exit */
+    do
+    {
+      alarmstatus = RTC->ISR & (RTC_Alarm >> 8);
+      alarmcounter++;  
+    } while((alarmcounter != INITMODE_TIMEOUT) && (alarmstatus == 0x00));
+    
+    if ((RTC->ISR & (RTC_Alarm >> 8)) == RESET)
+    {
+      status = ERROR;
+    } 
+    else
+    {
+      status = SUCCESS;
+    }        
+  } 
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+  
+  return status;
+}
+
+/**
+  * @brief  Configure the RTC AlarmA/B Subseconds value and mask.*
+  * @note   This function is performed only when the Alarm is disabled. 
+  * @param  RTC_Alarm: specifies the alarm to be configured.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_Alarm_A: to select Alarm A
+  *     @arg RTC_Alarm_B: to select Alarm B
+  * @param  RTC_AlarmSubSecondValue: specifies the Subseconds value.
+  *   This parameter can be a value from 0 to 0x00007FFF.
+  * @param  RTC_AlarmSubSecondMask:  specifies the Subseconds Mask.
+  *   This parameter can be any combination of the following values:
+  *     @arg RTC_AlarmSubSecondMask_All    : All Alarm SS fields are masked.
+  *                                          There is no comparison on sub seconds for Alarm.
+  *     @arg RTC_AlarmSubSecondMask_SS14_1 : SS[14:1] are don't care in Alarm comparison.
+  *                                          Only SS[0] is compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_2 : SS[14:2] are don't care in Alarm comparison.
+  *                                          Only SS[1:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_3 : SS[14:3] are don't care in Alarm comparison.
+  *                                          Only SS[2:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_4 : SS[14:4] are don't care in Alarm comparison.
+  *                                          Only SS[3:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_5 : SS[14:5] are don't care in Alarm comparison.
+  *                                          Only SS[4:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_6 : SS[14:6] are don't care in Alarm comparison.
+  *                                          Only SS[5:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_7 : SS[14:7] are don't care in Alarm comparison.
+  *                                          Only SS[6:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_8 : SS[14:8] are don't care in Alarm comparison.
+  *                                          Only SS[7:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_9 : SS[14:9] are don't care in Alarm comparison.
+  *                                          Only SS[8:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_10: SS[14:10] are don't care in Alarm comparison.
+  *                                          Only SS[9:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_11: SS[14:11] are don't care in Alarm comparison.
+  *                                          Only SS[10:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_12: SS[14:12] are don't care in Alarm comparison.
+  *                                          Only SS[11:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14_13: SS[14:13] are don't care in Alarm comparison.
+  *                                          Only SS[12:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_SS14   : SS[14] is don't care in Alarm comparison.
+  *                                          Only SS[13:0] are compared
+  *     @arg RTC_AlarmSubSecondMask_None   : SS[14:0] are compared and must match
+  *                                          to activate alarm
+  * @retval None
+  */
+void RTC_AlarmSubSecondConfig(uint32_t RTC_Alarm, uint32_t RTC_AlarmSubSecondValue, uint32_t RTC_AlarmSubSecondMask)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_ALARM(RTC_Alarm));
+  assert_param(IS_RTC_ALARM_SUB_SECOND_VALUE(RTC_AlarmSubSecondValue));
+  assert_param(IS_RTC_ALARM_SUB_SECOND_MASK(RTC_AlarmSubSecondMask));
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* Configure the Alarm A or Alarm B SubSecond registers */
+  tmpreg = (uint32_t) (uint32_t)(RTC_AlarmSubSecondValue) | (uint32_t)(RTC_AlarmSubSecondMask);
+  
+  if (RTC_Alarm == RTC_Alarm_A)
+  {
+    /* Configure the AlarmA SubSecond register */
+    RTC->ALRMASSR = tmpreg;
+  }
+  else
+  {
+    /* Configure the Alarm B SubSecond register */
+    RTC->ALRMBSSR = tmpreg;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+
+}
+
+/**
+  * @brief  Gets the RTC Alarm Subseconds value.
+  * @param  RTC_Alarm: specifies the alarm to be read.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_Alarm_A: to select Alarm A
+  *     @arg RTC_Alarm_B: to select Alarm B
+  * @param  None
+  * @retval RTC Alarm Subseconds value.
+  */
+uint32_t RTC_GetAlarmSubSecond(uint32_t RTC_Alarm)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Get the RTC_ALRMxR register */
+  if (RTC_Alarm == RTC_Alarm_A)
+  {
+    tmpreg = (uint32_t)((RTC->ALRMASSR) & RTC_ALRMASSR_SS);
+  }
+  else
+  {
+    tmpreg = (uint32_t)((RTC->ALRMBSSR) & RTC_ALRMBSSR_SS);
+  } 
+  
+  return (tmpreg);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group4 WakeUp Timer configuration functions
+ *  @brief   WakeUp Timer configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                     WakeUp Timer configuration functions
+ ===============================================================================  
+
+  This section provide functions allowing to program and read the RTC WakeUp.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the RTC Wakeup clock source.
+  * @note   The WakeUp Clock source can only be changed when the RTC WakeUp
+  *         is disabled (Use the RTC_WakeUpCmd(DISABLE)).      
+  * @param  RTC_WakeUpClock: Wakeup Clock source.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_WakeUpClock_RTCCLK_Div16: RTC Wakeup Counter Clock = RTCCLK/16
+  *            @arg RTC_WakeUpClock_RTCCLK_Div8: RTC Wakeup Counter Clock = RTCCLK/8
+  *            @arg RTC_WakeUpClock_RTCCLK_Div4: RTC Wakeup Counter Clock = RTCCLK/4
+  *            @arg RTC_WakeUpClock_RTCCLK_Div2: RTC Wakeup Counter Clock = RTCCLK/2
+  *            @arg RTC_WakeUpClock_CK_SPRE_16bits: RTC Wakeup Counter Clock = CK_SPRE
+  *            @arg RTC_WakeUpClock_CK_SPRE_17bits: RTC Wakeup Counter Clock = CK_SPRE
+  * @retval None
+  */
+void RTC_WakeUpClockConfig(uint32_t RTC_WakeUpClock)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_WAKEUP_CLOCK(RTC_WakeUpClock));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear the Wakeup Timer clock source bits in CR register */
+  RTC->CR &= (uint32_t)~RTC_CR_WUCKSEL;
+
+  /* Configure the clock source */
+  RTC->CR |= (uint32_t)RTC_WakeUpClock;
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Configures the RTC Wakeup counter.
+  * @note   The RTC WakeUp counter can only be written when the RTC WakeUp
+  *         is disabled (Use the RTC_WakeUpCmd(DISABLE)).        
+  * @param  RTC_WakeUpCounter: specifies the WakeUp counter.
+  *          This parameter can be a value from 0x0000 to 0xFFFF. 
+  * @retval None
+  */
+void RTC_SetWakeUpCounter(uint32_t RTC_WakeUpCounter)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_WAKEUP_COUNTER(RTC_WakeUpCounter));
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* Configure the Wakeup Timer counter */
+  RTC->WUTR = (uint32_t)RTC_WakeUpCounter;
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Returns the RTC WakeUp timer counter value.
+  * @param  None
+  * @retval The RTC WakeUp Counter value.
+  */
+uint32_t RTC_GetWakeUpCounter(void)
+{
+  /* Get the counter value */
+  return ((uint32_t)(RTC->WUTR & RTC_WUTR_WUT));
+}
+
+/**
+  * @brief  Enables or Disables the RTC WakeUp timer.
+  * @param  NewState: new state of the WakeUp timer.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+ErrorStatus RTC_WakeUpCmd(FunctionalState NewState)
+{
+  __IO uint32_t wutcounter = 0x00;
+  uint32_t wutwfstatus = 0x00;
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the Wakeup Timer */
+    RTC->CR |= (uint32_t)RTC_CR_WUTE;
+    status = SUCCESS;    
+  }
+  else
+  {
+    /* Disable the Wakeup Timer */
+    RTC->CR &= (uint32_t)~RTC_CR_WUTE;
+    /* Wait till RTC WUTWF flag is set and if Time out is reached exit */
+    do
+    {
+      wutwfstatus = RTC->ISR & RTC_ISR_WUTWF;
+      wutcounter++;  
+    } while((wutcounter != INITMODE_TIMEOUT) && (wutwfstatus == 0x00));
+    
+    if ((RTC->ISR & RTC_ISR_WUTWF) == RESET)
+    {
+      status = ERROR;
+    }
+    else
+    {
+      status = SUCCESS;
+    }    
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+  
+  return status;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group5 Daylight Saving configuration functions
+ *  @brief   Daylight Saving configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                    Daylight Saving configuration functions
+ ===============================================================================  
+
+  This section provide functions allowing to configure the RTC DayLight Saving.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Adds or substract one hour from the current time.
+  * @param  RTC_DayLightSaveOperation: the value of hour adjustment. 
+  *          This parameter can be one of the following values:
+  *            @arg RTC_DayLightSaving_SUB1H: Substract one hour (winter time)
+  *            @arg RTC_DayLightSaving_ADD1H: Add one hour (summer time)
+  * @param  RTC_StoreOperation: Specifies the value to be written in the BCK bit 
+  *                            in CR register to store the operation.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_StoreOperation_Reset: BCK Bit Reset
+  *            @arg RTC_StoreOperation_Set: BCK Bit Set
+  * @retval None
+  */
+void RTC_DayLightSavingConfig(uint32_t RTC_DayLightSaving, uint32_t RTC_StoreOperation)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_DAYLIGHT_SAVING(RTC_DayLightSaving));
+  assert_param(IS_RTC_STORE_OPERATION(RTC_StoreOperation));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear the bits to be configured */
+  RTC->CR &= (uint32_t)~(RTC_CR_BCK);
+
+  /* Configure the RTC_CR register */
+  RTC->CR |= (uint32_t)(RTC_DayLightSaving | RTC_StoreOperation);
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Returns the RTC Day Light Saving stored operation.
+  * @param  None
+  * @retval RTC Day Light Saving stored operation.
+  *          - RTC_StoreOperation_Reset
+  *          - RTC_StoreOperation_Set       
+  */
+uint32_t RTC_GetStoreOperation(void)
+{
+  return (RTC->CR & RTC_CR_BCK);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group6 Output pin Configuration function
+ *  @brief   Output pin Configuration function 
+ *
+@verbatim   
+ ===============================================================================
+                         Output pin Configuration function
+ ===============================================================================  
+
+  This section provide functions allowing to configure the RTC Output source.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the RTC output source (AFO_ALARM).
+  * @param  RTC_Output: Specifies which signal will be routed to the RTC output. 
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Output_Disable: No output selected
+  *            @arg RTC_Output_AlarmA: signal of AlarmA mapped to output
+  *            @arg RTC_Output_AlarmB: signal of AlarmB mapped to output
+  *            @arg RTC_Output_WakeUp: signal of WakeUp mapped to output
+  * @param  RTC_OutputPolarity: Specifies the polarity of the output signal. 
+  *          This parameter can be one of the following:
+  *            @arg RTC_OutputPolarity_High: The output pin is high when the 
+  *                                 ALRAF/ALRBF/WUTF is high (depending on OSEL)
+  *            @arg RTC_OutputPolarity_Low: The output pin is low when the 
+  *                                 ALRAF/ALRBF/WUTF is high (depending on OSEL)
+  * @retval None
+  */
+void RTC_OutputConfig(uint32_t RTC_Output, uint32_t RTC_OutputPolarity)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_OUTPUT(RTC_Output));
+  assert_param(IS_RTC_OUTPUT_POL(RTC_OutputPolarity));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Clear the bits to be configured */
+  RTC->CR &= (uint32_t)~(RTC_CR_OSEL | RTC_CR_POL);
+
+  /* Configure the output selection and polarity */
+  RTC->CR |= (uint32_t)(RTC_Output | RTC_OutputPolarity);
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group7 Digital Calibration configuration functions
+ *  @brief   Coarse Calibration configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                  Digital Calibration configuration functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the Coarse calibration parameters.
+  * @param  RTC_CalibSign: specifies the sign of the coarse calibration value.
+  *          This parameter can be  one of the following values:
+  *            @arg RTC_CalibSign_Positive: The value sign is positive 
+  *            @arg RTC_CalibSign_Negative: The value sign is negative
+  * @param  Value: value of coarse calibration expressed in ppm (coded on 5 bits).
+  *    
+  * @note   This Calibration value should be between 0 and 63 when using negative
+  *         sign with a 2-ppm step.
+  *           
+  * @note   This Calibration value should be between 0 and 126 when using positive
+  *         sign with a 4-ppm step.
+  *           
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Coarse calibration are initialized
+  *          - ERROR: RTC Coarse calibration are not initialized     
+  */
+ErrorStatus RTC_CoarseCalibConfig(uint32_t RTC_CalibSign, uint32_t Value)
+{
+  ErrorStatus status = ERROR;
+   
+  /* Check the parameters */
+  assert_param(IS_RTC_CALIB_SIGN(RTC_CalibSign));
+  assert_param(IS_RTC_CALIB_VALUE(Value)); 
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status = ERROR;
+  } 
+  else
+  {
+    /* Set the coarse calibration value */
+    RTC->CALIBR = (uint32_t)(RTC_CalibSign | Value);
+    /* Exit Initialization mode */
+    RTC_ExitInitMode();
+    
+    status = SUCCESS;
+  } 
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+  
+  return status;
+}
+
+/**
+  * @brief  Enables or disables the Coarse calibration process.
+  * @param  NewState: new state of the Coarse calibration.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Coarse calibration are enabled/disabled
+  *          - ERROR: RTC Coarse calibration are not enabled/disabled    
+  */
+ErrorStatus RTC_CoarseCalibCmd(FunctionalState NewState)
+{
+  ErrorStatus status = ERROR;
+  
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* Set Initialization mode */
+  if (RTC_EnterInitMode() == ERROR)
+  {
+    status =  ERROR;
+  }
+  else
+  {
+    if (NewState != DISABLE)
+    {
+      /* Enable the Coarse Calibration */
+      RTC->CR |= (uint32_t)RTC_CR_DCE;
+    }
+    else
+    { 
+      /* Disable the Coarse Calibration */
+      RTC->CR &= (uint32_t)~RTC_CR_DCE;
+    }
+    /* Exit Initialization mode */
+    RTC_ExitInitMode();
+    
+    status = SUCCESS;
+  } 
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+  
+  return status;
+}
+
+/**
+  * @brief  Enables or disables the RTC clock to be output through the relative pin.
+  * @param  NewState: new state of the digital calibration Output.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_CalibOutputCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the RTC clock output */
+    RTC->CR |= (uint32_t)RTC_CR_COE;
+  }
+  else
+  { 
+    /* Disable the RTC clock output */
+    RTC->CR &= (uint32_t)~RTC_CR_COE;
+  }
+  
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Configure the Calibration Pinout (RTC_CALIB) Selection (1Hz or 512Hz).
+  * @param  RTC_CalibOutput : Select the Calibration output Selection .
+  *   This parameter can be one of the following values:
+  *     @arg RTC_CalibOutput_512Hz: A signal has a regular waveform at 512Hz. 
+  *     @arg RTC_CalibOutput_1Hz  : A signal has a regular waveform at 1Hz.
+  * @retval None
+*/
+void RTC_CalibOutputConfig(uint32_t RTC_CalibOutput)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CALIB_OUTPUT(RTC_CalibOutput));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /*clear flags before config*/
+  RTC->CR &= (uint32_t)~(RTC_CR_COSEL);
+
+  /* Configure the RTC_CR register */
+  RTC->CR |= (uint32_t)RTC_CalibOutput;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+}
+
+/**
+  * @brief  Configures the Smooth Calibration Settings.
+  * @param  RTC_SmoothCalibPeriod : Select the Smooth Calibration Period.
+  *   This parameter can be can be one of the following values:
+  *     @arg RTC_SmoothCalibPeriod_32sec : The smooth calibration periode is 32s.
+  *     @arg RTC_SmoothCalibPeriod_16sec : The smooth calibration periode is 16s.
+  *     @arg RTC_SmoothCalibPeriod_8sec  : The smooth calibartion periode is 8s.
+  * @param  RTC_SmoothCalibPlusPulses : Select to Set or reset the CALP bit.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_SmoothCalibPlusPulses_Set  : Add one RTCCLK puls every 2**11 pulses.
+  *     @arg RTC_SmoothCalibPlusPulses_Reset: No RTCCLK pulses are added.
+  * @param  RTC_SmouthCalibMinusPulsesValue: Select the value of CALM[8:0] bits.
+  *   This parameter can be one any value from 0 to 0x000001FF.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Calib registers are configured
+  *          - ERROR: RTC Calib registers are not configured
+*/
+ErrorStatus RTC_SmoothCalibConfig(uint32_t RTC_SmoothCalibPeriod,
+                                  uint32_t RTC_SmoothCalibPlusPulses,
+                                  uint32_t RTC_SmouthCalibMinusPulsesValue)
+{
+  ErrorStatus status = ERROR;
+  uint32_t recalpfcount = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_SMOOTH_CALIB_PERIOD(RTC_SmoothCalibPeriod));
+  assert_param(IS_RTC_SMOOTH_CALIB_PLUS(RTC_SmoothCalibPlusPulses));
+  assert_param(IS_RTC_SMOOTH_CALIB_MINUS(RTC_SmouthCalibMinusPulsesValue));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* check if a calibration is pending*/
+  if ((RTC->ISR & RTC_ISR_RECALPF) != RESET)
+  {
+    /* wait until the Calibration is completed*/
+    while (((RTC->ISR & RTC_ISR_RECALPF) != RESET) && (recalpfcount != RECALPF_TIMEOUT))
+    {
+      recalpfcount++;
+    }
+  }
+
+  /* check if the calibration pending is completed or if there is no calibration operation at all*/
+  if ((RTC->ISR & RTC_ISR_RECALPF) == RESET)
+  {
+    /* Configure the Smooth calibration settings */
+    RTC->CALR = (uint32_t)((uint32_t)RTC_SmoothCalibPeriod | (uint32_t)RTC_SmoothCalibPlusPulses | (uint32_t)RTC_SmouthCalibMinusPulsesValue);
+
+    status = SUCCESS;
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return (ErrorStatus)(status);
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup RTC_Group8 TimeStamp configuration functions
+ *  @brief   TimeStamp configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                       TimeStamp configuration functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or Disables the RTC TimeStamp functionality with the 
+  *         specified time stamp pin stimulating edge.
+  * @param  RTC_TimeStampEdge: Specifies the pin edge on which the TimeStamp is 
+  *         activated.
+  *          This parameter can be one of the following:
+  *            @arg RTC_TimeStampEdge_Rising: the Time stamp event occurs on the rising 
+  *                                    edge of the related pin.
+  *            @arg RTC_TimeStampEdge_Falling: the Time stamp event occurs on the 
+  *                                     falling edge of the related pin.
+  * @param  NewState: new state of the TimeStamp.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_TimeStampCmd(uint32_t RTC_TimeStampEdge, FunctionalState NewState)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_TIMESTAMP_EDGE(RTC_TimeStampEdge));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Get the RTC_CR register and clear the bits to be configured */
+  tmpreg = (uint32_t)(RTC->CR & (uint32_t)~(RTC_CR_TSEDGE | RTC_CR_TSE));
+
+  /* Get the new configuration */
+  if (NewState != DISABLE)
+  {
+    tmpreg |= (uint32_t)(RTC_TimeStampEdge | RTC_CR_TSE);
+  }
+  else
+  {
+    tmpreg |= (uint32_t)(RTC_TimeStampEdge);
+  }
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  /* Configure the Time Stamp TSEDGE and Enable bits */
+  RTC->CR = (uint32_t)tmpreg;
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Get the RTC TimeStamp value and masks.
+  * @param  RTC_Format: specifies the format of the output parameters.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_Format_BIN: Binary data format 
+  *            @arg RTC_Format_BCD: BCD data format
+  * @param RTC_StampTimeStruct: pointer to a RTC_TimeTypeDef structure that will 
+  *                             contains the TimeStamp time values. 
+  * @param RTC_StampDateStruct: pointer to a RTC_DateTypeDef structure that will 
+  *                             contains the TimeStamp date values.     
+  * @retval None
+  */
+void RTC_GetTimeStamp(uint32_t RTC_Format, RTC_TimeTypeDef* RTC_StampTimeStruct, 
+                                      RTC_DateTypeDef* RTC_StampDateStruct)
+{
+  uint32_t tmptime = 0, tmpdate = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_FORMAT(RTC_Format));
+
+  /* Get the TimeStamp time and date registers values */
+  tmptime = (uint32_t)(RTC->TSTR & RTC_TR_RESERVED_MASK);
+  tmpdate = (uint32_t)(RTC->TSDR & RTC_DR_RESERVED_MASK);
+
+  /* Fill the Time structure fields with the read parameters */
+  RTC_StampTimeStruct->RTC_Hours = (uint8_t)((tmptime & (RTC_TR_HT | RTC_TR_HU)) >> 16);
+  RTC_StampTimeStruct->RTC_Minutes = (uint8_t)((tmptime & (RTC_TR_MNT | RTC_TR_MNU)) >> 8);
+  RTC_StampTimeStruct->RTC_Seconds = (uint8_t)(tmptime & (RTC_TR_ST | RTC_TR_SU));
+  RTC_StampTimeStruct->RTC_H12 = (uint8_t)((tmptime & (RTC_TR_PM)) >> 16);  
+
+  /* Fill the Date structure fields with the read parameters */
+  RTC_StampDateStruct->RTC_Year = 0;
+  RTC_StampDateStruct->RTC_Month = (uint8_t)((tmpdate & (RTC_DR_MT | RTC_DR_MU)) >> 8);
+  RTC_StampDateStruct->RTC_Date = (uint8_t)(tmpdate & (RTC_DR_DT | RTC_DR_DU));
+  RTC_StampDateStruct->RTC_WeekDay = (uint8_t)((tmpdate & (RTC_DR_WDU)) >> 13);
+
+  /* Check the input parameters format */
+  if (RTC_Format == RTC_Format_BIN)
+  {
+    /* Convert the Time structure parameters to Binary format */
+    RTC_StampTimeStruct->RTC_Hours = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Hours);
+    RTC_StampTimeStruct->RTC_Minutes = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Minutes);
+    RTC_StampTimeStruct->RTC_Seconds = (uint8_t)RTC_Bcd2ToByte(RTC_StampTimeStruct->RTC_Seconds);
+
+    /* Convert the Date structure parameters to Binary format */
+    RTC_StampDateStruct->RTC_Month = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Month);
+    RTC_StampDateStruct->RTC_Date = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_Date);
+    RTC_StampDateStruct->RTC_WeekDay = (uint8_t)RTC_Bcd2ToByte(RTC_StampDateStruct->RTC_WeekDay);
+  }
+}
+
+/**
+  * @brief  Get the RTC timestamp Subseconds value.
+  * @param  None
+  * @retval RTC current timestamp Subseconds value.
+  */
+uint32_t RTC_GetTimeStampSubSecond(void)
+{
+  /* Get timestamp subseconds values from the correspondent registers */
+  return (uint32_t)(RTC->TSSSR);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group9 Tampers configuration functions
+ *  @brief   Tampers configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                       Tampers configuration functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the select Tamper pin edge.
+  * @param  RTC_Tamper: Selected tamper pin.
+  *          This parameter can be RTC_Tamper_1.
+  * @param  RTC_TamperTrigger: Specifies the trigger on the tamper pin that 
+  *         stimulates tamper event. 
+  *   This parameter can be one of the following values:
+  *     @arg RTC_TamperTrigger_RisingEdge: Rising Edge of the tamper pin causes tamper event.
+  *     @arg RTC_TamperTrigger_FallingEdge: Falling Edge of the tamper pin causes tamper event.
+  *     @arg RTC_TamperTrigger_LowLevel: Low Level of the tamper pin causes tamper event.
+  *     @arg RTC_TamperTrigger_HighLevel: High Level of the tamper pin causes tamper event.
+  * @retval None
+  */
+void RTC_TamperTriggerConfig(uint32_t RTC_Tamper, uint32_t RTC_TamperTrigger)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER(RTC_Tamper)); 
+  assert_param(IS_RTC_TAMPER_TRIGGER(RTC_TamperTrigger));
+ 
+  if (RTC_TamperTrigger == RTC_TamperTrigger_RisingEdge)
+  {  
+    /* Configure the RTC_TAFCR register */
+    RTC->TAFCR &= (uint32_t)((uint32_t)~(RTC_Tamper << 1));	
+  }
+  else
+  { 
+    /* Configure the RTC_TAFCR register */
+    RTC->TAFCR |= (uint32_t)(RTC_Tamper << 1);  
+  }  
+}
+
+/**
+  * @brief  Enables or Disables the Tamper detection.
+  * @param  RTC_Tamper: Selected tamper pin.
+  *          This parameter can be RTC_Tamper_1.
+  * @param  NewState: new state of the tamper pin.
+  *          This parameter can be: ENABLE or DISABLE.                   
+  * @retval None
+  */
+void RTC_TamperCmd(uint32_t RTC_Tamper, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER(RTC_Tamper));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected Tamper pin */
+    RTC->TAFCR |= (uint32_t)RTC_Tamper;
+  }
+  else
+  {
+    /* Disable the selected Tamper pin */
+    RTC->TAFCR &= (uint32_t)~RTC_Tamper;    
+  }  
+}
+
+/**
+  * @brief  Configures the Tampers Filter.
+  * @param  RTC_TamperFilter: Specifies the tampers filter.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_TamperFilter_Disable: Tamper filter is disabled.
+  *     @arg RTC_TamperFilter_2Sample: Tamper is activated after 2 consecutive 
+  *                                    samples at the active level 
+  *     @arg RTC_TamperFilter_4Sample: Tamper is activated after 4 consecutive 
+  *                                    samples at the active level
+  *     @arg RTC_TamperFilter_8Sample: Tamper is activated after 8 consecutive 
+  *                                    samples at the active level 
+  * @retval None
+  */
+void RTC_TamperFilterConfig(uint32_t RTC_TamperFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_FILTER(RTC_TamperFilter));
+   
+  /* Clear TAMPFLT[1:0] bits in the RTC_TAFCR register */
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFLT);
+
+  /* Configure the RTC_TAFCR register */
+  RTC->TAFCR |= (uint32_t)RTC_TamperFilter;
+}
+
+/**
+  * @brief  Configures the Tampers Sampling Frequency.
+  * @param  RTC_TamperSamplingFreq: Specifies the tampers Sampling Frequency.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div32768: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 32768
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div16384: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 16384
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div8192: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 8192
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div4096: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 4096
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div2048: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 2048
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div1024: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 1024
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div512: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 512  
+  *     @arg RTC_TamperSamplingFreq_RTCCLK_Div256: Each of the tamper inputs are sampled
+  *                                           with a frequency =  RTCCLK / 256  
+  * @retval None
+  */
+void RTC_TamperSamplingFreqConfig(uint32_t RTC_TamperSamplingFreq)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_SAMPLING_FREQ(RTC_TamperSamplingFreq));
+ 
+  /* Clear TAMPFREQ[2:0] bits in the RTC_TAFCR register */
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPFREQ);
+
+  /* Configure the RTC_TAFCR register */
+  RTC->TAFCR |= (uint32_t)RTC_TamperSamplingFreq;
+}
+
+/**
+  * @brief  Configures the Tampers Pins input Precharge Duration.
+  * @param  RTC_TamperPrechargeDuration: Specifies the Tampers Pins input
+  *         Precharge Duration.
+  *   This parameter can be one of the following values:
+  *     @arg RTC_TamperPrechargeDuration_1RTCCLK: Tamper pins are pre-charged before sampling during 1 RTCCLK cycle
+  *     @arg RTC_TamperPrechargeDuration_2RTCCLK: Tamper pins are pre-charged before sampling during 2 RTCCLK cycle
+  *     @arg RTC_TamperPrechargeDuration_4RTCCLK: Tamper pins are pre-charged before sampling during 4 RTCCLK cycle    
+  *     @arg RTC_TamperPrechargeDuration_8RTCCLK: Tamper pins are pre-charged before sampling during 8 RTCCLK cycle
+  * @retval None
+  */
+void RTC_TamperPinsPrechargeDuration(uint32_t RTC_TamperPrechargeDuration)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_PRECHARGE_DURATION(RTC_TamperPrechargeDuration));
+   
+  /* Clear TAMPPRCH[1:0] bits in the RTC_TAFCR register */
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPPRCH);
+
+  /* Configure the RTC_TAFCR register */
+  RTC->TAFCR |= (uint32_t)RTC_TamperPrechargeDuration;
+}
+
+/**
+  * @brief  Enables or Disables the TimeStamp on Tamper Detection Event.
+  * @note   The timestamp is valid even the TSE bit in tamper control register 
+  *         is reset.   
+  * @param  NewState: new state of the timestamp on tamper event.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_TimeStampOnTamperDetectionCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+   
+  if (NewState != DISABLE)
+  {
+    /* Save timestamp on tamper detection event */
+    RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPTS;
+  }
+  else
+  {
+    /* Tamper detection does not cause a timestamp to be saved */
+    RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPTS;    
+  }
+}
+
+/**
+  * @brief  Enables or Disables the Precharge of Tamper pin.
+  * @param  NewState: new state of tamper pull up.
+  *   This parameter can be: ENABLE or DISABLE.                   
+  * @retval None
+  */
+void RTC_TamperPullUpCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+ if (NewState != DISABLE)
+  {
+    /* Enable precharge of the selected Tamper pin */
+    RTC->TAFCR &= (uint32_t)~RTC_TAFCR_TAMPPUDIS; 
+  }
+  else
+  {
+    /* Disable precharge of the selected Tamper pin */
+    RTC->TAFCR |= (uint32_t)RTC_TAFCR_TAMPPUDIS;    
+  } 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group10 Backup Data Registers configuration functions
+ *  @brief   Backup Data Registers configuration functions  
+ *
+@verbatim   
+ ===============================================================================
+                       Backup Data Registers configuration functions 
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Writes a data in a specified RTC Backup data register.
+  * @param  RTC_BKP_DR: RTC Backup data Register number.
+  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
+  *                          specify the register.
+  * @param  Data: Data to be written in the specified RTC Backup data register.                     
+  * @retval None
+  */
+void RTC_WriteBackupRegister(uint32_t RTC_BKP_DR, uint32_t Data)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_BKP(RTC_BKP_DR));
+
+  tmp = RTC_BASE + 0x50;
+  tmp += (RTC_BKP_DR * 4);
+
+  /* Write the specified register */
+  *(__IO uint32_t *)tmp = (uint32_t)Data;
+}
+
+/**
+  * @brief  Reads data from the specified RTC Backup data Register.
+  * @param  RTC_BKP_DR: RTC Backup data Register number.
+  *          This parameter can be: RTC_BKP_DRx where x can be from 0 to 19 to 
+  *                          specify the register.                   
+  * @retval None
+  */
+uint32_t RTC_ReadBackupRegister(uint32_t RTC_BKP_DR)
+{
+  __IO uint32_t tmp = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_BKP(RTC_BKP_DR));
+
+  tmp = RTC_BASE + 0x50;
+  tmp += (RTC_BKP_DR * 4);
+  
+  /* Read the specified register */
+  return (*(__IO uint32_t *)tmp);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group11 RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration functions
+ *  @brief   RTC Tamper and TimeStamp Pins Selection and Output Type Config 
+ *           configuration functions  
+ *
+@verbatim   
+ ===============================================================================
+  RTC Tamper and TimeStamp Pins Selection and Output Type Config configuration 
+  functions 
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Selects the RTC Tamper Pin.
+  * @param  RTC_TamperPin: specifies the RTC Tamper Pin.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_TamperPin_PC13: PC13 is selected as RTC Tamper Pin.
+  *            @arg RTC_TamperPin_PI8: PI8 is selected as RTC Tamper Pin.    
+  * @retval None
+  */
+void RTC_TamperPinSelection(uint32_t RTC_TamperPin)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TAMPER_PIN(RTC_TamperPin));
+  
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TAMPINSEL);
+  RTC->TAFCR |= (uint32_t)(RTC_TamperPin);  
+}
+
+/**
+  * @brief  Selects the RTC TimeStamp Pin.
+  * @param  RTC_TimeStampPin: specifies the RTC TimeStamp Pin.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_TimeStampPin_PC13: PC13 is selected as RTC TimeStamp Pin.
+  *            @arg RTC_TimeStampPin_PI8: PI8 is selected as RTC TimeStamp Pin.    
+  * @retval None
+  */
+void RTC_TimeStampPinSelection(uint32_t RTC_TimeStampPin)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_TIMESTAMP_PIN(RTC_TimeStampPin));
+  
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_TSINSEL);
+  RTC->TAFCR |= (uint32_t)(RTC_TimeStampPin);  
+}
+
+/**
+  * @brief  Configures the RTC Output Pin mode. 
+  * @param  RTC_OutputType: specifies the RTC Output (PC13) pin mode.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_OutputType_OpenDrain: RTC Output (PC13) is configured in 
+  *                                    Open Drain mode.
+  *            @arg RTC_OutputType_PushPull:  RTC Output (PC13) is configured in 
+  *                                    Push Pull mode.    
+  * @retval None
+  */
+void RTC_OutputTypeConfig(uint32_t RTC_OutputType)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_OUTPUT_TYPE(RTC_OutputType));
+  
+  RTC->TAFCR &= (uint32_t)~(RTC_TAFCR_ALARMOUTTYPE);
+  RTC->TAFCR |= (uint32_t)(RTC_OutputType);  
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group12 Shift control synchronisation functions
+ *  @brief   Shift control synchronisation functions 
+ *
+@verbatim   
+ ===============================================================================
+                   Shift control synchronisation functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the Synchronization Shift Control Settings.
+  * @note   When REFCKON is set, firmware must not write to Shift control register 
+  * @param  RTC_ShiftAdd1S : Select to add or not 1 second to the time Calendar.
+  *   This parameter can be one of the following values :
+  *     @arg RTC_ShiftAdd1S_Set  : Add one second to the clock calendar. 
+  *     @arg RTC_ShiftAdd1S_Reset: No effect.
+  * @param  RTC_ShiftSubFS: Select the number of Second Fractions to Substitute.
+  *         This parameter can be one any value from 0 to 0x7FFF.
+  * @retval An ErrorStatus enumeration value:
+  *          - SUCCESS: RTC Shift registers are configured
+  *          - ERROR: RTC Shift registers are not configured
+*/
+ErrorStatus RTC_SynchroShiftConfig(uint32_t RTC_ShiftAdd1S, uint32_t RTC_ShiftSubFS)
+{
+  ErrorStatus status = ERROR;
+  uint32_t shpfcount = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_SHIFT_ADD1S(RTC_ShiftAdd1S));
+  assert_param(IS_RTC_SHIFT_SUBFS(RTC_ShiftSubFS));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+  
+  /* Check if a Shift is pending*/
+  if ((RTC->ISR & RTC_ISR_SHPF) != RESET)
+  {
+    /* Wait until the shift is completed*/
+    while (((RTC->ISR & RTC_ISR_SHPF) != RESET) && (shpfcount != SHPF_TIMEOUT))
+    {
+      shpfcount++;
+    }
+  }
+
+  /* Check if the Shift pending is completed or if there is no Shift operation at all*/
+  if ((RTC->ISR & RTC_ISR_SHPF) == RESET)
+  {
+    /* check if the reference clock detection is disabled */
+    if((RTC->CR & RTC_CR_REFCKON) == RESET)
+    {
+      /* Configure the Shift settings */
+      RTC->SHIFTR = (uint32_t)(uint32_t)(RTC_ShiftSubFS) | (uint32_t)(RTC_ShiftAdd1S);
+    
+      if(RTC_WaitForSynchro() == ERROR)
+      {
+        status = ERROR;
+      }
+      else
+      {
+        status = SUCCESS;
+      }
+    }
+    else
+    {
+      status = ERROR;
+    }
+  }
+  else
+  {
+    status = ERROR;
+  }
+
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF;
+  
+  return (ErrorStatus)(status);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup RTC_Group13 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions  
+ *
+@verbatim   
+ ===============================================================================
+                       Interrupts and flags management functions
+ ===============================================================================  
+ All RTC interrupts are connected to the EXTI controller.
+ 
+ - To enable the RTC Alarm interrupt, the following sequence is required:
+   - Configure and enable the EXTI Line 17 in interrupt mode and select the rising 
+     edge sensitivity using the EXTI_Init() function.
+   - Configure and enable the RTC_Alarm IRQ channel in the NVIC using the NVIC_Init()
+     function.
+   - Configure the RTC to generate RTC alarms (Alarm A and/or Alarm B) using
+     the RTC_SetAlarm() and RTC_AlarmCmd() functions.
+
+ - To enable the RTC Wakeup interrupt, the following sequence is required:
+   - Configure and enable the EXTI Line 22 in interrupt mode and select the rising 
+     edge sensitivity using the EXTI_Init() function.
+   - Configure and enable the RTC_WKUP IRQ channel in the NVIC using the NVIC_Init()
+     function.
+   - Configure the RTC to generate the RTC wakeup timer event using the 
+     RTC_WakeUpClockConfig(), RTC_SetWakeUpCounter() and RTC_WakeUpCmd() functions.
+
+ - To enable the RTC Tamper interrupt, the following sequence is required:
+   - Configure and enable the EXTI Line 21 in interrupt mode and select the rising 
+     edge sensitivity using the EXTI_Init() function.
+   - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()
+     function.
+   - Configure the RTC to detect the RTC tamper event using the 
+     RTC_TamperTriggerConfig() and RTC_TamperCmd() functions.
+
+ - To enable the RTC TimeStamp interrupt, the following sequence is required:
+   - Configure and enable the EXTI Line 21 in interrupt mode and select the rising 
+     edge sensitivity using the EXTI_Init() function.
+   - Configure and enable the TAMP_STAMP IRQ channel in the NVIC using the NVIC_Init()
+     function.
+   - Configure the RTC to detect the RTC time-stamp event using the 
+     RTC_TimeStampCmd() functions.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified RTC interrupts.
+  * @param  RTC_IT: specifies the RTC interrupt sources to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_IT_TS:  Time Stamp interrupt mask
+  *            @arg RTC_IT_WUT:  WakeUp Timer interrupt mask
+  *            @arg RTC_IT_ALRB:  Alarm B interrupt mask
+  *            @arg RTC_IT_ALRA:  Alarm A interrupt mask
+  *            @arg RTC_IT_TAMP: Tamper event interrupt mask
+  * @param  NewState: new state of the specified RTC interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void RTC_ITConfig(uint32_t RTC_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CONFIG_IT(RTC_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* Disable the write protection for RTC registers */
+  RTC->WPR = 0xCA;
+  RTC->WPR = 0x53;
+
+  if (NewState != DISABLE)
+  {
+    /* Configure the Interrupts in the RTC_CR register */
+    RTC->CR |= (uint32_t)(RTC_IT & ~RTC_TAFCR_TAMPIE);
+    /* Configure the Tamper Interrupt in the RTC_TAFCR */
+    RTC->TAFCR |= (uint32_t)(RTC_IT & RTC_TAFCR_TAMPIE);
+  }
+  else
+  {
+    /* Configure the Interrupts in the RTC_CR register */
+    RTC->CR &= (uint32_t)~(RTC_IT & (uint32_t)~RTC_TAFCR_TAMPIE);
+    /* Configure the Tamper Interrupt in the RTC_TAFCR */
+    RTC->TAFCR &= (uint32_t)~(RTC_IT & RTC_TAFCR_TAMPIE);
+  }
+  /* Enable the write protection for RTC registers */
+  RTC->WPR = 0xFF; 
+}
+
+/**
+  * @brief  Checks whether the specified RTC flag is set or not.
+  * @param  RTC_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
+  *            @arg RTC_FLAG_TSOVF: Time Stamp OverFlow flag
+  *            @arg RTC_FLAG_TSF: Time Stamp event flag
+  *            @arg RTC_FLAG_WUTF: WakeUp Timer flag
+  *            @arg RTC_FLAG_ALRBF: Alarm B flag
+  *            @arg RTC_FLAG_ALRAF: Alarm A flag
+  *            @arg RTC_FLAG_INITF: Initialization mode flag
+  *            @arg RTC_FLAG_RSF: Registers Synchronized flag
+  *            @arg RTC_FLAG_INITS: Registers Configured flag
+  *            @arg RTC_FLAG_WUTWF: WakeUp Timer Write flag
+  *            @arg RTC_FLAG_ALRBWF: Alarm B Write flag
+  *            @arg RTC_FLAG_ALRAWF: Alarm A write flag
+  * @retval The new state of RTC_FLAG (SET or RESET).
+  */
+FlagStatus RTC_GetFlagStatus(uint32_t RTC_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_RTC_GET_FLAG(RTC_FLAG));
+  
+  /* Get all the flags */
+  tmpreg = (uint32_t)(RTC->ISR & RTC_FLAGS_MASK);
+  
+  /* Return the status of the flag */
+  if ((tmpreg & RTC_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RTC's pending flags.
+  * @param  RTC_FLAG: specifies the RTC flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_FLAG_TAMP1F: Tamper 1 event flag
+  *            @arg RTC_FLAG_TSOVF: Time Stamp Overflow flag 
+  *            @arg RTC_FLAG_TSF: Time Stamp event flag
+  *            @arg RTC_FLAG_WUTF: WakeUp Timer flag
+  *            @arg RTC_FLAG_ALRBF: Alarm B flag
+  *            @arg RTC_FLAG_ALRAF: Alarm A flag
+  *            @arg RTC_FLAG_RSF: Registers Synchronized flag
+  * @retval None
+  */
+void RTC_ClearFlag(uint32_t RTC_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_RTC_CLEAR_FLAG(RTC_FLAG));
+
+  /* Clear the Flags in the RTC_ISR register */
+  RTC->ISR = (uint32_t)((uint32_t)(~((RTC_FLAG | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT)));  
+}
+
+/**
+  * @brief  Checks whether the specified RTC interrupt has occurred or not.
+  * @param  RTC_IT: specifies the RTC interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg RTC_IT_TS: Time Stamp interrupt 
+  *            @arg RTC_IT_WUT: WakeUp Timer interrupt 
+  *            @arg RTC_IT_ALRB: Alarm B interrupt 
+  *            @arg RTC_IT_ALRA: Alarm A interrupt 
+  *            @arg RTC_IT_TAMP1: Tamper 1 event interrupt 
+  * @retval The new state of RTC_IT (SET or RESET).
+  */
+ITStatus RTC_GetITStatus(uint32_t RTC_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint32_t tmpreg = 0, enablestatus = 0;
+ 
+  /* Check the parameters */
+  assert_param(IS_RTC_GET_IT(RTC_IT));
+  
+  /* Get the TAMPER Interrupt enable bit and pending bit */
+  tmpreg = (uint32_t)(RTC->TAFCR & (RTC_TAFCR_TAMPIE));
+ 
+  /* Get the Interrupt enable Status */
+  enablestatus = (uint32_t)((RTC->CR & RTC_IT) | (tmpreg & (RTC_IT >> 15)));
+  
+  /* Get the Interrupt pending bit */
+  tmpreg = (uint32_t)((RTC->ISR & (uint32_t)(RTC_IT >> 4)));
+  
+  /* Get the status of the Interrupt */
+  if ((enablestatus != (uint32_t)RESET) && ((tmpreg & 0x0000FFFF) != (uint32_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the RTC's interrupt pending bits.
+  * @param  RTC_IT: specifies the RTC interrupt pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg RTC_IT_TS: Time Stamp interrupt 
+  *            @arg RTC_IT_WUT: WakeUp Timer interrupt 
+  *            @arg RTC_IT_ALRB: Alarm B interrupt 
+  *            @arg RTC_IT_ALRA: Alarm A interrupt 
+  *            @arg RTC_IT_TAMP1: Tamper 1 event interrupt 
+  * @retval None
+  */
+void RTC_ClearITPendingBit(uint32_t RTC_IT)
+{
+  uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_RTC_CLEAR_IT(RTC_IT));
+
+  /* Get the RTC_ISR Interrupt pending bits mask */
+  tmpreg = (uint32_t)(RTC_IT >> 4);
+
+  /* Clear the interrupt pending bits in the RTC_ISR register */
+  RTC->ISR = (uint32_t)((uint32_t)(~((tmpreg | RTC_ISR_INIT)& 0x0000FFFF) | (uint32_t)(RTC->ISR & RTC_ISR_INIT))); 
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @brief  Converts a 2 digit decimal to BCD format.
+  * @param  Value: Byte to be converted.
+  * @retval Converted byte
+  */
+static uint8_t RTC_ByteToBcd2(uint8_t Value)
+{
+  uint8_t bcdhigh = 0;
+  
+  while (Value >= 10)
+  {
+    bcdhigh++;
+    Value -= 10;
+  }
+  
+  return  ((uint8_t)(bcdhigh << 4) | Value);
+}
+
+/**
+  * @brief  Convert from 2 digit BCD to Binary.
+  * @param  Value: BCD value to be converted.
+  * @retval Converted word
+  */
+static uint8_t RTC_Bcd2ToByte(uint8_t Value)
+{
+  uint8_t tmp = 0;
+  tmp = ((uint8_t)(Value & (uint8_t)0xF0) >> (uint8_t)0x4) * 10;
+  return (tmp + (Value & (uint8_t)0x0F));
+}
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c
new file mode 100644
index 0000000000..7a00bc74b6
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_sdio.c
@@ -0,0 +1,1004 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_sdio.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Secure digital input/output interface (SDIO) 
+  *          peripheral:
+  *           - Initialization and Configuration
+  *           - Command path state machine (CPSM) management
+  *           - Data path state machine (DPSM) management
+  *           - SDIO IO Cards mode management
+  *           - CE-ATA mode management
+  *           - DMA transfers management
+  *           - Interrupts and flags management
+  *
+  *  @verbatim
+  *
+  *
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *          1. The SDIO clock (SDIOCLK = 48 MHz) is coming from a specific output
+  *             of PLL (PLL48CLK). Before to start working with SDIO peripheral
+  *             make sure that the PLL is well configured.
+  *          The SDIO peripheral uses two clock signals:
+  *              - SDIO adapter clock (SDIOCLK = 48 MHz)
+  *              - APB2 bus clock (PCLK2)
+  *          PCLK2 and SDIO_CK clock frequencies must respect the following condition:
+  *                   Frequenc(PCLK2) >= (3 / 8 x Frequency(SDIO_CK))
+  *
+  *          2. Enable peripheral clock using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SDIO, ENABLE).
+  *
+  *          3.  According to the SDIO mode, enable the GPIO clocks using 
+  *              RCC_AHB1PeriphClockCmd() function. 
+  *              The I/O can be one of the following configurations:
+  *                 - 1-bit data length: SDIO_CMD, SDIO_CK and D0.
+  *                 - 4-bit data length: SDIO_CMD, SDIO_CK and D[3:0].
+  *                 - 8-bit data length: SDIO_CMD, SDIO_CK and D[7:0].      
+  *
+  *          4. Peripheral's alternate function: 
+  *                 - Connect the pin to the desired peripherals' Alternate 
+  *                   Function (AF) using GPIO_PinAFConfig() function
+  *                 - Configure the desired pin in alternate function by:
+  *                   GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+  *                 - Select the type, pull-up/pull-down and output speed via 
+  *                   GPIO_PuPd, GPIO_OType and GPIO_Speed members
+  *                 - Call GPIO_Init() function
+  *
+  *          5. Program the Clock Edge, Clock Bypass, Clock Power Save, Bus Wide, 
+  *             hardware, flow control and the Clock Divider using the SDIO_Init()
+  *             function.
+  *
+  *          6. Enable the Power ON State using the SDIO_SetPowerState(SDIO_PowerState_ON) 
+  *             function.
+  *              
+  *          7. Enable the clock using the SDIO_ClockCmd() function.
+  *
+  *          8. Enable the NVIC and the corresponding interrupt using the function 
+  *             SDIO_ITConfig() if you need to use interrupt mode. 
+  *
+  *          9. When using the DMA mode 
+  *                   - Configure the DMA using DMA_Init() function
+  *                   - Active the needed channel Request using SDIO_DMACmd() function
+  *
+  *          10. Enable the DMA using the DMA_Cmd() function, when using DMA mode. 
+  *
+  *          11. To control the CPSM (Command Path State Machine) and send 
+  *              commands to the card use the SDIO_SendCommand(), 
+  *              SDIO_GetCommandResponse() and SDIO_GetResponse() functions.     
+  *              First, user has to fill the command structure (pointer to
+  *              SDIO_CmdInitTypeDef) according to the selected command to be sent.
+  *                 The parameters that should be filled are:
+  *                   - Command Argument
+  *                   - Command Index
+  *                   - Command Response type
+  *                   - Command Wait
+  *                   - CPSM Status (Enable or Disable)
+  *
+  *              To check if the command is well received, read the SDIO_CMDRESP
+  *              register using the SDIO_GetCommandResponse().
+  *              The SDIO responses registers (SDIO_RESP1 to SDIO_RESP2), use the
+  *              SDIO_GetResponse() function.
+  *
+  *          12. To control the DPSM (Data Path State Machine) and send/receive 
+  *              data to/from the card use the SDIO_DataConfig(), SDIO_GetDataCounter(), 
+  *              SDIO_ReadData(), SDIO_WriteData() and SDIO_GetFIFOCount() functions.
+  *
+  *              Read Operations
+  *              ---------------
+  *              a) First, user has to fill the data structure (pointer to
+  *                 SDIO_DataInitTypeDef) according to the selected data type to
+  *                 be received.
+  *                 The parameters that should be filled are:
+  *                   - Data TimeOut
+  *                   - Data Length
+  *                   - Data Block size
+  *                   - Data Transfer direction: should be from card (To SDIO)
+  *                   - Data Transfer mode
+  *                   - DPSM Status (Enable or Disable)
+  *                                   
+  *              b) Configure the SDIO resources to receive the data from the card
+  *                 according to selected transfer mode (Refer to Step 8, 9 and 10).
+  *
+  *              c) Send the selected Read command (refer to step 11).
+  *                  
+  *              d) Use the SDIO flags/interrupts to check the transfer status.
+  *
+  *              Write Operations
+  *              ---------------
+  *              a) First, user has to fill the data structure (pointer to
+  *                 SDIO_DataInitTypeDef) according to the selected data type to
+  *                 be received.
+  *                 The parameters that should be filled are:
+  *                   - Data TimeOut
+  *                   - Data Length
+  *                   - Data Block size
+  *                   - Data Transfer direction:  should be to card (To CARD)
+  *                   - Data Transfer mode
+  *                   - DPSM Status (Enable or Disable)
+  *
+  *              b) Configure the SDIO resources to send the data to the card
+  *                 according to selected transfer mode (Refer to Step 8, 9 and 10).
+  *                   
+  *              c) Send the selected Write command (refer to step 11).
+  *                  
+  *              d) Use the SDIO flags/interrupts to check the transfer status.
+  *
+  *
+  *  @endverbatim
+  *
+  *
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_sdio.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SDIO 
+  * @brief SDIO driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* ------------ SDIO registers bit address in the alias region ----------- */
+#define SDIO_OFFSET                (SDIO_BASE - PERIPH_BASE)
+
+/* --- CLKCR Register ---*/
+/* Alias word address of CLKEN bit */
+#define CLKCR_OFFSET              (SDIO_OFFSET + 0x04)
+#define CLKEN_BitNumber           0x08
+#define CLKCR_CLKEN_BB            (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4))
+
+/* --- CMD Register ---*/
+/* Alias word address of SDIOSUSPEND bit */
+#define CMD_OFFSET                (SDIO_OFFSET + 0x0C)
+#define SDIOSUSPEND_BitNumber     0x0B
+#define CMD_SDIOSUSPEND_BB        (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4))
+
+/* Alias word address of ENCMDCOMPL bit */
+#define ENCMDCOMPL_BitNumber      0x0C
+#define CMD_ENCMDCOMPL_BB         (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4))
+
+/* Alias word address of NIEN bit */
+#define NIEN_BitNumber            0x0D
+#define CMD_NIEN_BB               (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4))
+
+/* Alias word address of ATACMD bit */
+#define ATACMD_BitNumber          0x0E
+#define CMD_ATACMD_BB             (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4))
+
+/* --- DCTRL Register ---*/
+/* Alias word address of DMAEN bit */
+#define DCTRL_OFFSET              (SDIO_OFFSET + 0x2C)
+#define DMAEN_BitNumber           0x03
+#define DCTRL_DMAEN_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4))
+
+/* Alias word address of RWSTART bit */
+#define RWSTART_BitNumber         0x08
+#define DCTRL_RWSTART_BB          (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4))
+
+/* Alias word address of RWSTOP bit */
+#define RWSTOP_BitNumber          0x09
+#define DCTRL_RWSTOP_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4))
+
+/* Alias word address of RWMOD bit */
+#define RWMOD_BitNumber           0x0A
+#define DCTRL_RWMOD_BB            (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4))
+
+/* Alias word address of SDIOEN bit */
+#define SDIOEN_BitNumber          0x0B
+#define DCTRL_SDIOEN_BB           (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4))
+
+/* ---------------------- SDIO registers bit mask ------------------------ */
+/* --- CLKCR Register ---*/
+/* CLKCR register clear mask */
+#define CLKCR_CLEAR_MASK         ((uint32_t)0xFFFF8100) 
+
+/* --- PWRCTRL Register ---*/
+/* SDIO PWRCTRL Mask */
+#define PWR_PWRCTRL_MASK         ((uint32_t)0xFFFFFFFC)
+
+/* --- DCTRL Register ---*/
+/* SDIO DCTRL Clear Mask */
+#define DCTRL_CLEAR_MASK         ((uint32_t)0xFFFFFF08)
+
+/* --- CMD Register ---*/
+/* CMD Register clear mask */
+#define CMD_CLEAR_MASK           ((uint32_t)0xFFFFF800)
+
+/* SDIO RESP Registers Address */
+#define SDIO_RESP_ADDR           ((uint32_t)(SDIO_BASE + 0x14))
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SDIO_Private_Functions
+  * @{
+  */
+
+/** @defgroup SDIO_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                 Initialization and Configuration functions
+ ===============================================================================
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the SDIO peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void SDIO_DeInit(void)
+{
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, ENABLE);
+  RCC_APB2PeriphResetCmd(RCC_APB2Periph_SDIO, DISABLE);
+}
+
+/**
+  * @brief  Initializes the SDIO peripheral according to the specified 
+  *         parameters in the SDIO_InitStruct.
+  * @param  SDIO_InitStruct : pointer to a SDIO_InitTypeDef structure 
+  *         that contains the configuration information for the SDIO peripheral.
+  * @retval None
+  */
+void SDIO_Init(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+  uint32_t tmpreg = 0;
+    
+  /* Check the parameters */
+  assert_param(IS_SDIO_CLOCK_EDGE(SDIO_InitStruct->SDIO_ClockEdge));
+  assert_param(IS_SDIO_CLOCK_BYPASS(SDIO_InitStruct->SDIO_ClockBypass));
+  assert_param(IS_SDIO_CLOCK_POWER_SAVE(SDIO_InitStruct->SDIO_ClockPowerSave));
+  assert_param(IS_SDIO_BUS_WIDE(SDIO_InitStruct->SDIO_BusWide));
+  assert_param(IS_SDIO_HARDWARE_FLOW_CONTROL(SDIO_InitStruct->SDIO_HardwareFlowControl)); 
+   
+/*---------------------------- SDIO CLKCR Configuration ------------------------*/  
+  /* Get the SDIO CLKCR value */
+  tmpreg = SDIO->CLKCR;
+  
+  /* Clear CLKDIV, PWRSAV, BYPASS, WIDBUS, NEGEDGE, HWFC_EN bits */
+  tmpreg &= CLKCR_CLEAR_MASK;
+  
+  /* Set CLKDIV bits according to SDIO_ClockDiv value */
+  /* Set PWRSAV bit according to SDIO_ClockPowerSave value */
+  /* Set BYPASS bit according to SDIO_ClockBypass value */
+  /* Set WIDBUS bits according to SDIO_BusWide value */
+  /* Set NEGEDGE bits according to SDIO_ClockEdge value */
+  /* Set HWFC_EN bits according to SDIO_HardwareFlowControl value */
+  tmpreg |= (SDIO_InitStruct->SDIO_ClockDiv  | SDIO_InitStruct->SDIO_ClockPowerSave |
+             SDIO_InitStruct->SDIO_ClockBypass | SDIO_InitStruct->SDIO_BusWide |
+             SDIO_InitStruct->SDIO_ClockEdge | SDIO_InitStruct->SDIO_HardwareFlowControl); 
+  
+  /* Write to SDIO CLKCR */
+  SDIO->CLKCR = tmpreg;
+}
+
+/**
+  * @brief  Fills each SDIO_InitStruct member with its default value.
+  * @param  SDIO_InitStruct: pointer to an SDIO_InitTypeDef structure which 
+  *         will be initialized.
+  * @retval None
+  */
+void SDIO_StructInit(SDIO_InitTypeDef* SDIO_InitStruct)
+{
+  /* SDIO_InitStruct members default value */
+  SDIO_InitStruct->SDIO_ClockDiv = 0x00;
+  SDIO_InitStruct->SDIO_ClockEdge = SDIO_ClockEdge_Rising;
+  SDIO_InitStruct->SDIO_ClockBypass = SDIO_ClockBypass_Disable;
+  SDIO_InitStruct->SDIO_ClockPowerSave = SDIO_ClockPowerSave_Disable;
+  SDIO_InitStruct->SDIO_BusWide = SDIO_BusWide_1b;
+  SDIO_InitStruct->SDIO_HardwareFlowControl = SDIO_HardwareFlowControl_Disable;
+}
+
+/**
+  * @brief  Enables or disables the SDIO Clock.
+  * @param  NewState: new state of the SDIO Clock. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_ClockCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CLKCR_CLKEN_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Sets the power status of the controller.
+  * @param  SDIO_PowerState: new state of the Power state. 
+  *          This parameter can be one of the following values:
+  *            @arg SDIO_PowerState_OFF: SDIO Power OFF
+  *            @arg SDIO_PowerState_ON: SDIO Power ON
+  * @retval None
+  */
+void SDIO_SetPowerState(uint32_t SDIO_PowerState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_POWER_STATE(SDIO_PowerState));
+  
+  SDIO->POWER = SDIO_PowerState;
+}
+
+/**
+  * @brief  Gets the power status of the controller.
+  * @param  None
+  * @retval Power status of the controller. The returned value can be one of the 
+  *         following values:
+  *            - 0x00: Power OFF
+  *            - 0x02: Power UP
+  *            - 0x03: Power ON 
+  */
+uint32_t SDIO_GetPowerState(void)
+{
+  return (SDIO->POWER & (~PWR_PWRCTRL_MASK));
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Group2 Command path state machine (CPSM) management functions
+ *  @brief   Command path state machine (CPSM) management functions 
+ *
+@verbatim   
+ ===============================================================================
+              Command path state machine (CPSM) management functions
+ ===============================================================================  
+
+  This section provide functions allowing to program and read the Command path 
+  state machine (CPSM).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the SDIO Command according to the specified 
+  *         parameters in the SDIO_CmdInitStruct and send the command.
+  * @param  SDIO_CmdInitStruct : pointer to a SDIO_CmdInitTypeDef 
+  *         structure that contains the configuration information for the SDIO 
+  *         command.
+  * @retval None
+  */
+void SDIO_SendCommand(SDIO_CmdInitTypeDef *SDIO_CmdInitStruct)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_SDIO_CMD_INDEX(SDIO_CmdInitStruct->SDIO_CmdIndex));
+  assert_param(IS_SDIO_RESPONSE(SDIO_CmdInitStruct->SDIO_Response));
+  assert_param(IS_SDIO_WAIT(SDIO_CmdInitStruct->SDIO_Wait));
+  assert_param(IS_SDIO_CPSM(SDIO_CmdInitStruct->SDIO_CPSM));
+  
+/*---------------------------- SDIO ARG Configuration ------------------------*/
+  /* Set the SDIO Argument value */
+  SDIO->ARG = SDIO_CmdInitStruct->SDIO_Argument;
+  
+/*---------------------------- SDIO CMD Configuration ------------------------*/  
+  /* Get the SDIO CMD value */
+  tmpreg = SDIO->CMD;
+  /* Clear CMDINDEX, WAITRESP, WAITINT, WAITPEND, CPSMEN bits */
+  tmpreg &= CMD_CLEAR_MASK;
+  /* Set CMDINDEX bits according to SDIO_CmdIndex value */
+  /* Set WAITRESP bits according to SDIO_Response value */
+  /* Set WAITINT and WAITPEND bits according to SDIO_Wait value */
+  /* Set CPSMEN bits according to SDIO_CPSM value */
+  tmpreg |= (uint32_t)SDIO_CmdInitStruct->SDIO_CmdIndex | SDIO_CmdInitStruct->SDIO_Response
+           | SDIO_CmdInitStruct->SDIO_Wait | SDIO_CmdInitStruct->SDIO_CPSM;
+  
+  /* Write to SDIO CMD */
+  SDIO->CMD = tmpreg;
+}
+
+/**
+  * @brief  Fills each SDIO_CmdInitStruct member with its default value.
+  * @param  SDIO_CmdInitStruct: pointer to an SDIO_CmdInitTypeDef 
+  *         structure which will be initialized.
+  * @retval None
+  */
+void SDIO_CmdStructInit(SDIO_CmdInitTypeDef* SDIO_CmdInitStruct)
+{
+  /* SDIO_CmdInitStruct members default value */
+  SDIO_CmdInitStruct->SDIO_Argument = 0x00;
+  SDIO_CmdInitStruct->SDIO_CmdIndex = 0x00;
+  SDIO_CmdInitStruct->SDIO_Response = SDIO_Response_No;
+  SDIO_CmdInitStruct->SDIO_Wait = SDIO_Wait_No;
+  SDIO_CmdInitStruct->SDIO_CPSM = SDIO_CPSM_Disable;
+}
+
+/**
+  * @brief  Returns command index of last command for which response received.
+  * @param  None
+  * @retval Returns the command index of the last command response received.
+  */
+uint8_t SDIO_GetCommandResponse(void)
+{
+  return (uint8_t)(SDIO->RESPCMD);
+}
+
+/**
+  * @brief  Returns response received from the card for the last command.
+  * @param  SDIO_RESP: Specifies the SDIO response register. 
+  *          This parameter can be one of the following values:
+  *            @arg SDIO_RESP1: Response Register 1
+  *            @arg SDIO_RESP2: Response Register 2
+  *            @arg SDIO_RESP3: Response Register 3
+  *            @arg SDIO_RESP4: Response Register 4
+  * @retval The Corresponding response register value.
+  */
+uint32_t SDIO_GetResponse(uint32_t SDIO_RESP)
+{
+  __IO uint32_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SDIO_RESP(SDIO_RESP));
+
+  tmp = SDIO_RESP_ADDR + SDIO_RESP;
+  
+  return (*(__IO uint32_t *) tmp); 
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Group3 Data path state machine (DPSM) management functions
+ *  @brief   Data path state machine (DPSM) management functions
+ *
+@verbatim   
+ ===============================================================================
+              Data path state machine (DPSM) management functions
+ ===============================================================================  
+
+  This section provide functions allowing to program and read the Data path 
+  state machine (DPSM).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the SDIO data path according to the specified 
+  *         parameters in the SDIO_DataInitStruct.
+  * @param  SDIO_DataInitStruct : pointer to a SDIO_DataInitTypeDef structure 
+  *         that contains the configuration information for the SDIO command.
+  * @retval None
+  */
+void SDIO_DataConfig(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+{
+  uint32_t tmpreg = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_SDIO_DATA_LENGTH(SDIO_DataInitStruct->SDIO_DataLength));
+  assert_param(IS_SDIO_BLOCK_SIZE(SDIO_DataInitStruct->SDIO_DataBlockSize));
+  assert_param(IS_SDIO_TRANSFER_DIR(SDIO_DataInitStruct->SDIO_TransferDir));
+  assert_param(IS_SDIO_TRANSFER_MODE(SDIO_DataInitStruct->SDIO_TransferMode));
+  assert_param(IS_SDIO_DPSM(SDIO_DataInitStruct->SDIO_DPSM));
+
+/*---------------------------- SDIO DTIMER Configuration ---------------------*/
+  /* Set the SDIO Data TimeOut value */
+  SDIO->DTIMER = SDIO_DataInitStruct->SDIO_DataTimeOut;
+
+/*---------------------------- SDIO DLEN Configuration -----------------------*/
+  /* Set the SDIO DataLength value */
+  SDIO->DLEN = SDIO_DataInitStruct->SDIO_DataLength;
+
+/*---------------------------- SDIO DCTRL Configuration ----------------------*/  
+  /* Get the SDIO DCTRL value */
+  tmpreg = SDIO->DCTRL;
+  /* Clear DEN, DTMODE, DTDIR and DBCKSIZE bits */
+  tmpreg &= DCTRL_CLEAR_MASK;
+  /* Set DEN bit according to SDIO_DPSM value */
+  /* Set DTMODE bit according to SDIO_TransferMode value */
+  /* Set DTDIR bit according to SDIO_TransferDir value */
+  /* Set DBCKSIZE bits according to SDIO_DataBlockSize value */
+  tmpreg |= (uint32_t)SDIO_DataInitStruct->SDIO_DataBlockSize | SDIO_DataInitStruct->SDIO_TransferDir
+           | SDIO_DataInitStruct->SDIO_TransferMode | SDIO_DataInitStruct->SDIO_DPSM;
+
+  /* Write to SDIO DCTRL */
+  SDIO->DCTRL = tmpreg;
+}
+
+/**
+  * @brief  Fills each SDIO_DataInitStruct member with its default value.
+  * @param  SDIO_DataInitStruct: pointer to an SDIO_DataInitTypeDef structure 
+  *         which will be initialized.
+  * @retval None
+  */
+void SDIO_DataStructInit(SDIO_DataInitTypeDef* SDIO_DataInitStruct)
+{
+  /* SDIO_DataInitStruct members default value */
+  SDIO_DataInitStruct->SDIO_DataTimeOut = 0xFFFFFFFF;
+  SDIO_DataInitStruct->SDIO_DataLength = 0x00;
+  SDIO_DataInitStruct->SDIO_DataBlockSize = SDIO_DataBlockSize_1b;
+  SDIO_DataInitStruct->SDIO_TransferDir = SDIO_TransferDir_ToCard;
+  SDIO_DataInitStruct->SDIO_TransferMode = SDIO_TransferMode_Block;  
+  SDIO_DataInitStruct->SDIO_DPSM = SDIO_DPSM_Disable;
+}
+
+/**
+  * @brief  Returns number of remaining data bytes to be transferred.
+  * @param  None
+  * @retval Number of remaining data bytes to be transferred
+  */
+uint32_t SDIO_GetDataCounter(void)
+{ 
+  return SDIO->DCOUNT;
+}
+
+/**
+  * @brief  Read one data word from Rx FIFO.
+  * @param  None
+  * @retval Data received
+  */
+uint32_t SDIO_ReadData(void)
+{ 
+  return SDIO->FIFO;
+}
+
+/**
+  * @brief  Write one data word to Tx FIFO.
+  * @param  Data: 32-bit data word to write.
+  * @retval None
+  */
+void SDIO_WriteData(uint32_t Data)
+{ 
+  SDIO->FIFO = Data;
+}
+
+/**
+  * @brief  Returns the number of words left to be written to or read from FIFO.	
+  * @param  None
+  * @retval Remaining number of words.
+  */
+uint32_t SDIO_GetFIFOCount(void)
+{ 
+  return SDIO->FIFOCNT;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Group4 SDIO IO Cards mode management functions
+ *  @brief   SDIO IO Cards mode management functions
+ *
+@verbatim   
+ ===============================================================================
+              SDIO IO Cards mode management functions
+ ===============================================================================  
+
+  This section provide functions allowing to program and read the SDIO IO Cards.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Starts the SD I/O Read Wait operation.	
+  * @param  NewState: new state of the Start SDIO Read Wait operation. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_StartSDIOReadWait(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) DCTRL_RWSTART_BB = (uint32_t) NewState;
+}
+
+/**
+  * @brief  Stops the SD I/O Read Wait operation.	
+  * @param  NewState: new state of the Stop SDIO Read Wait operation. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_StopSDIOReadWait(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) DCTRL_RWSTOP_BB = (uint32_t) NewState;
+}
+
+/**
+  * @brief  Sets one of the two options of inserting read wait interval.
+  * @param  SDIO_ReadWaitMode: SD I/O Read Wait operation mode.
+  *          This parameter can be:
+  *            @arg SDIO_ReadWaitMode_CLK: Read Wait control by stopping SDIOCLK
+  *            @arg SDIO_ReadWaitMode_DATA2: Read Wait control using SDIO_DATA2
+  * @retval None
+  */
+void SDIO_SetSDIOReadWaitMode(uint32_t SDIO_ReadWaitMode)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_READWAIT_MODE(SDIO_ReadWaitMode));
+  
+  *(__IO uint32_t *) DCTRL_RWMOD_BB = SDIO_ReadWaitMode;
+}
+
+/**
+  * @brief  Enables or disables the SD I/O Mode Operation.
+  * @param  NewState: new state of SDIO specific operation. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_SetSDIOOperation(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) DCTRL_SDIOEN_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the SD I/O Mode suspend command sending.
+  * @param  NewState: new state of the SD I/O Mode suspend command.
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_SendSDIOSuspendCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CMD_SDIOSUSPEND_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Group5 CE-ATA mode management functions
+ *  @brief   CE-ATA mode management functions
+ *
+@verbatim   
+ ===============================================================================
+              CE-ATA mode management functions
+ ===============================================================================  
+
+  This section provide functions allowing to program and read the CE-ATA card.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the command completion signal.
+  * @param  NewState: new state of command completion signal. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_CommandCompletionCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CMD_ENCMDCOMPL_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Enables or disables the CE-ATA interrupt.
+  * @param  NewState: new state of CE-ATA interrupt. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_CEATAITCmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CMD_NIEN_BB = (uint32_t)((~((uint32_t)NewState)) & ((uint32_t)0x1));
+}
+
+/**
+  * @brief  Sends CE-ATA command (CMD61).
+  * @param  NewState: new state of CE-ATA command. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_SendCEATACmd(FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) CMD_ATACMD_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Group6 DMA transfers management functions
+ *  @brief   DMA transfers management functions
+ *
+@verbatim   
+ ===============================================================================
+              DMA transfers management functions
+ ===============================================================================  
+
+  This section provide functions allowing to program SDIO DMA transfer.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the SDIO DMA request.
+  * @param  NewState: new state of the selected SDIO DMA request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SDIO_DMACmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  *(__IO uint32_t *) DCTRL_DMAEN_BB = (uint32_t)NewState;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SDIO_Group7 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions  
+ *
+@verbatim   
+ ===============================================================================
+                       Interrupts and flags management functions
+ ===============================================================================  
+
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the SDIO interrupts.
+  * @param  SDIO_IT: specifies the SDIO interrupt sources to be enabled or disabled.
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                                   bus mode interrupt
+  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+  * @param  NewState: new state of the specified SDIO interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None 
+  */
+void SDIO_ITConfig(uint32_t SDIO_IT, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SDIO_IT(SDIO_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the SDIO interrupts */
+    SDIO->MASK |= SDIO_IT;
+  }
+  else
+  {
+    /* Disable the SDIO interrupts */
+    SDIO->MASK &= ~SDIO_IT;
+  } 
+}
+
+/**
+  * @brief  Checks whether the specified SDIO flag is set or not.
+  * @param  SDIO_FLAG: specifies the flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode.
+  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDIO_FLAG_CMDACT:   Command transfer in progress
+  *            @arg SDIO_FLAG_TXACT:    Data transmit in progress
+  *            @arg SDIO_FLAG_RXACT:    Data receive in progress
+  *            @arg SDIO_FLAG_TXFIFOHE: Transmit FIFO Half Empty
+  *            @arg SDIO_FLAG_RXFIFOHF: Receive FIFO Half Full
+  *            @arg SDIO_FLAG_TXFIFOF:  Transmit FIFO full
+  *            @arg SDIO_FLAG_RXFIFOF:  Receive FIFO full
+  *            @arg SDIO_FLAG_TXFIFOE:  Transmit FIFO empty
+  *            @arg SDIO_FLAG_RXFIFOE:  Receive FIFO empty
+  *            @arg SDIO_FLAG_TXDAVL:   Data available in transmit FIFO
+  *            @arg SDIO_FLAG_RXDAVL:   Data available in receive FIFO
+  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
+  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+  * @retval The new state of SDIO_FLAG (SET or RESET).
+  */
+FlagStatus SDIO_GetFlagStatus(uint32_t SDIO_FLAG)
+{ 
+  FlagStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_SDIO_FLAG(SDIO_FLAG));
+  
+  if ((SDIO->STA & SDIO_FLAG) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the SDIO's pending flags.
+  * @param  SDIO_FLAG: specifies the flag to clear.  
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDIO_FLAG_CCRCFAIL: Command response received (CRC check failed)
+  *            @arg SDIO_FLAG_DCRCFAIL: Data block sent/received (CRC check failed)
+  *            @arg SDIO_FLAG_CTIMEOUT: Command response timeout
+  *            @arg SDIO_FLAG_DTIMEOUT: Data timeout
+  *            @arg SDIO_FLAG_TXUNDERR: Transmit FIFO underrun error
+  *            @arg SDIO_FLAG_RXOVERR:  Received FIFO overrun error
+  *            @arg SDIO_FLAG_CMDREND:  Command response received (CRC check passed)
+  *            @arg SDIO_FLAG_CMDSENT:  Command sent (no response required)
+  *            @arg SDIO_FLAG_DATAEND:  Data end (data counter, SDIDCOUNT, is zero)
+  *            @arg SDIO_FLAG_STBITERR: Start bit not detected on all data signals in wide bus mode
+  *            @arg SDIO_FLAG_DBCKEND:  Data block sent/received (CRC check passed)
+  *            @arg SDIO_FLAG_SDIOIT:   SD I/O interrupt received
+  *            @arg SDIO_FLAG_CEATAEND: CE-ATA command completion signal received for CMD61
+  * @retval None
+  */
+void SDIO_ClearFlag(uint32_t SDIO_FLAG)
+{ 
+  /* Check the parameters */
+  assert_param(IS_SDIO_CLEAR_FLAG(SDIO_FLAG));
+   
+  SDIO->ICR = SDIO_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified SDIO interrupt has occurred or not.
+  * @param  SDIO_IT: specifies the SDIO interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIDCOUNT, is zero) interrupt
+  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                                   bus mode interrupt
+  *            @arg SDIO_IT_DBCKEND:  Data block sent/received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDACT:   Command transfer in progress interrupt
+  *            @arg SDIO_IT_TXACT:    Data transmit in progress interrupt
+  *            @arg SDIO_IT_RXACT:    Data receive in progress interrupt
+  *            @arg SDIO_IT_TXFIFOHE: Transmit FIFO Half Empty interrupt
+  *            @arg SDIO_IT_RXFIFOHF: Receive FIFO Half Full interrupt
+  *            @arg SDIO_IT_TXFIFOF:  Transmit FIFO full interrupt
+  *            @arg SDIO_IT_RXFIFOF:  Receive FIFO full interrupt
+  *            @arg SDIO_IT_TXFIFOE:  Transmit FIFO empty interrupt
+  *            @arg SDIO_IT_RXFIFOE:  Receive FIFO empty interrupt
+  *            @arg SDIO_IT_TXDAVL:   Data available in transmit FIFO interrupt
+  *            @arg SDIO_IT_RXDAVL:   Data available in receive FIFO interrupt
+  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61 interrupt
+  * @retval The new state of SDIO_IT (SET or RESET).
+  */
+ITStatus SDIO_GetITStatus(uint32_t SDIO_IT)
+{ 
+  ITStatus bitstatus = RESET;
+  
+  /* Check the parameters */
+  assert_param(IS_SDIO_GET_IT(SDIO_IT));
+  if ((SDIO->STA & SDIO_IT) != (uint32_t)RESET)  
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the SDIO's interrupt pending bits.
+  * @param  SDIO_IT: specifies the interrupt pending bit to clear. 
+  *          This parameter can be one or a combination of the following values:
+  *            @arg SDIO_IT_CCRCFAIL: Command response received (CRC check failed) interrupt
+  *            @arg SDIO_IT_DCRCFAIL: Data block sent/received (CRC check failed) interrupt
+  *            @arg SDIO_IT_CTIMEOUT: Command response timeout interrupt
+  *            @arg SDIO_IT_DTIMEOUT: Data timeout interrupt
+  *            @arg SDIO_IT_TXUNDERR: Transmit FIFO underrun error interrupt
+  *            @arg SDIO_IT_RXOVERR:  Received FIFO overrun error interrupt
+  *            @arg SDIO_IT_CMDREND:  Command response received (CRC check passed) interrupt
+  *            @arg SDIO_IT_CMDSENT:  Command sent (no response required) interrupt
+  *            @arg SDIO_IT_DATAEND:  Data end (data counter, SDIO_DCOUNT, is zero) interrupt
+  *            @arg SDIO_IT_STBITERR: Start bit not detected on all data signals in wide 
+  *                                   bus mode interrupt
+  *            @arg SDIO_IT_SDIOIT:   SD I/O interrupt received interrupt
+  *            @arg SDIO_IT_CEATAEND: CE-ATA command completion signal received for CMD61
+  * @retval None
+  */
+void SDIO_ClearITPendingBit(uint32_t SDIO_IT)
+{ 
+  /* Check the parameters */
+  assert_param(IS_SDIO_CLEAR_IT(SDIO_IT));
+   
+  SDIO->ICR = SDIO_IT;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c
new file mode 100644
index 0000000000..52cbd2ac52
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_spi.c
@@ -0,0 +1,1290 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_spi.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Serial peripheral interface (SPI):           
+  *           - Initialization and Configuration
+  *           - Data transfers functions
+  *           - Hardware CRC Calculation
+  *           - DMA transfers management
+  *           - Interrupts and flags management 
+  *           
+  *  @verbatim
+  *          
+  *                    
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================        
+  *    
+  *          1. Enable peripheral clock using the following functions 
+  *             RCC_APB2PeriphClockCmd(RCC_APB2Periph_SPI1, ENABLE) for SPI1
+  *             RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI2, ENABLE) for SPI2
+  *             RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE) for SPI3.
+  *
+  *          2. Enable SCK, MOSI, MISO and NSS GPIO clocks using RCC_AHB1PeriphClockCmd()
+  *             function.
+  *             In I2S mode, if an external clock source is used then the I2S CKIN pin GPIO
+  *             clock should also be enabled.
+  *
+  *          3. Peripherals alternate function: 
+  *                 - Connect the pin to the desired peripherals' Alternate 
+  *                   Function (AF) using GPIO_PinAFConfig() function
+  *                 - Configure the desired pin in alternate function by:
+  *                   GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+  *                 - Select the type, pull-up/pull-down and output speed via 
+  *                   GPIO_PuPd, GPIO_OType and GPIO_Speed members
+  *                 - Call GPIO_Init() function
+  *              In I2S mode, if an external clock source is used then the I2S CKIN pin
+  *              should be also configured in Alternate function Push-pull pull-up mode. 
+  *        
+  *          4. Program the Polarity, Phase, First Data, Baud Rate Prescaler, Slave 
+  *             Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
+  *             function.
+  *             In I2S mode, program the Mode, Standard, Data Format, MCLK Output, Audio 
+  *             frequency and Polarity using I2S_Init() function.
+  *             For I2S mode, make sure that either:
+  *              - I2S PLL is configured using the functions RCC_I2SCLKConfig(RCC_I2S2CLKSource_PLLI2S), 
+  *                RCC_PLLI2SCmd(ENABLE) and RCC_GetFlagStatus(RCC_FLAG_PLLI2SRDY).
+  *              or 
+  *              - External clock source is configured using the function 
+  *                RCC_I2SCLKConfig(RCC_I2S2CLKSource_Ext) and after setting correctly the define constant
+  *                I2S_EXTERNAL_CLOCK_VAL in the stm32f4xx_conf.h file. 
+  *
+  *          5. Enable the NVIC and the corresponding interrupt using the function 
+  *             SPI_ITConfig() if you need to use interrupt mode. 
+  *
+  *          6. When using the DMA mode 
+  *                   - Configure the DMA using DMA_Init() function
+  *                   - Active the needed channel Request using SPI_I2S_DMACmd() function
+  * 
+  *          7. Enable the SPI using the SPI_Cmd() function or enable the I2S using
+  *             I2S_Cmd().
+  * 
+  *          8. Enable the DMA using the DMA_Cmd() function when using DMA mode. 
+  *
+  *          9. Optionally, you can enable/configure the following parameters without
+  *             re-initialization (i.e there is no need to call again SPI_Init() function):
+  *              - When bidirectional mode (SPI_Direction_1Line_Rx or SPI_Direction_1Line_Tx)
+  *                is programmed as Data direction parameter using the SPI_Init() function
+  *                it can be possible to switch between SPI_Direction_Tx or SPI_Direction_Rx
+  *                using the SPI_BiDirectionalLineConfig() function.
+  *              - When SPI_NSS_Soft is selected as Slave Select Management parameter 
+  *                using the SPI_Init() function it can be possible to manage the 
+  *                NSS internal signal using the SPI_NSSInternalSoftwareConfig() function.
+  *              - Reconfigure the data size using the SPI_DataSizeConfig() function  
+  *              - Enable or disable the SS output using the SPI_SSOutputCmd() function  
+  *          
+  *          10. To use the CRC Hardware calculation feature refer to the Peripheral 
+  *              CRC hardware Calculation subsection.
+  *   
+  *
+  *          It is possible to use SPI in I2S full duplex mode, in this case, each SPI 
+  *          peripheral is able to manage sending and receiving data simultaneously
+  *          using two data lines. Each SPI peripheral has an extended block called I2Sxext
+  *          (ie. I2S2ext for SPI2 and I2S3ext for SPI3).
+  *          The extension block is not a full SPI IP, it is used only as I2S slave to
+  *          implement full duplex mode. The extension block uses the same clock sources
+  *          as its master.          
+  *          To configure I2S full duplex you have to:
+  *            
+  *          1. Configure SPIx in I2S mode (I2S_Init() function) as described above. 
+  *           
+  *          2. Call the I2S_FullDuplexConfig() function using the same strucutre passed to  
+  *             I2S_Init() function.
+  *            
+  *          3. Call I2S_Cmd() for SPIx then for its extended block.
+  *          
+  *          4. To configure interrupts or DMA requests and to get/clear flag status, 
+  *             use I2Sxext instance for the extension block.
+  *             
+  *          Functions that can be called with I2Sxext instances are:
+  *          I2S_Cmd(), I2S_FullDuplexConfig(), SPI_I2S_ReceiveData(), SPI_I2S_SendData(), 
+  *          SPI_I2S_DMACmd(), SPI_I2S_ITConfig(), SPI_I2S_GetFlagStatus(), SPI_I2S_ClearFlag(),
+  *          SPI_I2S_GetITStatus() and SPI_I2S_ClearITPendingBit().
+  *                 
+  *          Example: To use SPI3 in Full duplex mode (SPI3 is Master Tx, I2S3ext is Slave Rx):
+  *            
+  *          RCC_APB1PeriphClockCmd(RCC_APB1Periph_SPI3, ENABLE);   
+  *          I2S_StructInit(&I2SInitStruct);
+  *          I2SInitStruct.Mode = I2S_Mode_MasterTx;     
+  *          I2S_Init(SPI3, &I2SInitStruct);
+  *          I2S_FullDuplexConfig(SPI3ext, &I2SInitStruct)
+  *          I2S_Cmd(SPI3, ENABLE);
+  *          I2S_Cmd(SPI3ext, ENABLE);
+  *          ...
+  *          while (SPI_I2S_GetFlagStatus(SPI2, SPI_FLAG_TXE) == RESET)
+  *          {}
+  *          SPI_I2S_SendData(SPI3, txdata[i]);
+  *          ...  
+  *          while (SPI_I2S_GetFlagStatus(I2S3ext, SPI_FLAG_RXNE) == RESET)
+  *          {}
+  *          rxdata[i] = SPI_I2S_ReceiveData(I2S3ext);
+  *          ...          
+  *              
+  *       
+  *    
+  * @note    This driver supports only the I2S clock scheme available in Silicon
+  *          RevisionB and RevisionY.
+  *     
+  * @note    In I2S mode: if an external clock is used as source clock for the I2S,  
+  *          then the define I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should 
+  *          be enabled and set to the value of the source clock frequency (in Hz).
+  * 
+  * @note    In SPI mode: To use the SPI TI mode, call the function SPI_TIModeCmd() 
+  *          just after calling the function SPI_Init().
+  *
+  *  @endverbatim  
+  *                                  
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************  
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_spi.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SPI 
+  * @brief SPI driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* SPI registers Masks */
+#define CR1_CLEAR_MASK            ((uint16_t)0x3040)
+#define I2SCFGR_CLEAR_MASK        ((uint16_t)0xF040)
+
+/* RCC PLLs masks */
+#define PLLCFGR_PPLR_MASK         ((uint32_t)0x70000000)
+#define PLLCFGR_PPLN_MASK         ((uint32_t)0x00007FC0)
+
+#define SPI_CR2_FRF               ((uint16_t)0x0010)
+#define SPI_SR_TIFRFE             ((uint16_t)0x0100)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SPI_Private_Functions
+  * @{
+  */
+
+/** @defgroup SPI_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                  Initialization and Configuration functions
+ ===============================================================================  
+
+  This section provides a set of functions allowing to initialize the SPI Direction,
+  SPI Mode, SPI Data Size, SPI Polarity, SPI Phase, SPI NSS Management, SPI Baud
+  Rate Prescaler, SPI First Bit and SPI CRC Polynomial.
+  
+  The SPI_Init() function follows the SPI configuration procedures for Master mode
+  and Slave mode (details for these procedures are available in reference manual
+  (RM0090)).
+  
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitialize the SPIx peripheral registers to their default reset values.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode.   
+  *         
+  * @note   The extended I2S blocks (ie. I2S2ext and I2S3ext blocks) are deinitialized
+  *         when the relative I2S peripheral is deinitialized (the extended block's clock
+  *         is managed by the I2S peripheral clock).
+  *             
+  * @retval None
+  */
+void SPI_I2S_DeInit(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+
+  if (SPIx == SPI1)
+  {
+    /* Enable SPI1 reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, ENABLE);
+    /* Release SPI1 from reset state */
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_SPI1, DISABLE);
+  }
+  else if (SPIx == SPI2)
+  {
+    /* Enable SPI2 reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, ENABLE);
+    /* Release SPI2 from reset state */
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI2, DISABLE);
+    }
+  else
+  {
+    if (SPIx == SPI3)
+    {
+      /* Enable SPI3 reset state */
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, ENABLE);
+      /* Release SPI3 from reset state */
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_SPI3, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the SPIx peripheral according to the specified 
+  *         parameters in the SPI_InitStruct.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure that
+  *         contains the configuration information for the specified SPI peripheral.
+  * @retval None
+  */
+void SPI_Init(SPI_TypeDef* SPIx, SPI_InitTypeDef* SPI_InitStruct)
+{
+  uint16_t tmpreg = 0;
+  
+  /* check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  
+  /* Check the SPI parameters */
+  assert_param(IS_SPI_DIRECTION_MODE(SPI_InitStruct->SPI_Direction));
+  assert_param(IS_SPI_MODE(SPI_InitStruct->SPI_Mode));
+  assert_param(IS_SPI_DATASIZE(SPI_InitStruct->SPI_DataSize));
+  assert_param(IS_SPI_CPOL(SPI_InitStruct->SPI_CPOL));
+  assert_param(IS_SPI_CPHA(SPI_InitStruct->SPI_CPHA));
+  assert_param(IS_SPI_NSS(SPI_InitStruct->SPI_NSS));
+  assert_param(IS_SPI_BAUDRATE_PRESCALER(SPI_InitStruct->SPI_BaudRatePrescaler));
+  assert_param(IS_SPI_FIRST_BIT(SPI_InitStruct->SPI_FirstBit));
+  assert_param(IS_SPI_CRC_POLYNOMIAL(SPI_InitStruct->SPI_CRCPolynomial));
+
+/*---------------------------- SPIx CR1 Configuration ------------------------*/
+  /* Get the SPIx CR1 value */
+  tmpreg = SPIx->CR1;
+  /* Clear BIDIMode, BIDIOE, RxONLY, SSM, SSI, LSBFirst, BR, MSTR, CPOL and CPHA bits */
+  tmpreg &= CR1_CLEAR_MASK;
+  /* Configure SPIx: direction, NSS management, first transmitted bit, BaudRate prescaler
+     master/salve mode, CPOL and CPHA */
+  /* Set BIDImode, BIDIOE and RxONLY bits according to SPI_Direction value */
+  /* Set SSM, SSI and MSTR bits according to SPI_Mode and SPI_NSS values */
+  /* Set LSBFirst bit according to SPI_FirstBit value */
+  /* Set BR bits according to SPI_BaudRatePrescaler value */
+  /* Set CPOL bit according to SPI_CPOL value */
+  /* Set CPHA bit according to SPI_CPHA value */
+  tmpreg |= (uint16_t)((uint32_t)SPI_InitStruct->SPI_Direction | SPI_InitStruct->SPI_Mode |
+                  SPI_InitStruct->SPI_DataSize | SPI_InitStruct->SPI_CPOL |  
+                  SPI_InitStruct->SPI_CPHA | SPI_InitStruct->SPI_NSS |  
+                  SPI_InitStruct->SPI_BaudRatePrescaler | SPI_InitStruct->SPI_FirstBit);
+  /* Write to SPIx CR1 */
+  SPIx->CR1 = tmpreg;
+
+  /* Activate the SPI mode (Reset I2SMOD bit in I2SCFGR register) */
+  SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SMOD);
+/*---------------------------- SPIx CRCPOLY Configuration --------------------*/
+  /* Write to SPIx CRCPOLY */
+  SPIx->CRCPR = SPI_InitStruct->SPI_CRCPolynomial;
+}
+
+/**
+  * @brief  Initializes the SPIx peripheral according to the specified 
+  *         parameters in the I2S_InitStruct.
+  * @param  SPIx: where x can be  2 or 3 to select the SPI peripheral (configured in I2S mode).
+  * @param  I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
+  *         contains the configuration information for the specified SPI peripheral
+  *         configured in I2S mode.
+  *           
+  * @note   The function calculates the optimal prescaler needed to obtain the most 
+  *         accurate audio frequency (depending on the I2S clock source, the PLL values 
+  *         and the product configuration). But in case the prescaler value is greater 
+  *         than 511, the default value (0x02) will be configured instead.    
+  * 
+  * @note   if an external clock is used as source clock for the I2S, then the define
+  *         I2S_EXTERNAL_CLOCK_VAL in file stm32f4xx_conf.h should be enabled and set
+  *         to the value of the the source clock frequency (in Hz).
+  *  
+  * @retval None
+  */
+void I2S_Init(SPI_TypeDef* SPIx, I2S_InitTypeDef* I2S_InitStruct)
+{
+  uint16_t tmpreg = 0, i2sdiv = 2, i2sodd = 0, packetlength = 1;
+  uint32_t tmp = 0, i2sclk = 0;
+#ifndef I2S_EXTERNAL_CLOCK_VAL
+  uint32_t pllm = 0, plln = 0, pllr = 0;
+#endif /* I2S_EXTERNAL_CLOCK_VAL */
+  
+  /* Check the I2S parameters */
+  assert_param(IS_SPI_23_PERIPH(SPIx));
+  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
+  assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
+  assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
+  assert_param(IS_I2S_MCLK_OUTPUT(I2S_InitStruct->I2S_MCLKOutput));
+  assert_param(IS_I2S_AUDIO_FREQ(I2S_InitStruct->I2S_AudioFreq));
+  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));  
+
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
+  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+  SPIx->I2SCFGR &= I2SCFGR_CLEAR_MASK; 
+  SPIx->I2SPR = 0x0002;
+  
+  /* Get the I2SCFGR register value */
+  tmpreg = SPIx->I2SCFGR;
+  
+  /* If the default value has to be written, reinitialize i2sdiv and i2sodd*/
+  if(I2S_InitStruct->I2S_AudioFreq == I2S_AudioFreq_Default)
+  {
+    i2sodd = (uint16_t)0;
+    i2sdiv = (uint16_t)2;   
+  }
+  /* If the requested audio frequency is not the default, compute the prescaler */
+  else
+  {
+    /* Check the frame length (For the Prescaler computing) *******************/
+    if(I2S_InitStruct->I2S_DataFormat == I2S_DataFormat_16b)
+    {
+      /* Packet length is 16 bits */
+      packetlength = 1;
+    }
+    else
+    {
+      /* Packet length is 32 bits */
+      packetlength = 2;
+    }
+
+    /* Get I2S source Clock frequency (only in Silicon RevisionB and RevisionY) */
+      
+    /* If an external I2S clock has to be used, this define should be set  
+       in the project configuration or in the stm32f4xx_conf.h file */
+  #ifdef I2S_EXTERNAL_CLOCK_VAL     
+    /* Set external clock as I2S clock source */
+    if ((RCC->CFGR & RCC_CFGR_I2SSRC) == 0)
+    {
+      RCC->CFGR |= (uint32_t)RCC_CFGR_I2SSRC;
+    }
+    
+    /* Set the I2S clock to the external clock  value */
+    i2sclk = I2S_EXTERNAL_CLOCK_VAL;
+
+  #else /* There is no define for External I2S clock source */
+    /* Set PLLI2S as I2S clock source */
+    if ((RCC->CFGR & RCC_CFGR_I2SSRC) != 0)
+    {
+      RCC->CFGR &= ~(uint32_t)RCC_CFGR_I2SSRC;
+    }    
+    
+    /* Get the PLLI2SN value */
+    plln = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SN) >> 6) & \
+                      (RCC_PLLI2SCFGR_PLLI2SN >> 6));
+    
+    /* Get the PLLI2SR value */
+    pllr = (uint32_t)(((RCC->PLLI2SCFGR & RCC_PLLI2SCFGR_PLLI2SR) >> 28) & \
+                      (RCC_PLLI2SCFGR_PLLI2SR >> 28));
+    
+    /* Get the PLLM value */
+    pllm = (uint32_t)(RCC->PLLCFGR & RCC_PLLCFGR_PLLM);      
+    
+    /* Get the I2S source clock value */
+    i2sclk = (uint32_t)(((HSE_VALUE / pllm) * plln) / pllr);
+  #endif /* I2S_EXTERNAL_CLOCK_VAL */
+    
+    /* Compute the Real divider depending on the MCLK output state, with a floating point */
+    if(I2S_InitStruct->I2S_MCLKOutput == I2S_MCLKOutput_Enable)
+    {
+      /* MCLK output is enabled */
+      tmp = (uint16_t)(((((i2sclk / 256) * 10) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+    }
+    else
+    {
+      /* MCLK output is disabled */
+      tmp = (uint16_t)(((((i2sclk / (32 * packetlength)) *10 ) / I2S_InitStruct->I2S_AudioFreq)) + 5);
+    }
+    
+    /* Remove the flatting point */
+    tmp = tmp / 10;  
+      
+    /* Check the parity of the divider */
+    i2sodd = (uint16_t)(tmp & (uint16_t)0x0001);
+   
+    /* Compute the i2sdiv prescaler */
+    i2sdiv = (uint16_t)((tmp - i2sodd) / 2);
+   
+    /* Get the Mask for the Odd bit (SPI_I2SPR[8]) register */
+    i2sodd = (uint16_t) (i2sodd << 8);
+  }
+
+  /* Test if the divider is 1 or 0 or greater than 0xFF */
+  if ((i2sdiv < 2) || (i2sdiv > 0xFF))
+  {
+    /* Set the default values */
+    i2sdiv = 2;
+    i2sodd = 0;
+  }
+
+  /* Write to SPIx I2SPR register the computed value */
+  SPIx->I2SPR = (uint16_t)((uint16_t)i2sdiv | (uint16_t)(i2sodd | (uint16_t)I2S_InitStruct->I2S_MCLKOutput));
+ 
+  /* Configure the I2S with the SPI_InitStruct values */
+  tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(I2S_InitStruct->I2S_Mode | \
+                  (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
+                  (uint16_t)I2S_InitStruct->I2S_CPOL))));
+ 
+  /* Write to SPIx I2SCFGR */  
+  SPIx->I2SCFGR = tmpreg;
+}
+
+/**
+  * @brief  Fills each SPI_InitStruct member with its default value.
+  * @param  SPI_InitStruct: pointer to a SPI_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void SPI_StructInit(SPI_InitTypeDef* SPI_InitStruct)
+{
+/*--------------- Reset SPI init structure parameters values -----------------*/
+  /* Initialize the SPI_Direction member */
+  SPI_InitStruct->SPI_Direction = SPI_Direction_2Lines_FullDuplex;
+  /* initialize the SPI_Mode member */
+  SPI_InitStruct->SPI_Mode = SPI_Mode_Slave;
+  /* initialize the SPI_DataSize member */
+  SPI_InitStruct->SPI_DataSize = SPI_DataSize_8b;
+  /* Initialize the SPI_CPOL member */
+  SPI_InitStruct->SPI_CPOL = SPI_CPOL_Low;
+  /* Initialize the SPI_CPHA member */
+  SPI_InitStruct->SPI_CPHA = SPI_CPHA_1Edge;
+  /* Initialize the SPI_NSS member */
+  SPI_InitStruct->SPI_NSS = SPI_NSS_Hard;
+  /* Initialize the SPI_BaudRatePrescaler member */
+  SPI_InitStruct->SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_2;
+  /* Initialize the SPI_FirstBit member */
+  SPI_InitStruct->SPI_FirstBit = SPI_FirstBit_MSB;
+  /* Initialize the SPI_CRCPolynomial member */
+  SPI_InitStruct->SPI_CRCPolynomial = 7;
+}
+
+/**
+  * @brief  Fills each I2S_InitStruct member with its default value.
+  * @param  I2S_InitStruct: pointer to a I2S_InitTypeDef structure which will be initialized.
+  * @retval None
+  */
+void I2S_StructInit(I2S_InitTypeDef* I2S_InitStruct)
+{
+/*--------------- Reset I2S init structure parameters values -----------------*/
+  /* Initialize the I2S_Mode member */
+  I2S_InitStruct->I2S_Mode = I2S_Mode_SlaveTx;
+  
+  /* Initialize the I2S_Standard member */
+  I2S_InitStruct->I2S_Standard = I2S_Standard_Phillips;
+  
+  /* Initialize the I2S_DataFormat member */
+  I2S_InitStruct->I2S_DataFormat = I2S_DataFormat_16b;
+  
+  /* Initialize the I2S_MCLKOutput member */
+  I2S_InitStruct->I2S_MCLKOutput = I2S_MCLKOutput_Disable;
+  
+  /* Initialize the I2S_AudioFreq member */
+  I2S_InitStruct->I2S_AudioFreq = I2S_AudioFreq_Default;
+  
+  /* Initialize the I2S_CPOL member */
+  I2S_InitStruct->I2S_CPOL = I2S_CPOL_Low;
+}
+
+/**
+  * @brief  Enables or disables the specified SPI peripheral.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx peripheral. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI peripheral */
+    SPIx->CR1 |= SPI_CR1_SPE;
+  }
+  else
+  {
+    /* Disable the selected SPI peripheral */
+    SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_SPE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the specified SPI peripheral (in I2S mode).
+  * @param  SPIx: where x can be 2 or 3 to select the SPI peripheral (or I2Sxext 
+  *         for full duplex mode).
+  * @param  NewState: new state of the SPIx peripheral. 
+  *         This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void I2S_Cmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_23_PERIPH_EXT(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI peripheral (in I2S mode) */
+    SPIx->I2SCFGR |= SPI_I2SCFGR_I2SE;
+  }
+  else
+  {
+    /* Disable the selected SPI peripheral in I2S mode */
+    SPIx->I2SCFGR &= (uint16_t)~((uint16_t)SPI_I2SCFGR_I2SE);
+  }
+}
+
+/**
+  * @brief  Configures the data size for the selected SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_DataSize: specifies the SPI data size.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_DataSize_16b: Set data frame format to 16bit
+  *            @arg SPI_DataSize_8b: Set data frame format to 8bit
+  * @retval None
+  */
+void SPI_DataSizeConfig(SPI_TypeDef* SPIx, uint16_t SPI_DataSize)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_DATASIZE(SPI_DataSize));
+  /* Clear DFF bit */
+  SPIx->CR1 &= (uint16_t)~SPI_DataSize_16b;
+  /* Set new DFF bit value */
+  SPIx->CR1 |= SPI_DataSize;
+}
+
+/**
+  * @brief  Selects the data transfer direction in bidirectional mode for the specified SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_Direction: specifies the data transfer direction in bidirectional mode. 
+  *          This parameter can be one of the following values:
+  *            @arg SPI_Direction_Tx: Selects Tx transmission direction
+  *            @arg SPI_Direction_Rx: Selects Rx receive direction
+  * @retval None
+  */
+void SPI_BiDirectionalLineConfig(SPI_TypeDef* SPIx, uint16_t SPI_Direction)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_DIRECTION(SPI_Direction));
+  if (SPI_Direction == SPI_Direction_Tx)
+  {
+    /* Set the Tx only mode */
+    SPIx->CR1 |= SPI_Direction_Tx;
+  }
+  else
+  {
+    /* Set the Rx only mode */
+    SPIx->CR1 &= SPI_Direction_Rx;
+  }
+}
+
+/**
+  * @brief  Configures internally by software the NSS pin for the selected SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_NSSInternalSoft: specifies the SPI NSS internal state.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_NSSInternalSoft_Set: Set NSS pin internally
+  *            @arg SPI_NSSInternalSoft_Reset: Reset NSS pin internally
+  * @retval None
+  */
+void SPI_NSSInternalSoftwareConfig(SPI_TypeDef* SPIx, uint16_t SPI_NSSInternalSoft)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_NSS_INTERNAL(SPI_NSSInternalSoft));
+  if (SPI_NSSInternalSoft != SPI_NSSInternalSoft_Reset)
+  {
+    /* Set NSS pin internally by software */
+    SPIx->CR1 |= SPI_NSSInternalSoft_Set;
+  }
+  else
+  {
+    /* Reset NSS pin internally by software */
+    SPIx->CR1 &= SPI_NSSInternalSoft_Reset;
+  }
+}
+
+/**
+  * @brief  Enables or disables the SS output for the selected SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx SS output. 
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_SSOutputCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI SS output */
+    SPIx->CR2 |= (uint16_t)SPI_CR2_SSOE;
+  }
+  else
+  {
+    /* Disable the selected SPI SS output */
+    SPIx->CR2 &= (uint16_t)~((uint16_t)SPI_CR2_SSOE);
+  }
+}
+
+/**
+  * @brief  Enables or disables the SPIx/I2Sx DMA interface.
+  *   
+  * @note   This function can be called only after the SPI_Init() function has 
+  *         been called. 
+  * @note   When TI mode is selected, the control bits SSM, SSI, CPOL and CPHA 
+  *         are not taken into consideration and are configured by hardware
+  *         respectively to the TI mode requirements.  
+  * 
+  * @param  SPIx: where x can be 1, 2 or 3 
+  * @param  NewState: new state of the selected SPI TI communication mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_TIModeCmd(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the TI mode for the selected SPI peripheral */
+    SPIx->CR2 |= SPI_CR2_FRF;
+  }
+  else
+  {
+    /* Disable the TI mode for the selected SPI peripheral */
+    SPIx->CR2 &= (uint16_t)~SPI_CR2_FRF;
+  }
+}
+
+/**
+  * @brief  Configures the full duplex mode for the I2Sx peripheral using its
+  *         extension I2Sxext according to the specified parameters in the 
+  *         I2S_InitStruct.
+  * @param  I2Sxext: where x can be  2 or 3 to select the I2S peripheral extension block.
+  * @param  I2S_InitStruct: pointer to an I2S_InitTypeDef structure that
+  *         contains the configuration information for the specified I2S peripheral
+  *         extension.
+  * 
+  * @note   The structure pointed by I2S_InitStruct parameter should be the same
+  *         used for the master I2S peripheral. In this case, if the master is 
+  *         configured as transmitter, the slave will be receiver and vice versa.
+  *         Or you can force a different mode by modifying the field I2S_Mode to the
+  *         value I2S_SlaveRx or I2S_SlaveTx indepedently of the master configuration.    
+  *         
+  * @note   The I2S full duplex extension can be configured in slave mode only.    
+  *  
+  * @retval None
+  */
+void I2S_FullDuplexConfig(SPI_TypeDef* I2Sxext, I2S_InitTypeDef* I2S_InitStruct)
+{
+  uint16_t tmpreg = 0, tmp = 0;
+  
+  /* Check the I2S parameters */
+  assert_param(IS_I2S_EXT_PERIPH(I2Sxext));
+  assert_param(IS_I2S_MODE(I2S_InitStruct->I2S_Mode));
+  assert_param(IS_I2S_STANDARD(I2S_InitStruct->I2S_Standard));
+  assert_param(IS_I2S_DATA_FORMAT(I2S_InitStruct->I2S_DataFormat));
+  assert_param(IS_I2S_CPOL(I2S_InitStruct->I2S_CPOL));  
+
+/*----------------------- SPIx I2SCFGR & I2SPR Configuration -----------------*/
+  /* Clear I2SMOD, I2SE, I2SCFG, PCMSYNC, I2SSTD, CKPOL, DATLEN and CHLEN bits */
+  I2Sxext->I2SCFGR &= I2SCFGR_CLEAR_MASK; 
+  I2Sxext->I2SPR = 0x0002;
+  
+  /* Get the I2SCFGR register value */
+  tmpreg = I2Sxext->I2SCFGR;
+  
+  /* Get the mode to be configured for the extended I2S */
+  if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterTx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveTx))
+  {
+    tmp = I2S_Mode_SlaveRx;
+  }
+  else
+  {
+    if ((I2S_InitStruct->I2S_Mode == I2S_Mode_MasterRx) || (I2S_InitStruct->I2S_Mode == I2S_Mode_SlaveRx))
+    {
+      tmp = I2S_Mode_SlaveTx;
+    }
+  }
+
+ 
+  /* Configure the I2S with the SPI_InitStruct values */
+  tmpreg |= (uint16_t)((uint16_t)SPI_I2SCFGR_I2SMOD | (uint16_t)(tmp | \
+                  (uint16_t)(I2S_InitStruct->I2S_Standard | (uint16_t)(I2S_InitStruct->I2S_DataFormat | \
+                  (uint16_t)I2S_InitStruct->I2S_CPOL))));
+ 
+  /* Write to SPIx I2SCFGR */  
+  I2Sxext->I2SCFGR = tmpreg;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group2 Data transfers functions
+ *  @brief   Data transfers functions
+ *
+@verbatim   
+ ===============================================================================
+                         Data transfers functions
+ ===============================================================================  
+
+  This section provides a set of functions allowing to manage the SPI data transfers
+  
+  In reception, data are received and then stored into an internal Rx buffer while 
+  In transmission, data are first stored into an internal Tx buffer before being 
+  transmitted.
+
+  The read access of the SPI_DR register can be done using the SPI_I2S_ReceiveData()
+  function and returns the Rx buffered value. Whereas a write access to the SPI_DR 
+  can be done using SPI_I2S_SendData() function and stores the written data into 
+  Tx buffer.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Returns the most recent received data by the SPIx/I2Sx peripheral. 
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. 
+  * @retval The value of the received data.
+  */
+uint16_t SPI_I2S_ReceiveData(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+  
+  /* Return the data in the DR register */
+  return SPIx->DR;
+}
+
+/**
+  * @brief  Transmits a Data through the SPIx/I2Sx peripheral.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.     
+  * @param  Data: Data to be transmitted.
+  * @retval None
+  */
+void SPI_I2S_SendData(SPI_TypeDef* SPIx, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+  
+  /* Write in the DR register the data to be sent */
+  SPIx->DR = Data;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group3 Hardware CRC Calculation functions
+ *  @brief   Hardware CRC Calculation functions
+ *
+@verbatim   
+ ===============================================================================
+                         Hardware CRC Calculation functions
+ ===============================================================================  
+
+  This section provides a set of functions allowing to manage the SPI CRC hardware 
+  calculation
+
+  SPI communication using CRC is possible through the following procedure:
+     1. Program the Data direction, Polarity, Phase, First Data, Baud Rate Prescaler, 
+        Slave Management, Peripheral Mode and CRC Polynomial values using the SPI_Init()
+        function.
+     2. Enable the CRC calculation using the SPI_CalculateCRC() function.
+     3. Enable the SPI using the SPI_Cmd() function
+     4. Before writing the last data to the TX buffer, set the CRCNext bit using the 
+      SPI_TransmitCRC() function to indicate that after transmission of the last 
+      data, the CRC should be transmitted.
+     5. After transmitting the last data, the SPI transmits the CRC. The SPI_CR1_CRCNEXT
+        bit is reset. The CRC is also received and compared against the SPI_RXCRCR 
+        value. 
+        If the value does not match, the SPI_FLAG_CRCERR flag is set and an interrupt
+        can be generated when the SPI_I2S_IT_ERR interrupt is enabled.
+
+@note It is advised not to read the calculated CRC values during the communication.
+
+@note When the SPI is in slave mode, be careful to enable CRC calculation only 
+      when the clock is stable, that is, when the clock is in the steady state. 
+      If not, a wrong CRC calculation may be done. In fact, the CRC is sensitive 
+      to the SCK slave input clock as soon as CRCEN is set, and this, whatever 
+      the value of the SPE bit.
+
+@note With high bitrate frequencies, be careful when transmitting the CRC.
+      As the number of used CPU cycles has to be as low as possible in the CRC 
+      transfer phase, it is forbidden to call software functions in the CRC 
+      transmission sequence to avoid errors in the last data and CRC reception. 
+      In fact, CRCNEXT bit has to be written before the end of the transmission/reception 
+      of the last data.
+
+@note For high bit rate frequencies, it is advised to use the DMA mode to avoid the
+      degradation of the SPI speed performance due to CPU accesses impacting the 
+      SPI bandwidth.
+
+@note When the STM32F4xx is configured as slave and the NSS hardware mode is 
+      used, the NSS pin needs to be kept low between the data phase and the CRC 
+      phase.
+
+@note When the SPI is configured in slave mode with the CRC feature enabled, CRC
+      calculation takes place even if a high level is applied on the NSS pin. 
+      This may happen for example in case of a multi-slave environment where the 
+      communication master addresses slaves alternately.
+
+@note Between a slave de-selection (high level on NSS) and a new slave selection 
+      (low level on NSS), the CRC value should be cleared on both master and slave
+      sides in order to resynchronize the master and slave for their respective 
+      CRC calculation.
+
+@note To clear the CRC, follow the procedure below:
+        1. Disable SPI using the SPI_Cmd() function
+        2. Disable the CRC calculation using the SPI_CalculateCRC() function.
+        3. Enable the CRC calculation using the SPI_CalculateCRC() function.
+        4. Enable SPI using the SPI_Cmd() function.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the CRC value calculation of the transferred bytes.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  NewState: new state of the SPIx CRC value calculation.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_CalculateCRC(SPI_TypeDef* SPIx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI CRC calculation */
+    SPIx->CR1 |= SPI_CR1_CRCEN;
+  }
+  else
+  {
+    /* Disable the selected SPI CRC calculation */
+    SPIx->CR1 &= (uint16_t)~((uint16_t)SPI_CR1_CRCEN);
+  }
+}
+
+/**
+  * @brief  Transmit the SPIx CRC value.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval None
+  */
+void SPI_TransmitCRC(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  
+  /* Enable the selected SPI CRC transmission */
+  SPIx->CR1 |= SPI_CR1_CRCNEXT;
+}
+
+/**
+  * @brief  Returns the transmit or the receive CRC register value for the specified SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @param  SPI_CRC: specifies the CRC register to be read.
+  *          This parameter can be one of the following values:
+  *            @arg SPI_CRC_Tx: Selects Tx CRC register
+  *            @arg SPI_CRC_Rx: Selects Rx CRC register
+  * @retval The selected CRC register value..
+  */
+uint16_t SPI_GetCRC(SPI_TypeDef* SPIx, uint8_t SPI_CRC)
+{
+  uint16_t crcreg = 0;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  assert_param(IS_SPI_CRC(SPI_CRC));
+  if (SPI_CRC != SPI_CRC_Rx)
+  {
+    /* Get the Tx CRC register */
+    crcreg = SPIx->TXCRCR;
+  }
+  else
+  {
+    /* Get the Rx CRC register */
+    crcreg = SPIx->RXCRCR;
+  }
+  /* Return the selected CRC register */
+  return crcreg;
+}
+
+/**
+  * @brief  Returns the CRC Polynomial register value for the specified SPI.
+  * @param  SPIx: where x can be 1, 2 or 3 to select the SPI peripheral.
+  * @retval The CRC Polynomial register value.
+  */
+uint16_t SPI_GetCRCPolynomial(SPI_TypeDef* SPIx)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH(SPIx));
+  
+  /* Return the CRC polynomial register */
+  return SPIx->CRCPR;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group4 DMA transfers management functions
+ *  @brief   DMA transfers management functions
+  *
+@verbatim   
+ ===============================================================================
+                         DMA transfers management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the SPIx/I2Sx DMA interface.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. 
+  * @param  SPI_I2S_DMAReq: specifies the SPI DMA transfer request to be enabled or disabled. 
+  *          This parameter can be any combination of the following values:
+  *            @arg SPI_I2S_DMAReq_Tx: Tx buffer DMA transfer request
+  *            @arg SPI_I2S_DMAReq_Rx: Rx buffer DMA transfer request
+  * @param  NewState: new state of the selected SPI DMA transfer request.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_SPI_I2S_DMAREQ(SPI_I2S_DMAReq));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI DMA requests */
+    SPIx->CR2 |= SPI_I2S_DMAReq;
+  }
+  else
+  {
+    /* Disable the selected SPI DMA requests */
+    SPIx->CR2 &= (uint16_t)~SPI_I2S_DMAReq;
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup SPI_Group5 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions
+  *
+@verbatim   
+ ===============================================================================
+                         Interrupts and flags management functions
+ ===============================================================================  
+
+  This section provides a set of functions allowing to configure the SPI Interrupts 
+  sources and check or clear the flags or pending bits status.
+  The user should identify which mode will be used in his application to manage 
+  the communication: Polling mode, Interrupt mode or DMA mode. 
+    
+  Polling Mode
+  =============
+  In Polling Mode, the SPI/I2S communication can be managed by 9 flags:
+     1. SPI_I2S_FLAG_TXE : to indicate the status of the transmit buffer register
+     2. SPI_I2S_FLAG_RXNE : to indicate the status of the receive buffer register
+     3. SPI_I2S_FLAG_BSY : to indicate the state of the communication layer of the SPI.
+     4. SPI_FLAG_CRCERR : to indicate if a CRC Calculation error occur              
+     5. SPI_FLAG_MODF : to indicate if a Mode Fault error occur
+     6. SPI_I2S_FLAG_OVR : to indicate if an Overrun error occur
+     7. I2S_FLAG_TIFRFE: to indicate a Frame Format error occurs.
+     8. I2S_FLAG_UDR: to indicate an Underrun error occurs.
+     9. I2S_FLAG_CHSIDE: to indicate Channel Side.
+
+@note Do not use the BSY flag to handle each data transmission or reception.  It is
+      better to use the TXE and RXNE flags instead.
+
+  In this Mode it is advised to use the following functions:
+     - FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+     - void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG);
+
+  Interrupt Mode
+  ===============
+  In Interrupt Mode, the SPI communication can be managed by 3 interrupt sources
+  and 7 pending bits: 
+  Pending Bits:
+  ------------- 
+     1. SPI_I2S_IT_TXE : to indicate the status of the transmit buffer register
+     2. SPI_I2S_IT_RXNE : to indicate the status of the receive buffer register
+     3. SPI_IT_CRCERR : to indicate if a CRC Calculation error occur (available in SPI mode only)            
+     4. SPI_IT_MODF : to indicate if a Mode Fault error occur (available in SPI mode only)
+     5. SPI_I2S_IT_OVR : to indicate if an Overrun error occur
+     6. I2S_IT_UDR : to indicate an Underrun Error occurs (available in I2S mode only).
+     7. I2S_FLAG_TIFRFE : to indicate a Frame Format error occurs (available in TI mode only).
+
+  Interrupt Source:
+  -----------------
+     1. SPI_I2S_IT_TXE: specifies the interrupt source for the Tx buffer empty 
+                        interrupt.  
+     2. SPI_I2S_IT_RXNE : specifies the interrupt source for the Rx buffer not 
+                          empty interrupt.
+     3. SPI_I2S_IT_ERR : specifies the interrupt source for the errors interrupt.
+
+  In this Mode it is advised to use the following functions:
+     - void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState);
+     - ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+     - void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT);
+
+  DMA Mode
+  ========
+  In DMA Mode, the SPI communication can be managed by 2 DMA Channel requests:
+     1. SPI_I2S_DMAReq_Tx: specifies the Tx buffer DMA transfer request
+     2. SPI_I2S_DMAReq_Rx: specifies the Rx buffer DMA transfer request
+
+  In this Mode it is advised to use the following function:
+    - void SPI_I2S_DMACmd(SPI_TypeDef* SPIx, uint16_t SPI_I2S_DMAReq, FunctionalState NewState);
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified SPI/I2S interrupts.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. 
+  * @param  SPI_I2S_IT: specifies the SPI interrupt source to be enabled or disabled. 
+  *          This parameter can be one of the following values:
+  *            @arg SPI_I2S_IT_TXE: Tx buffer empty interrupt mask
+  *            @arg SPI_I2S_IT_RXNE: Rx buffer not empty interrupt mask
+  *            @arg SPI_I2S_IT_ERR: Error interrupt mask
+  * @param  NewState: new state of the specified SPI interrupt.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void SPI_I2S_ITConfig(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT, FunctionalState NewState)
+{
+  uint16_t itpos = 0, itmask = 0 ;
+  
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  assert_param(IS_SPI_I2S_CONFIG_IT(SPI_I2S_IT));
+
+  /* Get the SPI IT index */
+  itpos = SPI_I2S_IT >> 4;
+
+  /* Set the IT mask */
+  itmask = (uint16_t)1 << (uint16_t)itpos;
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected SPI interrupt */
+    SPIx->CR2 |= itmask;
+  }
+  else
+  {
+    /* Disable the selected SPI interrupt */
+    SPIx->CR2 &= (uint16_t)~itmask;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified SPIx/I2Sx flag is set or not.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. 
+  * @param  SPI_I2S_FLAG: specifies the SPI flag to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SPI_I2S_FLAG_TXE: Transmit buffer empty flag.
+  *            @arg SPI_I2S_FLAG_RXNE: Receive buffer not empty flag.
+  *            @arg SPI_I2S_FLAG_BSY: Busy flag.
+  *            @arg SPI_I2S_FLAG_OVR: Overrun flag.
+  *            @arg SPI_FLAG_MODF: Mode Fault flag.
+  *            @arg SPI_FLAG_CRCERR: CRC Error flag.
+  *            @arg SPI_I2S_FLAG_TIFRFE: Format Error.
+  *            @arg I2S_FLAG_UDR: Underrun Error flag.
+  *            @arg I2S_FLAG_CHSIDE: Channel Side flag.  
+  * @retval The new state of SPI_I2S_FLAG (SET or RESET).
+  */
+FlagStatus SPI_I2S_GetFlagStatus(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+  assert_param(IS_SPI_I2S_GET_FLAG(SPI_I2S_FLAG));
+  
+  /* Check the status of the specified SPI flag */
+  if ((SPIx->SR & SPI_I2S_FLAG) != (uint16_t)RESET)
+  {
+    /* SPI_I2S_FLAG is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SPI_I2S_FLAG is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SPI_I2S_FLAG status */
+  return  bitstatus;
+}
+
+/**
+  * @brief  Clears the SPIx CRC Error (CRCERR) flag.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode. 
+  * @param  SPI_I2S_FLAG: specifies the SPI flag to clear. 
+  *          This function clears only CRCERR flag.
+  *            @arg SPI_FLAG_CRCERR: CRC Error flag.  
+  *  
+  * @note   OVR (OverRun error) flag is cleared by software sequence: a read 
+  *          operation to SPI_DR register (SPI_I2S_ReceiveData()) followed by a read 
+  *          operation to SPI_SR register (SPI_I2S_GetFlagStatus()).
+  * @note   UDR (UnderRun error) flag is cleared by a read operation to 
+  *          SPI_SR register (SPI_I2S_GetFlagStatus()).   
+  * @note   MODF (Mode Fault) flag is cleared by software sequence: a read/write 
+  *          operation to SPI_SR register (SPI_I2S_GetFlagStatus()) followed by a 
+  *          write operation to SPI_CR1 register (SPI_Cmd() to enable the SPI).
+  *  
+  * @retval None
+  */
+void SPI_I2S_ClearFlag(SPI_TypeDef* SPIx, uint16_t SPI_I2S_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+  assert_param(IS_SPI_I2S_CLEAR_FLAG(SPI_I2S_FLAG));
+    
+  /* Clear the selected SPI CRC Error (CRCERR) flag */
+  SPIx->SR = (uint16_t)~SPI_I2S_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified SPIx/I2Sx interrupt has occurred or not.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.  
+  * @param  SPI_I2S_IT: specifies the SPI interrupt source to check. 
+  *          This parameter can be one of the following values:
+  *            @arg SPI_I2S_IT_TXE: Transmit buffer empty interrupt.
+  *            @arg SPI_I2S_IT_RXNE: Receive buffer not empty interrupt.
+  *            @arg SPI_I2S_IT_OVR: Overrun interrupt.
+  *            @arg SPI_IT_MODF: Mode Fault interrupt.
+  *            @arg SPI_IT_CRCERR: CRC Error interrupt.
+  *            @arg I2S_IT_UDR: Underrun interrupt.  
+  *            @arg SPI_I2S_IT_TIFRFE: Format Error interrupt.  
+  * @retval The new state of SPI_I2S_IT (SET or RESET).
+  */
+ITStatus SPI_I2S_GetITStatus(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
+{
+  ITStatus bitstatus = RESET;
+  uint16_t itpos = 0, itmask = 0, enablestatus = 0;
+
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+  assert_param(IS_SPI_I2S_GET_IT(SPI_I2S_IT));
+
+  /* Get the SPI_I2S_IT index */
+  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+  /* Get the SPI_I2S_IT IT mask */
+  itmask = SPI_I2S_IT >> 4;
+
+  /* Set the IT mask */
+  itmask = 0x01 << itmask;
+
+  /* Get the SPI_I2S_IT enable bit status */
+  enablestatus = (SPIx->CR2 & itmask) ;
+
+  /* Check the status of the specified SPI interrupt */
+  if (((SPIx->SR & itpos) != (uint16_t)RESET) && enablestatus)
+  {
+    /* SPI_I2S_IT is set */
+    bitstatus = SET;
+  }
+  else
+  {
+    /* SPI_I2S_IT is reset */
+    bitstatus = RESET;
+  }
+  /* Return the SPI_I2S_IT status */
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the SPIx CRC Error (CRCERR) interrupt pending bit.
+  * @param  SPIx: To select the SPIx/I2Sx peripheral, where x can be: 1, 2 or 3 
+  *         in SPI mode or 2 or 3 in I2S mode or I2Sxext for I2S full duplex mode.  
+  * @param  SPI_I2S_IT: specifies the SPI interrupt pending bit to clear.
+  *         This function clears only CRCERR interrupt pending bit.   
+  *            @arg SPI_IT_CRCERR: CRC Error interrupt.
+  *   
+  * @note   OVR (OverRun Error) interrupt pending bit is cleared by software 
+  *          sequence: a read operation to SPI_DR register (SPI_I2S_ReceiveData()) 
+  *          followed by a read operation to SPI_SR register (SPI_I2S_GetITStatus()).
+  * @note   UDR (UnderRun Error) interrupt pending bit is cleared by a read 
+  *          operation to SPI_SR register (SPI_I2S_GetITStatus()).   
+  * @note   MODF (Mode Fault) interrupt pending bit is cleared by software sequence:
+  *          a read/write operation to SPI_SR register (SPI_I2S_GetITStatus()) 
+  *          followed by a write operation to SPI_CR1 register (SPI_Cmd() to enable 
+  *          the SPI).
+  * @retval None
+  */
+void SPI_I2S_ClearITPendingBit(SPI_TypeDef* SPIx, uint8_t SPI_I2S_IT)
+{
+  uint16_t itpos = 0;
+  /* Check the parameters */
+  assert_param(IS_SPI_ALL_PERIPH_EXT(SPIx));
+  assert_param(IS_SPI_I2S_CLEAR_IT(SPI_I2S_IT));
+
+  /* Get the SPI_I2S IT index */
+  itpos = 0x01 << (SPI_I2S_IT & 0x0F);
+
+  /* Clear the selected SPI CRC Error (CRCERR) interrupt pending bit */
+  SPIx->SR = (uint16_t)~itpos;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c
new file mode 100644
index 0000000000..698823e04f
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_syscfg.c
@@ -0,0 +1,204 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_syscfg.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides firmware functions to manage the SYSCFG peripheral.
+  *
+  *  @verbatim
+  *  
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *                  
+  *          This driver provides functions for:
+  *          
+  *          1. Remapping the memory accessible in the code area using SYSCFG_MemoryRemapConfig()
+  *              
+  *          2. Manage the EXTI lines connection to the GPIOs using SYSCFG_EXTILineConfig()
+  *            
+  *          3. Select the ETHERNET media interface (RMII/RII) using SYSCFG_ETH_MediaInterfaceConfig()
+  *
+  *  @note  SYSCFG APB clock must be enabled to get write access to SYSCFG registers,
+  *         using RCC_APB2PeriphClockCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+  *                 
+  *  @endverbatim
+  *      
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_syscfg.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup SYSCFG 
+  * @brief SYSCFG driver modules
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* ------------ RCC registers bit address in the alias region ----------- */
+#define SYSCFG_OFFSET             (SYSCFG_BASE - PERIPH_BASE)
+/* ---  PMC Register ---*/ 
+/* Alias word address of MII_RMII_SEL bit */ 
+#define PMC_OFFSET                (SYSCFG_OFFSET + 0x04) 
+#define MII_RMII_SEL_BitNumber    ((uint8_t)0x17) 
+#define PMC_MII_RMII_SEL_BB       (PERIPH_BB_BASE + (PMC_OFFSET * 32) + (MII_RMII_SEL_BitNumber * 4)) 
+
+/* ---  CMPCR Register ---*/ 
+/* Alias word address of CMP_PD bit */ 
+#define CMPCR_OFFSET              (SYSCFG_OFFSET + 0x20) 
+#define CMP_PD_BitNumber          ((uint8_t)0x00) 
+#define CMPCR_CMP_PD_BB           (PERIPH_BB_BASE + (CMPCR_OFFSET * 32) + (CMP_PD_BitNumber * 4)) 
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup SYSCFG_Private_Functions
+  * @{
+  */ 
+
+/**
+  * @brief  Deinitializes the Alternate Functions (remap and EXTI configuration)
+  *   registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void SYSCFG_DeInit(void)
+{
+   RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, ENABLE);
+   RCC_APB2PeriphResetCmd(RCC_APB2Periph_SYSCFG, DISABLE);
+}
+
+/**
+  * @brief  Changes the mapping of the specified pin.
+  * @param  SYSCFG_Memory: selects the memory remapping.
+  *         This parameter can be one of the following values:
+  *            @arg SYSCFG_MemoryRemap_Flash:       Main Flash memory mapped at 0x00000000  
+  *            @arg SYSCFG_MemoryRemap_SystemFlash: System Flash memory mapped at 0x00000000
+  *            @arg SYSCFG_MemoryRemap_FSMC:        FSMC (Bank1 (NOR/PSRAM 1 and 2) mapped at 0x00000000
+  *            @arg SYSCFG_MemoryRemap_SRAM:        Embedded SRAM (112kB) mapped at 0x00000000
+  *  
+  * @note   In remap mode, the FSMC addressing is fixed to the remap address area only
+  *        (Bank1 NOR/PSRAM 1 and NOR/PSRAM 2) and FSMC control registers are not
+  *         accessible. The FSMC remap function must be disabled to allows addressing
+  *         other memory devices through the FSMC and/or to access FSMC control
+  *         registers. 
+  *        
+  * @retval None
+  */
+void SYSCFG_MemoryRemapConfig(uint8_t SYSCFG_MemoryRemap)
+{
+  /* Check the parameters */
+  assert_param(IS_SYSCFG_MEMORY_REMAP_CONFING(SYSCFG_MemoryRemap));
+
+  SYSCFG->MEMRMP = SYSCFG_MemoryRemap;
+}
+
+/**
+  * @brief  Selects the GPIO pin used as EXTI Line.
+  * @param  EXTI_PortSourceGPIOx : selects the GPIO port to be used as source for
+  *          EXTI lines where x can be (A..I).
+  * @param  EXTI_PinSourcex: specifies the EXTI line to be configured.
+  *           This parameter can be EXTI_PinSourcex where x can be (0..15, except
+  *           for EXTI_PortSourceGPIOI x can be (0..11).
+  * @retval None
+  */
+void SYSCFG_EXTILineConfig(uint8_t EXTI_PortSourceGPIOx, uint8_t EXTI_PinSourcex)
+{
+  uint32_t tmp = 0x00;
+
+  /* Check the parameters */
+  assert_param(IS_EXTI_PORT_SOURCE(EXTI_PortSourceGPIOx));
+  assert_param(IS_EXTI_PIN_SOURCE(EXTI_PinSourcex));
+
+  tmp = ((uint32_t)0x0F) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03));
+  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] &= ~tmp;
+  SYSCFG->EXTICR[EXTI_PinSourcex >> 0x02] |= (((uint32_t)EXTI_PortSourceGPIOx) << (0x04 * (EXTI_PinSourcex & (uint8_t)0x03)));
+}
+
+/**
+  * @brief  Selects the ETHERNET media interface 
+  * @param  SYSCFG_ETH_MediaInterface: specifies the Media Interface mode. 
+  *          This parameter can be one of the following values: 
+  *            @arg SYSCFG_ETH_MediaInterface_MII: MII mode selected
+  *            @arg SYSCFG_ETH_MediaInterface_RMII: RMII mode selected 
+  * @retval None 
+  */
+void SYSCFG_ETH_MediaInterfaceConfig(uint32_t SYSCFG_ETH_MediaInterface) 
+{ 
+  assert_param(IS_SYSCFG_ETH_MEDIA_INTERFACE(SYSCFG_ETH_MediaInterface)); 
+  /* Configure MII_RMII selection bit */ 
+  *(__IO uint32_t *) PMC_MII_RMII_SEL_BB = SYSCFG_ETH_MediaInterface; 
+}
+
+/**
+  * @brief  Enables or disables the I/O Compensation Cell.
+  * @note   The I/O compensation cell can be used only when the device supply
+  *         voltage ranges from 2.4 to 3.6 V.  
+  * @param  NewState: new state of the I/O Compensation Cell.
+  *          This parameter can be one of the following values:
+  *            @arg ENABLE: I/O compensation cell enabled  
+  *            @arg DISABLE: I/O compensation cell power-down mode  
+  * @retval None
+  */
+void SYSCFG_CompensationCellCmd(FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  *(__IO uint32_t *) CMPCR_CMP_PD_BB = (uint32_t)NewState;
+}
+
+/**
+  * @brief  Checks whether the I/O Compensation Cell ready flag is set or not.
+  * @param  None
+  * @retval The new state of the I/O Compensation Cell ready flag (SET or RESET)
+  */
+FlagStatus SYSCFG_GetCompensationCellStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+    
+  if ((SYSCFG->CMPCR & SYSCFG_CMPCR_READY ) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/   
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c
new file mode 100644
index 0000000000..ddb7e39338
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_tim.c
@@ -0,0 +1,3349 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_tim.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the TIM peripheral:
+  *            - TimeBase management
+  *            - Output Compare management
+  *            - Input Capture management
+  *            - Advanced-control timers (TIM1 and TIM8) specific features  
+  *            - Interrupts, DMA and flags management
+  *            - Clocks management
+  *            - Synchronization management
+  *            - Specific interface management
+  *            - Specific remapping management      
+  *              
+  *  @verbatim
+  *  
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *          This driver provides functions to configure and program the TIM 
+  *          of all STM32F4xx devices.
+  *          These functions are split in 9 groups: 
+  *   
+  *          1. TIM TimeBase management: this group includes all needed functions 
+  *             to configure the TM Timebase unit:
+  *                   - Set/Get Prescaler
+  *                   - Set/Get Autoreload  
+  *                   - Counter modes configuration
+  *                   - Set Clock division  
+  *                   - Select the One Pulse mode
+  *                   - Update Request Configuration
+  *                   - Update Disable Configuration
+  *                   - Auto-Preload Configuration 
+  *                   - Enable/Disable the counter     
+  *                 
+  *          2. TIM Output Compare management: this group includes all needed 
+  *             functions to configure the Capture/Compare unit used in Output 
+  *             compare mode: 
+  *                   - Configure each channel, independently, in Output Compare mode
+  *                   - Select the output compare modes
+  *                   - Select the Polarities of each channel
+  *                   - Set/Get the Capture/Compare register values
+  *                   - Select the Output Compare Fast mode 
+  *                   - Select the Output Compare Forced mode  
+  *                   - Output Compare-Preload Configuration 
+  *                   - Clear Output Compare Reference
+  *                   - Select the OCREF Clear signal
+  *                   - Enable/Disable the Capture/Compare Channels    
+  *                   
+  *          3. TIM Input Capture management: this group includes all needed 
+  *             functions to configure the Capture/Compare unit used in 
+  *             Input Capture mode:
+  *                   - Configure each channel in input capture mode
+  *                   - Configure Channel1/2 in PWM Input mode
+  *                   - Set the Input Capture Prescaler
+  *                   - Get the Capture/Compare values      
+  *                   
+  *          4. Advanced-control timers (TIM1 and TIM8) specific features
+  *                   - Configures the Break input, dead time, Lock level, the OSSI,
+  *                      the OSSR State and the AOE(automatic output enable)
+  *                   - Enable/Disable the TIM peripheral Main Outputs
+  *                   - Select the Commutation event
+  *                   - Set/Reset the Capture Compare Preload Control bit
+  *                              
+  *          5. TIM interrupts, DMA and flags management
+  *                   - Enable/Disable interrupt sources
+  *                   - Get flags status
+  *                   - Clear flags/ Pending bits
+  *                   - Enable/Disable DMA requests 
+  *                   - Configure DMA burst mode
+  *                   - Select CaptureCompare DMA request  
+  *              
+  *          6. TIM clocks management: this group includes all needed functions 
+  *             to configure the clock controller unit:
+  *                   - Select internal/External clock
+  *                   - Select the external clock mode: ETR(Mode1/Mode2), TIx or ITRx
+  *         
+  *          7. TIM synchronization management: this group includes all needed 
+  *             functions to configure the Synchronization unit:
+  *                   - Select Input Trigger  
+  *                   - Select Output Trigger  
+  *                   - Select Master Slave Mode 
+  *                   - ETR Configuration when used as external trigger   
+  *     
+  *          8. TIM specific interface management, this group includes all 
+  *             needed functions to use the specific TIM interface:
+  *                   - Encoder Interface Configuration
+  *                   - Select Hall Sensor   
+  *         
+  *          9. TIM specific remapping management includes the Remapping 
+  *             configuration of specific timers               
+  *   
+  *  @endverbatim
+  *    
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_tim.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup TIM 
+  * @brief TIM driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* ---------------------- TIM registers bit mask ------------------------ */
+#define SMCR_ETR_MASK      ((uint16_t)0x00FF) 
+#define CCMR_OFFSET        ((uint16_t)0x0018)
+#define CCER_CCE_SET       ((uint16_t)0x0001)  
+#define	CCER_CCNE_SET      ((uint16_t)0x0004) 
+#define CCMR_OC13M_MASK    ((uint16_t)0xFF8F)
+#define CCMR_OC24M_MASK    ((uint16_t)0x8FFF) 
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter);
+
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup TIM_Private_Functions
+  * @{
+  */
+
+/** @defgroup TIM_Group1 TimeBase management functions
+ *  @brief   TimeBase management functions 
+ *
+@verbatim   
+ ===============================================================================
+                       TimeBase management functions
+ ===============================================================================  
+  
+       ===================================================================      
+              TIM Driver: how to use it in Timing(Time base) Mode
+       =================================================================== 
+       To use the Timer in Timing(Time base) mode, the following steps are mandatory:
+       
+       1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
+                    
+       2. Fill the TIM_TimeBaseInitStruct with the desired parameters.
+       
+       3. Call TIM_TimeBaseInit(TIMx, &TIM_TimeBaseInitStruct) to configure the Time Base unit
+          with the corresponding configuration
+          
+       4. Enable the NVIC if you need to generate the update interrupt. 
+          
+       5. Enable the corresponding interrupt using the function TIM_ITConfig(TIMx, TIM_IT_Update) 
+       
+       6. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
+             
+       Note1: All other functions can be used separately to modify, if needed,
+          a specific feature of the Timer. 
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Deinitializes the TIMx peripheral registers to their default reset values.
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
+  * @retval None
+
+  */
+void TIM_DeInit(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
+ 
+  if (TIMx == TIM1)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM1, DISABLE);  
+  } 
+  else if (TIMx == TIM2) 
+  {     
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM2, DISABLE);
+  }  
+  else if (TIMx == TIM3)
+  { 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM3, DISABLE);
+  }  
+  else if (TIMx == TIM4)
+  { 
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM4, DISABLE);
+  }  
+  else if (TIMx == TIM5)
+  {      
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM5, DISABLE);
+  }  
+  else if (TIMx == TIM6)  
+  {    
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM6, DISABLE);
+  }  
+  else if (TIMx == TIM7)
+  {      
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM7, DISABLE);
+  }  
+  else if (TIMx == TIM8)
+  {      
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM8, DISABLE);  
+  }  
+  else if (TIMx == TIM9)
+  {      
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM9, DISABLE);  
+   }  
+  else if (TIMx == TIM10)
+  {      
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM10, DISABLE);  
+  }  
+  else if (TIMx == TIM11) 
+  {     
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_TIM11, DISABLE);  
+  }  
+  else if (TIMx == TIM12)
+  {      
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM12, DISABLE);  
+  }  
+  else if (TIMx == TIM13) 
+  {       
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM13, DISABLE);  
+  }  
+  else
+  { 
+    if (TIMx == TIM14) 
+    {     
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, ENABLE);
+      RCC_APB1PeriphResetCmd(RCC_APB1Periph_TIM14, DISABLE); 
+    }   
+  }
+}
+
+/**
+  * @brief  Initializes the TIMx Time Base Unit peripheral according to 
+  *         the specified parameters in the TIM_TimeBaseInitStruct.
+  * @param  TIMx: where x can be  1 to 14 to select the TIM peripheral.
+  * @param  TIM_TimeBaseInitStruct: pointer to a TIM_TimeBaseInitTypeDef structure
+  *         that contains the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+  uint16_t tmpcr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
+  assert_param(IS_TIM_COUNTER_MODE(TIM_TimeBaseInitStruct->TIM_CounterMode));
+  assert_param(IS_TIM_CKD_DIV(TIM_TimeBaseInitStruct->TIM_ClockDivision));
+
+  tmpcr1 = TIMx->CR1;  
+
+  if((TIMx == TIM1) || (TIMx == TIM8)||
+     (TIMx == TIM2) || (TIMx == TIM3)||
+     (TIMx == TIM4) || (TIMx == TIM5)) 
+  {
+    /* Select the Counter Mode */
+    tmpcr1 &= (uint16_t)(~(TIM_CR1_DIR | TIM_CR1_CMS));
+    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_CounterMode;
+  }
+ 
+  if((TIMx != TIM6) && (TIMx != TIM7))
+  {
+    /* Set the clock division */
+    tmpcr1 &=  (uint16_t)(~TIM_CR1_CKD);
+    tmpcr1 |= (uint32_t)TIM_TimeBaseInitStruct->TIM_ClockDivision;
+  }
+
+  TIMx->CR1 = tmpcr1;
+
+  /* Set the Autoreload value */
+  TIMx->ARR = TIM_TimeBaseInitStruct->TIM_Period ;
+ 
+  /* Set the Prescaler value */
+  TIMx->PSC = TIM_TimeBaseInitStruct->TIM_Prescaler;
+    
+  if ((TIMx == TIM1) || (TIMx == TIM8))  
+  {
+    /* Set the Repetition Counter value */
+    TIMx->RCR = TIM_TimeBaseInitStruct->TIM_RepetitionCounter;
+  }
+
+  /* Generate an update event to reload the Prescaler 
+     and the repetition counter(only for TIM1 and TIM8) value immediatly */
+  TIMx->EGR = TIM_PSCReloadMode_Immediate;          
+}
+
+/**
+  * @brief  Fills each TIM_TimeBaseInitStruct member with its default value.
+  * @param  TIM_TimeBaseInitStruct : pointer to a TIM_TimeBaseInitTypeDef
+  *         structure which will be initialized.
+  * @retval None
+  */
+void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct)
+{
+  /* Set the default configuration */
+  TIM_TimeBaseInitStruct->TIM_Period = 0xFFFFFFFF;
+  TIM_TimeBaseInitStruct->TIM_Prescaler = 0x0000;
+  TIM_TimeBaseInitStruct->TIM_ClockDivision = TIM_CKD_DIV1;
+  TIM_TimeBaseInitStruct->TIM_CounterMode = TIM_CounterMode_Up;
+  TIM_TimeBaseInitStruct->TIM_RepetitionCounter = 0x0000;
+}
+
+/**
+  * @brief  Configures the TIMx Prescaler.
+  * @param  TIMx: where x can be  1 to 14 to select the TIM peripheral.
+  * @param  Prescaler: specifies the Prescaler Register value
+  * @param  TIM_PSCReloadMode: specifies the TIM Prescaler Reload mode
+  *          This parameter can be one of the following values:
+  *            @arg TIM_PSCReloadMode_Update: The Prescaler is loaded at the update event.
+  *            @arg TIM_PSCReloadMode_Immediate: The Prescaler is loaded immediatly.
+  * @retval None
+  */
+void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_PRESCALER_RELOAD(TIM_PSCReloadMode));
+  /* Set the Prescaler value */
+  TIMx->PSC = Prescaler;
+  /* Set or reset the UG Bit */
+  TIMx->EGR = TIM_PSCReloadMode;
+}
+
+/**
+  * @brief  Specifies the TIMx Counter Mode to be used.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_CounterMode: specifies the Counter Mode to be used
+  *          This parameter can be one of the following values:
+  *            @arg TIM_CounterMode_Up: TIM Up Counting Mode
+  *            @arg TIM_CounterMode_Down: TIM Down Counting Mode
+  *            @arg TIM_CounterMode_CenterAligned1: TIM Center Aligned Mode1
+  *            @arg TIM_CounterMode_CenterAligned2: TIM Center Aligned Mode2
+  *            @arg TIM_CounterMode_CenterAligned3: TIM Center Aligned Mode3
+  * @retval None
+  */
+void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode)
+{
+  uint16_t tmpcr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_COUNTER_MODE(TIM_CounterMode));
+
+  tmpcr1 = TIMx->CR1;
+
+  /* Reset the CMS and DIR Bits */
+  tmpcr1 &= (uint16_t)~(TIM_CR1_DIR | TIM_CR1_CMS);
+
+  /* Set the Counter Mode */
+  tmpcr1 |= TIM_CounterMode;
+
+  /* Write to TIMx CR1 register */
+  TIMx->CR1 = tmpcr1;
+}
+
+/**
+  * @brief  Sets the TIMx Counter Register value
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
+  * @param  Counter: specifies the Counter register new value.
+  * @retval None
+  */
+void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter)
+{
+  /* Check the parameters */
+   assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+  /* Set the Counter Register value */
+  TIMx->CNT = Counter;
+}
+
+/**
+  * @brief  Sets the TIMx Autoreload Register value
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
+  * @param  Autoreload: specifies the Autoreload register new value.
+  * @retval None
+  */
+void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  
+  /* Set the Autoreload Register value */
+  TIMx->ARR = Autoreload;
+}
+
+/**
+  * @brief  Gets the TIMx Counter value.
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
+  * @retval Counter Register value
+  */
+uint32_t TIM_GetCounter(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+  /* Get the Counter Register value */
+  return TIMx->CNT;
+}
+
+/**
+  * @brief  Gets the TIMx Prescaler value.
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
+  * @retval Prescaler Register value.
+  */
+uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+  /* Get the Prescaler Register value */
+  return TIMx->PSC;
+}
+
+/**
+  * @brief  Enables or Disables the TIMx Update event.
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
+  * @param  NewState: new state of the TIMx UDIS bit
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the Update Disable Bit */
+    TIMx->CR1 |= TIM_CR1_UDIS;
+  }
+  else
+  {
+    /* Reset the Update Disable Bit */
+    TIMx->CR1 &= (uint16_t)~TIM_CR1_UDIS;
+  }
+}
+
+/**
+  * @brief  Configures the TIMx Update Request Interrupt source.
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
+  * @param  TIM_UpdateSource: specifies the Update source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_UpdateSource_Regular: Source of update is the counter
+  *                 overflow/underflow or the setting of UG bit, or an update
+  *                 generation through the slave mode controller.
+  *            @arg TIM_UpdateSource_Global: Source of update is counter overflow/underflow.
+  * @retval None
+  */
+void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_UPDATE_SOURCE(TIM_UpdateSource));
+
+  if (TIM_UpdateSource != TIM_UpdateSource_Global)
+  {
+    /* Set the URS Bit */
+    TIMx->CR1 |= TIM_CR1_URS;
+  }
+  else
+  {
+    /* Reset the URS Bit */
+    TIMx->CR1 &= (uint16_t)~TIM_CR1_URS;
+  }
+}
+
+/**
+  * @brief  Enables or disables TIMx peripheral Preload register on ARR.
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
+  * @param  NewState: new state of the TIMx peripheral Preload register
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the ARR Preload Bit */
+    TIMx->CR1 |= TIM_CR1_ARPE;
+  }
+  else
+  {
+    /* Reset the ARR Preload Bit */
+    TIMx->CR1 &= (uint16_t)~TIM_CR1_ARPE;
+  }
+}
+
+/**
+  * @brief  Selects the TIMx's One Pulse Mode.
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
+  * @param  TIM_OPMode: specifies the OPM Mode to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OPMode_Single
+  *            @arg TIM_OPMode_Repetitive
+  * @retval None
+  */
+void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_OPM_MODE(TIM_OPMode));
+
+  /* Reset the OPM Bit */
+  TIMx->CR1 &= (uint16_t)~TIM_CR1_OPM;
+
+  /* Configure the OPM Mode */
+  TIMx->CR1 |= TIM_OPMode;
+}
+
+/**
+  * @brief  Sets the TIMx Clock Division value.
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+  * @param  TIM_CKD: specifies the clock division value.
+  *          This parameter can be one of the following value:
+  *            @arg TIM_CKD_DIV1: TDTS = Tck_tim
+  *            @arg TIM_CKD_DIV2: TDTS = 2*Tck_tim
+  *            @arg TIM_CKD_DIV4: TDTS = 4*Tck_tim
+  * @retval None
+  */
+void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_CKD_DIV(TIM_CKD));
+
+  /* Reset the CKD Bits */
+  TIMx->CR1 &= (uint16_t)(~TIM_CR1_CKD);
+
+  /* Set the CKD value */
+  TIMx->CR1 |= TIM_CKD;
+}
+
+/**
+  * @brief  Enables or disables the specified TIM peripheral.
+  * @param  TIMx: where x can be 1 to 14 to select the TIMx peripheral.
+  * @param  NewState: new state of the TIMx peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the TIM Counter */
+    TIMx->CR1 |= TIM_CR1_CEN;
+  }
+  else
+  {
+    /* Disable the TIM Counter */
+    TIMx->CR1 &= (uint16_t)~TIM_CR1_CEN;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group2 Output Compare management functions
+ *  @brief    Output Compare management functions 
+ *
+@verbatim   
+ ===============================================================================
+                        Output Compare management functions
+ ===============================================================================  
+   
+       ===================================================================      
+              TIM Driver: how to use it in Output Compare Mode
+       =================================================================== 
+       To use the Timer in Output Compare mode, the following steps are mandatory:
+       
+       1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
+       
+       2. Configure the TIM pins by configuring the corresponding GPIO pins
+       
+       2. Configure the Time base unit as described in the first part of this driver, 
+          if needed, else the Timer will run with the default configuration:
+          - Autoreload value = 0xFFFF
+          - Prescaler value = 0x0000
+          - Counter mode = Up counting
+          - Clock Division = TIM_CKD_DIV1
+          
+       3. Fill the TIM_OCInitStruct with the desired parameters including:
+          - The TIM Output Compare mode: TIM_OCMode
+          - TIM Output State: TIM_OutputState
+          - TIM Pulse value: TIM_Pulse
+          - TIM Output Compare Polarity : TIM_OCPolarity
+       
+       4. Call TIM_OCxInit(TIMx, &TIM_OCInitStruct) to configure the desired channel with the 
+          corresponding configuration
+       
+       5. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
+       
+       Note1: All other functions can be used separately to modify, if needed,
+              a specific feature of the Timer. 
+          
+       Note2: In case of PWM mode, this function is mandatory:
+              TIM_OCxPreloadConfig(TIMx, TIM_OCPreload_ENABLE); 
+              
+       Note3: If the corresponding interrupt or DMA request are needed, the user should:
+                1. Enable the NVIC (or the DMA) to use the TIM interrupts (or DMA requests). 
+                2. Enable the corresponding interrupt (or DMA request) using the function 
+                   TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx))   
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIMx Channel1 according to the specified parameters in
+  *         the TIM_OCInitStruct.
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
+  *         the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
+  
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+    
+  /* Reset the Output Compare Mode Bits */
+  tmpccmrx &= (uint16_t)~TIM_CCMR1_OC1M;
+  tmpccmrx &= (uint16_t)~TIM_CCMR1_CC1S;
+  /* Select the Output Compare Mode */
+  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint16_t)~TIM_CCER_CC1P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= TIM_OCInitStruct->TIM_OCPolarity;
+  
+  /* Set the Output State */
+  tmpccer |= TIM_OCInitStruct->TIM_OutputState;
+    
+  if((TIMx == TIM1) || (TIMx == TIM8))
+  {
+    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    
+    /* Reset the Output N Polarity level */
+    tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
+    /* Set the Output N Polarity */
+    tmpccer |= TIM_OCInitStruct->TIM_OCNPolarity;
+    /* Reset the Output N State */
+    tmpccer &= (uint16_t)~TIM_CCER_CC1NE;
+    
+    /* Set the Output N State */
+    tmpccer |= TIM_OCInitStruct->TIM_OutputNState;
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= (uint16_t)~TIM_CR2_OIS1;
+    tmpcr2 &= (uint16_t)~TIM_CR2_OIS1N;
+    /* Set the Output Idle state */
+    tmpcr2 |= TIM_OCInitStruct->TIM_OCIdleState;
+    /* Set the Output N Idle state */
+    tmpcr2 |= TIM_OCInitStruct->TIM_OCNIdleState;
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+  
+  /* Set the Capture Compare Register value */
+  TIMx->CCR1 = TIM_OCInitStruct->TIM_Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TIMx Channel2 according to the specified parameters 
+  *         in the TIM_OCInitStruct.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
+  *         the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
+  
+  /* Get the TIMx CCER register value */  
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR1 register value */
+  tmpccmrx = TIMx->CCMR1;
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= (uint16_t)~TIM_CCMR1_OC2M;
+  tmpccmrx &= (uint16_t)~TIM_CCMR1_CC2S;
+  
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint16_t)~TIM_CCER_CC2P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 4);
+  
+  /* Set the Output State */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 4);
+    
+  if((TIMx == TIM1) || (TIMx == TIM8))
+  {
+    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    
+    /* Reset the Output N Polarity level */
+    tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 4);
+    /* Reset the Output N State */
+    tmpccer &= (uint16_t)~TIM_CCER_CC2NE;
+    
+    /* Set the Output N State */
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 4);
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= (uint16_t)~TIM_CR2_OIS2;
+    tmpcr2 &= (uint16_t)~TIM_CR2_OIS2N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 2);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 2);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmrx;
+  
+  /* Set the Capture Compare Register value */
+  TIMx->CCR2 = TIM_OCInitStruct->TIM_Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TIMx Channel3 according to the specified parameters
+  *         in the TIM_OCInitStruct.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
+  *         the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+
+  /* Disable the Channel 3: Reset the CC2E Bit */
+  TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
+  
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= (uint16_t)~TIM_CCMR2_OC3M;
+  tmpccmrx &= (uint16_t)~TIM_CCMR2_CC3S;  
+  /* Select the Output Compare Mode */
+  tmpccmrx |= TIM_OCInitStruct->TIM_OCMode;
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint16_t)~TIM_CCER_CC3P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 8);
+  
+  /* Set the Output State */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 8);
+    
+  if((TIMx == TIM1) || (TIMx == TIM8))
+  {
+    assert_param(IS_TIM_OUTPUTN_STATE(TIM_OCInitStruct->TIM_OutputNState));
+    assert_param(IS_TIM_OCN_POLARITY(TIM_OCInitStruct->TIM_OCNPolarity));
+    assert_param(IS_TIM_OCNIDLE_STATE(TIM_OCInitStruct->TIM_OCNIdleState));
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    
+    /* Reset the Output N Polarity level */
+    tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
+    /* Set the Output N Polarity */
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCNPolarity << 8);
+    /* Reset the Output N State */
+    tmpccer &= (uint16_t)~TIM_CCER_CC3NE;
+    
+    /* Set the Output N State */
+    tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputNState << 8);
+    /* Reset the Output Compare and Output Compare N IDLE State */
+    tmpcr2 &= (uint16_t)~TIM_CR2_OIS3;
+    tmpcr2 &= (uint16_t)~TIM_CR2_OIS3N;
+    /* Set the Output Idle state */
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 4);
+    /* Set the Output N Idle state */
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCNIdleState << 4);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmrx;
+  
+  /* Set the Capture Compare Register value */
+  TIMx->CCR3 = TIM_OCInitStruct->TIM_Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Initializes the TIMx Channel4 according to the specified parameters
+  *         in the TIM_OCInitStruct.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure that contains
+  *         the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  uint16_t tmpccmrx = 0, tmpccer = 0, tmpcr2 = 0;
+   
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
+  assert_param(IS_TIM_OC_MODE(TIM_OCInitStruct->TIM_OCMode));
+  assert_param(IS_TIM_OUTPUT_STATE(TIM_OCInitStruct->TIM_OutputState));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCInitStruct->TIM_OCPolarity));   
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
+  
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+  /* Get the TIMx CR2 register value */
+  tmpcr2 =  TIMx->CR2;
+  
+  /* Get the TIMx CCMR2 register value */
+  tmpccmrx = TIMx->CCMR2;
+    
+  /* Reset the Output Compare mode and Capture/Compare selection Bits */
+  tmpccmrx &= (uint16_t)~TIM_CCMR2_OC4M;
+  tmpccmrx &= (uint16_t)~TIM_CCMR2_CC4S;
+  
+  /* Select the Output Compare Mode */
+  tmpccmrx |= (uint16_t)(TIM_OCInitStruct->TIM_OCMode << 8);
+  
+  /* Reset the Output Polarity level */
+  tmpccer &= (uint16_t)~TIM_CCER_CC4P;
+  /* Set the Output Compare Polarity */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OCPolarity << 12);
+  
+  /* Set the Output State */
+  tmpccer |= (uint16_t)(TIM_OCInitStruct->TIM_OutputState << 12);
+  
+  if((TIMx == TIM1) || (TIMx == TIM8))
+  {
+    assert_param(IS_TIM_OCIDLE_STATE(TIM_OCInitStruct->TIM_OCIdleState));
+    /* Reset the Output Compare IDLE State */
+    tmpcr2 &=(uint16_t) ~TIM_CR2_OIS4;
+    /* Set the Output Idle state */
+    tmpcr2 |= (uint16_t)(TIM_OCInitStruct->TIM_OCIdleState << 6);
+  }
+  /* Write to TIMx CR2 */
+  TIMx->CR2 = tmpcr2;
+  
+  /* Write to TIMx CCMR2 */  
+  TIMx->CCMR2 = tmpccmrx;
+    
+  /* Set the Capture Compare Register value */
+  TIMx->CCR4 = TIM_OCInitStruct->TIM_Pulse;
+  
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Fills each TIM_OCInitStruct member with its default value.
+  * @param  TIM_OCInitStruct: pointer to a TIM_OCInitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct)
+{
+  /* Set the default configuration */
+  TIM_OCInitStruct->TIM_OCMode = TIM_OCMode_Timing;
+  TIM_OCInitStruct->TIM_OutputState = TIM_OutputState_Disable;
+  TIM_OCInitStruct->TIM_OutputNState = TIM_OutputNState_Disable;
+  TIM_OCInitStruct->TIM_Pulse = 0x00000000;
+  TIM_OCInitStruct->TIM_OCPolarity = TIM_OCPolarity_High;
+  TIM_OCInitStruct->TIM_OCNPolarity = TIM_OCPolarity_High;
+  TIM_OCInitStruct->TIM_OCIdleState = TIM_OCIdleState_Reset;
+  TIM_OCInitStruct->TIM_OCNIdleState = TIM_OCNIdleState_Reset;
+}
+
+/**
+  * @brief  Selects the TIM Output Compare Mode.
+  * @note   This function disables the selected channel before changing the Output
+  *         Compare Mode. If needed, user has to enable this channel using
+  *         TIM_CCxCmd() and TIM_CCxNCmd() functions.
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+  * @param  TIM_Channel: specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_Channel_1: TIM Channel 1
+  *            @arg TIM_Channel_2: TIM Channel 2
+  *            @arg TIM_Channel_3: TIM Channel 3
+  *            @arg TIM_Channel_4: TIM Channel 4
+  * @param  TIM_OCMode: specifies the TIM Output Compare Mode.
+  *           This parameter can be one of the following values:
+  *            @arg TIM_OCMode_Timing
+  *            @arg TIM_OCMode_Active
+  *            @arg TIM_OCMode_Toggle
+  *            @arg TIM_OCMode_PWM1
+  *            @arg TIM_OCMode_PWM2
+  *            @arg TIM_ForcedAction_Active
+  *            @arg TIM_ForcedAction_InActive
+  * @retval None
+  */
+void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode)
+{
+  uint32_t tmp = 0;
+  uint16_t tmp1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_CHANNEL(TIM_Channel));
+  assert_param(IS_TIM_OCM(TIM_OCMode));
+
+  tmp = (uint32_t) TIMx;
+  tmp += CCMR_OFFSET;
+
+  tmp1 = CCER_CCE_SET << (uint16_t)TIM_Channel;
+
+  /* Disable the Channel: Reset the CCxE Bit */
+  TIMx->CCER &= (uint16_t) ~tmp1;
+
+  if((TIM_Channel == TIM_Channel_1) ||(TIM_Channel == TIM_Channel_3))
+  {
+    tmp += (TIM_Channel>>1);
+
+    /* Reset the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp &= CCMR_OC13M_MASK;
+   
+    /* Configure the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp |= TIM_OCMode;
+  }
+  else
+  {
+    tmp += (uint16_t)(TIM_Channel - (uint16_t)4)>> (uint16_t)1;
+
+    /* Reset the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp &= CCMR_OC24M_MASK;
+    
+    /* Configure the OCxM bits in the CCMRx register */
+    *(__IO uint32_t *) tmp |= (uint16_t)(TIM_OCMode << 8);
+  }
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare1 Register value
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+  * @param  Compare1: specifies the Capture Compare1 register new value.
+  * @retval None
+  */
+void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+
+  /* Set the Capture Compare1 Register value */
+  TIMx->CCR1 = Compare1;
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare2 Register value
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
+  * @param  Compare2: specifies the Capture Compare2 register new value.
+  * @retval None
+  */
+void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+
+  /* Set the Capture Compare2 Register value */
+  TIMx->CCR2 = Compare2;
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare3 Register value
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  Compare3: specifies the Capture Compare3 register new value.
+  * @retval None
+  */
+void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+
+  /* Set the Capture Compare3 Register value */
+  TIMx->CCR3 = Compare3;
+}
+
+/**
+  * @brief  Sets the TIMx Capture Compare4 Register value
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  Compare4: specifies the Capture Compare4 register new value.
+  * @retval None
+  */
+void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+
+  /* Set the Capture Compare4 Register value */
+  TIMx->CCR4 = Compare4;
+}
+
+/**
+  * @brief  Forces the TIMx output 1 waveform to active or inactive level.
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ForcedAction_Active: Force active level on OC1REF
+  *            @arg TIM_ForcedAction_InActive: Force inactive level on OC1REF.
+  * @retval None
+  */
+void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint16_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OC1M Bits */
+  tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1M;
+
+  /* Configure The Forced output Mode */
+  tmpccmr1 |= TIM_ForcedAction;
+
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Forces the TIMx output 2 waveform to active or inactive level.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ForcedAction_Active: Force active level on OC2REF
+  *            @arg TIM_ForcedAction_InActive: Force inactive level on OC2REF.
+  * @retval None
+  */
+void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint16_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OC2M Bits */
+  tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2M;
+
+  /* Configure The Forced output Mode */
+  tmpccmr1 |= (uint16_t)(TIM_ForcedAction << 8);
+
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Forces the TIMx output 3 waveform to active or inactive level.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ForcedAction_Active: Force active level on OC3REF
+  *            @arg TIM_ForcedAction_InActive: Force inactive level on OC3REF.
+  * @retval None
+  */
+void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint16_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OC1M Bits */
+  tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3M;
+
+  /* Configure The Forced output Mode */
+  tmpccmr2 |= TIM_ForcedAction;
+
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Forces the TIMx output 4 waveform to active or inactive level.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ForcedAction: specifies the forced Action to be set to the output waveform.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ForcedAction_Active: Force active level on OC4REF
+  *            @arg TIM_ForcedAction_InActive: Force inactive level on OC4REF.
+  * @retval None
+  */
+void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction)
+{
+  uint16_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_FORCED_ACTION(TIM_ForcedAction));
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OC2M Bits */
+  tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4M;
+
+  /* Configure The Forced output Mode */
+  tmpccmr2 |= (uint16_t)(TIM_ForcedAction << 8);
+
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR1.
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPreload_Enable
+  *            @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint16_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OC1PE Bit */
+  tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC1PE);
+
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr1 |= TIM_OCPreload;
+
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR2.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPreload_Enable
+  *            @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint16_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OC2PE Bit */
+  tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2PE);
+
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr1 |= (uint16_t)(TIM_OCPreload << 8);
+
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR3.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPreload_Enable
+  *            @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint16_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OC3PE Bit */
+  tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC3PE);
+
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr2 |= TIM_OCPreload;
+
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Enables or disables the TIMx peripheral Preload register on CCR4.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCPreload: new state of the TIMx peripheral Preload register
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPreload_Enable
+  *            @arg TIM_OCPreload_Disable
+  * @retval None
+  */
+void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload)
+{
+  uint16_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCPRELOAD_STATE(TIM_OCPreload));
+
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OC4PE Bit */
+  tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4PE);
+
+  /* Enable or Disable the Output Compare Preload feature */
+  tmpccmr2 |= (uint16_t)(TIM_OCPreload << 8);
+
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Configures the TIMx Output Compare 1 Fast feature.
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCFast_Enable: TIM output compare fast enable
+  *            @arg TIM_OCFast_Disable: TIM output compare fast disable
+  * @retval None
+  */
+void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+  uint16_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OC1FE Bit */
+  tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1FE;
+
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr1 |= TIM_OCFast;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Configures the TIMx Output Compare 2 Fast feature.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCFast_Enable: TIM output compare fast enable
+  *            @arg TIM_OCFast_Disable: TIM output compare fast disable
+  * @retval None
+  */
+void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+  uint16_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OC2FE Bit */
+  tmpccmr1 &= (uint16_t)(~TIM_CCMR1_OC2FE);
+
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr1 |= (uint16_t)(TIM_OCFast << 8);
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Configures the TIMx Output Compare 3 Fast feature.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCFast_Enable: TIM output compare fast enable
+  *            @arg TIM_OCFast_Disable: TIM output compare fast disable
+  * @retval None
+  */
+void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+  uint16_t tmpccmr2 = 0;
+  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OC3FE Bit */
+  tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3FE;
+
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr2 |= TIM_OCFast;
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Configures the TIMx Output Compare 4 Fast feature.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCFast: new state of the Output Compare Fast Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCFast_Enable: TIM output compare fast enable
+  *            @arg TIM_OCFast_Disable: TIM output compare fast disable
+  * @retval None
+  */
+void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast)
+{
+  uint16_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCFAST_STATE(TIM_OCFast));
+
+  /* Get the TIMx CCMR2 register value */
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OC4FE Bit */
+  tmpccmr2 &= (uint16_t)(~TIM_CCMR2_OC4FE);
+
+  /* Enable or Disable the Output Compare Fast Bit */
+  tmpccmr2 |= (uint16_t)(TIM_OCFast << 8);
+
+  /* Write to TIMx CCMR2 */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF1 signal on an external event
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCClear_Enable: TIM Output clear enable
+  *            @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint16_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OC1CE Bit */
+  tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC1CE;
+
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr1 |= TIM_OCClear;
+
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF2 signal on an external event
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCClear_Enable: TIM Output clear enable
+  *            @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint16_t tmpccmr1 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Reset the OC2CE Bit */
+  tmpccmr1 &= (uint16_t)~TIM_CCMR1_OC2CE;
+
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr1 |= (uint16_t)(TIM_OCClear << 8);
+
+  /* Write to TIMx CCMR1 register */
+  TIMx->CCMR1 = tmpccmr1;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF3 signal on an external event
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCClear_Enable: TIM Output clear enable
+  *            @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint16_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OC3CE Bit */
+  tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC3CE;
+
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr2 |= TIM_OCClear;
+
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Clears or safeguards the OCREF4 signal on an external event
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCClear: new state of the Output Compare Clear Enable Bit.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCClear_Enable: TIM Output clear enable
+  *            @arg TIM_OCClear_Disable: TIM Output clear disable
+  * @retval None
+  */
+void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear)
+{
+  uint16_t tmpccmr2 = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OCCLEAR_STATE(TIM_OCClear));
+
+  tmpccmr2 = TIMx->CCMR2;
+
+  /* Reset the OC4CE Bit */
+  tmpccmr2 &= (uint16_t)~TIM_CCMR2_OC4CE;
+
+  /* Enable or Disable the Output Compare Clear Bit */
+  tmpccmr2 |= (uint16_t)(TIM_OCClear << 8);
+
+  /* Write to TIMx CCMR2 register */
+  TIMx->CCMR2 = tmpccmr2;
+}
+
+/**
+  * @brief  Configures the TIMx channel 1 polarity.
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+  * @param  TIM_OCPolarity: specifies the OC1 Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPolarity_High: Output Compare active high
+  *            @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint16_t tmpccer = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+  tmpccer = TIMx->CCER;
+
+  /* Set or Reset the CC1P Bit */
+  tmpccer &= (uint16_t)(~TIM_CCER_CC1P);
+  tmpccer |= TIM_OCPolarity;
+
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx Channel 1N polarity.
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
+  * @param  TIM_OCNPolarity: specifies the OC1N Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCNPolarity_High: Output Compare active high
+  *            @arg TIM_OCNPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+  uint16_t tmpccer = 0;
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+   
+  tmpccer = TIMx->CCER;
+
+  /* Set or Reset the CC1NP Bit */
+  tmpccer &= (uint16_t)~TIM_CCER_CC1NP;
+  tmpccer |= TIM_OCNPolarity;
+
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx channel 2 polarity.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
+  * @param  TIM_OCPolarity: specifies the OC2 Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPolarity_High: Output Compare active high
+  *            @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint16_t tmpccer = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+  tmpccer = TIMx->CCER;
+
+  /* Set or Reset the CC2P Bit */
+  tmpccer &= (uint16_t)(~TIM_CCER_CC2P);
+  tmpccer |= (uint16_t)(TIM_OCPolarity << 4);
+
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx Channel 2N polarity.
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
+  * @param  TIM_OCNPolarity: specifies the OC2N Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCNPolarity_High: Output Compare active high
+  *            @arg TIM_OCNPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+  uint16_t tmpccer = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+  
+  tmpccer = TIMx->CCER;
+
+  /* Set or Reset the CC2NP Bit */
+  tmpccer &= (uint16_t)~TIM_CCER_CC2NP;
+  tmpccer |= (uint16_t)(TIM_OCNPolarity << 4);
+
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx channel 3 polarity.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCPolarity: specifies the OC3 Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPolarity_High: Output Compare active high
+  *            @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint16_t tmpccer = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+  tmpccer = TIMx->CCER;
+
+  /* Set or Reset the CC3P Bit */
+  tmpccer &= (uint16_t)~TIM_CCER_CC3P;
+  tmpccer |= (uint16_t)(TIM_OCPolarity << 8);
+
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx Channel 3N polarity.
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
+  * @param  TIM_OCNPolarity: specifies the OC3N Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCNPolarity_High: Output Compare active high
+  *            @arg TIM_OCNPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity)
+{
+  uint16_t tmpccer = 0;
+ 
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_OCN_POLARITY(TIM_OCNPolarity));
+    
+  tmpccer = TIMx->CCER;
+
+  /* Set or Reset the CC3NP Bit */
+  tmpccer &= (uint16_t)~TIM_CCER_CC3NP;
+  tmpccer |= (uint16_t)(TIM_OCNPolarity << 8);
+
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configures the TIMx channel 4 polarity.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_OCPolarity: specifies the OC4 Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM_OCPolarity_High: Output Compare active high
+  *            @arg TIM_OCPolarity_Low: Output Compare active low
+  * @retval None
+  */
+void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity)
+{
+  uint16_t tmpccer = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_OC_POLARITY(TIM_OCPolarity));
+
+  tmpccer = TIMx->CCER;
+
+  /* Set or Reset the CC4P Bit */
+  tmpccer &= (uint16_t)~TIM_CCER_CC4P;
+  tmpccer |= (uint16_t)(TIM_OCPolarity << 12);
+
+  /* Write to TIMx CCER register */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel x.
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+  * @param  TIM_Channel: specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_Channel_1: TIM Channel 1
+  *            @arg TIM_Channel_2: TIM Channel 2
+  *            @arg TIM_Channel_3: TIM Channel 3
+  *            @arg TIM_Channel_4: TIM Channel 4
+  * @param  TIM_CCx: specifies the TIM Channel CCxE bit new state.
+  *          This parameter can be: TIM_CCx_Enable or TIM_CCx_Disable. 
+  * @retval None
+  */
+void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx)
+{
+  uint16_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 
+  assert_param(IS_TIM_CHANNEL(TIM_Channel));
+  assert_param(IS_TIM_CCX(TIM_CCx));
+
+  tmp = CCER_CCE_SET << TIM_Channel;
+
+  /* Reset the CCxE Bit */
+  TIMx->CCER &= (uint16_t)~ tmp;
+
+  /* Set or reset the CCxE Bit */ 
+  TIMx->CCER |=  (uint16_t)(TIM_CCx << TIM_Channel);
+}
+
+/**
+  * @brief  Enables or disables the TIM Capture Compare Channel xN.
+  * @param  TIMx: where x can be 1 or 8 to select the TIM peripheral.
+  * @param  TIM_Channel: specifies the TIM Channel
+  *          This parameter can be one of the following values:
+  *            @arg TIM_Channel_1: TIM Channel 1
+  *            @arg TIM_Channel_2: TIM Channel 2
+  *            @arg TIM_Channel_3: TIM Channel 3
+  * @param  TIM_CCxN: specifies the TIM Channel CCxNE bit new state.
+  *          This parameter can be: TIM_CCxN_Enable or TIM_CCxN_Disable. 
+  * @retval None
+  */
+void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN)
+{
+  uint16_t tmp = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_COMPLEMENTARY_CHANNEL(TIM_Channel));
+  assert_param(IS_TIM_CCXN(TIM_CCxN));
+
+  tmp = CCER_CCNE_SET << TIM_Channel;
+
+  /* Reset the CCxNE Bit */
+  TIMx->CCER &= (uint16_t) ~tmp;
+
+  /* Set or reset the CCxNE Bit */ 
+  TIMx->CCER |=  (uint16_t)(TIM_CCxN << TIM_Channel);
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group3 Input Capture management functions
+ *  @brief    Input Capture management functions 
+ *
+@verbatim   
+ ===============================================================================
+                      Input Capture management functions
+ ===============================================================================  
+   
+       ===================================================================      
+              TIM Driver: how to use it in Input Capture Mode
+       =================================================================== 
+       To use the Timer in Input Capture mode, the following steps are mandatory:
+       
+       1. Enable TIM clock using RCC_APBxPeriphClockCmd(RCC_APBxPeriph_TIMx, ENABLE) function
+       
+       2. Configure the TIM pins by configuring the corresponding GPIO pins
+       
+       2. Configure the Time base unit as described in the first part of this driver,
+          if needed, else the Timer will run with the default configuration:
+          - Autoreload value = 0xFFFF
+          - Prescaler value = 0x0000
+          - Counter mode = Up counting
+          - Clock Division = TIM_CKD_DIV1
+          
+       3. Fill the TIM_ICInitStruct with the desired parameters including:
+          - TIM Channel: TIM_Channel
+          - TIM Input Capture polarity: TIM_ICPolarity
+          - TIM Input Capture selection: TIM_ICSelection
+          - TIM Input Capture Prescaler: TIM_ICPrescaler
+          - TIM Input CApture filter value: TIM_ICFilter
+       
+       4. Call TIM_ICInit(TIMx, &TIM_ICInitStruct) to configure the desired channel with the 
+          corresponding configuration and to measure only frequency or duty cycle of the input signal,
+          or,
+          Call TIM_PWMIConfig(TIMx, &TIM_ICInitStruct) to configure the desired channels with the 
+          corresponding configuration and to measure the frequency and the duty cycle of the input signal
+          
+       5. Enable the NVIC or the DMA to read the measured frequency. 
+          
+       6. Enable the corresponding interrupt (or DMA request) to read the Captured value,
+          using the function TIM_ITConfig(TIMx, TIM_IT_CCx) (or TIM_DMA_Cmd(TIMx, TIM_DMA_CCx)) 
+       
+       7. Call the TIM_Cmd(ENABLE) function to enable the TIM counter.
+       
+       8. Use TIM_GetCapturex(TIMx); to read the captured value.
+       
+       Note1: All other functions can be used separately to modify, if needed,
+              a specific feature of the Timer. 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Initializes the TIM peripheral according to the specified parameters
+  *         in the TIM_ICInitStruct.
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
+  *         the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_POLARITY(TIM_ICInitStruct->TIM_ICPolarity));
+  assert_param(IS_TIM_IC_SELECTION(TIM_ICInitStruct->TIM_ICSelection));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICInitStruct->TIM_ICPrescaler));
+  assert_param(IS_TIM_IC_FILTER(TIM_ICInitStruct->TIM_ICFilter));
+  
+  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+  {
+    /* TI1 Configuration */
+    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+               TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_2)
+  {
+    /* TI2 Configuration */
+    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+               TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_3)
+  {
+    /* TI3 Configuration */
+    TI3_Config(TIMx,  TIM_ICInitStruct->TIM_ICPolarity,
+               TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC3Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else
+  {
+    /* TI4 Configuration */
+    TI4_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity,
+               TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC4Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+}
+
+/**
+  * @brief  Fills each TIM_ICInitStruct member with its default value.
+  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+  /* Set the default configuration */
+  TIM_ICInitStruct->TIM_Channel = TIM_Channel_1;
+  TIM_ICInitStruct->TIM_ICPolarity = TIM_ICPolarity_Rising;
+  TIM_ICInitStruct->TIM_ICSelection = TIM_ICSelection_DirectTI;
+  TIM_ICInitStruct->TIM_ICPrescaler = TIM_ICPSC_DIV1;
+  TIM_ICInitStruct->TIM_ICFilter = 0x00;
+}
+
+/**
+  * @brief  Configures the TIM peripheral according to the specified parameters
+  *         in the TIM_ICInitStruct to measure an external PWM signal.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5,8, 9 or 12 to select the TIM 
+  *         peripheral.
+  * @param  TIM_ICInitStruct: pointer to a TIM_ICInitTypeDef structure that contains
+  *         the configuration information for the specified TIM peripheral.
+  * @retval None
+  */
+void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct)
+{
+  uint16_t icoppositepolarity = TIM_ICPolarity_Rising;
+  uint16_t icoppositeselection = TIM_ICSelection_DirectTI;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+
+  /* Select the Opposite Input Polarity */
+  if (TIM_ICInitStruct->TIM_ICPolarity == TIM_ICPolarity_Rising)
+  {
+    icoppositepolarity = TIM_ICPolarity_Falling;
+  }
+  else
+  {
+    icoppositepolarity = TIM_ICPolarity_Rising;
+  }
+  /* Select the Opposite Input */
+  if (TIM_ICInitStruct->TIM_ICSelection == TIM_ICSelection_DirectTI)
+  {
+    icoppositeselection = TIM_ICSelection_IndirectTI;
+  }
+  else
+  {
+    icoppositeselection = TIM_ICSelection_DirectTI;
+  }
+  if (TIM_ICInitStruct->TIM_Channel == TIM_Channel_1)
+  {
+    /* TI1 Configuration */
+    TI1_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    /* TI2 Configuration */
+    TI2_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+  else
+  { 
+    /* TI2 Configuration */
+    TI2_Config(TIMx, TIM_ICInitStruct->TIM_ICPolarity, TIM_ICInitStruct->TIM_ICSelection,
+               TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC2Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+    /* TI1 Configuration */
+    TI1_Config(TIMx, icoppositepolarity, icoppositeselection, TIM_ICInitStruct->TIM_ICFilter);
+    /* Set the Input Capture Prescaler value */
+    TIM_SetIC1Prescaler(TIMx, TIM_ICInitStruct->TIM_ICPrescaler);
+  }
+}
+
+/**
+  * @brief  Gets the TIMx Input Capture 1 value.
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+  * @retval Capture Compare 1 Register value.
+  */
+uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+
+  /* Get the Capture 1 Register value */
+  return TIMx->CCR1;
+}
+
+/**
+  * @brief  Gets the TIMx Input Capture 2 value.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
+  * @retval Capture Compare 2 Register value.
+  */
+uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+
+  /* Get the Capture 2 Register value */
+  return TIMx->CCR2;
+}
+
+/**
+  * @brief  Gets the TIMx Input Capture 3 value.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @retval Capture Compare 3 Register value.
+  */
+uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx)); 
+
+  /* Get the Capture 3 Register value */
+  return TIMx->CCR3;
+}
+
+/**
+  * @brief  Gets the TIMx Input Capture 4 value.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @retval Capture Compare 4 Register value.
+  */
+uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+
+  /* Get the Capture 4 Register value */
+  return TIMx->CCR4;
+}
+
+/**
+  * @brief  Sets the TIMx Input Capture 1 prescaler.
+  * @param  TIMx: where x can be 1 to 14 except 6 and 7, to select the TIM peripheral.
+  * @param  TIM_ICPSC: specifies the Input Capture1 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+
+  /* Reset the IC1PSC Bits */
+  TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC1PSC;
+
+  /* Set the IC1PSC value */
+  TIMx->CCMR1 |= TIM_ICPSC;
+}
+
+/**
+  * @brief  Sets the TIMx Input Capture 2 prescaler.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
+  * @param  TIM_ICPSC: specifies the Input Capture2 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+
+  /* Reset the IC2PSC Bits */
+  TIMx->CCMR1 &= (uint16_t)~TIM_CCMR1_IC2PSC;
+
+  /* Set the IC2PSC value */
+  TIMx->CCMR1 |= (uint16_t)(TIM_ICPSC << 8);
+}
+
+/**
+  * @brief  Sets the TIMx Input Capture 3 prescaler.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ICPSC: specifies the Input Capture3 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+
+  /* Reset the IC3PSC Bits */
+  TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC3PSC;
+
+  /* Set the IC3PSC value */
+  TIMx->CCMR2 |= TIM_ICPSC;
+}
+
+/**
+  * @brief  Sets the TIMx Input Capture 4 prescaler.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ICPSC: specifies the Input Capture4 prescaler new value.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPSC_DIV1: no prescaler
+  *            @arg TIM_ICPSC_DIV2: capture is done once every 2 events
+  *            @arg TIM_ICPSC_DIV4: capture is done once every 4 events
+  *            @arg TIM_ICPSC_DIV8: capture is done once every 8 events
+  * @retval None
+  */
+void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC)
+{  
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_PRESCALER(TIM_ICPSC));
+
+  /* Reset the IC4PSC Bits */
+  TIMx->CCMR2 &= (uint16_t)~TIM_CCMR2_IC4PSC;
+
+  /* Set the IC4PSC value */
+  TIMx->CCMR2 |= (uint16_t)(TIM_ICPSC << 8);
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group4 Advanced-control timers (TIM1 and TIM8) specific features
+ *  @brief   Advanced-control timers (TIM1 and TIM8) specific features
+ *
+@verbatim   
+ ===============================================================================
+          Advanced-control timers (TIM1 and TIM8) specific features
+ ===============================================================================  
+  
+       ===================================================================      
+              TIM Driver: how to use the Break feature
+       =================================================================== 
+       After configuring the Timer channel(s) in the appropriate Output Compare mode: 
+                         
+       1. Fill the TIM_BDTRInitStruct with the desired parameters for the Timer
+          Break Polarity, dead time, Lock level, the OSSI/OSSR State and the 
+          AOE(automatic output enable).
+               
+       2. Call TIM_BDTRConfig(TIMx, &TIM_BDTRInitStruct) to configure the Timer
+          
+       3. Enable the Main Output using TIM_CtrlPWMOutputs(TIM1, ENABLE) 
+          
+       4. Once the break even occurs, the Timer's output signals are put in reset
+          state or in a known state (according to the configuration made in
+          TIM_BDTRConfig() function).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the Break feature, dead time, Lock level, OSSI/OSSR State
+  *         and the AOE(automatic output enable).
+  * @param  TIMx: where x can be  1 or 8 to select the TIM 
+  * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure that
+  *         contains the BDTR Register configuration  information for the TIM peripheral.
+  * @retval None
+  */
+void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_TIM_OSSR_STATE(TIM_BDTRInitStruct->TIM_OSSRState));
+  assert_param(IS_TIM_OSSI_STATE(TIM_BDTRInitStruct->TIM_OSSIState));
+  assert_param(IS_TIM_LOCK_LEVEL(TIM_BDTRInitStruct->TIM_LOCKLevel));
+  assert_param(IS_TIM_BREAK_STATE(TIM_BDTRInitStruct->TIM_Break));
+  assert_param(IS_TIM_BREAK_POLARITY(TIM_BDTRInitStruct->TIM_BreakPolarity));
+  assert_param(IS_TIM_AUTOMATIC_OUTPUT_STATE(TIM_BDTRInitStruct->TIM_AutomaticOutput));
+
+  /* Set the Lock level, the Break enable Bit and the Polarity, the OSSR State,
+     the OSSI State, the dead time value and the Automatic Output Enable Bit */
+  TIMx->BDTR = (uint32_t)TIM_BDTRInitStruct->TIM_OSSRState | TIM_BDTRInitStruct->TIM_OSSIState |
+             TIM_BDTRInitStruct->TIM_LOCKLevel | TIM_BDTRInitStruct->TIM_DeadTime |
+             TIM_BDTRInitStruct->TIM_Break | TIM_BDTRInitStruct->TIM_BreakPolarity |
+             TIM_BDTRInitStruct->TIM_AutomaticOutput;
+}
+
+/**
+  * @brief  Fills each TIM_BDTRInitStruct member with its default value.
+  * @param  TIM_BDTRInitStruct: pointer to a TIM_BDTRInitTypeDef structure which
+  *         will be initialized.
+  * @retval None
+  */
+void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct)
+{
+  /* Set the default configuration */
+  TIM_BDTRInitStruct->TIM_OSSRState = TIM_OSSRState_Disable;
+  TIM_BDTRInitStruct->TIM_OSSIState = TIM_OSSIState_Disable;
+  TIM_BDTRInitStruct->TIM_LOCKLevel = TIM_LOCKLevel_OFF;
+  TIM_BDTRInitStruct->TIM_DeadTime = 0x00;
+  TIM_BDTRInitStruct->TIM_Break = TIM_Break_Disable;
+  TIM_BDTRInitStruct->TIM_BreakPolarity = TIM_BreakPolarity_Low;
+  TIM_BDTRInitStruct->TIM_AutomaticOutput = TIM_AutomaticOutput_Disable;
+}
+
+/**
+  * @brief  Enables or disables the TIM peripheral Main Outputs.
+  * @param  TIMx: where x can be 1 or 8 to select the TIMx peripheral.
+  * @param  NewState: new state of the TIM peripheral Main Outputs.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the TIM Main Output */
+    TIMx->BDTR |= TIM_BDTR_MOE;
+  }
+  else
+  {
+    /* Disable the TIM Main Output */
+    TIMx->BDTR &= (uint16_t)~TIM_BDTR_MOE;
+  }  
+}
+
+/**
+  * @brief  Selects the TIM peripheral Commutation event.
+  * @param  TIMx: where x can be  1 or 8 to select the TIMx peripheral
+  * @param  NewState: new state of the Commutation event.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the COM Bit */
+    TIMx->CR2 |= TIM_CR2_CCUS;
+  }
+  else
+  {
+    /* Reset the COM Bit */
+    TIMx->CR2 &= (uint16_t)~TIM_CR2_CCUS;
+  }
+}
+
+/**
+  * @brief  Sets or Resets the TIM peripheral Capture Compare Preload Control bit.
+  * @param  TIMx: where x can be  1 or 8 to select the TIMx peripheral
+  * @param  NewState: new state of the Capture Compare Preload Control bit
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST4_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Set the CCPC Bit */
+    TIMx->CR2 |= TIM_CR2_CCPC;
+  }
+  else
+  {
+    /* Reset the CCPC Bit */
+    TIMx->CR2 &= (uint16_t)~TIM_CR2_CCPC;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group5 Interrupts DMA and flags management functions
+ *  @brief    Interrupts, DMA and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                 Interrupts, DMA and flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified TIM interrupts.
+  * @param  TIMx: where x can be 1 to 14 to select the TIMx peripheral.
+  * @param  TIM_IT: specifies the TIM interrupts sources to be enabled or disabled.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM_IT_Update: TIM update Interrupt source
+  *            @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+  *            @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+  *            @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+  *            @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+  *            @arg TIM_IT_COM: TIM Commutation Interrupt source
+  *            @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+  *            @arg TIM_IT_Break: TIM Break Interrupt source
+  *  
+  * @note   For TIM6 and TIM7 only the parameter TIM_IT_Update can be used
+  * @note   For TIM9 and TIM12 only one of the following parameters can be used: TIM_IT_Update,
+  *          TIM_IT_CC1, TIM_IT_CC2 or TIM_IT_Trigger. 
+  * @note   For TIM10, TIM11, TIM13 and TIM14 only one of the following parameters can
+  *          be used: TIM_IT_Update or TIM_IT_CC1   
+  * @note   TIM_IT_COM and TIM_IT_Break can be used only with TIM1 and TIM8 
+  *        
+  * @param  NewState: new state of the TIM interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState)
+{  
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_IT(TIM_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the Interrupt sources */
+    TIMx->DIER |= TIM_IT;
+  }
+  else
+  {
+    /* Disable the Interrupt sources */
+    TIMx->DIER &= (uint16_t)~TIM_IT;
+  }
+}
+
+/**
+  * @brief  Configures the TIMx event to be generate by software.
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
+  * @param  TIM_EventSource: specifies the event source.
+  *          This parameter can be one or more of the following values:	   
+  *            @arg TIM_EventSource_Update: Timer update Event source
+  *            @arg TIM_EventSource_CC1: Timer Capture Compare 1 Event source
+  *            @arg TIM_EventSource_CC2: Timer Capture Compare 2 Event source
+  *            @arg TIM_EventSource_CC3: Timer Capture Compare 3 Event source
+  *            @arg TIM_EventSource_CC4: Timer Capture Compare 4 Event source
+  *            @arg TIM_EventSource_COM: Timer COM event source  
+  *            @arg TIM_EventSource_Trigger: Timer Trigger Event source
+  *            @arg TIM_EventSource_Break: Timer Break event source
+  * 
+  * @note   TIM6 and TIM7 can only generate an update event. 
+  * @note   TIM_EventSource_COM and TIM_EventSource_Break are used only with TIM1 and TIM8.
+  *        
+  * @retval None
+  */
+void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_EVENT_SOURCE(TIM_EventSource));
+ 
+  /* Set the event sources */
+  TIMx->EGR = TIM_EventSource;
+}
+
+/**
+  * @brief  Checks whether the specified TIM flag is set or not.
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
+  * @param  TIM_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_FLAG_Update: TIM update Flag
+  *            @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+  *            @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+  *            @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+  *            @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+  *            @arg TIM_FLAG_COM: TIM Commutation Flag
+  *            @arg TIM_FLAG_Trigger: TIM Trigger Flag
+  *            @arg TIM_FLAG_Break: TIM Break Flag
+  *            @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
+  *            @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
+  *            @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
+  *            @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
+  *
+  * @note   TIM6 and TIM7 can have only one update flag. 
+  * @note   TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.    
+  *
+  * @retval The new state of TIM_FLAG (SET or RESET).
+  */
+FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
+{ 
+  ITStatus bitstatus = RESET;  
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_GET_FLAG(TIM_FLAG));
+
+  
+  if ((TIMx->SR & TIM_FLAG) != (uint16_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the TIMx's pending flags.
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
+  * @param  TIM_FLAG: specifies the flag bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM_FLAG_Update: TIM update Flag
+  *            @arg TIM_FLAG_CC1: TIM Capture Compare 1 Flag
+  *            @arg TIM_FLAG_CC2: TIM Capture Compare 2 Flag
+  *            @arg TIM_FLAG_CC3: TIM Capture Compare 3 Flag
+  *            @arg TIM_FLAG_CC4: TIM Capture Compare 4 Flag
+  *            @arg TIM_FLAG_COM: TIM Commutation Flag
+  *            @arg TIM_FLAG_Trigger: TIM Trigger Flag
+  *            @arg TIM_FLAG_Break: TIM Break Flag
+  *            @arg TIM_FLAG_CC1OF: TIM Capture Compare 1 over capture Flag
+  *            @arg TIM_FLAG_CC2OF: TIM Capture Compare 2 over capture Flag
+  *            @arg TIM_FLAG_CC3OF: TIM Capture Compare 3 over capture Flag
+  *            @arg TIM_FLAG_CC4OF: TIM Capture Compare 4 over capture Flag
+  *
+  * @note   TIM6 and TIM7 can have only one update flag. 
+  * @note   TIM_FLAG_COM and TIM_FLAG_Break are used only with TIM1 and TIM8.
+  *    
+  * @retval None
+  */
+void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG)
+{  
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+   
+  /* Clear the flags */
+  TIMx->SR = (uint16_t)~TIM_FLAG;
+}
+
+/**
+  * @brief  Checks whether the TIM interrupt has occurred or not.
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
+  * @param  TIM_IT: specifies the TIM interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_IT_Update: TIM update Interrupt source
+  *            @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+  *            @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+  *            @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+  *            @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+  *            @arg TIM_IT_COM: TIM Commutation Interrupt source
+  *            @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+  *            @arg TIM_IT_Break: TIM Break Interrupt source
+  *
+  * @note   TIM6 and TIM7 can generate only an update interrupt.
+  * @note   TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
+  *     
+  * @retval The new state of the TIM_IT(SET or RESET).
+  */
+ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+  ITStatus bitstatus = RESET;  
+  uint16_t itstatus = 0x0, itenable = 0x0;
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+  assert_param(IS_TIM_GET_IT(TIM_IT));
+   
+  itstatus = TIMx->SR & TIM_IT;
+  
+  itenable = TIMx->DIER & TIM_IT;
+  if ((itstatus != (uint16_t)RESET) && (itenable != (uint16_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the TIMx's interrupt pending bits.
+  * @param  TIMx: where x can be 1 to 14 to select the TIM peripheral.
+  * @param  TIM_IT: specifies the pending bit to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM_IT_Update: TIM1 update Interrupt source
+  *            @arg TIM_IT_CC1: TIM Capture Compare 1 Interrupt source
+  *            @arg TIM_IT_CC2: TIM Capture Compare 2 Interrupt source
+  *            @arg TIM_IT_CC3: TIM Capture Compare 3 Interrupt source
+  *            @arg TIM_IT_CC4: TIM Capture Compare 4 Interrupt source
+  *            @arg TIM_IT_COM: TIM Commutation Interrupt source
+  *            @arg TIM_IT_Trigger: TIM Trigger Interrupt source
+  *            @arg TIM_IT_Break: TIM Break Interrupt source
+  *
+  * @note   TIM6 and TIM7 can generate only an update interrupt.
+  * @note   TIM_IT_COM and TIM_IT_Break are used only with TIM1 and TIM8.
+  *      
+  * @retval None
+  */
+void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_ALL_PERIPH(TIMx));
+
+  /* Clear the IT pending Bit */
+  TIMx->SR = (uint16_t)~TIM_IT;
+}
+
+/**
+  * @brief  Configures the TIMx's DMA interface.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_DMABase: DMA Base address.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_DMABase_CR1  
+  *            @arg TIM_DMABase_CR2
+  *            @arg TIM_DMABase_SMCR
+  *            @arg TIM_DMABase_DIER
+  *            @arg TIM1_DMABase_SR
+  *            @arg TIM_DMABase_EGR
+  *            @arg TIM_DMABase_CCMR1
+  *            @arg TIM_DMABase_CCMR2
+  *            @arg TIM_DMABase_CCER
+  *            @arg TIM_DMABase_CNT   
+  *            @arg TIM_DMABase_PSC   
+  *            @arg TIM_DMABase_ARR
+  *            @arg TIM_DMABase_RCR
+  *            @arg TIM_DMABase_CCR1
+  *            @arg TIM_DMABase_CCR2
+  *            @arg TIM_DMABase_CCR3  
+  *            @arg TIM_DMABase_CCR4
+  *            @arg TIM_DMABase_BDTR
+  *            @arg TIM_DMABase_DCR
+  * @param  TIM_DMABurstLength: DMA Burst length. This parameter can be one value
+  *         between: TIM_DMABurstLength_1Transfer and TIM_DMABurstLength_18Transfers.
+  * @retval None
+  */
+void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_DMA_BASE(TIM_DMABase)); 
+  assert_param(IS_TIM_DMA_LENGTH(TIM_DMABurstLength));
+
+  /* Set the DMA Base and the DMA Burst Length */
+  TIMx->DCR = TIM_DMABase | TIM_DMABurstLength;
+}
+
+/**
+  * @brief  Enables or disables the TIMx's DMA Requests.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
+  * @param  TIM_DMASource: specifies the DMA Request sources.
+  *          This parameter can be any combination of the following values:
+  *            @arg TIM_DMA_Update: TIM update Interrupt source
+  *            @arg TIM_DMA_CC1: TIM Capture Compare 1 DMA source
+  *            @arg TIM_DMA_CC2: TIM Capture Compare 2 DMA source
+  *            @arg TIM_DMA_CC3: TIM Capture Compare 3 DMA source
+  *            @arg TIM_DMA_CC4: TIM Capture Compare 4 DMA source
+  *            @arg TIM_DMA_COM: TIM Commutation DMA source
+  *            @arg TIM_DMA_Trigger: TIM Trigger DMA source
+  * @param  NewState: new state of the DMA Request sources.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState)
+{ 
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST5_PERIPH(TIMx)); 
+  assert_param(IS_TIM_DMA_SOURCE(TIM_DMASource));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA sources */
+    TIMx->DIER |= TIM_DMASource; 
+  }
+  else
+  {
+    /* Disable the DMA sources */
+    TIMx->DIER &= (uint16_t)~TIM_DMASource;
+  }
+}
+
+/**
+  * @brief  Selects the TIMx peripheral Capture Compare DMA source.
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  NewState: new state of the Capture Compare DMA source
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the CCDS Bit */
+    TIMx->CR2 |= TIM_CR2_CCDS;
+  }
+  else
+  {
+    /* Reset the CCDS Bit */
+    TIMx->CR2 &= (uint16_t)~TIM_CR2_CCDS;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group6 Clocks management functions
+ *  @brief    Clocks management functions
+ *
+@verbatim   
+ ===============================================================================
+                         Clocks management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the TIMx internal Clock
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
+  * @retval None
+  */
+void TIM_InternalClockConfig(TIM_TypeDef* TIMx)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+
+  /* Disable slave mode to clock the prescaler directly with the internal clock */
+  TIMx->SMCR &=  (uint16_t)~TIM_SMCR_SMS;
+}
+
+/**
+  * @brief  Configures the TIMx Internal Trigger as External Clock
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
+  * @param  TIM_InputTriggerSource: Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal Trigger 0
+  *            @arg TIM_TS_ITR1: Internal Trigger 1
+  *            @arg TIM_TS_ITR2: Internal Trigger 2
+  *            @arg TIM_TS_ITR3: Internal Trigger 3
+  * @retval None
+  */
+void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_INTERNAL_TRIGGER_SELECTION(TIM_InputTriggerSource));
+
+  /* Select the Internal Trigger */
+  TIM_SelectInputTrigger(TIMx, TIM_InputTriggerSource);
+
+  /* Select the External clock mode1 */
+  TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+  * @brief  Configures the TIMx Trigger as External Clock
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14  
+  *         to select the TIM peripheral.
+  * @param  TIM_TIxExternalCLKSource: Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TIxExternalCLK1Source_TI1ED: TI1 Edge Detector
+  *            @arg TIM_TIxExternalCLK1Source_TI1: Filtered Timer Input 1
+  *            @arg TIM_TIxExternalCLK1Source_TI2: Filtered Timer Input 2
+  * @param  TIM_ICPolarity: specifies the TIx Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  * @param  ICFilter: specifies the filter value.
+  *          This parameter must be a value between 0x0 and 0xF.
+  * @retval None
+  */
+void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
+                                uint16_t TIM_ICPolarity, uint16_t ICFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx));
+  assert_param(IS_TIM_IC_POLARITY(TIM_ICPolarity));
+  assert_param(IS_TIM_IC_FILTER(ICFilter));
+
+  /* Configure the Timer Input Clock Source */
+  if (TIM_TIxExternalCLKSource == TIM_TIxExternalCLK1Source_TI2)
+  {
+    TI2_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+  }
+  else
+  {
+    TI1_Config(TIMx, TIM_ICPolarity, TIM_ICSelection_DirectTI, ICFilter);
+  }
+  /* Select the Trigger source */
+  TIM_SelectInputTrigger(TIMx, TIM_TIxExternalCLKSource);
+  /* Select the External clock mode1 */
+  TIMx->SMCR |= TIM_SlaveMode_External1;
+}
+
+/**
+  * @brief  Configures the External clock Mode1
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+  *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+  *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+  * @param  ExtTRGFilter: External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+                            uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+  uint16_t tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+  /* Configure the ETR Clock source */
+  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+  
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+
+  /* Reset the SMS Bits */
+  tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
+
+  /* Select the External clock mode1 */
+  tmpsmcr |= TIM_SlaveMode_External1;
+
+  /* Select the Trigger selection : ETRF */
+  tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
+  tmpsmcr |= TIM_TS_ETRF;
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Configures the External clock Mode2
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+  *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+  *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+  * @param  ExtTRGFilter: External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, 
+                             uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+
+  /* Configure the ETR Clock source */
+  TIM_ETRConfig(TIMx, TIM_ExtTRGPrescaler, TIM_ExtTRGPolarity, ExtTRGFilter);
+
+  /* Enable the External clock mode2 */
+  TIMx->SMCR |= TIM_SMCR_ECE;
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group7 Synchronization management functions
+ *  @brief    Synchronization management functions 
+ *
+@verbatim   
+ ===============================================================================
+                       Synchronization management functions
+ ===============================================================================  
+                   
+       ===================================================================      
+              TIM Driver: how to use it in synchronization Mode
+       =================================================================== 
+       Case of two/several Timers
+       **************************
+       1. Configure the Master Timers using the following functions:
+          - void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource); 
+          - void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);  
+       2. Configure the Slave Timers using the following functions: 
+          - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);  
+          - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); 
+          
+       Case of Timers and external trigger(ETR pin)
+       ********************************************       
+       1. Configure the External trigger using this function:
+          - void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
+                               uint16_t ExtTRGFilter);
+       2. Configure the Slave Timers using the following functions: 
+          - void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);  
+          - void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode); 
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Selects the Input Trigger source
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14  
+  *         to select the TIM peripheral.
+  * @param  TIM_InputTriggerSource: The Input Trigger source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_TS_ITR0: Internal Trigger 0
+  *            @arg TIM_TS_ITR1: Internal Trigger 1
+  *            @arg TIM_TS_ITR2: Internal Trigger 2
+  *            @arg TIM_TS_ITR3: Internal Trigger 3
+  *            @arg TIM_TS_TI1F_ED: TI1 Edge Detector
+  *            @arg TIM_TS_TI1FP1: Filtered Timer Input 1
+  *            @arg TIM_TS_TI2FP2: Filtered Timer Input 2
+  *            @arg TIM_TS_ETRF: External Trigger input
+  * @retval None
+  */
+void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource)
+{
+  uint16_t tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST1_PERIPH(TIMx)); 
+  assert_param(IS_TIM_TRIGGER_SELECTION(TIM_InputTriggerSource));
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+
+  /* Reset the TS Bits */
+  tmpsmcr &= (uint16_t)~TIM_SMCR_TS;
+
+  /* Set the Input Trigger source */
+  tmpsmcr |= TIM_InputTriggerSource;
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+
+/**
+  * @brief  Selects the TIMx Trigger Output Mode.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 6, 7 or 8 to select the TIM peripheral.
+  *     
+  * @param  TIM_TRGOSource: specifies the Trigger Output source.
+  *   This parameter can be one of the following values:
+  *
+  *  - For all TIMx
+  *            @arg TIM_TRGOSource_Reset:  The UG bit in the TIM_EGR register is used as the trigger output(TRGO)
+  *            @arg TIM_TRGOSource_Enable: The Counter Enable CEN is used as the trigger output(TRGO)
+  *            @arg TIM_TRGOSource_Update: The update event is selected as the trigger output(TRGO)
+  *
+  *  - For all TIMx except TIM6 and TIM7
+  *            @arg TIM_TRGOSource_OC1: The trigger output sends a positive pulse when the CC1IF flag
+  *                                     is to be set, as soon as a capture or compare match occurs(TRGO)
+  *            @arg TIM_TRGOSource_OC1Ref: OC1REF signal is used as the trigger output(TRGO)
+  *            @arg TIM_TRGOSource_OC2Ref: OC2REF signal is used as the trigger output(TRGO)
+  *            @arg TIM_TRGOSource_OC3Ref: OC3REF signal is used as the trigger output(TRGO)
+  *            @arg TIM_TRGOSource_OC4Ref: OC4REF signal is used as the trigger output(TRGO)
+  *
+  * @retval None
+  */
+void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST5_PERIPH(TIMx));
+  assert_param(IS_TIM_TRGO_SOURCE(TIM_TRGOSource));
+
+  /* Reset the MMS Bits */
+  TIMx->CR2 &= (uint16_t)~TIM_CR2_MMS;
+  /* Select the TRGO source */
+  TIMx->CR2 |=  TIM_TRGOSource;
+}
+
+/**
+  * @brief  Selects the TIMx Slave Mode.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
+  * @param  TIM_SlaveMode: specifies the Timer Slave Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_SlaveMode_Reset: Rising edge of the selected trigger signal(TRGI) reinitialize 
+  *                                      the counter and triggers an update of the registers
+  *            @arg TIM_SlaveMode_Gated:     The counter clock is enabled when the trigger signal (TRGI) is high
+  *            @arg TIM_SlaveMode_Trigger:   The counter starts at a rising edge of the trigger TRGI
+  *            @arg TIM_SlaveMode_External1: Rising edges of the selected trigger (TRGI) clock the counter
+  * @retval None
+  */
+void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_SLAVE_MODE(TIM_SlaveMode));
+
+  /* Reset the SMS Bits */
+  TIMx->SMCR &= (uint16_t)~TIM_SMCR_SMS;
+
+  /* Select the Slave Mode */
+  TIMx->SMCR |= TIM_SlaveMode;
+}
+
+/**
+  * @brief  Sets or Resets the TIMx Master/Slave Mode.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM peripheral.
+  * @param  TIM_MasterSlaveMode: specifies the Timer Master Slave Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_MasterSlaveMode_Enable: synchronization between the current timer
+  *                                             and its slaves (through TRGO)
+  *            @arg TIM_MasterSlaveMode_Disable: No action
+  * @retval None
+  */
+void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_MSM_STATE(TIM_MasterSlaveMode));
+
+  /* Reset the MSM Bit */
+  TIMx->SMCR &= (uint16_t)~TIM_SMCR_MSM;
+  
+  /* Set or Reset the MSM Bit */
+  TIMx->SMCR |= TIM_MasterSlaveMode;
+}
+
+/**
+  * @brief  Configures the TIMx External Trigger (ETR).
+  * @param  TIMx: where x can be  1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ExtTRGPrescaler: The external Trigger Prescaler.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ExtTRGPSC_OFF: ETRP Prescaler OFF.
+  *            @arg TIM_ExtTRGPSC_DIV2: ETRP frequency divided by 2.
+  *            @arg TIM_ExtTRGPSC_DIV4: ETRP frequency divided by 4.
+  *            @arg TIM_ExtTRGPSC_DIV8: ETRP frequency divided by 8.
+  * @param  TIM_ExtTRGPolarity: The external Trigger Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ExtTRGPolarity_Inverted: active low or falling edge active.
+  *            @arg TIM_ExtTRGPolarity_NonInverted: active high or rising edge active.
+  * @param  ExtTRGFilter: External Trigger Filter.
+  *          This parameter must be a value between 0x00 and 0x0F
+  * @retval None
+  */
+void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
+                   uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter)
+{
+  uint16_t tmpsmcr = 0;
+
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST3_PERIPH(TIMx));
+  assert_param(IS_TIM_EXT_PRESCALER(TIM_ExtTRGPrescaler));
+  assert_param(IS_TIM_EXT_POLARITY(TIM_ExtTRGPolarity));
+  assert_param(IS_TIM_EXT_FILTER(ExtTRGFilter));
+
+  tmpsmcr = TIMx->SMCR;
+
+  /* Reset the ETR Bits */
+  tmpsmcr &= SMCR_ETR_MASK;
+
+  /* Set the Prescaler, the Filter value and the Polarity */
+  tmpsmcr |= (uint16_t)(TIM_ExtTRGPrescaler | (uint16_t)(TIM_ExtTRGPolarity | (uint16_t)(ExtTRGFilter << (uint16_t)8)));
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group8 Specific interface management functions
+ *  @brief    Specific interface management functions 
+ *
+@verbatim   
+ ===============================================================================
+                    Specific interface management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the TIMx Encoder Interface.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
+  * @param  TIM_EncoderMode: specifies the TIMx Encoder Mode.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_EncoderMode_TI1: Counter counts on TI1FP1 edge depending on TI2FP2 level.
+  *            @arg TIM_EncoderMode_TI2: Counter counts on TI2FP2 edge depending on TI1FP1 level.
+  *            @arg TIM_EncoderMode_TI12: Counter counts on both TI1FP1 and TI2FP2 edges depending
+  *                                       on the level of the other input.
+  * @param  TIM_IC1Polarity: specifies the IC1 Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Falling: IC Falling edge.
+  *            @arg TIM_ICPolarity_Rising: IC Rising edge.
+  * @param  TIM_IC2Polarity: specifies the IC2 Polarity
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Falling: IC Falling edge.
+  *            @arg TIM_ICPolarity_Rising: IC Rising edge.
+  * @retval None
+  */
+void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
+                                uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity)
+{
+  uint16_t tmpsmcr = 0;
+  uint16_t tmpccmr1 = 0;
+  uint16_t tmpccer = 0;
+    
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_TIM_ENCODER_MODE(TIM_EncoderMode));
+  assert_param(IS_TIM_IC_POLARITY(TIM_IC1Polarity));
+  assert_param(IS_TIM_IC_POLARITY(TIM_IC2Polarity));
+
+  /* Get the TIMx SMCR register value */
+  tmpsmcr = TIMx->SMCR;
+
+  /* Get the TIMx CCMR1 register value */
+  tmpccmr1 = TIMx->CCMR1;
+
+  /* Get the TIMx CCER register value */
+  tmpccer = TIMx->CCER;
+
+  /* Set the encoder Mode */
+  tmpsmcr &= (uint16_t)~TIM_SMCR_SMS;
+  tmpsmcr |= TIM_EncoderMode;
+
+  /* Select the Capture Compare 1 and the Capture Compare 2 as input */
+  tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_CC2S);
+  tmpccmr1 |= TIM_CCMR1_CC1S_0 | TIM_CCMR1_CC2S_0;
+
+  /* Set the TI1 and the TI2 Polarities */
+  tmpccer &= ((uint16_t)~TIM_CCER_CC1P) & ((uint16_t)~TIM_CCER_CC2P);
+  tmpccer |= (uint16_t)(TIM_IC1Polarity | (uint16_t)(TIM_IC2Polarity << (uint16_t)4));
+
+  /* Write to TIMx SMCR */
+  TIMx->SMCR = tmpsmcr;
+
+  /* Write to TIMx CCMR1 */
+  TIMx->CCMR1 = tmpccmr1;
+
+  /* Write to TIMx CCER */
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Enables or disables the TIMx's Hall sensor interface.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
+  * @param  NewState: new state of the TIMx Hall sensor interface.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_TIM_LIST2_PERIPH(TIMx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  if (NewState != DISABLE)
+  {
+    /* Set the TI1S Bit */
+    TIMx->CR2 |= TIM_CR2_TI1S;
+  }
+  else
+  {
+    /* Reset the TI1S Bit */
+    TIMx->CR2 &= (uint16_t)~TIM_CR2_TI1S;
+  }
+}
+/**
+  * @}
+  */
+
+/** @defgroup TIM_Group9 Specific remapping management function
+ *  @brief   Specific remapping management function
+ *
+@verbatim   
+ ===============================================================================
+                     Specific remapping management function
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the TIM2, TIM5 and TIM11 Remapping input capabilities.
+  * @param  TIMx: where x can be 2, 5 or 11 to select the TIM peripheral.
+  * @param  TIM_Remap: specifies the TIM input remapping source.
+  *          This parameter can be one of the following values:
+  *            @arg TIM2_TIM8_TRGO: TIM2 ITR1 input is connected to TIM8 Trigger output(default)
+  *            @arg TIM2_ETH_PTP:   TIM2 ITR1 input is connected to ETH PTP trogger output.
+  *            @arg TIM2_USBFS_SOF: TIM2 ITR1 input is connected to USB FS SOF. 
+  *            @arg TIM2_USBHS_SOF: TIM2 ITR1 input is connected to USB HS SOF. 
+  *            @arg TIM5_GPIO:      TIM5 CH4 input is connected to dedicated Timer pin(default)
+  *            @arg TIM5_LSI:       TIM5 CH4 input is connected to LSI clock.
+  *            @arg TIM5_LSE:       TIM5 CH4 input is connected to LSE clock.
+  *            @arg TIM5_RTC:       TIM5 CH4 input is connected to RTC Output event.
+  *            @arg TIM11_GPIO:     TIM11 CH4 input is connected to dedicated Timer pin(default) 
+  *            @arg TIM11_HSE:      TIM11 CH4 input is connected to HSE_RTC clock
+  *                                 (HSE divided by a programmable prescaler)  
+  * @retval None
+  */
+void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap)
+{
+ /* Check the parameters */
+  assert_param(IS_TIM_LIST6_PERIPH(TIMx));
+  assert_param(IS_TIM_REMAP(TIM_Remap));
+
+  /* Set the Timer remapping configuration */
+  TIMx->OR =  TIM_Remap;
+}
+/**
+  * @}
+  */
+
+/**
+  * @brief  Configure the TI1 as Input.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9, 10, 11, 12, 13 or 14 
+  *         to select the TIM peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  *            @arg TIM_ICPolarity_BothEdge  
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 1 is selected to be connected to IC1.
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 1 is selected to be connected to IC2.
+  *            @arg TIM_ICSelection_TRC: TIM Input 1 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI1_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+  uint16_t tmpccmr1 = 0, tmpccer = 0;
+
+  /* Disable the Channel 1: Reset the CC1E Bit */
+  TIMx->CCER &= (uint16_t)~TIM_CCER_CC1E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+
+  /* Select the Input and set the filter */
+  tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR1_IC1F);
+  tmpccmr1 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+
+  /* Select the Polarity and set the CC1E Bit */
+  tmpccer &= (uint16_t)~(TIM_CCER_CC1P | TIM_CCER_CC1NP);
+  tmpccer |= (uint16_t)(TIM_ICPolarity | (uint16_t)TIM_CCER_CC1E);
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI2 as Input.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5, 8, 9 or 12 to select the TIM 
+  *         peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  *            @arg TIM_ICPolarity_BothEdge   
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 2 is selected to be connected to IC2.
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 2 is selected to be connected to IC1.
+  *            @arg TIM_ICSelection_TRC: TIM Input 2 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI2_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+  uint16_t tmpccmr1 = 0, tmpccer = 0, tmp = 0;
+
+  /* Disable the Channel 2: Reset the CC2E Bit */
+  TIMx->CCER &= (uint16_t)~TIM_CCER_CC2E;
+  tmpccmr1 = TIMx->CCMR1;
+  tmpccer = TIMx->CCER;
+  tmp = (uint16_t)(TIM_ICPolarity << 4);
+
+  /* Select the Input and set the filter */
+  tmpccmr1 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
+  tmpccmr1 |= (uint16_t)(TIM_ICFilter << 12);
+  tmpccmr1 |= (uint16_t)(TIM_ICSelection << 8);
+
+  /* Select the Polarity and set the CC2E Bit */
+  tmpccer &= (uint16_t)~(TIM_CCER_CC2P | TIM_CCER_CC2NP);
+  tmpccer |=  (uint16_t)(tmp | (uint16_t)TIM_CCER_CC2E);
+
+  /* Write to TIMx CCMR1 and CCER registers */
+  TIMx->CCMR1 = tmpccmr1 ;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI3 as Input.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  *            @arg TIM_ICPolarity_BothEdge         
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 3 is selected to be connected to IC3.
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 3 is selected to be connected to IC4.
+  *            @arg TIM_ICSelection_TRC: TIM Input 3 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI3_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+  /* Disable the Channel 3: Reset the CC3E Bit */
+  TIMx->CCER &= (uint16_t)~TIM_CCER_CC3E;
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+  tmp = (uint16_t)(TIM_ICPolarity << 8);
+
+  /* Select the Input and set the filter */
+  tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC1S) & ((uint16_t)~TIM_CCMR2_IC3F);
+  tmpccmr2 |= (uint16_t)(TIM_ICSelection | (uint16_t)(TIM_ICFilter << (uint16_t)4));
+
+  /* Select the Polarity and set the CC3E Bit */
+  tmpccer &= (uint16_t)~(TIM_CCER_CC3P | TIM_CCER_CC3NP);
+  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC3E);
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer;
+}
+
+/**
+  * @brief  Configure the TI4 as Input.
+  * @param  TIMx: where x can be 1, 2, 3, 4, 5 or 8 to select the TIM peripheral.
+  * @param  TIM_ICPolarity : The Input Polarity.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICPolarity_Rising
+  *            @arg TIM_ICPolarity_Falling
+  *            @arg TIM_ICPolarity_BothEdge     
+  * @param  TIM_ICSelection: specifies the input to be used.
+  *          This parameter can be one of the following values:
+  *            @arg TIM_ICSelection_DirectTI: TIM Input 4 is selected to be connected to IC4.
+  *            @arg TIM_ICSelection_IndirectTI: TIM Input 4 is selected to be connected to IC3.
+  *            @arg TIM_ICSelection_TRC: TIM Input 4 is selected to be connected to TRC.
+  * @param  TIM_ICFilter: Specifies the Input Capture Filter.
+  *          This parameter must be a value between 0x00 and 0x0F.
+  * @retval None
+  */
+static void TI4_Config(TIM_TypeDef* TIMx, uint16_t TIM_ICPolarity, uint16_t TIM_ICSelection,
+                       uint16_t TIM_ICFilter)
+{
+  uint16_t tmpccmr2 = 0, tmpccer = 0, tmp = 0;
+
+  /* Disable the Channel 4: Reset the CC4E Bit */
+  TIMx->CCER &= (uint16_t)~TIM_CCER_CC4E;
+  tmpccmr2 = TIMx->CCMR2;
+  tmpccer = TIMx->CCER;
+  tmp = (uint16_t)(TIM_ICPolarity << 12);
+
+  /* Select the Input and set the filter */
+  tmpccmr2 &= ((uint16_t)~TIM_CCMR1_CC2S) & ((uint16_t)~TIM_CCMR1_IC2F);
+  tmpccmr2 |= (uint16_t)(TIM_ICSelection << 8);
+  tmpccmr2 |= (uint16_t)(TIM_ICFilter << 12);
+
+  /* Select the Polarity and set the CC4E Bit */
+  tmpccer &= (uint16_t)~(TIM_CCER_CC4P | TIM_CCER_CC4NP);
+  tmpccer |= (uint16_t)(tmp | (uint16_t)TIM_CCER_CC4E);
+
+  /* Write to TIMx CCMR2 and CCER registers */
+  TIMx->CCMR2 = tmpccmr2;
+  TIMx->CCER = tmpccer ;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c
new file mode 100644
index 0000000000..06d5d94a09
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_usart.c
@@ -0,0 +1,1462 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_usart.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Universal synchronous asynchronous receiver
+  *          transmitter (USART):           
+  *           - Initialization and Configuration
+  *           - Data transfers
+  *           - Multi-Processor Communication
+  *           - LIN mode
+  *           - Half-duplex mode
+  *           - Smartcard mode
+  *           - IrDA mode
+  *           - DMA transfers management
+  *           - Interrupts and flags management 
+  *           
+  *  @verbatim
+  *      
+  *          ===================================================================
+  *                                 How to use this driver
+  *          ===================================================================
+  *          1. Enable peripheral clock using the follwoing functions
+  *             RCC_APB2PeriphClockCmd(RCC_APB2Periph_USARTx, ENABLE) for USART1 and USART6 
+  *             RCC_APB1PeriphClockCmd(RCC_APB1Periph_USARTx, ENABLE) for USART2, USART3, UART4 or UART5.
+  *
+  *          2.  According to the USART mode, enable the GPIO clocks using 
+  *              RCC_AHB1PeriphClockCmd() function. (The I/O can be TX, RX, CTS, 
+  *              or/and SCLK). 
+  *
+  *          3. Peripheral's alternate function: 
+  *                 - Connect the pin to the desired peripherals' Alternate 
+  *                   Function (AF) using GPIO_PinAFConfig() function
+  *                 - Configure the desired pin in alternate function by:
+  *                   GPIO_InitStruct->GPIO_Mode = GPIO_Mode_AF
+  *                 - Select the type, pull-up/pull-down and output speed via 
+  *                   GPIO_PuPd, GPIO_OType and GPIO_Speed members
+  *                 - Call GPIO_Init() function
+  *        
+  *          4. Program the Baud Rate, Word Length , Stop Bit, Parity, Hardware 
+  *             flow control and Mode(Receiver/Transmitter) using the USART_Init()
+  *             function.
+  *
+  *          5. For synchronous mode, enable the clock and program the polarity,
+  *             phase and last bit using the USART_ClockInit() function.
+  *
+  *          5. Enable the NVIC and the corresponding interrupt using the function 
+  *             USART_ITConfig() if you need to use interrupt mode. 
+  *
+  *          6. When using the DMA mode 
+  *                   - Configure the DMA using DMA_Init() function
+  *                   - Active the needed channel Request using USART_DMACmd() function
+  * 
+  *          7. Enable the USART using the USART_Cmd() function.
+  * 
+  *          8. Enable the DMA using the DMA_Cmd() function, when using DMA mode. 
+  *
+  *          Refer to Multi-Processor, LIN, half-duplex, Smartcard, IrDA sub-sections
+  *          for more details
+  *          
+  *          In order to reach higher communication baudrates, it is possible to
+  *          enable the oversampling by 8 mode using the function USART_OverSampling8Cmd().
+  *          This function should be called after enabling the USART clock (RCC_APBxPeriphClockCmd())
+  *          and before calling the function USART_Init().
+  *          
+  *  @endverbatim
+  *        
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************  
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_usart.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup USART 
+  * @brief USART driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/*!< USART CR1 register clear Mask ((~(uint16_t)0xE9F3)) */
+#define CR1_CLEAR_MASK            ((uint16_t)(USART_CR1_M | USART_CR1_PCE | \
+                                              USART_CR1_PS | USART_CR1_TE | \
+                                              USART_CR1_RE))
+
+/*!< USART CR2 register clock bits clear Mask ((~(uint16_t)0xF0FF)) */
+#define CR2_CLOCK_CLEAR_MASK      ((uint16_t)(USART_CR2_CLKEN | USART_CR2_CPOL | \
+                                              USART_CR2_CPHA | USART_CR2_LBCL))
+
+/*!< USART CR3 register clear Mask ((~(uint16_t)0xFCFF)) */
+#define CR3_CLEAR_MASK            ((uint16_t)(USART_CR3_RTSE | USART_CR3_CTSE))
+
+/*!< USART Interrupts mask */
+#define IT_MASK                   ((uint16_t)0x001F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup USART_Private_Functions
+  * @{
+  */
+
+/** @defgroup USART_Group1 Initialization and Configuration functions
+ *  @brief   Initialization and Configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+                  Initialization and Configuration functions
+ ===============================================================================  
+
+  This subsection provides a set of functions allowing to initialize the USART 
+  in asynchronous and in synchronous modes.
+   - For the asynchronous mode only these parameters can be configured: 
+        - Baud Rate
+        - Word Length 
+        - Stop Bit
+        - Parity: If the parity is enabled, then the MSB bit of the data written
+          in the data register is transmitted but is changed by the parity bit.
+          Depending on the frame length defined by the M bit (8-bits or 9-bits),
+          the possible USART frame formats are as listed in the following table:
+   +-------------------------------------------------------------+     
+   |   M bit |  PCE bit  |            USART frame                |
+   |---------------------|---------------------------------------|             
+   |    0    |    0      |    | SB | 8 bit data | STB |          |
+   |---------|-----------|---------------------------------------|  
+   |    0    |    1      |    | SB | 7 bit data | PB | STB |     |
+   |---------|-----------|---------------------------------------|  
+   |    1    |    0      |    | SB | 9 bit data | STB |          |
+   |---------|-----------|---------------------------------------|  
+   |    1    |    1      |    | SB | 8 bit data | PB | STB |     |
+   +-------------------------------------------------------------+            
+        - Hardware flow control
+        - Receiver/transmitter modes
+
+  The USART_Init() function follows the USART  asynchronous configuration procedure
+  (details for the procedure are available in reference manual (RM0090)).
+
+  - For the synchronous mode in addition to the asynchronous mode parameters these 
+    parameters should be also configured:
+        - USART Clock Enabled
+        - USART polarity
+        - USART phase
+        - USART LastBit
+  
+  These parameters can be configured using the USART_ClockInit() function.
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Deinitializes the USARTx peripheral registers to their default reset values.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @retval None
+  */
+void USART_DeInit(USART_TypeDef* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+
+  if (USARTx == USART1)
+  {
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, ENABLE);
+    RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART1, DISABLE);
+  }
+  else if (USARTx == USART2)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART2, DISABLE);
+  }
+  else if (USARTx == USART3)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_USART3, DISABLE);
+  }    
+  else if (USARTx == UART4)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART4, DISABLE);
+  }
+  else if (USARTx == UART5)
+  {
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, ENABLE);
+    RCC_APB1PeriphResetCmd(RCC_APB1Periph_UART5, DISABLE);
+  }     
+  else
+  {
+    if (USARTx == USART6)
+    { 
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, ENABLE);
+      RCC_APB2PeriphResetCmd(RCC_APB2Periph_USART6, DISABLE);
+    }
+  }
+}
+
+/**
+  * @brief  Initializes the USARTx peripheral according to the specified
+  *         parameters in the USART_InitStruct .
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure that contains
+  *         the configuration information for the specified USART peripheral.
+  * @retval None
+  */
+void USART_Init(USART_TypeDef* USARTx, USART_InitTypeDef* USART_InitStruct)
+{
+  uint32_t tmpreg = 0x00, apbclock = 0x00;
+  uint32_t integerdivider = 0x00;
+  uint32_t fractionaldivider = 0x00;
+  RCC_ClocksTypeDef RCC_ClocksStatus;
+
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_BAUDRATE(USART_InitStruct->USART_BaudRate));  
+  assert_param(IS_USART_WORD_LENGTH(USART_InitStruct->USART_WordLength));
+  assert_param(IS_USART_STOPBITS(USART_InitStruct->USART_StopBits));
+  assert_param(IS_USART_PARITY(USART_InitStruct->USART_Parity));
+  assert_param(IS_USART_MODE(USART_InitStruct->USART_Mode));
+  assert_param(IS_USART_HARDWARE_FLOW_CONTROL(USART_InitStruct->USART_HardwareFlowControl));
+
+  /* The hardware flow control is available only for USART1, USART2, USART3 and USART6 */
+  if (USART_InitStruct->USART_HardwareFlowControl != USART_HardwareFlowControl_None)
+  {
+    assert_param(IS_USART_1236_PERIPH(USARTx));
+  }
+
+/*---------------------------- USART CR2 Configuration -----------------------*/
+  tmpreg = USARTx->CR2;
+
+  /* Clear STOP[13:12] bits */
+  tmpreg &= (uint32_t)~((uint32_t)USART_CR2_STOP);
+
+  /* Configure the USART Stop Bits, Clock, CPOL, CPHA and LastBit :
+      Set STOP[13:12] bits according to USART_StopBits value */
+  tmpreg |= (uint32_t)USART_InitStruct->USART_StopBits;
+  
+  /* Write to USART CR2 */
+  USARTx->CR2 = (uint16_t)tmpreg;
+
+/*---------------------------- USART CR1 Configuration -----------------------*/
+  tmpreg = USARTx->CR1;
+
+  /* Clear M, PCE, PS, TE and RE bits */
+  tmpreg &= (uint32_t)~((uint32_t)CR1_CLEAR_MASK);
+
+  /* Configure the USART Word Length, Parity and mode: 
+     Set the M bits according to USART_WordLength value 
+     Set PCE and PS bits according to USART_Parity value
+     Set TE and RE bits according to USART_Mode value */
+  tmpreg |= (uint32_t)USART_InitStruct->USART_WordLength | USART_InitStruct->USART_Parity |
+            USART_InitStruct->USART_Mode;
+
+  /* Write to USART CR1 */
+  USARTx->CR1 = (uint16_t)tmpreg;
+
+/*---------------------------- USART CR3 Configuration -----------------------*/  
+  tmpreg = USARTx->CR3;
+
+  /* Clear CTSE and RTSE bits */
+  tmpreg &= (uint32_t)~((uint32_t)CR3_CLEAR_MASK);
+
+  /* Configure the USART HFC : 
+      Set CTSE and RTSE bits according to USART_HardwareFlowControl value */
+  tmpreg |= USART_InitStruct->USART_HardwareFlowControl;
+
+  /* Write to USART CR3 */
+  USARTx->CR3 = (uint16_t)tmpreg;
+
+/*---------------------------- USART BRR Configuration -----------------------*/
+  /* Configure the USART Baud Rate */
+  RCC_GetClocksFreq(&RCC_ClocksStatus);
+
+  if ((USARTx == USART1) || (USARTx == USART6))
+  {
+    apbclock = RCC_ClocksStatus.PCLK2_Frequency;
+  }
+  else
+  {
+    apbclock = RCC_ClocksStatus.PCLK1_Frequency;
+  }
+  
+  /* Determine the integer part */
+  if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
+  {
+    /* Integer part computing in case Oversampling mode is 8 Samples */
+    integerdivider = ((25 * apbclock) / (2 * (USART_InitStruct->USART_BaudRate)));    
+  }
+  else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */
+  {
+    /* Integer part computing in case Oversampling mode is 16 Samples */
+    integerdivider = ((25 * apbclock) / (4 * (USART_InitStruct->USART_BaudRate)));    
+  }
+  tmpreg = (integerdivider / 100) << 4;
+
+  /* Determine the fractional part */
+  fractionaldivider = integerdivider - (100 * (tmpreg >> 4));
+
+  /* Implement the fractional part in the register */
+  if ((USARTx->CR1 & USART_CR1_OVER8) != 0)
+  {
+    tmpreg |= ((((fractionaldivider * 8) + 50) / 100)) & ((uint8_t)0x07);
+  }
+  else /* if ((USARTx->CR1 & USART_CR1_OVER8) == 0) */
+  {
+    tmpreg |= ((((fractionaldivider * 16) + 50) / 100)) & ((uint8_t)0x0F);
+  }
+  
+  /* Write to USART BRR register */
+  USARTx->BRR = (uint16_t)tmpreg;
+}
+
+/**
+  * @brief  Fills each USART_InitStruct member with its default value.
+  * @param  USART_InitStruct: pointer to a USART_InitTypeDef structure which will
+  *         be initialized.
+  * @retval None
+  */
+void USART_StructInit(USART_InitTypeDef* USART_InitStruct)
+{
+  /* USART_InitStruct members default value */
+  USART_InitStruct->USART_BaudRate = 9600;
+  USART_InitStruct->USART_WordLength = USART_WordLength_8b;
+  USART_InitStruct->USART_StopBits = USART_StopBits_1;
+  USART_InitStruct->USART_Parity = USART_Parity_No ;
+  USART_InitStruct->USART_Mode = USART_Mode_Rx | USART_Mode_Tx;
+  USART_InitStruct->USART_HardwareFlowControl = USART_HardwareFlowControl_None;  
+}
+
+/**
+  * @brief  Initializes the USARTx peripheral Clock according to the 
+  *         specified parameters in the USART_ClockInitStruct .
+  * @param  USARTx: where x can be 1, 2, 3 or 6 to select the USART peripheral.
+  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure that
+  *         contains the configuration information for the specified  USART peripheral.
+  * @note   The Smart Card and Synchronous modes are not available for UART4 and UART5.    
+  * @retval None
+  */
+void USART_ClockInit(USART_TypeDef* USARTx, USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+  uint32_t tmpreg = 0x00;
+  /* Check the parameters */
+  assert_param(IS_USART_1236_PERIPH(USARTx));
+  assert_param(IS_USART_CLOCK(USART_ClockInitStruct->USART_Clock));
+  assert_param(IS_USART_CPOL(USART_ClockInitStruct->USART_CPOL));
+  assert_param(IS_USART_CPHA(USART_ClockInitStruct->USART_CPHA));
+  assert_param(IS_USART_LASTBIT(USART_ClockInitStruct->USART_LastBit));
+  
+/*---------------------------- USART CR2 Configuration -----------------------*/
+  tmpreg = USARTx->CR2;
+  /* Clear CLKEN, CPOL, CPHA and LBCL bits */
+  tmpreg &= (uint32_t)~((uint32_t)CR2_CLOCK_CLEAR_MASK);
+  /* Configure the USART Clock, CPOL, CPHA and LastBit ------------*/
+  /* Set CLKEN bit according to USART_Clock value */
+  /* Set CPOL bit according to USART_CPOL value */
+  /* Set CPHA bit according to USART_CPHA value */
+  /* Set LBCL bit according to USART_LastBit value */
+  tmpreg |= (uint32_t)USART_ClockInitStruct->USART_Clock | USART_ClockInitStruct->USART_CPOL | 
+                 USART_ClockInitStruct->USART_CPHA | USART_ClockInitStruct->USART_LastBit;
+  /* Write to USART CR2 */
+  USARTx->CR2 = (uint16_t)tmpreg;
+}
+
+/**
+  * @brief  Fills each USART_ClockInitStruct member with its default value.
+  * @param  USART_ClockInitStruct: pointer to a USART_ClockInitTypeDef structure
+  *         which will be initialized.
+  * @retval None
+  */
+void USART_ClockStructInit(USART_ClockInitTypeDef* USART_ClockInitStruct)
+{
+  /* USART_ClockInitStruct members default value */
+  USART_ClockInitStruct->USART_Clock = USART_Clock_Disable;
+  USART_ClockInitStruct->USART_CPOL = USART_CPOL_Low;
+  USART_ClockInitStruct->USART_CPHA = USART_CPHA_1Edge;
+  USART_ClockInitStruct->USART_LastBit = USART_LastBit_Disable;
+}
+
+/**
+  * @brief  Enables or disables the specified USART peripheral.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  NewState: new state of the USARTx peripheral.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the selected USART by setting the UE bit in the CR1 register */
+    USARTx->CR1 |= USART_CR1_UE;
+  }
+  else
+  {
+    /* Disable the selected USART by clearing the UE bit in the CR1 register */
+    USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_UE);
+  }
+}
+
+/**
+  * @brief  Sets the system clock prescaler.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  USART_Prescaler: specifies the prescaler clock. 
+  * @note   The function is used for IrDA mode with UART4 and UART5.   
+  * @retval None
+  */
+void USART_SetPrescaler(USART_TypeDef* USARTx, uint8_t USART_Prescaler)
+{ 
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  
+  /* Clear the USART prescaler */
+  USARTx->GTPR &= USART_GTPR_GT;
+  /* Set the USART prescaler */
+  USARTx->GTPR |= USART_Prescaler;
+}
+
+/**
+  * @brief  Enables or disables the USART's 8x oversampling mode.
+  * @note   This function has to be called before calling USART_Init() function
+  *         in order to have correct baudrate Divider value.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  NewState: new state of the USART 8x oversampling mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_OverSampling8Cmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the 8x Oversampling mode by setting the OVER8 bit in the CR1 register */
+    USARTx->CR1 |= USART_CR1_OVER8;
+  }
+  else
+  {
+    /* Disable the 8x Oversampling mode by clearing the OVER8 bit in the CR1 register */
+    USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_OVER8);
+  }
+}  
+
+/**
+  * @brief  Enables or disables the USART's one bit sampling method.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  NewState: new state of the USART one bit sampling method.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_OneBitMethodCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the one bit method by setting the ONEBITE bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_ONEBIT;
+  }
+  else
+  {
+    /* Disable the one bit method by clearing the ONEBITE bit in the CR3 register */
+    USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_ONEBIT);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group2 Data transfers functions
+ *  @brief   Data transfers functions 
+ *
+@verbatim   
+ ===============================================================================
+                            Data transfers functions
+ ===============================================================================  
+
+  This subsection provides a set of functions allowing to manage the USART data 
+  transfers.
+  
+  During an USART reception, data shifts in least significant bit first through 
+  the RX pin. In this mode, the USART_DR register consists of a buffer (RDR) 
+  between the internal bus and the received shift register.
+
+  When a transmission is taking place, a write instruction to the USART_DR register 
+  stores the data in the TDR register and which is copied in the shift register 
+  at the end of the current transmission.
+
+  The read access of the USART_DR register can be done using the USART_ReceiveData()
+  function and returns the RDR buffered value. Whereas a write access to the USART_DR 
+  can be done using USART_SendData() function and stores the written data into 
+  TDR buffer.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Transmits single data through the USARTx peripheral.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  Data: the data to transmit.
+  * @retval None
+  */
+void USART_SendData(USART_TypeDef* USARTx, uint16_t Data)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DATA(Data)); 
+    
+  /* Transmit Data */
+  USARTx->DR = (Data & (uint16_t)0x01FF);
+}
+
+/**
+  * @brief  Returns the most recent received data by the USARTx peripheral.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @retval The received data.
+  */
+uint16_t USART_ReceiveData(USART_TypeDef* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  
+  /* Receive Data */
+  return (uint16_t)(USARTx->DR & (uint16_t)0x01FF);
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group3 MultiProcessor Communication functions
+ *  @brief   Multi-Processor Communication functions 
+ *
+@verbatim   
+ ===============================================================================
+                    Multi-Processor Communication functions
+ ===============================================================================  
+
+  This subsection provides a set of functions allowing to manage the USART 
+  multiprocessor communication.
+  
+  For instance one of the USARTs can be the master, its TX output is connected to 
+  the RX input of the other USART. The others are slaves, their respective TX outputs 
+  are logically ANDed together and connected to the RX input of the master.
+
+  USART multiprocessor communication is possible through the following procedure:
+     1. Program the Baud rate, Word length = 9 bits, Stop bits, Parity, Mode transmitter 
+        or Mode receiver and hardware flow control values using the USART_Init()
+        function.
+     2. Configures the USART address using the USART_SetAddress() function.
+     3. Configures the wake up method (USART_WakeUp_IdleLine or USART_WakeUp_AddressMark)
+        using USART_WakeUpConfig() function only for the slaves.
+     4. Enable the USART using the USART_Cmd() function.
+     5. Enter the USART slaves in mute mode using USART_ReceiverWakeUpCmd() function.
+
+  The USART Slave exit from mute mode when receive the wake up condition.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets the address of the USART node.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  USART_Address: Indicates the address of the USART node.
+  * @retval None
+  */
+void USART_SetAddress(USART_TypeDef* USARTx, uint8_t USART_Address)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_ADDRESS(USART_Address)); 
+    
+  /* Clear the USART address */
+  USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_ADD);
+  /* Set the USART address node */
+  USARTx->CR2 |= USART_Address;
+}
+
+/**
+  * @brief  Determines if the USART is in mute mode or not.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  NewState: new state of the USART mute mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_ReceiverWakeUpCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the USART mute mode  by setting the RWU bit in the CR1 register */
+    USARTx->CR1 |= USART_CR1_RWU;
+  }
+  else
+  {
+    /* Disable the USART mute mode by clearing the RWU bit in the CR1 register */
+    USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_RWU);
+  }
+}
+/**
+  * @brief  Selects the USART WakeUp method.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  USART_WakeUp: specifies the USART wakeup method.
+  *          This parameter can be one of the following values:
+  *            @arg USART_WakeUp_IdleLine: WakeUp by an idle line detection
+  *            @arg USART_WakeUp_AddressMark: WakeUp by an address mark
+  * @retval None
+  */
+void USART_WakeUpConfig(USART_TypeDef* USARTx, uint16_t USART_WakeUp)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_WAKEUP(USART_WakeUp));
+  
+  USARTx->CR1 &= (uint16_t)~((uint16_t)USART_CR1_WAKE);
+  USARTx->CR1 |= USART_WakeUp;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group4 LIN mode functions
+ *  @brief   LIN mode functions 
+ *
+@verbatim   
+ ===============================================================================
+                                LIN mode functions
+ ===============================================================================  
+
+  This subsection provides a set of functions allowing to manage the USART LIN 
+  Mode communication.
+  
+  In LIN mode, 8-bit data format with 1 stop bit is required in accordance with 
+  the LIN standard.
+
+  Only this LIN Feature is supported by the USART IP:
+    - LIN Master Synchronous Break send capability and LIN slave break detection
+      capability :  13-bit break generation and 10/11 bit break detection
+
+
+  USART LIN Master transmitter communication is possible through the following procedure:
+     1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, 
+        Mode transmitter or Mode receiver and hardware flow control values using 
+        the USART_Init() function.
+     2. Enable the USART using the USART_Cmd() function.
+     3. Enable the LIN mode using the USART_LINCmd() function.
+     4. Send the break character using USART_SendBreak() function.
+
+  USART LIN Master receiver communication is possible through the following procedure:
+     1. Program the Baud rate, Word length = 8bits, Stop bits = 1bit, Parity, 
+        Mode transmitter or Mode receiver and hardware flow control values using 
+        the USART_Init() function.
+     2. Enable the USART using the USART_Cmd() function.
+     3. Configures the break detection length using the USART_LINBreakDetectLengthConfig()
+        function.
+     4. Enable the LIN mode using the USART_LINCmd() function.
+
+
+@note In LIN mode, the following bits must be kept cleared:
+        - CLKEN in the USART_CR2 register,
+        - STOP[1:0], SCEN, HDSEL and IREN in the USART_CR3 register.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets the USART LIN Break detection length.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  USART_LINBreakDetectLength: specifies the LIN break detection length.
+  *          This parameter can be one of the following values:
+  *            @arg USART_LINBreakDetectLength_10b: 10-bit break detection
+  *            @arg USART_LINBreakDetectLength_11b: 11-bit break detection
+  * @retval None
+  */
+void USART_LINBreakDetectLengthConfig(USART_TypeDef* USARTx, uint16_t USART_LINBreakDetectLength)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_LIN_BREAK_DETECT_LENGTH(USART_LINBreakDetectLength));
+  
+  USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LBDL);
+  USARTx->CR2 |= USART_LINBreakDetectLength;  
+}
+
+/**
+  * @brief  Enables or disables the USART's LIN mode.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  NewState: new state of the USART LIN mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_LINCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the LIN mode by setting the LINEN bit in the CR2 register */
+    USARTx->CR2 |= USART_CR2_LINEN;
+  }
+  else
+  {
+    /* Disable the LIN mode by clearing the LINEN bit in the CR2 register */
+    USARTx->CR2 &= (uint16_t)~((uint16_t)USART_CR2_LINEN);
+  }
+}
+
+/**
+  * @brief  Transmits break characters.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @retval None
+  */
+void USART_SendBreak(USART_TypeDef* USARTx)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  
+  /* Send break characters */
+  USARTx->CR1 |= USART_CR1_SBK;
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group5 Halfduplex mode function
+ *  @brief   Half-duplex mode function 
+ *
+@verbatim   
+ ===============================================================================
+                         Half-duplex mode function
+ ===============================================================================  
+
+  This subsection provides a set of functions allowing to manage the USART 
+  Half-duplex communication.
+  
+  The USART can be configured to follow a single-wire half-duplex protocol where 
+  the TX and RX lines are internally connected.
+
+  USART Half duplex communication is possible through the following procedure:
+     1. Program the Baud rate, Word length, Stop bits, Parity, Mode transmitter 
+        or Mode receiver and hardware flow control values using the USART_Init()
+        function.
+     2. Configures the USART address using the USART_SetAddress() function.
+     3. Enable the USART using the USART_Cmd() function.
+     4. Enable the half duplex mode using USART_HalfDuplexCmd() function.
+
+
+@note The RX pin is no longer used
+@note In Half-duplex mode the following bits must be kept cleared:
+        - LINEN and CLKEN bits in the USART_CR2 register.
+        - SCEN and IREN bits in the USART_CR3 register.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the USART's Half Duplex communication.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  NewState: new state of the USART Communication.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_HalfDuplexCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  
+  if (NewState != DISABLE)
+  {
+    /* Enable the Half-Duplex mode by setting the HDSEL bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_HDSEL;
+  }
+  else
+  {
+    /* Disable the Half-Duplex mode by clearing the HDSEL bit in the CR3 register */
+    USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_HDSEL);
+  }
+}
+
+/**
+  * @}
+  */
+
+
+/** @defgroup USART_Group6 Smartcard mode functions
+ *  @brief   Smartcard mode functions 
+ *
+@verbatim   
+ ===============================================================================
+                               Smartcard mode functions
+ ===============================================================================  
+
+  This subsection provides a set of functions allowing to manage the USART 
+  Smartcard communication.
+  
+  The Smartcard interface is designed to support asynchronous protocol Smartcards as
+  defined in the ISO 7816-3 standard.
+
+  The USART can provide a clock to the smartcard through the SCLK output.
+  In smartcard mode, SCLK is not associated to the communication but is simply derived 
+  from the internal peripheral input clock through a 5-bit prescaler.
+
+  Smartcard communication is possible through the following procedure:
+     1. Configures the Smartcard Prescaler using the USART_SetPrescaler() function.
+     2. Configures the Smartcard Guard Time using the USART_SetGuardTime() function.
+     3. Program the USART clock using the USART_ClockInit() function as following:
+        - USART Clock enabled
+        - USART CPOL Low
+        - USART CPHA on first edge
+        - USART Last Bit Clock Enabled
+     4. Program the Smartcard interface using the USART_Init() function as following:
+        - Word Length = 9 Bits
+        - 1.5 Stop Bit
+        - Even parity
+        - BaudRate = 12096 baud
+        - Hardware flow control disabled (RTS and CTS signals)
+        - Tx and Rx enabled
+     5. Optionally you can enable the parity error interrupt using the USART_ITConfig()
+        function
+     6. Enable the USART using the USART_Cmd() function.
+     7. Enable the Smartcard NACK using the USART_SmartCardNACKCmd() function.
+     8. Enable the Smartcard interface using the USART_SmartCardCmd() function.
+
+  Please refer to the ISO 7816-3 specification for more details.
+
+
+@note It is also possible to choose 0.5 stop bit for receiving but it is recommended 
+      to use 1.5 stop bits for both transmitting and receiving to avoid switching 
+      between the two configurations.
+@note In smartcard mode, the following bits must be kept cleared:
+        - LINEN bit in the USART_CR2 register.
+        - HDSEL and IREN bits in the USART_CR3 register.
+@note Smartcard mode is available on USART peripherals only (not available on UART4 
+      and UART5 peripherals).
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Sets the specified USART guard time.
+  * @param  USARTx: where x can be 1, 2, 3 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  USART_GuardTime: specifies the guard time.   
+  * @retval None
+  */
+void USART_SetGuardTime(USART_TypeDef* USARTx, uint8_t USART_GuardTime)
+{    
+  /* Check the parameters */
+  assert_param(IS_USART_1236_PERIPH(USARTx));
+  
+  /* Clear the USART Guard time */
+  USARTx->GTPR &= USART_GTPR_PSC;
+  /* Set the USART guard time */
+  USARTx->GTPR |= (uint16_t)((uint16_t)USART_GuardTime << 0x08);
+}
+
+/**
+  * @brief  Enables or disables the USART's Smart Card mode.
+  * @param  USARTx: where x can be 1, 2, 3 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  NewState: new state of the Smart Card mode.
+  *          This parameter can be: ENABLE or DISABLE.      
+  * @retval None
+  */
+void USART_SmartCardCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_1236_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the SC mode by setting the SCEN bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_SCEN;
+  }
+  else
+  {
+    /* Disable the SC mode by clearing the SCEN bit in the CR3 register */
+    USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_SCEN);
+  }
+}
+
+/**
+  * @brief  Enables or disables NACK transmission.
+  * @param  USARTx: where x can be 1, 2, 3 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  NewState: new state of the NACK transmission.
+  *          This parameter can be: ENABLE or DISABLE.  
+  * @retval None
+  */
+void USART_SmartCardNACKCmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_1236_PERIPH(USARTx)); 
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+  if (NewState != DISABLE)
+  {
+    /* Enable the NACK transmission by setting the NACK bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_NACK;
+  }
+  else
+  {
+    /* Disable the NACK transmission by clearing the NACK bit in the CR3 register */
+    USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_NACK);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group7 IrDA mode functions
+ *  @brief   IrDA mode functions 
+ *
+@verbatim   
+ ===============================================================================
+                                IrDA mode functions
+ ===============================================================================  
+
+  This subsection provides a set of functions allowing to manage the USART 
+  IrDA communication.
+  
+  IrDA is a half duplex communication protocol. If the Transmitter is busy, any data
+  on the IrDA receive line will be ignored by the IrDA decoder and if the Receiver 
+  is busy, data on the TX from the USART to IrDA will not be encoded by IrDA.
+  While receiving data, transmission should be avoided as the data to be transmitted
+  could be corrupted.
+
+  IrDA communication is possible through the following procedure:
+     1. Program the Baud rate, Word length = 8 bits, Stop bits, Parity, Transmitter/Receiver 
+        modes and hardware flow control values using the USART_Init() function.
+     2. Enable the USART using the USART_Cmd() function.
+     3. Configures the IrDA pulse width by configuring the prescaler using  
+        the USART_SetPrescaler() function.
+     4. Configures the IrDA  USART_IrDAMode_LowPower or USART_IrDAMode_Normal mode
+        using the USART_IrDAConfig() function.
+     5. Enable the IrDA using the USART_IrDACmd() function.
+
+@note A pulse of width less than two and greater than one PSC period(s) may or may
+      not be rejected.
+@note The receiver set up time should be managed by software. The IrDA physical layer
+      specification specifies a minimum of 10 ms delay between transmission and 
+      reception (IrDA is a half duplex protocol).
+@note In IrDA mode, the following bits must be kept cleared:
+        - LINEN, STOP and CLKEN bits in the USART_CR2 register.
+        - SCEN and HDSEL bits in the USART_CR3 register.
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Configures the USART's IrDA interface.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  USART_IrDAMode: specifies the IrDA mode.
+  *          This parameter can be one of the following values:
+  *            @arg USART_IrDAMode_LowPower
+  *            @arg USART_IrDAMode_Normal
+  * @retval None
+  */
+void USART_IrDAConfig(USART_TypeDef* USARTx, uint16_t USART_IrDAMode)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_IRDA_MODE(USART_IrDAMode));
+    
+  USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IRLP);
+  USARTx->CR3 |= USART_IrDAMode;
+}
+
+/**
+  * @brief  Enables or disables the USART's IrDA interface.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  NewState: new state of the IrDA mode.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_IrDACmd(USART_TypeDef* USARTx, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+    
+  if (NewState != DISABLE)
+  {
+    /* Enable the IrDA mode by setting the IREN bit in the CR3 register */
+    USARTx->CR3 |= USART_CR3_IREN;
+  }
+  else
+  {
+    /* Disable the IrDA mode by clearing the IREN bit in the CR3 register */
+    USARTx->CR3 &= (uint16_t)~((uint16_t)USART_CR3_IREN);
+  }
+}
+
+/**
+  * @}
+  */
+
+/** @defgroup USART_Group8 DMA transfers management functions
+ *  @brief   DMA transfers management functions
+ *
+@verbatim   
+ ===============================================================================
+                      DMA transfers management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+  
+/**
+  * @brief  Enables or disables the USART's DMA interface.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  USART_DMAReq: specifies the DMA request.
+  *          This parameter can be any combination of the following values:
+  *            @arg USART_DMAReq_Tx: USART DMA transmit request
+  *            @arg USART_DMAReq_Rx: USART DMA receive request
+  * @param  NewState: new state of the DMA Request sources.
+  *          This parameter can be: ENABLE or DISABLE.   
+  * @retval None
+  */
+void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_DMAREQ(USART_DMAReq));  
+  assert_param(IS_FUNCTIONAL_STATE(NewState)); 
+
+  if (NewState != DISABLE)
+  {
+    /* Enable the DMA transfer for selected requests by setting the DMAT and/or
+       DMAR bits in the USART CR3 register */
+    USARTx->CR3 |= USART_DMAReq;
+  }
+  else
+  {
+    /* Disable the DMA transfer for selected requests by clearing the DMAT and/or
+       DMAR bits in the USART CR3 register */
+    USARTx->CR3 &= (uint16_t)~USART_DMAReq;
+  }
+}
+
+/**
+  * @}
+  */
+  
+/** @defgroup USART_Group9 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                   Interrupts and flags management functions
+ ===============================================================================  
+
+  This subsection provides a set of functions allowing to configure the USART 
+  Interrupts sources, DMA channels requests and check or clear the flags or 
+  pending bits status.
+  The user should identify which mode will be used in his application to manage 
+  the communication: Polling mode, Interrupt mode or DMA mode. 
+    
+  Polling Mode
+  =============
+  In Polling Mode, the SPI communication can be managed by 10 flags:
+     1. USART_FLAG_TXE : to indicate the status of the transmit buffer register
+     2. USART_FLAG_RXNE : to indicate the status of the receive buffer register
+     3. USART_FLAG_TC : to indicate the status of the transmit operation
+     4. USART_FLAG_IDLE : to indicate the status of the Idle Line             
+     5. USART_FLAG_CTS : to indicate the status of the nCTS input
+     6. USART_FLAG_LBD : to indicate the status of the LIN break detection
+     7. USART_FLAG_NE : to indicate if a noise error occur
+     8. USART_FLAG_FE : to indicate if a frame error occur
+     9. USART_FLAG_PE : to indicate if a parity error occur
+     10. USART_FLAG_ORE : to indicate if an Overrun error occur
+
+  In this Mode it is advised to use the following functions:
+      - FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+      - void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG);
+
+  Interrupt Mode
+  ===============
+  In Interrupt Mode, the USART communication can be managed by 8 interrupt sources
+  and 10 pending bits: 
+
+  Pending Bits:
+  ------------- 
+     1. USART_IT_TXE : to indicate the status of the transmit buffer register
+     2. USART_IT_RXNE : to indicate the status of the receive buffer register
+     3. USART_IT_TC : to indicate the status of the transmit operation
+     4. USART_IT_IDLE : to indicate the status of the Idle Line             
+     5. USART_IT_CTS : to indicate the status of the nCTS input
+     6. USART_IT_LBD : to indicate the status of the LIN break detection
+     7. USART_IT_NE : to indicate if a noise error occur
+     8. USART_IT_FE : to indicate if a frame error occur
+     9. USART_IT_PE : to indicate if a parity error occur
+     10. USART_IT_ORE : to indicate if an Overrun error occur
+
+  Interrupt Source:
+  -----------------
+     1. USART_IT_TXE : specifies the interrupt source for the Tx buffer empty 
+                       interrupt. 
+     2. USART_IT_RXNE : specifies the interrupt source for the Rx buffer not 
+                        empty interrupt.
+     3. USART_IT_TC : specifies the interrupt source for the Transmit complete 
+                       interrupt. 
+     4. USART_IT_IDLE : specifies the interrupt source for the Idle Line interrupt.             
+     5. USART_IT_CTS : specifies the interrupt source for the CTS interrupt. 
+     6. USART_IT_LBD : specifies the interrupt source for the LIN break detection
+                       interrupt. 
+     7. USART_IT_PE : specifies the interrupt source for the parity error interrupt. 
+     8. USART_IT_ERR :  specifies the interrupt source for the errors interrupt.
+
+@note Some parameters are coded in order to use them as interrupt source or as pending bits.
+
+  In this Mode it is advised to use the following functions:
+     - void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState);
+     - ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT);
+     - void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT);
+
+  DMA Mode
+  ========
+  In DMA Mode, the USART communication can be managed by 2 DMA Channel requests:
+     1. USART_DMAReq_Tx: specifies the Tx buffer DMA transfer request
+     2. USART_DMAReq_Rx: specifies the Rx buffer DMA transfer request
+
+  In this Mode it is advised to use the following function:
+     - void USART_DMACmd(USART_TypeDef* USARTx, uint16_t USART_DMAReq, FunctionalState NewState);
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables or disables the specified USART interrupts.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  USART_IT: specifies the USART interrupt sources to be enabled or disabled.
+  *          This parameter can be one of the following values:
+  *            @arg USART_IT_CTS:  CTS change interrupt
+  *            @arg USART_IT_LBD:  LIN Break detection interrupt
+  *            @arg USART_IT_TXE:  Transmit Data Register empty interrupt
+  *            @arg USART_IT_TC:   Transmission complete interrupt
+  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
+  *            @arg USART_IT_IDLE: Idle line detection interrupt
+  *            @arg USART_IT_PE:   Parity Error interrupt
+  *            @arg USART_IT_ERR:  Error interrupt(Frame error, noise error, overrun error)
+  * @param  NewState: new state of the specified USARTx interrupts.
+  *          This parameter can be: ENABLE or DISABLE.
+  * @retval None
+  */
+void USART_ITConfig(USART_TypeDef* USARTx, uint16_t USART_IT, FunctionalState NewState)
+{
+  uint32_t usartreg = 0x00, itpos = 0x00, itmask = 0x00;
+  uint32_t usartxbase = 0x00;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CONFIG_IT(USART_IT));
+  assert_param(IS_FUNCTIONAL_STATE(NewState));
+
+  /* The CTS interrupt is not available for UART4 and UART5 */
+  if (USART_IT == USART_IT_CTS)
+  {
+    assert_param(IS_USART_1236_PERIPH(USARTx));
+  } 
+    
+  usartxbase = (uint32_t)USARTx;
+
+  /* Get the USART register index */
+  usartreg = (((uint8_t)USART_IT) >> 0x05);
+
+  /* Get the interrupt position */
+  itpos = USART_IT & IT_MASK;
+  itmask = (((uint32_t)0x01) << itpos);
+    
+  if (usartreg == 0x01) /* The IT is in CR1 register */
+  {
+    usartxbase += 0x0C;
+  }
+  else if (usartreg == 0x02) /* The IT is in CR2 register */
+  {
+    usartxbase += 0x10;
+  }
+  else /* The IT is in CR3 register */
+  {
+    usartxbase += 0x14; 
+  }
+  if (NewState != DISABLE)
+  {
+    *(__IO uint32_t*)usartxbase  |= itmask;
+  }
+  else
+  {
+    *(__IO uint32_t*)usartxbase &= ~itmask;
+  }
+}
+
+/**
+  * @brief  Checks whether the specified USART flag is set or not.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  USART_FLAG: specifies the flag to check.
+  *          This parameter can be one of the following values:
+  *            @arg USART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5)
+  *            @arg USART_FLAG_LBD:  LIN Break detection flag
+  *            @arg USART_FLAG_TXE:  Transmit data register empty flag
+  *            @arg USART_FLAG_TC:   Transmission Complete flag
+  *            @arg USART_FLAG_RXNE: Receive data register not empty flag
+  *            @arg USART_FLAG_IDLE: Idle Line detection flag
+  *            @arg USART_FLAG_ORE:  OverRun Error flag
+  *            @arg USART_FLAG_NE:   Noise Error flag
+  *            @arg USART_FLAG_FE:   Framing Error flag
+  *            @arg USART_FLAG_PE:   Parity Error flag
+  * @retval The new state of USART_FLAG (SET or RESET).
+  */
+FlagStatus USART_GetFlagStatus(USART_TypeDef* USARTx, uint16_t USART_FLAG)
+{
+  FlagStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_FLAG(USART_FLAG));
+
+  /* The CTS flag is not available for UART4 and UART5 */
+  if (USART_FLAG == USART_FLAG_CTS)
+  {
+    assert_param(IS_USART_1236_PERIPH(USARTx));
+  } 
+    
+  if ((USARTx->SR & USART_FLAG) != (uint16_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears the USARTx's pending flags.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  USART_FLAG: specifies the flag to clear.
+  *          This parameter can be any combination of the following values:
+  *            @arg USART_FLAG_CTS:  CTS Change flag (not available for UART4 and UART5).
+  *            @arg USART_FLAG_LBD:  LIN Break detection flag.
+  *            @arg USART_FLAG_TC:   Transmission Complete flag.
+  *            @arg USART_FLAG_RXNE: Receive data register not empty flag.
+  *   
+  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
+  *          error) and IDLE (Idle line detected) flags are cleared by software 
+  *          sequence: a read operation to USART_SR register (USART_GetFlagStatus()) 
+  *          followed by a read operation to USART_DR register (USART_ReceiveData()).
+  * @note   RXNE flag can be also cleared by a read to the USART_DR register 
+  *          (USART_ReceiveData()).
+  * @note   TC flag can be also cleared by software sequence: a read operation to 
+  *          USART_SR register (USART_GetFlagStatus()) followed by a write operation
+  *          to USART_DR register (USART_SendData()).
+  * @note   TXE flag is cleared only by a write to the USART_DR register 
+  *          (USART_SendData()).
+  *   
+  * @retval None
+  */
+void USART_ClearFlag(USART_TypeDef* USARTx, uint16_t USART_FLAG)
+{
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CLEAR_FLAG(USART_FLAG));
+
+  /* The CTS flag is not available for UART4 and UART5 */
+  if ((USART_FLAG & USART_FLAG_CTS) == USART_FLAG_CTS)
+  {
+    assert_param(IS_USART_1236_PERIPH(USARTx));
+  } 
+       
+  USARTx->SR = (uint16_t)~USART_FLAG;
+}
+
+/**
+  * @brief  Checks whether the specified USART interrupt has occurred or not.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  USART_IT: specifies the USART interrupt source to check.
+  *          This parameter can be one of the following values:
+  *            @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
+  *            @arg USART_IT_LBD:  LIN Break detection interrupt
+  *            @arg USART_IT_TXE:  Transmit Data Register empty interrupt
+  *            @arg USART_IT_TC:   Transmission complete interrupt
+  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt
+  *            @arg USART_IT_IDLE: Idle line detection interrupt
+  *            @arg USART_IT_ORE:  OverRun Error interrupt
+  *            @arg USART_IT_NE:   Noise Error interrupt
+  *            @arg USART_IT_FE:   Framing Error interrupt
+  *            @arg USART_IT_PE:   Parity Error interrupt
+  * @retval The new state of USART_IT (SET or RESET).
+  */
+ITStatus USART_GetITStatus(USART_TypeDef* USARTx, uint16_t USART_IT)
+{
+  uint32_t bitpos = 0x00, itmask = 0x00, usartreg = 0x00;
+  ITStatus bitstatus = RESET;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_GET_IT(USART_IT)); 
+
+  /* The CTS interrupt is not available for UART4 and UART5 */ 
+  if (USART_IT == USART_IT_CTS)
+  {
+    assert_param(IS_USART_1236_PERIPH(USARTx));
+  } 
+    
+  /* Get the USART register index */
+  usartreg = (((uint8_t)USART_IT) >> 0x05);
+  /* Get the interrupt position */
+  itmask = USART_IT & IT_MASK;
+  itmask = (uint32_t)0x01 << itmask;
+  
+  if (usartreg == 0x01) /* The IT  is in CR1 register */
+  {
+    itmask &= USARTx->CR1;
+  }
+  else if (usartreg == 0x02) /* The IT  is in CR2 register */
+  {
+    itmask &= USARTx->CR2;
+  }
+  else /* The IT  is in CR3 register */
+  {
+    itmask &= USARTx->CR3;
+  }
+  
+  bitpos = USART_IT >> 0x08;
+  bitpos = (uint32_t)0x01 << bitpos;
+  bitpos &= USARTx->SR;
+  if ((itmask != (uint16_t)RESET)&&(bitpos != (uint16_t)RESET))
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  
+  return bitstatus;  
+}
+
+/**
+  * @brief  Clears the USARTx's interrupt pending bits.
+  * @param  USARTx: where x can be 1, 2, 3, 4, 5 or 6 to select the USART or 
+  *         UART peripheral.
+  * @param  USART_IT: specifies the interrupt pending bit to clear.
+  *          This parameter can be one of the following values:
+  *            @arg USART_IT_CTS:  CTS change interrupt (not available for UART4 and UART5)
+  *            @arg USART_IT_LBD:  LIN Break detection interrupt
+  *            @arg USART_IT_TC:   Transmission complete interrupt. 
+  *            @arg USART_IT_RXNE: Receive Data register not empty interrupt.
+  *
+  * @note   PE (Parity error), FE (Framing error), NE (Noise error), ORE (OverRun 
+  *          error) and IDLE (Idle line detected) pending bits are cleared by 
+  *          software sequence: a read operation to USART_SR register 
+  *          (USART_GetITStatus()) followed by a read operation to USART_DR register 
+  *          (USART_ReceiveData()).
+  * @note   RXNE pending bit can be also cleared by a read to the USART_DR register 
+  *          (USART_ReceiveData()).
+  * @note   TC pending bit can be also cleared by software sequence: a read 
+  *          operation to USART_SR register (USART_GetITStatus()) followed by a write 
+  *          operation to USART_DR register (USART_SendData()).
+  * @note   TXE pending bit is cleared only by a write to the USART_DR register 
+  *          (USART_SendData()).
+  *  
+  * @retval None
+  */
+void USART_ClearITPendingBit(USART_TypeDef* USARTx, uint16_t USART_IT)
+{
+  uint16_t bitpos = 0x00, itmask = 0x00;
+  /* Check the parameters */
+  assert_param(IS_USART_ALL_PERIPH(USARTx));
+  assert_param(IS_USART_CLEAR_IT(USART_IT)); 
+
+  /* The CTS interrupt is not available for UART4 and UART5 */
+  if (USART_IT == USART_IT_CTS)
+  {
+    assert_param(IS_USART_1236_PERIPH(USARTx));
+  } 
+    
+  bitpos = USART_IT >> 0x08;
+  itmask = ((uint16_t)0x01 << (uint16_t)bitpos);
+  USARTx->SR = (uint16_t)~itmask;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c
new file mode 100644
index 0000000000..ab17a5162b
--- /dev/null
+++ b/bsp/stm32f40x/Libraries/STM32F4xx_StdPeriph_Driver/src/stm32f4xx_wwdg.c
@@ -0,0 +1,303 @@
+/**
+  ******************************************************************************
+  * @file    stm32f4xx_wwdg.c
+  * @author  MCD Application Team
+  * @version V1.0.0RC1
+  * @date    25-August-2011
+  * @brief   This file provides firmware functions to manage the following 
+  *          functionalities of the Window watchdog (WWDG) peripheral:           
+  *           - Prescaler, Refresh window and Counter configuration
+  *           - WWDG activation
+  *           - Interrupts and flags management
+  *             
+  *  @verbatim
+  *    
+  *          ===================================================================
+  *                                     WWDG features
+  *          ===================================================================
+  *                                        
+  *          Once enabled the WWDG generates a system reset on expiry of a programmed
+  *          time period, unless the program refreshes the counter (downcounter) 
+  *          before to reach 0x3F value (i.e. a reset is generated when the counter
+  *          value rolls over from 0x40 to 0x3F). 
+  *          An MCU reset is also generated if the counter value is refreshed
+  *          before the counter has reached the refresh window value. This 
+  *          implies that the counter must be refreshed in a limited window.
+  *            
+  *          Once enabled the WWDG cannot be disabled except by a system reset.                          
+  *          
+  *          WWDGRST flag in RCC_CSR register can be used to inform when a WWDG
+  *          reset occurs.
+  *            
+  *          The WWDG counter input clock is derived from the APB clock divided 
+  *          by a programmable prescaler.
+  *              
+  *          WWDG counter clock = PCLK1 / Prescaler
+  *          WWDG timeout = (WWDG counter clock) * (counter value)
+  *                      
+  *          Min-max timeout value @30 MHz(PCLK1): ~136.5 us / ~69.9 ms
+  *                            
+  *          ===================================================================
+  *                                 How to use this driver
+  *          =================================================================== 
+  *          1. Enable WWDG clock using RCC_APB1PeriphClockCmd(RCC_APB1Periph_WWDG, ENABLE) function
+  *            
+  *          2. Configure the WWDG prescaler using WWDG_SetPrescaler() function
+  *                           
+  *          3. Configure the WWDG refresh window using WWDG_SetWindowValue() function
+  *            
+  *          4. Set the WWDG counter value and start it using WWDG_Enable() function.
+  *             When the WWDG is enabled the counter value should be configured to 
+  *             a value greater than 0x40 to prevent generating an immediate reset.     
+  *            
+  *          5. Optionally you can enable the Early wakeup interrupt which is 
+  *             generated when the counter reach 0x40.
+  *             Once enabled this interrupt cannot be disabled except by a system reset.
+  *                 
+  *          6. Then the application program must refresh the WWDG counter at regular
+  *             intervals during normal operation to prevent an MCU reset, using
+  *             WWDG_SetCounter() function. This operation must occur only when
+  *             the counter value is lower than the refresh window value, 
+  *             programmed using WWDG_SetWindowValue().         
+  *
+  *  @endverbatim  
+  *                             
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_wwdg.h"
+#include "stm32f4xx_rcc.h"
+
+/** @addtogroup STM32F4xx_StdPeriph_Driver
+  * @{
+  */
+
+/** @defgroup WWDG 
+  * @brief WWDG driver modules
+  * @{
+  */
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+
+/* ----------- WWDG registers bit address in the alias region ----------- */
+#define WWDG_OFFSET       (WWDG_BASE - PERIPH_BASE)
+/* Alias word address of EWI bit */
+#define CFR_OFFSET        (WWDG_OFFSET + 0x04)
+#define EWI_BitNumber     0x09
+#define CFR_EWI_BB        (PERIPH_BB_BASE + (CFR_OFFSET * 32) + (EWI_BitNumber * 4))
+
+/* --------------------- WWDG registers bit mask ------------------------ */
+/* CFR register bit mask */
+#define CFR_WDGTB_MASK    ((uint32_t)0xFFFFFE7F)
+#define CFR_W_MASK        ((uint32_t)0xFFFFFF80)
+#define BIT_MASK          ((uint8_t)0x7F)
+
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/** @defgroup WWDG_Private_Functions
+  * @{
+  */
+
+/** @defgroup WWDG_Group1 Prescaler, Refresh window and Counter configuration functions
+ *  @brief   Prescaler, Refresh window and Counter configuration functions 
+ *
+@verbatim   
+ ===============================================================================
+          Prescaler, Refresh window and Counter configuration functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Deinitializes the WWDG peripheral registers to their default reset values.
+  * @param  None
+  * @retval None
+  */
+void WWDG_DeInit(void)
+{
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, ENABLE);
+  RCC_APB1PeriphResetCmd(RCC_APB1Periph_WWDG, DISABLE);
+}
+
+/**
+  * @brief  Sets the WWDG Prescaler.
+  * @param  WWDG_Prescaler: specifies the WWDG Prescaler.
+  *   This parameter can be one of the following values:
+  *     @arg WWDG_Prescaler_1: WWDG counter clock = (PCLK1/4096)/1
+  *     @arg WWDG_Prescaler_2: WWDG counter clock = (PCLK1/4096)/2
+  *     @arg WWDG_Prescaler_4: WWDG counter clock = (PCLK1/4096)/4
+  *     @arg WWDG_Prescaler_8: WWDG counter clock = (PCLK1/4096)/8
+  * @retval None
+  */
+void WWDG_SetPrescaler(uint32_t WWDG_Prescaler)
+{
+  uint32_t tmpreg = 0;
+  /* Check the parameters */
+  assert_param(IS_WWDG_PRESCALER(WWDG_Prescaler));
+  /* Clear WDGTB[1:0] bits */
+  tmpreg = WWDG->CFR & CFR_WDGTB_MASK;
+  /* Set WDGTB[1:0] bits according to WWDG_Prescaler value */
+  tmpreg |= WWDG_Prescaler;
+  /* Store the new value */
+  WWDG->CFR = tmpreg;
+}
+
+/**
+  * @brief  Sets the WWDG window value.
+  * @param  WindowValue: specifies the window value to be compared to the downcounter.
+  *   This parameter value must be lower than 0x80.
+  * @retval None
+  */
+void WWDG_SetWindowValue(uint8_t WindowValue)
+{
+  __IO uint32_t tmpreg = 0;
+
+  /* Check the parameters */
+  assert_param(IS_WWDG_WINDOW_VALUE(WindowValue));
+  /* Clear W[6:0] bits */
+
+  tmpreg = WWDG->CFR & CFR_W_MASK;
+
+  /* Set W[6:0] bits according to WindowValue value */
+  tmpreg |= WindowValue & (uint32_t) BIT_MASK;
+
+  /* Store the new value */
+  WWDG->CFR = tmpreg;
+}
+
+/**
+  * @brief  Enables the WWDG Early Wakeup interrupt(EWI).
+  * @note   Once enabled this interrupt cannot be disabled except by a system reset.
+  * @param  None
+  * @retval None
+  */
+void WWDG_EnableIT(void)
+{
+  *(__IO uint32_t *) CFR_EWI_BB = (uint32_t)ENABLE;
+}
+
+/**
+  * @brief  Sets the WWDG counter value.
+  * @param  Counter: specifies the watchdog counter value.
+  *   This parameter must be a number between 0x40 and 0x7F (to prevent generating
+  *   an immediate reset) 
+  * @retval None
+  */
+void WWDG_SetCounter(uint8_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_WWDG_COUNTER(Counter));
+  /* Write to T[6:0] bits to configure the counter value, no need to do
+     a read-modify-write; writing a 0 to WDGA bit does nothing */
+  WWDG->CR = Counter & BIT_MASK;
+}
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Group2 WWDG activation functions
+ *  @brief   WWDG activation functions 
+ *
+@verbatim   
+ ===============================================================================
+                       WWDG activation function
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Enables WWDG and load the counter value.                  
+  * @param  Counter: specifies the watchdog counter value.
+  *   This parameter must be a number between 0x40 and 0x7F (to prevent generating
+  *   an immediate reset)
+  * @retval None
+  */
+void WWDG_Enable(uint8_t Counter)
+{
+  /* Check the parameters */
+  assert_param(IS_WWDG_COUNTER(Counter));
+  WWDG->CR = WWDG_CR_WDGA | Counter;
+}
+/**
+  * @}
+  */
+
+/** @defgroup WWDG_Group3 Interrupts and flags management functions
+ *  @brief   Interrupts and flags management functions 
+ *
+@verbatim   
+ ===============================================================================
+                 Interrupts and flags management functions
+ ===============================================================================  
+
+@endverbatim
+  * @{
+  */
+
+/**
+  * @brief  Checks whether the Early Wakeup interrupt flag is set or not.
+  * @param  None
+  * @retval The new state of the Early Wakeup interrupt flag (SET or RESET)
+  */
+FlagStatus WWDG_GetFlagStatus(void)
+{
+  FlagStatus bitstatus = RESET;
+    
+  if ((WWDG->SR) != (uint32_t)RESET)
+  {
+    bitstatus = SET;
+  }
+  else
+  {
+    bitstatus = RESET;
+  }
+  return bitstatus;
+}
+
+/**
+  * @brief  Clears Early Wakeup interrupt flag.
+  * @param  None
+  * @retval None
+  */
+void WWDG_ClearFlag(void)
+{
+  WWDG->SR = (uint32_t)RESET;
+}
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/**
+  * @}
+  */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/SConscript b/bsp/stm32f40x/SConscript
new file mode 100644
index 0000000000..c294894be7
--- /dev/null
+++ b/bsp/stm32f40x/SConscript
@@ -0,0 +1,10 @@
+from building import *
+
+src_bsp = ['application.c', 'startup.c', 'board.c', 'stm32f4xx_it.c']
+src_drv = ['usart.c', 'serial.c']
+
+src = src_bsp + src_drv
+CPPPATH = [GetCurrentDir()]
+group = DefineGroup('Startup', src, depend = [''], CPPPATH = CPPPATH)
+
+Return('group')
diff --git a/bsp/stm32f40x/SConstruct b/bsp/stm32f40x/SConstruct
new file mode 100644
index 0000000000..63b1130d6a
--- /dev/null
+++ b/bsp/stm32f40x/SConstruct
@@ -0,0 +1,36 @@
+import os
+import sys
+import rtconfig
+
+RTT_ROOT = os.path.normpath(os.getcwd() + '/../..')
+sys.path = sys.path + [os.path.join(RTT_ROOT, 'tools')]
+from building import *
+
+TARGET = 'rtthread-stm32.' + rtconfig.TARGET_EXT
+
+env = Environment(tools = ['mingw'],
+	AS = rtconfig.AS, ASFLAGS = rtconfig.AFLAGS,
+	CC = rtconfig.CC, CCFLAGS = rtconfig.CFLAGS,
+	AR = rtconfig.AR, ARFLAGS = '-rc',
+	LINK = rtconfig.LINK, LINKFLAGS = rtconfig.LFLAGS)
+env.PrependENVPath('PATH', rtconfig.EXEC_PATH)
+
+if rtconfig.PLATFORM == 'iar':
+	env.Replace(CCCOM = ['$CC $CCFLAGS $CPPFLAGS $_CPPDEFFLAGS $_CPPINCFLAGS -o $TARGET $SOURCES'])
+	env.Replace(ARFLAGS = [''])
+	env.Replace(LINKCOM = ['$LINK $SOURCES $LINKFLAGS -o $TARGET --map project.map'])
+
+Export('RTT_ROOT')
+Export('rtconfig')
+
+# prepare building environment
+objs = PrepareBuilding(env, RTT_ROOT)
+
+# STM32 firemare library building script
+objs = objs + SConscript('Libraries/SConscript', variant_dir='build/bsp/Libraries', duplicate=0)
+
+# build program 
+env.Program(TARGET, objs)
+
+# end building 
+EndBuilding(TARGET)
diff --git a/bsp/stm32f40x/application.c b/bsp/stm32f40x/application.c
new file mode 100644
index 0000000000..db167c8183
--- /dev/null
+++ b/bsp/stm32f40x/application.c
@@ -0,0 +1,96 @@
+/*
+ * File      : application.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ */
+
+/**
+ * @addtogroup STM32
+ */
+/*@{*/
+
+#include 
+#include 
+
+#ifdef RT_USING_DFS
+/* dfs init */
+#include 
+/* dfs filesystem:ELM filesystem init */
+#include 
+/* dfs Filesystem APIs */
+#include 
+#endif
+
+#ifdef RT_USING_LWIP
+#include 
+#include 
+#include 
+#endif
+
+void rt_init_thread_entry(void* parameter)
+{
+/* Filesystem Initialization */
+#ifdef RT_USING_DFS
+	{
+		/* init the device filesystem */
+		dfs_init();
+
+#ifdef RT_USING_DFS_ELMFAT
+		/* init the elm chan FatFs filesystam*/
+		elm_init();
+
+		/* mount sd card fat partition 1 as root directory */
+		if (dfs_mount("sd0", "/", "elm", 0, 0) == 0)
+		{
+			rt_kprintf("File System initialized!\n");
+		}
+		else
+			rt_kprintf("File System initialzation failed!\n");
+#endif
+	}
+#endif
+
+/* LwIP Initialization */
+#ifdef RT_USING_LWIP
+	{
+		extern void lwip_sys_init(void);
+
+		/* register ethernetif device */
+		eth_system_device_init();
+	
+		/* initialize eth interface */
+		rt_hw_stm32_eth_init();
+	
+		/* re-init device driver */
+		rt_device_init_all();
+
+		/* init lwip system */
+		lwip_sys_init();
+		rt_kprintf("TCP/IP initialized!\n");
+	}
+#endif
+}
+
+int rt_application_init()
+{
+	rt_thread_t tid;
+
+	tid = rt_thread_create("init",
+								rt_init_thread_entry, RT_NULL,
+								2048, RT_THREAD_PRIORITY_MAX/3, 20);
+
+	if (tid != RT_NULL)
+		rt_thread_startup(tid);
+
+	return 0;
+}
+
+/*@}*/
diff --git a/bsp/stm32f40x/board.c b/bsp/stm32f40x/board.c
new file mode 100644
index 0000000000..8daa989f91
--- /dev/null
+++ b/bsp/stm32f40x/board.c
@@ -0,0 +1,90 @@
+/*
+ * File      : board.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first implementation
+ */
+
+#include 
+#include 
+
+#include "board.h"
+#include "usart.h"
+
+/**
+ * @addtogroup STM32
+ */
+
+/*@{*/
+
+/*******************************************************************************
+* Function Name  : NVIC_Configuration
+* Description    : Configures Vector Table base location.
+* Input          : None
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void NVIC_Configuration(void)
+{
+}
+
+/*******************************************************************************
+ * Function Name  : SysTick_Configuration
+ * Description    : Configures the SysTick for OS tick.
+ * Input          : None
+ * Output         : None
+ * Return         : None
+ *******************************************************************************/
+void  SysTick_Configuration(void)
+{
+	RCC_ClocksTypeDef  rcc_clocks;
+	rt_uint32_t         cnts;
+
+	RCC_GetClocksFreq(&rcc_clocks);
+
+	cnts = (rt_uint32_t)rcc_clocks.HCLK_Frequency / RT_TICK_PER_SECOND;
+
+	SysTick_Config(cnts);
+	SysTick_CLKSourceConfig(SysTick_CLKSource_HCLK);
+}
+
+/**
+ * This is the timer interrupt service routine.
+ *
+ */
+void SysTick_Handler(void)
+{
+	/* enter interrupt */
+	rt_interrupt_enter();
+
+	rt_tick_increase();
+
+	/* leave interrupt */
+	rt_interrupt_leave();
+}
+
+/**
+ * This function will initial STM32 board.
+ */
+void rt_hw_board_init()
+{
+	/* NVIC Configuration */
+	NVIC_Configuration();
+
+	/* Configure the SysTick */
+	SysTick_Configuration();
+
+	rt_hw_usart_init();
+#ifdef RT_USING_CONSOLE
+	rt_console_set_device(CONSOLE_DEVICE);
+#endif
+}
+
+/*@}*/
diff --git a/bsp/stm32f40x/board.h b/bsp/stm32f40x/board.h
new file mode 100644
index 0000000000..7351e00f10
--- /dev/null
+++ b/bsp/stm32f40x/board.h
@@ -0,0 +1,66 @@
+/*
+ * File      : board.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-09-22     Bernard      add board.h to this bsp
+ */
+
+// <<< Use Configuration Wizard in Context Menu >>>
+#ifndef __BOARD_H__
+#define __BOARD_H__
+
+#include 
+
+/* board configuration */
+//  SDCard Driver <1=>SDIO sdcard <0=>SPI MMC card
+// 	Default: 1
+#define STM32_USE_SDIO			1
+
+/* whether use board external SRAM memory */
+// Use external SRAM memory on the board
+// 	Enable External SRAM memory
+#define STM32_EXT_SRAM          0
+//	Begin Address of External SRAM
+//		Default: 0x68000000
+#define STM32_EXT_SRAM_BEGIN    0x68000000 /* the begining address of external SRAM */
+//	End Address of External SRAM
+//		Default: 0x68080000
+#define STM32_EXT_SRAM_END      0x68080000 /* the end address of external SRAM */
+// 
+
+//  Internal SRAM memory size[Kbytes] <8-128>
+//	Default: 64
+#define STM32_SRAM_SIZE         192
+#define STM32_SRAM_END          (0x20000000 + STM32_SRAM_SIZE * 1024)
+
+//  Console on USART: <0=> no console <1=>USART 1 <2=>USART 2 <3=> USART 3
+// 	Default: 1
+#define STM32_CONSOLE_USART		1
+
+//  Ethernet Interface: <0=> Microchip ENC28J60
+#define STM32_ETH_IF			0
+
+void rt_hw_board_led_on(int n);
+void rt_hw_board_led_off(int n);
+void rt_hw_board_init(void);
+
+#if STM32_CONSOLE_USART == 0
+#define CONSOLE_DEVICE "no"
+#elif STM32_CONSOLE_USART == 1
+#define CONSOLE_DEVICE "uart1"
+#elif STM32_CONSOLE_USART == 2
+#define CONSOLE_DEVICE "uart2"
+#elif STM32_CONSOLE_USART == 3
+#define CONSOLE_DEVICE "uart3"
+#endif
+
+#endif
+
+// <<< Use Configuration Wizard in Context Menu >>>
diff --git a/bsp/stm32f40x/project.uvopt b/bsp/stm32f40x/project.uvopt
new file mode 100644
index 0000000000..60e9b82573
--- /dev/null
+++ b/bsp/stm32f40x/project.uvopt
@@ -0,0 +1,4478 @@
+
+
+
+  1.0
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    *.c
+    *.s*; *.src; *.a*
+    *.obj
+    *.lib
+    *.txt; *.h; *.inc
+    *.plm
+    *.cpp
+  
+
+  
+    0
+    0
+  
+
+  
+    RT-Thread STM32
+    0x4
+    ARM-ADS
+    
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+      
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+          Reference Manual
+          DATASHTS\ST\STM32F4xx.PDF
+        
+      
+      
+        SARMCM3.DLL
+        -MPU
+        DCM.DLL
+        -pCM4
+        SARMCM3.DLL
+        -MPU
+        TCM.DLL
+        -pCM4
+      
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+      arm_cfft_radix4_init_q31.c
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+    
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+      0
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+      Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_rfft_f32.c
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+      0
+      0
+      0
+      0
+      0
+      Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_rfft_init_q31.c
+      arm_rfft_init_q31.c
+    
+    
+      5
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+      1
+      0
+      0
+      25
+      0
+      1
+      1
+      0
+      Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_rfft_q15.c
+      arm_rfft_q15.c
+    
+    
+      5
+      309
+      1
+      0
+      0
+      0
+      0
+      0
+      0
+      0
+      Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_rfft_q31.c
+      arm_rfft_q31.c
+    
+  
+
+    
diff --git a/bsp/stm32f40x/project.uvproj b/bsp/stm32f40x/project.uvproj
new file mode 100644
index 0000000000..3a991c1762
--- /dev/null
+++ b/bsp/stm32f40x/project.uvproj
@@ -0,0 +1,1945 @@
+
+
+
+  1.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      RT-Thread STM32
+      0x4
+      ARM-ADS
+      
+        
+          STM32F207VG
+          STMicroelectronics
+          IRAM(0x20000000-0x2001FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M3")
+          
+          "STARTUP\ST\STM32F2xx\startup_stm32f2xx.s" ("STM32F2xx Startup Code")
+          UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000)
+          5118
+          stm32f2xx.h
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          SFD\ST\STM32F2xx\STM32F2xx.sfr
+          0
+          
+          
+          
+          ST\STM32F2xx\
+          ST\STM32F2xx\
+          
+            0
+            0
+            0
+            0
+            1
+          
+          .\obj\
+          rtthread-stm32
+          1
+          0
+          0
+          1
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+          .\obj\
+          1
+          0
+          0
+          
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+          1
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+          0
+          0
+          0
+          3
+          
+          
+        
+        
+          SARMCM3.DLL
+          -MPU
+          DCM.DLL
+          -pCM4
+          SARMCM3.DLL
+          -MPU
+          TCM.DLL
+          -pCM4
+        
+        
+          
+            1
+            0
+            0
+            0
+            16
+          
+          
+            0
+            1
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+          
+            
+            
+            
+            
+            
+          
+          
+            
+            
+            
+            
+            
+            Segger\JL2CM3.dll
+          
+        
+        
+          
+            1
+            0
+            0
+            0
+            1
+            4099
+          
+          Segger\JL2CM3.dll
+          "" ()
+          
+        
+        
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+            1
+            1
+            1
+            1
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+            "Cortex-M3"
+            
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+              
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+                0x20000
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+                0x8000000
+                0x100000
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+            0
+            0
+            0
+            0
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+            0
+            0
+            0
+            0
+            
+              
+              USE_STDPERIPH_DRIVER, ARM_MATH_CM4, __FPU_PRESENT=1, ARM_MATH_BIG_ENDIAN, ARM_MATH_ROUNDING, ARM_MATH_MATRIX_CHECK
+              
+              Libraries\CMSIS\ST\STM32F4xx\Include;Libraries\CMSIS\Include;..\..\components\finsh;.;..\..\include;..\..\libcpu\arm\common;..\..\libcpu\arm\stm32;Libraries\STM32F4xx_StdPeriph_Driver\inc
+            
+          
+          
+            1
+            0
+            0
+            0
+            0
+            0
+            0
+            
+              
+              
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+          
+            1
+            0
+            0
+            0
+            1
+            0
+            0x08000000
+            0x20000000
+            
+            
+            
+             --keep __fsym_* --keep __vsym_* 
+            
+            
+          
+        
+      
+      
+        
+          Startup
+          
+            
+              application.c
+              1
+              .\application.c
+            
+            
+              startup.c
+              1
+              .\startup.c
+            
+            
+              board.c
+              1
+              .\board.c
+            
+            
+              stm32f4xx_it.c
+              1
+              .\stm32f4xx_it.c
+            
+            
+              usart.c
+              1
+              .\usart.c
+            
+            
+              serial.c
+              1
+              .\serial.c
+            
+          
+        
+        
+          Kernel
+          
+            
+              device.c
+              1
+              ..\..\src\device.c
+            
+            
+              thread.c
+              1
+              ..\..\src\thread.c
+            
+            
+              scheduler.c
+              1
+              ..\..\src\scheduler.c
+            
+            
+              timer.c
+              1
+              ..\..\src\timer.c
+            
+            
+              irq.c
+              1
+              ..\..\src\irq.c
+            
+            
+              kservice.c
+              1
+              ..\..\src\kservice.c
+            
+            
+              clock.c
+              1
+              ..\..\src\clock.c
+            
+            
+              object.c
+              1
+              ..\..\src\object.c
+            
+            
+              mempool.c
+              1
+              ..\..\src\mempool.c
+            
+            
+              ipc.c
+              1
+              ..\..\src\ipc.c
+            
+            
+              idle.c
+              1
+              ..\..\src\idle.c
+            
+            
+              mem.c
+              1
+              ..\..\src\mem.c
+            
+          
+        
+        
+          STM32
+          
+            
+              cpuport.c
+              1
+              ..\..\libcpu\arm\stm32\cpuport.c
+            
+            
+              context_rvds.S
+              2
+              ..\..\libcpu\arm\stm32\context_rvds.S
+            
+          
+        
+        
+          finsh
+          
+            
+              cmd.c
+              1
+              ..\..\components\finsh\cmd.c
+            
+            
+              finsh_compiler.c
+              1
+              ..\..\components\finsh\finsh_compiler.c
+            
+            
+              finsh_error.c
+              1
+              ..\..\components\finsh\finsh_error.c
+            
+            
+              finsh_heap.c
+              1
+              ..\..\components\finsh\finsh_heap.c
+            
+            
+              finsh_init.c
+              1
+              ..\..\components\finsh\finsh_init.c
+            
+            
+              finsh_node.c
+              1
+              ..\..\components\finsh\finsh_node.c
+            
+            
+              finsh_ops.c
+              1
+              ..\..\components\finsh\finsh_ops.c
+            
+            
+              finsh_parser.c
+              1
+              ..\..\components\finsh\finsh_parser.c
+            
+            
+              finsh_token.c
+              1
+              ..\..\components\finsh\finsh_token.c
+            
+            
+              finsh_var.c
+              1
+              ..\..\components\finsh\finsh_var.c
+            
+            
+              finsh_vm.c
+              1
+              ..\..\components\finsh\finsh_vm.c
+            
+            
+              shell.c
+              1
+              ..\..\components\finsh\shell.c
+            
+            
+              symbol.c
+              1
+              ..\..\components\finsh\symbol.c
+            
+          
+        
+        
+          STM32_StdPeriph
+          
+            
+              system_stm32f4xx.c
+              1
+              Libraries\CMSIS\ST\STM32F4xx\Source\Templates\system_stm32f4xx.c
+            
+            
+              misc.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\misc.c
+            
+            
+              stm32f4xx_adc.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_adc.c
+            
+            
+              stm32f4xx_can.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_can.c
+            
+            
+              stm32f4xx_crc.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_crc.c
+            
+            
+              stm32f4xx_cryp.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp.c
+            
+            
+              stm32f4xx_cryp_aes.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp_aes.c
+            
+            
+              stm32f4xx_cryp_des.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp_des.c
+            
+            
+              stm32f4xx_cryp_tdes.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_cryp_tdes.c
+            
+            
+              stm32f4xx_dac.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dac.c
+            
+            
+              stm32f4xx_dbgmcu.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dbgmcu.c
+            
+            
+              stm32f4xx_dcmi.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dcmi.c
+            
+            
+              stm32f4xx_dma.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_dma.c
+            
+            
+              stm32f4xx_exti.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_exti.c
+            
+            
+              stm32f4xx_flash.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_flash.c
+            
+            
+              stm32f4xx_fsmc.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_fsmc.c
+            
+            
+              stm32f4xx_gpio.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_gpio.c
+            
+            
+              stm32f4xx_hash.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_hash.c
+            
+            
+              stm32f4xx_hash_md5.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_hash_md5.c
+            
+            
+              stm32f4xx_hash_sha1.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_hash_sha1.c
+            
+            
+              stm32f4xx_i2c.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_i2c.c
+            
+            
+              stm32f4xx_iwdg.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_iwdg.c
+            
+            
+              stm32f4xx_pwr.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_pwr.c
+            
+            
+              stm32f4xx_rcc.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rcc.c
+            
+            
+              stm32f4xx_rng.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rng.c
+            
+            
+              stm32f4xx_rtc.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_rtc.c
+            
+            
+              stm32f4xx_sdio.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_sdio.c
+            
+            
+              stm32f4xx_spi.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_spi.c
+            
+            
+              stm32f4xx_syscfg.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_syscfg.c
+            
+            
+              stm32f4xx_tim.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_tim.c
+            
+            
+              stm32f4xx_usart.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_usart.c
+            
+            
+              stm32f4xx_wwdg.c
+              1
+              Libraries\STM32F4xx_StdPeriph_Driver\src\stm32f4xx_wwdg.c
+            
+            
+              startup_stm32f4xx.s
+              2
+              Libraries\CMSIS\ST\STM32F4xx\Source\Templates\arm\startup_stm32f4xx.s
+            
+            
+              arm_abs_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\BasicMathFunctions\arm_abs_f32.c
+            
+            
+              arm_abs_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\BasicMathFunctions\arm_abs_q15.c
+            
+            
+              arm_abs_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\BasicMathFunctions\arm_abs_q31.c
+            
+            
+              arm_abs_q7.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\BasicMathFunctions\arm_abs_q7.c
+            
+            
+              arm_add_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\BasicMathFunctions\arm_add_f32.c
+            
+            
+              arm_add_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\BasicMathFunctions\arm_add_q15.c
+            
+            
+              arm_add_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\BasicMathFunctions\arm_add_q31.c
+            
+            
+              arm_add_q7.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\BasicMathFunctions\arm_add_q7.c
+            
+            
+              arm_dot_prod_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\BasicMathFunctions\arm_dot_prod_f32.c
+            
+            
+              arm_dot_prod_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\BasicMathFunctions\arm_dot_prod_q15.c
+            
+            
+              arm_dot_prod_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\BasicMathFunctions\arm_dot_prod_q31.c
+            
+            
+              arm_dot_prod_q7.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\BasicMathFunctions\arm_dot_prod_q7.c
+            
+            
+              arm_mult_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\BasicMathFunctions\arm_mult_f32.c
+            
+            
+              arm_mult_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\BasicMathFunctions\arm_mult_q15.c
+            
+            
+              arm_mult_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\BasicMathFunctions\arm_mult_q31.c
+            
+            
+              arm_mult_q7.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\BasicMathFunctions\arm_mult_q7.c
+            
+            
+              arm_negate_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\BasicMathFunctions\arm_negate_f32.c
+            
+            
+              arm_negate_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\BasicMathFunctions\arm_negate_q15.c
+            
+            
+              arm_negate_q31.c
+              1
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+            
+            
+              arm_lms_norm_init_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\FilteringFunctions\arm_lms_norm_init_q31.c
+            
+            
+              arm_lms_norm_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\FilteringFunctions\arm_lms_norm_q15.c
+            
+            
+              arm_lms_norm_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\FilteringFunctions\arm_lms_norm_q31.c
+            
+            
+              arm_lms_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\FilteringFunctions\arm_lms_q15.c
+            
+            
+              arm_lms_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\FilteringFunctions\arm_lms_q31.c
+            
+            
+              arm_mat_add_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_add_f32.c
+            
+            
+              arm_mat_add_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_add_q15.c
+            
+            
+              arm_mat_add_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_add_q31.c
+            
+            
+              arm_mat_init_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_init_f32.c
+            
+            
+              arm_mat_init_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_init_q15.c
+            
+            
+              arm_mat_init_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_init_q31.c
+            
+            
+              arm_mat_inverse_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_inverse_f32.c
+            
+            
+              arm_mat_mult_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_mult_f32.c
+            
+            
+              arm_mat_mult_fast_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_mult_fast_q15.c
+            
+            
+              arm_mat_mult_fast_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_mult_fast_q31.c
+            
+            
+              arm_mat_mult_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_mult_q15.c
+            
+            
+              arm_mat_mult_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_mult_q31.c
+            
+            
+              arm_mat_scale_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_scale_f32.c
+            
+            
+              arm_mat_scale_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_scale_q15.c
+            
+            
+              arm_mat_scale_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_scale_q31.c
+            
+            
+              arm_mat_sub_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_sub_f32.c
+            
+            
+              arm_mat_sub_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_sub_q15.c
+            
+            
+              arm_mat_sub_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_sub_q31.c
+            
+            
+              arm_mat_trans_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_trans_f32.c
+            
+            
+              arm_mat_trans_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_trans_q15.c
+            
+            
+              arm_mat_trans_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\MatrixFunctions\arm_mat_trans_q31.c
+            
+            
+              arm_max_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_max_f32.c
+            
+            
+              arm_max_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_max_q15.c
+            
+            
+              arm_max_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_max_q31.c
+            
+            
+              arm_max_q7.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_max_q7.c
+            
+            
+              arm_mean_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_mean_f32.c
+            
+            
+              arm_mean_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_mean_q15.c
+            
+            
+              arm_mean_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_mean_q31.c
+            
+            
+              arm_mean_q7.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_mean_q7.c
+            
+            
+              arm_min_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_min_f32.c
+            
+            
+              arm_min_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_min_q15.c
+            
+            
+              arm_min_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_min_q31.c
+            
+            
+              arm_min_q7.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_min_q7.c
+            
+            
+              arm_power_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_power_f32.c
+            
+            
+              arm_power_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_power_q15.c
+            
+            
+              arm_power_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_power_q31.c
+            
+            
+              arm_power_q7.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_power_q7.c
+            
+            
+              arm_rms_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_rms_f32.c
+            
+            
+              arm_rms_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_rms_q15.c
+            
+            
+              arm_rms_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_rms_q31.c
+            
+            
+              arm_std_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_std_f32.c
+            
+            
+              arm_std_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_std_q15.c
+            
+            
+              arm_std_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_std_q31.c
+            
+            
+              arm_var_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_var_f32.c
+            
+            
+              arm_var_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_var_q15.c
+            
+            
+              arm_var_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\StatisticsFunctions\arm_var_q31.c
+            
+            
+              arm_copy_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\SupportFunctions\arm_copy_f32.c
+            
+            
+              arm_copy_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\SupportFunctions\arm_copy_q15.c
+            
+            
+              arm_copy_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\SupportFunctions\arm_copy_q31.c
+            
+            
+              arm_copy_q7.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\SupportFunctions\arm_copy_q7.c
+            
+            
+              arm_fill_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\SupportFunctions\arm_fill_f32.c
+            
+            
+              arm_fill_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\SupportFunctions\arm_fill_q15.c
+            
+            
+              arm_fill_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\SupportFunctions\arm_fill_q31.c
+            
+            
+              arm_fill_q7.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\SupportFunctions\arm_fill_q7.c
+            
+            
+              arm_float_to_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\SupportFunctions\arm_float_to_q15.c
+            
+            
+              arm_float_to_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\SupportFunctions\arm_float_to_q31.c
+            
+            
+              arm_float_to_q7.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\SupportFunctions\arm_float_to_q7.c
+            
+            
+              arm_q15_to_float.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\SupportFunctions\arm_q15_to_float.c
+            
+            
+              arm_q15_to_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\SupportFunctions\arm_q15_to_q31.c
+            
+            
+              arm_q15_to_q7.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\SupportFunctions\arm_q15_to_q7.c
+            
+            
+              arm_q31_to_float.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\SupportFunctions\arm_q31_to_float.c
+            
+            
+              arm_q31_to_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\SupportFunctions\arm_q31_to_q15.c
+            
+            
+              arm_q31_to_q7.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\SupportFunctions\arm_q31_to_q7.c
+            
+            
+              arm_q7_to_float.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\SupportFunctions\arm_q7_to_float.c
+            
+            
+              arm_q7_to_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\SupportFunctions\arm_q7_to_q15.c
+            
+            
+              arm_q7_to_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\SupportFunctions\arm_q7_to_q31.c
+            
+            
+              arm_cfft_radix4_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_cfft_radix4_f32.c
+            
+            
+              arm_cfft_radix4_init_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_cfft_radix4_init_f32.c
+            
+            
+              arm_cfft_radix4_init_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_cfft_radix4_init_q15.c
+            
+            
+              arm_cfft_radix4_init_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_cfft_radix4_init_q31.c
+            
+            
+              arm_cfft_radix4_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_cfft_radix4_q15.c
+            
+            
+              arm_cfft_radix4_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_cfft_radix4_q31.c
+            
+            
+              arm_dct4_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_dct4_f32.c
+            
+            
+              arm_dct4_init_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_dct4_init_f32.c
+            
+            
+              arm_dct4_init_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_dct4_init_q15.c
+            
+            
+              arm_dct4_init_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_dct4_init_q31.c
+            
+            
+              arm_dct4_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_dct4_q15.c
+            
+            
+              arm_dct4_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_dct4_q31.c
+            
+            
+              arm_rfft_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_rfft_f32.c
+            
+            
+              arm_rfft_init_f32.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_rfft_init_f32.c
+            
+            
+              arm_rfft_init_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_rfft_init_q15.c
+            
+            
+              arm_rfft_init_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_rfft_init_q31.c
+            
+            
+              arm_rfft_q15.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_rfft_q15.c
+            
+            
+              arm_rfft_q31.c
+              1
+              Libraries\CMSIS\DSP_Lib\Source\TransformFunctions\arm_rfft_q31.c
+            
+          
+        
+      
+    
+  
+
+    
diff --git a/bsp/stm32f40x/rtconfig.h b/bsp/stm32f40x/rtconfig.h
new file mode 100644
index 0000000000..31ca5853b4
--- /dev/null
+++ b/bsp/stm32f40x/rtconfig.h
@@ -0,0 +1,134 @@
+/* RT-Thread config file */
+#ifndef __RTTHREAD_CFG_H__
+#define __RTTHREAD_CFG_H__
+
+/* RT_NAME_MAX*/
+#define RT_NAME_MAX		8
+
+/* RT_ALIGN_SIZE*/
+#define RT_ALIGN_SIZE	4
+
+/* PRIORITY_MAX */
+#define RT_THREAD_PRIORITY_MAX	32
+
+/* Tick per Second */
+#define RT_TICK_PER_SECOND	100
+
+/* SECTION: RT_DEBUG */
+/* Thread Debug */
+#define RT_DEBUG
+#define RT_THREAD_DEBUG
+
+#define RT_USING_OVERFLOW_CHECK
+
+/* Using Hook */
+#define RT_USING_HOOK
+
+/* Using Software Timer */
+/* #define RT_USING_TIMER_SOFT */
+#define RT_TIMER_THREAD_PRIO		4
+#define RT_TIMER_THREAD_STACK_SIZE	512
+#define RT_TIMER_TICK_PER_SECOND	10
+
+/* SECTION: IPC */
+/* Using Semaphore*/
+#define RT_USING_SEMAPHORE
+
+/* Using Mutex */
+#define RT_USING_MUTEX
+
+/* Using Event */
+#define RT_USING_EVENT
+
+/* Using MailBox */
+#define RT_USING_MAILBOX
+
+/* Using Message Queue */
+#define RT_USING_MESSAGEQUEUE
+
+/* SECTION: Memory Management */
+/* Using Memory Pool Management*/
+#define RT_USING_MEMPOOL
+
+/* Using Dynamic Heap Management */
+#define RT_USING_HEAP
+
+/* Using Small MM */
+#define RT_USING_SMALL_MEM
+
+/* SECTION: Device System */
+/* Using Device System */
+#define RT_USING_DEVICE
+#define RT_USING_UART1
+
+/* SECTION: Console options */
+#define RT_USING_CONSOLE
+/* the buffer size of console*/
+#define RT_CONSOLEBUF_SIZE	128
+
+/* SECTION: finsh, a C-Express shell */
+#define RT_USING_FINSH
+/* Using symbol table */
+#define FINSH_USING_SYMTAB
+#define FINSH_USING_DESCRIPTION
+
+/* SECTION: device filesystem */
+/* #define RT_USING_DFS */
+#define RT_USING_DFS_ELMFAT
+#define RT_DFS_ELM_REENTRANT
+#define RT_DFS_ELM_WORD_ACCESS
+#define RT_DFS_ELM_DRIVES			1
+#define RT_DFS_ELM_USE_LFN			2
+#define RT_DFS_ELM_MAX_LFN			255
+#define RT_DFS_ELM_MAX_SECTOR_SIZE  512
+
+/* the max number of mounted filesystem */
+#define DFS_FILESYSTEMS_MAX			2
+/* the max number of opened files 		*/
+#define DFS_FD_MAX					4
+
+/* SECTION: lwip, a lighwight TCP/IP protocol stack */
+/* #define RT_USING_LWIP */
+/* LwIP uses RT-Thread Memory Management */
+#define RT_LWIP_USING_RT_MEM
+/* Enable ICMP protocol*/
+#define RT_LWIP_ICMP
+/* Enable UDP protocol*/
+#define RT_LWIP_UDP
+/* Enable TCP protocol*/
+#define RT_LWIP_TCP
+/* Enable DNS */
+#define RT_LWIP_DNS
+
+/* the number of simulatenously active TCP connections*/
+#define RT_LWIP_TCP_PCB_NUM	5
+
+/* ip address of target*/
+#define RT_LWIP_IPADDR0	192
+#define RT_LWIP_IPADDR1	168
+#define RT_LWIP_IPADDR2	1
+#define RT_LWIP_IPADDR3	30
+
+/* gateway address of target*/
+#define RT_LWIP_GWADDR0	192
+#define RT_LWIP_GWADDR1	168
+#define RT_LWIP_GWADDR2	1
+#define RT_LWIP_GWADDR3	1
+
+/* mask address of target*/
+#define RT_LWIP_MSKADDR0	255
+#define RT_LWIP_MSKADDR1	255
+#define RT_LWIP_MSKADDR2	255
+#define RT_LWIP_MSKADDR3	0
+
+/* tcp thread options */
+#define RT_LWIP_TCPTHREAD_PRIORITY		12
+#define RT_LWIP_TCPTHREAD_MBOX_SIZE		4
+#define RT_LWIP_TCPTHREAD_STACKSIZE		1024
+
+/* ethernet if thread options */
+#define RT_LWIP_ETHTHREAD_PRIORITY		15
+#define RT_LWIP_ETHTHREAD_MBOX_SIZE		4
+#define RT_LWIP_ETHTHREAD_STACKSIZE		512
+
+#endif
diff --git a/bsp/stm32f40x/rtconfig.py b/bsp/stm32f40x/rtconfig.py
new file mode 100644
index 0000000000..52820dfaf8
--- /dev/null
+++ b/bsp/stm32f40x/rtconfig.py
@@ -0,0 +1,111 @@
+# toolchains options
+ARCH='arm'
+CPU='cortex-m4'
+CROSS_TOOL='keil'
+
+if  CROSS_TOOL == 'gcc':
+	PLATFORM 	= 'gcc'
+	EXEC_PATH 	= 'E:/SourceryGCC/bin'
+elif CROSS_TOOL == 'keil':
+	PLATFORM 	= 'armcc'
+	EXEC_PATH 	= 'E:/Keil'
+elif CROSS_TOOL == 'iar':
+	PLATFORM 	= 'iar'
+	IAR_PATH 	= 'E:/Program Files/IAR Systems/Embedded Workbench 5.4 Evaluation_0'	
+
+BUILD = 'debug'
+
+if PLATFORM == 'gcc':
+    # toolchains
+    PREFIX = 'arm-none-eabi-'
+    CC = PREFIX + 'gcc'
+    AS = PREFIX + 'gcc'
+    AR = PREFIX + 'ar'
+    LINK = PREFIX + 'gcc'
+    TARGET_EXT = 'axf'
+    SIZE = PREFIX + 'size'
+    OBJDUMP = PREFIX + 'objdump'
+    OBJCPY = PREFIX + 'objcopy'
+
+    DEVICE = ' -mcpu=cortex-m3 -mthumb -ffunction-sections -fdata-sections'
+    CFLAGS = DEVICE
+    AFLAGS = ' -c' + DEVICE + ' -x assembler-with-cpp'
+    LFLAGS = DEVICE + ' -Wl,--gc-sections,-Map=rtthread-stm32.map,-cref,-u,Reset_Handler -T stm32_rom.ld'
+
+    CPATH = ''
+    LPATH = ''
+
+    if BUILD == 'debug':
+        CFLAGS += ' -O0 -gdwarf-2'
+        AFLAGS += ' -gdwarf-2'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = OBJCPY + ' -O binary $TARGET rtthread.bin\n' + SIZE + ' $TARGET \n'
+
+elif PLATFORM == 'armcc':
+    # toolchains
+    CC = 'armcc'
+    AS = 'armasm'
+    AR = 'armar'
+    LINK = 'armlink'
+    TARGET_EXT = 'axf'
+
+    DEVICE = ' --device DARMSTM'
+    CFLAGS = DEVICE + ' --apcs=interwork'
+    AFLAGS = DEVICE
+    LFLAGS = DEVICE + ' --info sizes --info totals --info unused --info veneers --list rtthread-stm32.map --scatter stm32_rom.sct'
+
+    CFLAGS += ' -I' + EXEC_PATH + '/ARM/RV31/INC'
+    LFLAGS += ' --libpath ' + EXEC_PATH + '/ARM/RV31/LIB'
+
+    EXEC_PATH += '/arm/bin40/'
+
+    if BUILD == 'debug':
+        CFLAGS += ' -g -O0'
+        AFLAGS += ' -g'
+    else:
+        CFLAGS += ' -O2'
+
+    POST_ACTION = 'fromelf --bin $TARGET --output rtthread.bin \nfromelf -z $TARGET'
+
+elif PLATFORM == 'iar':
+    # toolchains
+    CC = 'iccarm'
+    AS = 'iasmarm'
+    AR = 'iarchive'
+    LINK = 'ilinkarm'
+    TARGET_EXT = 'out'
+
+    DEVICE = ' -D USE_STDPERIPH_DRIVER'
+
+    CFLAGS = DEVICE
+    CFLAGS += ' --diag_suppress Pa050'
+    CFLAGS += ' --no_cse' 
+    CFLAGS += ' --no_unroll' 
+    CFLAGS += ' --no_inline' 
+    CFLAGS += ' --no_code_motion' 
+    CFLAGS += ' --no_tbaa' 
+    CFLAGS += ' --no_clustering' 
+    CFLAGS += ' --no_scheduling' 
+    CFLAGS += ' --debug' 
+    CFLAGS += ' --endian=little' 
+    CFLAGS += ' --cpu=Cortex-M3' 
+    CFLAGS += ' -e' 
+    CFLAGS += ' --fpu=None'
+    CFLAGS += ' --dlib_config "' + IAR_PATH + '/arm/INC/c/DLib_Config_Normal.h"'    
+    CFLAGS += ' -Ol'    
+        
+    AFLAGS = ''
+    AFLAGS += ' -s+' 
+    AFLAGS += ' -w+' 
+    AFLAGS += ' -r' 
+    AFLAGS += ' --cpu Cortex-M3' 
+    AFLAGS += ' --fpu None' 
+
+    LFLAGS = ' --config stm32_rom.icf'
+    LFLAGS += ' --semihosting' 
+    LFLAGS += ' --entry __iar_program_start'    
+
+    EXEC_PATH = IAR_PATH + '/arm/bin/'
+    POST_ACTION = ''
diff --git a/bsp/stm32f40x/serial.c b/bsp/stm32f40x/serial.c
new file mode 100644
index 0000000000..c031287f7f
--- /dev/null
+++ b/bsp/stm32f40x/serial.c
@@ -0,0 +1,418 @@
+/*
+ * File      : serial.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-02-05     Bernard      first version
+ * 2009-10-25     Bernard      fix rt_serial_read bug when there is no data
+ *                             in the buffer.
+ * 2010-03-29     Bernard      cleanup code.
+ */
+
+#include "serial.h"
+#include 
+#include 
+
+static void rt_serial_enable_dma(DMA_Stream_TypeDef* dma_channel,
+	rt_uint32_t address, rt_uint32_t size);
+
+/**
+ * @addtogroup STM32
+ */
+/*@{*/
+
+/* RT-Thread Device Interface */
+static rt_err_t rt_serial_init (rt_device_t dev)
+{
+	struct stm32_serial_device* uart = (struct stm32_serial_device*) dev->user_data;
+
+	if (!(dev->flag & RT_DEVICE_FLAG_ACTIVATED))
+	{
+		if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+		{
+			rt_memset(uart->int_rx->rx_buffer, 0,
+				sizeof(uart->int_rx->rx_buffer));
+			uart->int_rx->read_index = 0;
+			uart->int_rx->save_index = 0;
+		}
+
+		if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
+		{
+			RT_ASSERT(uart->dma_tx->dma_channel != RT_NULL);
+			uart->dma_tx->list_head = uart->dma_tx->list_tail = RT_NULL;
+
+			/* init data node memory pool */
+			rt_mp_init(&(uart->dma_tx->data_node_mp), "dn",
+				uart->dma_tx->data_node_mem_pool,
+				sizeof(uart->dma_tx->data_node_mem_pool),
+				sizeof(struct stm32_serial_data_node));
+		}
+
+		/* Enable USART */
+		USART_Cmd(uart->uart_device, ENABLE);
+
+		dev->flag |= RT_DEVICE_FLAG_ACTIVATED;
+	}
+
+	return RT_EOK;
+}
+
+static rt_err_t rt_serial_open(rt_device_t dev, rt_uint16_t oflag)
+{
+	return RT_EOK;
+}
+
+static rt_err_t rt_serial_close(rt_device_t dev)
+{
+	return RT_EOK;
+}
+
+static rt_size_t rt_serial_read (rt_device_t dev, rt_off_t pos, void* buffer, rt_size_t size)
+{
+	rt_uint8_t* ptr;
+	rt_err_t err_code;
+	struct stm32_serial_device* uart;
+
+	ptr = buffer;
+	err_code = RT_EOK;
+	uart = (struct stm32_serial_device*)dev->user_data;
+
+	if (dev->flag & RT_DEVICE_FLAG_INT_RX)
+	{
+		/* interrupt mode Rx */
+		while (size)
+		{
+			rt_base_t level;
+
+			/* disable interrupt */
+			level = rt_hw_interrupt_disable();
+
+			if (uart->int_rx->read_index != uart->int_rx->save_index)
+			{
+				/* read a character */
+				*ptr++ = uart->int_rx->rx_buffer[uart->int_rx->read_index];
+				size--;
+
+				/* move to next position */
+				uart->int_rx->read_index ++;
+				if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+					uart->int_rx->read_index = 0;
+			}
+			else
+			{
+				/* set error code */
+				err_code = -RT_EEMPTY;
+
+				/* enable interrupt */
+				rt_hw_interrupt_enable(level);
+				break;
+			}
+
+			/* enable interrupt */
+			rt_hw_interrupt_enable(level);
+		}
+	}
+	else
+	{
+		/* polling mode */
+		while ((rt_uint32_t)ptr - (rt_uint32_t)buffer < size)
+		{
+			while (uart->uart_device->SR & USART_FLAG_RXNE)
+			{
+				*ptr = uart->uart_device->DR & 0xff;
+				ptr ++;
+			}
+		}
+	}
+
+	/* set error code */
+	rt_set_errno(err_code);
+	return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static void rt_serial_enable_dma(DMA_Stream_TypeDef* dma_channel,
+	rt_uint32_t address, rt_uint32_t size)
+{
+	RT_ASSERT(dma_channel != RT_NULL);
+
+	/* disable DMA */
+	DMA_Cmd(dma_channel, DISABLE);
+
+	/* set buffer address */
+	dma_channel->M0AR = address;
+	/* set size */
+	dma_channel->NDTR = size;
+
+	/* enable DMA */
+	DMA_Cmd(dma_channel, ENABLE);
+}
+
+static rt_size_t rt_serial_write (rt_device_t dev, rt_off_t pos, const void* buffer, rt_size_t size)
+{
+	rt_uint8_t* ptr;
+	rt_err_t err_code;
+	struct stm32_serial_device* uart;
+
+	err_code = RT_EOK;
+	ptr = (rt_uint8_t*)buffer;
+	uart = (struct stm32_serial_device*)dev->user_data;
+
+	if (dev->flag & RT_DEVICE_FLAG_INT_TX)
+	{
+		/* interrupt mode Tx, does not support */
+		RT_ASSERT(0);
+	}
+	else if (dev->flag & RT_DEVICE_FLAG_DMA_TX)
+	{
+		/* DMA mode Tx */
+
+		/* allocate a data node */
+		struct stm32_serial_data_node* data_node = (struct stm32_serial_data_node*)
+			rt_mp_alloc (&(uart->dma_tx->data_node_mp), RT_WAITING_FOREVER);
+		if (data_node == RT_NULL)
+		{
+			/* set error code */
+			err_code = -RT_ENOMEM;
+		}
+		else
+		{
+			rt_uint32_t level;
+
+			/* fill data node */
+			data_node->data_ptr 	= ptr;
+			data_node->data_size 	= size;
+
+			/* insert to data link */
+			data_node->next = RT_NULL;
+
+			/* disable interrupt */
+			level = rt_hw_interrupt_disable();
+
+			data_node->prev = uart->dma_tx->list_tail;
+			if (uart->dma_tx->list_tail != RT_NULL)
+				uart->dma_tx->list_tail->next = data_node;
+			uart->dma_tx->list_tail = data_node;
+
+			if (uart->dma_tx->list_head == RT_NULL)
+			{
+				/* start DMA to transmit data */
+				uart->dma_tx->list_head = data_node;
+
+				/* Enable DMA Channel */
+				rt_serial_enable_dma(uart->dma_tx->dma_channel,
+					(rt_uint32_t)uart->dma_tx->list_head->data_ptr,
+					uart->dma_tx->list_head->data_size);
+			}
+
+			/* enable interrupt */
+			rt_hw_interrupt_enable(level);
+		}
+	}
+	else
+	{
+		/* polling mode */
+		if (dev->flag & RT_DEVICE_FLAG_STREAM)
+		{
+			/* stream mode */
+			while (size)
+			{
+				if (*ptr == '\n')
+				{
+					while (!(uart->uart_device->SR & USART_FLAG_TXE));
+					uart->uart_device->DR = '\r';
+				}
+
+				while (!(uart->uart_device->SR & USART_FLAG_TXE));
+				uart->uart_device->DR = (*ptr & 0x1FF);
+
+				++ptr; --size;
+			}
+		}
+		else
+		{
+			/* write data directly */
+			while (size)
+			{
+				while (!(uart->uart_device->SR & USART_FLAG_TXE));
+				uart->uart_device->DR = (*ptr & 0x1FF);
+
+				++ptr; --size;
+			}
+		}
+	}
+
+	/* set error code */
+	rt_set_errno(err_code);
+
+	return (rt_uint32_t)ptr - (rt_uint32_t)buffer;
+}
+
+static rt_err_t rt_serial_control (rt_device_t dev, rt_uint8_t cmd, void *args)
+{
+	struct stm32_serial_device* uart;
+
+	RT_ASSERT(dev != RT_NULL);
+
+	uart = (struct stm32_serial_device*)dev->user_data;
+	switch (cmd)
+	{
+	case RT_DEVICE_CTRL_SUSPEND:
+		/* suspend device */
+		dev->flag |= RT_DEVICE_FLAG_SUSPENDED;
+		USART_Cmd(uart->uart_device, DISABLE);
+		break;
+
+	case RT_DEVICE_CTRL_RESUME:
+		/* resume device */
+		dev->flag &= ~RT_DEVICE_FLAG_SUSPENDED;
+		USART_Cmd(uart->uart_device, ENABLE);
+		break;
+	}
+
+	return RT_EOK;
+}
+
+/*
+ * serial register for STM32
+ * support STM32F103VB and STM32F103ZE
+ */
+rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial)
+{
+	RT_ASSERT(device != RT_NULL);
+
+	if ((flag & RT_DEVICE_FLAG_DMA_RX) ||
+		(flag & RT_DEVICE_FLAG_INT_TX))
+	{
+		RT_ASSERT(0);
+	}
+
+	device->type 		= RT_Device_Class_Char;
+	device->rx_indicate = RT_NULL;
+	device->tx_complete = RT_NULL;
+	device->init 		= rt_serial_init;
+	device->open		= rt_serial_open;
+	device->close		= rt_serial_close;
+	device->read 		= rt_serial_read;
+	device->write 		= rt_serial_write;
+	device->control 	= rt_serial_control;
+	device->user_data	= serial;
+
+	/* register a character device */
+	return rt_device_register(device, name, RT_DEVICE_FLAG_RDWR | flag);
+}
+
+/* ISR for serial interrupt */
+void rt_hw_serial_isr(rt_device_t device)
+{
+	struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data;
+
+	if(USART_GetITStatus(uart->uart_device, USART_IT_RXNE) != RESET)
+	{
+		/* interrupt mode receive */
+		RT_ASSERT(device->flag & RT_DEVICE_FLAG_INT_RX);
+
+		/* save on rx buffer */
+		while (uart->uart_device->SR & USART_FLAG_RXNE)
+		{
+			rt_base_t level;
+
+			/* disable interrupt */
+			level = rt_hw_interrupt_disable();
+
+			/* save character */
+			uart->int_rx->rx_buffer[uart->int_rx->save_index] = uart->uart_device->DR & 0xff;
+			uart->int_rx->save_index ++;
+			if (uart->int_rx->save_index >= UART_RX_BUFFER_SIZE)
+				uart->int_rx->save_index = 0;
+
+			/* if the next position is read index, discard this 'read char' */
+			if (uart->int_rx->save_index == uart->int_rx->read_index)
+			{
+				uart->int_rx->read_index ++;
+				if (uart->int_rx->read_index >= UART_RX_BUFFER_SIZE)
+					uart->int_rx->read_index = 0;
+			}
+
+			/* enable interrupt */
+			rt_hw_interrupt_enable(level);
+		}
+
+		/* clear interrupt */
+		USART_ClearITPendingBit(uart->uart_device, USART_IT_RXNE);
+
+		/* invoke callback */
+		if (device->rx_indicate != RT_NULL)
+		{
+			rt_size_t rx_length;
+
+			/* get rx length */
+			rx_length = uart->int_rx->read_index > uart->int_rx->save_index ?
+				UART_RX_BUFFER_SIZE - uart->int_rx->read_index + uart->int_rx->save_index :
+				uart->int_rx->save_index - uart->int_rx->read_index;
+
+			device->rx_indicate(device, rx_length);
+		}
+	}
+
+	if (USART_GetITStatus(uart->uart_device, USART_IT_TC) != RESET)
+	{
+		/* clear interrupt */
+		USART_ClearITPendingBit(uart->uart_device, USART_IT_TC);
+	}
+}
+
+/*
+ * ISR for DMA mode Tx
+ */
+void rt_hw_serial_dma_tx_isr(rt_device_t device)
+{
+	rt_uint32_t level;
+	struct stm32_serial_data_node* data_node;
+	struct stm32_serial_device* uart = (struct stm32_serial_device*) device->user_data;
+
+	/* DMA mode receive */
+	RT_ASSERT(device->flag & RT_DEVICE_FLAG_DMA_TX);
+
+	/* get the first data node */
+	data_node = uart->dma_tx->list_head;
+	RT_ASSERT(data_node != RT_NULL);
+
+	/* invoke call to notify tx complete */
+	if (device->tx_complete != RT_NULL)
+		device->tx_complete(device, data_node->data_ptr);
+
+	/* disable interrupt */
+	level = rt_hw_interrupt_disable();
+
+	/* remove list head */
+	uart->dma_tx->list_head = data_node->next;
+	if (uart->dma_tx->list_head == RT_NULL) /* data link empty */
+		uart->dma_tx->list_tail = RT_NULL;
+
+	/* enable interrupt */
+	rt_hw_interrupt_enable(level);
+
+	/* release data node memory */
+	rt_mp_free(data_node);
+
+	if (uart->dma_tx->list_head != RT_NULL)
+	{
+		/* transmit next data node */
+		rt_serial_enable_dma(uart->dma_tx->dma_channel,
+			(rt_uint32_t)uart->dma_tx->list_head->data_ptr,
+			uart->dma_tx->list_head->data_size);
+	}
+	else
+	{
+		/* no data to be transmitted, disable DMA */
+		DMA_Cmd(uart->dma_tx->dma_channel, DISABLE);
+	}
+}
+
+/*@}*/
diff --git a/bsp/stm32f40x/serial.h b/bsp/stm32f40x/serial.h
new file mode 100644
index 0000000000..aa8ceb72e1
--- /dev/null
+++ b/bsp/stm32f40x/serial.h
@@ -0,0 +1,70 @@
+/*
+ * File      : serial.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009 - 2010, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      first version
+ * 2010-03-29     Bernard      remove interrupt tx and DMA rx mode.
+ */
+#ifndef __RT_HW_SERIAL_H__
+#define __RT_HW_SERIAL_H__
+
+#include 
+#include 
+
+/* STM32F40x library definitions */
+#include 
+
+#define UART_RX_BUFFER_SIZE		64
+#define UART_TX_DMA_NODE_SIZE	4
+
+/* data node for Tx Mode */
+struct stm32_serial_data_node
+{
+	rt_uint8_t *data_ptr;
+	rt_size_t  data_size;
+	struct stm32_serial_data_node *next, *prev;
+};
+struct stm32_serial_dma_tx
+{
+	/* DMA Channel */
+	DMA_Stream_TypeDef* dma_channel;
+
+	/* data list head and tail */
+	struct stm32_serial_data_node *list_head, *list_tail;
+
+	/* data node memory pool */
+	struct rt_mempool data_node_mp;
+	rt_uint8_t data_node_mem_pool[UART_TX_DMA_NODE_SIZE *
+		(sizeof(struct stm32_serial_data_node) + sizeof(void*))];
+};
+
+struct stm32_serial_int_rx
+{
+	rt_uint8_t  rx_buffer[UART_RX_BUFFER_SIZE];
+	rt_uint32_t read_index, save_index;
+};
+
+struct stm32_serial_device
+{
+	USART_TypeDef* uart_device;
+
+	/* rx structure */
+	struct stm32_serial_int_rx* int_rx;
+
+	/* tx structure */
+	struct stm32_serial_dma_tx* dma_tx;
+};
+
+rt_err_t rt_hw_serial_register(rt_device_t device, const char* name, rt_uint32_t flag, struct stm32_serial_device *serial);
+
+void rt_hw_serial_isr(rt_device_t device);
+void rt_hw_serial_dma_tx_isr(rt_device_t device);
+
+#endif
diff --git a/bsp/stm32f40x/startup.c b/bsp/stm32f40x/startup.c
new file mode 100644
index 0000000000..1778657e1f
--- /dev/null
+++ b/bsp/stm32f40x/startup.c
@@ -0,0 +1,147 @@
+/*
+ * File      : startup.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2006, RT-Thread Develop Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://openlab.rt-thread.com/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2006-08-31     Bernard      first implementation
+ */
+
+#include 
+#include 
+
+#include 
+#include "board.h"
+
+/**
+ * @addtogroup STM32
+ */
+
+/*@{*/
+
+extern int  rt_application_init(void);
+#ifdef RT_USING_FINSH
+extern void finsh_system_init(void);
+extern void finsh_set_device(const char* device);
+#endif
+
+#ifdef __CC_ARM
+extern int Image$$RW_IRAM1$$ZI$$Limit;
+#elif __ICCARM__
+#pragma section="HEAP"
+#else
+extern int __bss_end;
+#endif
+
+#ifdef  DEBUG
+/*******************************************************************************
+* Function Name  : assert_failed
+* Description    : Reports the name of the source file and the source line number
+*                  where the assert error has occurred.
+* Input          : - file: pointer to the source file name
+*                  - line: assert error line source number
+* Output         : None
+* Return         : None
+*******************************************************************************/
+void assert_failed(u8* file, u32 line)
+{
+	rt_kprintf("\n\r Wrong parameter value detected on\r\n");
+	rt_kprintf("       file  %s\r\n", file);
+	rt_kprintf("       line  %d\r\n", line);
+
+	while (1) ;
+}
+#endif
+
+/**
+ * This function will startup RT-Thread RTOS.
+ */
+void rtthread_startup(void)
+{
+	/* init board */
+	rt_hw_board_init();
+
+	/* show version */
+	rt_show_version();
+
+	/* init tick */
+	rt_system_tick_init();
+
+	/* init kernel object */
+	rt_system_object_init();
+
+	/* init timer system */
+	rt_system_timer_init();
+
+#ifdef RT_USING_HEAP
+#if STM32_EXT_SRAM
+	rt_system_heap_init((void*)STM32_EXT_SRAM_BEGIN, (void*)STM32_EXT_SRAM_END);
+#else
+	#ifdef __CC_ARM
+		rt_system_heap_init((void*)&Image$$RW_IRAM1$$ZI$$Limit, (void*)STM32_SRAM_END);
+	#elif __ICCARM__
+	    rt_system_heap_init(__segment_end("HEAP"), (void*)STM32_SRAM_END);
+	#else
+		/* init memory system */
+		rt_system_heap_init((void*)&__bss_end, (void*)STM32_SRAM_END);
+	#endif
+#endif
+#endif
+
+	/* init scheduler system */
+	rt_system_scheduler_init();
+
+#ifdef RT_USING_DFS
+	/* init sdcard driver */
+#if STM32_USE_SDIO
+	rt_hw_sdcard_init();
+#else
+	rt_hw_msd_init();
+#endif
+#endif
+
+	/* init all device */
+	rt_device_init_all();
+
+	/* init application */
+	rt_application_init();
+
+#ifdef RT_USING_FINSH
+	/* init finsh */
+	finsh_system_init();
+	finsh_set_device(CONSOLE_DEVICE);
+#endif
+
+    /* init timer thread */
+    rt_system_timer_thread_init();
+
+	/* init idle thread */
+	rt_thread_idle_init();
+
+	/* start scheduler */
+	rt_system_scheduler_start();
+
+	/* never reach here */
+	return ;
+}
+
+int main(void)
+{
+	/* disable interrupt first */
+	rt_hw_interrupt_disable();
+
+	/* init system setting */
+	SystemInit();
+
+	/* startup RT-Thread RTOS */
+	rtthread_startup();
+
+	return 0;
+}
+
+/*@}*/
diff --git a/bsp/stm32f40x/stm32f4xx_conf.h b/bsp/stm32f40x/stm32f4xx_conf.h
new file mode 100644
index 0000000000..9d0cc20210
--- /dev/null
+++ b/bsp/stm32f40x/stm32f4xx_conf.h
@@ -0,0 +1,94 @@
+/**
+  ******************************************************************************
+  * @file    IO_Toggle/stm32f4xx_conf.h  
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   Library configuration file.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_CONF_H
+#define __STM32F4xx_CONF_H
+
+#if defined  (HSE_VALUE)
+/* Redefine the HSE value; it's equal to 8 MHz on the STM32F4-DISCOVERY Kit */
+ #undef HSE_VALUE
+ #define HSE_VALUE    ((uint32_t)8000000) 
+#endif /* HSE_VALUE */
+
+/* Includes ------------------------------------------------------------------*/
+/* Uncomment the line below to enable peripheral header file inclusion */
+#include "stm32f4xx_adc.h"
+#include "stm32f4xx_can.h"
+#include "stm32f4xx_crc.h"
+#include "stm32f4xx_cryp.h"
+#include "stm32f4xx_dac.h"
+#include "stm32f4xx_dbgmcu.h"
+#include "stm32f4xx_dcmi.h"
+#include "stm32f4xx_dma.h"
+#include "stm32f4xx_exti.h"
+#include "stm32f4xx_flash.h"
+#include "stm32f4xx_fsmc.h"
+#include "stm32f4xx_hash.h"
+#include "stm32f4xx_gpio.h"
+#include "stm32f4xx_i2c.h"
+#include "stm32f4xx_iwdg.h"
+#include "stm32f4xx_pwr.h"
+#include "stm32f4xx_rcc.h"
+#include "stm32f4xx_rng.h"
+#include "stm32f4xx_rtc.h"
+#include "stm32f4xx_sdio.h"
+#include "stm32f4xx_spi.h"
+#include "stm32f4xx_syscfg.h"
+#include "stm32f4xx_tim.h"
+#include "stm32f4xx_usart.h"
+#include "stm32f4xx_wwdg.h"
+#include "misc.h" /* High level functions for NVIC and SysTick (add-on to CMSIS functions) */
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+
+/* If an external clock source is used, then the value of the following define 
+   should be set to the value of the external clock source, else, if no external 
+   clock is used, keep this define commented */
+/*#define I2S_EXTERNAL_CLOCK_VAL   12288000 */ /* Value of the external clock in Hz */
+
+
+/* Uncomment the line below to expanse the "assert_param" macro in the 
+   Standard Peripheral Library drivers code */
+/* #define USE_FULL_ASSERT    1 */
+
+/* Exported macro ------------------------------------------------------------*/
+#ifdef  USE_FULL_ASSERT
+
+/**
+  * @brief  The assert_param macro is used for function's parameters check.
+  * @param  expr: If expr is false, it calls assert_failed function
+  *   which reports the name of the source file and the source
+  *   line number of the call that failed. 
+  *   If expr is true, it returns no value.
+  * @retval None
+  */
+  #define assert_param(expr) ((expr) ? (void)0 : assert_failed((uint8_t *)__FILE__, __LINE__))
+/* Exported functions ------------------------------------------------------- */
+  void assert_failed(uint8_t* file, uint32_t line);
+#else
+  #define assert_param(expr) ((void)0)
+#endif /* USE_FULL_ASSERT */
+
+#endif /* __STM32F4xx_CONF_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/stm32f4xx_it.c b/bsp/stm32f40x/stm32f4xx_it.c
new file mode 100644
index 0000000000..0f4fd6a6bf
--- /dev/null
+++ b/bsp/stm32f40x/stm32f4xx_it.c
@@ -0,0 +1,136 @@
+/**
+  ******************************************************************************
+  * @file    IO_Toggle/stm32f4xx_it.c 
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   Main Interrupt Service Routines.
+  *          This file provides template for all exceptions handler and 
+  *          peripherals interrupt service routine.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */ 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx_it.h"
+
+/** @addtogroup STM32F4_Discovery_Peripheral_Examples
+  * @{
+  */
+
+/** @addtogroup IO_Toggle
+  * @{
+  */ 
+
+/* Private typedef -----------------------------------------------------------*/
+/* Private define ------------------------------------------------------------*/
+/* Private macro -------------------------------------------------------------*/
+/* Private variables ---------------------------------------------------------*/
+/* Private function prototypes -----------------------------------------------*/
+/* Private functions ---------------------------------------------------------*/
+
+/******************************************************************************/
+/*            Cortex-M4 Processor Exceptions Handlers                         */
+/******************************************************************************/
+
+/**
+  * @brief   This function handles NMI exception.
+  * @param  None
+  * @retval None
+  */
+void NMI_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Memory Manage exception.
+  * @param  None
+  * @retval None
+  */
+void MemManage_Handler(void)
+{
+  /* Go to infinite loop when Memory Manage exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Bus Fault exception.
+  * @param  None
+  * @retval None
+  */
+void BusFault_Handler(void)
+{
+  /* Go to infinite loop when Bus Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles Usage Fault exception.
+  * @param  None
+  * @retval None
+  */
+void UsageFault_Handler(void)
+{
+  /* Go to infinite loop when Usage Fault exception occurs */
+  while (1)
+  {
+  }
+}
+
+/**
+  * @brief  This function handles SVCall exception.
+  * @param  None
+  * @retval None
+  */
+void SVC_Handler(void)
+{
+}
+
+/**
+  * @brief  This function handles Debug Monitor exception.
+  * @param  None
+  * @retval None
+  */
+void DebugMon_Handler(void)
+{
+}
+
+/******************************************************************************/
+/*                 STM32F4xx Peripherals Interrupt Handlers                   */
+/*  Add here the Interrupt Handler for the used peripheral(s) (PPP), for the  */
+/*  available peripheral interrupt handler's name please refer to the startup */
+/*  file (startup_stm32f4xx.s).                                               */
+/******************************************************************************/
+
+/**
+  * @brief  This function handles PPP interrupt request.
+  * @param  None
+  * @retval None
+  */
+/*void PPP_IRQHandler(void)
+{
+}*/
+
+/**
+  * @}
+  */ 
+
+/**
+  * @}
+  */ 
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/stm32f4xx_it.h b/bsp/stm32f40x/stm32f4xx_it.h
new file mode 100644
index 0000000000..e29b25dbe8
--- /dev/null
+++ b/bsp/stm32f40x/stm32f4xx_it.h
@@ -0,0 +1,54 @@
+/**
+  ******************************************************************************
+  * @file    GPIO/IOToggle/stm32f4xx_it.h 
+  * @author  MCD Application Team
+  * @version V1.0.0
+  * @date    19-September-2011
+  * @brief   This file contains the headers of the interrupt handlers.
+  ******************************************************************************
+  * @attention
+  *
+  * THE PRESENT FIRMWARE WHICH IS FOR GUIDANCE ONLY AIMS AT PROVIDING CUSTOMERS
+  * WITH CODING INFORMATION REGARDING THEIR PRODUCTS IN ORDER FOR THEM TO SAVE
+  * TIME. AS A RESULT, STMICROELECTRONICS SHALL NOT BE HELD LIABLE FOR ANY
+  * DIRECT, INDIRECT OR CONSEQUENTIAL DAMAGES WITH RESPECT TO ANY CLAIMS ARISING
+  * FROM THE CONTENT OF SUCH FIRMWARE AND/OR THE USE MADE BY CUSTOMERS OF THE
+  * CODING INFORMATION CONTAINED HEREIN IN CONNECTION WITH THEIR PRODUCTS.
+  *
+  * 
    © COPYRIGHT 2011 STMicroelectronics
    
+  ******************************************************************************
+  */ 
+
+/* Define to prevent recursive inclusion -------------------------------------*/
+#ifndef __STM32F4xx_IT_H
+#define __STM32F4xx_IT_H
+
+#ifdef __cplusplus
+ extern "C" {
+#endif 
+
+/* Includes ------------------------------------------------------------------*/
+#include "stm32f4xx.h"
+
+/* Exported types ------------------------------------------------------------*/
+/* Exported constants --------------------------------------------------------*/
+/* Exported macro ------------------------------------------------------------*/
+/* Exported functions ------------------------------------------------------- */
+
+void NMI_Handler(void);
+void HardFault_Handler(void);
+void MemManage_Handler(void);
+void BusFault_Handler(void);
+void UsageFault_Handler(void);
+void SVC_Handler(void);
+void DebugMon_Handler(void);
+void PendSV_Handler(void);
+void SysTick_Handler(void);
+
+#ifdef __cplusplus
+}
+#endif
+
+#endif /* __STM32F4xx_IT_H */
+
+/******************* (C) COPYRIGHT 2011 STMicroelectronics *****END OF FILE****/
diff --git a/bsp/stm32f40x/template.uvproj b/bsp/stm32f40x/template.uvproj
new file mode 100644
index 0000000000..ce16bc94f2
--- /dev/null
+++ b/bsp/stm32f40x/template.uvproj
@@ -0,0 +1,388 @@
+
+
+
+  1.1
+
+  
    ### uVision Project, (C) Keil Software
    
+
+  
+    
+      RT-Thread STM32
+      0x4
+      ARM-ADS
+      
+        
+          STM32F207VG
+          STMicroelectronics
+          IRAM(0x20000000-0x2001FFFF) IROM(0x8000000-0x80FFFFF) CLOCK(25000000) CPUTYPE("Cortex-M3")
+          
+          "STARTUP\ST\STM32F2xx\startup_stm32f2xx.s" ("STM32F2xx Startup Code")
+          UL2CM3(-O207 -S0 -C0 -FO7 -FD20000000 -FC800 -FN1 -FF0STM32F2xx_1024 -FS08000000 -FL0100000)
+          5118
+          stm32f2xx.h
+          
+          
+          
+          
+          
+          
+          
+          
+          
+          SFD\ST\STM32F2xx\STM32F2xx.sfr
+          0
+          
+          
+          
+          ST\STM32F2xx\
+          ST\STM32F2xx\
+          
+            0
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+          
+          .\obj\
+          rtthread-stm32
+          1
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+          
+          
+        
+        
+          SARMCM3.DLL
+          -MPU
+          DARMSTM.DLL
+          -pSTM32F207VG
+          SARMCM3.DLL
+          -MPU
+          TARMSTM.DLL
+          -pSTM32F207VG
+        
+        
+          
+            1
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+            0
+            0
+            16
+          
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+            0
+            1
+            0
+            1
+            1
+            1
+            1
+            1
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+          
+          
+            1
+            1
+            1
+            1
+            1
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+            0
+            1
+          
+          0
+          7
+          
+            
+            
+            
+            
+            
+          
+          
+            
+            
+            
+            
+            
+            Segger\JL2CM3.dll
+          
+        
+        
+          
+            1
+            0
+            0
+            0
+            1
+            4099
+          
+          Segger\JL2CM3.dll
+          "" ()
+          
+        
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+            0
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+            "Cortex-M3"
+            
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+    
+  
+
+    
diff --git a/bsp/stm32f40x/usart.c b/bsp/stm32f40x/usart.c
new file mode 100644
index 0000000000..0874408283
--- /dev/null
+++ b/bsp/stm32f40x/usart.c
@@ -0,0 +1,281 @@
+/*
+ * File      : usart.c
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ * 2010-03-29     Bernard      remove interrupt Tx and DMA Rx mode
+ */
+
+#include "usart.h"
+#include 
+#include 
+#include 
+
+/*
+ * Use UART1 as console output and finsh input
+ * interrupt Rx and poll Tx (stream mode)
+ *
+ * Use UART2 with interrupt Rx and poll Tx
+ * Use UART3 with DMA Tx and interrupt Rx -- DMA channel 2
+ *
+ * USART DMA setting on STM32
+ * USART1 Tx --> DMA Channel 4
+ * USART1 Rx --> DMA Channel 5
+ * USART2 Tx --> DMA Channel 7
+ * USART2 Rx --> DMA Channel 6
+ * USART3 Tx --> DMA Channel 2
+ * USART3 Rx --> DMA Channel 3
+ */
+
+#ifdef RT_USING_UART1
+struct stm32_serial_int_rx uart1_int_rx;
+struct stm32_serial_device uart1 =
+{
+	USART1,
+	&uart1_int_rx,
+	RT_NULL
+};
+struct rt_device uart1_device;
+#endif
+
+#ifdef RT_USING_UART6
+struct stm32_serial_int_rx uart6_int_rx;
+struct stm32_serial_device uart6 =
+{
+	USART6,
+	&uart6_int_rx,
+	RT_NULL
+};
+struct rt_device uart6_device;
+#endif
+
+#ifdef RT_USING_UART2
+struct stm32_serial_int_rx uart2_int_rx;
+struct stm32_serial_device uart2 =
+{
+	USART2,
+	&uart2_int_rx,
+	RT_NULL
+};
+struct rt_device uart2_device;
+#endif
+
+#ifdef RT_USING_UART3
+struct stm32_serial_int_rx uart3_int_rx;
+struct stm32_serial_dma_tx uart3_dma_tx;
+struct stm32_serial_device uart3 =
+{
+	USART3,
+	&uart3_int_rx,
+	&uart3_dma_tx
+};
+struct rt_device uart3_device;
+#endif
+
+#define USART1_DR_Base  0x40013804
+#define USART2_DR_Base  0x40004404
+#define USART3_DR_Base  0x40004804
+
+/* USART1_REMAP = 0 */
+#define UART1_GPIO_TX		GPIO_Pin_9
+#define UART1_GPIO_RX		GPIO_Pin_10
+#define UART1_GPIO			GPIOA
+#define RCC_APBPeriph_UART1	RCC_APB2Periph_USART1
+#define UART1_TX_DMA		DMA1_Channel4
+#define UART1_RX_DMA		DMA1_Channel5
+
+#if defined(STM32F10X_LD) || defined(STM32F10X_MD) || defined(STM32F10X_CL)
+#define UART2_GPIO_TX	    GPIO_Pin_5
+#define UART2_GPIO_RX	    GPIO_Pin_6
+#define UART2_GPIO	    	GPIOD
+#define RCC_APBPeriph_UART2	RCC_APB1Periph_USART2
+#else /* for STM32F10X_HD */
+/* USART2_REMAP = 0 */
+#define UART2_GPIO_TX		GPIO_Pin_2
+#define UART2_GPIO_RX		GPIO_Pin_3
+#define UART2_GPIO			GPIOA
+#define RCC_APBPeriph_UART2	RCC_APB1Periph_USART2
+#define UART2_TX_DMA		DMA1_Channel7
+#define UART2_RX_DMA		DMA1_Channel6
+#endif
+
+/* USART3_REMAP[1:0] = 00 */
+#define UART3_GPIO_RX		GPIO_Pin_11
+#define UART3_GPIO_TX		GPIO_Pin_10
+#define UART3_GPIO			GPIOB
+#define RCC_APBPeriph_UART3	RCC_APB1Periph_USART3
+#define UART3_TX_DMA		DMA1_Channel2
+#define UART3_RX_DMA		DMA1_Channel3
+
+/* USART6_REMAP = 0 */
+#define UART6_GPIO_TX		GPIO_Pin_6
+#define UART6_GPIO_RX		GPIO_Pin_7
+#define UART6_GPIO			GPIOC
+#define RCC_APBPeriph_UART6	RCC_APB2Periph_USART6
+//#define UART1_TX_DMA		DMA1_Channel?
+//#define UART1_RX_DMA		DMA1_Channel?
+
+static void RCC_Configuration(void)
+{
+#ifdef RT_USING_UART1
+	/* Enable USART1 and GPIOA clocks */
+	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOA, ENABLE);
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE);
+#endif
+
+#ifdef RT_USING_UART6
+	/* Enable USART6 and GPIOC clocks */
+	RCC_AHB1PeriphClockCmd(RCC_AHB1Periph_GPIOC, ENABLE);
+	RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART6, ENABLE);
+#endif
+}
+
+static void GPIO_Configuration(void)
+{
+	GPIO_InitTypeDef GPIO_InitStruct;
+
+#ifdef RT_USING_UART1
+	GPIO_InitStruct.GPIO_Mode=GPIO_Mode_AF;
+	GPIO_InitStruct.GPIO_Speed=GPIO_Speed_50MHz;
+	GPIO_InitStruct.GPIO_OType=GPIO_OType_PP;
+	GPIO_InitStruct.GPIO_PuPd=GPIO_PuPd_UP;
+
+	GPIO_InitStruct.GPIO_Pin=GPIO_Pin_9|GPIO_Pin_10;
+	GPIO_Init(GPIOA,&GPIO_InitStruct);
+
+	GPIO_PinAFConfig(GPIOA, GPIO_PinSource9, GPIO_AF_USART1);
+	GPIO_PinAFConfig(GPIOA, GPIO_PinSource10, GPIO_AF_USART1);
+#endif
+
+#ifdef RT_USING_UART6
+	GPIO_InitStruct.GPIO_Mode=GPIO_Mode_AF;
+	GPIO_InitStruct.GPIO_Speed=GPIO_Speed_50MHz;
+	GPIO_InitStruct.GPIO_OType=GPIO_OType_PP;
+	GPIO_InitStruct.GPIO_PuPd=GPIO_PuPd_UP;
+
+	GPIO_InitStruct.GPIO_Pin=UART6_GPIO_TX|UART6_GPIO_RX;
+	GPIO_Init(UART6_GPIO,&GPIO_InitStruct);
+
+	GPIO_PinAFConfig(UART6_GPIO, GPIO_PinSource6, GPIO_AF_USART6);
+	GPIO_PinAFConfig(UART6_GPIO, GPIO_PinSource7, GPIO_AF_USART6);
+#endif
+}
+
+static void NVIC_Configuration(void)
+{
+	NVIC_InitTypeDef NVIC_InitStructure;
+
+#ifdef RT_USING_UART1
+	/* Enable the USART1 Interrupt */
+	NVIC_InitStructure.NVIC_IRQChannel = USART1_IRQn;
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+	NVIC_Init(&NVIC_InitStructure);
+#endif
+
+#ifdef RT_USING_UART6
+	/* Enable the USART1 Interrupt */
+	NVIC_InitStructure.NVIC_IRQChannel = USART6_IRQn;
+	NVIC_InitStructure.NVIC_IRQChannelPreemptionPriority = 0;
+	NVIC_InitStructure.NVIC_IRQChannelSubPriority = 0;
+	NVIC_InitStructure.NVIC_IRQChannelCmd = ENABLE;
+	NVIC_Init(&NVIC_InitStructure);
+#endif
+}
+
+/*
+ * Init all related hardware in here
+ * rt_hw_serial_init() will register all supported USART device
+ */
+void rt_hw_usart_init()
+{
+	USART_InitTypeDef USART_InitStructure;
+
+	RCC_Configuration();
+
+	GPIO_Configuration();
+
+	NVIC_Configuration();
+
+	/* uart init */
+#ifdef RT_USING_UART1
+	USART_DeInit(USART1);
+	USART_InitStructure.USART_BaudRate            = 115200;
+	USART_InitStructure.USART_WordLength          = USART_WordLength_8b;
+	USART_InitStructure.USART_StopBits            = USART_StopBits_1;
+	USART_InitStructure.USART_Parity              = USART_Parity_No ;
+	USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+	USART_InitStructure.USART_Mode                = USART_Mode_Rx | USART_Mode_Tx;
+
+	USART_Init(USART1, &USART_InitStructure);
+
+	/* register uart1 */
+	rt_hw_serial_register(&uart1_device, "uart1",
+		RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+		&uart1);
+
+	/* enable interrupt */
+	USART_ITConfig(USART1, USART_IT_RXNE, ENABLE);
+	/* Enable USART1 */
+	USART_Cmd(USART1, ENABLE);
+	USART_ClearFlag(USART1,USART_FLAG_TXE);
+#endif
+
+	/* uart init */
+#ifdef RT_USING_UART6
+	USART_DeInit(USART6);
+	USART_InitStructure.USART_BaudRate            = 115200;
+	USART_InitStructure.USART_WordLength          = USART_WordLength_8b;
+	USART_InitStructure.USART_StopBits            = USART_StopBits_1;
+	USART_InitStructure.USART_Parity              = USART_Parity_No ;
+	USART_InitStructure.USART_HardwareFlowControl = USART_HardwareFlowControl_None;
+	USART_InitStructure.USART_Mode                = USART_Mode_Rx | USART_Mode_Tx;
+
+	USART_Init(USART6, &USART_InitStructure);
+
+	/* register uart1 */
+	rt_hw_serial_register(&uart6_device, "uart6",
+		RT_DEVICE_FLAG_RDWR | RT_DEVICE_FLAG_INT_RX | RT_DEVICE_FLAG_STREAM,
+		&uart6);
+
+	/* enable interrupt */
+	USART_ITConfig(USART6, USART_IT_RXNE, ENABLE);
+	/* Enable USART6 */
+	USART_Cmd(USART6, ENABLE);
+	USART_ClearFlag(USART6,USART_FLAG_TXE);
+#endif
+}
+
+#ifdef RT_USING_UART1
+void USART1_IRQHandler()
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_hw_serial_isr(&uart1_device);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
+
+#ifdef RT_USING_UART6
+void USART6_IRQHandler()
+{
+    /* enter interrupt */
+    rt_interrupt_enter();
+
+    rt_hw_serial_isr(&uart6_device);
+
+    /* leave interrupt */
+    rt_interrupt_leave();
+}
+#endif
diff --git a/bsp/stm32f40x/usart.h b/bsp/stm32f40x/usart.h
new file mode 100644
index 0000000000..36c5f19b1e
--- /dev/null
+++ b/bsp/stm32f40x/usart.h
@@ -0,0 +1,23 @@
+/*
+ * File      : usart.h
+ * This file is part of RT-Thread RTOS
+ * COPYRIGHT (C) 2009, RT-Thread Development Team
+ *
+ * The license and distribution terms for this file may be
+ * found in the file LICENSE in this distribution or at
+ * http://www.rt-thread.org/license/LICENSE
+ *
+ * Change Logs:
+ * Date           Author       Notes
+ * 2009-01-05     Bernard      the first version
+ */
+
+#ifndef __USART_H__
+#define __USART_H__
+
+#include 
+#include 
+
+void rt_hw_usart_init(void);
+
+#endif