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Support for TawakiV2 (STM32H7) (#3199)

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* tawakiV2 support.
* clean and update linker scripts
* update ram configuration
* update chibios
* update airframe
This commit is contained in:
Fabien-B
2023-12-14 11:19:27 +01:00
committed by GitHub
parent 38d8388f3d
commit f7a981a0d0
28 changed files with 4331 additions and 175 deletions
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conf/airframes/ENAC/conf_enac.xml
+11
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@@ -153,4 +153,15 @@
settings_modules="modules/ahrs_int_cmpl_quat.xml modules/air_data.xml modules/electrical.xml modules/gps.xml modules/guidance_pid_rotorcraft.xml modules/guidance_rotorcraft.xml modules/imu_common.xml modules/nav_rotorcraft.xml modules/stabilization_int_quat.xml" settings_modules="modules/ahrs_int_cmpl_quat.xml modules/air_data.xml modules/electrical.xml modules/gps.xml modules/guidance_pid_rotorcraft.xml modules/guidance_rotorcraft.xml modules/imu_common.xml modules/nav_rotorcraft.xml modules/stabilization_int_quat.xml"
gui_color="red" gui_color="red"
/> />
<aircraft
name="CobraV2"
ac_id="11"
airframe="airframes/ENAC/quadrotor/cobraV2.xml"
radio="radios/FrSky_X-Lite.xml"
telemetry="telemetry/default_rotorcraft.xml"
flight_plan="flight_plans/rotorcraft_basic.xml"
settings="settings/rotorcraft_basic.xml"
settings_modules="modules/electrical.xml modules/gps.xml modules/guidance_indi.xml modules/guidance_rotorcraft.xml modules/imu_common.xml modules/ins_ekf2.xml modules/jevois.xml modules/logger_sd_chibios.xml modules/nav_rotorcraft.xml modules/preflight_checks.xml modules/stabilization_indi.xml modules/switch_servo.xml modules/tag_tracking.xml"
gui_color="#55005500ff00"
/>
</conf> </conf>
conf/airframes/ENAC/quadrotor/cobra.xml
+228
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@@ -0,0 +1,228 @@
<!DOCTYPE airframe SYSTEM "../../airframe.dtd">
<airframe name="Cobra">
<description>
* Autopilot: Tawaki
* Actuators: 4 in 1
* Telemetry: XBee
* GPS: datalink
* RC: SBUS
</description>
<firmware name="rotorcraft">
<!--configure name="RTOS_DEBUG" value="TRUE"/-->
<configure name="PERIODIC_FREQUENCY" value="500"/>
<configure name="AHRS_PROPAGATE_FREQUENCY" value="$(PERIODIC_FREQUENCY)"/>
<target name="ap" board="tawaki_1.1">
<module name="radio_control" type="sbus"/>
<configure name="BARO_PERIODIC_FREQUENCY" value="50"/>
<define name="RADIO_KILL_SWITCH" value="RADIO_GAIN1"/>
</target>
<target name="nps" board="pc">
<module name="fdm" type="jsbsim"/>
<module name="radio_control" type="ppm"/>
</target>
<module name="telemetry" type="xbee_api"/>
<!--module name="telemetry" type="transparent">
<configure name="MODEM_PORT" value="usb_serial"/>
</module-->
<module name="actuators" type="dshot"/>
<module name="actuators" type="pwm"/>
<module name="switch" type="servo"/>
<define name="SWITCH_SERVO_ON_VALUE" value="SERVO_SWITCH_MAX"/>
<define name="SWITCH_SERVO_OFF_VALUE" value="SERVO_SWITCH_MIN"/>
<module name="board" type="tawaki">
<define name="IMU_MPU_LOWPASS_FILTER" value="MPU60X0_DLPF_256HZ"/>
<define name="IMU_MPU_ACCEL_LOWPASS_FILTER" value="MPU60X0_DLPF_ACC_218HZ"/>
<define name="IMU_MPU_SMPLRT_DIV" value="0"/>
</module>
<!--module name="gps" type="ublox">
<configure name="GPS_BAUD" value="B115200"/>
<define name="USE_GPS_UBX_RTCM" value="TRUE"/>
<define name="GPS_FIX_TIMEOUT" value="0.5"/>
</module-->
<module name="gps" type="optitrack"/>
<module name="stabilization" type="indi"/>
<module name="guidance" type="indi"/>
<module name="ins" type="ekf2">
<define name="INS_EKF2_OPTITRACK" value="TRUE"/>
</module>
<module name="preflight_checks"/>
<!--module name="filter" type="1euro_imu">
<define name="AHRS_ICQ_IMU_ID" value="IMU_F1E_ID"/>
<define name="AHRS_ALIGNER_IMU_ID" value="IMU_F1E_ID"/>
</module-->
<module name="motor_mixing"/>
<module name="tag_tracking">
<configure name="JEVOIS_UART" value="UART3"/>
</module>
<module name="flight_recorder"/>
</firmware>
<servos driver="Pwm">
<servo name="SWITCH" no="1" min="800" neutral="800" max="1500"/>
</servos>
<servos driver="DShot">
<servo name="FR" no="3" min="0" neutral="100" max="2000"/>
<servo name="BR" no="4" min="0" neutral="100" max="2000"/>
<servo name="BL" no="2" min="0" neutral="100" max="2000"/>
<servo name="FL" no="1" min="0" neutral="100" max="2000"/>
</servos>
<commands>
<axis name="ROLL" failsafe_value="0"/>
<axis name="PITCH" failsafe_value="0"/>
<axis name="YAW" failsafe_value="0"/>
<axis name="THRUST" failsafe_value="0"/>
</commands>
<section name="MIXING" prefix="MOTOR_MIXING_">
<define name="TYPE" value="QUAD_X"/>
<define name="REVERSE" value="TRUE"/>
</section>
<command_laws>
<set servo="FR" value="autopilot_get_motors_on() ? actuators_pprz[0] : -MAX_PPRZ"/>
<set servo="BR" value="autopilot_get_motors_on() ? actuators_pprz[1] : -MAX_PPRZ"/>
<set servo="BL" value="autopilot_get_motors_on() ? actuators_pprz[2] : -MAX_PPRZ"/>
<set servo="FL" value="autopilot_get_motors_on() ? actuators_pprz[3] : -MAX_PPRZ"/>
</command_laws>
<section name="IMU" prefix="IMU_">
<define name="ACCEL_CALIB" value="{{.abi_id=9, .calibrated={.neutral=true, .scale=true},.neutral={-12,23,29}, .scale={{65369,62166,40813},{28737,25351,16753}}}}"/>
<!--define name="MAG_CALIB" value="{{.abi_id=3, .calibrated={.neutral=true, .scale=true},.neutral={-833,-5969,-931}, .scale={{22816,38799,15650},{34941,60353,24187}}}}"/-->
<define name="BODY_TO_IMU_PHI" value="0." unit="deg"/>
<define name="BODY_TO_IMU_THETA" value="0." unit="deg"/>
<define name="BODY_TO_IMU_PSI" value="180." unit="deg"/>
</section>
<include href="conf/mag/toulouse_muret.xml"/>
<section name="STABILIZATION_ATTITUDE" prefix="STABILIZATION_ATTITUDE_">
<!-- setpoint limits for attitude stabilization rc flight -->
<define name="SP_MAX_PHI" value="45" unit="deg"/>
<define name="SP_MAX_THETA" value="45" unit="deg"/>
<define name="SP_MAX_R" value="60" unit="deg/s"/>
<define name="DEADBAND_A" value="0"/>
<define name="DEADBAND_E" value="0"/>
<define name="DEADBAND_R" value="50"/>
</section>
<section name="STABILIZATION_ATTITUDE_INDI" prefix="STABILIZATION_INDI_">
<define name="NUM_ACT" value="4"/>
<!-- reference acceleration for attitude control -->
<define name="REF_ERR_P" value="120"/>
<define name="REF_ERR_Q" value="130"/>
<define name="REF_ERR_R" value="120"/>
<define name="REF_RATE_P" value="15"/>
<define name="REF_RATE_Q" value="15"/>
<define name="REF_RATE_R" value="10"/>
<define name="MAX_R" value="60" unit="deg/s"/>
<!-- second order filter parameters -->
<define name="FILT_CUTOFF" value="4.0"/>
<define name="FILT_CUTOFF_R" value="4.0"/>
<!-- Adaptive Learning Rate -->
<define name="USE_ADAPTIVE" value="FALSE"/>
<define name="ADAPTIVE_MU" value="0.0001"/>
<!-- Full INDI -->
<!-- control effectiveness -->
<define name="G1_ROLL" value="{ -20.0, -20.0, 20.0, 20.0 }"/>
<define name="G1_PITCH" value="{ 20.0, -20.0, -20.0, 20.0 }"/>
<define name="G1_YAW" value="{ 3, -3, 3, -3 }"/>
<define name="G1_THRUST" value="{ -1., -1., -1., -1.}"/>
<!--Counter torque effect of spinning up a rotor-->
<define name="G2" value="{80, -80, 80, -80.0 }"/>
<!-- first order actuator dynamics -->
<define name="ACT_FREQ" value="{10.10, 10.10, 10.10, 10.10}"/>
<define name="ESTIMATION_FILT_CUTOFF" value="4.0"/>
<!--Priority for each axis (roll, pitch, yaw and thrust)-->
<define name="WLS_PRIORITIES" value="{1000, 1000, 1, 100}"/>
</section>
<section name="GUIDANCE_V" prefix="GUIDANCE_V_">
<define name="REF_MIN_ZDD" value="-0.4*9.81"/>
<define name="REF_MAX_ZDD" value=" 0.4*9.81"/>
<define name="REF_MIN_ZD" value="-2."/>
<define name="REF_MAX_ZD" value=" 2."/>
<define name="HOVER_KP" value="90"/>
<define name="HOVER_KD" value="110"/>
<define name="HOVER_KI" value="10"/>
<define name="NOMINAL_HOVER_THROTTLE" value="0.35"/>
<define name="ADAPT_THROTTLE_ENABLED" value="TRUE"/>
<define name="ADAPT_NOISE_FACTOR" value="1."/>
<define name="ADAPT_INITIAL_HOVER_THROTTLE" value="0.3"/>
</section>
<section name="GUIDANCE_H" prefix="GUIDANCE_H_">
<define name="MAX_BANK" value="30" unit="deg"/>
<define name="PGAIN" value="41"/>
<define name="DGAIN" value="108"/>
<define name="IGAIN" value="20"/>
<define name="NGAIN" value="0"/>
<!-- feedforward -->
<define name="AGAIN" value="0"/>
<define name="REF_MAX_SPEED" value="0.5"/>
<define name="REF_MAX_ACCEL" value="2."/>
</section>
<section name="GUIDANCE_INDI" prefix="GUIDANCE_INDI_">
<define name="SPECIFIC_FORCE_GAIN" value="-500.0"/>
<define name="THRUST_DYNAMICS_FREQ" value="25.64"/>
<define name="RC_DEBUG" value="FALSE"/>
<define name="SPEED_GAINZ" value="2.5"/>
</section>
<section name="NAV">
<define name="ARRIVED_AT_WAYPOINT" value="0.25"/>
<define name="NAV_CLIMB_VSPEED" value="0.8"/>
<define name="NAV_DESCEND_VSPEED" value="-0.5"/>
<define name="NAV_CARROT_DIST" value="18"/>
</section>
<section name="BAT">
<define name="CRITIC_BAT_LEVEL" value="9.3" unit="V"/>
</section>
<section name="AUTOPILOT">
<define name="MODE_STARTUP" value="AP_MODE_NAV"/>
<define name="MODE_MANUAL" value="AP_MODE_ATTITUDE_DIRECT"/>
<define name="MODE_AUTO1" value="AP_MODE_ATTITUDE_Z_HOLD"/>
<define name="MODE_AUTO2" value="AP_MODE_NAV"/>
<define name="FAILSAFE_FIXED_THROTTLE" value="0.4"/>
</section>
<section name="TAG_TRACKING" prefix="TAG_TRACKING_">
<define name="BODY_TO_CAM_PSI" value="M_PI_2"/>
<define name="CAM_POS_X" value="0.15"/>
</section>
<section name="GCS">
<define name="ALT_SHIFT_PLUS_PLUS" value="3"/>
<define name="ALT_SHIFT_PLUS" value="1"/>
<define name="ALT_SHIFT_MINUS" value="-0.5"/>
</section>
<section name="SIMULATOR" prefix="NPS_">
<define name="ACTUATOR_NAMES" value="nw_motor, ne_motor, se_motor, sw_motor" type="string[]"/>
<define name="JSBSIM_MODEL" value="simple_x_quad_ccw" type="string"/>
</section>
</airframe>
conf/airframes/ENAC/quadrotor/cobraV2.xml
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@@ -0,0 +1,226 @@
<!DOCTYPE airframe SYSTEM "../../airframe.dtd">
<airframe name="CobraV2">
<description>
* Autopilot: TawakiV2
* Actuators: 4 in 1
* Telemetry: XBee
* GPS: datalink
* RC: SBUS
</description>
<firmware name="rotorcraft">
<configure name="RTOS_DEBUG" value="FALSE"/>
<configure name="PERIODIC_FREQUENCY" value="500"/>
<configure name="AHRS_PROPAGATE_FREQUENCY" value="$(PERIODIC_FREQUENCY)"/>
<target name="ap" board="tawaki_2.0">
<module name="radio_control" type="sbus"/>
<configure name="BARO_PERIODIC_FREQUENCY" value="50"/>
<define name="RADIO_KILL_SWITCH" value="RADIO_GAIN1"/>
</target>
<target name="nps" board="pc">
<module name="fdm" type="jsbsim"/>
<module name="radio_control" type="ppm"/>
</target>
<module name="telemetry" type="xbee_api"/>
<!--module name="telemetry" type="transparent">
<configure name="MODEM_PORT" value="usb_serial"/>
</module-->
<module name="actuators" type="dshot"/>
<module name="actuators" type="pwm"/>
<module name="switch" type="servo"/>
<define name="SWITCH_SERVO_ON_VALUE" value="SERVO_SWITCH_MAX"/>
<define name="SWITCH_SERVO_OFF_VALUE" value="SERVO_SWITCH_MIN"/>
<module name="board" type="tawaki_2.0">
</module>
<!--module name="gps" type="ublox">
<configure name="GPS_BAUD" value="B115200"/>
<define name="USE_GPS_UBX_RTCM" value="TRUE"/>
<define name="GPS_FIX_TIMEOUT" value="0.5"/>
</module-->
<module name="gps" type="optitrack"/>
<module name="stabilization" type="indi"/>
<module name="guidance" type="indi"/>
<module name="ins" type="ekf2">
<define name="INS_EKF2_OPTITRACK" value="TRUE"/>
</module>
<module name="preflight_checks"/>
<!--module name="filter" type="1euro_imu">
<define name="AHRS_ICQ_IMU_ID" value="IMU_F1E_ID"/>
<define name="AHRS_ALIGNER_IMU_ID" value="IMU_F1E_ID"/>
</module-->
<module name="motor_mixing"/>
<module name="tag_tracking">
<configure name="JEVOIS_UART" value="UART3"/>
</module>
<module name="flight_recorder"/>
</firmware>
<servos driver="Pwm">
<servo name="SWITCH" no="1" min="800" neutral="800" max="1500"/>
</servos>
<servos driver="DShot">
<servo name="FR" no="3" min="0" neutral="100" max="2000"/>
<servo name="BR" no="4" min="0" neutral="100" max="2000"/>
<servo name="BL" no="2" min="0" neutral="100" max="2000"/>
<servo name="FL" no="1" min="0" neutral="100" max="2000"/>
</servos>
<commands>
<axis name="ROLL" failsafe_value="0"/>
<axis name="PITCH" failsafe_value="0"/>
<axis name="YAW" failsafe_value="0"/>
<axis name="THRUST" failsafe_value="0"/>
</commands>
<section name="MIXING" prefix="MOTOR_MIXING_">
<define name="TYPE" value="QUAD_X"/>
<define name="REVERSE" value="TRUE"/>
</section>
<command_laws>
<set servo="FR" value="autopilot_get_motors_on() ? actuators_pprz[0] : -MAX_PPRZ"/>
<set servo="BR" value="autopilot_get_motors_on() ? actuators_pprz[1] : -MAX_PPRZ"/>
<set servo="BL" value="autopilot_get_motors_on() ? actuators_pprz[2] : -MAX_PPRZ"/>
<set servo="FL" value="autopilot_get_motors_on() ? actuators_pprz[3] : -MAX_PPRZ"/>
</command_laws>
<section name="IMU" prefix="IMU_">
<define name="ACCEL_CALIB" value="{{.abi_id=24, .calibrated={.neutral=true, .scale=true, .rotation=true},.neutral={-10,-47,-130}, .scale={{36821,8142,5741},{60003,13319,9358}}, TAWAKIV2_IMU_ROT}}"/>
<define name="GYRO_CALIB" value="{{.abi_id=24, .calibrated={.neutral=false, .scale=false, .rotation=true}, TAWAKIV2_IMU_ROT}}"/>
<define name="MAG_CALIB" value="{{.abi_id=3, .calibrated={.neutral=true, .scale=true, .rotation=true},.neutral={791,-190,2545}, .scale={{26437,35997,25098},{35181,44272,29767}}, TAWAKIV2_MAG_ROT}}"/>
<define name="BODY_TO_IMU_PHI" value="0." unit="deg"/>
<define name="BODY_TO_IMU_THETA" value="0." unit="deg"/>
<define name="BODY_TO_IMU_PSI" value="180." unit="deg"/>
</section>
<include href="conf/mag/toulouse_muret.xml"/>
<section name="STABILIZATION_ATTITUDE" prefix="STABILIZATION_ATTITUDE_">
<!-- setpoint limits for attitude stabilization rc flight -->
<define name="SP_MAX_PHI" value="45" unit="deg"/>
<define name="SP_MAX_THETA" value="45" unit="deg"/>
<define name="SP_MAX_R" value="60" unit="deg/s"/>
<define name="DEADBAND_A" value="0"/>
<define name="DEADBAND_E" value="0"/>
<define name="DEADBAND_R" value="50"/>
</section>
<section name="STABILIZATION_ATTITUDE_INDI" prefix="STABILIZATION_INDI_">
<define name="NUM_ACT" value="4"/>
<!-- reference acceleration for attitude control -->
<define name="REF_ERR_P" value="120"/>
<define name="REF_ERR_Q" value="130"/>
<define name="REF_ERR_R" value="120"/>
<define name="REF_RATE_P" value="15"/>
<define name="REF_RATE_Q" value="15"/>
<define name="REF_RATE_R" value="10"/>
<define name="MAX_R" value="60" unit="deg/s"/>
<!-- second order filter parameters -->
<define name="FILT_CUTOFF" value="4.0"/>
<define name="FILT_CUTOFF_R" value="4.0"/>
<!-- Adaptive Learning Rate -->
<define name="USE_ADAPTIVE" value="FALSE"/>
<define name="ADAPTIVE_MU" value="0.0001"/>
<!-- Full INDI -->
<!-- control effectiveness -->
<define name="G1_ROLL" value="{ -20.0, -20.0, 20.0, 20.0 }"/>
<define name="G1_PITCH" value="{ 20.0, -20.0, -20.0, 20.0 }"/>
<define name="G1_YAW" value="{ 3, -3, 3, -3 }"/>
<define name="G1_THRUST" value="{ -1., -1., -1., -1.}"/>
<!--Counter torque effect of spinning up a rotor-->
<define name="G2" value="{80, -80, 80, -80.0 }"/>
<!-- first order actuator dynamics -->
<define name="ACT_FREQ" value="{10.10, 10.10, 10.10, 10.10}"/>
<define name="ESTIMATION_FILT_CUTOFF" value="4.0"/>
<!--Priority for each axis (roll, pitch, yaw and thrust)-->
<define name="WLS_PRIORITIES" value="{1000, 1000, 1, 100}"/>
</section>
<section name="GUIDANCE_V" prefix="GUIDANCE_V_">
<define name="REF_MIN_ZDD" value="-0.4*9.81"/>
<define name="REF_MAX_ZDD" value=" 0.4*9.81"/>
<define name="REF_MIN_ZD" value="-2."/>
<define name="REF_MAX_ZD" value=" 2."/>
<define name="HOVER_KP" value="90"/>
<define name="HOVER_KD" value="110"/>
<define name="HOVER_KI" value="10"/>
<define name="NOMINAL_HOVER_THROTTLE" value="0.35"/>
<define name="ADAPT_THROTTLE_ENABLED" value="TRUE"/>
<define name="ADAPT_NOISE_FACTOR" value="1."/>
<define name="ADAPT_INITIAL_HOVER_THROTTLE" value="0.3"/>
</section>
<section name="GUIDANCE_H" prefix="GUIDANCE_H_">
<define name="MAX_BANK" value="30" unit="deg"/>
<define name="PGAIN" value="41"/>
<define name="DGAIN" value="108"/>
<define name="IGAIN" value="20"/>
<define name="NGAIN" value="0"/>
<!-- feedforward -->
<define name="AGAIN" value="0"/>
<define name="REF_MAX_SPEED" value="0.5"/>
<define name="REF_MAX_ACCEL" value="2."/>
</section>
<section name="GUIDANCE_INDI" prefix="GUIDANCE_INDI_">
<define name="SPECIFIC_FORCE_GAIN" value="-500.0"/>
<define name="THRUST_DYNAMICS_FREQ" value="25.64"/>
<define name="RC_DEBUG" value="FALSE"/>
<define name="SPEED_GAINZ" value="2.5"/>
</section>
<section name="NAV">
<define name="ARRIVED_AT_WAYPOINT" value="0.25"/>
<define name="NAV_CLIMB_VSPEED" value="0.8"/>
<define name="NAV_DESCEND_VSPEED" value="-0.5"/>
<define name="NAV_CARROT_DIST" value="18"/>
</section>
<section name="BAT">
<define name="CRITIC_BAT_LEVEL" value="9.3" unit="V"/>
</section>
<section name="AUTOPILOT">
<define name="MODE_STARTUP" value="AP_MODE_NAV"/>
<define name="MODE_MANUAL" value="AP_MODE_ATTITUDE_DIRECT"/>
<define name="MODE_AUTO1" value="AP_MODE_ATTITUDE_Z_HOLD"/>
<define name="MODE_AUTO2" value="AP_MODE_NAV"/>
<define name="FAILSAFE_FIXED_THROTTLE" value="0.4"/>
</section>
<section name="TAG_TRACKING" prefix="TAG_TRACKING_">
<define name="BODY_TO_CAM_PSI" value="M_PI_2"/>
<define name="CAM_POS_X" value="0.15"/>
</section>
<section name="GCS">
<define name="ALT_SHIFT_PLUS_PLUS" value="3"/>
<define name="ALT_SHIFT_PLUS" value="1"/>
<define name="ALT_SHIFT_MINUS" value="-0.5"/>
</section>
<section name="SIMULATOR" prefix="NPS_">
<define name="ACTUATOR_NAMES" value="nw_motor, ne_motor, se_motor, sw_motor" type="string[]"/>
<define name="JSBSIM_MODEL" value="simple_x_quad_ccw" type="string"/>
</section>
</airframe>
conf/boards/matek_h743_slim.makefile
+1 -1
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@@ -34,7 +34,7 @@ PROJECT = $(TARGET)
# Project specific files and paths (see Makefile.chibios for details) # Project specific files and paths (see Makefile.chibios for details)
CHIBIOS_BOARD_PLATFORM = STM32H7xx/platform.mk CHIBIOS_BOARD_PLATFORM = STM32H7xx/platform.mk
CHIBIOS_LINKER_DIR = $(PAPARAZZI_SRC)/sw/airborne/arch/chibios/ CHIBIOS_LINKER_DIR = $(PAPARAZZI_SRC)/sw/airborne/arch/chibios/
CHIBIOS_BOARD_LINKER = STM32H743xI_no_bl.ld CHIBIOS_BOARD_LINKER = STM32H743xI_nobl_nc.ld
CHIBIOS_BOARD_STARTUP = startup_stm32h7xx.mk CHIBIOS_BOARD_STARTUP = startup_stm32h7xx.mk
############################################################################## ##############################################################################
conf/boards/tawaki_2.0.makefile
+101
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@@ -0,0 +1,101 @@
# Hey Emacs, this is a -*- makefile -*-
#
# tawaki_common.makefile
#
# based on STM32H7
# only compatible with ChibiOS
#
BOARD=tawaki
BOARD_VERSION=2.0
BOARD_DIR=$(BOARD)/chibios/v$(BOARD_VERSION)
BOARD_CFG=\"boards/$(BOARD_DIR)/$(BOARD)_v$(BOARD_VERSION).h\"
ARCH=chibios
$(TARGET).ARCHDIR = $(ARCH)
RTOS=chibios
MCU=cortex-m7
## FPU on F7
USE_FPU=softfp
USE_FPU_OPT= -mfpu=fpv5-d16
USE_LTO ?= yes
$(TARGET).CFLAGS += -DPPRZLINK_ENABLE_FD -DDSHOT_CHANNEL_FIRST_INDEX=1U
##############################################################################
# Architecture or project specific options
#
# Define project name here (target)
PROJECT = $(TARGET)
CHIBIOS_LINKER_DIR = $(PAPARAZZI_SRC)/sw/airborne/arch/chibios/
# Project specific files and paths (see Makefile.chibios for details)
CHIBIOS_BOARD_PLATFORM = STM32H7xx/platform.mk
CHIBIOS_BOARD_LINKER = STM32H743xI_nobl_nc.ld
CHIBIOS_BOARD_STARTUP = startup_stm32h7xx.mk
# ITCM flash is a special flash that allow faster operations
# At the moment it is not possible to flash the code in this mode using dfu-util
# but it should work with the BlackMagicProbe or STLINK
# By default, normal flash is used
ifeq ($(USE_ITCM),1)
$(TARGET).CFLAGS += -DUSE_ITCM=1
DFU_ADDR = 0x00200000
else
$(TARGET).CFLAGS += -DUSE_ITCM=0
DFU_ADDR = 0x08000000
endif
##############################################################################
# Compiler settings
#
# default flash mode is via usb dfu bootloader
# possibilities: DFU-UTIL, SWD, STLINK
FLASH_MODE ?= DFU-UTIL
HAS_LUFTBOOT = FALSE
#
# default LED configuration
#
RADIO_CONTROL_LED ?= 4
BARO_LED ?= none
AHRS_ALIGNER_LED ?= 2
GPS_LED ?= 3
SYS_TIME_LED ?= 1
#
# default UART configuration (modem, gps, spektrum)
#
MODEM_PORT ?= UART2
MODEM_BAUD ?= B57600
GPS_PORT ?= UART7
GPS_BAUD ?= B57600
RADIO_CONTROL_SPEKTRUM_PRIMARY_PORT ?= UART6
RADIO_CONTROL_SPEKTRUM_SECONDARY_PORT ?= UART8
# single mode
SBUS_PORT ?= UART8
# dual mode
SBUS1_PORT ?= UART8
SBUS2_PORT ?= UART6
#
# default actuator configuration
#
# you can use different actuators by adding a configure option to your firmware section
# e.g. <configure name="ACTUATORS" value="actuators_ppm/>
# and by setting the correct "driver" attribute in servo section
# e.g. <servo driver="Ppm">
#
ACTUATORS ?= actuators_pwm
conf/modules/board_tawaki_2.0.xml
+27
View File
@@ -0,0 +1,27 @@
<!DOCTYPE module SYSTEM "module.dtd">
<module name="board_tawaki_2.0" dir="boards">
<doc>
<description>
Autoload several onboard sensors for the Tawaki board with proper configuration
- IMU (ICM42688)
- Baro (BMP390)
- Mag (LIS3MDL)
Normal front of the board is on USB connector side
Normal up of the board is on the Molex connector side
</description>
</doc>
<dep>
<depends>baro_bmp3,mag_lis3mdl,imu_icm42688</depends>
</dep>
<makefile target="!sim|nps|fbw">
<configure name="IMU_SPI_DEV" value="spi6" case="upper|lower"/>
<configure name="IMU_SPI_SLAVE_IDX" value="SPI_SLAVE5"/>
<configure name="BMP3_I2C_DEV" value="i2c4" case="upper|lower"/>
<define name="BMP3_SLAVE_ADDR" value="BMP3_I2C_ADDR_ALT"/>
<define name="TAWAKIV2_IMU_ROT" value=".body_to_sensor={{0,-16383,0,16383,0,0,0,0,16382}}"/>
<define name="TAWAKIV2_MAG_ROT" value=".body_to_sensor={{2,16382,0,-16382,2,0,0,0,16382}}"/>
<configure name="MAG_LIS3MDL_I2C_DEV" default="i2c4" case="upper|lower"/>
<define name="MODULE_LIS3MDL_UPDATE_AHRS"/>
</makefile>
</module>
conf/modules/boards/tawaki_2.0.xml
+14
View File
@@ -0,0 +1,14 @@
<!DOCTYPE module SYSTEM "../module.dtd">
<module name="tawaki_2.0" dir="boards">
<doc>
<description>
Specific configuration for Tawaki 2.0
</description>
</doc>
<dep>
<depends>hard_fault_recovery</depends>
</dep>
<makefile target="!sim|nps|fbw"/>
</module>
sw/airborne/arch/chibios/STM32H743xI.ld
+71 -10
View File
@@ -35,11 +35,12 @@ MEMORY
flash5 (rx) : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x24000000, len = 64k /* AXI SRAM no-cache*/ ram0nc (wx) : org = 0x24000000, len = 128k /* AXI SRAM NON CACHED */
ram1 (wx) : org = 0x24010000, len = 448k /* AXI SRAM cached */ ram0 (wx) : org = 0x24020000, len = 384k /* AXI SRAM */
ram1 (wx) : org = 0x30000000, len = 256k /* AHB SRAM1+SRAM2 */
ram2 (wx) : org = 0x30000000, len = 288k /* AHB SRAM1+SRAM2+SRAM3 */ ram2 (wx) : org = 0x30000000, len = 288k /* AHB SRAM1+SRAM2+SRAM3 */
ram3 (wx) : org = 0x30040000, len = 32k /* AHB SRAM3 */ ram3 (wx) : org = 0x30040000, len = 32k /* AHB SRAM3 NON CACHED*/
ram4 (wx) : org = 0x38000000, len = 64k /* AHB SRAM4 */ ram4 (wx) : org = 0x38000000, len = 64k /* AHB SRAM4 NON CACHED*/
ram5 (wx) : org = 0x20000000, len = 128k /* DTCM-RAM */ ram5 (wx) : org = 0x20000000, len = 128k /* DTCM-RAM */
ram6 (wx) : org = 0x00000000, len = 64k /* ITCM-RAM */ ram6 (wx) : org = 0x00000000, len = 64k /* ITCM-RAM */
ram7 (wx) : org = 0x38800000, len = 4k /* BCKP SRAM */ ram7 (wx) : org = 0x38800000, len = 4k /* BCKP SRAM */
@@ -80,14 +81,14 @@ REGION_ALIAS("MAIN_STACK_RAM", ram5);
REGION_ALIAS("PROCESS_STACK_RAM", ram5); REGION_ALIAS("PROCESS_STACK_RAM", ram5);
/* RAM region to be used for data segment.*/ /* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram1); REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0); REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/ /* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram1); REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/ /* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram1); REGION_ALIAS("HEAP_RAM", ram0);
/* Stack rules inclusion.*/ /* Stack rules inclusion.*/
INCLUDE rules_stacks.ld INCLUDE rules_stacks.ld
@@ -97,8 +98,15 @@ INCLUDE rules_stacks.ld
/* SRAM3 is assumed to be marked non-cacheable using MPU. */ /* SRAM3 is assumed to be marked non-cacheable using MPU. */
/*===========================================================================*/ /*===========================================================================*/
/* RAM region to be used for nocache segment.*/ /* RAM region to be used for ram0nc (SDMMC1) nocache segment.*/
REGION_ALIAS("NOCACHE_RAM", ram0); /* named nocache because SDIO driver is hardwired to declare buffer nocache */
REGION_ALIAS("NOCACHE_RAM", ram0nc);
/* RAM region to be used for ram3 nocache segment.*/
REGION_ALIAS("NOCACHE3_RAM", ram3);
/* RAM region to be used for ram4 (BDMA) nocache segment.*/
REGION_ALIAS("NOCACHE4_RAM", ram4);
/* RAM region to be used for eth segment.*/ /* RAM region to be used for eth segment.*/
REGION_ALIAS("ETH_RAM", ram3); REGION_ALIAS("ETH_RAM", ram3);
@@ -114,7 +122,29 @@ SECTIONS
*(.bss.__nocache_*) *(.bss.__nocache_*)
. = ALIGN(4); . = ALIGN(4);
__nocache_end__ = .; __nocache_end__ = .;
} > NOCACHE_RAM } > NOCACHE_RAM
/* Special section for non cache-able areas.*/
.nocache3 (NOLOAD) : ALIGN(4)
{
__nocache3_base__ = .;
*(.nocache3)
*(.nocache3.*)
*(.bss.__nocache3_*)
. = ALIGN(4);
__nocache3_end__ = .;
} > NOCACHE3_RAM
/* Special section for non cache4-able areas.*/
.nocache4 (NOLOAD) : ALIGN(4)
{
__nocache4_base__ = .;
*(.nocache4)
*(.nocache4.*)
*(.bss.__nocache4_*)
. = ALIGN(4);
__nocache4_end__ = .;
} > NOCACHE4_RAM
/* Special section for Ethernet DMA non cache-able areas.*/ /* Special section for Ethernet DMA non cache-able areas.*/
.eth (NOLOAD) : ALIGN(4) .eth (NOLOAD) : ALIGN(4)
@@ -134,6 +164,37 @@ INCLUDE rules_code.ld
/* Data rules inclusion.*/ /* Data rules inclusion.*/
INCLUDE rules_data.ld INCLUDE rules_data.ld
/* Custom memory rules.*/
__ram0nc_base__ = ORIGIN(ram0nc);
__ram0nc_size__ = LENGTH(ram0nc);
__ram0nc_end__ = __ram0nc_base__ + __ram0nc_size__;
SECTIONS
{
.ram0nc_init : ALIGN(4)
{
__ram0nc_init_text__ = LOADADDR(.ram0nc_init);
__ram0nc_init__ = .;
KEEP(*(.ram0nc_init))
KEEP(*(.ram0nc_init.*))
. = ALIGN(4);
} > ram0nc AT > RAM_INIT_FLASH_LMA
.ram0nc (NOLOAD) : ALIGN(4)
{
__ram0nc_clear__ = .;
*(.ram0nc_clear)
*(.ram0nc_clear.*)
. = ALIGN(4);
__ram0nc_noinit__ = .;
*(.ram0nc)
*(.ram0nc.*)
. = ALIGN(4);
__ram0nc_free__ = .;
} > ram0nc
}
/* Memory rules inclusion.*/ /* Memory rules inclusion.*/
INCLUDE rules_memory.ld INCLUDE rules_memory.ld
sw/airborne/arch/chibios/STM32H743xI_no_bl.ld → sw/airborne/arch/chibios/STM32H743xI_nobl_nc.ld
Regular → Executable
+200 -139
View File
@@ -1,139 +1,200 @@
/* /*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License"); Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License. you may not use this file except in compliance with the License.
You may obtain a copy of the License at You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0 http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS, distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and See the License for the specific language governing permissions and
limitations under the License. limitations under the License.
*/ */
/* /*
* STM32H743xI generic setup. * STM32H743xI generic setup.
* *
* AXI SRAM - BSS, Data, Heap. * AXI SRAM - BSS, Data, Heap.
* SRAM1+SRAM2 - None. * SRAM1+SRAM2 - None.
* SRAM3 - NOCACHE, ETH. * SRAM3 - NOCACHE, ETH.
* SRAM4 - None. * SRAM4 - None.
* DTCM-RAM - Main Stack, Process Stack. * DTCM-RAM - Main Stack, Process Stack.
* ITCM-RAM - None. * ITCM-RAM - None.
* BCKP SRAM - None. * BCKP SRAM - None.
*/ */
MEMORY MEMORY
{ {
flash0 (rx) : org = 0x08000000, len = 2M /* Flash bank1+bank2 */ flash0 (rx) : org = 0x08000000, len = 2M /* Flash bank1+bank2 */
flash1 (rx) : org = 0x08000000, len = 1M /* Flash bank 1 */ flash1 (rx) : org = 0x08000000, len = 1M /* Flash bank 1 */
flash2 (rx) : org = 0x08100000, len = 1M /* Flash bank 2 */ flash2 (rx) : org = 0x08100000, len = 1M /* Flash bank 2 */
flash3 (rx) : org = 0x00000000, len = 0 flash3 (rx) : org = 0x00000000, len = 0
flash4 (rx) : org = 0x00000000, len = 0 flash4 (rx) : org = 0x00000000, len = 0
flash5 (rx) : org = 0x00000000, len = 0 flash5 (rx) : org = 0x00000000, len = 0
flash6 (rx) : org = 0x00000000, len = 0 flash6 (rx) : org = 0x00000000, len = 0
flash7 (rx) : org = 0x00000000, len = 0 flash7 (rx) : org = 0x00000000, len = 0
ram0 (wx) : org = 0x24000000, len = 64k /* AXI SRAM no-cache*/ ram0nc (wx) : org = 0x24000000, len = 128k /* AXI SRAM NON CACHED */
ram1 (wx) : org = 0x24010000, len = 448k /* AXI SRAM cached */ ram0 (wx) : org = 0x24020000, len = 384k /* AXI SRAM */
ram2 (wx) : org = 0x30000000, len = 288k /* AHB SRAM1+SRAM2+SRAM3 */ ram1 (wx) : org = 0x30000000, len = 256k /* AHB SRAM1+SRAM2 */
ram3 (wx) : org = 0x30040000, len = 32k /* AHB SRAM3 */ ram2 (wx) : org = 0x30000000, len = 288k /* AHB SRAM1+SRAM2+SRAM3 */
ram4 (wx) : org = 0x38000000, len = 64k /* AHB SRAM4 */ ram3 (wx) : org = 0x30040000, len = 32k /* AHB SRAM3 NON CACHED*/
ram5 (wx) : org = 0x20000000, len = 128k /* DTCM-RAM */ ram4 (wx) : org = 0x38000000, len = 64k /* AHB SRAM4 NON CACHED*/
ram6 (wx) : org = 0x00000000, len = 64k /* ITCM-RAM */ ram5 (wx) : org = 0x20000000, len = 128k /* DTCM-RAM */
ram7 (wx) : org = 0x38800000, len = 4k /* BCKP SRAM */ ram6 (wx) : org = 0x00000000, len = 64k /* ITCM-RAM */
} ram7 (wx) : org = 0x38800000, len = 4k /* BCKP SRAM */
}
/* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/ /* For each data/text section two region are defined, a virtual region
and a load region (_LMA suffix).*/
/* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH", flash0); /* Flash region to be used for exception vectors.*/
REGION_ALIAS("VECTORS_FLASH_LMA", flash0); REGION_ALIAS("VECTORS_FLASH", flash0);
REGION_ALIAS("VECTORS_FLASH_LMA", flash0);
/* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH", flash0); /* Flash region to be used for constructors and destructors.*/
REGION_ALIAS("XTORS_FLASH_LMA", flash0); REGION_ALIAS("XTORS_FLASH", flash0);
REGION_ALIAS("XTORS_FLASH_LMA", flash0);
/* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH", flash0); /* Flash region to be used for code text.*/
REGION_ALIAS("TEXT_FLASH_LMA", flash0); REGION_ALIAS("TEXT_FLASH", flash0);
REGION_ALIAS("TEXT_FLASH_LMA", flash0);
/* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH", flash0); /* Flash region to be used for read only data.*/
REGION_ALIAS("RODATA_FLASH_LMA", flash0); REGION_ALIAS("RODATA_FLASH", flash0);
REGION_ALIAS("RODATA_FLASH_LMA", flash0);
/* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH", flash0); /* Flash region to be used for various.*/
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0); REGION_ALIAS("VARIOUS_FLASH", flash0);
REGION_ALIAS("VARIOUS_FLASH_LMA", flash0);
/* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0); /* Flash region to be used for RAM(n) initialization data.*/
REGION_ALIAS("RAM_INIT_FLASH_LMA", flash0);
/* RAM region to be used for Main stack. This stack accommodates the processing
of all exceptions and interrupts.*/ /* RAM region to be used for Main stack. This stack accommodates the processing
REGION_ALIAS("MAIN_STACK_RAM", ram5); of all exceptions and interrupts.*/
REGION_ALIAS("MAIN_STACK_RAM", ram5);
/* RAM region to be used for the process stack. This is the stack used by
the main() function.*/ /* RAM region to be used for the process stack. This is the stack used by
REGION_ALIAS("PROCESS_STACK_RAM", ram5); the main() function.*/
REGION_ALIAS("PROCESS_STACK_RAM", ram5);
/* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM", ram1); /* RAM region to be used for data segment.*/
REGION_ALIAS("DATA_RAM_LMA", flash0); REGION_ALIAS("DATA_RAM", ram0);
REGION_ALIAS("DATA_RAM_LMA", flash0);
/* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram1); /* RAM region to be used for BSS segment.*/
REGION_ALIAS("BSS_RAM", ram0);
/* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram1); /* RAM region to be used for the default heap.*/
REGION_ALIAS("HEAP_RAM", ram0);
/* Stack rules inclusion.*/
INCLUDE rules_stacks.ld /* Stack rules inclusion.*/
INCLUDE rules_stacks.ld
/*===========================================================================*/
/* Custom sections for STM32H7xx. */ /*===========================================================================*/
/* SRAM3 is assumed to be marked non-cacheable using MPU. */ /* Custom sections for STM32H7xx. */
/*===========================================================================*/ /* SRAM3 is assumed to be marked non-cacheable using MPU. */
/*===========================================================================*/
/* RAM region to be used for nocache segment.*/
REGION_ALIAS("NOCACHE_RAM", ram0); /* RAM region to be used for ram0nc (SDMMC1) nocache segment.*/
/* named nocache because SDIO driver is hardwired to declare buffer nocache */
/* RAM region to be used for eth segment.*/ REGION_ALIAS("NOCACHE_RAM", ram0nc);
REGION_ALIAS("ETH_RAM", ram3);
/* RAM region to be used for ram3 nocache segment.*/
SECTIONS REGION_ALIAS("NOCACHE3_RAM", ram3);
{
/* Special section for non cache-able areas.*/ /* RAM region to be used for ram4 (BDMA) nocache segment.*/
.nocache (NOLOAD) : ALIGN(4) REGION_ALIAS("NOCACHE4_RAM", ram4);
{
__nocache_base__ = .; /* RAM region to be used for eth segment.*/
*(.nocache) REGION_ALIAS("ETH_RAM", ram3);
*(.nocache.*)
*(.bss.__nocache_*) SECTIONS
. = ALIGN(4); {
__nocache_end__ = .; /* Special section for non cache-able areas.*/
} > NOCACHE_RAM .nocache (NOLOAD) : ALIGN(4)
{
/* Special section for Ethernet DMA non cache-able areas.*/ __nocache_base__ = .;
.eth (NOLOAD) : ALIGN(4) *(.nocache)
{ *(.nocache.*)
__eth_base__ = .; *(.bss.__nocache_*)
*(.eth) . = ALIGN(4);
*(.eth.*) __nocache_end__ = .;
*(.bss.__eth_*) } > NOCACHE_RAM
. = ALIGN(4);
__eth_end__ = .; /* Special section for non cache-able areas.*/
} > ETH_RAM .nocache3 (NOLOAD) : ALIGN(4)
} {
__nocache3_base__ = .;
/* Code rules inclusion.*/ *(.nocache3)
INCLUDE rules_code.ld *(.nocache3.*)
*(.bss.__nocache3_*)
/* Data rules inclusion.*/ . = ALIGN(4);
INCLUDE rules_data.ld __nocache3_end__ = .;
} > NOCACHE3_RAM
/* Memory rules inclusion.*/
INCLUDE rules_memory.ld /* Special section for non cache4-able areas.*/
.nocache4 (NOLOAD) : ALIGN(4)
{
__nocache4_base__ = .;
*(.nocache4)
*(.nocache4.*)
*(.bss.__nocache4_*)
. = ALIGN(4);
__nocache4_end__ = .;
} > NOCACHE4_RAM
/* Special section for Ethernet DMA non cache-able areas.*/
.eth (NOLOAD) : ALIGN(4)
{
__eth_base__ = .;
*(.eth)
*(.eth.*)
*(.bss.__eth_*)
. = ALIGN(4);
__eth_end__ = .;
} > ETH_RAM
}
/* Code rules inclusion.*/
INCLUDE rules_code.ld
/* Data rules inclusion.*/
INCLUDE rules_data.ld
/* Custom memory rules.*/
__ram0nc_base__ = ORIGIN(ram0nc);
__ram0nc_size__ = LENGTH(ram0nc);
__ram0nc_end__ = __ram0nc_base__ + __ram0nc_size__;
SECTIONS
{
.ram0nc_init : ALIGN(4)
{
__ram0nc_init_text__ = LOADADDR(.ram0nc_init);
__ram0nc_init__ = .;
KEEP(*(.ram0nc_init))
KEEP(*(.ram0nc_init.*))
. = ALIGN(4);
} > ram0nc AT > RAM_INIT_FLASH_LMA
.ram0nc (NOLOAD) : ALIGN(4)
{
__ram0nc_clear__ = .;
*(.ram0nc_clear)
*(.ram0nc_clear.*)
. = ALIGN(4);
__ram0nc_noinit__ = .;
*(.ram0nc)
*(.ram0nc.*)
. = ALIGN(4);
__ram0nc_free__ = .;
} > ram0nc
}
/* Memory rules inclusion.*/
INCLUDE rules_memory.ld
sw/airborne/arch/chibios/mcu_arch.c
+148 -11
View File
@@ -39,11 +39,29 @@
/* Paparazzi includes */ /* Paparazzi includes */
#include "mcu.h" #include "mcu.h"
#include "mcu_periph/ram_arch.h"
#if defined(STM32H7XX)
typedef struct {
uint32_t *init_text_area;
uint32_t *init_area;
uint32_t *clear_area;
uint32_t *no_init_area;
} ram_init_area_t;
static void initRam0nc(void);
static void init_ram_areas(const ram_init_area_t *rap);
static void mpuConfigureNonCachedRam(void);
#endif
#if USE_HARD_FAULT_RECOVERY #if USE_HARD_FAULT_RECOVERY
#if defined(STM32F4XX) || defined (STM32F7XX) #if defined(STM32F4XX) || defined (STM32F7XX)
#define BCKP_SECTION ".ram5" #define BCKP_SECTION ".ram5"
#define IN_BCKP_SECTION(var) var __attribute__ ((section(BCKP_SECTION), aligned(8))) #define IN_BCKP_SECTION(var) var __attribute__ ((section(BCKP_SECTION), aligned(8)))
#elif defined(STM32H7XX)
#define BCKP_SECTION ".ram7"
#define IN_BCKP_SECTION(var) var __attribute__ ((section(BCKP_SECTION), aligned(8)))
#else #else
#error "No backup ram available" #error "No backup ram available"
#endif #endif
@@ -88,13 +106,26 @@ bool recovering_from_hard_fault;
// select correct register // select correct register
#if defined(STM32F4XX) #if defined(STM32F4XX)
#define __PWR_CSR PWR->CSR #define __PWR_BACKUP_REG PWR->CSR
#define __PWR_CSR_BRE PWR_CSR_BRE #define __PWR_BACKUP_ENABLE PWR_CSR_BRE
#define __PWR_CSR_BRR PWR_CSR_BRR #define __PWR_BACKUP_READY PWR_CSR_BRR
#define __RCC_RESET_REGISTER RCC->CSR
#define __RCC_RESET_FLAG RCC_CSR_SFTRSTF
#define __RCC_RESET_REMOVE_FLAG RCC_CSR_RMVF
#elif defined(STM32F7XX) #elif defined(STM32F7XX)
#define __PWR_CSR PWR->CSR1 #define __PWR_BACKUP_REG PWR->CSR1
#define __PWR_CSR_BRE PWR_CSR1_BRE #define __PWR_BACKUP_ENABLE PWR_CSR1_BRE
#define __PWR_CSR_BRR PWR_CSR1_BRR #define __PWR_BACKUP_READY PWR_CSR1_BRR
#define __RCC_RESET_REGISTER RCC->CSR
#define __RCC_RESET_FLAG RCC_CSR_SFTRSTF
#define __RCC_RESET_REMOVE_FLAG RCC_CSR_RMVF
#elif defined(STM32H7XX)
#define __PWR_BACKUP_REG PWR->CR2
#define __PWR_BACKUP_ENABLE PWR_CR2_BREN
#define __PWR_BACKUP_READY PWR_CR2_BRRDY
#define __RCC_RESET_REGISTER RCC->RSR
#define __RCC_RESET_FLAG RCC_RSR_SFTRSTF
#define __RCC_RESET_REMOVE_FLAG RCC_RSR_RMVF
#else #else
#error Hard fault recovery not supported #error Hard fault recovery not supported
#endif #endif
@@ -133,20 +164,24 @@ void mcu_arch_init(void)
halInit(); halInit();
chSysInit(); chSysInit();
#if defined(STM32H7XX)
mpuConfigureNonCachedRam();
#endif
#if USE_HARD_FAULT_RECOVERY #if USE_HARD_FAULT_RECOVERY
/* Backup domain SRAM enable, and with it, the regulator */ /* Backup domain SRAM enable, and with it, the regulator */
#if defined(STM32F4XX) || defined(STM32F7XX) #if defined(STM32F4XX) || defined(STM32F7XX)
RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN; RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN;
__PWR_CSR |= __PWR_CSR_BRE; __PWR_BACKUP_REG |= __PWR_BACKUP_ENABLE;
while ((__PWR_CSR & __PWR_CSR_BRR) == 0) ; /* Waits until the regulator is stable */ while ((__PWR_BACKUP_REG & __PWR_BACKUP_READY) == 0) ; /* Waits until the regulator is stable */
#endif /* STM32F4 | STM32F7 */ #endif /* STM32F4 | STM32F7 */
// test if last reset was a 'real' hard fault // test if last reset was a 'real' hard fault
recovering_from_hard_fault = false; recovering_from_hard_fault = false;
if (!(RCC->CSR & RCC_CSR_SFTRSTF)) { if (!(__RCC_RESET_REGISTER & __RCC_RESET_FLAG)) {
// not coming from soft reset // not coming from soft reset
hard_fault = false; hard_fault = false;
} else if ((RCC->CSR & RCC_CSR_SFTRSTF) && !hard_fault) { } else if ((__RCC_RESET_REGISTER & __RCC_RESET_FLAG) && !hard_fault) {
// this is a soft reset, probably from a debug probe, so let's start in normal mode // this is a soft reset, probably from a debug probe, so let's start in normal mode
hard_fault = false; hard_fault = false;
} else { } else {
@@ -155,7 +190,7 @@ void mcu_arch_init(void)
hard_fault = false; hard_fault = false;
} }
// *MANDATORY* clear of rcc bits // *MANDATORY* clear of rcc bits
RCC->CSR = RCC_CSR_RMVF; __RCC_RESET_REGISTER = __RCC_RESET_REMOVE_FLAG;
// end of reset bit probing // end of reset bit probing
#endif /* USE_HARD_FAULT_RECOVERY */ #endif /* USE_HARD_FAULT_RECOVERY */
} }
@@ -278,3 +313,105 @@ static void mcu_set_rtcbackup(uint32_t val) {
#endif #endif
} }
#endif /* USE_RTC_BACKUP */ #endif /* USE_RTC_BACKUP */
#if defined(STM32H7XX)
/*
nocache regions are
° ram0nc for sdmmc1
° ram3 for miscellanous ?
° ram4 for bdma attached peripherals (i2c4, spi6, adc3)
*/
extern const uint32_t __ram0nc_base__;
extern const uint32_t __ram0nc_size__;
extern const uint32_t __ram3_base__;
extern const uint32_t __ram3_size__;
extern const uint32_t __ram4_base__;
extern const uint32_t __ram4_size__;
static uint32_t getMPU_RASR_SIZE(const uint32_t ldSize)
{
// 2^n -> n-1
chDbgAssert(__builtin_popcount(ldSize) == 1U, "MPU region size must be 2^n");
chDbgAssert(ldSize >= 32U, "MPU region size must be >= 32");
return MPU_RASR_SIZE(__builtin_ctz(ldSize) - 1U);
}
static void mpuConfigureNonCachedRam(void)
{
const uint32_t mpuSharedOption = MPU_RASR_ATTR_AP_RW_RW |
MPU_RASR_ATTR_NON_CACHEABLE | MPU_RASR_ATTR_S |
MPU_RASR_ENABLE;
const uint32_t ram0nc_base = (uint32_t) &__ram0nc_base__;
const uint32_t ram3_base = (uint32_t) &__ram3_base__;
const uint32_t ram4_base = (uint32_t) &__ram4_base__;
const uint32_t ram0nc_size = (uint32_t) &__ram0nc_size__;
const uint32_t ram3_size = (uint32_t) &__ram3_size__;
const uint32_t ram4_size = (uint32_t) &__ram4_size__;
chDbgAssert(ram0nc_base == 0x24000000, "MPU ram0nc addr mismatch");
chDbgAssert(ram3_base == 0x30040000, "MPU ram3 addr mismatch");
chDbgAssert(ram4_base == 0x38000000, "MPU ram4 addr mismatch");
chDbgAssert((ram0nc_base % ram0nc_size) == 0, "MPU ram0nc base addr must be size aligned");
chDbgAssert(ram0nc_size == 128 * 1024, "MPU ram0nc size must be 128K");
chDbgAssert((ram3_base % ram3_size) == 0, "MPU ram3 base addr must be size aligned");
chDbgAssert((ram4_base % ram4_size) == 0, "MPU ram4 base addr must be size aligned");
chDbgAssert(getMPU_RASR_SIZE(ram0nc_size) == MPU_RASR_SIZE_128K, "getMPU_RASR_SIZE error");
mpuConfigureRegion(MPU_REGION_6,
ram0nc_base,
getMPU_RASR_SIZE(ram0nc_size) | mpuSharedOption
);
mpuConfigureRegion(MPU_REGION_5,
ram3_base,
getMPU_RASR_SIZE(ram3_size) | mpuSharedOption
);
mpuConfigureRegion(MPU_REGION_4,
ram4_base,
getMPU_RASR_SIZE(ram4_size) | mpuSharedOption
);
initRam0nc();
mpuEnable(MPU_CTRL_PRIVDEFENA);
__ISB();
__DSB();
SCB_CleanInvalidateDCache();
}
static void initRam0nc(void)
{
extern uint32_t __ram0nc_init_text__, __ram0nc_init__, __ram0nc_clear__, __ram0nc_noinit__;
static const ram_init_area_t ram_areas[1] = {
{&__ram0nc_init_text__, &__ram0nc_init__, &__ram0nc_clear__, &__ram0nc_noinit__},
};
init_ram_areas(ram_areas);
}
static void init_ram_areas(const ram_init_area_t *rap)
{
uint32_t *tp = rap->init_text_area;
uint32_t *p = rap->init_area;
/* Copying initialization data.*/
while (p < rap->clear_area) {
*p = *tp;
p++;
tp++;
}
/* Zeroing clear area.*/
while (p < rap->no_init_area) {
*p = 0;
p++;
}
}
#endif
sw/airborne/arch/chibios/mcu_periph/hal_stm32_dma.c
+9
View File
@@ -455,10 +455,12 @@ bool dma_lld_start(DMADriver *dmap)
#endif #endif
// portable way (V1, V2) to retreive controler number // portable way (V1, V2) to retreive controler number
#if STM32_DMA_SUPPORTS_DMAMUX == 0
#if STM32_DMA_ADVANCED #if STM32_DMA_ADVANCED
dmap->controller = 1 + (cfg->stream / STM32_DMA_STREAM_ID(2, 0)); dmap->controller = 1 + (cfg->stream / STM32_DMA_STREAM_ID(2, 0));
#else #else
dmap->controller = 1 + (cfg->stream / STM32_DMA_STREAM_ID(2, 1)); dmap->controller = 1 + (cfg->stream / STM32_DMA_STREAM_ID(2, 1));
#endif
#endif #endif
dmap->dmamode = STM32_DMA_CR_PL(cfg->dma_priority) | dmap->dmamode = STM32_DMA_CR_PL(cfg->dma_priority) |
@@ -470,7 +472,9 @@ bool dma_lld_start(DMADriver *dmap)
#if STM32_DMA_SUPPORTS_CSELR #if STM32_DMA_SUPPORTS_CSELR
| STM32_DMA_CR_CHSEL(cfg->request) | STM32_DMA_CR_CHSEL(cfg->request)
#elif STM32_DMA_ADVANCED #elif STM32_DMA_ADVANCED
#if STM32_DMA_SUPPORTS_DMAMUX == 0
| STM32_DMA_CR_CHSEL(cfg->channel) | STM32_DMA_CR_CHSEL(cfg->channel)
#endif
| (cfg->periph_inc_size_4 ? STM32_DMA_CR_PINCOS : 0UL) | | (cfg->periph_inc_size_4 ? STM32_DMA_CR_PINCOS : 0UL) |
(cfg->transfert_end_ctrl_by_periph ? STM32_DMA_CR_PFCTRL : 0UL) (cfg->transfert_end_ctrl_by_periph ? STM32_DMA_CR_PFCTRL : 0UL)
# endif # endif
@@ -631,10 +635,12 @@ bool dma_lld_start(DMADriver *dmap)
Only the DMA2 controller is able to perform memory-to-memory transfers. Only the DMA2 controller is able to perform memory-to-memory transfers.
*/ */
#if STM32_DMA_SUPPORTS_DMAMUX == 0
if (cfg->direction == DMA_DIR_M2M) { if (cfg->direction == DMA_DIR_M2M) {
osalDbgAssert(dmap->controller == 2, "M2M not available on DMA1"); osalDbgAssert(dmap->controller == 2, "M2M not available on DMA1");
osalDbgAssert(cfg->circular == false, "M2M not available in circular mode"); osalDbgAssert(cfg->circular == false, "M2M not available in circular mode");
} }
#endif
# endif # endif
@@ -704,6 +710,9 @@ bool dma_lld_start_transfert(DMADriver *dmap, volatile void *periphp, void *mem0
#endif #endif
dmap->size = size; dmap->size = size;
dmaStreamSetPeripheral(dmap->dmastream, periphp); dmaStreamSetPeripheral(dmap->dmastream, periphp);
#if STM32_DMA_SUPPORTS_DMAMUX
dmaSetRequestSource(dmap->dmastream, dmap->config->dmamux);
#endif
dmaStreamSetMemory0(dmap->dmastream, mem0p); dmaStreamSetMemory0(dmap->dmastream, mem0p);
dmaStreamSetTransactionSize(dmap->dmastream, size); dmaStreamSetTransactionSize(dmap->dmastream, size);
dmaStreamSetMode(dmap->dmastream, dmap->dmamode); dmaStreamSetMode(dmap->dmastream, dmap->dmamode);
sw/airborne/arch/chibios/mcu_periph/hal_stm32_dma.h
+7 -1
View File
@@ -245,6 +245,9 @@ typedef struct {
*/ */
uint32_t stream; uint32_t stream;
#if STM32_DMA_SUPPORTS_DMAMUX
uint8_t dmamux;
#else
#if STM32_DMA_SUPPORTS_CSELR #if STM32_DMA_SUPPORTS_CSELR
/** /**
* @brief DMA request or DMA channel * @brief DMA request or DMA channel
@@ -254,8 +257,9 @@ typedef struct {
uint8_t request; // STM terminology for dmaV1 uint8_t request; // STM terminology for dmaV1
uint8_t channel; // ChibiOS terminology for both dmaV1 and dmaV2 (portability) uint8_t channel; // ChibiOS terminology for both dmaV1 and dmaV2 (portability)
}; };
#elif STM32_DMA_ADVANCED #else
uint8_t channel; uint8_t channel;
#endif
#endif #endif
/** /**
@@ -444,7 +448,9 @@ struct DMADriver {
/** /**
* @brief controller associated with stream * @brief controller associated with stream
*/ */
#if STM32_DMA_SUPPORTS_DMAMUX == 0
uint8_t controller; uint8_t controller;
#endif
}; };
sw/airborne/arch/chibios/mcu_periph/i2c_arch.c
+6
View File
@@ -345,8 +345,14 @@ void i2c3_hw_init(void)
#if USE_I2C4 #if USE_I2C4
PRINT_CONFIG_VAR(I2C4_CLOCK_SPEED) PRINT_CONFIG_VAR(I2C4_CLOCK_SPEED)
#if defined(STM32H7XX)
// Local variables (in DMA safe memory)
static IN_BDMA_SECTION(struct i2c_init i2c4_init_s) = {
#else
// Local variables (in DMA safe memory) // Local variables (in DMA safe memory)
static IN_DMA_SECTION(struct i2c_init i2c4_init_s) = { static IN_DMA_SECTION(struct i2c_init i2c4_init_s) = {
#endif
.name = "i2c4", .name = "i2c4",
.sem = __SEMAPHORE_DATA(i2c4_init_s.sem, 0), .sem = __SEMAPHORE_DATA(i2c4_init_s.sem, 0),
.cfg = I2C4_CFG_DEF, .cfg = I2C4_CFG_DEF,
sw/airborne/arch/chibios/mcu_periph/ram_arch.h
+11 -1
View File
@@ -66,7 +66,9 @@
#elif defined(STM32H7XX) #elif defined(STM32H7XX)
#define STD_SECTION ".ram1" #define STD_SECTION ".ram1"
#define FAST_SECTION ".ram5" #define FAST_SECTION ".ram5"
#define DMA_SECTION ".ram0" #define DMA_SECTION ".ram0nc"
#define BDMA_SECTION ".ram4"
#define SDMMC_SECTION DMA_SECTION
#define DMA_ALIGN 32 #define DMA_ALIGN 32
#else #else
#error "section defined only for STM32F1, STM32F3, STM32F4, STM32F7 and STM32H7" #error "section defined only for STM32F1, STM32F3, STM32F4, STM32F7 and STM32H7"
@@ -84,5 +86,13 @@
#define IN_DMA_SECTION_CLEAR(var) var __attribute__ ((section(DMA_SECTION "_clear"), aligned(DMA_ALIGN))) #define IN_DMA_SECTION_CLEAR(var) var __attribute__ ((section(DMA_SECTION "_clear"), aligned(DMA_ALIGN)))
#define IN_DMA_SECTION(var) var __attribute__ ((section(DMA_SECTION "_init"), aligned(DMA_ALIGN))) #define IN_DMA_SECTION(var) var __attribute__ ((section(DMA_SECTION "_init"), aligned(DMA_ALIGN)))
#define IN_BDMA_SECTION_NOINIT(var) var __attribute__ ((section(BDMA_SECTION), aligned(DMA_ALIGN)))
#define IN_BDMA_SECTION_CLEAR(var) var __attribute__ ((section(BDMA_SECTION "_clear"), aligned(DMA_ALIGN)))
#define IN_BDMA_SECTION(var) var __attribute__ ((section(BDMA_SECTION "_init"), aligned(DMA_ALIGN)))
#define IN_SDMMC_SECTION_NOINIT(var) var __attribute__ ((section(SDMMC_SECTION), aligned(DMA_ALIGN)))
#define IN_SDMMC_SECTION_CLEAR(var) var __attribute__ ((section(SDMMC_SECTION "_clear"), aligned(DMA_ALIGN)))
#define IN_SDMMC_SECTION(var) var __attribute__ ((section(SDMMC_SECTION "_init"), aligned(DMA_ALIGN)))
#endif #endif
sw/airborne/arch/chibios/mcu_periph/spi_arch.c
+25
View File
@@ -487,6 +487,31 @@ void spi4_arch_init(void)
} }
#endif #endif
#if USE_SPI6
#if defined(STM32H7XX)
// Local variables (in DMA safe memory)
static IN_BDMA_SECTION(struct spi_init spi6_init_s) = {
#else
// Local variables (in DMA safe memory)
static IN_DMA_SECTION(struct spi_init spi6_init_s) = {
#endif
.name = "spi6",
.sem = __SEMAPHORE_DATA(spi6_init_s.sem, 0),
};
static THD_WORKING_AREA(wa_thd_spi6, SPI_THREAD_STACK_SIZE);
// Initialize the interface
void spi6_arch_init(void)
{
spi6.reg_addr = &SPID6;
spi6.init_struct = &spi6_init_s;
// Create thread
chThdCreateStatic(wa_thd_spi6, sizeof(wa_thd_spi6),
NORMALPRIO + 1, thd_spi, (void *)&spi6);
}
#endif
/** /**
* Submit SPI transaction * Submit SPI transaction
sw/airborne/arch/chibios/mcu_periph/sys_time_arch.h
+1
View File
@@ -35,6 +35,7 @@
#include "mcu_periph/sys_time.h" #include "mcu_periph/sys_time.h"
#include <ch.h> #include <ch.h>
#include <hal.h>
#if (defined STM32H7XX) && !(defined STM32_SYSCLK) #if (defined STM32H7XX) && !(defined STM32_SYSCLK)
#define STM32_SYSCLK STM32_SYS_CK #define STM32_SYSCLK STM32_SYS_CK
sw/airborne/arch/chibios/modules/actuators/esc_dshot.c
+25 -5
View File
@@ -31,6 +31,7 @@
#include <stdnoreturn.h> #include <stdnoreturn.h>
#include <math.h> #include <math.h>
#include <string.h> #include <string.h>
#include "mcu_periph/sys_time_arch.h"
/* /*
# _ __ _ _ _ _ # _ __ _ _ _ _
@@ -45,14 +46,14 @@
* Possible values are: 150, 300, 600 * Possible values are: 150, 300, 600
*/ */
#ifndef DSHOT_SPEED #ifndef DSHOT_SPEED
#define DSHOT_SPEED 300 #define DSHOT_SPEED 300U
#endif #endif
/** Baudrate of the serial link used for telemetry data /** Baudrate of the serial link used for telemetry data
* Can depend on the ESC, but only 115k have been used so far * Can depend on the ESC, but only 115k have been used so far
*/ */
#ifndef DSHOT_TELEMETRY_BAUD #ifndef DSHOT_TELEMETRY_BAUD
#define DSHOT_TELEMETRY_BAUD 115200 #define DSHOT_TELEMETRY_BAUD 115200U
#endif #endif
/** Telemetry timeout in ms /** Telemetry timeout in ms
@@ -61,8 +62,17 @@
#define DSHOT_TELEMETRY_TIMEOUT_MS 3 #define DSHOT_TELEMETRY_TIMEOUT_MS 3
#endif #endif
/** the timer will beat @84Mhz on STM32F4 // TODO check on F7 */
#define PWM_FREQ (STM32_SYSCLK/2000) #ifdef STM32H7XX
// each H7 timer have the same max clock speed
#define PWM_FREQ (STM32_TIMCLK1 / 1000U) // the timer will beat @240Mhz on STM32H7
#else
// some F4 and F7 timers are limited to / 2
// others are limited to STM32_SYSCLK
// so we take the max frequency that all timers can run
#define PWM_FREQ (STM32_SYSCLK / 2000U) // the timer will beat @84Mhz on STM32F4
#endif
/** Ticks per period /** Ticks per period
* that let use any timer: * that let use any timer:
@@ -72,11 +82,17 @@
*/ */
#define TICKS_PER_PERIOD 1000 #define TICKS_PER_PERIOD 1000
// ESCs are quite sensitive to the DSHOT duty cycle.
// 333 should work most of the time, but some ESC need 373
#ifndef DSHOT_BIT0_DUTY_RATIO
#define DSHOT_BIT0_DUTY_RATIO 373U
#endif
// Some extra defines and macros // Some extra defines and macros
#define DSHOT_FREQ (DSHOT_SPEED*1000) // in Hz #define DSHOT_FREQ (DSHOT_SPEED*1000) // in Hz
#define TICK_FREQ (PWM_FREQ * TICKS_PER_PERIOD) #define TICK_FREQ (PWM_FREQ * TICKS_PER_PERIOD)
#define DSHOT_PWM_PERIOD (TICK_FREQ/DSHOT_FREQ) #define DSHOT_PWM_PERIOD (TICK_FREQ/DSHOT_FREQ)
#define DSHOT_BIT0_DUTY (DSHOT_PWM_PERIOD * 373 / 1000) #define DSHOT_BIT0_DUTY (DSHOT_PWM_PERIOD * DSHOT_BIT0_DUTY_RATIO / 1000)
#define DSHOT_BIT1_DUTY (DSHOT_BIT0_DUTY*2) #define DSHOT_BIT1_DUTY (DSHOT_BIT0_DUTY*2)
#define DCR_DBL ((DSHOT_CHANNELS-1) << 8) // DSHOT_CHANNELS transfert(s), first register to get is CCR1 #define DCR_DBL ((DSHOT_CHANNELS-1) << 8) // DSHOT_CHANNELS transfert(s), first register to get is CCR1
#define DCR_DBA(pwmd) (((uint32_t *) (&pwmd->tim->CCR) - ((uint32_t *) pwmd->tim))) #define DCR_DBA(pwmd) (((uint32_t *) (&pwmd->tim->CCR) - ((uint32_t *) pwmd->tim)))
@@ -135,7 +151,11 @@ void dshotStart(DSHOTDriver *driver, const DSHOTConfig *config)
// use pburst, mburst only if buffer size satisfy aligmnent requirement // use pburst, mburst only if buffer size satisfy aligmnent requirement
driver->dma_conf = (DMAConfig) { driver->dma_conf = (DMAConfig) {
.stream = config->dma_stream, .stream = config->dma_stream,
#if STM32_DMA_SUPPORTS_DMAMUX
.dmamux = config->dmamux,
#else
.channel = config->dma_channel, .channel = config->dma_channel,
#endif
.dma_priority = 3, .dma_priority = 3,
.irq_priority = CORTEX_MAX_KERNEL_PRIORITY + 1, .irq_priority = CORTEX_MAX_KERNEL_PRIORITY + 1,
.direction = DMA_DIR_M2P, .direction = DMA_DIR_M2P,
sw/airborne/arch/chibios/modules/actuators/esc_dshot.h
+12 -1
View File
@@ -161,7 +161,11 @@ typedef struct {
/** /**
* @brief : dma channel associated with pwm timer used to generate dshot output * @brief : dma channel associated with pwm timer used to generate dshot output
*/ */
uint8_t dma_channel; #if STM32_DMA_SUPPORTS_DMAMUX
uint8_t dmamux;
#else
uint8_t dma_channel;
#endif
/** /**
* @brief PWM driver that feed up to 4 dshot lines * @brief PWM driver that feed up to 4 dshot lines
@@ -178,6 +182,13 @@ typedef struct {
*/ */
DshotDmaBuffer *dma_buf; DshotDmaBuffer *dma_buf;
#if DSHOT_BIDIR
/**
* @brief : DshotRpmCapture configuration structure when DSHOT_BIDIR is enabled
*/
DshotRpmCaptureConfig dma_capt_cfg;
#endif
#if __DCACHE_PRESENT #if __DCACHE_PRESENT
/** /**
* @brief DMA memory is in a cached section and beed to be flushed * @brief DMA memory is in a cached section and beed to be flushed
sw/airborne/boards/tawaki/chibios/v2.0/Makefile
+9
View File
@@ -0,0 +1,9 @@
# file board.h is generated from file board.cfg by a script which is hosted here :
# https://github.com/alex31/chibios_enac_various_common/blob/master/TOOLS/boardGen.pl
# documentation is here :
# https://github.com/alex31/chibios_enac_various_common/blob/master/TOOLS/DOC/boardGen.pdf
board.h: tawaki_2.0.cfg Makefile
boardGen.pl --no-pp-pin --no-pp-line $< $@
sw/airborne/boards/tawaki/chibios/v2.0/board.h
+1655
View File
File diff suppressed because it is too large Load Diff
sw/airborne/boards/tawaki/chibios/v2.0/mcuconf.h
+566
View File
File diff suppressed because it is too large Load Diff
sw/airborne/boards/tawaki/chibios/v2.0/tawaki_2.0.cfg
+148
View File
@@ -0,0 +1,148 @@
MCU_MODEL = STM32H753VIHx
CHIBIOS_VERSION = 3.0
HEADER
/*
* Board identifier.
*/
#define BOARD_TAWAKI_V2
#define BOARD_NAME "Tawaki V2Autopilot"
/*
* Board oscillators-related settings.
*/
#if !defined(STM32_LSECLK)
#define STM32_LSECLK 0
#endif
#define STM32_LSEDRV (3U << 3U)
#if !defined(STM32_HSECLK)
#define STM32_HSECLK 8000000U
#define STM32_HSE_BYPASS TRUE
#endif
/*
* Board voltages.
* Required for performance limits calculation.
*/
#define STM32_VDD 300U
/*
* MCU type as defined in the ST header.
*/
#define STM32H743xx
#define STM32H753xx
/*
* PWM TIM defines
* enable TIM1 by default
*/
#ifndef USE_PWM_TIM1
#define USE_PWM_TIM1 1
#endif
CONFIG
# PIN NAME PERIPH_TYPE AF_NUMBER or
# PIN NAME FUNCTION PP_or_OPENDRAIN PIN_SPEED PULL_RESISTOR INITIAL_LEVEL AF_NUMBER
# SPEED : SPEED_VERYLOW, SPEED_LOW, SPEED_MEDIUM, SPEED_HIGH
#
# DEFAULT AND SYS
#
# 'SYS' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
# 'ADC' => ['ANALOG', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_LOW'],
# 'PWM' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_LOW'],
# 'ICU' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
# 'I2C' => ['ALTERNATE', 'OPENDRAIN', 'SPEED_HIGH', 'PULLUP', 'LEVEL_HIGH'],
# 'SPI' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
# 'UART' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'PULLUP', 'LEVEL_HIGH'],
# 'OTG' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
# 'ETH' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
# 'FSMC' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
# 'SDIO' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'PULLUP', 'LEVEL_HIGH'],
# 'SDIOCK' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
# 'CAN' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
# 'DCMI' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
# 'LED' => ['OUTPUT', 'PUSHPULL', 'SPEED_VERYLOW', 'FLOATING', 'LEVEL_LOW'],
# 'PASSIVE' => ['INPUT', 'PUSHPULL', 'SPEED_VERYLOW', 'FLOATING', 'LEVEL_LOW']);
#
# SYSTEM
A13 SWDIO SWDIO AF:DEBUG_JTMS-SWDIO
A14 SWCLK SWDIO AF:DEBUG_JTCK-SWCLK
H00 OSC_IN SYS AF0
#C14 OSC32_IN SYS AF0
#C15 OSC32_OUT SYS AF0
#H01 OSC_OUT SYS AF0
#DEFAULT
DEFAULT INPUT PUSHPULL SPEED_VERYLOW PULLDOWN LEVEL_LOW AF0
# ACTIVE PINS
PA00 AUX_A1 PASSIVE (AF:USART2_CTS, AF:TIM2_CH1, ADC1_INP16)
PA01 AUX_A2 PASSIVE (AF:USART2_RTS, AF:TIM2_CH2, ADC1_INP17)
PA02 AUX_A3 PASSIVE (AF:TIM15_CH1)
PA03 AUX_A4 PASSIVE (AF:TIM15_CH2)
PA05 SPI6_INTERNAL_CLK SPI AF:SPI6_SCK
PA06 SRVB1 PWM AF:TIM3_CH1 ()
PA07 SRVB2 PWM AF:TIM3_CH2 ()
PA09 USB_VBUS INPUT PULLDOWN
PA10 DSHOT_TLM UART AF:USART1_RX
PA11 OTG_FS_DM OTG AF:USB_OTG_FS_DM
PA12 OTG_FS_DP OTG AF:USB_OTG_FS_DP
PA15 UART7_TX UART AF:UART7_TX
PB00 SRVB3 PWM AF:TIM3_CH3 ()
PB01 SRVB4 PWM AF:TIM3_CH4 ()
PB03 UART7_RX UART AF:UART7_RX
PB04 SPI6_INTERNAL_MISO SPI AF:SPI6_MISO
PB05 SPI6_INTERNAL_MOSI SPI AF:SPI6_MOSI
PB06 AUX_B1 PWM AF:TIM4_CH1
PB07 AUX_B2 PWM AF:TIM4_CH2
PB08 AUX_B3 PWM AF:TIM4_CH3
PB09 AUX_B4 PWM AF:TIM4_CH4
PB10 I2C2_SCL_EXTERNAL I2C AF:I2C2_SCL
PB11 I2C2_SDA_EXTERNAL I2C AF:I2C2_SDA
PB12 SPI2_EXTERNAL_CS OUTPUT PUSHPULL SPEED_HIGH FLOATING LEVEL_HIGH
PB14 SPI2_EXTERNAL_MISO SPI AF:SPI2_MISO
PB15 SPI2_EXTERNAL_MOSI SPI AF:SPI2_MOSI
PC00 VBAT_MEAS ADC ADC3_INP10 ()
PC06 RC2 PASSIVE (AF:USART6_TX)
PC07 LED1 LED
PC08 SDMMC1_D0 SDIO AF:SDMMC1_D0
PC09 SDMMC1_D1 SDIO AF:SDMMC1_D1
PC10 SDMMC1_D2 SDIO AF:SDMMC1_D2
PC11 SDMMC1_D3 SDIO AF:SDMMC1_D3
PC12 SDMMC1_CK SDIO AF:SDMMC1_CK
PC13 APSW OUTPUT PUSHPULL SPEED_VERYLOW FLOATING LEVEL_HIGH
PD00 CAN_RX CAN AF:FDCAN1_RX
PD01 CAN_TX CAN AF:FDCAN1_TX
PD02 SDMMC1_CMD SDIO AF:SDMMC1_CMD
PD03 SPI2_EXTERNAL_CLK SPI AF:SPI2_SCK
PD04 LED2 LED
PD05 UART2_TX UART AF:USART2_TX
PD06 UART2_RX UART AF:USART2_RX
PD08 UART3_TX UART AF:USART3_TX
PD09 UART3_RX UART AF:USART3_RX
PD10 LED4 LED
PD12 I2C4_SCL I2C AF:I2C4_SCL
PD13 I2C4_SDA I2C AF:I2C4_SDA
PD15 LED3 LED
PE00 RC1 UART AF:UART8_RX ()
PE03 SPI6_INTERNAL_CS OUTPUT PUSHPULL SPEED_HIGH FLOATING LEVEL_HIGH
PE09 SRVA1 PWM AF:TIM1_CH1 ()
PE11 SRVA2 PWM AF:TIM1_CH2 ()
PE13 SRVA3 PWM AF:TIM1_CH3 ()
PE14 SRVA4 PWM AF:TIM1_CH4 ()
sw/airborne/boards/tawaki/chibios/v2.0/tawaki_v2.0.h
+766
View File
File diff suppressed because it is too large Load Diff
sw/airborne/mcu.c
+3
View File
@@ -219,6 +219,9 @@ void mcu_init(void)
#endif #endif
#if USE_SPI4 #if USE_SPI4
spi4_init(); spi4_init();
#endif
#if USE_SPI6
spi6_init();
#endif #endif
spi_init_slaves(); spi_init_slaves();
#endif // SPI_MASTER #endif // SPI_MASTER
sw/airborne/mcu_periph/spi.c
+9
View File
@@ -85,6 +85,15 @@ void spi4_init(void)
} }
#endif // USE_SPI4 #endif // USE_SPI4
#if USE_SPI6
struct spi_periph spi6;
void spi6_init(void)
{
spi_init(&spi6);
spi6_arch_init();
}
#endif // USE_SPI6
void spi_init(struct spi_periph *p) void spi_init(struct spi_periph *p)
{ {
sw/airborne/mcu_periph/spi.h
+12
View File
@@ -262,6 +262,18 @@ extern void spi4_arch_init(void);
#endif // USE_SPI4 #endif // USE_SPI4
#if USE_SPI6
extern struct spi_periph spi6;
extern void spi6_init(void);
/** Architecture dependent SPI6 initialization.
* Must be implemented by underlying architecture
*/
extern void spi6_arch_init(void);
#endif // USE_SPI6
/** Initialize a spi peripheral. /** Initialize a spi peripheral.
* @param p spi peripheral to be configured * @param p spi peripheral to be configured
*/ */
sw/airborne/modules/loggers/sdlog_chibios/sdLog.c
+39 -5
View File
@@ -108,10 +108,44 @@
stm32f7 : regular sram : 256ko, dma only possible if data cache are explicitely flushed, fast stm32f7 : regular sram : 256ko, dma only possible if data cache are explicitely flushed, fast
dtcm sram : 64ko, dma, slow (no cache) dtcm sram : 64ko, dma, slow (no cache)
stm32h7 :
ram0nc (wx) : org = 0x24000000, len = 128k : non cached for DMA stuff
ram0 (wx) : org = 0x24000000, len = 384k : standard
ram1 (wx) : org = 0x30000000, len = 256k
ram2 (wx) : org = 0x30000000, len = 288k : ram1+ram3
ram3 (wx) : org = 0x30040000, len = 32k
ram4 (wx) : org = 0x38000000, len = 64k
ram5 (wx) : org = 0x20000000, len = 128k : DTCM : fast ram
ram6 (wx) : org = 0x00000000, len = 64k
ram7 (wx) : org = 0x38800000, len = 4k
*/ */
#ifdef STM32H7XX
#define IN_SDMMC_DMA_SECTION(x) IN_SDMMC_SECTION(x)
#define IN_SDMMC_DMA_SECTION_CLEAR(x) IN_SDMMC_SECTION_CLEAR(x)
#define IN_SDMMC_DMA_SECTION_NOINIT(x) IN_SDMMC_SECTION_NOINIT(x)
#else
#define IN_SDMMC_DMA_SECTION(x) IN_DMA_SECTION(x)
#define IN_SDMMC_DMA_SECTION_CLEAR(x) IN_DMA_SECTION_CLEAR(x)
#define IN_SDMMC_DMA_SECTION_NOINIT(x) IN_DMA_SECTION_NOINIT(x)
#endif
/*
s*printf functions are supposed to be thread safe, but the ones provided by
newlib function are not. One has to use _s*printf_r family that take a
struct _reent as first parameter.
*/
// #pragma GCC diagnostic push
// #pragma GCC diagnostic ignored "-Wmissing-field-initializers"
// static struct _reent reent = _REENT_INIT(reent);
// #pragma GCC diagnostic pop
static msg_t IN_STD_SECTION_CLEAR(queMbBuffer[SDLOG_QUEUE_BUCKETS]); static msg_t IN_STD_SECTION_CLEAR(queMbBuffer[SDLOG_QUEUE_BUCKETS]);
static MsgQueue messagesQueue; static MsgQueue messagesQueue;
@@ -139,7 +173,7 @@ struct FilePoolUnit {
uint8_t writeByteSeek; uint8_t writeByteSeek;
}; };
static struct FilePoolUnit IN_DMA_SECTION(fileDes[SDLOG_NUM_FILES]) = { static struct FilePoolUnit IN_SDMMC_DMA_SECTION(fileDes[SDLOG_NUM_FILES]) = {
[0 ... SDLOG_NUM_FILES - 1] = { [0 ... SDLOG_NUM_FILES - 1] = {
.fil = {{0}}, .inUse = false, .tagAtClose = false, .fil = {{0}}, .inUse = false, .tagAtClose = false,
.writeByteCache = NULL, .writeByteSeek = 0 .writeByteCache = NULL, .writeByteSeek = 0
@@ -167,7 +201,7 @@ struct _SdLogBuffer {
#endif // SDLOG_NEED_QUEUE #endif // SDLOG_NEED_QUEUE
/* File system object */ /* File system object */
static IN_DMA_SECTION(FATFS fatfs); static IN_SDMMC_DMA_SECTION(FATFS fatfs);
#ifdef SDLOG_NEED_QUEUE #ifdef SDLOG_NEED_QUEUE
static size_t logMessageLen(const LogMessage *lm); static size_t logMessageLen(const LogMessage *lm);
@@ -661,9 +695,9 @@ SdioError sdLogWriteByte(const FileDes fd, const uint8_t value)
#define WA_LOG_BASE_SIZE 1024 #define WA_LOG_BASE_SIZE 1024
#if FF_USE_LFN == 2 #if FF_USE_LFN == 2
#if FF_FS_EXFAT #if FF_FS_EXFAT
static IN_DMA_SECTION_NOINIT(THD_WORKING_AREA(waThdSdLog, WA_LOG_BASE_SIZE+((FF_MAX_LFN+1)*2)+(19*32))); static IN_SDMMC_DMA_SECTION_NOINIT(THD_WORKING_AREA(waThdSdLog, WA_LOG_BASE_SIZE+((FF_MAX_LFN+1)*2)+(19*32)));
#else #else
static IN_DMA_SECTION_NOINIT(THD_WORKING_AREA(waThdSdLog, WA_LOG_BASE_SIZE+((FF_MAX_LFN+1)*2))); static IN_SDMMC_DMA_SECTION_NOINIT(THD_WORKING_AREA(waThdSdLog, WA_LOG_BASE_SIZE+((FF_MAX_LFN+1)*2)));
#endif #endif
#else #else
static THD_WORKING_AREA(waThdSdLog, WA_LOG_BASE_SIZE); static THD_WORKING_AREA(waThdSdLog, WA_LOG_BASE_SIZE);
@@ -924,7 +958,7 @@ static void thdSdLog(void *arg)
} ; } ;
UINT bw; UINT bw;
static IN_DMA_SECTION_CLEAR(struct PerfBuffer perfBuffers[SDLOG_NUM_FILES]); static IN_SDMMC_DMA_SECTION_CLEAR(struct PerfBuffer perfBuffers[SDLOG_NUM_FILES]);
storageStatus = SDLOG_OK; storageStatus = SDLOG_OK;
chRegSetThreadName("thdSdLog"); chRegSetThreadName("thdSdLog");
while (true) { while (true) {
sw/ext/chibios
+1 -1
Submodule sw/ext/chibios updated: 5aa52cc1a4...686f812436