diff --git a/conf/airframes/CDW/LisaAspirin2.xml b/conf/airframes/CDW/LisaAspirin2.xml index f754ff8e00..365f2e4406 100644 --- a/conf/airframes/CDW/LisaAspirin2.xml +++ b/conf/airframes/CDW/LisaAspirin2.xml @@ -203,13 +203,13 @@ - + + --> @@ -256,8 +256,8 @@ - - + + diff --git a/conf/autopilot/subsystems/shared/imu_aspirin_v2.0.makefile b/conf/autopilot/subsystems/shared/imu_aspirin_v2.0.makefile index f96478e6a2..103c70d277 100644 --- a/conf/autopilot/subsystems/shared/imu_aspirin_v2.0.makefile +++ b/conf/autopilot/subsystems/shared/imu_aspirin_v2.0.makefile @@ -50,7 +50,7 @@ ifeq ($(ARCH), lpc21) #TODO else ifeq ($(ARCH), stm32) # IMU_ASPIRIN_CFLAGS += -DUSE_EXTI15_10_IRQ # Gyro Int on PC14 -# IMU_ASPIRIN_CFLAGS += -DUSE_DMA1_C4_IRQ # SPI2 Rx DMA +IMU_ASPIRIN_CFLAGS += -DUSE_DMA1_C4_IRQ # SPI2 Rx DMA endif IMU_ASPIRIN_CFLAGS += -DIMU_ASPIRIN_VERSION_2_0 diff --git a/sw/airborne/arch/stm32/mcu_periph/spi_arch.c b/sw/airborne/arch/stm32/mcu_periph/spi_arch.c index 4469e94ac4..fc17a26688 100644 --- a/sw/airborne/arch/stm32/mcu_periph/spi_arch.c +++ b/sw/airborne/arch/stm32/mcu_periph/spi_arch.c @@ -13,6 +13,7 @@ #define Spi2Slave0Unselect() GPIOB->BSRR = GPIO_Pin_12 #define Spi2Slave0Select() GPIOB->BRR = GPIO_Pin_12 + // spi dma end of rx handler void dma1_c4_irq_handler(void); @@ -63,7 +64,7 @@ void spi_init(void) { SPI_InitStructure.SPI_CPOL = SPI_CPOL_High; SPI_InitStructure.SPI_CPHA = SPI_CPHA_2Edge; SPI_InitStructure.SPI_NSS = SPI_NSS_Soft; - SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_32; + SPI_InitStructure.SPI_BaudRatePrescaler = SPI_BaudRatePrescaler_64; SPI_InitStructure.SPI_FirstBit = SPI_FirstBit_MSB; SPI_InitStructure.SPI_CRCPolynomial = 7; SPI_Init(SPI2, &SPI_InitStructure); @@ -71,6 +72,16 @@ void spi_init(void) { // Enable SPI_2 DMA clock --------------------------------------------------- RCC_AHBPeriphClockCmd(RCC_AHBPeriph_DMA1, ENABLE); + // SLAVE 0 + // set accel slave select as output and assert it ( on PB12) + Spi2Slave0Unselect(); + RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); + GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; + GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; + GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; + GPIO_Init(GPIOB, &GPIO_InitStructure); + + spi_arch_int_enable(); } /* @@ -147,8 +158,10 @@ void spi_rw(volatile uint8_t* _send, volatile uint8_t* _read, volatile int _len) // Accel end of DMA transfert -void dma1_c4_irq_handler(void) { +void dma1_c4_irq_handler(void) +{ Spi2Slave0Unselect(); + if (DMA_GetITStatus(DMA1_IT_TC4)) { // clear int pending bit DMA_ClearITPendingBit(DMA1_IT_GL4); diff --git a/sw/airborne/arch/stm32/mcu_periph/spi_arch.h b/sw/airborne/arch/stm32/mcu_periph/spi_arch.h index 7dfefa4b9a..8477924504 100644 --- a/sw/airborne/arch/stm32/mcu_periph/spi_arch.h +++ b/sw/airborne/arch/stm32/mcu_periph/spi_arch.h @@ -31,7 +31,6 @@ #include "mcu_periph/spi.h" #include - extern void spi_arch_int_enable(void); extern void spi_arch_int_disable(void); diff --git a/sw/airborne/arch/stm32/subsystems/imu/imu_aspirin2_arch.c b/sw/airborne/arch/stm32/subsystems/imu/imu_aspirin2_arch.c index 3120676324..d7bc7268e3 100644 --- a/sw/airborne/arch/stm32/subsystems/imu/imu_aspirin2_arch.c +++ b/sw/airborne/arch/stm32/subsystems/imu/imu_aspirin2_arch.c @@ -10,7 +10,7 @@ -// gyro int handler +// gyro interupt handler void exti15_10_irq_handler(void); void imu_aspirin2_arch_int_enable(void) { @@ -72,16 +72,8 @@ void imu_aspirin2_arch_init(void) { EXTI_InitStructure.EXTI_Trigger = EXTI_Trigger_Falling; EXTI_InitStructure.EXTI_LineCmd = ENABLE; EXTI_Init(&EXTI_InitStructure); - - // Accel - // set accel slave select as output and assert it ( on PB12) - Adxl345Unselect(); - RCC_APB2PeriphClockCmd(RCC_APB2Periph_GPIOB, ENABLE); - GPIO_InitStructure.GPIO_Pin = GPIO_Pin_12; - GPIO_InitStructure.GPIO_Mode = GPIO_Mode_Out_PP; - GPIO_InitStructure.GPIO_Speed = GPIO_Speed_50MHz; - GPIO_Init(GPIOB, &GPIO_InitStructure); */ + } diff --git a/sw/airborne/subsystems/imu/imu_aspirin2.c b/sw/airborne/subsystems/imu/imu_aspirin2.c index 0067265f6c..3a226d74ec 100644 --- a/sw/airborne/subsystems/imu/imu_aspirin2.c +++ b/sw/airborne/subsystems/imu/imu_aspirin2.c @@ -1,8 +1,13 @@ #include "subsystems/imu.h" +#include "led.h" #include "mcu_periph/spi.h" #include "mcu_periph/spi_arch.h" +// Peripherials +#include "../../peripherals/mpu60X0.h" + + struct ImuAspirin2 imu_aspirin2; /* @@ -19,11 +24,26 @@ void imu_impl_init(void) { imu_aspirin2.status = Aspirin2StatusUninit; imu_aspirin2.imu_available = FALSE; - imu_aspirin2_arch_init(); +// imu_aspirin2_arch_init(); +// spi_arch_int_enable(); + +// LED_TOGGLE(2); + LED_TOGGLE(3); } -void imu_periodic(void) { +void imu_periodic(void) +{ + +// LED_TOGGLE(2); +// LED_TOGGLE(3); + + imu_aspirin2.imu_len = 2; + imu_aspirin2.imu_tx_buf[0] = MPU60X0_REG_WHO_AM_I + 0x80; + imu_aspirin2.imu_tx_buf[1] = 0x00; + + spi_rw(imu_aspirin2.imu_tx_buf, imu_aspirin2.imu_rx_buf, imu_aspirin2.imu_len); + /* hmc5843_periodic(); if (imu_aspirin.status == AspirinStatusUninit) { @@ -39,7 +59,7 @@ void imu_periodic(void) { configure_accel(); imu_aspirin.time_since_last_accel_reading=0; } - } + } */ } diff --git a/sw/airborne/subsystems/imu/imu_aspirin2.h b/sw/airborne/subsystems/imu/imu_aspirin2.h index c1d054c791..f386c36bf4 100644 --- a/sw/airborne/subsystems/imu/imu_aspirin2.h +++ b/sw/airborne/subsystems/imu/imu_aspirin2.h @@ -66,6 +66,7 @@ struct ImuAspirin2 { volatile uint8_t imu_available; volatile uint8_t imu_tx_buf[64]; volatile uint8_t imu_rx_buf[64]; + volatile uint8_t imu_len; uint32_t time_since_last_reading; };