diff --git a/conf/boards/vms_ecu_1.0_chibios.makefile b/conf/boards/vms_ecu_1.0_chibios.makefile new file mode 100644 index 0000000000..9b3ec51ffa --- /dev/null +++ b/conf/boards/vms_ecu_1.0_chibios.makefile @@ -0,0 +1,77 @@ +# Hey Emacs, this is a -*- makefile -*- +# +# VMS_ECU_1.0_chibios.makefile +# +# + +BOARD=vms_ecu +BOARD_VERSION=1.0 +BOARD_DIR=$(BOARD)/chibios/v$(BOARD_VERSION) +BOARD_CFG=\"boards/$(BOARD_DIR)/board.h\" + +ARCH=chibios +$(TARGET).ARCHDIR = $(ARCH) + +RTOS=chibios + +# FPU on F4 +USE_FPU=yes +HARD_FLOAT=yes + +$(TARGET).CFLAGS += -DSTM32F4 -DPPRZLINK_ENABLE_FD + +############################################################################## +# Architecture or project specific options +# +# Define project name here (target) +PROJECT = $(TARGET) + +# Project specific files and paths (see Makefile.chibios for details) +CHIBIOS_BOARD_PLATFORM = STM32F4xx/platform.mk +CHIBIOS_BOARD_LINKER = STM32F407xG.ld +CHIBIOS_BOARD_STARTUP = startup_stm32f4xx.mk + +############################################################################## +# Compiler settings +# +MCU = cortex-m4 + +# default flash mode is via usb dfu bootloader +# possibilities: DFU-UTIL, SWD, STLINK +FLASH_MODE ?= SWD + +HAS_LUFTBOOT = FALSE + +# +# default LED configuration +# +RADIO_CONTROL_LED ?= none +BARO_LED ?= none +AHRS_ALIGNER_LED ?= none +GPS_LED ?= none +SYS_TIME_LED ?= none + +# +# default UART configuration (modem, gps, spektrum) +# + +RADIO_CONTROL_SPEKTRUM_PRIMARY_PORT ?= UART2 + +MODEM_PORT ?= UART2 +MODEM_BAUD ?= B57600 + +GPS_PORT ?= UART6 +GPS_BAUD ?= B38400 + +SBUS_PORT ?= UART5 + +# +# default actuator configuration +# +# you can use different actuators by adding a configure option to your firmware section +# e.g. +# +ACTUATORS ?= actuators_pwm + diff --git a/sw/airborne/boards/vms_ecu/chibios/v1.0/board.c b/sw/airborne/boards/vms_ecu/chibios/v1.0/board.c new file mode 100644 index 0000000000..777c0bc89f --- /dev/null +++ b/sw/airborne/boards/vms_ecu/chibios/v1.0/board.c @@ -0,0 +1,124 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} +#endif +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + return !palReadPad(GPIOB, GPIOB_SDIO_DETECT); +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} + diff --git a/sw/airborne/boards/vms_ecu/chibios/v1.0/board.h b/sw/airborne/boards/vms_ecu/chibios/v1.0/board.h new file mode 100644 index 0000000000..72110cdeb7 --- /dev/null +++ b/sw/airborne/boards/vms_ecu/chibios/v1.0/board.h @@ -0,0 +1,1345 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for STMicroelectronics STM32F4-Lisa MX. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM32F4_ECU +#define BOARD_NAME "STMicroelectronics STM32F4-Ecu" + + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 0 +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 25000000 +#endif + + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 330 + +/* + * MCU type as defined in the ST header file stm32f4xx.h. + */ +#define STM32F407xx + + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_2M(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_25M(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_50M(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_100M(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * Port A setup. + * + * PA0 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PA1 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PA2 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PA3 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PA4 - Analog output (DAC1) - set up as INPUT ANALOG (per reference manual) + * PA5 - Analog output (DAC2) - set up as INPUT ANALOG (per reference manual) + * PA6 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PA7 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PA8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PA9 - Alternate output (UART1_Tx) + * PA10 - Alternate input (UART1_Rx) + * PA11 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PA12 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PA13 - Digital input (JTAG_TMS/SWDIO) + * PA14 - Digital input (JTAG_TCK/SWCLCK) + * PA15 - Digital input (JTAG_TDI) + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(0)| \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_ALTERNATE(9) | \ + PIN_MODE_ALTERNATE(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_ALTERNATE(13) | \ + PIN_MODE_ALTERNATE(14) | \ + PIN_MODE_ALTERNATE(15)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLDOWN(0) | \ + PIN_PUPDR_PULLDOWN(1) | \ + PIN_PUPDR_PULLDOWN(2) | \ + PIN_PUPDR_PULLDOWN(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_PULLDOWN(6) | \ + PIN_PUPDR_PULLDOWN(7) | \ + PIN_PUPDR_PULLDOWN(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_PULLDOWN(11) | \ + PIN_PUPDR_PULLDOWN(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOA_ODR (PIN_ODR_LOW(0) | \ + PIN_ODR_LOW(1) | \ + PIN_ODR_LOW(2) | \ + PIN_ODR_LOW(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_LOW(6) | \ + PIN_ODR_LOW(7) | \ + PIN_ODR_LOW(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_LOW(10) | \ + PIN_ODR_LOW(11) | \ + PIN_ODR_LOW(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 7) | \ + PIN_AFIO_AF(10, 7) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * Port B setup: + * PB0 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PB1 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PB2 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PB3 - Digital input (JTAG_TDO/SWD) + * PB4 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PB5 - Alternate Digital input. (CAN2_RX) + * PB6 - Alternate Open Drain output 50MHz. (CAN2_TX) + * PB7 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PB8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PB9 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PB10 - Alternate Open Drain output 2MHz.(I2C2_SCL) + * PB11 - Alternate Open Drain output 2MHz.(I2C2_SDA) + * PB12 - Push Pull output 50MHz. (IMU_ACC_SPI2_CS) + * PB13 - Alternate Push Pull output 50MHz (IMU_SPI2_SCK) + * PB14 - Digital input (IMU_SPI2_MISO) + * PB15 - Alternate Push Pull output 50MHz (IMU_SPI2_MOSI) + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_ALTERNATE(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_ALTERNATE(5) | \ + PIN_MODE_ALTERNATE(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_ALTERNATE(10) | \ + PIN_MODE_ALTERNATE(11) | \ + PIN_MODE_OUTPUT(12) | \ + PIN_MODE_ALTERNATE(13) | \ + PIN_MODE_ALTERNATE(14) | \ + PIN_MODE_ALTERNATE(15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_OPENDRAIN(10) | \ + PIN_OTYPE_OPENDRAIN(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_50M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_2M(10) | \ + PIN_OSPEED_2M(11) | \ + PIN_OSPEED_50M(12) | \ + PIN_OSPEED_50M(13) | \ + PIN_OSPEED_50M(14) | \ + PIN_OSPEED_50M(15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLDOWN(0) | \ + PIN_PUPDR_PULLDOWN(1) | \ + PIN_PUPDR_PULLDOWN(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_PULLDOWN(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_PULLDOWN(7) | \ + PIN_PUPDR_PULLDOWN(8) | \ + PIN_PUPDR_PULLDOWN(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOB_ODR (PIN_ODR_LOW(0) | \ + PIN_ODR_LOW(1) | \ + PIN_ODR_LOW(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_LOW(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_LOW(7) | \ + PIN_ODR_LOW(8) | \ + PIN_ODR_LOW(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 9) | \ + PIN_AFIO_AF(6, 9) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 4) | \ + PIN_AFIO_AF(11, 4) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 5) | \ + PIN_AFIO_AF(14, 5) | \ + PIN_AFIO_AF(15, 5)) + +/* + * Port C setup: + * PC0 - Analog input (ADC1) + * PC1 - Analog input (ADC2) + * PC2 - Analog input (ADC3) + * PC3 - Analog input (ADC4) + * PC4 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PC5 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PC6 - Alternate Push Pull output 50MHz (UART6_TX) + * PC7 - Alternate input (UART7_RX) + * PC8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PC9 - Push Pull output 50MHz (SPI3_NSS) + * PC10 - Alternate Push Pull output 50MHz (SPI3_SCK) + * PC11 - Alternate Digital input (SPI3_MISO) + * PC12 - Alternate Push Pull output 50MHz (SPI3_MOSI) + * PC13 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PC14 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PC15 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(0) |\ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_ALTERNATE(6) | \ + PIN_MODE_ALTERNATE(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_OUTPUT(9) | \ + PIN_MODE_ALTERNATE(10) | \ + PIN_MODE_ALTERNATE(11) | \ + PIN_MODE_ALTERNATE(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(0) |\ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(0) |\ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_50M(6) | \ + PIN_OSPEED_50M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_50M(9) | \ + PIN_OSPEED_50M(10) | \ + PIN_OSPEED_50M(11) | \ + PIN_OSPEED_50M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(0) |\ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_PULLDOWN(4) | \ + PIN_PUPDR_PULLDOWN(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_PULLDOWN(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_PULLDOWN(13) | \ + PIN_PUPDR_PULLDOWN(14) | \ + PIN_PUPDR_PULLDOWN(15)) +#define VAL_GPIOC_ODR (PIN_ODR_LOW(0) | \ + PIN_ODR_LOW(1) | \ + PIN_ODR_LOW(2) | \ + PIN_ODR_LOW(3) | \ + PIN_ODR_LOW(4) | \ + PIN_ODR_LOW(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_LOW(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_LOW(13) | \ + PIN_ODR_LOW(14) | \ + PIN_ODR_LOW(15)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(0, 0) |\ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 8) | \ + PIN_AFIO_AF(7, 8)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 6) | \ + PIN_AFIO_AF(11, 6) | \ + PIN_AFIO_AF(12, 6) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * Port D setup: + * PD0 - Alternate Digital input. (CAN1_RX). + * PD1 - Alternate Open Drain output 50MHz (CAN1_TX). + * PD2 - Digital input (CARD_DETECT). + * PD3 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD4 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD5 - Alternate Push Pull output 50MHz. (UART2_TX). + * PD6 - Alternate Digital input. (UART2_RX). + * PD7 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD8 - Alternate Push Pull output 50MHz. (UART3_TX). + * PD9 - Alternate Digital input. (UART3_RX). + * PD10 - Digital output. (DOUT_LS1). + * PD11 - Digital output. (DOUT_LS2). + * PD12 - Digital output. (DOUT_LS3). + * PD13 - Digital output. (DOUT_LS4). + * PD14 - Digital output. (DOUT_HS1). + * PD15 - Digital output. (DOUT_HS2). + */ +#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(0) | \ + PIN_MODE_ALTERNATE(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_ALTERNATE(5) | \ + PIN_MODE_ALTERNATE(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_ALTERNATE(8) | \ + PIN_MODE_ALTERNATE(9) | \ + PIN_MODE_OUTPUT(10) | \ + PIN_MODE_OUTPUT(11) | \ + PIN_MODE_OUTPUT(12) | \ + PIN_MODE_OUTPUT(13) | \ + PIN_MODE_OUTPUT(14) | \ + PIN_MODE_OUTPUT(15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) |\ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_50M(0) | \ + PIN_OSPEED_50M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_50M(5) | \ + PIN_OSPEED_50M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_50M(8) | \ + PIN_OSPEED_50M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) |\ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_LOW(3) | \ + PIN_ODR_LOW(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_LOW(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_LOW(10) | \ + PIN_ODR_LOW(11) | \ + PIN_ODR_LOW(12) | \ + PIN_ODR_LOW(13) | \ + PIN_ODR_LOW(14) | \ + PIN_ODR_LOW(15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(0, 9) | \ + PIN_AFIO_AF(1, 9) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 7) | \ + PIN_AFIO_AF(6, 7) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(8, 7) | \ + PIN_AFIO_AF(9, 7) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * Port E setup: + * PE0 - Digital input (IMU_MAG_DRDY) + * PE1 - Digital input (IMU_ACC_DRDY) + * PE2 - Digital input (IMU_GYRO_DRDY) + * PE3 - Push Pull output 50MHz. (IMU_GYRO_SS) + * PE4 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PE5 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PE6 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PE7 - Digital input. (DIN1). + * PE8 - Digital input. (DIN2). + * PE9 - Digital input. (DIN3). + * PE10 - Digital input. (DIN4). + * PE11 - Digital input. (DIN5). + * PE12 - Digital input. (DIN6). + * PE13 - Digital input. (DIN7). + * PE14 - Digital input. (DIN8). + * PE15 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_OUTPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_50M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * GPIOF setup: + * + * PF0 - PF15 (input floating). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * GPIOG setup: + * + * PG0 - PG15 (input floating). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * GPIOH setup: + * + * PH0 - PH15 (input floating). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * GPIOI setup: + * + * PI0 - PI15 (input floating). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + + +/* + * AHB_CLK + */ +#define AHB_CLK STM32_HCLK + + +/* + * LEDs + */ +/* 1 red, on PA8 */ +#ifndef USE_LED_1 +#define USE_LED_1 1 +#endif +#define LED_1_GPIO GPIOA +#define LED_1_GPIO_PIN 8 +#define LED_1_GPIO_ON gpio_clear +#define LED_1_GPIO_OFF gpio_set + +/* 2 green, shared with JTAG_TRST */ +#ifndef USE_LED_2 +#define USE_LED_2 1 +#endif +#define LED_2_GPIO GPIOB +#define LED_2_GPIO_PIN 4 +#define LED_2_GPIO_ON gpio_clear +#define LED_2_GPIO_OFF gpio_set + +/* 3 green, shared with ADC12 (ADC_6 on connector ANALOG2) */ +#ifndef USE_LED_3 +#define USE_LED_3 1 +#endif +#define LED_3_GPIO GPIOC +#define LED_3_GPIO_PIN 2 +#define LED_3_GPIO_ON gpio_clear +#define LED_3_GPIO_OFF gpio_set + +/* 4 red, shared with ADC15 (ADC_4 on connector ANALOG2) */ +#ifndef USE_LED_4 +#define USE_LED_4 1 +#endif +#define LED_4_GPIO GPIOC +#define LED_4_GPIO_PIN 5 +#define LED_4_GPIO_ON gpio_clear +#define LED_4_GPIO_OFF gpio_set + +/* 5 green, on PC15 */ +#ifndef USE_LED_5 +#define USE_LED_5 0 +#endif +#define LED_5_GPIO GPIOC +#define LED_5_GPIO_PIN 15 +#define LED_5_GPIO_ON gpio_set +#define LED_5_GPIO_OFF gpio_clear + +/* + * ADCs + */ +// AIN1 enabled by default +#ifndef USE_ADC_1 +#define USE_ADC_1 1 +#endif +#if USE_ADC_1 +#define AD1_1_CHANNEL ADC_CHANNEL_IN10 +#define ADC_1 AD1_1 +#define ADC_1_GPIO_PORT GPIOC +#define ADC_1_GPIO_PIN GPIO0 +#endif + +// AIN2 enabled by default +#ifndef USE_ADC_2 +#define USE_ADC_2 1 +#endif +#if USE_ADC_2 +#define AD1_2_CHANNEL ADC_CHANNEL_IN11 +#define ADC_2 AD1_2 +#define ADC_2_GPIO_PORT GPIOC +#define ADC_2_GPIO_PIN GPIO1 +#endif + +// AIN3 enabled by default +#ifndef USE_ADC_3 +#define USE_ADC_3 1 +#endif +#if USE_ADC_3 +#define AD1_3_CHANNEL ADC_CHANNEL_IN12 +#define ADC_3 AD1_3 +#define ADC_3_GPIO_PORT GPIOC +#define ADC_3_GPIO_PIN GPIO2 +#endif + +// AIN4 enabled by default +#ifndef USE_ADC_4 +#define USE_ADC_4 1 +#endif +#if USE_ADC_4 +#define AD1_4_CHANNEL ADC_CHANNEL_IN13 +#define ADC_4 AD1_4 +#define ADC_4_GPIO_PORT GPIOC +#define ADC_4_GPIO_PIN GPIO3 +#endif + + +// Internal Temperature sensor enabled by default +/* +#ifndef USE_ADC_5 +#define USE_ADC_5 1 +#define USE_ADC_SENSOR 1 +#endif +#if USE_ADC_5 +#define AD1_5_CHANNEL ADC_CHANNEL_SENSOR +#define ADC_5 AD1_5 +#define ADC_5_GPIO_PORT GPIOC // dummy pin +#define ADC_5_GPIO_PIN GPIO3 // dummy pin +#endif +*/ + +// Add board defines +#define AIN_1 AD1_1_CHANNEL +#define AIN_2 AD1_2_CHANNEL +#define AIN_3 AD1_3_CHANNEL +#define AIN_4 AD1_4_CHANNEL + +/* allow to define ADC_CHANNEL_VSUPPLY in the airframe file*/ +//#ifndef ADC_CHANNEL_VSUPPLY +//#define ADC_CHANNEL_VSUPPLY ADC_1 +//#endif + +//#define ADC_CHANNEL_CURRENT ADC_2 + +#define DefaultVoltageOfAdc(adc) (0.000805664*adc)//(0.004489*adc) +#define DefaultMilliAmpereOfAdc(adc) (0.004489*adc) + +/* + * PWM defines + */ +#ifndef USE_PWM0 +#define USE_PWM0 1 +#endif +#if USE_PWM0 +#define PWM_SERVO_0 0 +#define PWM_SERVO_0_GPIO GPIOB +#define PWM_SERVO_0_PIN GPIO0 +#define PWM_SERVO_0_AF GPIO_AF2 +#define PWM_SERVO_0_DRIVER PWMD3 +#define PWM_SERVO_0_CHANNEL 2 +#define PWM_SERVO_0_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_0_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM1 +#define USE_PWM1 1 +#endif +#if USE_PWM1 +#define PWM_SERVO_1 1 +#define PWM_SERVO_1_GPIO GPIOA +#define PWM_SERVO_1_PIN GPIO2 +#define PWM_SERVO_1_AF GPIO_AF1 +#define PWM_SERVO_1_DRIVER PWMD3 +#define PWM_SERVO_1_CHANNEL 2 +#define PWM_SERVO_1_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_1_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM2 +#define USE_PWM2 1 +#endif +#if USE_PWM2 +#define PWM_SERVO_2 2 +#define PWM_SERVO_2_GPIO GPIOB +#define PWM_SERVO_2_PIN GPIO5 +#define PWM_SERVO_2_AF GPIO_AF3 +#define PWM_SERVO_2_DRIVER PWMD3 +#define PWM_SERVO_2_CHANNEL 1 +#define PWM_SERVO_2_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_2_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM3 +#define USE_PWM3 1 +#endif +#if USE_PWM3 +#define PWM_SERVO_3 3 +#define PWM_SERVO_3_GPIO GPIOB +#define PWM_SERVO_3_PIN GPIO4 +#define PWM_SERVO_3_AF GPIO_AF2 +#define PWM_SERVO_3_DRIVER PWMD3 +#define PWM_SERVO_3_CHANNEL 0 +#define PWM_SERVO_3_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_3_ACTIVE PWM_OUTPUT_DISABLED +#endif + + +/** + * PPM radio defines + */ +#define RC_PPM_TICKS_PER_USEC 6 +#define PPM_TIMER_FREQUENCY 6000000 +#define PPM_CHANNEL ICU_CHANNEL_3 +#define PPM_TIMER ICUD1 + +/** + * I2C defines + */ +#define I2C1_CLOCK_SPEED 400000 +#define I2C1_CFG_DEF { \ + OPMODE_I2C, \ + I2C1_CLOCK_SPEED, \ + FAST_DUTY_CYCLE_2, \ + } + +#define I2C2_CLOCK_SPEED 400000 +#define I2C2_CFG_DEF { \ + OPMODE_I2C, \ + I2C2_CLOCK_SPEED, \ + FAST_DUTY_CYCLE_2, \ + } + +/** + * SPI Config + */ +#define SPI1_GPIO_AF GPIO_AF5 +#define SPI1_GPIO_PORT_MISO GPIOA +#define SPI1_GPIO_MISO GPIO6 +#define SPI1_GPIO_PORT_MOSI GPIOA +#define SPI1_GPIO_MOSI GPIO7 +#define SPI1_GPIO_PORT_SCK GPIOA +#define SPI1_GPIO_SCK GPIO5 + +// SLAVE0 on SPI connector +#define SPI_SELECT_SLAVE0_PORT GPIOB +#define SPI_SELECT_SLAVE0_PIN 9 +// SLAVE1 on AUX1 +#define SPI_SELECT_SLAVE1_PORT GPIOB +#define SPI_SELECT_SLAVE1_PIN 1 +// SLAVE2 on AUX2 +#define SPI_SELECT_SLAVE2_PORT GPIOC +#define SPI_SELECT_SLAVE2_PIN 5 +// SLAVE3 on AUX3 +#define SPI_SELECT_SLAVE3_PORT GPIOC +#define SPI_SELECT_SLAVE3_PIN 4 +// SLAVE4 on AUX4 +#define SPI_SELECT_SLAVE4_PORT GPIOB +#define SPI_SELECT_SLAVE4_PIN 5 + +/** + * Baro + * + * Apparently needed for backwards compatibility + * with the ancient onboard baro boards + */ +#ifndef USE_BARO_BOARD +#define USE_BARO_BOARD 0 +#endif + +/* + * Actuators for fixedwing + */ + /* Default actuators driver */ +#define DEFAULT_ACTUATORS "subsystems/actuators/actuators_pwm.h" +#define ActuatorDefaultSet(_x,_y) ActuatorPwmSet(_x,_y) +#define ActuatorsDefaultInit() ActuatorsPwmInit() +#define ActuatorsDefaultCommit() ActuatorsPwmCommit() + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/sw/airborne/boards/vms_ecu/chibios/v1.0/board.mk b/sw/airborne/boards/vms_ecu/chibios/v1.0/board.mk new file mode 100644 index 0000000000..5a109515f4 --- /dev/null +++ b/sw/airborne/boards/vms_ecu/chibios/v1.0/board.mk @@ -0,0 +1,20 @@ +# +# ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Required include directories +BOARDINC = $(CHIBIOS_BOARD_DIR) + +# List of all the board related files. +BOARDSRC = ${BOARDINC}/board.c diff --git a/sw/airborne/boards/vms_ecu/chibios/v1.0/mcuconf.h b/sw/airborne/boards/vms_ecu/chibios/v1.0/mcuconf.h new file mode 100644 index 0000000000..035d5259f8 --- /dev/null +++ b/sw/airborne/boards/vms_ecu/chibios/v1.0/mcuconf.h @@ -0,0 +1,374 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 25 +#define STM32_PLLN_VALUE 432 +#define STM32_PLLP_VALUE 4 +#define STM32_PLLQ_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#if USE_CAN1 +#define STM32_CAN_USE_CAN1 TRUE +#else +#define STM32_CAN_USE_CAN1 FALSE +#endif +#if USE_CAN2 +#define STM32_CAN_USE_CAN2 TRUE +#else +#define STM32_CAN_USE_CAN2 FALSE +#endif +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#if USE_DAC1 +#define STM32_DAC_USE_DAC1_CH1 TRUE +#else +#define STM32_DAC_USE_DAC1_CH1 FALSE +#endif +#if USE_DAC2 +#define STM32_DAC_USE_DAC1_CH2 TRUE +#else +#define STM32_DAC_USE_DAC1_CH2 FALSE +#endif +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#if USE_I2C1 +#define STM32_I2C_USE_I2C1 TRUE +#else +#define STM32_I2C_USE_I2C1 FALSE +#endif +#if USE_I2C2 +#define STM32_I2C_USE_I2C2 TRUE +#else +#define STM32_I2C_USE_I2C2 FALSE +#endif +#if USE_I2C3 +#define STM32_I2C_USE_I2C3 TRUE +#else +#define STM32_I2C_USE_I2C3 FALSE +#endif +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 TRUE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#if USE_UART1 +#define STM32_SERIAL_USE_USART1 TRUE +#else +#define STM32_SERIAL_USE_USART1 FALSE +#endif +#if USE_UART2 +#define STM32_SERIAL_USE_USART2 TRUE +#else +#define STM32_SERIAL_USE_USART2 FALSE +#endif +#if USE_UART3 +#define STM32_SERIAL_USE_USART3 TRUE +#else +#define STM32_SERIAL_USE_USART3 FALSE +#endif +#if USE_UART4 +#define STM32_SERIAL_USE_UART4 TRUE +#else +#define STM32_SERIAL_USE_UART4 FALSE +#endif +#if USE_UART5 +#define STM32_SERIAL_USE_UART5 TRUE +#else +#define STM32_SERIAL_USE_UART5 FALSE +#endif +#if USE_UART6 +#define STM32_SERIAL_USE_USART6 TRUE +#else +#define STM32_SERIAL_USE_USART6 FALSE +#endif +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 15 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#if USE_SPI1 +#define STM32_SPI_USE_SPI1 TRUE +#else +#define STM32_SPI_USE_SPI1 FALSE +#endif +#if USE_SPI2 +#define STM32_SPI_USE_SPI2 TRUE +#else +#define STM32_SPI_USE_SPI2 FALSE +#endif +#if USE_SPI3 +#define STM32_SPI_USE_SPI3 TRUE +#else +#define STM32_SPI_USE_SPI3 FALSE +#endif +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + + +/* + * UART driver system settings. + */ +#if USE_UARTD1 +#define STM32_UART_USE_USART1 TRUE +#else +#define STM32_UART_USE_USART1 FALSE +#endif +#if USE_UARTD2 +#define STM32_UART_USE_USART2 TRUE +#else +#define STM32_UART_USE_USART2 FALSE +#endif +#if USE_UARTD3 +#define STM32_UART_USE_USART3 TRUE +#else +#define STM32_UART_USE_USART3 FALSE +#endif +#if USE_UARTD6 +#define STM32_UART_USE_USART6 TRUE +#else +#define STM32_UART_USE_USART6 FALSE +#endif +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 7 +#define STM32_UART_USART2_IRQ_PRIORITY 6 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 13 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#if USE_USB_SERIAL +#define STM32_USB_USE_OTG1 TRUE +#else +#define STM32_USB_USE_OTG1 FALSE +#endif +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 +