From 601d942c71b390726ca92bfe99c66c3378638f85 Mon Sep 17 00:00:00 2001
From: Michal Podhradsky <michal.podhradsky@aggiemail.usu.edu>
Date: Sat, 11 Feb 2017 10:09:37 -0800
Subject: [PATCH] [chibios] Make compatible with STM32F1 chips

---
 sw/airborne/arch/chibios/mcu_arch.c             |  9 ++-------
 sw/airborne/arch/chibios/mcu_periph/gpio_arch.c | 11 +++++++++++
 sw/airborne/arch/chibios/mcu_periph/spi_arch.c  |  4 ++--
 3 files changed, 15 insertions(+), 9 deletions(-)

diff --git a/sw/airborne/arch/chibios/mcu_arch.c b/sw/airborne/arch/chibios/mcu_arch.c
index 50724c0c7f..dd0bd17baf 100644
--- a/sw/airborne/arch/chibios/mcu_arch.c
+++ b/sw/airborne/arch/chibios/mcu_arch.c
@@ -90,18 +90,13 @@ bool recovering_from_hard_fault;
 
 /*
  * SCB_VTOR has to be relocated if Luftboot is used
+ * The new SCB_VTOR location is defined in the board makefile
  */
 void mcu_arch_init(void)
 {
 #if LUFTBOOT
   PRINT_CONFIG_MSG("We are running luftboot, the interrupt vector is being relocated.")
-#if defined STM32F4
-  PRINT_CONFIG_MSG("STM32F4")
-  SCB->VTOR = 0x00004000;
-#else
-  PRINT_CONFIG_MSG("STM32F1")
-  SCB->VTOR = 0x00002000;
-#endif
+  SCB->VTOR = CORTEX_VTOR_INIT;
 #endif
 
   /*
diff --git a/sw/airborne/arch/chibios/mcu_periph/gpio_arch.c b/sw/airborne/arch/chibios/mcu_periph/gpio_arch.c
index 3a787a9182..39c5678f53 100644
--- a/sw/airborne/arch/chibios/mcu_periph/gpio_arch.c
+++ b/sw/airborne/arch/chibios/mcu_periph/gpio_arch.c
@@ -61,7 +61,18 @@ void gpio_setup_input_pulldown(ioportid_t port, uint16_t gpios)
 void gpio_setup_pin_af(ioportid_t port, uint16_t pin, uint8_t af)
 {
   chSysLock();
+// architecture dependent settings
+#if defined(__STM32F10x_H) || defined(__STM32F105xC_H) || defined (__STM32F107xC_H)
+// STM32F1xx
+// FIXME: STM32F1xx doesn't support several alternate modes, is it needed for drivers?
+  (void)port;
+  (void)pin;
+  (void)af;
+#elif defined(__STM32F4xx_H)
+// STM32F4xx
   palSetPadMode(port, pin, PAL_MODE_ALTERNATE(af));
+#endif // STM32F1xx vs STM32F4xx
+
   chSysUnlock();
 }
 
diff --git a/sw/airborne/arch/chibios/mcu_periph/spi_arch.c b/sw/airborne/arch/chibios/mcu_periph/spi_arch.c
index e695fa462d..6e6e7b7876 100644
--- a/sw/airborne/arch/chibios/mcu_periph/spi_arch.c
+++ b/sw/airborne/arch/chibios/mcu_periph/spi_arch.c
@@ -148,7 +148,7 @@ static inline uint16_t spi_resolve_slave_pin(uint8_t slave)
 static inline uint16_t spi_resolve_CR1(struct spi_transaction *t)
 {
   uint16_t CR1 = 0;
-#if defined(__STM32F10x_H) || defined(__STM32F4xx_H)
+#if defined(__STM32F10x_H) || defined(__STM32F105xC_H) || defined (__STM32F107xC_H) || defined(__STM32F4xx_H)
   if (t->dss == SPIDss16bit) {
     CR1 |= SPI_CR1_DFF;
   }
@@ -189,7 +189,7 @@ static inline uint16_t spi_resolve_CR1(struct spi_transaction *t)
     default:
       break;
   }
-#endif /* STM32F10x_H || STM32F4xx_H */
+#endif /* __STM32F10x_H || __STM32F105xC_H || __STM32F107xC_H || STM32F4xx_H */
   return CR1;
 }