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[board] support of the Chimera autopilot based on STM32F7 (#2018)

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* [board] support of the Chimera autopilot based on STM32F7

- based on ChibiOS only (updated to master for proper support of F7)
- requires some specific ram for DMA operations
- SBUS driver updated and support of internal inverted logic option of F7

* [chibios] fix some compilation errors

* [chibios] fix some a few PR comments

- test less MCU types
- support F1 for uart driver
- more autodetect for VTOR_INIT

* use correct path

* choose a working version of chibios

* [chibios] fix some comments from PR review

- add some doc
- protect LED
- update TRUE/FALSE for lowercase
- pick a slightly older version of chibios (wrong path in makefile not
  fixed yet)
This commit is contained in:
Gautier Hattenberger
2017-02-23 19:31:50 +01:00
committed by Michal Podhradsky
parent 81fd2161c4
commit 4e5d863291
50 changed files with 4074 additions and 201 deletions
Download Patch File Download Diff File Expand all files Collapse all files
conf/Makefile.chibios
+15 -11
View File
@@ -50,7 +50,7 @@ ifdef CHIBIOS_BOOTLOADER_SCRIPT
CHIBIOS_LINKER_DIR ?= $(PAPARAZZI_SRC)/sw/airborne/arch/chibios/
else
# we use the original linker script
CHIBIOS_LINKER_DIR ?= $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld
CHIBIOS_LINKER_DIR ?= $(STARTUPLD)
endif
# Launch with "make Q=''" to get full command display
@@ -129,6 +129,11 @@ endif
# Enable this if you want link time optimizations (LTO)
ifeq ($(USE_LTO),)
USE_LTO = no
else
# Force LTO to 'no' if in debug mode
ifeq (,$(findstring $(RTOS_DEBUG),0 FALSE))
USE_LTO = no
endif
endif
# If enabled, this option allows to compile the application in THUMB mode.
@@ -171,9 +176,9 @@ ifeq ($(USE_EXCEPTIONS_STACKSIZE),)
USE_EXCEPTIONS_STACKSIZE = 0x400
endif
# Enables the use of FPU on Cortex-M4.
# Enables the use of FPU on Cortex-M4 / M7 (no, softfp, hard).
ifeq ($(USE_FPU),)
USE_FPU = yes
USE_FPU = hard
endif
#
@@ -188,7 +193,7 @@ endif
# Imported source files and paths
# Startup files.
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/$(CHIBIOS_BOARD_STARTUP)
include $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC/mk/$(CHIBIOS_BOARD_STARTUP)
# HAL-OSAL files (optional).
include $(CHIBIOS)/os/hal/hal.mk
include $(CHIBIOS)/os/hal/ports/STM32/$(CHIBIOS_BOARD_PLATFORM)
@@ -196,9 +201,9 @@ include $(CHIBIOS_BOARD_DIR)/board.mk
include $(CHIBIOS)/os/hal/osal/rt/osal.mk
# RTOS files (optional).
include $(CHIBIOS)/os/rt/rt.mk
include $(CHIBIOS)/os/rt/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
include $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/mk/port_v7m.mk
# Other files (optional).
#include $(CHIBIOS)/test/rt/test.mk
#
ifeq ($(USE_FATFS), TRUE)
include $(PAPARAZZI_HOME)/conf/chibios/fatfs.mk
endif
@@ -246,9 +251,9 @@ TCSRC =
TCPPSRC =
# List ASM source files here
ASMSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
ASMXSRC = $(STARTUPASM) $(PORTASM) $(OSALASM)
INCDIR = $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
INCDIR = $(CHIBIOS)/os/license $(STARTUPINC) $(KERNINC) $(PORTINC) $(OSALINC) \
$(HALINC) $(PLATFORMINC) $(BOARDINC) $(FATFSINC) \
$(CHIBIOS)/os/various $(CHIBIOS_BOARD_DIR) $(CHIBIOS_PROJECT_DIR)
@@ -308,7 +313,7 @@ UADEFS = $($(TARGET).CFLAGS) $(USER_CFLAGS) $(BOARD_CFLAGS)
# List all user directories here
# remove -I before include dir because ChibiOS is adding them again
UINCDIR = $(patsubst -I%,%,$(INCLUDES))
UINCDIR = $(CHIBIOS)/os/license $(patsubst -I%,%,$(INCLUDES))
# List the user directory to look for the libraries here
ULIBDIR =
@@ -334,7 +339,6 @@ endif
# Settings for GDB
# default port configuration for BMP
GDB = $(shell which arm-none-eabi-gdb)
@@ -355,7 +359,7 @@ include $(PAPARAZZI_HOME)/conf/Makefile.stm32-upload
###############################################################################
RULESPATH = $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC
RULESPATH = $(CHIBIOS)/os/common/startup/ARMCMx/compilers/GCC
#include $(RULESPATH)/rules.mk
EXTRA_RULES_INCLUDE_PATH = $(PAPARAZZI_HOME)/conf/chibios/chibios_extra_rules.mk
conf/airframes/ENAC/fixed-wing/chimera.xml
+227
View File
@@ -0,0 +1,227 @@
<!DOCTYPE airframe SYSTEM "../../airframe.dtd">
<!--
Chimera test board
Mako (http://www.readymaderc.com)
Apogee 1.0
XBEE modem
UBX GPS / HMC58XX mag (drotek)
-->
<airframe name="Chimera">
<firmware name="fixedwing">
<configure name="RTOS_DEBUG" value="1"/>
<target name="ap" board="chimera_1.0">
<module name="radio_control" type="sbus"/>
<configure name="PERIODIC_FREQUENCY" value="100"/>
</target>
<target name="sim" board="pc">
<module name="radio_control" type="ppm"/>
</target>
<!-- Communication -->
<module name="telemetry" type="xbee_api"/>
<!-- Actuators are automatically chosen according to board-->
<module name="imu" type="chimera"/>
<configure name="USE_MAGNETOMETER" value="FALSE"/>
<module name="ahrs" type="float_dcm"/>
<module name="ins" type="alt_float"/>
<module name="control" type="new"/>
<module name="navigation"/>
<!-- Sensors -->
<module name="gps" type="ublox"/>
<module name="air_data"/>
<module name="airspeed" type="ms45xx_i2c">
<define name="MS45XX_I2C_DEV" value="i2c1"/>
</module>
<module name="sys_mon"/>
<!--module name="pwm_meas"/-->
<!--module name="spi_master"/-->
<!--module name="meteo_stick">
<configure name="MS_SPI_DEV" value="SPI1"/>
<configure name="MS_PRESSURE_SLAVE_IDX" value="0"/>
<configure name="MS_DIFF_PRESSURE_SLAVE_IDX" value="3"/>
<configure name="MS_TEMPERATURE_SLAVE_IDX" value="2"/>
<configure name="MS_EEPROM_SLAVE_IDX" value="1"/>
<configure name="MS_HUMIDITY_PWM_INPUT" value="PWM_INPUT1"/>
<define name="USE_MS_TEMPERATURE" value="FALSE"/>
</module-->
<!--module name="AOA_pwm">
<configure name="AOA_PWM_CHANNEL" value="PWM_INPUT2"/>
</module-->
<module name="tlsf"/>
<module name="pprzlog"/>
<module name="logger" type="sd_chibios"/>
<module name="flight_recorder"/>
<!-- <module name="mcp355x"> -->
<!-- <define name="USE_SPI1"/> -->
<!-- </module> -->
<!--module name="extra_dl">
<configure name="EXTRA_DL_PORT" value="UART6"/>
<configure name="EXTRA_DL_BAUD" value="B57600"/>
</module>
<module name="meteo_france_DAQ"/-->
</firmware>
<firmware name="test_chibios">
<target name="test_sys_time_timer" board="chimera_1.0"/>
<target name="test_led" board="chimera_1.0"/>
<target name="test_sys_gpio" board="chimera_1.0"/>
</firmware>
<section name="METEO_STICK">
<define name="LOG_MS" value="TRUE"/>
<define name="SEND_MS" value="TRUE"/>
</section>
<!-- commands section -->
<servos>
<servo name="MOTOR" no="0" min="1000" neutral="1000" max="1800"/>
<servo name="AILEVON_LEFT" no="1" min="1000" neutral="1500" max="2000"/>
<servo name="AILEVON_RIGHT" no="2" min="2000" neutral="1500" max="1000"/>
</servos>
<commands>
<axis name="THROTTLE" failsafe_value="0"/>
<axis name="ROLL" failsafe_value="0"/>
<axis name="PITCH" failsafe_value="0"/>
</commands>
<rc_commands>
<set command="THROTTLE" value="@THROTTLE"/>
<set command="ROLL" value="@ROLL"/>
<set command="PITCH" value="@PITCH"/>
</rc_commands>
<section name="MIXER">
<define name="AILEVON_AILERON_RATE" value="0.75"/>
<define name="AILEVON_ELEVATOR_RATE" value="0.75"/>
<define name="AILERON_DIFF" value="0.5"/>
<define name="COMMAND_ROLL_TRIM" value="0"/>
<define name="COMMAND_PITCH_TRIM" value="718"/>
</section>
<command_laws>
<let var="aileron" value="@ROLL * AILEVON_AILERON_RATE"/>
<let var="elevator" value="@PITCH * AILEVON_ELEVATOR_RATE"/>
<set servo="MOTOR" value="@THROTTLE"/>
<set servo="AILEVON_LEFT" value="$elevator - ($aileron > 0 ? AILERON_DIFF : 1) * $aileron"/>
<set servo="AILEVON_RIGHT" value="$elevator + ($aileron > 0 ? 1 : AILERON_DIFF) * $aileron"/>
</command_laws>
<section name="AUTO1" prefix="AUTO1_">
<define name="MAX_ROLL" value="45." unit="deg"/>
<define name="MAX_PITCH" value="30." unit="deg"/>
</section>
<section name="IMU" prefix="IMU_">
<!-- Calibration Neutral -->
<define name="GYRO_P_NEUTRAL" value="0"/>
<define name="GYRO_Q_NEUTRAL" value="0"/>
<define name="GYRO_R_NEUTRAL" value="0 "/>
<define name="ACCEL_X_NEUTRAL" value="-36"/>
<define name="ACCEL_Y_NEUTRAL" value="26"/>
<define name="ACCEL_Z_NEUTRAL" value="7"/>
<define name="ACCEL_X_SENS" value="2.44787379999" integer="16"/>
<define name="ACCEL_Y_SENS" value="2.45127482156" integer="16"/>
<define name="ACCEL_Z_SENS" value="2.43752998117" integer="16"/>
<define name="MAG_X_SIGN" value="1"/>
<define name="MAG_Y_SIGN" value="-1"/>
<define name="MAG_Z_SIGN" value="-1"/>
<define name="MAG_X_NEUTRAL" value="27"/>
<define name="MAG_Y_NEUTRAL" value="-241"/>
<define name="MAG_Z_NEUTRAL" value="139"/>
<define name="MAG_X_SENS" value="3.89895537059" integer="16"/>
<define name="MAG_Y_SENS" value="3.96680514301" integer="16"/>
<define name="MAG_Z_SENS" value="4.60606895547" integer="16"/>
<define name="BODY_TO_IMU_PHI" value="-3.00000701874" unit="deg"/>
<define name="BODY_TO_IMU_THETA" value="3.00000701874" unit="deg"/>
<define name="BODY_TO_IMU_PSI" value="0" unit="deg"/>
</section>
<section name="INS" prefix="INS_">
<define name="H_X" value="0.5180"/>
<define name="H_Y" value="-0.0071"/>
<define name="H_Z" value="0.8554"/>
</section>
<section name="BAT">
<define name="CATASTROPHIC_BAT_LEVEL" value="9.3" unit="V"/>
<define name="MilliAmpereOfAdc(_adc)" value="(_adc-158)*16.5698"/>
</section>
<section name="MISC">
<define name="NOMINAL_AIRSPEED" value="15." unit="m/s"/>
<define name="CARROT" value="5." unit="s"/>
<define name="KILL_MODE_DISTANCE" value="(1.5*MAX_DIST_FROM_HOME)"/>
<define name="DEFAULT_CIRCLE_RADIUS" value="80."/>
<define name="UNLOCKED_HOME_MODE" value="TRUE"/>
</section>
<section name="VERTICAL CONTROL" prefix="V_CTL_">
<!--define name="POWER_CTL_BAT_NOMINAL" value="11.1" unit="volt"/-->
<!-- outer loop proportional gain -->
<define name="ALTITUDE_PGAIN" value="0.06"/>
<!-- outer loop saturation -->
<define name="ALTITUDE_MAX_CLIMB" value="3."/>
<!-- auto throttle inner loop -->
<define name="AUTO_THROTTLE_NOMINAL_CRUISE_THROTTLE" value="0.5"/>
<define name="AUTO_THROTTLE_MIN_CRUISE_THROTTLE" value="0.25"/>
<define name="AUTO_THROTTLE_MAX_CRUISE_THROTTLE" value="0.85"/>
<define name="AUTO_THROTTLE_LOITER_TRIM" value="1000"/>
<define name="AUTO_THROTTLE_DASH_TRIM" value="-1200"/>
<define name="AUTO_THROTTLE_CLIMB_THROTTLE_INCREMENT" value="0.08" unit="%/(m/s)"/>
<define name="AUTO_THROTTLE_PGAIN" value="0.011"/>
<define name="AUTO_THROTTLE_IGAIN" value="0.006"/>
<define name="AUTO_THROTTLE_PITCH_OF_VZ_PGAIN" value="0.13"/>
<define name="THROTTLE_SLEW" value="0.1"/>
<!-- TODO : CTRL_NEW "Climb loop (pitch)" -->
<define name="AUTO_PITCH_PGAIN" value="0.028"/>
<define name="AUTO_PITCH_DGAIN" value="0.013"/>
<define name="AUTO_PITCH_IGAIN" value="0.006"/>
<define name="AUTO_PITCH_MAX_PITCH" value="20" unit="deg"/>
<define name="AUTO_PITCH_MIN_PITCH" value="-20" unit="deg"/>
<define name="PITCH_TRIM" value="4.59999166346" unit="deg"/>
</section>
<section name="HORIZONTAL CONTROL" prefix="H_CTL_">
<define name="COURSE_PGAIN" value="0.58"/>
<define name="ROLL_MAX_SETPOINT" value="41.0000004297" unit="deg"/>
<define name="PITCH_MAX_SETPOINT" value="30." unit="deg"/>
<define name="PITCH_MIN_SETPOINT" value="-30." unit="deg"/>
<define name="ROLL_ATTITUDE_GAIN" value="10041"/>
<define name="ROLL_RATE_GAIN" value="1500"/>
<define name="PITCH_PGAIN" value="10672"/>
<define name="PITCH_DGAIN" value="1343"/>
<define name="AILERON_OF_THROTTLE" value="0.0"/>
<define name="PITCH_OF_ROLL" value="0.024"/>
</section>
<section name="FAILSAFE" prefix="FAILSAFE_">
<define name="DELAY_WITHOUT_GPS" value="2" unit="s"/>
<define name="DEFAULT_THROTTLE" value="0.3" unit="%"/>
<define name="DEFAULT_ROLL" value="10" unit="deg"/>
<define name="DEFAULT_PITCH" value="5" unit="deg"/>
<define name="HOME_RADIUS" value="100" unit="m"/>
</section>
<section name="SIMU">
<!--define name="ROLL_RESPONSE_FACTOR" value="10"/>
<define name="MAX_ROLL_DOT" value="20" unit="rad/s"/-->
</section>
</airframe>
conf/boards/apogee_1.0_chibios.makefile
+2 -3
View File
@@ -14,9 +14,8 @@ $(TARGET).ARCHDIR = $(ARCH)
RTOS=chibios
# FPU on F4
USE_FPU=yes
HARD_FLOAT=yes
## FPU on F4
USE_FPU=softfp
$(TARGET).CFLAGS += -DSTM32F4 -DPPRZLINK_ENABLE_FD -DUSE_HARD_FAULT_RECOVERY
conf/boards/chimera_1.0.makefile
+99
View File
@@ -0,0 +1,99 @@
# Hey Emacs, this is a -*- makefile -*-
#
# chimera_1.0.makefile
#
# based on STM32F7
# pre-version, only compatible with ChibiOS
#
BOARD=chimera
BOARD_VERSION=1.0
BOARD_DIR=$(BOARD)/chibios/v$(BOARD_VERSION)
BOARD_CFG=\"boards/$(BOARD_DIR)/$(BOARD).h\"
ARCH=chibios
$(TARGET).ARCHDIR = $(ARCH)
RTOS=chibios
MCU=cortex-m7
## FPU on F7
USE_FPU=softfp
USE_FPU_OPT= -mfpu=fpv5-d16
USE_LTO=yes
$(TARGET).CFLAGS += -DSTM32F7 -DPPRZLINK_ENABLE_FD -DUSE_HARD_FAULT_RECOVERY
##############################################################################
# Architecture or project specific options
#
# Define project name here (target)
PROJECT = $(TARGET)
# Project specific files and paths (see Makefile.chibios for details)
CHIBIOS_BOARD_PLATFORM = STM32F7xx/platform.mk
CHIBIOS_BOARD_PORT = ARMCMx/STM32F7xx/port.mk
CHIBIOS_BOARD_LINKER = STM32F76xxI.ld
CHIBIOS_BOARD_STARTUP = startup_stm32f7xx.mk
# ITCM flash is a special flash that allow faster operations
# At the moment it is not possible to flash the code in this mode using dfu-util
# but it should work with the BlackMagicProbe or STLINK
# By default, normal flash is used
ifeq ($(USE_ITCM),1)
$(TARGET).CFLAGS += -DUSE_ITCM=1
DFU_ADDR = 0x00200000
else
$(TARGET).CFLAGS += -DUSE_ITCM=0
DFU_ADDR = 0x08000000
endif
##############################################################################
# Compiler settings
#
# default flash mode is via usb dfu bootloader
# possibilities: DFU-UTIL, SWD, STLINK
FLASH_MODE ?= DFU-UTIL
HAS_LUFTBOOT = FALSE
#
# default LED configuration
#
RADIO_CONTROL_LED ?= 4
BARO_LED ?= none
AHRS_ALIGNER_LED ?= 2
GPS_LED ?= 3
SYS_TIME_LED ?= 1
#
# default UART configuration (modem, gps, spektrum)
#
MODEM_PORT ?= UART3
MODEM_BAUD ?= B57600
GPS_PORT ?= UART8
GPS_BAUD ?= B57600
RADIO_CONTROL_SPEKTRUM_PRIMARY_PORT ?= UART4
RADIO_CONTROL_SPEKTRUM_SECONDARY_PORT ?= UART7
# single mode
SBUS_PORT ?= UART7
# dual mode
SBUS1_PORT ?= UART7
SBUS2_PORT ?= UART4
#
# default actuator configuration
#
# you can use different actuators by adding a configure option to your firmware section
# e.g. <configure name="ACTUATORS" value="actuators_ppm/>
# and by setting the correct "driver" attribute in servo section
# e.g. <servo driver="Ppm">
#
ACTUATORS ?= actuators_pwm
conf/boards/lia_1.1_chibios.makefile
+1 -1
View File
@@ -38,4 +38,4 @@ GPS_BAUD ?= B38400
#
ACTUATORS ?= actuators_pwm
include $(PAPARAZZI_SRC)/conf/boards/lisa_m_common_chibios.makefile
include $(PAPARAZZI_HOME)/conf/boards/lisa_m_common_chibios.makefile
conf/boards/lisa_mx_2.1_chibios.makefile
+2 -3
View File
@@ -14,9 +14,8 @@ $(TARGET).ARCHDIR = $(ARCH)
RTOS=chibios
# FPU on F4
USE_FPU=yes
HARD_FLOAT=yes
## FPU on F4
USE_FPU=hard
$(TARGET).CFLAGS += -DSTM32F4 -DPPRZLINK_ENABLE_FD
conf/boards/px4fmu_2.4_chibios.makefile
+1 -2
View File
@@ -17,8 +17,7 @@ $(TARGET).ARCHDIR = $(ARCH)
RTOS=chibios
# FPU on F4
USE_FPU=yes
HARD_FLOAT=yes
USE_FPU=hard
$(TARGET).CFLAGS += -DSTM32F4 -DPPRZLINK_ENABLE_FD
conf/boards/vms_ecu_1.0_chibios.makefile
+1 -2
View File
@@ -15,8 +15,7 @@ $(TARGET).ARCHDIR = $(ARCH)
RTOS=chibios
# FPU on F4
USE_FPU=yes
HARD_FLOAT=yes
USE_FPU=hard
$(TARGET).CFLAGS += -DSTM32F4 -DPPRZLINK_ENABLE_FD
conf/chibios/chibios_rules.mk
+27 -17
View File
@@ -27,17 +27,21 @@ ifeq ($(USE_LTO),yes)
OPT += -flto
endif
# FPU-related options
ifeq ($(USE_FPU),yes)
ifeq ($(HARD_FLOAT),yes)
OPT += -mfloat-abi=hard -mfpu=fpv4-sp-d16 -fsingle-precision-constant
else
OPT += -mfloat-abi=softfp -mfpu=fpv4-sp-d16 -fsingle-precision-constant
# FPU options default (Cortex-M4 and Cortex-M7 single precision).
ifeq ($(USE_FPU_OPT),)
USE_FPU_OPT = -mfpu=fpv4-sp-d16 -fsingle-precision-constant
endif
DDEFS += -DCORTEX_USE_FPU=TRUE
# FPU-related options
ifeq ($(USE_FPU),)
USE_FPU = no
endif
ifneq ($(USE_FPU),no)
OPT += -mfloat-abi=$(USE_FPU) $(USE_FPU_OPT)
DDEFS += -DCORTEX_USE_FPU=TRUE
DADEFS += -DCORTEX_USE_FPU=TRUE
else
DDEFS += -DCORTEX_USE_FPU=FALSE
DDEFS += -DCORTEX_USE_FPU=FALSE
DADEFS += -DCORTEX_USE_FPU=FALSE
endif
@@ -80,8 +84,8 @@ else
ACSRC += $(CSRC)
ACPPSRC += $(CPPSRC)
endif
ASRC = $(ACSRC)$(ACPPSRC)
TSRC = $(TCSRC)$(TCPPSRC)
ASRC = $(ACSRC) $(ACPPSRC)
TSRC = $(TCSRC) $(TCPPSRC)
SRCPATHS = $(sort $(dir $(ASMXSRC)) $(dir $(ASMSRC)) $(dir $(ASRC)) $(dir $(TSRC)))
# Various directories
@@ -115,24 +119,27 @@ ASFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.s=.lst)) $(ADEFS)
ASXFLAGS = $(MCFLAGS) -Wa,-amhls=$(LSTDIR)/$(notdir $(<:.S=.lst)) $(ADEFS)
CFLAGS = $(MCFLAGS) $(OPT) $(COPT) $(CWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.c=.lst)) $(DEFS)
CPPFLAGS = $(MCFLAGS) $(OPT) $(CPPOPT) $(CPPWARN) -Wa,-alms=$(LSTDIR)/$(notdir $(<:.cpp=.lst)) $(DEFS)
LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH),--script=$(LDSCRIPT)$(LDOPT)
LDFLAGS = $(MCFLAGS) $(OPT) -nostartfiles $(LLIBDIR) -Wl,-Map=$(BUILDDIR)/$(PROJECT).map,--cref,--no-warn-mismatch,--library-path=$(RULESPATH)/ld,--script=$(LDSCRIPT)$(LDOPT)
# Thumb interwork enabled only if needed because it kills performance.
ifneq ($(TSRC),)
ifneq ($(strip $(TSRC)),)
CFLAGS += -DTHUMB_PRESENT
CPPFLAGS += -DTHUMB_PRESENT
ASFLAGS += -DTHUMB_PRESENT
ifneq ($(ASRC),)
ASXFLAGS += -DTHUMB_PRESENT
ifneq ($(strip $(ASRC)),)
# Mixed ARM and THUMB mode.
CFLAGS += -mthumb-interwork
CPPFLAGS += -mthumb-interwork
ASFLAGS += -mthumb-interwork
ASXFLAGS += -mthumb-interwork
LDFLAGS += -mthumb-interwork
else
# Pure THUMB mode, THUMB C code cannot be called by ARM asm code directly.
CFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING
CPPFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING
ASFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb
ASXFLAGS += -mno-thumb-interwork -DTHUMB_NO_INTERWORKING -mthumb
LDFLAGS += -mno-thumb-interwork -mthumb
endif
else
@@ -140,11 +147,13 @@ else
CFLAGS += -mno-thumb-interwork
CPPFLAGS += -mno-thumb-interwork
ASFLAGS += -mno-thumb-interwork
ASXFLAGS += -mno-thumb-interwork
LDFLAGS += -mno-thumb-interwork
endif
# Generate dependency information
ASFLAGS += -MD -MP -MF $(BUILDDIR)/.dep/$(@F).d
ASXFLAGS += -MD -MP -MF $(BUILDDIR)/.dep/$(@F).d
CFLAGS += -MD -MP -MF $(BUILDDIR)/.dep/$(@F).d
CPPFLAGS += -MD -MP -MF $(BUILDDIR)/.dep/$(@F).d
@@ -239,6 +248,7 @@ else
endif
%.elf: $(OBJS) $(LDSCRIPT)
#$(BUILDDIR)/$(PROJECT).elf: $(OBJS) $(LDSCRIPT)
ifeq ($(USE_VERBOSE_COMPILE),yes)
@echo
$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
@@ -247,7 +257,7 @@ else
@$(LD) $(OBJS) $(LDFLAGS) $(LIBS) -o $@
endif
%.hex: %.elf $(LDSCRIPT)
%.hex: %.elf
ifeq ($(USE_VERBOSE_COMPILE),yes)
$(HEX) $< $@
else
@@ -255,7 +265,7 @@ else
@$(HEX) $< $@
endif
%.bin: %.elf $(LDSCRIPT)
%.bin: %.elf
ifeq ($(USE_VERBOSE_COMPILE),yes)
$(BIN) $< $@
else
@@ -263,7 +273,7 @@ else
@$(BIN) $< $@
endif
%.srec: %.elf $(LDSCRIPT)
%.srec: %.elf
ifeq ($(USE_VERBOSE_COMPILE),yes)
$(SREC) $< $@
else
@@ -271,7 +281,7 @@ else
@$(SREC) $< $@
endif
%.dmp: %.elf $(LDSCRIPT)
%.dmp: %.elf
ifeq ($(USE_VERBOSE_COMPILE),yes)
$(OD) $(ODFLAGS) $< > $@
$(SZ) $<
conf/firmwares/subsystems/shared/baro_board.makefile
+9
View File
@@ -247,6 +247,15 @@ else ifeq ($(BOARD), openpilot_revo)
BARO_BOARD_SRCS += peripherals/ms5611_i2c.c
BARO_BOARD_SRCS += boards/baro_board_ms5611_i2c.c
else ifeq ($(BOARD), chimera)
BARO_BOARD_CFLAGS += -DBARO_BOARD=BARO_MS5611_I2C
BARO_BOARD_CFLAGS += -DUSE_I2C1
BARO_BOARD_CFLAGS += -DBB_MS5611_I2C_DEV=i2c1
BARO_BOARD_CFLAGS += -DBB_MS5611_SLAVE_ADDR=MS5611_I2C_SLAVE_ADDR_ALT
BARO_BOARD_SRCS += peripherals/ms5611.c
BARO_BOARD_SRCS += peripherals/ms5611_i2c.c
BARO_BOARD_SRCS += boards/baro_board_ms5611_i2c.c
endif # check board
BARO_LED ?= none
conf/flash_modes.xml
+3
View File
@@ -59,6 +59,7 @@
<board name="navstik_.*"/>
<board name="elle*"/>
<board name="openpilot_revo.*"/>
<board name="chimera_.*"/>
</boards>
</mode>
<mode name="STLink (SWD)">
@@ -71,6 +72,7 @@
<board name="elle*"/>
<board name="naze32*"/>
<board name="openpilot_revo.*"/>
<board name="chimera_.*"/>
</boards>
</mode>
<mode name="BlackMagic Probe (SWD)">
@@ -88,6 +90,7 @@
<board name="cjmcu*"/>
<board name="openpilot_revo.*"/>
<board name="lia_.*"/>
<board name="chimera_.*"/>
<board name="vms_ecu_.*"/>
</boards>
</mode>
conf/modules/imu_chimera.xml
+20
View File
@@ -0,0 +1,20 @@
<!DOCTYPE module SYSTEM "module.dtd">
<module name="imu_chimera" dir="imu">
<doc>
<description>
MPU9250 IMU via SPI.
Basically the same as imu_mpu9250_spi, only changed axes assignment for Chimera.
</description>
</doc>
<autoload name="imu_mpu9250_i2c"/>
<makefile target="!sim|nps|fbw">
<configure name="IMU_MPU9250_I2C_DEV" value="i2c1" case="upper|lower"/>
<define name="IMU_MPU9250_CHAN_X" value="1"/>
<define name="IMU_MPU9250_CHAN_Y" value="0"/>
<define name="IMU_MPU9250_CHAN_Z" value="2"/>
<define name="IMU_MPU9250_X_SIGN" value="-1"/>
<define name="IMU_MPU9250_Y_SIGN" value="-1"/>
<define name="IMU_MPU9250_Z_SIGN" value="-1"/>
</makefile>
</module>
sw/airborne/arch/chibios/chconf.h
+61 -6
View File
@@ -25,8 +25,10 @@
* @{
*/
#ifndef _CHCONF_H_
#define _CHCONF_H_
#ifndef CHCONF_H
#define CHCONF_H
#define _CHIBIOS_RT_CONF_
/*===========================================================================*/
/**
@@ -368,11 +370,16 @@
* @details If enabled then the context switch circular trace buffer is
* activated.
*
* @note The default is @p FALSE.
* @note The default is @p CH_DBG_TRACE_MASK_DISABLED.
*/
#if !defined(CH_DBG_ENABLE_TRACE)
#define CH_DBG_ENABLE_TRACE FALSE
#endif
#define CH_DBG_TRACE_MASK CH_DBG_TRACE_MASK_DISABLED
/**
* @brief Trace buffer entries.
* @note The trace buffer is only allocated if @p CH_DBG_TRACE_MASK is
* different from @p CH_DBG_TRACE_MASK_DISABLED.
*/
#define CH_DBG_TRACE_BUFFER_SIZE 128
/**
* @brief Debug option, stack checks.
@@ -460,6 +467,20 @@
/* Context switch code here.*/ \
}
/**
* @brief ISR enter hook.
*/
#define CH_CFG_IRQ_PROLOGUE_HOOK() { \
/* IRQ prologue code here.*/ \
}
/**
* @brief ISR exit hook.
*/
#define CH_CFG_IRQ_EPILOGUE_HOOK() { \
/* IRQ epilogue code here.*/ \
}
/**
* @brief Idle thread enter hook.
* @note This hook is invoked within a critical zone, no OS functions
@@ -467,6 +488,7 @@
* @note This macro can be used to activate a power saving mode.
*/
#define CH_CFG_IDLE_ENTER_HOOK() { \
/* Idle-enter code here.*/ \
}
/**
@@ -476,6 +498,7 @@
* @note This macro can be used to deactivate a power saving mode.
*/
#define CH_CFG_IDLE_LEAVE_HOOK() { \
/* Idle-leave code here.*/ \
}
/**
@@ -504,12 +527,44 @@
/* System halt code here.*/ \
}
/**
* @brief Trace hook.
* @details This hook is invoked each time a new record is written in the
* trace buffer.
*/
#define CH_CFG_TRACE_HOOK(tep) { \
/* Trace code here.*/ \
}
/** @} */
/*===========================================================================*/
/* Port-specific settings (override port settings defaulted in chcore.h). */
/*===========================================================================*/
#ifndef CORTEX_VTOR_INIT // try to find the correct init address if not defined
#if USE_ITCM // point to correct interrupt vector when using ITCM flash on F7
#define CORTEX_VTOR_INIT 0x00200000U
#elif LUFTBOOT // using LUFTBOOT bootloader
#if defined STM32F4
#define CORTEX_VTOR_INIT 0x00004000U
#else
#define CORTEX_VTOR_INIT 0x00002000U
#endif
#else // default value
#define CORTEX_VTOR_INIT 0x08000000U
#endif
#endif // CORTEX_VTOR_INIT
// allow float for the ChibiOS print function (used with logger)
#define CHPRINTF_USE_FLOAT 1
#endif /* _CHCONF_H_ */
/** @} */
sw/airborne/arch/chibios/halconf.h
+69 -1
View File
@@ -1,5 +1,5 @@
/*
ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
modified by: AggieAir, A Remote Sensing Unmanned Aerial System for Scientific Applications
Utah State University, http://aggieair.usu.edu/
@@ -7,6 +7,8 @@
Michal Podhradsky (michal.podhradsky@aggiemail.usu.edu)
Calvin Coopmans (c.r.coopmans@ieee.org)
modified by Gautier Hattenberger for STM32F7 support
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
@@ -125,7 +127,11 @@
* ifdef RADIO_CONTROL_TYPE_PPM then TRUE, otherwise FALSE
*/
#if !defined(HAL_USE_ICU) || defined(__DOXYGEN__)
#if RADIO_CONTROL_TYPE_PPM || USE_PWM_INPUT || defined USE_PWM_INPUT1 || defined USE_PWM_INPUT2
#define HAL_USE_ICU TRUE
#else
#define HAL_USE_ICU FALSE
#endif
#endif
/**
@@ -214,6 +220,13 @@
#endif
#endif
/**
* @brief Enables the WDG subsystem.
*/
#if !defined(HAL_USE_WDG) || defined(__DOXYGEN__)
#define HAL_USE_WDG FALSE
#endif
/*===========================================================================*/
/* ADC driver related settings. */
/*===========================================================================*/
@@ -345,6 +358,29 @@
#define SERIAL_BUFFERS_SIZE 1024
#endif
/*===========================================================================*/
/* SERIAL_USB driver related setting. */
/*===========================================================================*/
/**
* @brief Serial over USB buffers size.
* @details Configuration parameter, the buffer size must be a multiple of
* the USB data endpoint maximum packet size.
* @note The default is 256 bytes for both the transmission and receive
* buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_SIZE) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_SIZE 256
#endif
/**
* @brief Serial over USB number of buffers.
* @note The default is 2 buffers.
*/
#if !defined(SERIAL_USB_BUFFERS_NUMBER) || defined(__DOXYGEN__)
#define SERIAL_USB_BUFFERS_NUMBER 2
#endif
/*===========================================================================*/
/* SPI driver related settings. */
/*===========================================================================*/
@@ -365,6 +401,38 @@
#define SPI_USE_MUTUAL_EXCLUSION TRUE
#endif
/*===========================================================================*/
/* UART driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_WAIT) || defined(__DOXYGEN__)
#define UART_USE_WAIT FALSE
#endif
/**
* @brief Enables the @p uartAcquireBus() and @p uartReleaseBus() APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(UART_USE_MUTUAL_EXCLUSION) || defined(__DOXYGEN__)
#define UART_USE_MUTUAL_EXCLUSION FALSE
#endif
/*===========================================================================*/
/* USB driver related settings. */
/*===========================================================================*/
/**
* @brief Enables synchronous APIs.
* @note Disabling this option saves both code and data space.
*/
#if !defined(USB_USE_WAIT) || defined(__DOXYGEN__)
#define USB_USE_WAIT FALSE
#endif
#endif /* _HALCONF_H_ */
/** @} */
sw/airborne/arch/chibios/led_hw.h
+1
View File
@@ -35,6 +35,7 @@
*/
#include "hal.h"
#include "mcu_periph/gpio_def.h"
#include BOARD_CONFIG
/*
* Regular GPIO driven LEDs
sw/airborne/arch/chibios/mcu_arch.c
+19 -5
View File
@@ -41,7 +41,7 @@
#if USE_HARD_FAULT_RECOVERY
#ifdef STM32F4
#if defined STM32F4 || defined STM32F7
#define BCKP_SECTION ".ram5"
#define IN_BCKP_SECTION(var) var __attribute__ ((section(BCKP_SECTION), aligned(8)))
#else
@@ -85,6 +85,20 @@ CH_IRQ_HANDLER(UsageFault_Handler)
}
bool recovering_from_hard_fault;
// select correct register
#if defined STM32F4
#define __PWR_CSR PWR->CSR
#define __PWR_CSR_BRE PWR_CSR_BRE
#define __PWR_CSR_BRR PWR_CSR_BRR
#elif defined STM32F7
#define __PWR_CSR PWR->CSR1
#define __PWR_CSR_BRE PWR_CSR1_BRE
#define __PWR_CSR_BRR PWR_CSR1_BRR
#else
#error Hard fault recovery not supported
#endif
#endif
@@ -111,11 +125,11 @@ void mcu_arch_init(void)
#if USE_HARD_FAULT_RECOVERY
/* Backup domain SRAM enable, and with it, the regulator */
#if STM32F4
#if defined STM32F4 || defined STM32F7
RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN;
PWR->CSR |= PWR_CSR_BRE;
while ((PWR->CSR & PWR_CSR_BRR) == 0) ; /* Waits until the regulator is stable */
#endif /* STM32F4 */
__PWR_CSR |= __PWR_CSR_BRE;
while ((__PWR_CSR & __PWR_CSR_BRR) == 0) ; /* Waits until the regulator is stable */
#endif /* STM32F4 | STM32F7*/
// test if last reset was a 'real' hard fault
recovering_from_hard_fault = false;
sw/airborne/arch/chibios/mcu_arch.h
+46 -2
View File
@@ -27,8 +27,6 @@
* @file arch/chibios/mcu_arch.h
* Microcontroller initialization function for ChibiOS
*
* ChibiOS initialized peripherals by itself, hence empty
* functions for Paparazzi compatibility.
*/
#ifndef CHIBIOS_MCU_ARCH_H
#define CHIBIOS_MCU_ARCH_H
@@ -44,4 +42,50 @@ extern void mcu_arch_init(void);
extern bool recovering_from_hard_fault;
#endif
#include <ch.h>
/** Put MCU into deep sleep mode
*
* This can be used when closing the SD log files
* right after a power down to save the remaining
* energy for the SD card internal MCU
*
* Never call this during flight!
*/
static inline void mcu_deep_sleep(void)
{
#if defined STM32F4
/* clear PDDS and LPDS bits */
PWR->CR &= ~(PWR_CR_PDDS | PWR_CR_LPDS);
/* set LPDS and clear */
PWR->CR |= (PWR_CR_LPDS | PWR_CR_CSBF | PWR_CR_CWUF);
#elif defined STM32F7
/* clear PDDS and LPDS bits */
PWR->CR1 &= ~(PWR_CR1_PDDS | PWR_CR1_LPDS);
/* set LPDS and clear */
PWR->CR1 |= (PWR_CR1_LPDS | PWR_CR1_CSBF);
#endif
/* Setup the deepsleep mask */
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
__disable_irq();
__SEV();
__WFE();
__WFE();
__enable_irq();
/* clear the deepsleep mask */
SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk;
}
/** Request a software reset of the MCU
*/
static inline void mcu_reset(void)
{
NVIC_SystemReset();
}
#endif /* CHIBIOS_MCU_ARCH_H */
sw/airborne/arch/chibios/mcu_periph/adc_arch.c
+5 -4
View File
@@ -54,6 +54,7 @@
#include "mcu_periph/gpio.h"
#include "hal.h"
#include "std.h"
#include "mcu_periph/ram_arch.h"
// Macros to automatically enable the correct ADC
@@ -70,11 +71,11 @@
// STM32F1xx
#define ADC_SAMPLE_RATE ADC_SAMPLE_41P5
#define ADC_CR2_CFG ADC_CR2_TSVREFE
#elif defined(__STM32F4xx_H)
// STM32F4xx
#elif defined(__STM32F4xx_H) || defined(__STM32F7xx_H)
// STM32F4xx | STM32F7xx
#define ADC_SAMPLE_RATE ADC_SAMPLE_480
#define ADC_CR2_CFG ADC_CR2_SWSTART
#endif // STM32F1xx vs STM32F4xx
#endif
// Create channel map
@@ -137,7 +138,7 @@ ADCDriver *adcp_err = NULL;
#ifndef ADC_BUF_DEPTH
#define ADC_BUF_DEPTH (MAX_AV_NB_SAMPLE/2)
#endif
static adcsample_t adc_samples[ADC_NUM_CHANNELS * ADC_BUF_DEPTH];
static IN_DMA_SECTION(adcsample_t adc_samples[ADC_NUM_CHANNELS * ADC_BUF_DEPTH]);
#if USE_AD1
static struct adc_buf *adc1_buffers[ADC_NUM_CHANNELS];
sw/airborne/arch/chibios/mcu_periph/gpio_arch.c
+13 -6
View File
@@ -58,7 +58,7 @@ void gpio_setup_input_pulldown(ioportid_t port, uint16_t gpios)
chSysUnlock();
}
void gpio_setup_pin_af(ioportid_t port, uint16_t pin, uint8_t af)
void gpio_setup_pin_af(ioportid_t port, uint16_t pin, uint8_t af, bool is_output)
{
chSysLock();
// architecture dependent settings
@@ -68,11 +68,18 @@ void gpio_setup_pin_af(ioportid_t port, uint16_t pin, uint8_t af)
(void)port;
(void)pin;
(void)af;
#elif defined(__STM32F4xx_H)
// STM32F4xx
palSetPadMode(port, pin, PAL_MODE_ALTERNATE(af));
#endif // STM32F1xx vs STM32F4xx
#elif defined(__STM32F4xx_H) || defined(__STM32F7xx_H)
// STM32F4xx and STM32F7xx
if (af) {
palSetPadMode(port, pin, PAL_MODE_ALTERNATE(af));
} else {
if (is_output) {
palSetPadMode(port, pin, PAL_MODE_OUTPUT_PUSHPULL);
} else {
palSetPadMode(port, pin, PAL_MODE_INPUT);
}
}
#endif
chSysUnlock();
}
sw/airborne/arch/chibios/mcu_periph/gpio_arch.h
+7 -2
View File
@@ -30,9 +30,14 @@
#ifndef GPIO_ARCH_H
#define GPIO_ARCH_H
#include "hal.h"
#include <hal.h>
#include "mcu_periph/gpio_def.h"
/**
* Abstract gpio port type for hardware independent part
*/
typedef ioportid_t gpio_port_t;
/**
* Setup one or more pins of the given GPIO port as outputs.
* @param[in] port
@@ -65,7 +70,7 @@ extern void gpio_setup_input_pulldown(ioportid_t port, uint16_t gpios);
* Setup a gpio for input or output with alternate function.
* This is an STM32 specific helper funtion and should only be used in stm32 code.
*/
extern void gpio_setup_pin_af(ioportid_t port, uint16_t pin, uint8_t af);
extern void gpio_setup_pin_af(ioportid_t port, uint16_t pin, uint8_t af, bool is_output);
/**
* Setup a gpio for analog use.
sw/airborne/arch/chibios/mcu_periph/i2c_arch.c
+59
View File
@@ -38,6 +38,9 @@
#include <ch.h>
#include <hal.h>
#include "mcu_periph/ram_arch.h"
#include "string.h"
#if USE_I2C1 || USE_I2C2 || USE_I2C3
@@ -45,6 +48,9 @@
struct i2c_init {
semaphore_t *sem;
I2CConfig *cfg;
#ifdef STM32F7
uint8_t *dma_buf;
#endif
};
@@ -78,18 +84,41 @@ static void handle_i2c_thd(struct i2c_periph *p)
msg_t status;
// submit i2c transaction (R/W or R only depending of len_w)
if (t->len_w > 0) {
#if defined STM32F7
// we do stupid mem copy because F7 needs a special RAM for DMA operation
memcpy(i->dma_buf, (void*)t->buf, (size_t)(t->len_w));
status = i2cMasterTransmitTimeout(
(I2CDriver*)p->reg_addr,
(i2caddr_t)((t->slave_addr)>>1),
(uint8_t*)i->dma_buf, (size_t)(t->len_w),
(uint8_t*)i->dma_buf, (size_t)(t->len_r),
tmo);
memcpy((void*)t->buf, i->dma_buf, (size_t)(t->len_r));
#else
status = i2cMasterTransmitTimeout(
(I2CDriver*)p->reg_addr,
(i2caddr_t)((t->slave_addr)>>1),
(uint8_t*)t->buf, (size_t)(t->len_w),
(uint8_t*)t->buf, (size_t)(t->len_r),
tmo);
#endif
} else {
#if defined STM32F7
// we do stupid mem copy because F7 needs a special RAM for DMA operation
memcpy(i->dma_buf, (void*)t->buf, (size_t)(t->len_w));
status = i2cMasterReceiveTimeout(
(I2CDriver*)p->reg_addr,
(i2caddr_t)((t->slave_addr)>>1),
(uint8_t*)i->dma_buf, (size_t)(t->len_r),
tmo);
memcpy((void*)t->buf, i->dma_buf, (size_t)(t->len_r));
#else
status = i2cMasterReceiveTimeout(
(I2CDriver*)p->reg_addr,
(i2caddr_t)((t->slave_addr)>>1),
(uint8_t*)t->buf, (size_t)(t->len_r),
tmo);
#endif
}
chSysLock();
@@ -151,10 +180,20 @@ static void handle_i2c_thd(struct i2c_periph *p)
PRINT_CONFIG_VAR(I2C1_CLOCK_SPEED)
static SEMAPHORE_DECL(i2c1_sem, 0);
static I2CConfig i2cfg1 = I2C1_CFG_DEF;
#if defined STM32F7
// We need a special buffer for DMA operations
static IN_DMA_SECTION(uint8_t i2c1_dma_buf[I2C_BUF_LEN]);
static struct i2c_init i2c1_init_s = {
.sem = &i2c1_sem,
.cfg = &i2cfg1,
.dma_buf = i2c1_dma_buf
};
#else
static struct i2c_init i2c1_init_s = {
.sem = &i2c1_sem,
.cfg = &i2cfg1
};
#endif
// Errors
struct i2c_errors i2c1_errors;
// Thread
@@ -195,10 +234,20 @@ static void thd_i2c1(void *arg)
PRINT_CONFIG_VAR(I2C2_CLOCK_SPEED)
static SEMAPHORE_DECL(i2c2_sem, 0);
static I2CConfig i2cfg2 = I2C2_CFG_DEF;
#if defined STM32F7
// We need a special buffer for DMA operations
static IN_DMA_SECTION(uint8_t i2c2_dma_buf[I2C_BUF_LEN]);
static struct i2c_init i2c2_init_s = {
.sem = &i2c2_sem,
.cfg = &i2cfg2,
.dma_buf = i2c2_dma_buf
};
#else
static struct i2c_init i2c2_init_s = {
.sem = &i2c2_sem,
.cfg = &i2cfg2
};
#endif
// Errors
struct i2c_errors i2c2_errors;
// Thread
@@ -240,10 +289,20 @@ static void thd_i2c2(void *arg)
PRINT_CONFIG_VAR(I2C3_CLOCK_SPEED)
static SEMAPHORE_DECL(i2c3_sem, 0);
static I2CConfig i2cfg3 = I2C3_CFG_DEF;
#if defined STM32F7
// We need a special buffer for DMA operations
static IN_DMA_SECTION(uint8_t i2c3_dma_buf[I2C_BUF_LEN]);
static struct i2c_init i2c3_init_s = {
.sem = &i2c3_sem,
.cfg = &i2cfg3,
.dma_buf = i2c3_dma_buf
};
#else
static struct i2c_init i2c3_init_s = {
.sem = &i2c3_sem,
.cfg = &i2cfg3
};
#endif
// Errors
struct i2c_errors i2c3_errors;
// Thread
sw/airborne/arch/chibios/mcu_periph/pwm_input_arch.c
+6 -6
View File
@@ -34,12 +34,12 @@
#ifdef USE_PWM_INPUT1
static void input1_period_cb(ICUDriver *icup) {
pwm_input_period_tics[PWM_INPUT1] = icuGetPeriodX(icup);
pwm_input_period_valid[PWM_INPUT1] = TRUE;
pwm_input_period_valid[PWM_INPUT1] = true;
}
static void input1_width_cb(ICUDriver *icup) {
pwm_input_duty_tics[PWM_INPUT1] = icuGetWidthX(icup);
pwm_input_duty_valid[PWM_INPUT1] = TRUE;
pwm_input_duty_valid[PWM_INPUT1] = true;
}
static ICUConfig pwm_input1_cfg = {
@@ -62,12 +62,12 @@ static ICUConfig pwm_input1_cfg = {
#ifdef USE_PWM_INPUT2
static void input2_period_cb(ICUDriver *icup) {
pwm_input_period_tics[PWM_INPUT2] = icuGetPeriodX(icup);
pwm_input_period_valid[PWM_INPUT2] = TRUE;
pwm_input_period_valid[PWM_INPUT2] = true;
}
static void input2_width_cb(ICUDriver *icup) {
pwm_input_duty_tics[PWM_INPUT2] = icuGetWidthX(icup);
pwm_input_duty_valid[PWM_INPUT2] = TRUE;
pwm_input_duty_valid[PWM_INPUT2] = true;
}
static ICUConfig pwm_input2_cfg = {
@@ -100,14 +100,14 @@ void pwm_input_init(void)
#ifdef USE_PWM_INPUT1
icuStart(&PWM_INPUT1_ICU, &pwm_input1_cfg);
gpio_setup_pin_af(PWM_INPUT1_GPIO_PORT, PWM_INPUT1_GPIO_PIN, PWM_INPUT1_GPIO_AF);
gpio_setup_pin_af(PWM_INPUT1_GPIO_PORT, PWM_INPUT1_GPIO_PIN, PWM_INPUT1_GPIO_AF, false);
icuStartCapture(&PWM_INPUT1_ICU);
icuEnableNotifications(&PWM_INPUT1_ICU);
#endif
#ifdef USE_PWM_INPUT2
icuStart(&PWM_INPUT2_ICU, &pwm_input2_cfg);
gpio_setup_pin_af(PWM_INPUT2_GPIO_PORT, PWM_INPUT2_GPIO_PIN, PWM_INPUT2_GPIO_AF);
gpio_setup_pin_af(PWM_INPUT2_GPIO_PORT, PWM_INPUT2_GPIO_PIN, PWM_INPUT2_GPIO_AF, false);
icuStartCapture(&PWM_INPUT2_ICU);
icuEnableNotifications(&PWM_INPUT2_ICU);
#endif
sw/airborne/arch/chibios/mcu_periph/ram_arch.h
+62
View File
@@ -0,0 +1,62 @@
/*
* Copyright (C) 2016 Gautier Hattenberger and Alexandre Bustico
*
* This file is part of paparazzi.
*
* paparazzi is free software; you can redistribute it and/or modify
* it under the terms of the GNU General Public License as published by
* the Free Software Foundation; either version 2, or (at your option)
* any later version.
*
* paparazzi is distributed in the hope that it will be useful,
* but WITHOUT ANY WARRANTY; without even the implied warranty of
* MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the
* GNU General Public License for more details.
*
* You should have received a copy of the GNU General Public License
* along with paparazzi; see the file COPYING. If not, see
* <http://www.gnu.org/licenses/>.
*/
/**
* @file arch/chibios/mcu_periph/ram_arch.h
*
* Specific RAM section for DMA usage on F7
*
* F1
* ram0: 64ko std
*
* F4
* ram4: 64ko ccm, fast, no dma
* ram0: 128Ko std
*
* F7
* ram0: std, fast, no dma
* ram3: dma
*/
#ifndef RAM_ARCH_H
#define RAM_ARCH_H
#if defined STM32F1
#define STD_SECTION ".ram0"
#define FAST_SECTION ".ram0"
#define DMA_SECTION ".ram0"
#elif defined STM32F4
#define STD_SECTION ".ram0"
#define FAST_SECTION ".ram4"
#define DMA_SECTION ".ram0"
#elif defined STM32F7
#define STD_SECTION ".ram0"
#define FAST_SECTION ".ram0"
#define DMA_SECTION ".ram3"
#else
#error "section defined only for STM32F1, STM32F4 and STM32F7"
#endif
#define IN_STD_SECTION(var) var __attribute__ ((section(STD_SECTION), aligned(8)))
#define IN_FAST_SECTION(var) var __attribute__ ((section(FAST_SECTION), aligned(8)))
#define IN_DMA_SECTION(var) var __attribute__ ((section(DMA_SECTION), aligned(8)))
#endif
sw/airborne/arch/chibios/mcu_periph/sdio_arch.c
+10 -8
View File
@@ -38,6 +38,8 @@
#include <hal.h>
#include "mcu_periph/sdio.h"
#include <stdarg.h>
#include "mcu_periph/gpio.h"
#include BOARD_CONFIG
static enum {STOP, CONNECT} cnxState = STOP;
@@ -56,17 +58,17 @@ bool sdio_connect(void)
/*
* Initializes the SDIO drivers.
*
* FIXME hardcoded for Apogee board ?
* FIXME This could be hardcoded in board file ?
*/
const uint32_t mode = PAL_MODE_ALTERNATE(12) | PAL_STM32_OTYPE_PUSHPULL |
const uint32_t mode = PAL_MODE_ALTERNATE(SDIO_AF) | PAL_STM32_OTYPE_PUSHPULL |
PAL_STM32_OSPEED_HIGHEST | PAL_STM32_PUPDR_FLOATING | PAL_STM32_MODE_ALTERNATE;
palSetPadMode (GPIOC, GPIOC_SDIO_D0, mode | PAL_STM32_PUPDR_PULLUP);
palSetPadMode (GPIOC, GPIOC_SDIO_D1, mode | PAL_STM32_PUPDR_PULLUP);
palSetPadMode (GPIOC, GPIOC_SDIO_D2, mode | PAL_STM32_PUPDR_PULLUP);
palSetPadMode (GPIOC, GPIOC_SDIO_D3, mode | PAL_STM32_PUPDR_PULLUP);
palSetPadMode (GPIOC, GPIOC_SDIO_CK, mode);
palSetPadMode (GPIOD, GPIOD_SDIO_CMD, mode | PAL_STM32_PUPDR_PULLUP);
palSetPadMode (SDIO_D0_PORT, SDIO_D0_PIN, mode | PAL_STM32_PUPDR_PULLUP);
palSetPadMode (SDIO_D1_PORT, SDIO_D1_PIN, mode | PAL_STM32_PUPDR_PULLUP);
palSetPadMode (SDIO_D2_PORT, SDIO_D2_PIN, mode | PAL_STM32_PUPDR_PULLUP);
palSetPadMode (SDIO_D3_PORT, SDIO_D3_PIN, mode | PAL_STM32_PUPDR_PULLUP);
palSetPadMode (SDIO_CK_PORT, SDIO_CK_PIN, mode);
palSetPadMode (SDIO_CMD_PORT, SDIO_CMD_PIN, mode | PAL_STM32_PUPDR_PULLUP);
// palSetPadMode (GPIOD, GPIOD_SDIO_CMD, mode);
chThdSleepMilliseconds(100);
sw/airborne/arch/chibios/mcu_periph/spi_arch.c
+104 -10
View File
@@ -31,6 +31,9 @@
#include "mcu_periph/spi.h"
#include "mcu_periph/gpio.h"
#include <string.h>
#include "mcu_periph/ram_arch.h"
#if SPI_SLAVE
#error "ChibiOS operates only in SPI_MASTER mode"
#endif
@@ -39,6 +42,16 @@
#error "ChibiOS architectures don't have SPI0"
#endif
// private SPI init structure
struct spi_init {
semaphore_t *sem;
#ifdef STM32F7
uint8_t *dma_buf_out;
uint8_t *dma_buf_in;
#endif
};
#define SPI_DMA_BUF_LEN 512 // it has to be big enough
/**
* Resolve slave port
*
@@ -140,15 +153,15 @@ static inline uint16_t spi_resolve_slave_pin(uint8_t slave)
* SPIx_CR1 register.
*
* This function is currently architecture dependent (for STM32F1xx
* and STM32F4xx only)
* STM32F4xx and STM32F7xx only)
* TODO: extend for other architectures too
*
* @param[in] t pointer to a @p spi_transaction struct
*/
static inline uint16_t spi_resolve_CR1(struct spi_transaction *t)
static inline uint16_t spi_resolve_CR1(struct spi_transaction *t __attribute__((unused)))
{
uint16_t CR1 = 0;
#if defined(__STM32F10x_H) || defined(__STM32F105xC_H) || defined (__STM32F107xC_H) || defined(__STM32F4xx_H)
#if defined(STM32F1) || defined(STM32F4) || defined(STM32F7)
if (t->dss == SPIDss16bit) {
CR1 |= SPI_CR1_DFF;
}
@@ -189,10 +202,36 @@ static inline uint16_t spi_resolve_CR1(struct spi_transaction *t)
default:
break;
}
#endif /* __STM32F10x_H || __STM32F105xC_H || __STM32F107xC_H || STM32F4xx_H */
#endif /* STM32F1 || STM32F4 || STM32F7 */
return CR1;
}
/**
* Resolve CR2
*
* Given the transaction settings, returns the right configuration of
* SPIx_CR2 register.
*
* This function is currently architecture dependent (for STM32F1xx
* STM32F4xx and STM32F7xx only)
* TODO: extend for other architectures too
*
* @param[in] t pointer to a @p spi_transaction struct
*/
static inline uint16_t spi_resolve_CR2(struct spi_transaction *t __attribute__((unused)))
{
uint16_t CR2 = 0;
#if defined(STM32F7)
if (t->dss == SPIDss16bit) {
CR2 |= SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2 | SPI_CR2_DS_3;
}
else {
CR2 |= SPI_CR2_DS_0 | SPI_CR2_DS_1 | SPI_CR2_DS_2;
}
#endif /* STM32F7 */
return CR2;
}
/**
* main thread function
*
@@ -200,8 +239,10 @@ static inline uint16_t spi_resolve_CR1(struct spi_transaction *t)
*/
static void handle_spi_thd(struct spi_periph *p)
{
struct spi_init *i = (struct spi_init *) p->init_struct;
// wait for a transaction to be pushed in the queue
chSemWait ((semaphore_t *) p->init_struct);
chSemWait (i->sem);
if ((p->trans_insert_idx == p->trans_extract_idx) || p->suspend) {
p->status = SPIIdle;
@@ -218,7 +259,8 @@ static void handle_spi_thd(struct spi_periph *p)
NULL, // no callback
spi_resolve_slave_port(t->slave_idx),
spi_resolve_slave_pin(t->slave_idx),
spi_resolve_CR1(t)
spi_resolve_CR1(t),
spi_resolve_CR2(t)
};
// find max transaction length
@@ -240,7 +282,14 @@ static void handle_spi_thd(struct spi_periph *p)
}
// Start synchronous data transfer
#if defined STM32F7
// we do stupid mem copy because F7 needs a special RAM for DMA operation
memcpy(i->dma_buf_out, (void*)t->output_buf, (size_t)t->output_length);
spiExchange((SPIDriver *)p->reg_addr, t_length, i->dma_buf_out, i->dma_buf_in);
memcpy((void*)t->input_buf, i->dma_buf_in, (size_t)t->input_length);
#else
spiExchange((SPIDriver *)p->reg_addr, t_length, (uint8_t*)t->output_buf, (uint8_t*)t->input_buf);
#endif
// Unselect the slave
spiUnselect((SPIDriver *)p->reg_addr);
@@ -273,6 +322,21 @@ static void handle_spi_thd(struct spi_periph *p)
#if USE_SPI1
static SEMAPHORE_DECL(spi1_sem, 0);
#if defined STM32F7
// We need a special buffer for DMA operations
static IN_DMA_SECTION(uint8_t spi1_dma_buf_out[SPI_DMA_BUF_LEN]);
static IN_DMA_SECTION(uint8_t spi1_dma_buf_in[SPI_DMA_BUF_LEN]);
static struct spi_init spi1_init_s = {
.sem = &spi1_sem,
.dma_buf_out = spi1_dma_buf_out,
.dma_buf_in = spi1_dma_buf_in
};
#else
static struct spi_init spi1_init_s = {
.sem = &spi1_sem,
};
#endif
static __attribute__((noreturn)) void thd_spi1(void *arg)
{
(void) arg;
@@ -288,7 +352,7 @@ static THD_WORKING_AREA(wa_thd_spi1, 1024);
void spi1_arch_init(void)
{
spi1.reg_addr = &SPID1;
spi1.init_struct = &spi1_sem;
spi1.init_struct = &spi1_init_s;
// Create thread
chThdCreateStatic(wa_thd_spi1, sizeof(wa_thd_spi1),
NORMALPRIO+1, thd_spi1, NULL);
@@ -297,6 +361,21 @@ void spi1_arch_init(void)
#if USE_SPI2
static SEMAPHORE_DECL(spi2_sem, 0);
#if defined STM32F7
// We need a special buffer for DMA operations
static IN_DMA_SECTION(uint8_t spi2_dma_buf_out[SPI_DMA_BUF_LEN]);
static IN_DMA_SECTION(uint8_t spi2_dma_buf_in[SPI_DMA_BUF_LEN]);
static struct spi_init spi2_init_s = {
.sem = &spi2_sem,
.dma_buf_out = spi2_dma_buf_out,
.dma_buf_in = spi2_dma_buf_in
};
#else
static struct spi_init spi2_init_s = {
.sem = &spi2_sem,
};
#endif
static __attribute__((noreturn)) void thd_spi2(void *arg)
{
(void) arg;
@@ -312,7 +391,7 @@ static THD_WORKING_AREA(wa_thd_spi2, 1024);
void spi2_arch_init(void)
{
spi2.reg_addr = &SPID2;
spi2.init_struct = &spi2_sem;
spi2.init_struct = &spi2_init_s;
// Create thread
chThdCreateStatic(wa_thd_spi2, sizeof(wa_thd_spi2),
NORMALPRIO+1, thd_spi2, NULL);
@@ -321,6 +400,21 @@ void spi2_arch_init(void)
#if USE_SPI3
static SEMAPHORE_DECL(spi3_sem, 0);
#if defined STM32F7
// We need a special buffer for DMA operations
static IN_DMA_SECTION(uint8_t spi3_dma_buf_out[SPI_DMA_BUF_LEN]);
static IN_DMA_SECTION(uint8_t spi3_dma_buf_in[SPI_DMA_BUF_LEN]);
static struct spi_init spi3_init_s = {
.sem = &spi3_sem,
.dma_buf_out = spi3_dma_buf_out,
.dma_buf_in = spi3_dma_buf_in
};
#else
static struct spi_init spi3_init_s = {
.sem = &spi3_sem,
};
#endif
static __attribute__((noreturn)) void thd_spi3(void *arg)
{
(void) arg;
@@ -336,7 +430,7 @@ static THD_WORKING_AREA(wa_thd_spi3, 1024);
void spi3_arch_init(void)
{
spi3.reg_addr = &SPID3;
spi3.init_struct = &spi3_sem;
spi3.init_struct = &spi3_init_s;
// Create thread
chThdCreateStatic(wa_thd_spi3, sizeof(wa_thd_spi3),
NORMALPRIO+1, thd_spi3, NULL);
@@ -383,7 +477,7 @@ bool spi_submit(struct spi_periph *p, struct spi_transaction *t)
p->trans_insert_idx = idx;
chSysUnlock();
chSemSignal ((semaphore_t *) p->init_struct);
chSemSignal (((struct spi_init *)p->init_struct)->sem);
// transaction submitted
return TRUE;
}
sw/airborne/arch/chibios/mcu_periph/uart_arch.c
+46 -5
View File
@@ -38,6 +38,7 @@
#include <ch.h>
#include <hal.h>
#include "mcu_periph/gpio.h"
#include BOARD_CONFIG
struct SerialInit {
SerialConfig *conf;
@@ -195,11 +196,20 @@ void uart1_init(void)
#define USE_UART2_RX TRUE
#endif
/* by default disable HW flow control */
#ifndef UART2_HW_FLOW_CONTROL
#define UART2_HW_FLOW_CONTROL FALSE
#endif
static SerialConfig usart2_config = {
UART2_BAUD, /* BITRATE */
0, /* USART CR1 */
USART_CR2_STOP1_BITS, /* USART CR2 */
#if UART2_HW_FLOW_CONTROL
USART_CR3_CTSE | USART_CR3_RTSE
#else
0 /* USART CR3 */
#endif
};
static struct SerialInit uart2_init_struct = { NULL, NULL, NULL, NULL, NULL };
@@ -852,6 +862,14 @@ void uart_periph_set_baudrate(struct uart_periph *p, uint32_t baud )
void uart_periph_set_mode(struct uart_periph *p __attribute__((unused)), bool tx_enabled __attribute__((unused)),
bool rx_enabled __attribute__((unused)), bool hw_flow_control __attribute__((unused))) {}
#if defined STM32F7
#define __USART_CR1_M USART_CR1_M_0
#elif defined STM32F1 || defined STM32F4
#define __USART_CR1_M USART_CR1_M
#else
#error unsupported board
#endif
/**
* Set parity and stop bits
*/
@@ -866,21 +884,21 @@ void uart_periph_set_bits_stop_parity(struct uart_periph *p,
conf->cr1 |= USART_CR1_PCE; // set parity control bit
conf->cr1 &= ~USART_CR1_PS; // clear parity selection bit
if (bits == UBITS_7) {
conf->cr1 &= ~USART_CR1_M; // clear word length bit
conf->cr1 &= ~__USART_CR1_M; // clear word length bit
} else { // 8 data bits by default
conf->cr1 |= USART_CR1_M; // set word length bit
conf->cr1 |= __USART_CR1_M; // set word length bit
}
} else if (parity == UPARITY_ODD) {
conf->cr1 |= USART_CR1_PCE; // set parity control bit
conf->cr1 |= USART_CR1_PS; // set parity selection bit
if (bits == UBITS_7) {
conf->cr1 &= ~USART_CR1_M; // clear word length bit
conf->cr1 &= ~__USART_CR1_M; // clear word length bit
} else { // 8 data bits by default
conf->cr1 |= USART_CR1_M; // set word length bit
conf->cr1 |= __USART_CR1_M; // set word length bit
}
} else { // 8 data bist, NO_PARITY by default
conf->cr1 &= ~USART_CR1_PCE; // clear parity control bit
conf->cr1 &= ~USART_CR1_M; // clear word length bit
conf->cr1 &= ~__USART_CR1_M; // clear word length bit
}
/* Configure USART stop bits */
conf->cr2 &= ~USART_CR2_STOP; // clear stop bits
@@ -894,6 +912,29 @@ void uart_periph_set_bits_stop_parity(struct uart_periph *p,
sdStart((SerialDriver*)(p->reg_addr), conf);
}
#ifdef STM32F7
/**
* Invert data logic
*/
void uart_periph_invert_data_logic(struct uart_periph *p, bool invert_rx, bool invert_tx)
{
struct SerialInit *init_struct = (struct SerialInit*)(p->init_struct);
SerialConfig *conf = init_struct->conf;
if (invert_rx) {
conf->cr2 |= USART_CR2_RXINV; // set rxinv bit
} else {
conf->cr2 &= ~USART_CR2_RXINV; // clear rxinv bit
}
if (invert_tx) {
conf->cr2 |= USART_CR2_TXINV; // set txinv bit
} else {
conf->cr2 &= ~USART_CR2_TXINV; // clear txinv bit
}
sdStop((SerialDriver*)(p->reg_addr));
sdStart((SerialDriver*)(p->reg_addr), conf);
}
#endif
// Check free space and set a positive value for fd if valid
// and lock driver with mutex
bool uart_check_free_space(struct uart_periph *p, long *fd, uint16_t len)
sw/airborne/arch/chibios/modules/core/rtos_mon_arch.c
+5 -5
View File
@@ -59,8 +59,8 @@ void rtos_mon_periodic_arch(void)
tp = chRegFirstThread();
do {
// add beginning of thread name to buffer
for (i = 0; i < RTOS_MON_NAME_LEN-1 && tp->p_name[i] != '\0'; i++) {
rtos_mon.thread_names[rtos_mon.thread_name_idx++] = tp->p_name[i];
for (i = 0; i < RTOS_MON_NAME_LEN-1 && tp->name[i] != '\0'; i++) {
rtos_mon.thread_names[rtos_mon.thread_name_idx++] = tp->name[i];
}
rtos_mon.thread_names[rtos_mon.thread_name_idx++] = ';';
@@ -68,12 +68,12 @@ void rtos_mon_periodic_arch(void)
rtos_mon.thread_free_stack[i] = get_stack_free(tp);
// store time spend in thread
thread_p_time[rtos_mon.thread_counter] = tp->p_time;
sum += (float)(tp->p_time);
thread_p_time[rtos_mon.thread_counter] = tp->time;
sum += (float)(tp->time);
// if current thread is 'idle' thread, store its value separately
if (tp == chSysGetIdleThreadX()) {
idle_counter = (uint32_t)tp->p_time;
idle_counter = (uint32_t)tp->time;
}
// get next thread
tp = chRegNextThread(tp);
sw/airborne/arch/chibios/subsystems/actuators/actuators_pwm_arch.c
+12 -12
View File
@@ -89,40 +89,40 @@ void actuators_pwm_arch_init(void)
* Configure GPIO
*----------------*/
#ifdef PWM_SERVO_0
gpio_setup_pin_af(PWM_SERVO_0_GPIO, PWM_SERVO_0_PIN, PWM_SERVO_0_AF);
gpio_setup_pin_af(PWM_SERVO_0_GPIO, PWM_SERVO_0_PIN, PWM_SERVO_0_AF, true);
#endif
#ifdef PWM_SERVO_1
gpio_setup_pin_af(PWM_SERVO_1_GPIO, PWM_SERVO_1_PIN, PWM_SERVO_1_AF);
gpio_setup_pin_af(PWM_SERVO_1_GPIO, PWM_SERVO_1_PIN, PWM_SERVO_1_AF, true);
#endif
#ifdef PWM_SERVO_2
gpio_setup_pin_af(PWM_SERVO_2_GPIO, PWM_SERVO_2_PIN, PWM_SERVO_2_AF);
gpio_setup_pin_af(PWM_SERVO_2_GPIO, PWM_SERVO_2_PIN, PWM_SERVO_2_AF, true);
#endif
#ifdef PWM_SERVO_3
gpio_setup_pin_af(PWM_SERVO_3_GPIO, PWM_SERVO_3_PIN, PWM_SERVO_3_AF);
gpio_setup_pin_af(PWM_SERVO_3_GPIO, PWM_SERVO_3_PIN, PWM_SERVO_3_AF, true);
#endif
#ifdef PWM_SERVO_4
gpio_setup_pin_af(PWM_SERVO_4_GPIO, PWM_SERVO_4_PIN, PWM_SERVO_4_AF);
gpio_setup_pin_af(PWM_SERVO_4_GPIO, PWM_SERVO_4_PIN, PWM_SERVO_4_AF, true);
#endif
#ifdef PWM_SERVO_5
gpio_setup_pin_af(PWM_SERVO_5_GPIO, PWM_SERVO_5_PIN, PWM_SERVO_5_AF);
gpio_setup_pin_af(PWM_SERVO_5_GPIO, PWM_SERVO_5_PIN, PWM_SERVO_5_AF, true);
#endif
#ifdef PWM_SERVO_6
gpio_setup_pin_af(PWM_SERVO_6_GPIO, PWM_SERVO_6_PIN, PWM_SERVO_6_AF);
gpio_setup_pin_af(PWM_SERVO_6_GPIO, PWM_SERVO_6_PIN, PWM_SERVO_6_AF, true);
#endif
#ifdef PWM_SERVO_7
gpio_setup_pin_af(PWM_SERVO_7_GPIO, PWM_SERVO_7_PIN, PWM_SERVO_7_AF);
gpio_setup_pin_af(PWM_SERVO_7_GPIO, PWM_SERVO_7_PIN, PWM_SERVO_7_AF, true);
#endif
#ifdef PWM_SERVO_8
gpio_setup_pin_af(PWM_SERVO_8_GPIO, PWM_SERVO_8_PIN, PWM_SERVO_8_AF);
gpio_setup_pin_af(PWM_SERVO_8_GPIO, PWM_SERVO_8_PIN, PWM_SERVO_8_AF, true);
#endif
#ifdef PWM_SERVO_9
gpio_setup_pin_af(PWM_SERVO_9_GPIO, PWM_SERVO_9_PIN, PWM_SERVO_9_AF);
gpio_setup_pin_af(PWM_SERVO_9_GPIO, PWM_SERVO_9_PIN, PWM_SERVO_9_AF, true);
#endif
#ifdef PWM_SERVO_10
gpio_setup_pin_af(PWM_SERVO_10_GPIO, PWM_SERVO_10_PIN, PWM_SERVO_10_AF);
gpio_setup_pin_af(PWM_SERVO_10_GPIO, PWM_SERVO_10_PIN, PWM_SERVO_10_AF, true);
#endif
#ifdef PWM_SERVO_11
gpio_setup_pin_af(PWM_SERVO_11_GPIO, PWM_SERVO_11_PIN, PWM_SERVO_11_AF);
gpio_setup_pin_af(PWM_SERVO_11_GPIO, PWM_SERVO_11_PIN, PWM_SERVO_11_AF, true);
#endif
/*---------------
sw/airborne/arch/stm32/mcu_periph/gpio_arch.h
+5
View File
@@ -33,6 +33,11 @@
#include <libopencm3/stm32/gpio.h>
/**
* Abstract gpio port type for hardware independent part
*/
typedef uint32_t gpio_port_t;
/**
* Setup one or more pins of the given GPIO port as outputs.
* @param[in] port
sw/airborne/boards/apogee/chibios/v1.0/board.h
+25
View File
@@ -1019,6 +1019,31 @@
#define ActuatorsDefaultInit() ActuatorsPwmInit()
#define ActuatorsDefaultCommit() ActuatorsPwmCommit()
/**
* SDIO
*/
#define SDIO_D0_PORT GPIOC
#define SDIO_D0_PIN GPIOC_SDIO_D0
#define SDIO_D1_PORT GPIOC
#define SDIO_D1_PIN GPIOC_SDIO_D1
#define SDIO_D2_PORT GPIOC
#define SDIO_D2_PIN GPIOC_SDIO_D2
#define SDIO_D3_PORT GPIOC
#define SDIO_D3_PIN GPIOC_SDIO_D3
#define SDIO_CK_PORT GPIOC
#define SDIO_CK_PIN GPIOC_SDIO_CK
#define SDIO_CMD_PORT GPIOD
#define SDIO_CMD_PIN GPIOD_SDIO_CMD
#define SDIO_AF 12
// bat monitoring for file closing
#define SDLOG_BAT_ADC ADCD1
#define SDLOG_BAT_CHAN AD1_4_CHANNEL
// usb led status
#define SDLOG_USB_LED 4
#define SDLOG_USB_VBUS_PORT GPIOA
#define SDLOG_USB_VBUS_PIN GPIO9
#if !defined(_FROM_ASM_)
#ifdef __cplusplus
extern "C" {
sw/airborne/boards/chimera/baro_board.h
+18
View File
@@ -0,0 +1,18 @@
/*
* board specific functions for the chimera board
*
*/
#ifndef BOARDS_CHIMERA_BARO_H
#define BOARDS_CHIMERA_BARO_H
// only for printing the baro type during compilation
#ifndef BARO_BOARD
#define BARO_BOARD BARO_MS5611_I2C
#endif
extern void baro_event(void);
#define BaroEvent baro_event
#endif /* BOARDS_CHIMERA_BARO_H */
sw/airborne/boards/chimera/chibios/v1.0/board.c
+132
View File
@@ -0,0 +1,132 @@
/*
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#include "hal.h"
#if HAL_USE_PAL || defined(__DOXYGEN__)
/**
* @brief PAL setup.
* @details Digital I/O ports static configuration as defined in @p board.h.
* This variable is used by the HAL when initializing the PAL driver.
*/
const PALConfig pal_default_config = {
#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
#endif
#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
#endif
#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
#endif
#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
#endif
#if STM32_HAS_GPIOE
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
#endif
#if STM32_HAS_GPIOF
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
#endif
#if STM32_HAS_GPIOG
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
#endif
#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
#endif
#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
#endif
#if STM32_HAS_GPIOJ
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
#endif
#if STM32_HAS_GPIOK
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
#endif
};
#endif
/**
* @brief Early initialization code.
* @details This initialization must be performed just after stack setup
* and before any other initialization.
*/
void __early_init(void) {
stm32_clock_init();
}
#if HAL_USE_SDC || defined(__DOXYGEN__)
/**
* @brief SDC card detection.
*/
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
return !palReadLine (LINE_SD_DETECT);
}
/**
* @brief SDC card write protection detection.
*/
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
/* TODO: Fill the implementation.*/
return false;
}
#endif /* HAL_USE_SDC */
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
/**
* @brief MMC_SPI card detection.
*/
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
return true;
}
/**
* @brief MMC_SPI card write protection detection.
*/
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
return false;
}
#endif
/**
* @brief Board-specific initialization code.
* @todo Add your board-specific code, if any.
*/
void boardInit(void) {
}
sw/airborne/boards/chimera/chibios/v1.0/board.h
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sw/airborne/boards/chimera/chibios/v1.0/board.mk
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#
# ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# Required include directories
BOARDINC = $(CHIBIOS_BOARD_DIR)
# List of all the board related files.
BOARDSRC = ${BOARDINC}/board.c
sw/airborne/boards/chimera/chibios/v1.0/chimera.h
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sw/airborne/boards/chimera/chibios/v1.0/ffconf.h
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/* CHIBIOS FIX */
#include "ch.h"
/*---------------------------------------------------------------------------/
/ FatFs - FAT file system module configuration file R0.10b (C)ChaN, 2014
/---------------------------------------------------------------------------*/
#ifndef _FFCONF
#define _FFCONF 8051 /* Revision ID */
/*---------------------------------------------------------------------------/
/ Functions and Buffer Configurations
/---------------------------------------------------------------------------*/
#define _FS_TINY 0 /* 0:Normal or 1:Tiny */
/* When _FS_TINY is set to 1, it reduces memory consumption _MAX_SS bytes each
/ file object. For file data transfer, FatFs uses the common sector buffer in
/ the file system object (FATFS) instead of private sector buffer eliminated
/ from the file object (FIL). */
#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */
/* Setting _FS_READONLY to 1 defines read only configuration. This removes
/ writing functions, f_write(), f_sync(), f_unlink(), f_mkdir(), f_chmod(),
/ f_rename(), f_truncate() and useless f_getfree(). */
#define _FS_MINIMIZE 0 /* 0 to 3 */
/* The _FS_MINIMIZE option defines minimization level to remove API functions.
/
/ 0: All basic functions are enabled.
/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_chmod(), f_utime(),
/ f_truncate() and f_rename() function are removed.
/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
/ 3: f_lseek() function is removed in addition to 2. */
#define _USE_STRFUNC 2 /* 0:Disable or 1-2:Enable */
/* To enable string functions, set _USE_STRFUNC to 1 or 2. */
#define _USE_MKFS 1 /* 0:Disable or 1:Enable */
/* To enable f_mkfs() function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */
#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */
/* To enable fast seek feature, set _USE_FASTSEEK to 1. */
#define _USE_LABEL 0 /* 0:Disable or 1:Enable */
/* To enable volume label functions, set _USE_LAVEL to 1 */
#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */
/* To enable f_forward() function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */
/*---------------------------------------------------------------------------/
/ Locale and Namespace Configurations
/---------------------------------------------------------------------------*/
#define _CODE_PAGE 1252
/* The _CODE_PAGE specifies the OEM code page to be used on the target system.
/ Incorrect setting of the code page can cause a file open failure.
/
/ 932 - Japanese Shift_JIS (DBCS, OEM, Windows)
/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows)
/ 949 - Korean (DBCS, OEM, Windows)
/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows)
/ 1250 - Central Europe (Windows)
/ 1251 - Cyrillic (Windows)
/ 1252 - Latin 1 (Windows)
/ 1253 - Greek (Windows)
/ 1254 - Turkish (Windows)
/ 1255 - Hebrew (Windows)
/ 1256 - Arabic (Windows)
/ 1257 - Baltic (Windows)
/ 1258 - Vietnam (OEM, Windows)
/ 437 - U.S. (OEM)
/ 720 - Arabic (OEM)
/ 737 - Greek (OEM)
/ 775 - Baltic (OEM)
/ 850 - Multilingual Latin 1 (OEM)
/ 858 - Multilingual Latin 1 + Euro (OEM)
/ 852 - Latin 2 (OEM)
/ 855 - Cyrillic (OEM)
/ 866 - Russian (OEM)
/ 857 - Turkish (OEM)
/ 862 - Hebrew (OEM)
/ 874 - Thai (OEM, Windows)
/ 1 - ASCII (Valid for only non-LFN configuration) */
#define _USE_LFN 2 /* 0 to 3 */
#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */
/* The _USE_LFN option switches the LFN feature.
/
/ 0: Disable LFN feature. _MAX_LFN has no effect.
/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
/ 2: Enable LFN with dynamic working buffer on the STACK.
/ 3: Enable LFN with dynamic working buffer on the HEAP.
/
/ When enable LFN feature, Unicode handling functions ff_convert() and ff_wtoupper()
/ function must be added to the project.
/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. When use stack for the
/ working buffer, take care on stack overflow. When use heap memory for the working
/ buffer, memory management functions, ff_memalloc() and ff_memfree(), must be added
/ to the project. */
#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */
/* To switch the character encoding on the FatFs API (TCHAR) to Unicode, enable LFN
/ feature and set _LFN_UNICODE to 1. This option affects behavior of string I/O
/ functions. This option must be 0 when LFN feature is not enabled. */
#define _STRF_ENCODE 3 /* 0:ANSI/OEM, 1:UTF-16LE, 2:UTF-16BE, 3:UTF-8 */
/* When Unicode API is enabled by _LFN_UNICODE option, this option selects the character
/ encoding on the file to be read/written via string I/O functions, f_gets(), f_putc(),
/ f_puts and f_printf(). This option has no effect when Unicode API is not enabled. */
#define _FS_RPATH 2 /* 0 to 2 */
/* The _FS_RPATH option configures relative path feature.
/
/ 0: Disable relative path feature and remove related functions.
/ 1: Enable relative path. f_chdrive() and f_chdir() function are available.
/ 2: f_getcwd() function is available in addition to 1.
/
/ Note that output of the f_readdir() fnction is affected by this option. */
/*---------------------------------------------------------------------------/
/ Drive/Volume Configurations
/---------------------------------------------------------------------------*/
#define _VOLUMES 1
/* Number of volumes (logical drives) to be used. */
#define _STR_VOLUME_ID 0 /* 0:Use only 0-9 for drive ID, 1:Use strings for drive ID */
#define _VOLUME_STRS "RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3"
/* When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive
/ number in the path name. _VOLUME_STRS defines the drive ID strings for each logical
/ drives. Number of items must be equal to _VOLUMES. Valid characters for the drive ID
/ strings are: 0-9 and A-Z. */
#define _MULTI_PARTITION 0 /* 0:Single partition, 1:Enable multiple partition */
/* By default(0), each logical drive number is bound to the same physical drive number
/ and only a FAT volume found on the physical drive is mounted. When it is set to 1,
/ each logical drive number is bound to arbitrary drive/partition listed in VolToPart[].
*/
#define _MIN_SS 512
#define _MAX_SS 512
/* These options configure the range of sector size to be supported. (512, 1024, 2048 or
/ 4096) Always set both 512 for most systems, all memory card and harddisk. But a larger
/ value may be required for on-board flash memory and some type of optical media.
/ When _MAX_SS is larger than _MIN_SS, FatFs is configured to variable sector size and
/ GET_SECTOR_SIZE command must be implemented to the disk_ioctl() function. */
#define _USE_ERASE 1 /* 0:Disable or 1:Enable */
/* To enable sector erase feature, set _USE_ERASE to 1. Also CTRL_ERASE_SECTOR command
/ should be added to the disk_ioctl() function. */
#define _FS_NOFSINFO 0 /* 0 to 3 */
/* If you need to know correct free space on the FAT32 volume, set bit 0 of this option
/ and f_getfree() function at first time after volume mount will force a full FAT scan.
/ Bit 1 controls the last allocated cluster number as bit 0.
/
/ bit0=0: Use free cluster count in the FSINFO if available.
/ bit0=1: Do not trust free cluster count in the FSINFO.
/ bit1=0: Use last allocated cluster number in the FSINFO if available.
/ bit1=1: Do not trust last allocated cluster number in the FSINFO.
*/
/*---------------------------------------------------------------------------/
/ System Configurations
/---------------------------------------------------------------------------*/
#define _FS_REENTRANT 1 /* 0:Disable or 1:Enable */
#define _FS_TIMEOUT MS2ST(1000) /* Timeout period in unit of time tick */
#define _SYNC_t semaphore_t* /* O/S dependent sync object type. e.g. HANDLE, OS_EVENT*, ID, SemaphoreHandle_t and etc.. */
/* The _FS_REENTRANT option switches the re-entrancy (thread safe) of the FatFs module.
/
/ 0: Disable re-entrancy. _FS_TIMEOUT and _SYNC_t have no effect.
/ 1: Enable re-entrancy. Also user provided synchronization handlers,
/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
/ function must be added to the project.
*/
#define _WORD_ACCESS 1 /* 0 or 1 */
/* The _WORD_ACCESS option is an only platform dependent option. It defines
/ which access method is used to the word data on the FAT volume.
/
/ 0: Byte-by-byte access. Always compatible with all platforms.
/ 1: Word access. Do not choose this unless under both the following conditions.
/
/ * Address misaligned memory access is always allowed for ALL instructions.
/ * Byte order on the memory is little-endian.
/
/ If it is the case, _WORD_ACCESS can also be set to 1 to improve performance and
/ reduce code size. Following table shows an example of some processor types.
/
/ ARM7TDMI 0 ColdFire 0 V850E2 0
/ Cortex-M3 0 Z80 0/1 V850ES 0/1
/ Cortex-M0 0 RX600(LE) 0/1 TLCS-870 0/1
/ AVR 0/1 RX600(BE) 0 TLCS-900 0/1
/ AVR32 0 RL78 0 R32C 0
/ PIC18 0/1 SH-2 0 M16C 0/1
/ PIC24 0 H8S 0 MSP430 0
/ PIC32 0 H8/300H 0 x86 0/1
*/
#define _FS_LOCK 0 /* 0:Disable or >=1:Enable */
/* To enable file lock control feature, set _FS_LOCK to non-zero value.
/ The value defines how many files/sub-directories can be opened simultaneously
/ with file lock control. This feature uses bss _FS_LOCK * 12 bytes.
/
/ IMPORTANT NOTE:
/ For Paparazzi, we don't need file locking since all file are written sequentially
/ from one thread (thdSdLog)
/
*/
#endif /* _FFCONF */
sw/airborne/boards/chimera/chibios/v1.0/mcuconf.h
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/*
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _MCUCONF_H_
#define _MCUCONF_H_
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F7xx_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
#define STM32_HSI_ENABLED TRUE
#define STM32_LSI_ENABLED FALSE
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED TRUE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 16
#define STM32_PLLN_VALUE 432
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 9
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#define STM32_RTCSEL STM32_RTCSEL_LSE
#define STM32_RTCPRE_VALUE 25
#define STM32_MCO1SEL STM32_MCO1SEL_HSE
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
#define STM32_PLLI2SR_VALUE 4
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIDIVR STM32_PLLSAIDIVR_OFF
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
#define STM32_USART2SEL STM32_USART2SEL_PCLK1
#define STM32_USART3SEL STM32_USART3SEL_PCLK1
#define STM32_UART4SEL STM32_UART4SEL_PCLK1
#define STM32_UART5SEL STM32_UART5SEL_PCLK1
#define STM32_USART6SEL STM32_USART6SEL_PCLK2
#define STM32_UART7SEL STM32_UART7SEL_PCLK1
#define STM32_UART8SEL STM32_UART8SEL_PCLK1
#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 // STM32_I2C1SEL_SYSCLK
#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL STM32_CECSEL_LSE
#define STM32_CK48MSEL STM32_CK48MSEL_PLL
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
#define STM32_SRAM2_NOCACHE FALSE
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
/*
* CAN driver system settings.
*/
#if USE_CAN1
#define STM32_CAN_USE_CAN1 TRUE
#else
#define STM32_CAN_USE_CAN1 FALSE
#endif
#if USE_CAN2
#define STM32_CAN_USE_CAN2 TRUE
#else
#define STM32_CAN_USE_CAN2 FALSE
#endif
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#if USE_DAC1
#define STM32_DAC_USE_DAC1_CH2 TRUE
#else
#define STM32_DAC_USE_DAC1_CH2 FALSE
#endif
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
//#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
/*
* EXT driver system settings.
*/
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE // keep free if in tickless mode
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_USE_TIM12 FALSE
#define STM32_GPT_USE_TIM14 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
#define STM32_GPT_TIM12_IRQ_PRIORITY 7
#define STM32_GPT_TIM14_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
#if USE_I2C1
#define STM32_I2C_USE_I2C1 TRUE
#else
#define STM32_I2C_USE_I2C1 FALSE
#endif
#if USE_I2C2 // CAN or I2C2 because of dma conflict
#define STM32_I2C_USE_I2C2 TRUE
#else
#define STM32_I2C_USE_I2C2 FALSE
#endif
#define STM32_I2C_USE_I2C3 FALSE
#define STM32_I2C_USE_I2C4 FALSE
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
//#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C4_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_I2C4_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#ifdef USE_PWM_INPUT1
#define STM32_ICU_USE_TIM2 TRUE
#else
#define STM32_ICU_USE_TIM2 FALSE // keep free if in tickless mode
#endif
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#if RADIO_CONTROL_TYPE_PPM
#define STM32_ICU_USE_TIM5 TRUE
#else
#define STM32_ICU_USE_TIM5 FALSE
#endif
#ifdef USE_PWM_INPUT2
#define STM32_ICU_USE_TIM8 TRUE
#else
#define STM32_ICU_USE_TIM8 FALSE
#endif
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#define STM32_PWM_USE_TIM1 FALSE
#ifndef STM32_PWM_USE_TIM2
#define STM32_PWM_USE_TIM2 FALSE // keep free if in tickless mode, can be used in systick mode
#endif
#ifndef STM32_PWM_USE_TIM3
#define STM32_PWM_USE_TIM3 TRUE
#endif
#ifndef STM32_PWM_USE_TIM4
#define STM32_PWM_USE_TIM4 TRUE
#endif
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
/*
* SERIAL driver system settings.
*/
#if USE_UART1
#define STM32_SERIAL_USE_USART1 TRUE
#else
#define STM32_SERIAL_USE_USART1 FALSE
#endif
#if USE_UART2
#define STM32_SERIAL_USE_USART2 TRUE
#else
#define STM32_SERIAL_USE_USART2 FALSE
#endif
#if USE_UART3
#define STM32_SERIAL_USE_USART3 TRUE
#else
#define STM32_SERIAL_USE_USART3 FALSE
#endif
#if USE_UART4
#define STM32_SERIAL_USE_UART4 TRUE
#else
#define STM32_SERIAL_USE_UART4 FALSE
#endif
#if USE_UART5
#define STM32_SERIAL_USE_UART5 TRUE
#else
#define STM32_SERIAL_USE_UART5 FALSE
#endif
#if USE_UART6
#define STM32_SERIAL_USE_USART6 TRUE
#else
#define STM32_SERIAL_USE_USART6 FALSE
#endif
#if USE_UART7
#define STM32_SERIAL_USE_UART7 TRUE
#else
#define STM32_SERIAL_USE_UART7 FALSE
#endif
#if USE_UART8
#define STM32_SERIAL_USE_UART8 TRUE
#else
#define STM32_SERIAL_USE_UART8 FALSE
#endif
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART3_PRIORITY 12
#define STM32_SERIAL_UART4_PRIORITY 12
#define STM32_SERIAL_UART5_PRIORITY 12
#define STM32_SERIAL_USART6_PRIORITY 12
#define STM32_SERIAL_UART7_PRIORITY 12
#define STM32_SERIAL_UART8_PRIORITY 12
/*
* SPI driver system settings.
*/
#if USE_SPI1
#define STM32_SPI_USE_SPI1 TRUE
#else
#define STM32_SPI_USE_SPI1 FALSE
#endif
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_USE_SPI4 FALSE
#define STM32_SPI_USE_SPI5 FALSE
#define STM32_SPI_USE_SPI6 FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
//#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI4_DMA_PRIORITY 1
#define STM32_SPI_SPI4_DMA_PRIORITY 1
#define STM32_SPI_SPI4_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_SPI4_IRQ_PRIORITY 10
#define STM32_SPI_SPI5_IRQ_PRIORITY 10
#define STM32_SPI_SPI6_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE /* DMA OK */
#define STM32_UART_USE_USART2 FALSE /* NO DMA AVAIL */
#define STM32_UART_USE_USART3 FALSE /* DMA OK */
#define STM32_UART_USE_UART4 FALSE /* NO DMA AVAIL */
#define STM32_UART_USE_UART5 FALSE /* NO DMA AVAIL */
#define STM32_UART_USE_USART6 FALSE /* NO DMA AVAIL */
#define STM32_UART_USE_UART7 FALSE /* NO DMA AVAIL */
#define STM32_UART_USE_UART8 FALSE /* NO DMA AVAIL */
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
/* #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) */
/* #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) */
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
/* #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) */
/* #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) */
/* #define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) */
/* #define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) */
/* #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) */
/* #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) */
/* #define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) */
/* #define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) */
/* #define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) */
/* #define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) */
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_UART7_DMA_PRIORITY 0
#define STM32_UART_UART8_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_USE_OTG2 FALSE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG2_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
#define STM32_USB_OTG_THREAD_STACK_SIZE 128
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
/*
* SDC driver system settings.
*/
#define STM32_SDC_USE_SDMMC1 TRUE
#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
#define STM32_SDC_SDMMC_WRITE_TIMEOUT 250
#define STM32_SDC_SDMMC_READ_TIMEOUT 25
#define STM32_SDC_SDMMC_CLOCK_DELAY 10
#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
#define STM32_SDC_SDMMC1_DMA_PRIORITY 3
#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
/* sdlog message buffer and queue configuration
*/
#define SDLOG_QUEUE_BUCKETS 512
#define SDLOG_ALL_BUFFERS_SIZE 8192
#define SDLOG_MAX_MESSAGE_LEN 252
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
//#define CH_HEAP_SIZE (32*1024)
//#define CH_HEAP_USE_TLSF 1 // if 0 or undef, chAlloc will be used
#endif /* _MCUCONF_H_ */
sw/airborne/mcu_periph/uart.c
+4
View File
@@ -296,3 +296,7 @@ void WEAK uart_arch_init(void)
{
}
void WEAK uart_periph_invert_data_logic(struct uart_periph *p __attribute__((unused)), bool invert_rx __attribute__((unused)), bool invert_tx __attribute__((unused)))
{
}
sw/airborne/mcu_periph/uart.h
+3 -2
View File
@@ -33,7 +33,7 @@
#include "std.h"
#ifndef UART_RX_BUFFER_SIZE
#ifdef STM32F4 //the F4 has enough memory
#if defined STM32F4 || defined STM32F7 //the F4 and F7 have enough memory
#define UART_RX_BUFFER_SIZE 256
#else
#define UART_RX_BUFFER_SIZE 128
@@ -41,7 +41,7 @@
#endif
#ifndef UART_TX_BUFFER_SIZE
#ifdef STM32F4 //the F4 has enough memory, and the PX4 bootloader needs more then 128
#if defined STM32F4 || defined STM32F7 //the F4 and F7 have enough memory, and the PX4 bootloader needs more then 128
#define UART_TX_BUFFER_SIZE 256
#else
#define UART_TX_BUFFER_SIZE 128
@@ -97,6 +97,7 @@ extern void uart_periph_init(struct uart_periph *p);
extern void uart_periph_set_baudrate(struct uart_periph *p, uint32_t baud);
extern void uart_periph_set_bits_stop_parity(struct uart_periph *p, uint8_t bits, uint8_t stop, uint8_t parity);
extern void uart_periph_set_mode(struct uart_periph *p, bool tx_enabled, bool rx_enabled, bool hw_flow_control);
extern void uart_periph_invert_data_logic(struct uart_periph *p, bool invert_rx, bool invert_tx);
extern void uart_put_byte(struct uart_periph *p, long fd, uint8_t data);
extern void uart_put_buffer(struct uart_periph *p, long fd, const uint8_t *data, uint16_t len);
extern bool uart_check_free_space(struct uart_periph *p, long *fd, uint16_t len);
sw/airborne/modules/loggers/sdlog_chibios.c
+4 -14
View File
@@ -32,10 +32,11 @@
#include "modules/loggers/sdlog_chibios.h"
#include "modules/tlsf/tlsf_malloc.h"
#include "mcu_periph/adc.h"
#include "mcu.h"
#include "led.h"
#if HAL_USE_RTC
#include <rtc.h>
#include <hal_rtc.h>
#include <time.h>
#include "subsystems/gps.h"
#endif
@@ -67,7 +68,6 @@ static __attribute__((noreturn)) void thd_startlog(void *arg);
static THD_WORKING_AREA(wa_thd_bat_survey, 1024);
static __attribute__((noreturn)) void thd_bat_survey(void *arg);
static void powerOutageIsr (void);
static void systemDeepSleep (void);
event_source_t powerOutageSource;
event_listener_t powerOutageListener;
@@ -235,13 +235,12 @@ static void thd_bat_survey(void *arg)
chEvtRegister(&powerOutageSource, &powerOutageListener, 1);
chThdSleepMilliseconds (2000);
// FIXME: &ADCD1 and channel AD1_4 should not be hardcoded like this
register_adc_watchdog(&ADCD1, AD1_4_CHANNEL, V_ALERT, &powerOutageIsr);
register_adc_watchdog(&SDLOG_BAT_ADC, SDLOG_BAT_CHAN, V_ALERT, &powerOutageIsr);
chEvtWaitOne(EVENT_MASK(1));
sdlog_chibios_finish (true);
chThdExit(0);
systemDeepSleep();
mcu_deep_sleep();
chThdSleepMilliseconds (TIME_INFINITE);
while (1); // never goes here, only to avoid compiler warning: 'noreturn' function does return
}
@@ -255,12 +254,3 @@ static void powerOutageIsr (void)
chEvtBroadcastI(&powerOutageSource);
}
static void systemDeepSleep (void)
{
chSysLock();
SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk;
PWR->CR |= (PWR_CR_PDDS | PWR_CR_LPDS | PWR_CR_CSBF | PWR_CR_CWUF);
__WFE();
chSysUnlock();
}
sw/airborne/modules/loggers/sdlog_chibios/printf.c
+1 -1
View File
@@ -191,7 +191,7 @@ static void _chvsnprintf(char *buffer, BaseSequentialStream *chp, size_t size, c
return true;
}
} else if (chp != NULL) {
chSequentialStreamPut(chp, _c);
streamPut(chp, _c);
return false;
}
return false;
sw/airborne/modules/loggers/sdlog_chibios/printf.h
+3
View File
@@ -30,6 +30,9 @@
#define _PRINTF_H_
#include <stdarg.h>
#include <ch.h>
#include <hal.h>
/**
* @brief Float type support.
*/
sw/airborne/modules/loggers/sdlog_chibios/sdLog.c
+22 -14
View File
@@ -78,17 +78,25 @@
#ifdef SDLOG_NEED_QUEUE
#include "modules/loggers/sdlog_chibios/msg_queue.h"
#if defined STM32F4XX
#define NODMA_SECTION ".ram4"
#define DMA_SECTION ".ram0"
#elif defined STM32F7XX
#define NODMA_SECTION ".ram0"
#define DMA_SECTION ".ram3"
#else
#error "section defined only for STM32F4 and STM32F7"
#endif
#include "mcu_periph/ram_arch.h"
static msg_t queMbBuffer[SDLOG_QUEUE_BUCKETS] __attribute__((section(NODMA_SECTION), aligned(8))) ;
/*
The buffers that do DMA are the caches (named buf) in the FIL and FATFS struct of fatfs library
It's the only buffers that have to reside in DMA capable memory.
The buffer associated with message queue, and the cache buffer for caching file write
could reside in non DMA capable memory.
stm32f4 : regular sram : 128ko, dma, slow
ccm sram : 64ko, no_dma, fast
stm32f7 : regular sram : 256ko, dma only possible if data cache are explicitely flushed, fast
dtcm sram : 64ko, dma, slow (no cache)
*/
static msg_t IN_STD_SECTION (queMbBuffer[SDLOG_QUEUE_BUCKETS]);
static MsgQueue messagesQueue;
#define WRITE_BYTE_CACHE_SIZE 15 // limit overhead :
@@ -113,7 +121,7 @@ struct FilePoolUnit {
uint8_t writeByteSeek;
};
static struct FilePoolUnit fileDes[SDLOG_NUM_BUFFER] = {
static struct FilePoolUnit IN_DMA_SECTION (fileDes[SDLOG_NUM_BUFFER]) = {
[0 ... SDLOG_NUM_BUFFER - 1] = {
.fil = {0}, .inUse = false, .tagAtClose = false,
.writeByteCache = NULL, .writeByteSeek = 0
@@ -138,8 +146,8 @@ struct _SdLogBuffer {
#define LOG_MESSAGE_PREBUF_LEN (SDLOG_MAX_MESSAGE_LEN+sizeof(LogMessage))
#endif // SDLOG_NEED_QUEUE
static FATFS fatfs; /* File system object */
/* File system object */
static IN_DMA_SECTION (FATFS fatfs);
#ifdef SDLOG_NEED_QUEUE
static size_t logMessageLen(const LogMessage *lm);
@@ -801,7 +809,7 @@ static msg_t thdSdLog(void *arg)
} ;
UINT bw;
static struct PerfBuffer perfBuffers[SDLOG_NUM_BUFFER] __attribute__((section(DMA_SECTION), aligned(8))) = {
static IN_STD_SECTION(struct PerfBuffer perfBuffers[SDLOG_NUM_BUFFER]) = {
[0 ... SDLOG_NUM_BUFFER - 1] = {.buffer = {0}, .size = 0}
};
sw/airborne/modules/loggers/sdlog_chibios/usbStorage.c
+11 -10
View File
@@ -32,7 +32,9 @@
#include <stdio.h>
#include <string.h>
#include "main_chibios.h"
#include "mcu.h"
#include "mcu_periph/sdio.h"
#include "led.h"
static uint8_t nibbleToHex(uint8_t nibble);
static void populateSerialNumberDescriptorData(void);
@@ -44,8 +46,6 @@ static bool isRunning = false;
/* endpoint index */
#define USB_MS_DATA_EP 1
// cortex_m4 specific
#define MCU_RESTART() {*((unsigned long *)0x0E000ED0C) = 0x05FA0004;}
/* USB device descriptor */
static const uint8_t deviceDescriptorData[] = {
@@ -221,12 +221,13 @@ const USBConfig usbConfig = {
};
/* Turns on a LED when there is I/O activity on the USB port */
static void usbActivity(bool active)
static void usbActivity(bool active __attribute__((unused)))
{
#ifdef GPIOC_LED4
palWritePad(GPIOC, GPIOC_LED4, active);
#else
(void)active;
#ifdef SDLOG_USB_LED
if (active)
LED_ON(SDLOG_USB_LED);
else
LED_OFF(SDLOG_USB_LED);
#endif
}
@@ -285,7 +286,7 @@ static void thdUsbStorage(void *arg)
// Should be fixed when using chibios-rt branch
// FIXME: Is the comment still relevant?
while (!chThdShouldTerminateX() && antiBounce) {
const bool usbConnected = palReadPad(GPIOA, GPIOA_OTG_FS_VBUS);
const bool usbConnected = palReadPad(SDLOG_USB_VBUS_PORT, SDLOG_USB_VBUS_PIN);
if (usbConnected) {
antiBounce--;
} else {
@@ -326,7 +327,7 @@ static void thdUsbStorage(void *arg)
pprz_terminate_autopilot_threads();
/* wait until usb-storage is unmount and usb cable is unplugged*/
while (!chThdShouldTerminateX() && palReadPad(GPIOA, GPIOA_OTG_FS_VBUS)) {
while (!chThdShouldTerminateX() && palReadPad(SDLOG_USB_VBUS_PORT, SDLOG_USB_VBUS_PIN)) {
chThdSleepMilliseconds(10);
}
@@ -337,7 +338,7 @@ static void thdUsbStorage(void *arg)
msdStop(&UMSD1);
sdio_disconnect();
MCU_RESTART();
mcu_reset();
return;
}
sw/airborne/subsystems/imu/imu_mpu9250_i2c.c
+22 -9
View File
@@ -83,6 +83,19 @@ PRINT_CONFIG_VAR(IMU_MPU9250_CHAN_Y)
#endif
PRINT_CONFIG_VAR(IMU_MPU9250_CHAN_Z)
#ifndef IMU_MPU9250_X_SIGN
#define IMU_MPU9250_X_SIGN 1
#endif
PRINT_CONFIG_VAR(IMU_MPU9250_X_SIGN)
#ifndef IMU_MPU9250_Y_SIGN
#define IMU_MPU9250_Y_SIGN 1
#endif
PRINT_CONFIG_VAR(IMU_MPU9250_Y_SIGN)
#ifndef IMU_MPU9250_Z_SIGN
#define IMU_MPU9250_Z_SIGN 1
#endif
PRINT_CONFIG_VAR(IMU_MPU9250_Z_SIGN)
struct ImuMpu9250 imu_mpu9250;
@@ -113,14 +126,14 @@ void imu_mpu9250_event(void)
if (imu_mpu9250.mpu.data_available) {
// set channel order
struct Int32Vect3 accel = {
(int32_t)(imu_mpu9250.mpu.data_accel.value[IMU_MPU9250_CHAN_X]),
(int32_t)(imu_mpu9250.mpu.data_accel.value[IMU_MPU9250_CHAN_Y]),
(int32_t)(imu_mpu9250.mpu.data_accel.value[IMU_MPU9250_CHAN_Z])
IMU_MPU9250_X_SIGN * (int32_t)(imu_mpu9250.mpu.data_accel.value[IMU_MPU9250_CHAN_X]),
IMU_MPU9250_Y_SIGN * (int32_t)(imu_mpu9250.mpu.data_accel.value[IMU_MPU9250_CHAN_Y]),
IMU_MPU9250_Z_SIGN * (int32_t)(imu_mpu9250.mpu.data_accel.value[IMU_MPU9250_CHAN_Z])
};
struct Int32Rates rates = {
(int32_t)(imu_mpu9250.mpu.data_rates.value[IMU_MPU9250_CHAN_X]),
(int32_t)(imu_mpu9250.mpu.data_rates.value[IMU_MPU9250_CHAN_Y]),
(int32_t)(imu_mpu9250.mpu.data_rates.value[IMU_MPU9250_CHAN_Z])
IMU_MPU9250_X_SIGN * (int32_t)(imu_mpu9250.mpu.data_rates.value[IMU_MPU9250_CHAN_X]),
IMU_MPU9250_Y_SIGN * (int32_t)(imu_mpu9250.mpu.data_rates.value[IMU_MPU9250_CHAN_Y]),
IMU_MPU9250_Z_SIGN * (int32_t)(imu_mpu9250.mpu.data_rates.value[IMU_MPU9250_CHAN_Z])
};
// unscaled vector
VECT3_COPY(imu.accel_unscaled, accel);
@@ -137,9 +150,9 @@ void imu_mpu9250_event(void)
// Test if mag data are updated
if (imu_mpu9250.mpu.akm.data_available) {
struct Int32Vect3 mag = {
(int32_t)(imu_mpu9250.mpu.akm.data.value[IMU_MPU9250_CHAN_Y]),
(int32_t)(imu_mpu9250.mpu.akm.data.value[IMU_MPU9250_CHAN_X]),
-(int32_t)(imu_mpu9250.mpu.akm.data.value[IMU_MPU9250_CHAN_Z])
IMU_MPU9250_X_SIGN * (int32_t)(imu_mpu9250.mpu.akm.data.value[IMU_MPU9250_CHAN_Y]),
IMU_MPU9250_Y_SIGN * (int32_t)(imu_mpu9250.mpu.akm.data.value[IMU_MPU9250_CHAN_X]),
-IMU_MPU9250_Z_SIGN * (int32_t)(imu_mpu9250.mpu.akm.data.value[IMU_MPU9250_CHAN_Z])
};
VECT3_COPY(imu.mag_unscaled, mag);
imu_mpu9250.mpu.akm.data_available = false;
sw/airborne/subsystems/radio_control/sbus.c
+7 -1
View File
@@ -28,6 +28,12 @@
#include "subsystems/radio_control/sbus.h"
#include BOARD_CONFIG
#ifndef RC_POLARITY_GPIO_PORT
#define RC_POLARITY_GPIO_PORT 0
#endif
#ifndef RC_POLARITY_GPIO_PIN
#define RC_POLARITY_GPIO_PIN 0
#endif
/** SBUS struct */
struct Sbus sbus;
@@ -47,7 +53,7 @@ static void send_sbus(struct transport_tx *trans, struct link_device *dev)
// Init function
void radio_control_impl_init(void)
{
sbus_common_init(&sbus, &SBUS_UART_DEV);
sbus_common_init(&sbus, &SBUS_UART_DEV, RC_POLARITY_GPIO_PORT, RC_POLARITY_GPIO_PIN);
// Register telemetry message
#if PERIODIC_TELEMETRY
sw/airborne/subsystems/radio_control/sbus_common.c
+31 -34
View File
@@ -26,7 +26,6 @@
#include "subsystems/radio_control.h"
#include "subsystems/radio_control/sbus_common.h"
#include BOARD_CONFIG
#include "mcu_periph/gpio.h"
#include <string.h>
/*
@@ -54,7 +53,8 @@
#endif
void sbus_common_init(struct Sbus *sbus_p, struct uart_periph *dev)
void sbus_common_init(struct Sbus *sbus_p, struct uart_periph *dev,
gpio_port_t gpio_polarity_port, uint16_t gpio_polarity_pin)
{
sbus_p->frame_available = false;
sbus_p->status = SBUS_STATUS_UNINIT;
@@ -62,12 +62,14 @@ void sbus_common_init(struct Sbus *sbus_p, struct uart_periph *dev)
// Set UART parameters (100K, 8 bits, 2 stops, even parity)
uart_periph_set_baudrate(dev, B100000);
uart_periph_set_bits_stop_parity(dev, UBITS_8, USTOP_2, UPARITY_EVEN);
// Try to invert RX data logic when available in hardware periph
uart_periph_invert_data_logic(dev, true, false);
// Set polarity
#ifdef RC_POLARITY_GPIO_PORT
gpio_setup_output(RC_POLARITY_GPIO_PORT, RC_POLARITY_GPIO_PIN);
RC_SET_POLARITY(RC_POLARITY_GPIO_PORT, RC_POLARITY_GPIO_PIN);
#endif
// Set polarity (when not done in hardware, don't use both!)
if (gpio_polarity_port != 0) {
gpio_setup_output(gpio_polarity_port, gpio_polarity_pin);
RC_SET_POLARITY(gpio_polarity_port, gpio_polarity_pin);
}
}
@@ -76,36 +78,31 @@ void sbus_common_init(struct Sbus *sbus_p, struct uart_periph *dev)
static void decode_sbus_buffer(const uint8_t *src, uint16_t *dst, bool *available,
uint16_t *dstppm __attribute__((unused)))
{
// reset counters
uint8_t byteInRawBuf = 0;
uint8_t bitInRawBuf = 0;
uint8_t channel = 0;
uint8_t bitInChannel = 0;
// decode sbus data, unrolling the loop for efficiency
dst[0] = ((src[0] ) | (src[1]<<8)) & 0x07FF;
dst[1] = ((src[1]>>3 ) | (src[2]<<5)) & 0x07FF;
dst[2] = ((src[2]>>6 ) | (src[3]<<2) | (src[4]<<10)) & 0x07FF;
dst[3] = ((src[4]>>1 ) | (src[5]<<7)) & 0x07FF;
dst[4] = ((src[5]>>4 ) | (src[6]<<4)) & 0x07FF;
dst[5] = ((src[6]>>7 ) | (src[7]<<1 ) | (src[8]<<9)) & 0x07FF;
dst[6] = ((src[8]>>2 ) | (src[9]<<6)) & 0x07FF;
dst[7] = ((src[9]>>5) | (src[10]<<3)) & 0x07FF;
dst[8] = ((src[11] ) | (src[12]<<8)) & 0x07FF;
dst[9] = ((src[12]>>3) | (src[13]<<5)) & 0x07FF;
dst[10] = ((src[13]>>6) | (src[14]<<2) | (src[15]<<10)) & 0x07FF;
dst[11] = ((src[15]>>1) | (src[16]<<7)) & 0x07FF;
dst[12] = ((src[16]>>4) | (src[17]<<4)) & 0x07FF;
dst[13] = ((src[17]>>7) | (src[18]<<1) | (src[19]<<9)) & 0x07FF;
dst[14] = ((src[19]>>2) | (src[20]<<6)) & 0x07FF;
dst[15] = ((src[20]>>5) | (src[21]<<3)) & 0x07FF;
// clear bits
memset(dst, 0, SBUS_NB_CHANNEL * sizeof(uint16_t));
// decode sbus data
for (uint8_t i = 0; i < (SBUS_NB_CHANNEL * SBUS_BIT_PER_CHANNEL); i++) {
if (src[byteInRawBuf] & (1 << bitInRawBuf)) {
dst[channel] |= (1 << bitInChannel);
}
bitInRawBuf++;
bitInChannel++;
if (bitInRawBuf == SBUS_BIT_PER_BYTE) {
bitInRawBuf = 0;
byteInRawBuf++;
}
if (bitInChannel == SBUS_BIT_PER_CHANNEL) {
bitInChannel = 0;
// convert sbus to ppm
#if PERIODIC_TELEMETRY
dstppm[channel] = USEC_OF_RC_PPM_TICKS(dst[channel]);
#endif
channel++;
}
for (int channel=0; channel < SBUS_NB_CHANNEL; channel++) {
dstppm[channel] = USEC_OF_RC_PPM_TICKS(dst[channel]);
}
#endif
// test frame lost flag
*available = !bit_is_set(src[SBUS_FLAGS_BYTE], SBUS_FRAME_LOST_BIT);
}
sw/airborne/subsystems/radio_control/sbus_common.h
+3 -1
View File
@@ -29,6 +29,7 @@
#include "std.h"
#include "mcu_periph/uart.h"
#include "mcu_periph/gpio.h"
/* in case you want to override RADIO_CONTROL_NB_CHANNEL */
#include "generated/airframe.h"
@@ -87,7 +88,8 @@ struct Sbus {
/**
* Init function
*/
void sbus_common_init(struct Sbus *sbus, struct uart_periph *dev);
void sbus_common_init(struct Sbus *sbus, struct uart_periph *dev,
gpio_port_t gpio_polarity_port, uint16_t gpio_polarity_pin);
/**
* Decoding event function
sw/airborne/subsystems/radio_control/sbus_dual.c
+15 -3
View File
@@ -28,9 +28,21 @@
#include "subsystems/radio_control/sbus_dual.h"
#include BOARD_CONFIG
#include "mcu_periph/uart.h"
#include "mcu_periph/gpio.h"
#include <string.h>
#ifndef RC_POLARITY_GPIO_PORT
#define RC_POLARITY_GPIO_PORT 0
#endif
#ifndef RC_POLARITY_GPIO_PIN
#define RC_POLARITY_GPIO_PIN 0
#endif
#ifndef RC2_POLARITY_GPIO_PORT
#define RC2_POLARITY_GPIO_PORT RC_POLARITY_GPIO_PORT
#endif
#ifndef RC2_POLARITY_GPIO_PIN
#define RC2_POLARITY_GPIO_PIN RC_POLARITY_GPIO_PIN
#endif
/** SBUS struct */
struct Sbus sbus1, sbus2;
@@ -50,8 +62,8 @@ static void send_sbus(struct transport_tx *trans, struct link_device *dev)
// Init function
void radio_control_impl_init(void)
{
sbus_common_init(&sbus1, &SBUS1_UART_DEV);
sbus_common_init(&sbus2, &SBUS2_UART_DEV);
sbus_common_init(&sbus1, &SBUS1_UART_DEV, RC_POLARITY_GPIO_PORT, RC_POLARITY_GPIO_PIN);
sbus_common_init(&sbus2, &SBUS2_UART_DEV, RC2_POLARITY_GPIO_PORT, RC2_POLARITY_GPIO_PIN);
// Register telemetry message
#if PERIODIC_TELEMETRY
sw/ext/chibios
+1 -1
Submodule sw/ext/chibios updated: 024738d265...0db56fc105