From 478631a28c48792ce6d57657e5f0428decfad08b Mon Sep 17 00:00:00 2001 From: Gautier Hattenberger Date: Tue, 19 Apr 2011 14:55:55 +0200 Subject: [PATCH] new uart driver parted for stm32, still working with lpc, needs to be tested on stm32 --- sw/airborne/arch/lpc21/mcu_periph/uart_arch.c | 2 +- sw/airborne/arch/stm32/mcu_periph/uart_arch.c | 506 ++++-------------- sw/airborne/arch/stm32/mcu_periph/uart_arch.h | 88 +-- sw/airborne/mcu_periph/uart.c | 4 + sw/airborne/mcu_periph/uart.h | 21 +- 5 files changed, 122 insertions(+), 499 deletions(-) diff --git a/sw/airborne/arch/lpc21/mcu_periph/uart_arch.c b/sw/airborne/arch/lpc21/mcu_periph/uart_arch.c index 6f7472932a..3e2071cfcc 100644 --- a/sw/airborne/arch/lpc21/mcu_periph/uart_arch.c +++ b/sw/airborne/arch/lpc21/mcu_periph/uart_arch.c @@ -30,7 +30,7 @@ #include "armVIC.h" -void uart_periph_init_param(struct uart_periph* p, uint16_t baud, uint8_t mode, uint8_t fmode, char * dev) { +void uart_periph_init_param(struct uart_periph* p, uint32_t baud, uint8_t mode, uint8_t fmode, char * dev) { ((uartRegs_t *)(p->reg_addr))->ier = 0x00; // disable all interrupts ((uartRegs_t *)(p->reg_addr))->iir; // clear interrupt ID diff --git a/sw/airborne/arch/stm32/mcu_periph/uart_arch.c b/sw/airborne/arch/stm32/mcu_periph/uart_arch.c index e0406d9c85..8461cbd62d 100644 --- a/sw/airborne/arch/stm32/mcu_periph/uart_arch.c +++ b/sw/airborne/arch/stm32/mcu_periph/uart_arch.c @@ -30,28 +30,98 @@ #include "std.h" #include "pprz_baudrate.h" +void uart_periph_init_param(struct uart_periph* p, uint32_t baud, uint8_t mode, uint8_t fmode, char * dev) { + + /* Configure USART */ + USART_InitTypeDef usart; + usart.USART_BaudRate = baud; + usart.USART_WordLength = USART_WordLength_8b; // TODO mode, fmode + usart.USART_StopBits = USART_StopBits_1; + usart.USART_Parity = USART_Parity_No; + usart.USART_HardwareFlowControl = USART_HardwareFlowControl_None; + usart.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; + USART_Init(p->reg_addr, &usart); + /* Enable USART1 Receive interrupts */ + USART_ITConfig(p->reg_addr, USART_IT_RXNE, ENABLE); + + pprz_usart_set_baudrate(p->reg_addr, UART1_BAUD); + + /* Enable the USART */ + USART_Cmd(p->reg_addr, ENABLE); + +} + +void uart_transmit(struct uart_periph* p, uint8_t data ) { + + uint16_t temp = (p->tx_insert_idx + 1) % UART_TX_BUFFER_SIZE; + + if (temp == p->tx_extract_idx) + return; // no room + + USART_ITConfig(p->reg_addr, USART_IT_TXE, DISABLE); + + // check if in process of sending data + if (p->tx_running) { // yes, add to queue + p->tx_buffer[p->tx_insert_idx] = data; + p->tx_insert_idx = temp; + } + else { // no, set running flag and write to output register + p->tx_running = TRUE; + USART_SendData(p->reg_addr, data); + } + + USART_ITConfig(p->reg_addr, USART_IT_TXE, ENABLE); + +} + +static inline void usart_irq_handler(struct uart_periph* p) { + + if(USART_GetITStatus(p->reg_addr, USART_IT_TXE) != RESET){ + // check if more data to send + if (p->tx_insert_idx != p->tx_extract_idx) { + USART_SendData(p->reg_addr,p->tx_buffer[p->tx_extract_idx]); + p->tx_extract_idx++; + p->tx_extract_idx %= UART_TX_BUFFER_SIZE; + } + else { + p->tx_running = FALSE; // clear running flag + USART_ITConfig(p->reg_addr, USART_IT_TXE, DISABLE); + } + } + + if(USART_GetITStatus(p->reg_addr, USART_IT_RXNE) != RESET){ + uint16_t temp = (p->rx_insert_idx + 1) % UART_RX_BUFFER_SIZE;; + p->rx_buffer[p->rx_insert_idx] = USART_ReceiveData(p->reg_addr); + // check for more room in queue + if (temp != p->rx_extract_idx) + p->rx_insert_idx = temp; // update insert index + } + +} + +static inline void usart_enable_irq(IRQn_Type IRQn) { + /* Enable USART interrupts */ + NVIC_InitTypeDef nvic; + nvic.NVIC_IRQChannel = IRQn; + nvic.NVIC_IRQChannelPreemptionPriority = 2; + nvic.NVIC_IRQChannelSubPriority = 1; + nvic.NVIC_IRQChannelCmd = ENABLE; + NVIC_Init(&nvic); +} + #ifdef USE_UART1 -volatile uint16_t uart1_rx_insert_idx, uart1_rx_extract_idx; -uint8_t uart1_rx_buffer[UART1_RX_BUFFER_SIZE]; - -volatile uint16_t uart1_tx_insert_idx, uart1_tx_extract_idx; -volatile bool_t uart1_tx_running; -uint8_t uart1_tx_buffer[UART1_TX_BUFFER_SIZE]; - - void uart1_init( void ) { + + uart_periph_init(&uart1); + uart1.reg_addr = USART1; + /* init RCC */ RCC_APB2PeriphClockCmd(RCC_APB2Periph_USART1, ENABLE); RCC_APB2PeriphClockCmd(UART1_Periph, ENABLE); /* Enable USART1 interrupts */ - NVIC_InitTypeDef nvic; - nvic.NVIC_IRQChannel = USART1_IRQn; - nvic.NVIC_IRQChannelPreemptionPriority = 2; - nvic.NVIC_IRQChannelSubPriority = 1; - nvic.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&nvic); + usart_enable_irq(USART1_IRQn); /* Init GPIOS */ GPIO_InitTypeDef gpio; @@ -66,119 +136,26 @@ void uart1_init( void ) { GPIO_Init(UART1_RxPort, &gpio); /* Configure USART1 */ - USART_InitTypeDef usart; - usart.USART_BaudRate = UART1_BAUD; - usart.USART_WordLength = USART_WordLength_8b; - usart.USART_StopBits = USART_StopBits_1; - usart.USART_Parity = USART_Parity_No; - usart.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - usart.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_Init(USART1, &usart); - /* Enable USART1 Receive interrupts */ - USART_ITConfig(USART1, USART_IT_RXNE, ENABLE); - - pprz_usart_set_baudrate(USART1, UART1_BAUD); - - /* Enable the USART1 */ - USART_Cmd(USART1, ENABLE); - - // initialize the transmit data queue - uart1_tx_extract_idx = 0; - uart1_tx_insert_idx = 0; - uart1_tx_running = FALSE; - - // initialize the receive data queue - uart1_rx_extract_idx = 0; - uart1_rx_insert_idx = 0; - -} - -void uart1_transmit( uint8_t data ) { - - uint16_t temp = (uart1_tx_insert_idx + 1) % UART1_TX_BUFFER_SIZE; - - if (temp == uart1_tx_extract_idx) - return; // no room - - USART_ITConfig(USART1, USART_IT_TXE, DISABLE); - - // check if in process of sending data - if (uart1_tx_running) { // yes, add to queue - uart1_tx_buffer[uart1_tx_insert_idx] = data; - uart1_tx_insert_idx = temp; - } - else { // no, set running flag and write to output register - uart1_tx_running = TRUE; - USART_SendData(USART1, data); - } - - USART_ITConfig(USART1, USART_IT_TXE, ENABLE); - -} - -bool_t uart1_check_free_space( uint8_t len) { - int16_t space = uart1_tx_extract_idx - uart1_tx_insert_idx; - if (space <= 0) - space += UART1_TX_BUFFER_SIZE; - return (uint16_t)(space - 1) >= len; -} - -void usart1_irq_handler(void) { - - if(USART_GetITStatus(USART1, USART_IT_TXE) != RESET){ - // check if more data to send - if (uart1_tx_insert_idx != uart1_tx_extract_idx) { - USART_SendData(USART1,uart1_tx_buffer[uart1_tx_extract_idx]); - uart1_tx_extract_idx++; - uart1_tx_extract_idx %= UART1_TX_BUFFER_SIZE; - } - else { - uart1_tx_running = FALSE; // clear running flag - USART_ITConfig(USART1, USART_IT_TXE, DISABLE); - } - } - - if(USART_GetITStatus(USART1, USART_IT_RXNE) != RESET){ - uint16_t temp = (uart1_rx_insert_idx + 1) % UART1_RX_BUFFER_SIZE;; - uart1_rx_buffer[uart1_rx_insert_idx] = USART_ReceiveData(USART1); - // check for more room in queue - if (temp != uart1_rx_extract_idx) - uart1_rx_insert_idx = temp; // update insert index - } - + uart_periph_init_param(&uart1, UART1_BAUD, 0, 0, ""); } +void usart1_irq_handler(void) { usart_irq_handler(&uart1); } #endif /* USE_UART1 */ - - - - - - #ifdef USE_UART2 -volatile uint16_t uart2_rx_insert_idx, uart2_rx_extract_idx; -uint8_t uart2_rx_buffer[UART2_RX_BUFFER_SIZE]; - -volatile uint16_t uart2_tx_insert_idx, uart2_tx_extract_idx; -volatile bool_t uart2_tx_running; -uint8_t uart2_tx_buffer[UART2_TX_BUFFER_SIZE]; - - void uart2_init( void ) { + + uart_periph_init(&uart2); + uart2.reg_addr = USART2; + /* init RCC */ RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART2, ENABLE); RCC_APB2PeriphClockCmd(UART2_Periph, ENABLE); /* Enable USART2 interrupts */ - NVIC_InitTypeDef nvic; - nvic.NVIC_IRQChannel = USART2_IRQn; - nvic.NVIC_IRQChannelPreemptionPriority = 2; - nvic.NVIC_IRQChannelSubPriority = 1; - nvic.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&nvic); + usart_enable_irq(USART2_IRQn); /* Init GPIOS */ GPIO_InitTypeDef gpio; @@ -193,118 +170,27 @@ void uart2_init( void ) { GPIO_Init(UART2_RxPort, &gpio); /* Configure USART2 */ - USART_InitTypeDef usart; - usart.USART_BaudRate = UART2_BAUD; - usart.USART_WordLength = USART_WordLength_8b; - usart.USART_StopBits = USART_StopBits_1; - usart.USART_Parity = USART_Parity_No; - usart.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - usart.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_Init(USART2, &usart); - /* Enable USART2 Receive interrupts */ - USART_ITConfig(USART2, USART_IT_RXNE, ENABLE); - - pprz_usart_set_baudrate(USART2, UART2_BAUD); - - /* Enable the USART2 */ - USART_Cmd(USART2, ENABLE); - - // initialize the transmit data queue - uart2_tx_extract_idx = 0; - uart2_tx_insert_idx = 0; - uart2_tx_running = FALSE; - - // initialize the receive data queue - uart2_rx_extract_idx = 0; - uart2_rx_insert_idx = 0; - -} - -void uart2_transmit( uint8_t data ) { - - uint16_t temp = (uart2_tx_insert_idx + 1) % UART2_TX_BUFFER_SIZE; - - if (temp == uart2_tx_extract_idx) - return; // no room - - USART_ITConfig(USART2, USART_IT_TXE, DISABLE); - - // check if in process of sending data - if (uart2_tx_running) { // yes, add to queue - uart2_tx_buffer[uart2_tx_insert_idx] = data; - uart2_tx_insert_idx = temp; - } - else { // no, set running flag and write to output register - uart2_tx_running = TRUE; - USART_SendData(USART2, data); - } - - USART_ITConfig(USART2, USART_IT_TXE, ENABLE); - -} - -bool_t uart2_check_free_space( uint8_t len) { - int16_t space = uart2_tx_extract_idx - uart2_tx_insert_idx; - if (space <= 0) - space += UART2_TX_BUFFER_SIZE; - return (uint16_t)(space - 1) >= len; -} - -void usart2_irq_handler(void) { - if(USART_GetITStatus(USART2, USART_IT_TXE) != RESET){ - // check if more data to send - if (uart2_tx_insert_idx != uart2_tx_extract_idx) { - USART_SendData(USART2,uart2_tx_buffer[uart2_tx_extract_idx]); - uart2_tx_extract_idx++; - uart2_tx_extract_idx %= UART2_TX_BUFFER_SIZE; - } - else { - uart2_tx_running = FALSE; // clear running flag - USART_ITConfig(USART2, USART_IT_TXE, DISABLE); - } - } - - if(USART_GetITStatus(USART2, USART_IT_RXNE) != RESET){ - uint16_t temp = (uart2_rx_insert_idx + 1) % UART2_RX_BUFFER_SIZE;; - uart2_rx_buffer[uart2_rx_insert_idx] = USART_ReceiveData(USART2); - // check for more room in queue - if (temp != uart2_rx_extract_idx) - uart2_rx_insert_idx = temp; // update insert index - } - + uart_periph_init_param(&uart2, UART2_BAUD, 0, 0, ""); } +void usart2_irq_handler(void) { usart_irq_handler(&uart2); } #endif /* USE_UART2 */ - - - - - #ifdef USE_UART3 -volatile uint16_t uart3_rx_insert_idx, uart3_rx_extract_idx; -uint8_t uart3_rx_buffer[UART3_RX_BUFFER_SIZE]; - -volatile uint16_t uart3_tx_insert_idx, uart3_tx_extract_idx; -volatile bool_t uart3_tx_running; -uint8_t uart3_tx_buffer[UART3_TX_BUFFER_SIZE]; - void uart3_init( void ) { + uart_periph_init(&uart3); + uart3.reg_addr = USART3; + /* init RCC */ RCC_APB1PeriphClockCmd(RCC_APB1Periph_USART3, ENABLE); RCC_APB2PeriphClockCmd(RCC_APB2Periph_AFIO, ENABLE); RCC_APB2PeriphClockCmd(UART3_Periph, ENABLE); /* Enable USART3 interrupts */ - NVIC_InitTypeDef nvic; - nvic.NVIC_IRQChannel = USART3_IRQn; - nvic.NVIC_IRQChannelPreemptionPriority = 2; - nvic.NVIC_IRQChannelSubPriority = 1; - nvic.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&nvic); + usart_enable_irq(USART3_IRQn); /* Init GPIOS */ GPIO_PinRemapConfig(GPIO_PartialRemap_USART3, ENABLE); @@ -320,114 +206,27 @@ void uart3_init( void ) { GPIO_Init(UART3_RxPort, &gpio); /* Configure USART3 */ - USART_InitTypeDef usart; - usart.USART_BaudRate = UART3_BAUD; - usart.USART_WordLength = USART_WordLength_8b; - usart.USART_StopBits = USART_StopBits_1; - usart.USART_Parity = USART_Parity_No; - usart.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - usart.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_Init(USART3, &usart); - /* Enable USART3 Receive interrupts */ - USART_ITConfig(USART3, USART_IT_RXNE, ENABLE); - - pprz_usart_set_baudrate(USART3, UART3_BAUD); - - /* Enable the USART3 */ - USART_Cmd(USART3, ENABLE); - - // initialize the transmit data queue - uart3_tx_extract_idx = 0; - uart3_tx_insert_idx = 0; - uart3_tx_running = FALSE; - - // initialize the receive data queuenn - uart3_rx_extract_idx = 0; - uart3_rx_insert_idx = 0; - -} - -void uart3_transmit( uint8_t data ) { - - uint16_t temp = (uart3_tx_insert_idx + 1) % UART3_TX_BUFFER_SIZE; - - if (temp == uart3_tx_extract_idx) - return; // no room - - USART_ITConfig(USART3, USART_IT_TXE, DISABLE); - - // check if in process of sending data - if (uart3_tx_running) { // yes, add to queue - uart3_tx_buffer[uart3_tx_insert_idx] = data; - uart3_tx_insert_idx = temp; - } - else { // no, set running flag and write to output register - uart3_tx_running = TRUE; - USART_SendData(USART3, data); - } - USART_ITConfig(USART3, USART_IT_TXE, ENABLE); - -} - -bool_t uart3_check_free_space( uint8_t len) { - int16_t space = uart3_tx_extract_idx - uart3_tx_insert_idx; - if (space <= 0) - space += UART3_TX_BUFFER_SIZE; - return (uint16_t)(space - 1) >= len; -} - - -void usart3_irq_handler(void) { - - if(USART_GetITStatus(USART3, USART_IT_TXE) != RESET){ - // check if more data to send - if (uart3_tx_insert_idx != uart3_tx_extract_idx) { - USART_SendData(USART3,uart3_tx_buffer[uart3_tx_extract_idx]); - uart3_tx_extract_idx++; - uart3_tx_extract_idx %= UART3_TX_BUFFER_SIZE; - } - else { - uart3_tx_running = FALSE; // clear running flag - USART_ITConfig(USART3, USART_IT_TXE, DISABLE); - } - } - - if(USART_GetITStatus(USART3, USART_IT_RXNE) != RESET){ - uint16_t temp = (uart3_rx_insert_idx + 1) % UART3_RX_BUFFER_SIZE;; - uart3_rx_buffer[uart3_rx_insert_idx] = USART_ReceiveData(USART3); - // check for more room in queue - if (temp != uart3_rx_extract_idx) - uart3_rx_insert_idx = temp; // update insert index - } - + uart_periph_init_param(&uart3, UART3_BAUD, 0, 0, ""); } +void usart3_irq_handler(void) { usart_irq_handler(&uart3); } #endif /* USE_UART3 */ #ifdef USE_UART5 -volatile uint16_t uart5_rx_insert_idx, uart5_rx_extract_idx; -uint8_t uart5_rx_buffer[UART5_RX_BUFFER_SIZE]; - -volatile uint16_t uart5_tx_insert_idx, uart5_tx_extract_idx; -volatile bool_t uart5_tx_running; -uint8_t uart5_tx_buffer[UART5_TX_BUFFER_SIZE]; - void uart5_init( void ) { + uart_periph_init(&uart5); + uart5.reg_addr = USART5; + /* init RCC */ RCC_APB1PeriphClockCmd(RCC_APB1Periph_UART5, ENABLE); RCC_APB2PeriphClockCmd(UART5_PeriphTx, ENABLE); RCC_APB2PeriphClockCmd(UART5_PeriphRx, ENABLE); /* Enable UART5 interrupts */ - NVIC_InitTypeDef nvic; - nvic.NVIC_IRQChannel = UART5_IRQn; - nvic.NVIC_IRQChannelPreemptionPriority = 2; - nvic.NVIC_IRQChannelSubPriority = 1; - nvic.NVIC_IRQChannelCmd = ENABLE; - NVIC_Init(&nvic); + usart_enable_irq(USART5_IRQn); /* Init GPIOS */ GPIO_InitTypeDef gpio; @@ -442,105 +241,10 @@ void uart5_init( void ) { GPIO_Init(UART5_RxPort, &gpio); /* Configure UART5 */ - USART_InitTypeDef usart; - usart.USART_BaudRate = UART5_BAUD; - usart.USART_WordLength = USART_WordLength_8b; - usart.USART_StopBits = USART_StopBits_1; - usart.USART_Parity = USART_Parity_No; - usart.USART_HardwareFlowControl = USART_HardwareFlowControl_None; - usart.USART_Mode = USART_Mode_Rx | USART_Mode_Tx; - USART_Init(USART5, &usart); - /* Enable UART5 Receive interrupts */ - USART_ITConfig(UART5, USART_IT_RXNE, ENABLE); - - pprz_usart_set_baudrate(UART5, UART5_BAUD); - - /* Enable the UART5 */ - USART_Cmd(UART5, ENABLE); - - // initialize the transmit data queue - uart5_tx_extract_idx = 0; - uart5_tx_insert_idx = 0; - uart5_tx_running = FALSE; - - // initialize the receive data queuenn - uart5_rx_extract_idx = 0; - uart5_rx_insert_idx = 0; - -} - -void uart5_transmit( uint8_t data ) { - - uint16_t temp = (uart5_tx_insert_idx + 1) % UART5_TX_BUFFER_SIZE; - - if (temp == uart5_tx_extract_idx) - return; // no room - - USART_ITConfig(USART5, USART_IT_TXE, DISABLE); - - // check if in process of sending data - if (uart5_tx_running) { // yes, add to queue - uart5_tx_buffer[uart5_tx_insert_idx] = data; - uart5_tx_insert_idx = temp; - } - else { // no, set running flag and write to output register - uart5_tx_running = TRUE; - USART_SendData(USART5, data); - } - USART_ITConfig(USART5, USART_IT_TXE, ENABLE); - -} - -bool_t uart5_check_free_space( uint8_t len) { - int16_t space = uart5_tx_extract_idx - uart5_tx_insert_idx; - if (space <= 0) - space += UART5_TX_BUFFER_SIZE; - return (uint16_t)(space - 1) >= len; -} - - -void usart5_irq_handler(void) { - - if(USART_GetITStatus(USART5, USART_IT_TXE) != RESET){ - // check if more data to send - if (uart5_tx_insert_idx != uart5_tx_extract_idx) { - USART_SendData(USART5,uart5_tx_buffer[uart5_tx_extract_idx]); - uart5_tx_extract_idx++; - uart5_tx_extract_idx %= UART5_TX_BUFFER_SIZE; - } - else { - uart5_tx_running = FALSE; // clear running flag - USART_ITConfig(USART5, USART_IT_TXE, DISABLE); - } - } - - if(USART_GetITStatus(USART5, USART_IT_RXNE) != RESET){ - uint16_t temp = (uart5_rx_insert_idx + 1) % UART5_RX_BUFFER_SIZE;; - uart5_rx_buffer[uart5_rx_insert_idx] = USART_ReceiveData(USART5); - // check for more room in queue - if (temp != uart5_rx_extract_idx) - uart5_rx_insert_idx = temp; // update insert index - } - + uart_periph_init_param(&uart5, UART5_BAUD, 0, 0, ""); } +void usart5_irq_handler(void) { usart_irq_handler(&uart5); } #endif /* USE_UART5 */ -void uart_init( void ) -{ -#ifdef USE_UART1 - uart1_init(); -#endif -#ifdef USE_UART2 - uart2_init(); -#endif -#ifdef USE_UART3 - uart3_init(); -#endif -#ifdef USE_UART5 - uart5_init(); -#endif -} - - diff --git a/sw/airborne/arch/stm32/mcu_periph/uart_arch.h b/sw/airborne/arch/stm32/mcu_periph/uart_arch.h index 3d7113ef42..420086f854 100644 --- a/sw/airborne/arch/stm32/mcu_periph/uart_arch.h +++ b/sw/airborne/arch/stm32/mcu_periph/uart_arch.h @@ -125,92 +125,6 @@ extern void usart3_irq_handler(void); extern void usart5_irq_handler(void); #endif -#ifdef USE_UART1 -#define UART1_RX_BUFFER_SIZE 128 -#define UART1_TX_BUFFER_SIZE 128 - -extern volatile uint16_t uart1_rx_insert_idx, uart1_rx_extract_idx; -extern uint8_t uart1_rx_buffer[UART1_RX_BUFFER_SIZE]; - -extern volatile uint16_t uart1_tx_insert_idx, uart1_tx_extract_idx; -extern volatile bool_t uart1_tx_running; -extern uint8_t uart1_tx_buffer[UART1_TX_BUFFER_SIZE]; - -#define Uart1ChAvailable() (uart1_rx_insert_idx != uart1_rx_extract_idx) -#define Uart1Getch() ({ \ - uint8_t ret = uart1_rx_buffer[uart1_rx_extract_idx]; \ - uart1_rx_extract_idx = (uart1_rx_extract_idx + 1)%UART1_RX_BUFFER_SIZE; \ - ret; \ - }) - -#endif /* USE_UART1 */ - - -#ifdef USE_UART2 - -#define UART2_RX_BUFFER_SIZE 128 -#define UART2_TX_BUFFER_SIZE 128 - -extern volatile uint16_t uart2_rx_insert_idx, uart2_rx_extract_idx; -extern uint8_t uart2_rx_buffer[UART2_RX_BUFFER_SIZE]; - -extern volatile uint16_t uart2_tx_insert_idx, uart2_tx_extract_idx; -extern volatile bool_t uart2_tx_running; -extern uint8_t uart2_tx_buffer[UART2_TX_BUFFER_SIZE]; - -#define Uart2ChAvailable() (uart2_rx_insert_idx != uart2_rx_extract_idx) -#define Uart2Getch() ({ \ - uint8_t ret = uart2_rx_buffer[uart2_rx_extract_idx]; \ - uart2_rx_extract_idx = (uart2_rx_extract_idx + 1)%UART2_RX_BUFFER_SIZE; \ - ret; \ - }) - -#endif /* USE_UART2 */ - - -#ifdef USE_UART3 - -#define UART3_RX_BUFFER_SIZE 128 -#define UART3_TX_BUFFER_SIZE 128 - -extern volatile uint16_t uart3_rx_insert_idx, uart3_rx_extract_idx; -extern uint8_t uart3_rx_buffer[UART3_RX_BUFFER_SIZE]; - -extern volatile uint16_t uart3_tx_insert_idx, uart3_tx_extract_idx; -extern volatile bool_t uart3_tx_running; -extern uint8_t uart3_tx_buffer[UART3_TX_BUFFER_SIZE]; - -#define Uart3ChAvailable() (uart3_rx_insert_idx != uart3_rx_extract_idx) -#define Uart3Getch() ({ \ - uint8_t ret = uart3_rx_buffer[uart3_rx_extract_idx]; \ - uart3_rx_extract_idx = (uart3_rx_extract_idx + 1)%UART3_RX_BUFFER_SIZE; \ - ret; \ - }) - -#endif /* USE_UART3 */ - -#ifdef USE_UART5 - -#define UART5_RX_BUFFER_SIZE 128 -#define UART5_TX_BUFFER_SIZE 128 - -extern volatile uint16_t uart5_rx_insert_idx, uart5_rx_extract_idx; -extern uint8_t uart5_rx_buffer[UART5_RX_BUFFER_SIZE]; - -extern volatile uint16_t uart5_tx_insert_idx, uart5_tx_extract_idx; -extern volatile bool_t uart5_tx_running; -extern uint8_t uart5_tx_buffer[UART5_TX_BUFFER_SIZE]; - -#define Uart5ChAvailable() (uart5_rx_insert_idx != uart5_rx_extract_idx) -#define Uart5Getch() ({ \ - uint8_t ret = uart5_rx_buffer[uart5_rx_extract_idx]; \ - uart5_rx_extract_idx = (uart5_rx_extract_idx + 1)%UART5_RX_BUFFER_SIZE; \ - ret; \ - }) - -#endif /* USE_UART5 */ - - -void uart_init( void ); +//void uart_init( void ); #endif /* STM32_UART_ARCH_H */ diff --git a/sw/airborne/mcu_periph/uart.c b/sw/airborne/mcu_periph/uart.c index c17d790835..7391225f4b 100644 --- a/sw/airborne/mcu_periph/uart.c +++ b/sw/airborne/mcu_periph/uart.c @@ -40,6 +40,10 @@ struct uart_periph uart2; struct uart_periph uart3; #endif +#ifdef USE_UART5 +struct uart_periph uart5; +#endif + void uart_periph_init(struct uart_periph* p) { p->rx_insert_idx = 0; p->rx_extract_idx = 0; diff --git a/sw/airborne/mcu_periph/uart.h b/sw/airborne/mcu_periph/uart.h index eaaee1fcd4..26eb5ec18d 100644 --- a/sw/airborne/mcu_periph/uart.h +++ b/sw/airborne/mcu_periph/uart.h @@ -54,7 +54,7 @@ struct uart_periph { }; extern void uart_periph_init(struct uart_periph* p); -extern void uart_periph_init_param(struct uart_periph* p, uint16_t baud, uint8_t mode, uint8_t fmode, char * dev); +extern void uart_periph_init_param(struct uart_periph* p, uint32_t baud, uint8_t mode, uint8_t fmode, char * dev); extern void uart_transmit(struct uart_periph* p, uint8_t data); extern bool_t uart_check_free_space(struct uart_periph* p, uint8_t len); @@ -156,16 +156,17 @@ extern void uart3_init(void); #endif // USE_UART3 #ifdef USE_UART5 +extern struct uart_periph uart5; +extern void uart5_init(void); -//TODO adapt to new driver -extern void uart5_init( void ); -extern void uart5_transmit( uint8_t data ); -extern bool_t uart5_check_free_space( uint8_t len); - -#define Uart5Init uart5_init -#define Uart5CheckFreeSpace(_x) uart5_check_free_space(_x) -#define Uart5Transmit(_x) uart5_transmit(_x) +#define Uart5Init() uart_periph_init(&uart5) +#define Uart5CheckFreeSpace(_x) uart_check_free_space(&uart5, _x) +#define Uart5Transmit(_x) uart_transmit(&uart5, _x) #define Uart5SendMessage() {} +#define Uart5ChAvailable() UartChAvailable(uart5) +#define Uart5Getch() UartGetch(uart5) +#define Uart5TxRunning uart5.tx_running +#define Uart5InitParam(_b, _m, _fm) uart_periph_init_param(&uart5, _b, _m, _fm, "") #define UART5Init Uart5Init #define UART5CheckFreeSpace Uart5CheckFreeSpace @@ -174,6 +175,6 @@ extern bool_t uart5_check_free_space( uint8_t len); #define UART5ChAvailable Uart5ChAvailable #define UART5Getch Uart5Getch -#endif /* USE_UART5 */ +#endif // USE_UART5 #endif /* MCU_PERIPH_UART_H */