diff --git a/conf/airframes/OPENUAS/openuas_zohd_talon_nano.xml b/conf/airframes/OPENUAS/openuas_zohd_talon_nano.xml
new file mode 100644
index 0000000000..68e7e29a26
--- /dev/null
+++ b/conf/airframes/OPENUAS/openuas_zohd_talon_nano.xml
@@ -0,0 +1,463 @@
+
+
+
+ + Fun airframe to test some OSD functionality and Matek H734 Wing v3 FC
+
+ + MODEL: ZoHD Talon Nano
+ + FLIGHTCONTROLLER: Mateksys H734 Wing v3
+ + IMU: ICM42688
+ + ACTUATORS: Corona DS-919 and CS-929 MG
+ + GNSS uBlox M10 GNSS
+ + MAGNETOMETER QMC5883L
+ + ESC: HAKRC 50A with AM32 firmware
+ + RCRX: OpenR-XSR
+ + AIRSPEED: OPT: Sensirion SDP33
+ + TELEMETRY: ESP32 C3 WiFi Modem
+ + BARO: OPT: B310 on FC
+ + CURRENT: FC onboard sensor on the default analog ports
+ + RANGEFINDER: OPT: TF-Luna on I2C
+ + MOTOR: Kv 2600 rpm V Outrunner Brushless
+ + PROPELLER: Default 2 Blade 6in x 3in Left
+ + BATTERY: 21700 Li-Ion 3S1P INR21700M58T 5650mAh
+
+NOTES:
+ + Flightcontroller rotated 90deg Clockwise, the I2C and CAN bus connectors point to front of aircraft
+ + Engine battery voltage and current values via FC build in sensor
+ + Servos powered via 2nd BEC of the FC powerboard, FC sensors via BEC
+ + Flashing the firmware can be done via original STM32 Bootloader
+ Simply, press bootbutton, USB cable in, upload.. voila PPRZ aircraft flashed
+ + A GNSS device with magnetometer is used
+ + On I2C2 we can have the airspeed sensor
+
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diff --git a/conf/boards/matek_h743_wing.makefile b/conf/boards/matek_h743_wing.makefile
new file mode 100644
index 0000000000..699dc5fede
--- /dev/null
+++ b/conf/boards/matek_h743_wing.makefile
@@ -0,0 +1,86 @@
+# Hey Emacs, this is a -*- makefile -*-
+#
+# matek_h743_wing.makefile
+#
+# This is for the Flight Controller Matek H743 WING
+# See http://www.mateksys.com/?portfolio=h743-wing for details
+#
+
+BOARD=mateksys
+BOARD_VERSION=H743-WING
+BOARD_DIR=$(BOARD)/$(BOARD_VERSION)
+BOARD_CFG=\"arch/chibios/common_board.h\"
+
+ARCH=chibios
+$(TARGET).ARCHDIR = $(ARCH)
+
+RTOS=chibios
+MCU=cortex-m7
+
+# FPU on H7
+USE_FPU=hard
+USE_FPU_OPT= -mfpu=fpv5-d16
+
+USE_LTO ?= yes
+
+$(TARGET).CFLAGS += -DPPRZLINK_ENABLE_FD
+
+##############################################################################
+# Architecture or project specific options
+#
+# Define project name here (target)
+PROJECT = $(TARGET)
+
+# Project specific files and paths (see Makefile.chibios for details)
+CHIBIOS_BOARD_PLATFORM = STM32H7xx/platform.mk
+CHIBIOS_LINKER_DIR = $(PAPARAZZI_SRC)/sw/airborne/arch/chibios/
+CHIBIOS_BOARD_LINKER = STM32H743xI_nobl_nc.ld
+CHIBIOS_BOARD_STARTUP = startup_stm32h7xx.mk
+
+##############################################################################
+# Compiler settings
+#
+
+# default flash mode is the DFU
+# possibilities: DFU-UTIL, SWD, PX4 bootloader
+FLASH_MODE ?= DFU-UTIL
+DFU_ADDR = 0x08000000
+PX4_TARGET = "ap"
+PX4_PROTOTYPE ?= "${PAPARAZZI_HOME}/sw/tools/px4/matek_h743_slim.prototype"
+PX4_BL_PORT ?= "/dev/serial/by-id/*MatekH743*"
+
+#
+# default LED configuration
+#
+SDLOG_LED ?= none
+RADIO_CONTROL_LED ?= none
+BARO_LED ?= none
+AHRS_ALIGNER_LED ?= 2
+GPS_LED ?= none
+SYS_TIME_LED ?= 1
+
+#
+# default UART configuration (modem, gps, spektrum)
+#
+SBUS_PORT ?= UART6
+RADIO_CONTROL_SPEKTRUM_PRIMARY_PORT ?= UART6
+
+MODEM_PORT ?= UART7
+MODEM_BAUD ?= B57600
+
+#TELEM1 ?= MODEM_PORT
+#TELEM2 ?= UART1
+
+GPS_PORT ?= UART2
+GPS_BAUD ?= B57600
+
+#
+# default actuator configuration
+#
+# you can use different actuators by adding a configure option to your firmware section
+# e.g.
+#
+ACTUATORS ?= actuators_pwm
+
diff --git a/conf/userconf/OPENUAS/openuas_conf.xml b/conf/userconf/OPENUAS/openuas_conf.xml
index 60dcf92d1a..4975e1e538 100644
--- a/conf/userconf/OPENUAS/openuas_conf.xml
+++ b/conf/userconf/OPENUAS/openuas_conf.xml
@@ -1,4 +1,15 @@
+
['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
+# 'ADC' => ['ANALOG', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_LOW'],
+# 'PWM' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_LOW'],
+# 'ICU' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
+# 'I2C' => ['ALTERNATE', 'OPENDRAIN', 'SPEED_HIGH', 'PULLUP', 'LEVEL_HIGH'],
+# 'SPI' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
+# 'UART' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'PULLUP', 'LEVEL_HIGH'],
+# 'OTG' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
+# 'ETH' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
+# 'FSMC' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
+# 'SDIO' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'PULLUP', 'LEVEL_HIGH'],
+# 'SDIOCK' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
+# 'CAN' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
+# 'DCMI' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
+# 'LED' => ['OUTPUT', 'PUSHPULL', 'SPEED_VERYLOW', 'FLOATING', 'LEVEL_LOW'],
+# 'PASSIVE' => ['INPUT', 'PUSHPULL', 'SPEED_VERYLOW', 'FLOATING', 'LEVEL_LOW']);
+#
+# SYSTEM
+A13 SWDIO SYS AF:DEBUG_JTMS-SWDIO
+A14 SWCLK SYS AF:DEBUG_JTCK-SWCLK
+H00 OSC_IN SYS AF0
+H01 OSC_OUT SYS AF0
+
+# DEFAULT
+DEFAULT INPUT PUSHPULL SPEED_VERYLOW PULLDOWN LEVEL_LOW AF0
+
+# ACTIVE PINS
+PA00 SERVO3 PWM AF:TIM5_CH1 ()
+PA01 SERVO4 PWM AF:TIM5_CH2 ()
+PA02 SERVO5 PWM AF:TIM5_CH3 ()
+PA03 SERVO6 PWM AF:TIM5_CH4 ()
+PA04 ADC3 ADC ADC1_INP18 () # Vbat 2 0-69 V, scale 210
+PA05 SPI1_SCK SPI AF:SPI1_SCK # MPU6000
+PA06 SPI1_MISO SPI AF:SPI1_MISO # MPU6000
+PA07 ADC4 ADC ADC1_INP7 () # Current 2 0-3.3V
+PA08 LED_WS2812 PWM AF:TIM1_CH1 ()
+PA09 UART1_TX UART AF:USART1_TX
+PA10 UART1_RX UART AF:USART1_RX
+PA11 USB_DM OTG AF:USB_OTG_FS_DM
+PA12 USB_DP OTG AF:USB_OTG_FS_DP
+PA15 ALARM PWM AF:TIM2_CH1 ()
+
+PB00 SERVO1 PWM AF:TIM3_CH3 ()
+PB01 SERVO2 PWM AF:TIM3_CH4 ()
+PB03 SPI3_SCK SPI AF:SPI3_SCK # SPI external
+PB04 SPI3_MISO SPI AF:SPI3_MISO # SPI external
+PB05 SPI3_MOSI SPI AF:SPI3_MOSI # SPI external
+PB06 I2C1_SCL I2C AF:I2C1_SCL
+PB07 I2C1_SDA I2C AF:I2C1_SDA
+PB08 UART4_RX UART AF:UART4_RX
+PB09 UART4_TX UART AF:UART4_TX
+PB10 I2C2_SCL I2C AF:I2C2_SCL
+PB11 I2C2_SDA I2C AF:I2C2_SDA
+PB12 SPI_SLAVE4 OUTPUT PUSHPULL SPEED_HIGH FLOATING LEVEL_HIGH # MAX7456 OSD CS
+PB13 SPI2_SCK SPI AF:SPI2_SCK # OSD
+PB14 SPI2_MISO SPI AF:SPI2_MISO # OSD
+PB15 SPI2_MOSI SPI AF:SPI2_MOSI # OSD
+
+PC00 ADC5 ADC ADC1_INP10 () # Vbat 0-36 V, scale 110
+PC01 ADC6 ADC ADC1_INP11 () # Current 0-3.3V
+PC05 ADC1 ADC ADC1_INP8 () # RSSI 0-3.3V
+PC04 ADC2 ADC ADC1_INP4 () # AirS 0-6.6V
+PC06 UART6_TX UART AF:USART6_TX
+PC07 UART6_RX UART AF:USART6_RX
+PC08 SDIO_D0 SDIO AF:SDMMC1_D0
+PC09 SDIO_D1 SDIO AF:SDMMC1_D1
+PC10 SDIO_D2 SDIO AF:SDMMC1_D2
+PC11 SDIO_D3 SDIO AF:SDMMC1_D3
+PC12 SDIO_CK SDIOCK AF:SDMMC1_CK
+PC13 SPI_SLAVE6 OUTPUT PUSHPULL SPEED_HIGH FLOATING LEVEL_HIGH # ICM42605 CS (backup ICM20602 on spi4)
+PC15 SPI_SLAVE5 OUTPUT PUSHPULL SPEED_HIGH FLOATING LEVEL_HIGH # INV MPU_CS
+
+PD00 CAN1_RX CAN AF:FDCAN1_RX
+PD01 CAN1_TX CAN AF:FDCAN1_TX
+PD02 SDIO_CMD SDIO AF:SDMMC1_CMD
+PD04 SPI_SLAVE1 OUTPUT PUSHPULL SPEED_HIGH FLOATING LEVEL_HIGH # external CS1
+PD05 UART2_TX UART AF:USART2_TX
+PD06 UART2_RX UART AF:USART2_RX
+PD07 SPI1_MOSI SPI AF:SPI1_MOSI # MPU6000
+PD08 UART3_TX UART AF:USART3_TX
+PD09 UART3_RX UART AF:USART3_RX
+PD12 SERVO7 PWM AF:TIM4_CH1 ()
+PD13 SERVO8 PWM AF:TIM4_CH2 ()
+PD14 SERVO9 PWM AF:TIM4_CH3 ()
+PD15 SERVO10 PWM AF:TIM4_CH4 () # NO DMA
+
+PE00 UART8_RX UART AF:UART8_RX
+PE01 UART8_TX UART AF:UART8_TX
+PE02 SPI_SLAVE2 OUTPUT PUSHPULL SPEED_HIGH FLOATING LEVEL_HIGH # external CS2
+PE03 LED1 LED # blue (marked as ACT)
+PE04 LED2 LED # green (marked as B/E)
+PE05 SERVO11 PWM AF:TIM15_CH1 ()
+PE06 SERVO12 PWM AF:TIM15_CH2 ()
+PE07 UART7_RX UART AF:UART7_RX
+PE08 UART7_TX UART AF:UART7_TX
+PE09 UART7_RTS PASSIVE
+PE10 UART7_CTS PASSIVE
+PE11 SPI_SLAVE3 OUTPUT PUSHPULL SPEED_HIGH FLOATING LEVEL_HIGH # ICM20602 CS
+PE12 SPI4_CLK SPI AF:SPI4_SCK # ICM
+PE13 SPI4_MISO SPI AF:SPI4_MISO # ICM
+PE14 SPI4_MOSI SPI AF:SPI4_MOSI # ICM
+
+# GROUPS
+GROUP ENERGY_SAVE_INPUTS %NAME=~/^SERVO[0-9]+|LED[0-9]+|SPI_SLAVE[0-9]+$/
+GROUP ENERGY_SAVE_LOWS %NAME=~/^VDD_3V3_SENSORS_EN|VDD_5V_PERIPH_EN|PWM_VOLT_SEL|ALARM$/
diff --git a/sw/airborne/boards/mateksys/H743-WING/board.h b/sw/airborne/boards/mateksys/H743-WING/board.h
new file mode 100644
index 0000000000..bc4c29d671
--- /dev/null
+++ b/sw/airborne/boards/mateksys/H743-WING/board.h
@@ -0,0 +1,1745 @@
+/*
+ ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#pragma once
+
+/*
+ * Board identifier.
+ */
+#define BOARD_MATEKH743_SLIM
+#define BOARD_NAME "MATEKSYS FC H743 SLIM"
+
+/*
+ * Board oscillators-related settings.
+ */
+#if !defined(STM32_LSECLK)
+#define STM32_LSECLK 32768U
+#endif
+
+#define STM32_LSEDRV (3U << 3U)
+
+#if !defined(STM32_HSECLK)
+#define STM32_HSECLK 8000000U
+#endif
+
+/*
+ * MCU type as defined in the ST header.
+ */
+#define STM32H743xx
+
+/* allow to define ADC_CHANNEL_VSUPPLY in the airframe file*/
+#ifndef ADC_CHANNEL_VSUPPLY
+#define ADC_CHANNEL_VSUPPLY ADC_5
+#endif
+
+/* Default powerbrick values */
+#define DefaultVoltageOfAdc(adc) ((3.3f/65536.0f) * 11.00f * adc)
+#define DefaultMilliAmpereOfAdc(adc) ((3.3f/65536.0f) * 39.877f * adc)
+
+/* Battery monitoring for file closing */
+#define SDLOG_BAT_ADC ADCD1
+#define SDLOG_BAT_CHAN AD1_5_CHANNEL
+
+/*
+ * PWM TIM defines
+ * enable TIM 3, 4 and 5 by default
+ */
+#ifndef USE_PWM_TIM3
+#define USE_PWM_TIM3 1
+#endif
+
+#ifndef USE_PWM_TIM4
+#define USE_PWM_TIM4 1
+#endif
+
+#ifndef USE_PWM_TIM5
+#define USE_PWM_TIM5 1
+#endif
+
+/*
+ * IO pins assignments.
+ */
+#define PA00_SERVO3 0U
+#define PA01_SERVO4 1U
+#define PA02_SERVO5 2U
+#define PA03_SERVO6 3U
+#define PA04_ADC3 4U
+#define PA05_SPI1_SCK 5U
+#define PA06_SPI1_MISO 6U
+#define PA07_ADC4 7U
+#define PA08_LED_WS2812 8U
+#define PA09_UART1_TX 9U
+#define PA10_UART1_RX 10U
+#define PA11_USB_DM 11U
+#define PA12_USB_DP 12U
+#define PA13_SWDIO 13U
+#define PA14_SWCLK 14U
+#define PA15_ALARM 15U
+
+#define PB00_SERVO1 0U
+#define PB01_SERVO2 1U
+#define PB02 2U
+#define PB03_SPI3_SCK 3U
+#define PB04_SPI3_MISO 4U
+#define PB05_SPI3_MOSI 5U
+#define PB06_I2C1_SCL 6U
+#define PB07_I2C1_SDA 7U
+#define PB08_UART4_RX 8U
+#define PB09_UART4_TX 9U
+#define PB10_I2C2_SCL 10U
+#define PB11_I2C2_SDA 11U
+#define PB12_SPI_SLAVE4 12U
+#define PB13_SPI2_SCK 13U
+#define PB14_SPI2_MISO 14U
+#define PB15_SPI2_MOSI 15U
+
+#define PC00_ADC5 0U
+#define PC01_ADC6 1U
+#define PC02 2U
+#define PC03 3U
+#define PC04_ADC2 4U
+#define PC05_ADC1 5U
+#define PC06_UART6_TX 6U
+#define PC07_UART6_RX 7U
+#define PC08_SDIO_D0 8U
+#define PC09_SDIO_D1 9U
+#define PC10_SDIO_D2 10U
+#define PC11_SDIO_D3 11U
+#define PC12_SDIO_CK 12U
+#define PC13_SPI_SLAVE6 13U
+#define PC14 14U
+#define PC15_SPI_SLAVE5 15U
+
+#define PD00_CAN1_RX 0U
+#define PD01_CAN1_TX 1U
+#define PD02_SDIO_CMD 2U
+#define PD03 3U
+#define PD04_SPI_SLAVE1 4U
+#define PD05_UART2_TX 5U
+#define PD06_UART2_RX 6U
+#define PD07_SPI1_MOSI 7U
+#define PD08_UART3_TX 8U
+#define PD09_UART3_RX 9U
+#define PD10 10U
+#define PD11 11U
+#define PD12_SERVO7 12U
+#define PD13_SERVO8 13U
+#define PD14_SERVO9 14U
+#define PD15_SERVO10 15U
+
+#define PE00_UART8_RX 0U
+#define PE01_UART8_TX 1U
+#define PE02_SPI_SLAVE2 2U
+#define PE03_LED1 3U
+#define PE04_LED2 4U
+#define PE05_SERVO11 5U
+#define PE06_SERVO12 6U
+#define PE07_UART7_RX 7U
+#define PE08_UART7_TX 8U
+#define PE09_UART7_RTS 9U
+#define PE10_UART7_CTS 10U
+#define PE11_SPI_SLAVE3 11U
+#define PE12_SPI4_CLK 12U
+#define PE13_SPI4_MISO 13U
+#define PE14_SPI4_MOSI 14U
+#define PE15 15U
+
+#define PF00 0U
+#define PF01 1U
+#define PF02 2U
+#define PF03 3U
+#define PF04 4U
+#define PF05 5U
+#define PF06 6U
+#define PF07 7U
+#define PF08 8U
+#define PF09 9U
+#define PF10 10U
+#define PF11 11U
+#define PF12 12U
+#define PF13 13U
+#define PF14 14U
+#define PF15 15U
+
+#define PG00 0U
+#define PG01 1U
+#define PG02 2U
+#define PG03 3U
+#define PG04 4U
+#define PG05 5U
+#define PG06 6U
+#define PG07 7U
+#define PG08 8U
+#define PG09 9U
+#define PG10 10U
+#define PG11 11U
+#define PG12 12U
+#define PG13 13U
+#define PG14 14U
+#define PG15 15U
+
+#define PH00_OSC_IN 0U
+#define PH01_OSC_OUT 1U
+#define PH02 2U
+#define PH03 3U
+#define PH04 4U
+#define PH05 5U
+#define PH06 6U
+#define PH07 7U
+#define PH08 8U
+#define PH09 9U
+#define PH10 10U
+#define PH11 11U
+#define PH12 12U
+#define PH13 13U
+#define PH14 14U
+#define PH15 15U
+
+#define PI00 0U
+#define PI01 1U
+#define PI02 2U
+#define PI03 3U
+#define PI04 4U
+#define PI05 5U
+#define PI06 6U
+#define PI07 7U
+#define PI08 8U
+#define PI09 9U
+#define PI10 10U
+#define PI11 11U
+#define PI12 12U
+#define PI13 13U
+#define PI14 14U
+#define PI15 15U
+
+#define PJ00 0U
+#define PJ01 1U
+#define PJ02 2U
+#define PJ03 3U
+#define PJ04 4U
+#define PJ05 5U
+#define PJ06 6U
+#define PJ07 7U
+#define PJ08 8U
+#define PJ09 9U
+#define PJ10 10U
+#define PJ11 11U
+#define PJ12 12U
+#define PJ13 13U
+#define PJ14 14U
+#define PJ15 15U
+
+#define PK00 0U
+#define PK01 1U
+#define PK02 2U
+#define PK03 3U
+#define PK04 4U
+#define PK05 5U
+#define PK06 6U
+#define PK07 7U
+#define PK08 8U
+#define PK09 9U
+#define PK10 10U
+#define PK11 11U
+#define PK12 12U
+#define PK13 13U
+#define PK14 14U
+#define PK15 15U
+
+/*
+ * IO lines assignments.
+ */
+#define LINE_SERVO3 PAL_LINE(GPIOA, 0U)
+#define LINE_SERVO4 PAL_LINE(GPIOA, 1U)
+#define LINE_SERVO5 PAL_LINE(GPIOA, 2U)
+#define LINE_SERVO6 PAL_LINE(GPIOA, 3U)
+#define LINE_ADC3 PAL_LINE(GPIOA, 4U)
+#define LINE_SPI1_SCK PAL_LINE(GPIOA, 5U)
+#define LINE_SPI1_MISO PAL_LINE(GPIOA, 6U)
+#define LINE_ADC4 PAL_LINE(GPIOA, 7U)
+#define LINE_LED_WS2812 PAL_LINE(GPIOA, 8U)
+#define LINE_UART1_TX PAL_LINE(GPIOA, 9U)
+#define LINE_UART1_RX PAL_LINE(GPIOA, 10U)
+#define LINE_USB_DM PAL_LINE(GPIOA, 11U)
+#define LINE_USB_DP PAL_LINE(GPIOA, 12U)
+#define LINE_SWDIO PAL_LINE(GPIOA, 13U)
+#define LINE_SWCLK PAL_LINE(GPIOA, 14U)
+#define LINE_ALARM PAL_LINE(GPIOA, 15U)
+
+#define LINE_SERVO1 PAL_LINE(GPIOB, 0U)
+#define LINE_SERVO2 PAL_LINE(GPIOB, 1U)
+#define LINE_SPI3_SCK PAL_LINE(GPIOB, 3U)
+#define LINE_SPI3_MISO PAL_LINE(GPIOB, 4U)
+#define LINE_SPI3_MOSI PAL_LINE(GPIOB, 5U)
+#define LINE_I2C1_SCL PAL_LINE(GPIOB, 6U)
+#define LINE_I2C1_SDA PAL_LINE(GPIOB, 7U)
+#define LINE_UART4_RX PAL_LINE(GPIOB, 8U)
+#define LINE_UART4_TX PAL_LINE(GPIOB, 9U)
+#define LINE_I2C2_SCL PAL_LINE(GPIOB, 10U)
+#define LINE_I2C2_SDA PAL_LINE(GPIOB, 11U)
+#define LINE_SPI_SLAVE4 PAL_LINE(GPIOB, 12U)
+#define LINE_SPI2_SCK PAL_LINE(GPIOB, 13U)
+#define LINE_SPI2_MISO PAL_LINE(GPIOB, 14U)
+#define LINE_SPI2_MOSI PAL_LINE(GPIOB, 15U)
+
+#define LINE_ADC5 PAL_LINE(GPIOC, 0U)
+#define LINE_ADC6 PAL_LINE(GPIOC, 1U)
+#define LINE_ADC2 PAL_LINE(GPIOC, 4U)
+#define LINE_ADC1 PAL_LINE(GPIOC, 5U)
+#define LINE_UART6_TX PAL_LINE(GPIOC, 6U)
+#define LINE_UART6_RX PAL_LINE(GPIOC, 7U)
+#define LINE_SDIO_D0 PAL_LINE(GPIOC, 8U)
+#define LINE_SDIO_D1 PAL_LINE(GPIOC, 9U)
+#define LINE_SDIO_D2 PAL_LINE(GPIOC, 10U)
+#define LINE_SDIO_D3 PAL_LINE(GPIOC, 11U)
+#define LINE_SDIO_CK PAL_LINE(GPIOC, 12U)
+#define LINE_SPI_SLAVE6 PAL_LINE(GPIOC, 13U)
+#define LINE_SPI_SLAVE5 PAL_LINE(GPIOC, 15U)
+
+#define LINE_CAN1_RX PAL_LINE(GPIOD, 0U)
+#define LINE_CAN1_TX PAL_LINE(GPIOD, 1U)
+#define LINE_SDIO_CMD PAL_LINE(GPIOD, 2U)
+#define LINE_SPI_SLAVE1 PAL_LINE(GPIOD, 4U)
+#define LINE_UART2_TX PAL_LINE(GPIOD, 5U)
+#define LINE_UART2_RX PAL_LINE(GPIOD, 6U)
+#define LINE_SPI1_MOSI PAL_LINE(GPIOD, 7U)
+#define LINE_UART3_TX PAL_LINE(GPIOD, 8U)
+#define LINE_UART3_RX PAL_LINE(GPIOD, 9U)
+#define LINE_SERVO7 PAL_LINE(GPIOD, 12U)
+#define LINE_SERVO8 PAL_LINE(GPIOD, 13U)
+#define LINE_SERVO9 PAL_LINE(GPIOD, 14U)
+#define LINE_SERVO10 PAL_LINE(GPIOD, 15U)
+
+#define LINE_UART8_RX PAL_LINE(GPIOE, 0U)
+#define LINE_UART8_TX PAL_LINE(GPIOE, 1U)
+#define LINE_SPI_SLAVE2 PAL_LINE(GPIOE, 2U)
+#define LINE_LED1 PAL_LINE(GPIOE, 3U)
+#define LINE_LED2 PAL_LINE(GPIOE, 4U)
+#define LINE_SERVO11 PAL_LINE(GPIOE, 5U)
+#define LINE_SERVO12 PAL_LINE(GPIOE, 6U)
+#define LINE_UART7_RX PAL_LINE(GPIOE, 7U)
+#define LINE_UART7_TX PAL_LINE(GPIOE, 8U)
+#define LINE_UART7_RTS PAL_LINE(GPIOE, 9U)
+#define LINE_UART7_CTS PAL_LINE(GPIOE, 10U)
+#define LINE_SPI_SLAVE3 PAL_LINE(GPIOE, 11U)
+#define LINE_SPI4_CLK PAL_LINE(GPIOE, 12U)
+#define LINE_SPI4_MISO PAL_LINE(GPIOE, 13U)
+#define LINE_SPI4_MOSI PAL_LINE(GPIOE, 14U)
+
+#define LINE_OSC_IN PAL_LINE(GPIOH, 0U)
+#define LINE_OSC_OUT PAL_LINE(GPIOH, 1U)
+
+
+/*
+ * I/O ports initial setup, this configuration is established soon after reset
+ * in the initialization code.
+ * Please refer to the STM32 Reference Manual for details.
+ */
+#define PIN_MODE_INPUT(n) (0U << ((n) * 2U))
+#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U))
+#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U))
+#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U))
+#define PIN_ODR_LEVEL_LOW(n) (0U << (n))
+#define PIN_ODR_LEVEL_HIGH(n) (1U << (n))
+#define PIN_OTYPE_PUSHPULL(n) (0U << (n))
+#define PIN_OTYPE_OPENDRAIN(n) (1U << (n))
+#define PIN_OSPEED_SPEED_VERYLOW(n) (0U << ((n) * 2U))
+#define PIN_OSPEED_SPEED_LOW(n) (1U << ((n) * 2U))
+#define PIN_OSPEED_SPEED_MEDIUM(n) (2U << ((n) * 2U))
+#define PIN_OSPEED_SPEED_HIGH(n) (3U << ((n) * 2U))
+#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U))
+#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U))
+#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U))
+#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U))
+
+#define VAL_GPIOA_MODER (PIN_MODE_ALTERNATE(PA00_SERVO3) | \
+ PIN_MODE_ALTERNATE(PA01_SERVO4) | \
+ PIN_MODE_ALTERNATE(PA02_SERVO5) | \
+ PIN_MODE_ALTERNATE(PA03_SERVO6) | \
+ PIN_MODE_ANALOG(PA04_ADC3) | \
+ PIN_MODE_ALTERNATE(PA05_SPI1_SCK) | \
+ PIN_MODE_ALTERNATE(PA06_SPI1_MISO) | \
+ PIN_MODE_ANALOG(PA07_ADC4) | \
+ PIN_MODE_ALTERNATE(PA08_LED_WS2812) | \
+ PIN_MODE_ALTERNATE(PA09_UART1_TX) | \
+ PIN_MODE_ALTERNATE(PA10_UART1_RX) | \
+ PIN_MODE_ALTERNATE(PA11_USB_DM) | \
+ PIN_MODE_ALTERNATE(PA12_USB_DP) | \
+ PIN_MODE_ALTERNATE(PA13_SWDIO) | \
+ PIN_MODE_ALTERNATE(PA14_SWCLK) | \
+ PIN_MODE_ALTERNATE(PA15_ALARM))
+
+#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(PA00_SERVO3) | \
+ PIN_OTYPE_PUSHPULL(PA01_SERVO4) | \
+ PIN_OTYPE_PUSHPULL(PA02_SERVO5) | \
+ PIN_OTYPE_PUSHPULL(PA03_SERVO6) | \
+ PIN_OTYPE_PUSHPULL(PA04_ADC3) | \
+ PIN_OTYPE_PUSHPULL(PA05_SPI1_SCK) | \
+ PIN_OTYPE_PUSHPULL(PA06_SPI1_MISO) | \
+ PIN_OTYPE_PUSHPULL(PA07_ADC4) | \
+ PIN_OTYPE_PUSHPULL(PA08_LED_WS2812) | \
+ PIN_OTYPE_PUSHPULL(PA09_UART1_TX) | \
+ PIN_OTYPE_PUSHPULL(PA10_UART1_RX) | \
+ PIN_OTYPE_PUSHPULL(PA11_USB_DM) | \
+ PIN_OTYPE_PUSHPULL(PA12_USB_DP) | \
+ PIN_OTYPE_PUSHPULL(PA13_SWDIO) | \
+ PIN_OTYPE_PUSHPULL(PA14_SWCLK) | \
+ PIN_OTYPE_PUSHPULL(PA15_ALARM))
+
+#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_SPEED_HIGH(PA00_SERVO3) | \
+ PIN_OSPEED_SPEED_HIGH(PA01_SERVO4) | \
+ PIN_OSPEED_SPEED_HIGH(PA02_SERVO5) | \
+ PIN_OSPEED_SPEED_HIGH(PA03_SERVO6) | \
+ PIN_OSPEED_SPEED_VERYLOW(PA04_ADC3) | \
+ PIN_OSPEED_SPEED_HIGH(PA05_SPI1_SCK) | \
+ PIN_OSPEED_SPEED_HIGH(PA06_SPI1_MISO) | \
+ PIN_OSPEED_SPEED_VERYLOW(PA07_ADC4) | \
+ PIN_OSPEED_SPEED_HIGH(PA08_LED_WS2812) | \
+ PIN_OSPEED_SPEED_HIGH(PA09_UART1_TX) | \
+ PIN_OSPEED_SPEED_HIGH(PA10_UART1_RX) | \
+ PIN_OSPEED_SPEED_HIGH(PA11_USB_DM) | \
+ PIN_OSPEED_SPEED_HIGH(PA12_USB_DP) | \
+ PIN_OSPEED_SPEED_HIGH(PA13_SWDIO) | \
+ PIN_OSPEED_SPEED_HIGH(PA14_SWCLK) | \
+ PIN_OSPEED_SPEED_HIGH(PA15_ALARM))
+
+#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(PA00_SERVO3) | \
+ PIN_PUPDR_FLOATING(PA01_SERVO4) | \
+ PIN_PUPDR_FLOATING(PA02_SERVO5) | \
+ PIN_PUPDR_FLOATING(PA03_SERVO6) | \
+ PIN_PUPDR_FLOATING(PA04_ADC3) | \
+ PIN_PUPDR_FLOATING(PA05_SPI1_SCK) | \
+ PIN_PUPDR_FLOATING(PA06_SPI1_MISO) | \
+ PIN_PUPDR_FLOATING(PA07_ADC4) | \
+ PIN_PUPDR_FLOATING(PA08_LED_WS2812) | \
+ PIN_PUPDR_FLOATING(PA09_UART1_TX) | \
+ PIN_PUPDR_FLOATING(PA10_UART1_RX) | \
+ PIN_PUPDR_FLOATING(PA11_USB_DM) | \
+ PIN_PUPDR_FLOATING(PA12_USB_DP) | \
+ PIN_PUPDR_FLOATING(PA13_SWDIO) | \
+ PIN_PUPDR_FLOATING(PA14_SWCLK) | \
+ PIN_PUPDR_FLOATING(PA15_ALARM))
+
+#define VAL_GPIOA_ODR (PIN_ODR_LEVEL_LOW(PA00_SERVO3) | \
+ PIN_ODR_LEVEL_LOW(PA01_SERVO4) | \
+ PIN_ODR_LEVEL_LOW(PA02_SERVO5) | \
+ PIN_ODR_LEVEL_LOW(PA03_SERVO6) | \
+ PIN_ODR_LEVEL_LOW(PA04_ADC3) | \
+ PIN_ODR_LEVEL_HIGH(PA05_SPI1_SCK) | \
+ PIN_ODR_LEVEL_HIGH(PA06_SPI1_MISO) | \
+ PIN_ODR_LEVEL_LOW(PA07_ADC4) | \
+ PIN_ODR_LEVEL_LOW(PA08_LED_WS2812) | \
+ PIN_ODR_LEVEL_HIGH(PA09_UART1_TX) | \
+ PIN_ODR_LEVEL_HIGH(PA10_UART1_RX) | \
+ PIN_ODR_LEVEL_HIGH(PA11_USB_DM) | \
+ PIN_ODR_LEVEL_HIGH(PA12_USB_DP) | \
+ PIN_ODR_LEVEL_HIGH(PA13_SWDIO) | \
+ PIN_ODR_LEVEL_HIGH(PA14_SWCLK) | \
+ PIN_ODR_LEVEL_LOW(PA15_ALARM))
+
+#define VAL_GPIOA_AFRL (PIN_AFIO_AF(PA00_SERVO3, 2) | \
+ PIN_AFIO_AF(PA01_SERVO4, 2) | \
+ PIN_AFIO_AF(PA02_SERVO5, 2) | \
+ PIN_AFIO_AF(PA03_SERVO6, 2) | \
+ PIN_AFIO_AF(PA04_ADC3, 0) | \
+ PIN_AFIO_AF(PA05_SPI1_SCK, 5) | \
+ PIN_AFIO_AF(PA06_SPI1_MISO, 5) | \
+ PIN_AFIO_AF(PA07_ADC4, 0))
+
+#define VAL_GPIOA_AFRH (PIN_AFIO_AF(PA08_LED_WS2812, 1) | \
+ PIN_AFIO_AF(PA09_UART1_TX, 7) | \
+ PIN_AFIO_AF(PA10_UART1_RX, 7) | \
+ PIN_AFIO_AF(PA11_USB_DM, 10) | \
+ PIN_AFIO_AF(PA12_USB_DP, 10) | \
+ PIN_AFIO_AF(PA13_SWDIO, 0) | \
+ PIN_AFIO_AF(PA14_SWCLK, 0) | \
+ PIN_AFIO_AF(PA15_ALARM, 1))
+
+#define VAL_GPIOB_MODER (PIN_MODE_ALTERNATE(PB00_SERVO1) | \
+ PIN_MODE_ALTERNATE(PB01_SERVO2) | \
+ PIN_MODE_INPUT(PB02) | \
+ PIN_MODE_ALTERNATE(PB03_SPI3_SCK) | \
+ PIN_MODE_ALTERNATE(PB04_SPI3_MISO) | \
+ PIN_MODE_ALTERNATE(PB05_SPI3_MOSI) | \
+ PIN_MODE_ALTERNATE(PB06_I2C1_SCL) | \
+ PIN_MODE_ALTERNATE(PB07_I2C1_SDA) | \
+ PIN_MODE_ALTERNATE(PB08_UART4_RX) | \
+ PIN_MODE_ALTERNATE(PB09_UART4_TX) | \
+ PIN_MODE_ALTERNATE(PB10_I2C2_SCL) | \
+ PIN_MODE_ALTERNATE(PB11_I2C2_SDA) | \
+ PIN_MODE_OUTPUT(PB12_SPI_SLAVE4) | \
+ PIN_MODE_ALTERNATE(PB13_SPI2_SCK) | \
+ PIN_MODE_ALTERNATE(PB14_SPI2_MISO) | \
+ PIN_MODE_ALTERNATE(PB15_SPI2_MOSI))
+
+#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(PB00_SERVO1) | \
+ PIN_OTYPE_PUSHPULL(PB01_SERVO2) | \
+ PIN_OTYPE_PUSHPULL(PB02) | \
+ PIN_OTYPE_PUSHPULL(PB03_SPI3_SCK) | \
+ PIN_OTYPE_PUSHPULL(PB04_SPI3_MISO) | \
+ PIN_OTYPE_PUSHPULL(PB05_SPI3_MOSI) | \
+ PIN_OTYPE_OPENDRAIN(PB06_I2C1_SCL) | \
+ PIN_OTYPE_OPENDRAIN(PB07_I2C1_SDA) | \
+ PIN_OTYPE_PUSHPULL(PB08_UART4_RX) | \
+ PIN_OTYPE_PUSHPULL(PB09_UART4_TX) | \
+ PIN_OTYPE_OPENDRAIN(PB10_I2C2_SCL) | \
+ PIN_OTYPE_OPENDRAIN(PB11_I2C2_SDA) | \
+ PIN_OTYPE_PUSHPULL(PB12_SPI_SLAVE4) | \
+ PIN_OTYPE_PUSHPULL(PB13_SPI2_SCK) | \
+ PIN_OTYPE_PUSHPULL(PB14_SPI2_MISO) | \
+ PIN_OTYPE_PUSHPULL(PB15_SPI2_MOSI))
+
+#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_SPEED_HIGH(PB00_SERVO1) | \
+ PIN_OSPEED_SPEED_HIGH(PB01_SERVO2) | \
+ PIN_OSPEED_SPEED_VERYLOW(PB02) | \
+ PIN_OSPEED_SPEED_HIGH(PB03_SPI3_SCK) | \
+ PIN_OSPEED_SPEED_HIGH(PB04_SPI3_MISO) | \
+ PIN_OSPEED_SPEED_HIGH(PB05_SPI3_MOSI) | \
+ PIN_OSPEED_SPEED_HIGH(PB06_I2C1_SCL) | \
+ PIN_OSPEED_SPEED_HIGH(PB07_I2C1_SDA) | \
+ PIN_OSPEED_SPEED_HIGH(PB08_UART4_RX) | \
+ PIN_OSPEED_SPEED_HIGH(PB09_UART4_TX) | \
+ PIN_OSPEED_SPEED_HIGH(PB10_I2C2_SCL) | \
+ PIN_OSPEED_SPEED_HIGH(PB11_I2C2_SDA) | \
+ PIN_OSPEED_SPEED_HIGH(PB12_SPI_SLAVE4) | \
+ PIN_OSPEED_SPEED_HIGH(PB13_SPI2_SCK) | \
+ PIN_OSPEED_SPEED_HIGH(PB14_SPI2_MISO) | \
+ PIN_OSPEED_SPEED_HIGH(PB15_SPI2_MOSI))
+
+#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(PB00_SERVO1) | \
+ PIN_PUPDR_FLOATING(PB01_SERVO2) | \
+ PIN_PUPDR_PULLDOWN(PB02) | \
+ PIN_PUPDR_FLOATING(PB03_SPI3_SCK) | \
+ PIN_PUPDR_FLOATING(PB04_SPI3_MISO) | \
+ PIN_PUPDR_FLOATING(PB05_SPI3_MOSI) | \
+ PIN_PUPDR_PULLUP(PB06_I2C1_SCL) | \
+ PIN_PUPDR_PULLUP(PB07_I2C1_SDA) | \
+ PIN_PUPDR_FLOATING(PB08_UART4_RX) | \
+ PIN_PUPDR_FLOATING(PB09_UART4_TX) | \
+ PIN_PUPDR_PULLUP(PB10_I2C2_SCL) | \
+ PIN_PUPDR_PULLUP(PB11_I2C2_SDA) | \
+ PIN_PUPDR_FLOATING(PB12_SPI_SLAVE4) | \
+ PIN_PUPDR_FLOATING(PB13_SPI2_SCK) | \
+ PIN_PUPDR_FLOATING(PB14_SPI2_MISO) | \
+ PIN_PUPDR_FLOATING(PB15_SPI2_MOSI))
+
+#define VAL_GPIOB_ODR (PIN_ODR_LEVEL_LOW(PB00_SERVO1) | \
+ PIN_ODR_LEVEL_LOW(PB01_SERVO2) | \
+ PIN_ODR_LEVEL_LOW(PB02) | \
+ PIN_ODR_LEVEL_HIGH(PB03_SPI3_SCK) | \
+ PIN_ODR_LEVEL_HIGH(PB04_SPI3_MISO) | \
+ PIN_ODR_LEVEL_HIGH(PB05_SPI3_MOSI) | \
+ PIN_ODR_LEVEL_HIGH(PB06_I2C1_SCL) | \
+ PIN_ODR_LEVEL_HIGH(PB07_I2C1_SDA) | \
+ PIN_ODR_LEVEL_HIGH(PB08_UART4_RX) | \
+ PIN_ODR_LEVEL_HIGH(PB09_UART4_TX) | \
+ PIN_ODR_LEVEL_HIGH(PB10_I2C2_SCL) | \
+ PIN_ODR_LEVEL_HIGH(PB11_I2C2_SDA) | \
+ PIN_ODR_LEVEL_HIGH(PB12_SPI_SLAVE4) | \
+ PIN_ODR_LEVEL_HIGH(PB13_SPI2_SCK) | \
+ PIN_ODR_LEVEL_HIGH(PB14_SPI2_MISO) | \
+ PIN_ODR_LEVEL_HIGH(PB15_SPI2_MOSI))
+
+#define VAL_GPIOB_AFRL (PIN_AFIO_AF(PB00_SERVO1, 2) | \
+ PIN_AFIO_AF(PB01_SERVO2, 2) | \
+ PIN_AFIO_AF(PB02, 0) | \
+ PIN_AFIO_AF(PB03_SPI3_SCK, 6) | \
+ PIN_AFIO_AF(PB04_SPI3_MISO, 6) | \
+ PIN_AFIO_AF(PB05_SPI3_MOSI, 7) | \
+ PIN_AFIO_AF(PB06_I2C1_SCL, 4) | \
+ PIN_AFIO_AF(PB07_I2C1_SDA, 4))
+
+#define VAL_GPIOB_AFRH (PIN_AFIO_AF(PB08_UART4_RX, 8) | \
+ PIN_AFIO_AF(PB09_UART4_TX, 8) | \
+ PIN_AFIO_AF(PB10_I2C2_SCL, 4) | \
+ PIN_AFIO_AF(PB11_I2C2_SDA, 4) | \
+ PIN_AFIO_AF(PB12_SPI_SLAVE4, 0) | \
+ PIN_AFIO_AF(PB13_SPI2_SCK, 5) | \
+ PIN_AFIO_AF(PB14_SPI2_MISO, 5) | \
+ PIN_AFIO_AF(PB15_SPI2_MOSI, 5))
+
+#define VAL_GPIOC_MODER (PIN_MODE_ANALOG(PC00_ADC5) | \
+ PIN_MODE_ANALOG(PC01_ADC6) | \
+ PIN_MODE_INPUT(PC02) | \
+ PIN_MODE_INPUT(PC03) | \
+ PIN_MODE_ANALOG(PC04_ADC2) | \
+ PIN_MODE_ANALOG(PC05_ADC1) | \
+ PIN_MODE_ALTERNATE(PC06_UART6_TX) | \
+ PIN_MODE_ALTERNATE(PC07_UART6_RX) | \
+ PIN_MODE_ALTERNATE(PC08_SDIO_D0) | \
+ PIN_MODE_ALTERNATE(PC09_SDIO_D1) | \
+ PIN_MODE_ALTERNATE(PC10_SDIO_D2) | \
+ PIN_MODE_ALTERNATE(PC11_SDIO_D3) | \
+ PIN_MODE_ALTERNATE(PC12_SDIO_CK) | \
+ PIN_MODE_OUTPUT(PC13_SPI_SLAVE6) | \
+ PIN_MODE_INPUT(PC14) | \
+ PIN_MODE_OUTPUT(PC15_SPI_SLAVE5))
+
+#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(PC00_ADC5) | \
+ PIN_OTYPE_PUSHPULL(PC01_ADC6) | \
+ PIN_OTYPE_PUSHPULL(PC02) | \
+ PIN_OTYPE_PUSHPULL(PC03) | \
+ PIN_OTYPE_PUSHPULL(PC04_ADC2) | \
+ PIN_OTYPE_PUSHPULL(PC05_ADC1) | \
+ PIN_OTYPE_PUSHPULL(PC06_UART6_TX) | \
+ PIN_OTYPE_PUSHPULL(PC07_UART6_RX) | \
+ PIN_OTYPE_PUSHPULL(PC08_SDIO_D0) | \
+ PIN_OTYPE_PUSHPULL(PC09_SDIO_D1) | \
+ PIN_OTYPE_PUSHPULL(PC10_SDIO_D2) | \
+ PIN_OTYPE_PUSHPULL(PC11_SDIO_D3) | \
+ PIN_OTYPE_PUSHPULL(PC12_SDIO_CK) | \
+ PIN_OTYPE_PUSHPULL(PC13_SPI_SLAVE6) | \
+ PIN_OTYPE_PUSHPULL(PC14) | \
+ PIN_OTYPE_PUSHPULL(PC15_SPI_SLAVE5))
+
+#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(PC00_ADC5) | \
+ PIN_OSPEED_SPEED_VERYLOW(PC01_ADC6) | \
+ PIN_OSPEED_SPEED_VERYLOW(PC02) | \
+ PIN_OSPEED_SPEED_VERYLOW(PC03) | \
+ PIN_OSPEED_SPEED_VERYLOW(PC04_ADC2) | \
+ PIN_OSPEED_SPEED_VERYLOW(PC05_ADC1) | \
+ PIN_OSPEED_SPEED_HIGH(PC06_UART6_TX) | \
+ PIN_OSPEED_SPEED_HIGH(PC07_UART6_RX) | \
+ PIN_OSPEED_SPEED_HIGH(PC08_SDIO_D0) | \
+ PIN_OSPEED_SPEED_HIGH(PC09_SDIO_D1) | \
+ PIN_OSPEED_SPEED_HIGH(PC10_SDIO_D2) | \
+ PIN_OSPEED_SPEED_HIGH(PC11_SDIO_D3) | \
+ PIN_OSPEED_SPEED_HIGH(PC12_SDIO_CK) | \
+ PIN_OSPEED_SPEED_HIGH(PC13_SPI_SLAVE6) | \
+ PIN_OSPEED_SPEED_VERYLOW(PC14) | \
+ PIN_OSPEED_SPEED_HIGH(PC15_SPI_SLAVE5))
+
+#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(PC00_ADC5) | \
+ PIN_PUPDR_FLOATING(PC01_ADC6) | \
+ PIN_PUPDR_PULLDOWN(PC02) | \
+ PIN_PUPDR_PULLDOWN(PC03) | \
+ PIN_PUPDR_FLOATING(PC04_ADC2) | \
+ PIN_PUPDR_FLOATING(PC05_ADC1) | \
+ PIN_PUPDR_FLOATING(PC06_UART6_TX) | \
+ PIN_PUPDR_FLOATING(PC07_UART6_RX) | \
+ PIN_PUPDR_PULLUP(PC08_SDIO_D0) | \
+ PIN_PUPDR_PULLUP(PC09_SDIO_D1) | \
+ PIN_PUPDR_PULLUP(PC10_SDIO_D2) | \
+ PIN_PUPDR_PULLUP(PC11_SDIO_D3) | \
+ PIN_PUPDR_FLOATING(PC12_SDIO_CK) | \
+ PIN_PUPDR_FLOATING(PC13_SPI_SLAVE6) | \
+ PIN_PUPDR_PULLDOWN(PC14) | \
+ PIN_PUPDR_FLOATING(PC15_SPI_SLAVE5))
+
+#define VAL_GPIOC_ODR (PIN_ODR_LEVEL_LOW(PC00_ADC5) | \
+ PIN_ODR_LEVEL_LOW(PC01_ADC6) | \
+ PIN_ODR_LEVEL_LOW(PC02) | \
+ PIN_ODR_LEVEL_LOW(PC03) | \
+ PIN_ODR_LEVEL_LOW(PC04_ADC2) | \
+ PIN_ODR_LEVEL_LOW(PC05_ADC1) | \
+ PIN_ODR_LEVEL_HIGH(PC06_UART6_TX) | \
+ PIN_ODR_LEVEL_HIGH(PC07_UART6_RX) | \
+ PIN_ODR_LEVEL_HIGH(PC08_SDIO_D0) | \
+ PIN_ODR_LEVEL_HIGH(PC09_SDIO_D1) | \
+ PIN_ODR_LEVEL_HIGH(PC10_SDIO_D2) | \
+ PIN_ODR_LEVEL_HIGH(PC11_SDIO_D3) | \
+ PIN_ODR_LEVEL_HIGH(PC12_SDIO_CK) | \
+ PIN_ODR_LEVEL_HIGH(PC13_SPI_SLAVE6) | \
+ PIN_ODR_LEVEL_LOW(PC14) | \
+ PIN_ODR_LEVEL_HIGH(PC15_SPI_SLAVE5))
+
+#define VAL_GPIOC_AFRL (PIN_AFIO_AF(PC00_ADC5, 0) | \
+ PIN_AFIO_AF(PC01_ADC6, 0) | \
+ PIN_AFIO_AF(PC02, 0) | \
+ PIN_AFIO_AF(PC03, 0) | \
+ PIN_AFIO_AF(PC04_ADC2, 0) | \
+ PIN_AFIO_AF(PC05_ADC1, 0) | \
+ PIN_AFIO_AF(PC06_UART6_TX, 7) | \
+ PIN_AFIO_AF(PC07_UART6_RX, 7))
+
+#define VAL_GPIOC_AFRH (PIN_AFIO_AF(PC08_SDIO_D0, 12) | \
+ PIN_AFIO_AF(PC09_SDIO_D1, 12) | \
+ PIN_AFIO_AF(PC10_SDIO_D2, 12) | \
+ PIN_AFIO_AF(PC11_SDIO_D3, 12) | \
+ PIN_AFIO_AF(PC12_SDIO_CK, 12) | \
+ PIN_AFIO_AF(PC13_SPI_SLAVE6, 0) | \
+ PIN_AFIO_AF(PC14, 0) | \
+ PIN_AFIO_AF(PC15_SPI_SLAVE5, 0))
+
+#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(PD00_CAN1_RX) | \
+ PIN_MODE_ALTERNATE(PD01_CAN1_TX) | \
+ PIN_MODE_ALTERNATE(PD02_SDIO_CMD) | \
+ PIN_MODE_INPUT(PD03) | \
+ PIN_MODE_OUTPUT(PD04_SPI_SLAVE1) | \
+ PIN_MODE_ALTERNATE(PD05_UART2_TX) | \
+ PIN_MODE_ALTERNATE(PD06_UART2_RX) | \
+ PIN_MODE_ALTERNATE(PD07_SPI1_MOSI) | \
+ PIN_MODE_ALTERNATE(PD08_UART3_TX) | \
+ PIN_MODE_ALTERNATE(PD09_UART3_RX) | \
+ PIN_MODE_INPUT(PD10) | \
+ PIN_MODE_INPUT(PD11) | \
+ PIN_MODE_ALTERNATE(PD12_SERVO7) | \
+ PIN_MODE_ALTERNATE(PD13_SERVO8) | \
+ PIN_MODE_ALTERNATE(PD14_SERVO9) | \
+ PIN_MODE_ALTERNATE(PD15_SERVO10))
+
+#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(PD00_CAN1_RX) | \
+ PIN_OTYPE_PUSHPULL(PD01_CAN1_TX) | \
+ PIN_OTYPE_PUSHPULL(PD02_SDIO_CMD) | \
+ PIN_OTYPE_PUSHPULL(PD03) | \
+ PIN_OTYPE_PUSHPULL(PD04_SPI_SLAVE1) | \
+ PIN_OTYPE_PUSHPULL(PD05_UART2_TX) | \
+ PIN_OTYPE_PUSHPULL(PD06_UART2_RX) | \
+ PIN_OTYPE_PUSHPULL(PD07_SPI1_MOSI) | \
+ PIN_OTYPE_PUSHPULL(PD08_UART3_TX) | \
+ PIN_OTYPE_PUSHPULL(PD09_UART3_RX) | \
+ PIN_OTYPE_PUSHPULL(PD10) | \
+ PIN_OTYPE_PUSHPULL(PD11) | \
+ PIN_OTYPE_PUSHPULL(PD12_SERVO7) | \
+ PIN_OTYPE_PUSHPULL(PD13_SERVO8) | \
+ PIN_OTYPE_PUSHPULL(PD14_SERVO9) | \
+ PIN_OTYPE_PUSHPULL(PD15_SERVO10))
+
+#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_SPEED_HIGH(PD00_CAN1_RX) | \
+ PIN_OSPEED_SPEED_HIGH(PD01_CAN1_TX) | \
+ PIN_OSPEED_SPEED_HIGH(PD02_SDIO_CMD) | \
+ PIN_OSPEED_SPEED_VERYLOW(PD03) | \
+ PIN_OSPEED_SPEED_HIGH(PD04_SPI_SLAVE1) | \
+ PIN_OSPEED_SPEED_HIGH(PD05_UART2_TX) | \
+ PIN_OSPEED_SPEED_HIGH(PD06_UART2_RX) | \
+ PIN_OSPEED_SPEED_HIGH(PD07_SPI1_MOSI) | \
+ PIN_OSPEED_SPEED_HIGH(PD08_UART3_TX) | \
+ PIN_OSPEED_SPEED_HIGH(PD09_UART3_RX) | \
+ PIN_OSPEED_SPEED_VERYLOW(PD10) | \
+ PIN_OSPEED_SPEED_VERYLOW(PD11) | \
+ PIN_OSPEED_SPEED_HIGH(PD12_SERVO7) | \
+ PIN_OSPEED_SPEED_HIGH(PD13_SERVO8) | \
+ PIN_OSPEED_SPEED_HIGH(PD14_SERVO9) | \
+ PIN_OSPEED_SPEED_HIGH(PD15_SERVO10))
+
+#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(PD00_CAN1_RX) | \
+ PIN_PUPDR_FLOATING(PD01_CAN1_TX) | \
+ PIN_PUPDR_PULLUP(PD02_SDIO_CMD) | \
+ PIN_PUPDR_PULLDOWN(PD03) | \
+ PIN_PUPDR_FLOATING(PD04_SPI_SLAVE1) | \
+ PIN_PUPDR_FLOATING(PD05_UART2_TX) | \
+ PIN_PUPDR_FLOATING(PD06_UART2_RX) | \
+ PIN_PUPDR_FLOATING(PD07_SPI1_MOSI) | \
+ PIN_PUPDR_FLOATING(PD08_UART3_TX) | \
+ PIN_PUPDR_FLOATING(PD09_UART3_RX) | \
+ PIN_PUPDR_PULLDOWN(PD10) | \
+ PIN_PUPDR_PULLDOWN(PD11) | \
+ PIN_PUPDR_FLOATING(PD12_SERVO7) | \
+ PIN_PUPDR_FLOATING(PD13_SERVO8) | \
+ PIN_PUPDR_FLOATING(PD14_SERVO9) | \
+ PIN_PUPDR_FLOATING(PD15_SERVO10))
+
+#define VAL_GPIOD_ODR (PIN_ODR_LEVEL_HIGH(PD00_CAN1_RX) | \
+ PIN_ODR_LEVEL_HIGH(PD01_CAN1_TX) | \
+ PIN_ODR_LEVEL_HIGH(PD02_SDIO_CMD) | \
+ PIN_ODR_LEVEL_LOW(PD03) | \
+ PIN_ODR_LEVEL_HIGH(PD04_SPI_SLAVE1) | \
+ PIN_ODR_LEVEL_HIGH(PD05_UART2_TX) | \
+ PIN_ODR_LEVEL_HIGH(PD06_UART2_RX) | \
+ PIN_ODR_LEVEL_HIGH(PD07_SPI1_MOSI) | \
+ PIN_ODR_LEVEL_HIGH(PD08_UART3_TX) | \
+ PIN_ODR_LEVEL_HIGH(PD09_UART3_RX) | \
+ PIN_ODR_LEVEL_LOW(PD10) | \
+ PIN_ODR_LEVEL_LOW(PD11) | \
+ PIN_ODR_LEVEL_LOW(PD12_SERVO7) | \
+ PIN_ODR_LEVEL_LOW(PD13_SERVO8) | \
+ PIN_ODR_LEVEL_LOW(PD14_SERVO9) | \
+ PIN_ODR_LEVEL_LOW(PD15_SERVO10))
+
+#define VAL_GPIOD_AFRL (PIN_AFIO_AF(PD00_CAN1_RX, 9) | \
+ PIN_AFIO_AF(PD01_CAN1_TX, 9) | \
+ PIN_AFIO_AF(PD02_SDIO_CMD, 12) | \
+ PIN_AFIO_AF(PD03, 0) | \
+ PIN_AFIO_AF(PD04_SPI_SLAVE1, 0) | \
+ PIN_AFIO_AF(PD05_UART2_TX, 7) | \
+ PIN_AFIO_AF(PD06_UART2_RX, 7) | \
+ PIN_AFIO_AF(PD07_SPI1_MOSI, 5))
+
+#define VAL_GPIOD_AFRH (PIN_AFIO_AF(PD08_UART3_TX, 7) | \
+ PIN_AFIO_AF(PD09_UART3_RX, 7) | \
+ PIN_AFIO_AF(PD10, 0) | \
+ PIN_AFIO_AF(PD11, 0) | \
+ PIN_AFIO_AF(PD12_SERVO7, 2) | \
+ PIN_AFIO_AF(PD13_SERVO8, 2) | \
+ PIN_AFIO_AF(PD14_SERVO9, 2) | \
+ PIN_AFIO_AF(PD15_SERVO10, 2))
+
+#define VAL_GPIOE_MODER (PIN_MODE_ALTERNATE(PE00_UART8_RX) | \
+ PIN_MODE_ALTERNATE(PE01_UART8_TX) | \
+ PIN_MODE_OUTPUT(PE02_SPI_SLAVE2) | \
+ PIN_MODE_OUTPUT(PE03_LED1) | \
+ PIN_MODE_OUTPUT(PE04_LED2) | \
+ PIN_MODE_ALTERNATE(PE05_SERVO11) | \
+ PIN_MODE_ALTERNATE(PE06_SERVO12) | \
+ PIN_MODE_ALTERNATE(PE07_UART7_RX) | \
+ PIN_MODE_ALTERNATE(PE08_UART7_TX) | \
+ PIN_MODE_INPUT(PE09_UART7_RTS) | \
+ PIN_MODE_INPUT(PE10_UART7_CTS) | \
+ PIN_MODE_OUTPUT(PE11_SPI_SLAVE3) | \
+ PIN_MODE_ALTERNATE(PE12_SPI4_CLK) | \
+ PIN_MODE_ALTERNATE(PE13_SPI4_MISO) | \
+ PIN_MODE_ALTERNATE(PE14_SPI4_MOSI) | \
+ PIN_MODE_INPUT(PE15))
+
+#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(PE00_UART8_RX) | \
+ PIN_OTYPE_PUSHPULL(PE01_UART8_TX) | \
+ PIN_OTYPE_PUSHPULL(PE02_SPI_SLAVE2) | \
+ PIN_OTYPE_PUSHPULL(PE03_LED1) | \
+ PIN_OTYPE_PUSHPULL(PE04_LED2) | \
+ PIN_OTYPE_PUSHPULL(PE05_SERVO11) | \
+ PIN_OTYPE_PUSHPULL(PE06_SERVO12) | \
+ PIN_OTYPE_PUSHPULL(PE07_UART7_RX) | \
+ PIN_OTYPE_PUSHPULL(PE08_UART7_TX) | \
+ PIN_OTYPE_OPENDRAIN(PE09_UART7_RTS) | \
+ PIN_OTYPE_OPENDRAIN(PE10_UART7_CTS) | \
+ PIN_OTYPE_PUSHPULL(PE11_SPI_SLAVE3) | \
+ PIN_OTYPE_PUSHPULL(PE12_SPI4_CLK) | \
+ PIN_OTYPE_PUSHPULL(PE13_SPI4_MISO) | \
+ PIN_OTYPE_PUSHPULL(PE14_SPI4_MOSI) | \
+ PIN_OTYPE_PUSHPULL(PE15))
+
+#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_SPEED_HIGH(PE00_UART8_RX) | \
+ PIN_OSPEED_SPEED_HIGH(PE01_UART8_TX) | \
+ PIN_OSPEED_SPEED_HIGH(PE02_SPI_SLAVE2) | \
+ PIN_OSPEED_SPEED_VERYLOW(PE03_LED1) | \
+ PIN_OSPEED_SPEED_VERYLOW(PE04_LED2) | \
+ PIN_OSPEED_SPEED_HIGH(PE05_SERVO11) | \
+ PIN_OSPEED_SPEED_HIGH(PE06_SERVO12) | \
+ PIN_OSPEED_SPEED_HIGH(PE07_UART7_RX) | \
+ PIN_OSPEED_SPEED_HIGH(PE08_UART7_TX) | \
+ PIN_OSPEED_SPEED_VERYLOW(PE09_UART7_RTS) | \
+ PIN_OSPEED_SPEED_VERYLOW(PE10_UART7_CTS) | \
+ PIN_OSPEED_SPEED_HIGH(PE11_SPI_SLAVE3) | \
+ PIN_OSPEED_SPEED_HIGH(PE12_SPI4_CLK) | \
+ PIN_OSPEED_SPEED_HIGH(PE13_SPI4_MISO) | \
+ PIN_OSPEED_SPEED_HIGH(PE14_SPI4_MOSI) | \
+ PIN_OSPEED_SPEED_VERYLOW(PE15))
+
+#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(PE00_UART8_RX) | \
+ PIN_PUPDR_FLOATING(PE01_UART8_TX) | \
+ PIN_PUPDR_FLOATING(PE02_SPI_SLAVE2) | \
+ PIN_PUPDR_FLOATING(PE03_LED1) | \
+ PIN_PUPDR_FLOATING(PE04_LED2) | \
+ PIN_PUPDR_FLOATING(PE05_SERVO11) | \
+ PIN_PUPDR_FLOATING(PE06_SERVO12) | \
+ PIN_PUPDR_FLOATING(PE07_UART7_RX) | \
+ PIN_PUPDR_FLOATING(PE08_UART7_TX) | \
+ PIN_PUPDR_PULLDOWN(PE09_UART7_RTS) | \
+ PIN_PUPDR_PULLDOWN(PE10_UART7_CTS) | \
+ PIN_PUPDR_FLOATING(PE11_SPI_SLAVE3) | \
+ PIN_PUPDR_FLOATING(PE12_SPI4_CLK) | \
+ PIN_PUPDR_FLOATING(PE13_SPI4_MISO) | \
+ PIN_PUPDR_FLOATING(PE14_SPI4_MOSI) | \
+ PIN_PUPDR_PULLDOWN(PE15))
+
+#define VAL_GPIOE_ODR (PIN_ODR_LEVEL_HIGH(PE00_UART8_RX) | \
+ PIN_ODR_LEVEL_HIGH(PE01_UART8_TX) | \
+ PIN_ODR_LEVEL_HIGH(PE02_SPI_SLAVE2) | \
+ PIN_ODR_LEVEL_LOW(PE03_LED1) | \
+ PIN_ODR_LEVEL_LOW(PE04_LED2) | \
+ PIN_ODR_LEVEL_LOW(PE05_SERVO11) | \
+ PIN_ODR_LEVEL_LOW(PE06_SERVO12) | \
+ PIN_ODR_LEVEL_HIGH(PE07_UART7_RX) | \
+ PIN_ODR_LEVEL_HIGH(PE08_UART7_TX) | \
+ PIN_ODR_LEVEL_HIGH(PE09_UART7_RTS) | \
+ PIN_ODR_LEVEL_HIGH(PE10_UART7_CTS) | \
+ PIN_ODR_LEVEL_HIGH(PE11_SPI_SLAVE3) | \
+ PIN_ODR_LEVEL_HIGH(PE12_SPI4_CLK) | \
+ PIN_ODR_LEVEL_HIGH(PE13_SPI4_MISO) | \
+ PIN_ODR_LEVEL_HIGH(PE14_SPI4_MOSI) | \
+ PIN_ODR_LEVEL_LOW(PE15))
+
+#define VAL_GPIOE_AFRL (PIN_AFIO_AF(PE00_UART8_RX, 8) | \
+ PIN_AFIO_AF(PE01_UART8_TX, 8) | \
+ PIN_AFIO_AF(PE02_SPI_SLAVE2, 0) | \
+ PIN_AFIO_AF(PE03_LED1, 0) | \
+ PIN_AFIO_AF(PE04_LED2, 0) | \
+ PIN_AFIO_AF(PE05_SERVO11, 4) | \
+ PIN_AFIO_AF(PE06_SERVO12, 4) | \
+ PIN_AFIO_AF(PE07_UART7_RX, 7))
+
+#define VAL_GPIOE_AFRH (PIN_AFIO_AF(PE08_UART7_TX, 7) | \
+ PIN_AFIO_AF(PE09_UART7_RTS, 0) | \
+ PIN_AFIO_AF(PE10_UART7_CTS, 0) | \
+ PIN_AFIO_AF(PE11_SPI_SLAVE3, 0) | \
+ PIN_AFIO_AF(PE12_SPI4_CLK, 5) | \
+ PIN_AFIO_AF(PE13_SPI4_MISO, 5) | \
+ PIN_AFIO_AF(PE14_SPI4_MOSI, 5) | \
+ PIN_AFIO_AF(PE15, 0))
+
+#define VAL_GPIOF_MODER (PIN_MODE_INPUT(PF00) | \
+ PIN_MODE_INPUT(PF01) | \
+ PIN_MODE_INPUT(PF02) | \
+ PIN_MODE_INPUT(PF03) | \
+ PIN_MODE_INPUT(PF04) | \
+ PIN_MODE_INPUT(PF05) | \
+ PIN_MODE_INPUT(PF06) | \
+ PIN_MODE_INPUT(PF07) | \
+ PIN_MODE_INPUT(PF08) | \
+ PIN_MODE_INPUT(PF09) | \
+ PIN_MODE_INPUT(PF10) | \
+ PIN_MODE_INPUT(PF11) | \
+ PIN_MODE_INPUT(PF12) | \
+ PIN_MODE_INPUT(PF13) | \
+ PIN_MODE_INPUT(PF14) | \
+ PIN_MODE_INPUT(PF15))
+
+#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(PF00) | \
+ PIN_OTYPE_PUSHPULL(PF01) | \
+ PIN_OTYPE_PUSHPULL(PF02) | \
+ PIN_OTYPE_PUSHPULL(PF03) | \
+ PIN_OTYPE_PUSHPULL(PF04) | \
+ PIN_OTYPE_PUSHPULL(PF05) | \
+ PIN_OTYPE_PUSHPULL(PF06) | \
+ PIN_OTYPE_PUSHPULL(PF07) | \
+ PIN_OTYPE_PUSHPULL(PF08) | \
+ PIN_OTYPE_PUSHPULL(PF09) | \
+ PIN_OTYPE_PUSHPULL(PF10) | \
+ PIN_OTYPE_PUSHPULL(PF11) | \
+ PIN_OTYPE_PUSHPULL(PF12) | \
+ PIN_OTYPE_PUSHPULL(PF13) | \
+ PIN_OTYPE_PUSHPULL(PF14) | \
+ PIN_OTYPE_PUSHPULL(PF15))
+
+#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(PF00) | \
+ PIN_OSPEED_SPEED_VERYLOW(PF01) | \
+ PIN_OSPEED_SPEED_VERYLOW(PF02) | \
+ PIN_OSPEED_SPEED_VERYLOW(PF03) | \
+ PIN_OSPEED_SPEED_VERYLOW(PF04) | \
+ PIN_OSPEED_SPEED_VERYLOW(PF05) | \
+ PIN_OSPEED_SPEED_VERYLOW(PF06) | \
+ PIN_OSPEED_SPEED_VERYLOW(PF07) | \
+ PIN_OSPEED_SPEED_VERYLOW(PF08) | \
+ PIN_OSPEED_SPEED_VERYLOW(PF09) | \
+ PIN_OSPEED_SPEED_VERYLOW(PF10) | \
+ PIN_OSPEED_SPEED_VERYLOW(PF11) | \
+ PIN_OSPEED_SPEED_VERYLOW(PF12) | \
+ PIN_OSPEED_SPEED_VERYLOW(PF13) | \
+ PIN_OSPEED_SPEED_VERYLOW(PF14) | \
+ PIN_OSPEED_SPEED_VERYLOW(PF15))
+
+#define VAL_GPIOF_PUPDR (PIN_PUPDR_PULLDOWN(PF00) | \
+ PIN_PUPDR_PULLDOWN(PF01) | \
+ PIN_PUPDR_PULLDOWN(PF02) | \
+ PIN_PUPDR_PULLDOWN(PF03) | \
+ PIN_PUPDR_PULLDOWN(PF04) | \
+ PIN_PUPDR_PULLDOWN(PF05) | \
+ PIN_PUPDR_PULLDOWN(PF06) | \
+ PIN_PUPDR_PULLDOWN(PF07) | \
+ PIN_PUPDR_PULLDOWN(PF08) | \
+ PIN_PUPDR_PULLDOWN(PF09) | \
+ PIN_PUPDR_PULLDOWN(PF10) | \
+ PIN_PUPDR_PULLDOWN(PF11) | \
+ PIN_PUPDR_PULLDOWN(PF12) | \
+ PIN_PUPDR_PULLDOWN(PF13) | \
+ PIN_PUPDR_PULLDOWN(PF14) | \
+ PIN_PUPDR_PULLDOWN(PF15))
+
+#define VAL_GPIOF_ODR (PIN_ODR_LEVEL_LOW(PF00) | \
+ PIN_ODR_LEVEL_LOW(PF01) | \
+ PIN_ODR_LEVEL_LOW(PF02) | \
+ PIN_ODR_LEVEL_LOW(PF03) | \
+ PIN_ODR_LEVEL_LOW(PF04) | \
+ PIN_ODR_LEVEL_LOW(PF05) | \
+ PIN_ODR_LEVEL_LOW(PF06) | \
+ PIN_ODR_LEVEL_LOW(PF07) | \
+ PIN_ODR_LEVEL_LOW(PF08) | \
+ PIN_ODR_LEVEL_LOW(PF09) | \
+ PIN_ODR_LEVEL_LOW(PF10) | \
+ PIN_ODR_LEVEL_LOW(PF11) | \
+ PIN_ODR_LEVEL_LOW(PF12) | \
+ PIN_ODR_LEVEL_LOW(PF13) | \
+ PIN_ODR_LEVEL_LOW(PF14) | \
+ PIN_ODR_LEVEL_LOW(PF15))
+
+#define VAL_GPIOF_AFRL (PIN_AFIO_AF(PF00, 0) | \
+ PIN_AFIO_AF(PF01, 0) | \
+ PIN_AFIO_AF(PF02, 0) | \
+ PIN_AFIO_AF(PF03, 0) | \
+ PIN_AFIO_AF(PF04, 0) | \
+ PIN_AFIO_AF(PF05, 0) | \
+ PIN_AFIO_AF(PF06, 0) | \
+ PIN_AFIO_AF(PF07, 0))
+
+#define VAL_GPIOF_AFRH (PIN_AFIO_AF(PF08, 0) | \
+ PIN_AFIO_AF(PF09, 0) | \
+ PIN_AFIO_AF(PF10, 0) | \
+ PIN_AFIO_AF(PF11, 0) | \
+ PIN_AFIO_AF(PF12, 0) | \
+ PIN_AFIO_AF(PF13, 0) | \
+ PIN_AFIO_AF(PF14, 0) | \
+ PIN_AFIO_AF(PF15, 0))
+
+#define VAL_GPIOG_MODER (PIN_MODE_INPUT(PG00) | \
+ PIN_MODE_INPUT(PG01) | \
+ PIN_MODE_INPUT(PG02) | \
+ PIN_MODE_INPUT(PG03) | \
+ PIN_MODE_INPUT(PG04) | \
+ PIN_MODE_INPUT(PG05) | \
+ PIN_MODE_INPUT(PG06) | \
+ PIN_MODE_INPUT(PG07) | \
+ PIN_MODE_INPUT(PG08) | \
+ PIN_MODE_INPUT(PG09) | \
+ PIN_MODE_INPUT(PG10) | \
+ PIN_MODE_INPUT(PG11) | \
+ PIN_MODE_INPUT(PG12) | \
+ PIN_MODE_INPUT(PG13) | \
+ PIN_MODE_INPUT(PG14) | \
+ PIN_MODE_INPUT(PG15))
+
+#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(PG00) | \
+ PIN_OTYPE_PUSHPULL(PG01) | \
+ PIN_OTYPE_PUSHPULL(PG02) | \
+ PIN_OTYPE_PUSHPULL(PG03) | \
+ PIN_OTYPE_PUSHPULL(PG04) | \
+ PIN_OTYPE_PUSHPULL(PG05) | \
+ PIN_OTYPE_PUSHPULL(PG06) | \
+ PIN_OTYPE_PUSHPULL(PG07) | \
+ PIN_OTYPE_PUSHPULL(PG08) | \
+ PIN_OTYPE_PUSHPULL(PG09) | \
+ PIN_OTYPE_PUSHPULL(PG10) | \
+ PIN_OTYPE_PUSHPULL(PG11) | \
+ PIN_OTYPE_PUSHPULL(PG12) | \
+ PIN_OTYPE_PUSHPULL(PG13) | \
+ PIN_OTYPE_PUSHPULL(PG14) | \
+ PIN_OTYPE_PUSHPULL(PG15))
+
+#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(PG00) | \
+ PIN_OSPEED_SPEED_VERYLOW(PG01) | \
+ PIN_OSPEED_SPEED_VERYLOW(PG02) | \
+ PIN_OSPEED_SPEED_VERYLOW(PG03) | \
+ PIN_OSPEED_SPEED_VERYLOW(PG04) | \
+ PIN_OSPEED_SPEED_VERYLOW(PG05) | \
+ PIN_OSPEED_SPEED_VERYLOW(PG06) | \
+ PIN_OSPEED_SPEED_VERYLOW(PG07) | \
+ PIN_OSPEED_SPEED_VERYLOW(PG08) | \
+ PIN_OSPEED_SPEED_VERYLOW(PG09) | \
+ PIN_OSPEED_SPEED_VERYLOW(PG10) | \
+ PIN_OSPEED_SPEED_VERYLOW(PG11) | \
+ PIN_OSPEED_SPEED_VERYLOW(PG12) | \
+ PIN_OSPEED_SPEED_VERYLOW(PG13) | \
+ PIN_OSPEED_SPEED_VERYLOW(PG14) | \
+ PIN_OSPEED_SPEED_VERYLOW(PG15))
+
+#define VAL_GPIOG_PUPDR (PIN_PUPDR_PULLDOWN(PG00) | \
+ PIN_PUPDR_PULLDOWN(PG01) | \
+ PIN_PUPDR_PULLDOWN(PG02) | \
+ PIN_PUPDR_PULLDOWN(PG03) | \
+ PIN_PUPDR_PULLDOWN(PG04) | \
+ PIN_PUPDR_PULLDOWN(PG05) | \
+ PIN_PUPDR_PULLDOWN(PG06) | \
+ PIN_PUPDR_PULLDOWN(PG07) | \
+ PIN_PUPDR_PULLDOWN(PG08) | \
+ PIN_PUPDR_PULLDOWN(PG09) | \
+ PIN_PUPDR_PULLDOWN(PG10) | \
+ PIN_PUPDR_PULLDOWN(PG11) | \
+ PIN_PUPDR_PULLDOWN(PG12) | \
+ PIN_PUPDR_PULLDOWN(PG13) | \
+ PIN_PUPDR_PULLDOWN(PG14) | \
+ PIN_PUPDR_PULLDOWN(PG15))
+
+#define VAL_GPIOG_ODR (PIN_ODR_LEVEL_LOW(PG00) | \
+ PIN_ODR_LEVEL_LOW(PG01) | \
+ PIN_ODR_LEVEL_LOW(PG02) | \
+ PIN_ODR_LEVEL_LOW(PG03) | \
+ PIN_ODR_LEVEL_LOW(PG04) | \
+ PIN_ODR_LEVEL_LOW(PG05) | \
+ PIN_ODR_LEVEL_LOW(PG06) | \
+ PIN_ODR_LEVEL_LOW(PG07) | \
+ PIN_ODR_LEVEL_LOW(PG08) | \
+ PIN_ODR_LEVEL_LOW(PG09) | \
+ PIN_ODR_LEVEL_LOW(PG10) | \
+ PIN_ODR_LEVEL_LOW(PG11) | \
+ PIN_ODR_LEVEL_LOW(PG12) | \
+ PIN_ODR_LEVEL_LOW(PG13) | \
+ PIN_ODR_LEVEL_LOW(PG14) | \
+ PIN_ODR_LEVEL_LOW(PG15))
+
+#define VAL_GPIOG_AFRL (PIN_AFIO_AF(PG00, 0) | \
+ PIN_AFIO_AF(PG01, 0) | \
+ PIN_AFIO_AF(PG02, 0) | \
+ PIN_AFIO_AF(PG03, 0) | \
+ PIN_AFIO_AF(PG04, 0) | \
+ PIN_AFIO_AF(PG05, 0) | \
+ PIN_AFIO_AF(PG06, 0) | \
+ PIN_AFIO_AF(PG07, 0))
+
+#define VAL_GPIOG_AFRH (PIN_AFIO_AF(PG08, 0) | \
+ PIN_AFIO_AF(PG09, 0) | \
+ PIN_AFIO_AF(PG10, 0) | \
+ PIN_AFIO_AF(PG11, 0) | \
+ PIN_AFIO_AF(PG12, 0) | \
+ PIN_AFIO_AF(PG13, 0) | \
+ PIN_AFIO_AF(PG14, 0) | \
+ PIN_AFIO_AF(PG15, 0))
+
+#define VAL_GPIOH_MODER (PIN_MODE_ALTERNATE(PH00_OSC_IN) | \
+ PIN_MODE_ALTERNATE(PH01_OSC_OUT) | \
+ PIN_MODE_INPUT(PH02) | \
+ PIN_MODE_INPUT(PH03) | \
+ PIN_MODE_INPUT(PH04) | \
+ PIN_MODE_INPUT(PH05) | \
+ PIN_MODE_INPUT(PH06) | \
+ PIN_MODE_INPUT(PH07) | \
+ PIN_MODE_INPUT(PH08) | \
+ PIN_MODE_INPUT(PH09) | \
+ PIN_MODE_INPUT(PH10) | \
+ PIN_MODE_INPUT(PH11) | \
+ PIN_MODE_INPUT(PH12) | \
+ PIN_MODE_INPUT(PH13) | \
+ PIN_MODE_INPUT(PH14) | \
+ PIN_MODE_INPUT(PH15))
+
+#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(PH00_OSC_IN) | \
+ PIN_OTYPE_PUSHPULL(PH01_OSC_OUT) | \
+ PIN_OTYPE_PUSHPULL(PH02) | \
+ PIN_OTYPE_PUSHPULL(PH03) | \
+ PIN_OTYPE_PUSHPULL(PH04) | \
+ PIN_OTYPE_PUSHPULL(PH05) | \
+ PIN_OTYPE_PUSHPULL(PH06) | \
+ PIN_OTYPE_PUSHPULL(PH07) | \
+ PIN_OTYPE_PUSHPULL(PH08) | \
+ PIN_OTYPE_PUSHPULL(PH09) | \
+ PIN_OTYPE_PUSHPULL(PH10) | \
+ PIN_OTYPE_PUSHPULL(PH11) | \
+ PIN_OTYPE_PUSHPULL(PH12) | \
+ PIN_OTYPE_PUSHPULL(PH13) | \
+ PIN_OTYPE_PUSHPULL(PH14) | \
+ PIN_OTYPE_PUSHPULL(PH15))
+
+#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_SPEED_HIGH(PH00_OSC_IN) | \
+ PIN_OSPEED_SPEED_HIGH(PH01_OSC_OUT) | \
+ PIN_OSPEED_SPEED_VERYLOW(PH02) | \
+ PIN_OSPEED_SPEED_VERYLOW(PH03) | \
+ PIN_OSPEED_SPEED_VERYLOW(PH04) | \
+ PIN_OSPEED_SPEED_VERYLOW(PH05) | \
+ PIN_OSPEED_SPEED_VERYLOW(PH06) | \
+ PIN_OSPEED_SPEED_VERYLOW(PH07) | \
+ PIN_OSPEED_SPEED_VERYLOW(PH08) | \
+ PIN_OSPEED_SPEED_VERYLOW(PH09) | \
+ PIN_OSPEED_SPEED_VERYLOW(PH10) | \
+ PIN_OSPEED_SPEED_VERYLOW(PH11) | \
+ PIN_OSPEED_SPEED_VERYLOW(PH12) | \
+ PIN_OSPEED_SPEED_VERYLOW(PH13) | \
+ PIN_OSPEED_SPEED_VERYLOW(PH14) | \
+ PIN_OSPEED_SPEED_VERYLOW(PH15))
+
+#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(PH00_OSC_IN) | \
+ PIN_PUPDR_FLOATING(PH01_OSC_OUT) | \
+ PIN_PUPDR_PULLDOWN(PH02) | \
+ PIN_PUPDR_PULLDOWN(PH03) | \
+ PIN_PUPDR_PULLDOWN(PH04) | \
+ PIN_PUPDR_PULLDOWN(PH05) | \
+ PIN_PUPDR_PULLDOWN(PH06) | \
+ PIN_PUPDR_PULLDOWN(PH07) | \
+ PIN_PUPDR_PULLDOWN(PH08) | \
+ PIN_PUPDR_PULLDOWN(PH09) | \
+ PIN_PUPDR_PULLDOWN(PH10) | \
+ PIN_PUPDR_PULLDOWN(PH11) | \
+ PIN_PUPDR_PULLDOWN(PH12) | \
+ PIN_PUPDR_PULLDOWN(PH13) | \
+ PIN_PUPDR_PULLDOWN(PH14) | \
+ PIN_PUPDR_PULLDOWN(PH15))
+
+#define VAL_GPIOH_ODR (PIN_ODR_LEVEL_HIGH(PH00_OSC_IN) | \
+ PIN_ODR_LEVEL_HIGH(PH01_OSC_OUT) | \
+ PIN_ODR_LEVEL_LOW(PH02) | \
+ PIN_ODR_LEVEL_LOW(PH03) | \
+ PIN_ODR_LEVEL_LOW(PH04) | \
+ PIN_ODR_LEVEL_LOW(PH05) | \
+ PIN_ODR_LEVEL_LOW(PH06) | \
+ PIN_ODR_LEVEL_LOW(PH07) | \
+ PIN_ODR_LEVEL_LOW(PH08) | \
+ PIN_ODR_LEVEL_LOW(PH09) | \
+ PIN_ODR_LEVEL_LOW(PH10) | \
+ PIN_ODR_LEVEL_LOW(PH11) | \
+ PIN_ODR_LEVEL_LOW(PH12) | \
+ PIN_ODR_LEVEL_LOW(PH13) | \
+ PIN_ODR_LEVEL_LOW(PH14) | \
+ PIN_ODR_LEVEL_LOW(PH15))
+
+#define VAL_GPIOH_AFRL (PIN_AFIO_AF(PH00_OSC_IN, 0) | \
+ PIN_AFIO_AF(PH01_OSC_OUT, 0) | \
+ PIN_AFIO_AF(PH02, 0) | \
+ PIN_AFIO_AF(PH03, 0) | \
+ PIN_AFIO_AF(PH04, 0) | \
+ PIN_AFIO_AF(PH05, 0) | \
+ PIN_AFIO_AF(PH06, 0) | \
+ PIN_AFIO_AF(PH07, 0))
+
+#define VAL_GPIOH_AFRH (PIN_AFIO_AF(PH08, 0) | \
+ PIN_AFIO_AF(PH09, 0) | \
+ PIN_AFIO_AF(PH10, 0) | \
+ PIN_AFIO_AF(PH11, 0) | \
+ PIN_AFIO_AF(PH12, 0) | \
+ PIN_AFIO_AF(PH13, 0) | \
+ PIN_AFIO_AF(PH14, 0) | \
+ PIN_AFIO_AF(PH15, 0))
+
+#define VAL_GPIOI_MODER (PIN_MODE_INPUT(PI00) | \
+ PIN_MODE_INPUT(PI01) | \
+ PIN_MODE_INPUT(PI02) | \
+ PIN_MODE_INPUT(PI03) | \
+ PIN_MODE_INPUT(PI04) | \
+ PIN_MODE_INPUT(PI05) | \
+ PIN_MODE_INPUT(PI06) | \
+ PIN_MODE_INPUT(PI07) | \
+ PIN_MODE_INPUT(PI08) | \
+ PIN_MODE_INPUT(PI09) | \
+ PIN_MODE_INPUT(PI10) | \
+ PIN_MODE_INPUT(PI11) | \
+ PIN_MODE_INPUT(PI12) | \
+ PIN_MODE_INPUT(PI13) | \
+ PIN_MODE_INPUT(PI14) | \
+ PIN_MODE_INPUT(PI15))
+
+#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(PI00) | \
+ PIN_OTYPE_PUSHPULL(PI01) | \
+ PIN_OTYPE_PUSHPULL(PI02) | \
+ PIN_OTYPE_PUSHPULL(PI03) | \
+ PIN_OTYPE_PUSHPULL(PI04) | \
+ PIN_OTYPE_PUSHPULL(PI05) | \
+ PIN_OTYPE_PUSHPULL(PI06) | \
+ PIN_OTYPE_PUSHPULL(PI07) | \
+ PIN_OTYPE_PUSHPULL(PI08) | \
+ PIN_OTYPE_PUSHPULL(PI09) | \
+ PIN_OTYPE_PUSHPULL(PI10) | \
+ PIN_OTYPE_PUSHPULL(PI11) | \
+ PIN_OTYPE_PUSHPULL(PI12) | \
+ PIN_OTYPE_PUSHPULL(PI13) | \
+ PIN_OTYPE_PUSHPULL(PI14) | \
+ PIN_OTYPE_PUSHPULL(PI15))
+
+#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(PI00) | \
+ PIN_OSPEED_SPEED_VERYLOW(PI01) | \
+ PIN_OSPEED_SPEED_VERYLOW(PI02) | \
+ PIN_OSPEED_SPEED_VERYLOW(PI03) | \
+ PIN_OSPEED_SPEED_VERYLOW(PI04) | \
+ PIN_OSPEED_SPEED_VERYLOW(PI05) | \
+ PIN_OSPEED_SPEED_VERYLOW(PI06) | \
+ PIN_OSPEED_SPEED_VERYLOW(PI07) | \
+ PIN_OSPEED_SPEED_VERYLOW(PI08) | \
+ PIN_OSPEED_SPEED_VERYLOW(PI09) | \
+ PIN_OSPEED_SPEED_VERYLOW(PI10) | \
+ PIN_OSPEED_SPEED_VERYLOW(PI11) | \
+ PIN_OSPEED_SPEED_VERYLOW(PI12) | \
+ PIN_OSPEED_SPEED_VERYLOW(PI13) | \
+ PIN_OSPEED_SPEED_VERYLOW(PI14) | \
+ PIN_OSPEED_SPEED_VERYLOW(PI15))
+
+#define VAL_GPIOI_PUPDR (PIN_PUPDR_PULLDOWN(PI00) | \
+ PIN_PUPDR_PULLDOWN(PI01) | \
+ PIN_PUPDR_PULLDOWN(PI02) | \
+ PIN_PUPDR_PULLDOWN(PI03) | \
+ PIN_PUPDR_PULLDOWN(PI04) | \
+ PIN_PUPDR_PULLDOWN(PI05) | \
+ PIN_PUPDR_PULLDOWN(PI06) | \
+ PIN_PUPDR_PULLDOWN(PI07) | \
+ PIN_PUPDR_PULLDOWN(PI08) | \
+ PIN_PUPDR_PULLDOWN(PI09) | \
+ PIN_PUPDR_PULLDOWN(PI10) | \
+ PIN_PUPDR_PULLDOWN(PI11) | \
+ PIN_PUPDR_PULLDOWN(PI12) | \
+ PIN_PUPDR_PULLDOWN(PI13) | \
+ PIN_PUPDR_PULLDOWN(PI14) | \
+ PIN_PUPDR_PULLDOWN(PI15))
+
+#define VAL_GPIOI_ODR (PIN_ODR_LEVEL_LOW(PI00) | \
+ PIN_ODR_LEVEL_LOW(PI01) | \
+ PIN_ODR_LEVEL_LOW(PI02) | \
+ PIN_ODR_LEVEL_LOW(PI03) | \
+ PIN_ODR_LEVEL_LOW(PI04) | \
+ PIN_ODR_LEVEL_LOW(PI05) | \
+ PIN_ODR_LEVEL_LOW(PI06) | \
+ PIN_ODR_LEVEL_LOW(PI07) | \
+ PIN_ODR_LEVEL_LOW(PI08) | \
+ PIN_ODR_LEVEL_LOW(PI09) | \
+ PIN_ODR_LEVEL_LOW(PI10) | \
+ PIN_ODR_LEVEL_LOW(PI11) | \
+ PIN_ODR_LEVEL_LOW(PI12) | \
+ PIN_ODR_LEVEL_LOW(PI13) | \
+ PIN_ODR_LEVEL_LOW(PI14) | \
+ PIN_ODR_LEVEL_LOW(PI15))
+
+#define VAL_GPIOI_AFRL (PIN_AFIO_AF(PI00, 0) | \
+ PIN_AFIO_AF(PI01, 0) | \
+ PIN_AFIO_AF(PI02, 0) | \
+ PIN_AFIO_AF(PI03, 0) | \
+ PIN_AFIO_AF(PI04, 0) | \
+ PIN_AFIO_AF(PI05, 0) | \
+ PIN_AFIO_AF(PI06, 0) | \
+ PIN_AFIO_AF(PI07, 0))
+
+#define VAL_GPIOI_AFRH (PIN_AFIO_AF(PI08, 0) | \
+ PIN_AFIO_AF(PI09, 0) | \
+ PIN_AFIO_AF(PI10, 0) | \
+ PIN_AFIO_AF(PI11, 0) | \
+ PIN_AFIO_AF(PI12, 0) | \
+ PIN_AFIO_AF(PI13, 0) | \
+ PIN_AFIO_AF(PI14, 0) | \
+ PIN_AFIO_AF(PI15, 0))
+
+#define VAL_GPIOJ_MODER (PIN_MODE_INPUT(PJ00) | \
+ PIN_MODE_INPUT(PJ01) | \
+ PIN_MODE_INPUT(PJ02) | \
+ PIN_MODE_INPUT(PJ03) | \
+ PIN_MODE_INPUT(PJ04) | \
+ PIN_MODE_INPUT(PJ05) | \
+ PIN_MODE_INPUT(PJ06) | \
+ PIN_MODE_INPUT(PJ07) | \
+ PIN_MODE_INPUT(PJ08) | \
+ PIN_MODE_INPUT(PJ09) | \
+ PIN_MODE_INPUT(PJ10) | \
+ PIN_MODE_INPUT(PJ11) | \
+ PIN_MODE_INPUT(PJ12) | \
+ PIN_MODE_INPUT(PJ13) | \
+ PIN_MODE_INPUT(PJ14) | \
+ PIN_MODE_INPUT(PJ15))
+
+#define VAL_GPIOJ_OTYPER (PIN_OTYPE_PUSHPULL(PJ00) | \
+ PIN_OTYPE_PUSHPULL(PJ01) | \
+ PIN_OTYPE_PUSHPULL(PJ02) | \
+ PIN_OTYPE_PUSHPULL(PJ03) | \
+ PIN_OTYPE_PUSHPULL(PJ04) | \
+ PIN_OTYPE_PUSHPULL(PJ05) | \
+ PIN_OTYPE_PUSHPULL(PJ06) | \
+ PIN_OTYPE_PUSHPULL(PJ07) | \
+ PIN_OTYPE_PUSHPULL(PJ08) | \
+ PIN_OTYPE_PUSHPULL(PJ09) | \
+ PIN_OTYPE_PUSHPULL(PJ10) | \
+ PIN_OTYPE_PUSHPULL(PJ11) | \
+ PIN_OTYPE_PUSHPULL(PJ12) | \
+ PIN_OTYPE_PUSHPULL(PJ13) | \
+ PIN_OTYPE_PUSHPULL(PJ14) | \
+ PIN_OTYPE_PUSHPULL(PJ15))
+
+#define VAL_GPIOJ_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(PJ00) | \
+ PIN_OSPEED_SPEED_VERYLOW(PJ01) | \
+ PIN_OSPEED_SPEED_VERYLOW(PJ02) | \
+ PIN_OSPEED_SPEED_VERYLOW(PJ03) | \
+ PIN_OSPEED_SPEED_VERYLOW(PJ04) | \
+ PIN_OSPEED_SPEED_VERYLOW(PJ05) | \
+ PIN_OSPEED_SPEED_VERYLOW(PJ06) | \
+ PIN_OSPEED_SPEED_VERYLOW(PJ07) | \
+ PIN_OSPEED_SPEED_VERYLOW(PJ08) | \
+ PIN_OSPEED_SPEED_VERYLOW(PJ09) | \
+ PIN_OSPEED_SPEED_VERYLOW(PJ10) | \
+ PIN_OSPEED_SPEED_VERYLOW(PJ11) | \
+ PIN_OSPEED_SPEED_VERYLOW(PJ12) | \
+ PIN_OSPEED_SPEED_VERYLOW(PJ13) | \
+ PIN_OSPEED_SPEED_VERYLOW(PJ14) | \
+ PIN_OSPEED_SPEED_VERYLOW(PJ15))
+
+#define VAL_GPIOJ_PUPDR (PIN_PUPDR_PULLDOWN(PJ00) | \
+ PIN_PUPDR_PULLDOWN(PJ01) | \
+ PIN_PUPDR_PULLDOWN(PJ02) | \
+ PIN_PUPDR_PULLDOWN(PJ03) | \
+ PIN_PUPDR_PULLDOWN(PJ04) | \
+ PIN_PUPDR_PULLDOWN(PJ05) | \
+ PIN_PUPDR_PULLDOWN(PJ06) | \
+ PIN_PUPDR_PULLDOWN(PJ07) | \
+ PIN_PUPDR_PULLDOWN(PJ08) | \
+ PIN_PUPDR_PULLDOWN(PJ09) | \
+ PIN_PUPDR_PULLDOWN(PJ10) | \
+ PIN_PUPDR_PULLDOWN(PJ11) | \
+ PIN_PUPDR_PULLDOWN(PJ12) | \
+ PIN_PUPDR_PULLDOWN(PJ13) | \
+ PIN_PUPDR_PULLDOWN(PJ14) | \
+ PIN_PUPDR_PULLDOWN(PJ15))
+
+#define VAL_GPIOJ_ODR (PIN_ODR_LEVEL_LOW(PJ00) | \
+ PIN_ODR_LEVEL_LOW(PJ01) | \
+ PIN_ODR_LEVEL_LOW(PJ02) | \
+ PIN_ODR_LEVEL_LOW(PJ03) | \
+ PIN_ODR_LEVEL_LOW(PJ04) | \
+ PIN_ODR_LEVEL_LOW(PJ05) | \
+ PIN_ODR_LEVEL_LOW(PJ06) | \
+ PIN_ODR_LEVEL_LOW(PJ07) | \
+ PIN_ODR_LEVEL_LOW(PJ08) | \
+ PIN_ODR_LEVEL_LOW(PJ09) | \
+ PIN_ODR_LEVEL_LOW(PJ10) | \
+ PIN_ODR_LEVEL_LOW(PJ11) | \
+ PIN_ODR_LEVEL_LOW(PJ12) | \
+ PIN_ODR_LEVEL_LOW(PJ13) | \
+ PIN_ODR_LEVEL_LOW(PJ14) | \
+ PIN_ODR_LEVEL_LOW(PJ15))
+
+#define VAL_GPIOJ_AFRL (PIN_AFIO_AF(PJ00, 0) | \
+ PIN_AFIO_AF(PJ01, 0) | \
+ PIN_AFIO_AF(PJ02, 0) | \
+ PIN_AFIO_AF(PJ03, 0) | \
+ PIN_AFIO_AF(PJ04, 0) | \
+ PIN_AFIO_AF(PJ05, 0) | \
+ PIN_AFIO_AF(PJ06, 0) | \
+ PIN_AFIO_AF(PJ07, 0))
+
+#define VAL_GPIOJ_AFRH (PIN_AFIO_AF(PJ08, 0) | \
+ PIN_AFIO_AF(PJ09, 0) | \
+ PIN_AFIO_AF(PJ10, 0) | \
+ PIN_AFIO_AF(PJ11, 0) | \
+ PIN_AFIO_AF(PJ12, 0) | \
+ PIN_AFIO_AF(PJ13, 0) | \
+ PIN_AFIO_AF(PJ14, 0) | \
+ PIN_AFIO_AF(PJ15, 0))
+
+#define VAL_GPIOK_MODER (PIN_MODE_INPUT(PK00) | \
+ PIN_MODE_INPUT(PK01) | \
+ PIN_MODE_INPUT(PK02) | \
+ PIN_MODE_INPUT(PK03) | \
+ PIN_MODE_INPUT(PK04) | \
+ PIN_MODE_INPUT(PK05) | \
+ PIN_MODE_INPUT(PK06) | \
+ PIN_MODE_INPUT(PK07) | \
+ PIN_MODE_INPUT(PK08) | \
+ PIN_MODE_INPUT(PK09) | \
+ PIN_MODE_INPUT(PK10) | \
+ PIN_MODE_INPUT(PK11) | \
+ PIN_MODE_INPUT(PK12) | \
+ PIN_MODE_INPUT(PK13) | \
+ PIN_MODE_INPUT(PK14) | \
+ PIN_MODE_INPUT(PK15))
+
+#define VAL_GPIOK_OTYPER (PIN_OTYPE_PUSHPULL(PK00) | \
+ PIN_OTYPE_PUSHPULL(PK01) | \
+ PIN_OTYPE_PUSHPULL(PK02) | \
+ PIN_OTYPE_PUSHPULL(PK03) | \
+ PIN_OTYPE_PUSHPULL(PK04) | \
+ PIN_OTYPE_PUSHPULL(PK05) | \
+ PIN_OTYPE_PUSHPULL(PK06) | \
+ PIN_OTYPE_PUSHPULL(PK07) | \
+ PIN_OTYPE_PUSHPULL(PK08) | \
+ PIN_OTYPE_PUSHPULL(PK09) | \
+ PIN_OTYPE_PUSHPULL(PK10) | \
+ PIN_OTYPE_PUSHPULL(PK11) | \
+ PIN_OTYPE_PUSHPULL(PK12) | \
+ PIN_OTYPE_PUSHPULL(PK13) | \
+ PIN_OTYPE_PUSHPULL(PK14) | \
+ PIN_OTYPE_PUSHPULL(PK15))
+
+#define VAL_GPIOK_OSPEEDR (PIN_OSPEED_SPEED_VERYLOW(PK00) | \
+ PIN_OSPEED_SPEED_VERYLOW(PK01) | \
+ PIN_OSPEED_SPEED_VERYLOW(PK02) | \
+ PIN_OSPEED_SPEED_VERYLOW(PK03) | \
+ PIN_OSPEED_SPEED_VERYLOW(PK04) | \
+ PIN_OSPEED_SPEED_VERYLOW(PK05) | \
+ PIN_OSPEED_SPEED_VERYLOW(PK06) | \
+ PIN_OSPEED_SPEED_VERYLOW(PK07) | \
+ PIN_OSPEED_SPEED_VERYLOW(PK08) | \
+ PIN_OSPEED_SPEED_VERYLOW(PK09) | \
+ PIN_OSPEED_SPEED_VERYLOW(PK10) | \
+ PIN_OSPEED_SPEED_VERYLOW(PK11) | \
+ PIN_OSPEED_SPEED_VERYLOW(PK12) | \
+ PIN_OSPEED_SPEED_VERYLOW(PK13) | \
+ PIN_OSPEED_SPEED_VERYLOW(PK14) | \
+ PIN_OSPEED_SPEED_VERYLOW(PK15))
+
+#define VAL_GPIOK_PUPDR (PIN_PUPDR_PULLDOWN(PK00) | \
+ PIN_PUPDR_PULLDOWN(PK01) | \
+ PIN_PUPDR_PULLDOWN(PK02) | \
+ PIN_PUPDR_PULLDOWN(PK03) | \
+ PIN_PUPDR_PULLDOWN(PK04) | \
+ PIN_PUPDR_PULLDOWN(PK05) | \
+ PIN_PUPDR_PULLDOWN(PK06) | \
+ PIN_PUPDR_PULLDOWN(PK07) | \
+ PIN_PUPDR_PULLDOWN(PK08) | \
+ PIN_PUPDR_PULLDOWN(PK09) | \
+ PIN_PUPDR_PULLDOWN(PK10) | \
+ PIN_PUPDR_PULLDOWN(PK11) | \
+ PIN_PUPDR_PULLDOWN(PK12) | \
+ PIN_PUPDR_PULLDOWN(PK13) | \
+ PIN_PUPDR_PULLDOWN(PK14) | \
+ PIN_PUPDR_PULLDOWN(PK15))
+
+#define VAL_GPIOK_ODR (PIN_ODR_LEVEL_LOW(PK00) | \
+ PIN_ODR_LEVEL_LOW(PK01) | \
+ PIN_ODR_LEVEL_LOW(PK02) | \
+ PIN_ODR_LEVEL_LOW(PK03) | \
+ PIN_ODR_LEVEL_LOW(PK04) | \
+ PIN_ODR_LEVEL_LOW(PK05) | \
+ PIN_ODR_LEVEL_LOW(PK06) | \
+ PIN_ODR_LEVEL_LOW(PK07) | \
+ PIN_ODR_LEVEL_LOW(PK08) | \
+ PIN_ODR_LEVEL_LOW(PK09) | \
+ PIN_ODR_LEVEL_LOW(PK10) | \
+ PIN_ODR_LEVEL_LOW(PK11) | \
+ PIN_ODR_LEVEL_LOW(PK12) | \
+ PIN_ODR_LEVEL_LOW(PK13) | \
+ PIN_ODR_LEVEL_LOW(PK14) | \
+ PIN_ODR_LEVEL_LOW(PK15))
+
+#define VAL_GPIOK_AFRL (PIN_AFIO_AF(PK00, 0) | \
+ PIN_AFIO_AF(PK01, 0) | \
+ PIN_AFIO_AF(PK02, 0) | \
+ PIN_AFIO_AF(PK03, 0) | \
+ PIN_AFIO_AF(PK04, 0) | \
+ PIN_AFIO_AF(PK05, 0) | \
+ PIN_AFIO_AF(PK06, 0) | \
+ PIN_AFIO_AF(PK07, 0))
+
+#define VAL_GPIOK_AFRH (PIN_AFIO_AF(PK08, 0) | \
+ PIN_AFIO_AF(PK09, 0) | \
+ PIN_AFIO_AF(PK10, 0) | \
+ PIN_AFIO_AF(PK11, 0) | \
+ PIN_AFIO_AF(PK12, 0) | \
+ PIN_AFIO_AF(PK13, 0) | \
+ PIN_AFIO_AF(PK14, 0) | \
+ PIN_AFIO_AF(PK15, 0))
+
+#define AF_PA00_SERVO3 2U
+#define AF_LINE_SERVO3 2U
+#define AF_PA01_SERVO4 2U
+#define AF_LINE_SERVO4 2U
+#define AF_PA02_SERVO5 2U
+#define AF_LINE_SERVO5 2U
+#define AF_PA03_SERVO6 2U
+#define AF_LINE_SERVO6 2U
+#define AF_PA05_SPI1_SCK 5U
+#define AF_LINE_SPI1_SCK 5U
+#define AF_PA06_SPI1_MISO 5U
+#define AF_LINE_SPI1_MISO 5U
+#define AF_PA08_LED_WS2812 1U
+#define AF_LINE_LED_WS2812 1U
+#define AF_PA09_UART1_TX 7U
+#define AF_LINE_UART1_TX 7U
+#define AF_PA10_UART1_RX 7U
+#define AF_LINE_UART1_RX 7U
+#define AF_PA11_USB_DM 10U
+#define AF_LINE_USB_DM 10U
+#define AF_PA12_USB_DP 10U
+#define AF_LINE_USB_DP 10U
+#define AF_PA13_SWDIO 0U
+#define AF_LINE_SWDIO 0U
+#define AF_PA14_SWCLK 0U
+#define AF_LINE_SWCLK 0U
+#define AF_PA15_ALARM 1U
+#define AF_LINE_ALARM 1U
+#define AF_PB00_SERVO1 2U
+#define AF_LINE_SERVO1 2U
+#define AF_PB01_SERVO2 2U
+#define AF_LINE_SERVO2 2U
+#define AF_PB03_SPI3_SCK 6U
+#define AF_LINE_SPI3_SCK 6U
+#define AF_PB04_SPI3_MISO 6U
+#define AF_LINE_SPI3_MISO 6U
+#define AF_PB05_SPI3_MOSI 7U
+#define AF_LINE_SPI3_MOSI 7U
+#define AF_PB06_I2C1_SCL 4U
+#define AF_LINE_I2C1_SCL 4U
+#define AF_PB07_I2C1_SDA 4U
+#define AF_LINE_I2C1_SDA 4U
+#define AF_PB08_UART4_RX 8U
+#define AF_LINE_UART4_RX 8U
+#define AF_PB09_UART4_TX 8U
+#define AF_LINE_UART4_TX 8U
+#define AF_PB10_I2C2_SCL 4U
+#define AF_LINE_I2C2_SCL 4U
+#define AF_PB11_I2C2_SDA 4U
+#define AF_LINE_I2C2_SDA 4U
+#define AF_PB13_SPI2_SCK 5U
+#define AF_LINE_SPI2_SCK 5U
+#define AF_PB14_SPI2_MISO 5U
+#define AF_LINE_SPI2_MISO 5U
+#define AF_PB15_SPI2_MOSI 5U
+#define AF_LINE_SPI2_MOSI 5U
+#define AF_PC06_UART6_TX 7U
+#define AF_LINE_UART6_TX 7U
+#define AF_PC07_UART6_RX 7U
+#define AF_LINE_UART6_RX 7U
+#define AF_PC08_SDIO_D0 12U
+#define AF_LINE_SDIO_D0 12U
+#define AF_PC09_SDIO_D1 12U
+#define AF_LINE_SDIO_D1 12U
+#define AF_PC10_SDIO_D2 12U
+#define AF_LINE_SDIO_D2 12U
+#define AF_PC11_SDIO_D3 12U
+#define AF_LINE_SDIO_D3 12U
+#define AF_PC12_SDIO_CK 12U
+#define AF_LINE_SDIO_CK 12U
+#define AF_PD00_CAN1_RX 9U
+#define AF_LINE_CAN1_RX 9U
+#define AF_PD01_CAN1_TX 9U
+#define AF_LINE_CAN1_TX 9U
+#define AF_PD02_SDIO_CMD 12U
+#define AF_LINE_SDIO_CMD 12U
+#define AF_PD05_UART2_TX 7U
+#define AF_LINE_UART2_TX 7U
+#define AF_PD06_UART2_RX 7U
+#define AF_LINE_UART2_RX 7U
+#define AF_PD07_SPI1_MOSI 5U
+#define AF_LINE_SPI1_MOSI 5U
+#define AF_PD08_UART3_TX 7U
+#define AF_LINE_UART3_TX 7U
+#define AF_PD09_UART3_RX 7U
+#define AF_LINE_UART3_RX 7U
+#define AF_PD12_SERVO7 2U
+#define AF_LINE_SERVO7 2U
+#define AF_PD13_SERVO8 2U
+#define AF_LINE_SERVO8 2U
+#define AF_PD14_SERVO9 2U
+#define AF_LINE_SERVO9 2U
+#define AF_PD15_SERVO10 2U
+#define AF_LINE_SERVO10 2U
+#define AF_PE00_UART8_RX 8U
+#define AF_LINE_UART8_RX 8U
+#define AF_PE01_UART8_TX 8U
+#define AF_LINE_UART8_TX 8U
+#define AF_PE05_SERVO11 4U
+#define AF_LINE_SERVO11 4U
+#define AF_PE06_SERVO12 4U
+#define AF_LINE_SERVO12 4U
+#define AF_PE07_UART7_RX 7U
+#define AF_LINE_UART7_RX 7U
+#define AF_PE08_UART7_TX 7U
+#define AF_LINE_UART7_TX 7U
+#define AF_PE12_SPI4_CLK 5U
+#define AF_LINE_SPI4_CLK 5U
+#define AF_PE13_SPI4_MISO 5U
+#define AF_LINE_SPI4_MISO 5U
+#define AF_PE14_SPI4_MOSI 5U
+#define AF_LINE_SPI4_MOSI 5U
+#define AF_PH00_OSC_IN 0U
+#define AF_LINE_OSC_IN 0U
+#define AF_PH01_OSC_OUT 0U
+#define AF_LINE_OSC_OUT 0U
+
+
+#define SERVO3_TIM 5
+#define SERVO3_TIM_FN CH
+#define SERVO3_TIM_CH 1
+#define SERVO3_TIM_AF 2
+#define SERVO4_TIM 5
+#define SERVO4_TIM_FN CH
+#define SERVO4_TIM_CH 2
+#define SERVO4_TIM_AF 2
+#define SERVO5_TIM 5
+#define SERVO5_TIM_FN CH
+#define SERVO5_TIM_CH 3
+#define SERVO5_TIM_AF 2
+#define SERVO6_TIM 5
+#define SERVO6_TIM_FN CH
+#define SERVO6_TIM_CH 4
+#define SERVO6_TIM_AF 2
+#define ADC3_ADC 1
+#define ADC3_ADC_FN INP
+#define ADC3_ADC_INP 18
+#define ADC4_ADC 1
+#define ADC4_ADC_FN INP
+#define ADC4_ADC_INP 7
+#define LED_WS2812_TIM 1
+#define LED_WS2812_TIM_FN CH
+#define LED_WS2812_TIM_CH 1
+#define LED_WS2812_TIM_AF 1
+#define ALARM_TIM 2
+#define ALARM_TIM_FN CH
+#define ALARM_TIM_CH 1
+#define ALARM_TIM_AF 1
+#define SERVO1_TIM 3
+#define SERVO1_TIM_FN CH
+#define SERVO1_TIM_CH 3
+#define SERVO1_TIM_AF 2
+#define SERVO2_TIM 3
+#define SERVO2_TIM_FN CH
+#define SERVO2_TIM_CH 4
+#define SERVO2_TIM_AF 2
+#define ADC5_ADC 1
+#define ADC5_ADC_FN INP
+#define ADC5_ADC_INP 10
+#define ADC6_ADC 1
+#define ADC6_ADC_FN INP
+#define ADC6_ADC_INP 11
+#define ADC1_ADC 1
+#define ADC1_ADC_FN INP
+#define ADC1_ADC_INP 8
+#define ADC2_ADC 1
+#define ADC2_ADC_FN INP
+#define ADC2_ADC_INP 4
+#define SERVO7_TIM 4
+#define SERVO7_TIM_FN CH
+#define SERVO7_TIM_CH 1
+#define SERVO7_TIM_AF 2
+#define SERVO8_TIM 4
+#define SERVO8_TIM_FN CH
+#define SERVO8_TIM_CH 2
+#define SERVO8_TIM_AF 2
+#define SERVO9_TIM 4
+#define SERVO9_TIM_FN CH
+#define SERVO9_TIM_CH 3
+#define SERVO9_TIM_AF 2
+#define SERVO10_TIM 4
+#define SERVO10_TIM_FN CH
+#define SERVO10_TIM_CH 4
+#define SERVO10_TIM_AF 2
+#define SERVO11_TIM 15
+#define SERVO11_TIM_FN CH
+#define SERVO11_TIM_CH 1
+#define SERVO11_TIM_AF 4
+#define SERVO12_TIM 15
+#define SERVO12_TIM_FN CH
+#define SERVO12_TIM_CH 2
+#define SERVO12_TIM_AF 4
+
+#define BOARD_GROUP_DECLFOREACH(line, group) \
+ static const ioline_t group ## _ARRAY[] = {group}; \
+ for (ioline_t i=0, line = group ## _ARRAY[i]; (i < group ## _SIZE) && (line = group ## _ARRAY[i]); i++)
+
+#define BOARD_GROUP_FOREACH(line, group) \
+ for (ioline_t i=0, line = group ## _ARRAY[i]; (i < group ## _SIZE) && (line = group ## _ARRAY[i]); i++)
+
+
+#define BOARD_GROUP_DECLFOR(array, index, group) \
+ static const ioline_t group ## _ARRAY[] = {group}; \
+ for (ioline_t index=0, *array = (ioline_t *) group ## _ARRAY; index < group ## _SIZE; index++)
+
+#define BOARD_GROUP_FOR(array, index, group) \
+ for (ioline_t index=0, *array = (ioline_t *) group ## _ARRAY; index < group ## _SIZE; index++)
+
+#define ENERGY_SAVE_INPUTS \
+ LINE_SERVO3, \
+ LINE_SERVO4, \
+ LINE_SERVO5, \
+ LINE_SERVO6, \
+ LINE_SERVO1, \
+ LINE_SERVO2, \
+ LINE_SPI_SLAVE4, \
+ LINE_SPI_SLAVE6, \
+ LINE_SPI_SLAVE5, \
+ LINE_SPI_SLAVE1, \
+ LINE_SERVO7, \
+ LINE_SERVO8, \
+ LINE_SERVO9, \
+ LINE_SERVO10, \
+ LINE_SPI_SLAVE2, \
+ LINE_LED1, \
+ LINE_LED2, \
+ LINE_SERVO11, \
+ LINE_SERVO12, \
+ LINE_SPI_SLAVE3
+#define ENERGY_SAVE_INPUTS_SIZE 20
+
+#define ENERGY_SAVE_LOWS \
+ LINE_ALARM
+#define ENERGY_SAVE_LOWS_SIZE 1
+
+#if !defined(_FROM_ASM_)
+#ifdef __cplusplus
+extern "C" {
+#endif
+ void boardInit(void);
+#ifdef __cplusplus
+}
+#endif
+#endif /* _FROM_ASM_ */
+
diff --git a/sw/airborne/boards/mateksys/H743-WING/mcuconf_board.h b/sw/airborne/boards/mateksys/H743-WING/mcuconf_board.h
new file mode 100644
index 0000000000..3e66a3462c
--- /dev/null
+++ b/sw/airborne/boards/mateksys/H743-WING/mcuconf_board.h
@@ -0,0 +1,600 @@
+/*
+ ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
+
+ Licensed under the Apache License, Version 2.0 (the "License");
+ you may not use this file except in compliance with the License.
+ You may obtain a copy of the License at
+
+ http://www.apache.org/licenses/LICENSE-2.0
+
+ Unless required by applicable law or agreed to in writing, software
+ distributed under the License is distributed on an "AS IS" BASIS,
+ WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
+ See the License for the specific language governing permissions and
+ limitations under the License.
+*/
+
+#ifndef MCUCONF_H
+#define MCUCONF_H
+
+/*
+ * Enforce old versions of the chip
+ */
+#define STM32_ENFORCE_H7_REV_XY
+
+/*
+ * STM32H7xx drivers configuration.
+ * The following settings override the default settings present in
+ * the various device driver implementation headers.
+ * Note that the settings for each driver only have effect if the whole
+ * driver is enabled in halconf.h.
+ *
+ * IRQ priorities:
+ * 15...0 Lowest...Highest.
+ *
+ * DMA priorities:
+ * 0...3 Lowest...Highest.
+ */
+
+#define STM32H7xx_MCUCONF
+#define STM32H742_MCUCONF
+#define STM32H743_MCUCONF
+#define STM32H753_MCUCONF
+#define STM32H745_MCUCONF
+#define STM32H755_MCUCONF
+#define STM32H747_MCUCONF
+#define STM32H757_MCUCONF
+
+/*
+ * General settings.
+ */
+#define STM32_NO_INIT FALSE
+#define STM32_TARGET_CORE 1
+
+/*
+ * Memory attributes settings.
+ */
+#define STM32_NOCACHE_ENABLE TRUE
+#define STM32_NOCACHE_MPU_REGION MPU_REGION_6
+#define STM32_NOCACHE_RBAR 0x24000000U
+#define STM32_NOCACHE_RASR MPU_RASR_SIZE_64K
+
+/*
+ * PWR system settings.
+ * Reading STM32 Reference Manual is required, settings in PWR_CR3 are
+ * very critical.
+ * Register constants are taken from the ST header.
+ */
+#define STM32_VOS STM32_VOS_SCALE1
+#define STM32_PWR_CR1 (PWR_CR1_SVOS_1 | PWR_CR1_SVOS_0)
+#define STM32_PWR_CR2 (PWR_CR2_BREN)
+#define STM32_PWR_CR3 (PWR_CR3_LDOEN | PWR_CR3_USB33DEN)
+#define STM32_PWR_CPUCR 0
+
+/*
+ * Clock tree static settings.
+ * Reading STM32 Reference Manual is required.
+ */
+#define STM32_HSI_ENABLED FALSE
+#define STM32_LSI_ENABLED FALSE
+#define STM32_CSI_ENABLED FALSE
+#define STM32_HSI48_ENABLED TRUE
+#define STM32_HSE_ENABLED TRUE
+#define STM32_LSE_ENABLED FALSE
+#define STM32_HSIDIV STM32_HSIDIV_DIV1
+
+/*
+ * PLLs static settings.
+ * Reading STM32 Reference Manual is required.
+ */
+#define STM32_PLLSRC STM32_PLLSRC_HSE_CK
+#define STM32_PLLCFGR_MASK ~0
+#define STM32_PLL1_ENABLED TRUE
+#define STM32_PLL1_P_ENABLED TRUE
+#define STM32_PLL1_Q_ENABLED TRUE
+#define STM32_PLL1_R_ENABLED TRUE
+#define STM32_PLL1_DIVM_VALUE 1
+#define STM32_PLL1_DIVN_VALUE 100
+#define STM32_PLL1_FRACN_VALUE 0
+#define STM32_PLL1_DIVP_VALUE 2
+#define STM32_PLL1_DIVQ_VALUE 10
+#define STM32_PLL1_DIVR_VALUE 2
+#define STM32_PLL2_ENABLED TRUE
+#define STM32_PLL2_P_ENABLED TRUE
+#define STM32_PLL2_Q_ENABLED TRUE
+#define STM32_PLL2_R_ENABLED TRUE
+#define STM32_PLL2_DIVM_VALUE 1
+#define STM32_PLL2_DIVN_VALUE 45
+#define STM32_PLL2_FRACN_VALUE 0
+#define STM32_PLL2_DIVP_VALUE 2
+#define STM32_PLL2_DIVQ_VALUE 5
+#define STM32_PLL2_DIVR_VALUE 1
+#define STM32_PLL3_ENABLED TRUE
+#define STM32_PLL3_P_ENABLED TRUE
+#define STM32_PLL3_Q_ENABLED TRUE
+#define STM32_PLL3_R_ENABLED TRUE
+#define STM32_PLL3_DIVM_VALUE 2
+#define STM32_PLL3_DIVN_VALUE 72
+#define STM32_PLL3_FRACN_VALUE 0
+#define STM32_PLL3_DIVP_VALUE 2
+#define STM32_PLL3_DIVQ_VALUE 6
+#define STM32_PLL3_DIVR_VALUE 9
+
+/*
+ * Core clocks dynamic settings (can be changed at runtime).
+ * Reading STM32 Reference Manual is required.
+ */
+#define STM32_SW STM32_SW_PLL1_P_CK
+#define STM32_RTCSEL STM32_RTCSEL_NOCLK
+#define STM32_D1CPRE STM32_D1CPRE_DIV1
+#define STM32_D1HPRE STM32_D1HPRE_DIV2
+#define STM32_D1PPRE3 STM32_D1PPRE3_DIV2
+#define STM32_D2PPRE1 STM32_D2PPRE1_DIV2
+#define STM32_D2PPRE2 STM32_D2PPRE2_DIV2
+#define STM32_D3PPRE4 STM32_D3PPRE4_DIV2
+
+/*
+ * Peripherals clocks static settings.
+ * Reading STM32 Reference Manual is required.
+ */
+#define STM32_MCO1SEL STM32_MCO1SEL_HSE_CK
+#define STM32_MCO1PRE_VALUE 4
+#define STM32_MCO2SEL STM32_MCO2SEL_SYS_CK
+#define STM32_MCO2PRE_VALUE 4
+#define STM32_TIMPRE_ENABLE TRUE
+#define STM32_HRTIMSEL 0
+#define STM32_STOPKERWUCK 0
+#define STM32_STOPWUCK 0
+#define STM32_RTCPRE_VALUE 8
+#define STM32_CKPERSEL STM32_CKPERSEL_HSE_CK
+#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL1_Q_CK
+#define STM32_QSPISEL STM32_QSPISEL_PLL2_R_CK
+#define STM32_FMCSEL STM32_FMCSEL_HCLK
+#define STM32_SWPSEL STM32_SWPSEL_PCLK1
+#define STM32_FDCANSEL STM32_FDCANSEL_PLL1_Q_CK
+#define STM32_DFSDM1SEL STM32_DFSDM1SEL_PCLK2
+#define STM32_SPDIFSEL STM32_SPDIFSEL_PLL1_Q_CK
+#define STM32_SPI45SEL STM32_SPI45SEL_PCLK2
+#define STM32_SPI123SEL STM32_SPI123SEL_PLL1_Q_CK
+#define STM32_SAI23SEL STM32_SAI23SEL_PLL1_Q_CK
+#define STM32_SAI1SEL STM32_SAI1SEL_PLL1_Q_CK
+#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
+#define STM32_CECSEL STM32_CECSEL_DISABLE
+#define STM32_USBSEL STM32_USBSEL_PLL3_Q_CK
+#define STM32_I2C123SEL STM32_I2C123SEL_PLL3_R_CK
+#define STM32_RNGSEL STM32_RNGSEL_HSI48_CK
+#define STM32_USART16SEL STM32_USART16SEL_PCLK2
+#define STM32_USART234578SEL STM32_USART234578SEL_PCLK1
+#define STM32_SPI6SEL STM32_SPI6SEL_PCLK4
+#define STM32_SAI4BSEL STM32_SAI4BSEL_PLL1_Q_CK
+#define STM32_SAI4ASEL STM32_SAI4ASEL_PLL1_Q_CK
+#define STM32_ADCSEL STM32_ADCSEL_PLL3_R_CK
+#define STM32_LPTIM345SEL STM32_LPTIM345SEL_PCLK4
+#define STM32_LPTIM2SEL STM32_LPTIM2SEL_PCLK4
+#define STM32_I2C4SEL STM32_I2C4SEL_PLL3_R_CK
+#define STM32_LPUART1SEL STM32_LPUART1SEL_PCLK4
+
+/*
+ * IRQ system settings.
+ */
+#define STM32_IRQ_EXTI0_PRIORITY 6
+#define STM32_IRQ_EXTI1_PRIORITY 6
+#define STM32_IRQ_EXTI2_PRIORITY 6
+#define STM32_IRQ_EXTI3_PRIORITY 6
+#define STM32_IRQ_EXTI4_PRIORITY 6
+#define STM32_IRQ_EXTI5_9_PRIORITY 6
+#define STM32_IRQ_EXTI10_15_PRIORITY 6
+#define STM32_IRQ_EXTI16_PRIORITY 6
+#define STM32_IRQ_EXTI17_PRIORITY 15 //#TODO: is this correct?
+#define STM32_IRQ_EXTI18_PRIORITY 6
+#define STM32_IRQ_EXTI19_PRIORITY 6
+#define STM32_IRQ_EXTI20_21_PRIORITY 6
+
+#define STM32_IRQ_FDCAN1_PRIORITY 10
+#define STM32_IRQ_FDCAN2_PRIORITY 10
+
+#define STM32_IRQ_MDMA_PRIORITY 9
+
+#define STM32_IRQ_QUADSPI1_PRIORITY 10
+
+#define STM32_IRQ_SDMMC1_PRIORITY 9
+#define STM32_IRQ_SDMMC2_PRIORITY 9
+
+#define STM32_IRQ_TIM1_UP_PRIORITY 7
+#define STM32_IRQ_TIM1_CC_PRIORITY 7
+#define STM32_IRQ_TIM2_PRIORITY 7
+#define STM32_IRQ_TIM3_PRIORITY 7
+#define STM32_IRQ_TIM4_PRIORITY 7
+#define STM32_IRQ_TIM5_PRIORITY 7
+#define STM32_IRQ_TIM6_PRIORITY 7
+#define STM32_IRQ_TIM7_PRIORITY 7
+#define STM32_IRQ_TIM8_BRK_TIM12_PRIORITY 7
+#define STM32_IRQ_TIM8_UP_TIM13_PRIORITY 7
+#define STM32_IRQ_TIM8_TRGCO_TIM14_PRIORITY 7
+#define STM32_IRQ_TIM8_CC_PRIORITY 7
+#define STM32_IRQ_TIM15_PRIORITY 7
+#define STM32_IRQ_TIM16_PRIORITY 7
+#define STM32_IRQ_TIM17_PRIORITY 7
+
+#define STM32_IRQ_USART1_PRIORITY 12
+#define STM32_IRQ_USART2_PRIORITY 12
+#define STM32_IRQ_USART3_PRIORITY 12
+#define STM32_IRQ_UART4_PRIORITY 12
+#define STM32_IRQ_UART5_PRIORITY 12
+#define STM32_IRQ_USART6_PRIORITY 12
+#define STM32_IRQ_UART7_PRIORITY 12
+#define STM32_IRQ_UART8_PRIORITY 12
+#define STM32_IRQ_LPUART1_PRIORITY 12
+
+/*
+ * ADC driver system settings.
+ */
+#define STM32_ADC_DUAL_MODE FALSE
+#define STM32_ADC_SAMPLES_SIZE 16
+#define STM32_ADC_USE_ADC12 TRUE
+#define STM32_ADC_USE_ADC3 TRUE
+#define STM32_ADC_ADC12_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_ADC_ADC3_BDMA_STREAM 7
+#define STM32_ADC_ADC12_DMA_PRIORITY 2
+#define STM32_ADC_ADC3_DMA_PRIORITY 2
+#define STM32_ADC_ADC12_IRQ_PRIORITY 5
+#define STM32_ADC_ADC3_IRQ_PRIORITY 5
+#define STM32_ADC_ADC12_CLOCK_MODE ADC_CCR_CKMODE_ADCCK
+#define STM32_ADC_ADC3_CLOCK_MODE ADC_CCR_CKMODE_ADCCK
+
+/*
+ * CAN driver system settings.
+ */
+#if USE_CAN1
+#define STM32_CAN_USE_FDCAN1 TRUE
+#else
+#define STM32_CAN_USE_FDCAN1 FALSE
+#endif
+#if USE_CAN2
+#define STM32_CAN_USE_FDCAN2 TRUE
+#else
+#define STM32_CAN_USE_FDCAN2 FALSE
+#endif
+#define STM32_CAN_USE_FDCAN3 FALSE
+
+/*
+ * DAC driver system settings.
+ */
+#define STM32_DAC_DUAL_MODE FALSE
+#define STM32_DAC_USE_DAC1_CH1 FALSE
+#define STM32_DAC_USE_DAC1_CH2 FALSE
+#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
+#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
+#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+
+/*
+ * GPT driver system settings.
+ */
+#define STM32_GPT_USE_TIM1 FALSE
+#define STM32_GPT_USE_TIM2 FALSE
+#define STM32_GPT_USE_TIM3 FALSE
+#define STM32_GPT_USE_TIM4 FALSE
+#define STM32_GPT_USE_TIM5 FALSE
+#define STM32_GPT_USE_TIM6 FALSE
+#define STM32_GPT_USE_TIM7 FALSE
+#define STM32_GPT_USE_TIM8 FALSE
+#define STM32_GPT_USE_TIM12 FALSE
+#define STM32_GPT_USE_TIM13 FALSE
+#define STM32_GPT_USE_TIM14 FALSE
+#define STM32_GPT_USE_TIM15 FALSE
+#define STM32_GPT_USE_TIM16 FALSE
+#define STM32_GPT_USE_TIM17 FALSE
+
+/*
+ * I2C driver system settings.
+ */
+#if USE_I2C1
+#define STM32_I2C_USE_I2C1 TRUE
+#else
+#define STM32_I2C_USE_I2C1 FALSE
+#endif
+#if USE_I2C2
+#define STM32_I2C_USE_I2C2 TRUE
+#else
+#define STM32_I2C_USE_I2C2 FALSE
+#endif
+#if USE_I2C3
+#define STM32_I2C_USE_I2C3 TRUE
+#else
+#define STM32_I2C_USE_I2C3 FALSE
+#endif
+#if USE_I2C4
+#define STM32_I2C_USE_I2C4 TRUE
+#else
+#define STM32_I2C_USE_I2C4 FALSE
+#endif
+#define STM32_I2C_ISR_LIMIT 6
+#define STM32_I2C_BUSY_TIMEOUT 0
+#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_I2C_I2C4_RX_BDMA_STREAM 1
+#define STM32_I2C_I2C4_TX_BDMA_STREAM 2
+#define STM32_I2C_I2C1_IRQ_PRIORITY 5
+#define STM32_I2C_I2C2_IRQ_PRIORITY 5
+#define STM32_I2C_I2C3_IRQ_PRIORITY 5
+#define STM32_I2C_I2C4_IRQ_PRIORITY 5
+#define STM32_I2C_I2C1_DMA_PRIORITY 3
+#define STM32_I2C_I2C2_DMA_PRIORITY 3
+#define STM32_I2C_I2C3_DMA_PRIORITY 3
+#define STM32_I2C_I2C4_DMA_PRIORITY 3
+#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
+
+/*
+ * ICU driver system settings.
+ */
+#ifdef USE_PWM_INPUT1
+#define STM32_ICU_USE_TIM1 TRUE
+#else
+#define STM32_ICU_USE_TIM1 FALSE
+#endif
+#define STM32_ICU_USE_TIM2 FALSE
+#define STM32_ICU_USE_TIM3 FALSE
+#define STM32_ICU_USE_TIM4 FALSE
+#if RADIO_CONTROL_TYPE_PPM
+#define STM32_ICU_USE_TIM5 TRUE
+#else
+#define STM32_ICU_USE_TIM5 FALSE
+#endif
+#define STM32_ICU_USE_TIM8 FALSE
+#define STM32_ICU_USE_TIM12 FALSE
+#define STM32_ICU_USE_TIM13 FALSE
+#define STM32_ICU_USE_TIM14 FALSE
+#define STM32_ICU_USE_TIM15 FALSE
+#define STM32_ICU_USE_TIM16 FALSE
+#define STM32_ICU_USE_TIM17 FALSE
+
+/*
+ * MAC driver system settings.
+ */
+#define STM32_MAC_TRANSMIT_BUFFERS 2
+#define STM32_MAC_RECEIVE_BUFFERS 4
+#define STM32_MAC_BUFFERS_SIZE 1522
+#define STM32_MAC_PHY_TIMEOUT 100
+#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
+#define STM32_MAC_ETH1_IRQ_PRIORITY 13
+#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
+
+/*
+ * PWM driver system settings.
+ */
+#define STM32_PWM_USE_ADVANCED FALSE
+#define STM32_PWM_USE_TIM1 TRUE // LED tim
+#define STM32_PWM_USE_TIM2 FALSE
+#ifndef STM32_PWM_USE_TIM3
+#define STM32_PWM_USE_TIM3 TRUE // servo 1-2
+#endif
+#ifndef STM32_PWM_USE_TIM4
+#define STM32_PWM_USE_TIM4 TRUE // servo 7-8-9-10
+#endif
+#ifndef STM32_PWM_USE_TIM5
+#define STM32_PWM_USE_TIM5 TRUE // servo 3-4-5-6
+#endif
+#define STM32_PWM_USE_TIM8 FALSE
+#define STM32_PWM_USE_TIM9 FALSE
+#define STM32_PWM_USE_TIM10 FALSE
+#define STM32_PWM_USE_TIM11 FALSE
+#define STM32_PWM_USE_TIM12 FALSE
+#define STM32_PWM_USE_TIM13 FALSE
+#define STM32_PWM_USE_TIM14 FALSE
+#ifndef STM32_PWM_USE_TIM15
+#define STM32_PWM_USE_TIM15 FALSE // enable for servo 11-12
+#endif
+#define STM32_PWM_USE_TIM16 FALSE
+#define STM32_PWM_USE_TIM17 FALSE
+
+// TODO DMA UP for Dshot ?
+
+/*
+ * RTC driver system settings.
+ */
+#define STM32_RTC_PRESA_VALUE 32
+#define STM32_RTC_PRESS_VALUE 1024
+#define STM32_RTC_CR_INIT 0
+#define STM32_RTC_TAMPCR_INIT 0
+
+/*
+ * SDC driver system settings.
+ */
+#define STM32_SDC_USE_SDMMC1 TRUE
+#define STM32_SDC_USE_SDMMC2 FALSE
+#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
+#define STM32_SDC_SDMMC_WRITE_TIMEOUT 6000000
+#define STM32_SDC_SDMMC_READ_TIMEOUT 6000000
+#define STM32_SDC_SDMMC_CLOCK_DELAY 20
+#define STM32_SDC_SDMMC_PWRSAV TRUE
+#define STM32_SDC_FORCE_25MHZ TRUE
+
+/*
+ * SERIAL driver system settings.
+ */
+#if USE_UART1
+#define STM32_SERIAL_USE_USART1 TRUE
+#else
+#define STM32_SERIAL_USE_USART1 TRUE
+#endif
+#if USE_UART2
+#define STM32_SERIAL_USE_USART2 TRUE
+#else
+#define STM32_SERIAL_USE_USART2 FALSE
+#endif
+#if USE_UART3
+#define STM32_SERIAL_USE_USART3 TRUE
+#else
+#define STM32_SERIAL_USE_USART3 FALSE
+#endif
+#if USE_UART4
+#define STM32_SERIAL_USE_UART4 TRUE
+#else
+#define STM32_SERIAL_USE_UART4 FALSE
+#endif
+#if USE_UART5
+#define STM32_SERIAL_USE_UART5 TRUE
+#else
+#define STM32_SERIAL_USE_UART5 FALSE
+#endif
+#if USE_UART6
+#define STM32_SERIAL_USE_USART6 TRUE
+#else
+#define STM32_SERIAL_USE_USART6 TRUE
+#endif
+#if USE_UART7
+#define STM32_SERIAL_USE_UART7 TRUE
+#else
+#define STM32_SERIAL_USE_UART7 FALSE
+#endif
+#if USE_UART8
+#define STM32_SERIAL_USE_UART8 TRUE
+#else
+#define STM32_SERIAL_USE_UART8 FALSE
+#endif
+#define STM32_SERIAL_USE_LPUART1 FALSE
+
+/*
+ * SPI driver system settings.
+ */
+#if USE_SPI1
+#define STM32_SPI_USE_SPI1 TRUE
+#else
+#define STM32_SPI_USE_SPI1 FALSE
+#endif
+#if USE_SPI2
+#define STM32_SPI_USE_SPI2 TRUE
+#else
+#define STM32_SPI_USE_SPI2 FALSE
+#endif
+#if USE_SPI3
+#define STM32_SPI_USE_SPI3 TRUE
+#else
+#define STM32_SPI_USE_SPI3 FALSE
+#endif
+#if USE_SPI4
+#define STM32_SPI_USE_SPI4 TRUE
+#else
+#define STM32_SPI_USE_SPI4 FALSE
+#endif
+#define STM32_SPI_USE_SPI5 FALSE
+#define STM32_SPI_USE_SPI6 FALSE
+#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_SPI_SPI1_DMA_PRIORITY 1
+#define STM32_SPI_SPI2_DMA_PRIORITY 1
+#define STM32_SPI_SPI3_DMA_PRIORITY 1
+#define STM32_SPI_SPI4_DMA_PRIORITY 1
+#define STM32_SPI_SPI5_DMA_PRIORITY 1
+#define STM32_SPI_SPI6_DMA_PRIORITY 1
+#define STM32_SPI_SPI1_IRQ_PRIORITY 10
+#define STM32_SPI_SPI2_IRQ_PRIORITY 10
+#define STM32_SPI_SPI3_IRQ_PRIORITY 10
+#define STM32_SPI_SPI4_IRQ_PRIORITY 10
+#define STM32_SPI_SPI5_IRQ_PRIORITY 10
+#define STM32_SPI_SPI6_IRQ_PRIORITY 10
+#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
+
+/*
+ * ST driver system settings.
+ */
+#define STM32_ST_IRQ_PRIORITY 8
+#ifndef STM32_ST_USE_TIMER
+#define STM32_ST_USE_TIMER 5
+#endif
+
+/*
+ * TRNG driver system settings.
+ */
+#define STM32_TRNG_USE_RNG1 FALSE
+
+/*
+ * UART driver system settings.
+ */
+#define STM32_UART_USE_USART1 FALSE
+#define STM32_UART_USE_USART2 FALSE
+#define STM32_UART_USE_USART3 FALSE
+#define STM32_UART_USE_UART4 FALSE
+#define STM32_UART_USE_UART5 FALSE
+#define STM32_UART_USE_USART6 FALSE
+#define STM32_UART_USE_UART7 FALSE
+#define STM32_UART_USE_UART8 FALSE
+#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID_ANY
+#define STM32_UART_USART1_DMA_PRIORITY 1
+#define STM32_UART_USART2_DMA_PRIORITY 0
+#define STM32_UART_USART3_DMA_PRIORITY 0
+#define STM32_UART_UART4_DMA_PRIORITY 0
+#define STM32_UART_UART5_DMA_PRIORITY 0
+#define STM32_UART_USART6_DMA_PRIORITY 0
+#define STM32_UART_UART7_DMA_PRIORITY 0
+#define STM32_UART_UART8_DMA_PRIORITY 0
+#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
+
+/*
+ * USB driver system settings.
+ */
+#define STM32_USB_USE_OTG1 TRUE // FS, DFU_BOOT
+#define STM32_USB_USE_OTG2 FALSE // HS
+#define STM32_USB_OTG1_IRQ_PRIORITY 14
+#define STM32_USB_OTG2_IRQ_PRIORITY 14
+#define STM32_USB_OTG1_RX_FIFO_SIZE 512
+#define STM32_USB_OTG2_RX_FIFO_SIZE 512
+#define STM32_USB_HOST_WAKEUP_DURATION 2
+
+/*
+ * WDG driver system settings.
+ */
+#define STM32_WDG_USE_IWDG FALSE
+
+/*
+ * WSPI driver system settings.
+ */
+#define STM32_WSPI_USE_QUADSPI1 FALSE
+#define STM32_WSPI_QUADSPI1_PRESCALER_VALUE ((STM32_QSPICLK / HAL_QSPI1_CLK) - 1)
+#define STM32_WSPI_QUADSPI1_MDMA_CHANNEL STM32_MDMA_CHANNEL_ID_ANY
+#define STM32_WSPI_QUADSPI1_MDMA_PRIORITY 1
+#define STM32_WSPI_MDMA_ERROR_HOOK(wspip) osalSysHalt("MDMA failure")
+
+/*
+ sdlog message buffer and queue configuration
+ */
+#define SDLOG_QUEUE_BUCKETS 1024
+#define SDLOG_MAX_MESSAGE_LEN 300
+#define SDLOG_NUM_FILES 2
+#define SDLOG_ALL_BUFFERS_SIZE (SDLOG_NUM_FILES*16*1024)
+
+#endif /* MCUCONF_H */