diff --git a/sw/airborne/arch/lpc21/peripherals/ms2001_arch.h b/sw/airborne/arch/lpc21/peripherals/ms2001_arch.h
index 5e04b88317..f8ae16e180 100644
--- a/sw/airborne/arch/lpc21/peripherals/ms2001_arch.h
+++ b/sw/airborne/arch/lpc21/peripherals/ms2001_arch.h
@@ -22,64 +22,64 @@ extern volatile uint8_t ms2001_cur_axe;
 #define Ms2001Reset() SetBit(MS2001_RESET_IOCLR,MS2001_RESET_PIN)
 #define Ms2001Set()   SetBit(MS2001_RESET_IOSET,MS2001_RESET_PIN)
 
-#define Ms2001OnSpiIt() {						\
-    switch (ms2001_status) {						\
-    case MS2001_SENDING_REQ:						\
-      {									\
-    /* read dummy control byte reply */				\
-    uint8_t foo __attribute__ ((unused)) = SSPDR;			\
-    ms2001_status = MS2001_WAITING_EOC;				\
-    Ms2001Unselect();						\
-    SSP_ClearRti();							\
-    SSP_DisableRti();						\
-    SSP_Disable();							\
-      }									\
-      break;								\
-    case MS2001_READING_RES:						\
-      {									\
-    int16_t new_val;						\
-    new_val = SSPDR << 8;						\
-    new_val += SSPDR;						\
-    if (abs(new_val) < 2000)					\
-      ms2001_values[ms2001_cur_axe] = new_val;			\
-    Ms2001Unselect();						\
-    SSP_ClearRti();							\
-    SSP_DisableRti();						\
-    SSP_Disable();							\
-    ms2001_cur_axe++;						\
-    if (ms2001_cur_axe > 2) {					\
-      ms2001_cur_axe = 0;						\
-      ms2001_status = MS2001_DATA_AVAILABLE;			\
-    }								\
-    else								\
-      ms2001_status = MS2001_IDLE;					\
-      }									\
-      break;								\
-    }									\
+#define Ms2001OnSpiInt() {                                   \
+    switch (ms2001_status) {                                \
+    case MS2001_SENDING_REQ:                                \
+      {                                                     \
+        /* read dummy control byte reply */                 \
+        uint8_t foo __attribute__ ((unused)) = SSPDR;       \
+        ms2001_status = MS2001_WAITING_EOC;                 \
+        Ms2001Unselect();                                   \
+        SSP_ClearRti();                                     \
+        SSP_DisableRti();                                   \
+        SSP_Disable();                                      \
+      }                                                     \
+      break;                                                \
+    case MS2001_READING_RES:                                \
+      {                                                     \
+        int16_t new_val;                                    \
+        new_val = SSPDR << 8;                               \
+        new_val += SSPDR;                                   \
+        if (abs(new_val) < 2000)                            \
+          ms2001_values[ms2001_cur_axe] = new_val;			\
+        Ms2001Unselect();                                   \
+        SSP_ClearRti();                                     \
+        SSP_DisableRti();                                   \
+        SSP_Disable();                                      \
+        ms2001_cur_axe++;                                   \
+        if (ms2001_cur_axe > 2) {                           \
+          ms2001_cur_axe = 0;                               \
+          ms2001_status = MS2001_DATA_AVAILABLE;			\
+        }                                                   \
+        else                                                \
+          ms2001_status = MS2001_IDLE;                      \
+      }                                                     \
+      break;                                                \
+    }                                                       \
   }
 
 
-#define Ms2001SendReq() {						\
-    Ms2001Select();							\
+#define Ms2001SendReq() {                               \
+    Ms2001Select();                                     \
     ms2001_status = MS2001_SENDING_REQ;					\
-    Ms2001Set();							\
-    SSP_ClearRti();							\
-    SSP_EnableRti();							\
-    Ms2001Reset();							\
-    uint8_t control_byte = (ms2001_cur_axe+1) << 0 |			\
-                            MS2001_DIVISOR << 4;			\
-    SSP_Send(control_byte);						\
-    SSP_Enable();							\
+    Ms2001Set();                                        \
+    SSP_ClearRti();                                     \
+    SSP_EnableRti();                                    \
+    Ms2001Reset();                                      \
+    uint8_t control_byte = (ms2001_cur_axe+1) << 0 |    \
+      MS2001_DIVISOR << 4;                              \
+    SSP_Send(control_byte);                             \
+    SSP_Enable();                                       \
   }
 
 #define Ms2001ReadRes() {						\
-    ms2001_status = MS2001_READING_RES;					\
-    Ms2001Select();							\
-    /* trigger 2 bytes read */						\
-    SSP_Send(0);							\
-    SSP_Send(0);							\
-    SSP_Enable();							\
-    SSP_ClearRti();							\
+    ms2001_status = MS2001_READING_RES;         \
+    Ms2001Select();                             \
+    /* trigger 2 bytes read */                  \
+    SSP_Send(0);                                \
+    SSP_Send(0);                                \
+    SSP_Enable();                               \
+    SSP_ClearRti();                             \
     SSP_EnableRti();							\
   }
 
diff --git a/sw/airborne/arch/lpc21/subsystems/imu/imu_b2_arch.c b/sw/airborne/arch/lpc21/subsystems/imu/imu_b2_arch.c
index 858581dca1..057babd73c 100644
--- a/sw/airborne/arch/lpc21/subsystems/imu/imu_b2_arch.c
+++ b/sw/airborne/arch/lpc21/subsystems/imu/imu_b2_arch.c
@@ -135,7 +135,7 @@ static void SSP_ISR(void) {
      imu_ssp_status = IMU_SSP_STA_IDLE;
    break;
  case IMU_SSP_STA_BUSY_MS2100:
-   Ms2001OnSpiIt();
+   Ms2001OnSpiInt();
    imu_ssp_status = IMU_SSP_STA_IDLE;
    break;
  default:
@@ -175,7 +175,7 @@ static void SSP_ISR(void) {
   break;
 #if defined IMU_B2_MAG_TYPE && IMU_B2_MAG_TYPE == IMU_B2_MAG_MS2001
  case IMU_SSP_STA_BUSY_MS2100:
-   Ms2001OnSpiIt();
+   Ms2001OnSpiInt();
    if (ms2001_status == MS2001_IDLE) {
     Ms2001SendReq();
     imu_ssp_status = IMU_SSP_STA_BUSY_MS2100;