diff --git a/conf/firmwares/rotorcraft.makefile b/conf/firmwares/rotorcraft.makefile
index 33698e9d82..a1d843231e 100644
--- a/conf/firmwares/rotorcraft.makefile
+++ b/conf/firmwares/rotorcraft.makefile
@@ -150,7 +150,7 @@ else ifeq ($(BOARD), lisa_m)
 # defaults to i2c baro bmp085 on the board
 LISA_M_BARO ?= BARO_BOARD_BMP085
   ifeq ($(LISA_M_BARO), BARO_MS5611_SPI)
-    include $(CFG_SHARED)/spi.makefile
+    include $(CFG_SHARED)/spi_master.makefile
     ap.CFLAGS += -DUSE_SPI2 -DUSE_SPI_SLAVE3
     ap.srcs += $(SRC_BOARD)/baro_ms5611_spi.c
   else ifeq ($(LISA_M_BARO), BARO_MS5611_I2C)
@@ -167,7 +167,7 @@ else ifeq ($(BOARD), lia)
 # fixme, reuse the baro drivers in lisa_m dir
 LIA_BARO ?= BARO_MS5611_SPI
   ifeq ($(LIA_BARO), BARO_MS5611_SPI)
-    include $(CFG_SHARED)/spi.makefile
+    include $(CFG_SHARED)/spi_master.makefile
     ap.CFLAGS += -DUSE_SPI2 -DUSE_SPI_SLAVE3
     ap.srcs += boards/lisa_m/baro_ms5611_spi.c
   else ifeq ($(LIA_BARO), BARO_MS5611_I2C)
@@ -178,7 +178,7 @@ LIA_BARO ?= BARO_MS5611_SPI
 
 # navgo baro
 else ifeq ($(BOARD), navgo)
-include $(CFG_SHARED)/spi.makefile
+include $(CFG_SHARED)/spi_master.makefile
 ap.CFLAGS += -DUSE_SPI_SLAVE0
 ap.CFLAGS += -DUSE_SPI1
 ap.srcs += peripherals/mcp355x.c
diff --git a/conf/firmwares/subsystems/fixedwing/intermcu_spi.makefile b/conf/firmwares/subsystems/fixedwing/intermcu_spi.makefile
index 2387863ec2..c44b38f0b8 100644
--- a/conf/firmwares/subsystems/fixedwing/intermcu_spi.makefile
+++ b/conf/firmwares/subsystems/fixedwing/intermcu_spi.makefile
@@ -10,9 +10,9 @@ ifeq ($(INTER_MCU_SLAVE),)
 INTER_MCU_SLAVE = SLAVE0
 endif
 
-fbw.CFLAGS  += -DMCU_SPI_LINK -DUSE_$(INTER_MCU_SPI)_SLAVE -DSPI_SLAVE
+fbw.CFLAGS  += -DMCU_SPI_LINK -DUSE_$(INTER_MCU_SPI)_SLAVE -DSPI_SLAVE -DUSE_SPI
 fbw.srcs    += $(SRC_FIXEDWING)/link_mcu_spi.c mcu_periph/spi.c $(SRC_ARCH)/mcu_periph/spi_arch.c
 ap_srcs     += $(SRC_FIRMWARE)/fbw_downlink.c
-ap.CFLAGS   += -DMCU_SPI_LINK -DUSE_$(INTER_MCU_SPI) -DSPI_MASTER -DUSE_SPI_$(INTER_MCU_SLAVE)
+ap.CFLAGS   += -DMCU_SPI_LINK -DUSE_$(INTER_MCU_SPI) -DSPI_MASTER -DUSE_SPI_$(INTER_MCU_SLAVE) -DUSE_SPI
 ap.srcs     += $(SRC_FIXEDWING)/link_mcu_spi.c mcu_periph/spi.c $(SRC_ARCH)/mcu_periph/spi_arch.c
 SEPARATE_FBW    = 1
diff --git a/conf/firmwares/subsystems/shared/imu_aspirin_common.makefile b/conf/firmwares/subsystems/shared/imu_aspirin_common.makefile
index 9b7746ca13..7fa9186de7 100644
--- a/conf/firmwares/subsystems/shared/imu_aspirin_common.makefile
+++ b/conf/firmwares/subsystems/shared/imu_aspirin_common.makefile
@@ -27,9 +27,7 @@ IMU_ASPIRIN_SRCS   += $(SRC_SUBSYSTEMS)/imu/imu_aspirin.c
 #IMU_ASPIRIN_SRCS   += $(SRC_ARCH)/subsystems/imu/imu_aspirin_arch.c
 IMU_ASPIRIN_CFLAGS += -DASPIRIN_ARCH_INDEP
 
-IMU_ASPIRIN_SRCS   += mcu_periph/spi.c $(SRC_ARCH)/mcu_periph/spi_arch.c
-
-IMU_ASPIRIN_CFLAGS += -DUSE_SPI -DSPI_MASTER
+include $(CFG_SHARED)/spi_master.makefile
 
 # for fixedwing firmware and ap only
 ifeq ($(TARGET), ap)
diff --git a/conf/firmwares/subsystems/shared/imu_aspirin_v2.1.makefile b/conf/firmwares/subsystems/shared/imu_aspirin_v2.1.makefile
index 810271975b..446b84af59 100644
--- a/conf/firmwares/subsystems/shared/imu_aspirin_v2.1.makefile
+++ b/conf/firmwares/subsystems/shared/imu_aspirin_v2.1.makefile
@@ -46,7 +46,7 @@ IMU_ASPIRIN_CFLAGS += -DIMU_TYPE_H=\"imu/imu_aspirin2.h\"
 IMU_ASPIRIN_SRCS    = $(SRC_SUBSYSTEMS)/imu.c             \
                       $(SRC_SUBSYSTEMS)/imu/imu_aspirin2.c
 
-include $(CFG_SHARED)/spi.makefile
+include $(CFG_SHARED)/spi_master.makefile
 
 ifeq ($(ARCH), lpc21)
 IMU_ASPIRIN_CFLAGS += -DUSE_SPI1
diff --git a/conf/firmwares/subsystems/shared/imu_aspirin_v2.2.makefile b/conf/firmwares/subsystems/shared/imu_aspirin_v2.2.makefile
index f36ee75375..8dfb93613a 100644
--- a/conf/firmwares/subsystems/shared/imu_aspirin_v2.2.makefile
+++ b/conf/firmwares/subsystems/shared/imu_aspirin_v2.2.makefile
@@ -46,7 +46,7 @@ IMU_ASPIRIN_CFLAGS += -DIMU_TYPE_H=\"imu/imu_aspirin2.h\"
 IMU_ASPIRIN_SRCS    = $(SRC_SUBSYSTEMS)/imu.c             \
                       $(SRC_SUBSYSTEMS)/imu/imu_aspirin2.c
 
-include $(CFG_SHARED)/spi.makefile
+include $(CFG_SHARED)/spi_master.makefile
 
 ifeq ($(ARCH), lpc21)
 IMU_ASPIRIN_CFLAGS += -DUSE_SPI1
diff --git a/conf/firmwares/subsystems/shared/imu_b2_common.makefile b/conf/firmwares/subsystems/shared/imu_b2_common.makefile
index 8f11d64793..9e94416002 100644
--- a/conf/firmwares/subsystems/shared/imu_b2_common.makefile
+++ b/conf/firmwares/subsystems/shared/imu_b2_common.makefile
@@ -45,7 +45,7 @@ imu_srcs += $(SRC_SUBSYSTEMS)/imu/imu_b2.c
 imu_srcs += peripherals/max1168.c
 imu_srcs += $(SRC_ARCH)/peripherals/max1168_arch.c
 
-include $(CFG_SHARED)/spi.makefile
+include $(CFG_SHARED)/spi_master.makefile
 
 ifeq ($(ARCH), lpc21)
 imu_CFLAGS += -DUSE_SPI_SLAVE0
diff --git a/conf/firmwares/subsystems/shared/spi.makefile b/conf/firmwares/subsystems/shared/spi.makefile
deleted file mode 100644
index 55caffce3f..0000000000
--- a/conf/firmwares/subsystems/shared/spi.makefile
+++ /dev/null
@@ -1,13 +0,0 @@
-# Hey Emacs, this is a -*- makefile -*-
-
-ifndef SPI_INCLUDED
-
-SPI_INCLUDED = 1
-
-#generic spi driver
-$(TARGET).CFLAGS += -DUSE_SPI -DSPI_MASTER
-
-ap.srcs += mcu_periph/spi.c $(SRC_ARCH)/mcu_periph/spi_arch.c
-sim.srcs += mcu_periph/spi.c $(SRC_ARCH)/mcu_periph/spi_arch.c
-
-endif
diff --git a/conf/firmwares/subsystems/shared/spi_master.makefile b/conf/firmwares/subsystems/shared/spi_master.makefile
new file mode 100644
index 0000000000..3dea6f2fbb
--- /dev/null
+++ b/conf/firmwares/subsystems/shared/spi_master.makefile
@@ -0,0 +1,14 @@
+# Hey Emacs, this is a -*- makefile -*-
+
+ifndef SPI_INCLUDED
+
+SPI_INCLUDED = 1
+
+#generic spi master driver
+SPI_CFLAGS = -DUSE_SPI -DSPI_MASTER
+SPI_SRCS = mcu_periph/spi.c $(SRC_ARCH)/mcu_periph/spi_arch.c
+
+ap.CFLAGS += $(SPI_CFLAGS)
+ap.srcs += $(SPI_SRCS)
+
+endif
diff --git a/sw/airborne/arch/stm32/mcu_periph/spi_arch.c b/sw/airborne/arch/stm32/mcu_periph/spi_arch.c
index 75ccdfed7d..5671ffb2bf 100644
--- a/sw/airborne/arch/stm32/mcu_periph/spi_arch.c
+++ b/sw/airborne/arch/stm32/mcu_periph/spi_arch.c
@@ -27,19 +27,6 @@
  * Handling of SPI hardware for STM32.
  * SPI Master code.
  *
- * This file manages the SPI implementation how it appears to the chip.
- * The public "API" that is used across the modules has different ideas about the
- * numbers used in the spi structures (spi_periph).
- *
- * This means that from the outside, a spi_periph 2 may be mapped to SPI2, even though it's
- * not the primary spi peripheral to use. Alternatively, it may as well be spi0 (mcu_periph/spi.c)
- * which connects to the IMU (SPI2), instead of spi2.
- *
- * See the "spix_arch_init()" functions to see where the mapping occurs.
- *
- * This does require modifications in the makefiles, because the correct arch_init needs to be called
- * for the selection of aspirin v2.1 for example.
- *
  * When a transaction is submitted:
  * - The transaction is added to the queue if there is space, otherwise it returns false
  * - The pending state is set
@@ -100,7 +87,7 @@ struct spi_periph_dma {
 };
 
 #if USE_SPI0
-static struct spi_periph_dma spi0_dma;
+#error "The STM32 doesn't have SPI0"
 #endif
 #if USE_SPI1
 static struct spi_periph_dma spi1_dma;
@@ -108,18 +95,10 @@ static struct spi_periph_dma spi1_dma;
 #if USE_SPI2
 static struct spi_periph_dma spi2_dma;
 #endif
+#if USE_SPI3
+static struct spi_periph_dma spi3_dma;
+#endif
 
-// SPI2 Slave Selection
-
-// This mapping is related to the mapping of spi(x) structures in the modules and not
-// necessarily to the identifiers as they appear to the processor.
-// The IMU on Lisam2 for example is assigned to the SPI2 bus, but we continue to use
-// the mapping to spi(x) structures as in modules here. The actual mapping of pins
-// occurs in "arch_init".
-// What this means is that we're effectively 'locking':
-// SPI2 to spi2
-// SPI1 to spi1
-// SPI3 to spi0
 
 #define SPI_SELECT_SLAVE0_PERIPH RCC_APB2ENR_IOPAEN
 #define SPI_SELECT_SLAVE0_PORT GPIOA
@@ -233,79 +212,33 @@ static void spi_arch_int_disable( struct spi_periph *spi ) {
  *  These functions map the publically available "spi" structures to
  *  specific pins on this processor
  */
-#if USE_SPI0
-void spi0_arch_init(void) {
-
-  // Enable SPI3 Periph and gpio clocks -------------------------------------------------
-  rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_SPI3EN);
-
-  // Configure GPIOs: SCK, MISO and MOSI  --------------------------------
-  gpio_set_mode(GPIO_BANK_SPI3_SCK, GPIO_MODE_OUTPUT_50_MHZ,
-            GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI3_SCK |
-                                            GPIO_SPI3_MOSI);
-
-  gpio_set_mode(GPIO_BANK_SPI3_MISO, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT,
-          GPIO_SPI3_MISO);
-
-  // reset SPI
-  spi_reset(SPI3);
-
-  // Disable SPI peripheral
-  spi_disable(SPI3);
-
-  // Initialize the slave select pins
-  // done from mcu_init, is it really necessary to do that here?
-  //spi_init_slaves();
-
-  // rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_OTGFSEN);
-
-  spi0_dma.config = (SPIDss8bit << 6) | (SPIDiv64 << 3) | (SPIMSBFirst << 2) | (SPICphaEdge2 << 1) | (SPICpolIdleHigh);
-
-  // Force SPI mode over I2S.
-  SPI3_I2SCFGR = 0;
-
-  // configure master SPI.
-  spi_init_master(SPI3, SPI_CR1_BAUDRATE_FPCLK_DIV_64, SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE,
-                  SPI_CR1_CPHA_CLK_TRANSITION_2, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
-
-  /*
-   * Set NSS management to software.
-   *
-   * Note:
-   * Setting nss high is very important, even if we are controlling the GPIO
-   * ourselves this bit needs to be at least set to 1, otherwise the spi
-   * peripheral will not send any data out.
-   */
-  spi_enable_software_slave_management(SPI3);
-  spi_set_nss_high(SPI3);
-
-  // Enable SPI_3 DMA clock ---------------------------------------------------
-  rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA2EN);
-
-  // Enable SPI3 periph.
-  spi_enable(SPI3);
-
-  spi0.init_struct = &spi0_dma;
-  spi0_dma.spi = SPI3;
-  spi0_dma.spidr = (u32)&SPI3_DR;
-  spi0_dma.dma = DMA2;
-  spi0_dma.rx_chan = DMA_CHANNEL1;
-  spi0_dma.tx_chan = DMA_CHANNEL2;
-  spi0_dma.rx_nvic_irq = NVIC_DMA2_CHANNEL1_IRQ;
-  spi0_dma.tx_nvic_irq = NVIC_DMA2_CHANNEL2_IRQ;
-  spi0_dma.other_dma_finished = 0;
-
-  spi0.trans_insert_idx = 0;
-  spi0.trans_extract_idx = 0;
-  spi0.status = SPIIdle;
-
-  spi_arch_int_enable( &spi0 );
-}
-#endif
-
 #if USE_SPI1
 void spi1_arch_init(void) {
 
+  // set the default configuration
+  spi1_dma.spi = SPI1;
+  spi1_dma.spidr = (u32)&SPI1_DR;
+  spi1_dma.dma = DMA1;
+  spi1_dma.rx_chan = DMA_CHANNEL2;
+  spi1_dma.tx_chan = DMA_CHANNEL3;
+  spi1_dma.rx_nvic_irq = NVIC_DMA1_CHANNEL2_IRQ;
+  spi1_dma.tx_nvic_irq = NVIC_DMA1_CHANNEL3_IRQ;
+
+  // set the default configuration
+  spi1_dma.other_dma_finished = 0;
+  spi1_dma.cdiv = SPI_CR1_BAUDRATE_FPCLK_DIV_64;
+  spi1_dma.cpol = SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE;
+  spi1_dma.cpha = SPI_CR1_CPHA_CLK_TRANSITION_2;
+  spi1_dma.dss = SPI_CR1_DFF_8BIT;
+  spi1_dma.bo = SPI_CR1_MSBFIRST;
+  spi1_dma.config = (SPIDss8bit << 6) | (SPIDiv64 << 3) | (SPIMSBFirst << 2) | (SPICphaEdge2 << 1) | (SPICpolIdleHigh);
+
+  // set init struct, indices and status
+  spi1.init_struct = &spi1_dma;
+  spi1.trans_insert_idx = 0;
+  spi1.trans_extract_idx = 0;
+  spi1.status = SPIIdle;
+
   // Enable SPI1 Periph and gpio clocks -------------------------------------------------
   rcc_peripheral_enable_clock(&RCC_APB2ENR, RCC_APB2ENR_SPI1EN);
 
@@ -332,12 +265,8 @@ void spi1_arch_init(void) {
   // Force SPI mode over I2S.
   SPI1_I2SCFGR = 0;
 
-  spi1_dma.config = (SPIDss8bit << 6) | (SPIDiv64 << 3) | (SPIMSBFirst << 2) | (SPICphaEdge2 << 1) | (SPICpolIdleHigh);
-
   // configure master SPI.
-  spi_init_master(SPI1, SPI_CR1_BAUDRATE_FPCLK_DIV_64, SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE,
-                  SPI_CR1_CPHA_CLK_TRANSITION_2, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
-
+  spi_init_master(SPI1, spi1_dma.cdiv, spi1_dma.cpol, spi1_dma.cpha, spi1_dma.dss, spi1_dma.bo);
   /*
    * Set NSS management to software.
    *
@@ -355,20 +284,6 @@ void spi1_arch_init(void) {
   // Enable SPI1 periph.
   spi_enable(SPI1);
 
-  spi1.init_struct = &spi1_dma;
-  spi1_dma.spi = SPI1;
-  spi1_dma.spidr = (u32)&SPI1_DR;
-  spi1_dma.dma = DMA1;
-  spi1_dma.rx_chan = DMA_CHANNEL2;
-  spi1_dma.tx_chan = DMA_CHANNEL3;
-  spi1_dma.rx_nvic_irq = NVIC_DMA1_CHANNEL2_IRQ;
-  spi1_dma.tx_nvic_irq = NVIC_DMA1_CHANNEL3_IRQ;
-  spi1_dma.other_dma_finished = 0;
-
-  spi1.trans_insert_idx = 0;
-  spi1.trans_extract_idx = 0;
-  spi1.status = SPIIdle;
-
   spi_arch_int_enable( &spi1 );
 }
 #endif
@@ -376,6 +291,30 @@ void spi1_arch_init(void) {
 #if USE_SPI2
 void spi2_arch_init(void) {
 
+  // set the default configuration
+  spi2_dma.spi = SPI2;
+  spi2_dma.spidr = (u32)&SPI2_DR;
+  spi2_dma.dma = DMA1;
+  spi2_dma.rx_chan = DMA_CHANNEL4;
+  spi2_dma.tx_chan = DMA_CHANNEL5;
+  spi2_dma.rx_nvic_irq = NVIC_DMA1_CHANNEL4_IRQ;
+  spi2_dma.tx_nvic_irq = NVIC_DMA1_CHANNEL5_IRQ;
+
+  spi2_dma.other_dma_finished = 0;
+  spi2_dma.cdiv = SPI_CR1_BAUDRATE_FPCLK_DIV_64;
+  spi2_dma.cpol = SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE;
+  spi2_dma.cpha = SPI_CR1_CPHA_CLK_TRANSITION_2;
+  spi2_dma.dss = SPI_CR1_DFF_8BIT;
+  spi2_dma.bo = SPI_CR1_MSBFIRST;
+  spi2_dma.config = (SPIDss8bit << 6) | (SPIDiv64 << 3) | (SPIMSBFirst << 2) | (SPICphaEdge2 << 1) | (SPICpolIdleHigh);
+
+  // set init struct, indices and status
+  spi2.init_struct = &spi2_dma;
+  spi2.trans_insert_idx = 0;
+  spi2.trans_extract_idx = 0;
+  spi2.status = SPIIdle;
+
+
   // Enable SPI2 Periph and gpio clocks -------------------------------------------------
   rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_SPI2EN);
 
@@ -402,11 +341,8 @@ void spi2_arch_init(void) {
   // Force SPI mode over I2S.
   SPI2_I2SCFGR = 0;
 
-  spi2_dma.config = (SPIDss8bit << 6) | (SPIDiv64 << 3) | (SPIMSBFirst << 2) | (SPICphaEdge2 << 1) | (SPICpolIdleHigh);
-
   // configure master SPI.
-  spi_init_master(SPI2, SPI_CR1_BAUDRATE_FPCLK_DIV_64, SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE,
-                  SPI_CR1_CPHA_CLK_TRANSITION_2, SPI_CR1_DFF_8BIT, SPI_CR1_MSBFIRST);
+  spi_init_master(SPI2, spi2_dma.cdiv, spi2_dma.cpol, spi2_dma.cpha, spi2_dma.dss, spi2_dma.bo);
 
   /*
    * Set NSS management to software.
@@ -425,24 +361,87 @@ void spi2_arch_init(void) {
   // Enable SPI2 periph.
   spi_enable(SPI2);
 
-  spi2.init_struct = &spi2_dma;
-  spi2_dma.spi = SPI2;
-  spi2_dma.spidr = (u32)&SPI2_DR;
-  spi2_dma.dma = DMA1;
-  spi2_dma.rx_chan = DMA_CHANNEL4;
-  spi2_dma.tx_chan = DMA_CHANNEL5;
-  spi2_dma.rx_nvic_irq = NVIC_DMA1_CHANNEL4_IRQ;
-  spi2_dma.tx_nvic_irq = NVIC_DMA1_CHANNEL5_IRQ;
-  spi2_dma.other_dma_finished = 0;
-
-  spi2.trans_insert_idx = 0;
-  spi2.trans_extract_idx = 0;
-  spi2.status = SPIIdle;
-
   spi_arch_int_enable( &spi2 );
 }
 #endif
 
+#if USE_SPI3
+void spi3_arch_init(void) {
+
+  // set the default configuration
+  spi3_dma.spi = SPI3;
+  spi3_dma.spidr = (u32)&SPI3_DR;
+  spi3_dma.dma = DMA2;
+  spi3_dma.rx_chan = DMA_CHANNEL1;
+  spi3_dma.tx_chan = DMA_CHANNEL2;
+  spi3_dma.rx_nvic_irq = NVIC_DMA2_CHANNEL1_IRQ;
+  spi3_dma.tx_nvic_irq = NVIC_DMA2_CHANNEL2_IRQ;
+
+  spi3_dma.other_dma_finished = 0;
+  spi3_dma.cdiv = SPI_CR1_BAUDRATE_FPCLK_DIV_64;
+  spi3_dma.cpol = SPI_CR1_CPOL_CLK_TO_1_WHEN_IDLE;
+  spi3_dma.cpha = SPI_CR1_CPHA_CLK_TRANSITION_2;
+  spi3_dma.dss = SPI_CR1_DFF_8BIT;
+  spi3_dma.bo = SPI_CR1_MSBFIRST;
+  spi3_dma.config = (SPIDss8bit << 6) | (SPIDiv64 << 3) | (SPIMSBFirst << 2) | (SPICphaEdge2 << 1) | (SPICpolIdleHigh);
+
+  // set init struct, indices and status
+  spi3.init_struct = &spi3_dma;
+  spi3.trans_insert_idx = 0;
+  spi3.trans_extract_idx = 0;
+  spi3.status = SPIIdle;
+
+
+  // Enable SPI3 Periph and gpio clocks -------------------------------------------------
+  rcc_peripheral_enable_clock(&RCC_APB1ENR, RCC_APB1ENR_SPI3EN);
+
+  // Configure GPIOs: SCK, MISO and MOSI  --------------------------------
+  gpio_set_mode(GPIO_BANK_SPI3_SCK, GPIO_MODE_OUTPUT_50_MHZ,
+                GPIO_CNF_OUTPUT_ALTFN_PUSHPULL, GPIO_SPI3_SCK |
+                GPIO_SPI3_MOSI);
+
+  gpio_set_mode(GPIO_BANK_SPI3_MISO, GPIO_MODE_INPUT, GPIO_CNF_INPUT_FLOAT,
+                GPIO_SPI3_MISO);
+
+  // reset SPI
+  spi_reset(SPI3);
+
+  // Disable SPI peripheral
+  spi_disable(SPI3);
+
+  // Initialize the slave select pins
+  // done from mcu_init, is it really necessary to do that here?
+  //spi_init_slaves();
+
+  // rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_OTGFSEN);
+
+  // Force SPI mode over I2S.
+  SPI3_I2SCFGR = 0;
+
+  // configure master SPI.
+  spi_init_master(SPI3, spi3_dma.cdiv, spi3_dma.cpol, spi3_dma.cpha, spi3_dma.dss, spi3_dma.bo);
+
+  /*
+   * Set NSS management to software.
+   *
+   * Note:
+   * Setting nss high is very important, even if we are controlling the GPIO
+   * ourselves this bit needs to be at least set to 1, otherwise the spi
+   * peripheral will not send any data out.
+   */
+  spi_enable_software_slave_management(SPI3);
+  spi_set_nss_high(SPI3);
+
+  // Enable SPI_3 DMA clock ---------------------------------------------------
+  rcc_peripheral_enable_clock(&RCC_AHBENR, RCC_AHBENR_DMA2EN);
+
+  // Enable SPI3 periph.
+  spi_enable(SPI3);
+
+  spi_arch_int_enable( &spi3 );
+}
+#endif
+
 static void spi_rw(struct spi_periph* p, struct spi_transaction  * _trans)
 {
   struct spi_periph_dma *dma;
@@ -808,7 +807,7 @@ void dma1_channel5_isr(void)
 
 #endif
 
-#if USE_SPI0
+#if USE_SPI3
 /// receive transferred over DMA
 void dma2_channel1_isr(void)
 {
diff --git a/sw/airborne/mcu.c b/sw/airborne/mcu.c
index 7c53ff9641..043366504c 100644
--- a/sw/airborne/mcu.c
+++ b/sw/airborne/mcu.c
@@ -49,7 +49,7 @@
 #ifdef USE_USB_SERIAL
 #include "mcu_periph/usb_serial.h"
 #endif
-#if USE_SPI0 || USE_SPI1 || USE_SPI2 || USE_SPI0_SLAVE || USE_SPI1_SLAVE || USE_SPI2_SLAVE
+#if USE_SPI
 #include "mcu_periph/spi.h"
 #endif
 #ifdef USE_DAC
@@ -103,6 +103,10 @@ void mcu_init(void) {
 #ifdef USE_USB_SERIAL
   VCOM_init();
 #endif
+
+#if USE_SPI
+#if SPI_MASTER
+
 #if USE_SPI0
   spi0_init();
 #endif
@@ -112,9 +116,10 @@ void mcu_init(void) {
 #if USE_SPI2
   spi2_init();
 #endif
-#if USE_SPI0 || USE_SPI1 || USE_SPI2
   spi_init_slaves();
-#endif
+#endif // SPI_MASTER
+
+#if SPI_SLAVE
 #if USE_SPI0_SLAVE
   spi0_slave_init();
 #endif
@@ -124,6 +129,9 @@ void mcu_init(void) {
 #if USE_SPI2_SLAVE
   spi2_slave_init();
 #endif
+#endif // SPI_SLAVE
+#endif // USE_SPI
+
 #ifdef USE_DAC
   dac_init();
 #endif
diff --git a/sw/airborne/mcu_periph/spi.h b/sw/airborne/mcu_periph/spi.h
index e78bf419f7..dcb7d89ba5 100644
--- a/sw/airborne/mcu_periph/spi.h
+++ b/sw/airborne/mcu_periph/spi.h
@@ -194,7 +194,7 @@ extern void spi0_init(void);
  */
 extern void spi0_arch_init(void);
 
-#endif
+#endif // USE_SPI0
 
 #if USE_SPI1
 
@@ -206,7 +206,7 @@ extern void spi1_init(void);
  */
 extern void spi1_arch_init(void);
 
-#endif
+#endif // USE_SPI1
 
 #if USE_SPI2
 
@@ -218,8 +218,19 @@ extern void spi2_init(void);
  */
 extern void spi2_arch_init(void);
 
+#endif // USE_SPI2
 
-#endif
+#if USE_SPI3
+
+extern struct spi_periph spi3;
+extern void spi3_init(void);
+
+/** Architecture dependant SPI3 initialization.
+ * Must be implemented by underlying architecture
+ */
+extern void spi3_arch_init(void);
+
+#endif // USE_SPI3
 
 /** Initialize a spi peripheral.
  * @param p spi peripheral to be configured
@@ -275,7 +286,7 @@ extern bool_t spi_resume(struct spi_periph* p, uint8_t slave);
 extern struct spi_periph spi0;
 extern void spi0_slave_init(void);
 
-/** Architecture dependant SPI1 initialization.
+/** Architecture dependant SPI0 initialization as slave.
  * Must be implemented by underlying architecture
  */
 extern void spi0_slave_arch_init(void);
@@ -287,7 +298,7 @@ extern void spi0_slave_arch_init(void);
 extern struct spi_periph spi1;
 extern void spi1_slave_init(void);
 
-/** Architecture dependant SPI1 initialization.
+/** Architecture dependant SPI1 initialization as slave.
  * Must be implemented by underlying architecture
  */
 extern void spi1_slave_arch_init(void);
@@ -299,13 +310,25 @@ extern void spi1_slave_arch_init(void);
 extern struct spi_periph spi2;
 extern void spi2_slave_init(void);
 
-/** Architecture dependant SPI1 initialization.
+/** Architecture dependant SPI2 initialization as slave.
  * Must be implemented by underlying architecture
  */
 extern void spi2_slave_arch_init(void);
 
 #endif
 
+#if USE_SPI3_SLAVE
+
+extern struct spi_periph spi3;
+extern void spi3_slave_init(void);
+
+/** Architecture dependant SPI3 initialization as slave.
+ * Must be implemented by underlying architecture
+ */
+extern void spi3_slave_arch_init(void);
+
+#endif
+
 /** Initialize a spi peripheral in slave mode.
  * @param p spi peripheral to be configured
  */