Mirrors_Framework/paparazzi
1
0
Fork 0
mirror of https://github.com/paparazzi/paparazzi.git synced 2026-05-27 08:55:51 +08:00
Code Issues Actions 29 Packages Projects Releases Wiki Activity

Merge pull request #2419 from paparazzi/tawaki_board-integration

Browse Source 
Tawaki board integration
This commit is contained in:
Gautier Hattenberger
2019-06-19 09:43:46 +02:00
committed by GitHub
parent 4d7045d6ff 5ed41ced72
commit 17b185d4b2
30 changed files with 3871 additions and 44 deletions
Download Patch File Download Diff File Expand all files Collapse all files
sw/airborne/arch/chibios/halconf.h
+1 -1
View File
@@ -105,7 +105,7 @@
* @brief Enables the I2C subsystem.
*/
#if !defined(HAL_USE_I2C) || defined(__DOXYGEN__)
#if USE_I2C1 || USE_I2C2 || USE_I2C3
#if USE_I2C1 || USE_I2C2 || USE_I2C3 || USE_I2C4
#define HAL_USE_I2C TRUE
#else
#define HAL_USE_I2C FALSE
sw/airborne/arch/chibios/led_hw.h
+11 -10
View File
@@ -34,23 +34,24 @@
* hal.h is needed for palXXX functions
*/
#include <hal.h>
#include "mcu_periph/gpio_def.h"
#include "mcu_periph/gpio.h"
#include BOARD_CONFIG
/*
* Regular GPIO driven LEDs
*/
#define _LED_GPIO(i) i
#define _LED_GPIO_PIN(i) i
#define _LED_EVAL(i) i
#define LED_GPIO(i) _LED_GPIO(LED_ ## i ## _GPIO)
#define LED_GPIO_PIN(i) _LED_GPIO_PIN(LED_ ## i ## _GPIO_PIN)
#define LED_GPIO(i) _LED_EVAL(LED_ ## i ## _GPIO)
#define LED_GPIO_PIN(i) _LED_EVAL(LED_ ## i ## _GPIO_PIN)
#define LED_GPIO_ON(i) _LED_EVAL(LED_ ## i ## _GPIO_ON)
#define LED_GPIO_OFF(i) _LED_EVAL(LED_ ## i ## _GPIO_OFF)
#define LED_INIT(i) palSetPadMode(LED_GPIO(i), LED_GPIO_PIN(i), PAL_MODE_OUTPUT_PUSHPULL)
#define LED_ON(i) palClearPad(LED_GPIO(i), LED_GPIO_PIN(i))
#define LED_OFF(i) palSetPad(LED_GPIO(i), LED_GPIO_PIN(i))
#define LED_TOGGLE(i) palTogglePad(LED_GPIO(i), LED_GPIO_PIN(i))
#define LED_DISABLE(i) palSetPadMode(LED_GPIO(i), LED_GPIO_PIN(i), PAL_MODE_INPUT)
#define LED_INIT(i) gpio_setup_output(LED_GPIO(i), LED_GPIO_PIN(i))
#define LED_ON(i) LED_GPIO_ON(i)(LED_GPIO(i), LED_GPIO_PIN(i))
#define LED_OFF(i) LED_GPIO_OFF(i)(LED_GPIO(i), LED_GPIO_PIN(i))
#define LED_TOGGLE(i) gpio_toggle(LED_GPIO(i), LED_GPIO_PIN(i))
#define LED_DISABLE(i) gpio_setup_input(LED_GPIO(i), LED_GPIO_PIN(i))
#define LED_PERIODIC() {}
#endif /* LED_HW_H */
sw/airborne/arch/chibios/mcu_periph/i2c_arch.c
+59 -4
View File
@@ -46,7 +46,7 @@
#define I2C_THREAD_STACK_SIZE 512
#endif
#if USE_I2C1 || USE_I2C2 || USE_I2C3
#if USE_I2C1 || USE_I2C2 || USE_I2C3 || USE_I2C4
// private I2C init structure
struct i2c_init {
@@ -177,7 +177,7 @@ static void handle_i2c_thd(struct i2c_periph *p)
break;
}
}
#endif /* USE_I2C1 || USE_I2C2 || USE_I2C3 */
#endif /* USE_I2C1 || USE_I2C2 || USE_I2C3 || USE_I2C4 */
#if USE_I2C1
// I2C1 config
@@ -342,6 +342,61 @@ static void thd_i2c3(void *arg)
}
#endif /* USE_I2C3 */
#if USE_I2C4
// I2C4 config
PRINT_CONFIG_VAR(I2C4_CLOCK_SPEED)
static SEMAPHORE_DECL(i2c4_sem, 0);
static I2CConfig i2cfg4 = I2C4_CFG_DEF;
#if defined STM32F7
// We need a special buffer for DMA operations
static IN_DMA_SECTION(uint8_t i2c4_dma_buf[I2C_BUF_LEN]);
static struct i2c_init i2c4_init_s = {
.sem = &i2c4_sem,
.cfg = &i2cfg4,
.dma_buf = i2c4_dma_buf
};
#else
static struct i2c_init i2c4_init_s = {
.sem = &i2c4_sem,
.cfg = &i2cfg4
};
#endif
// Errors
struct i2c_errors i2c4_errors;
// Thread
static __attribute__((noreturn)) void thd_i2c4(void *arg);
static THD_WORKING_AREA(wa_thd_i2c4, 128);
/*
* I2C4 init
*/
void i2c4_hw_init(void)
{
i2cStart(&I2CD4, &i2cfg4);
i2c4.reg_addr = &I2CD4;
i2c4.init_struct = NULL;
i2c4.errors = &i2c4_errors;
i2c4.init_struct = &i2c4_init_s;
// Create thread
chThdCreateStatic(wa_thd_i2c4, sizeof(wa_thd_i2c4),
NORMALPRIO + 1, thd_i2c4, NULL);
}
/*
* I2C4 thread
*
*/
static void thd_i2c4(void *arg)
{
(void) arg;
chRegSetThreadName("i2c4");
while (TRUE) {
handle_i2c_thd(&i2c4);
}
}
#endif /* USE_I2C4 */
/**
* i2c_event() function
@@ -377,7 +432,7 @@ void i2c_setbitrate(struct i2c_periph *p __attribute__((unused)), int bitrate __
*/
bool i2c_submit(struct i2c_periph *p, struct i2c_transaction *t)
{
#if USE_I2C1 || USE_I2C2 || USE_I2C3
#if USE_I2C1 || USE_I2C2 || USE_I2C3 || USE_I2C4
// sys lock
chSysLock();
uint8_t temp;
@@ -406,7 +461,7 @@ bool i2c_submit(struct i2c_periph *p, struct i2c_transaction *t)
(void)p;
(void)t;
return FALSE;
#endif /* USE_I2C1 || USE_I2C2 || USE_I2C3 */
#endif /* USE_I2C1 || USE_I2C2 || USE_I2C3 || USE_I2C4 */
}
/**
sw/airborne/arch/chibios/mcu_periph/i2c_arch.h
+4
View File
@@ -45,4 +45,8 @@ extern void i2c2_hw_init(void);
extern void i2c3_hw_init(void);
#endif /* USE_I2C3 */
#if USE_I2C4
extern void i2c4_hw_init(void);
#endif /* USE_I2C4 */
#endif /* I2C_HW_H */
sw/airborne/arch/chibios/mcu_periph/spi_arch.c
+43 -2
View File
@@ -167,10 +167,12 @@ static inline uint16_t spi_resolve_slave_pin(uint8_t slave)
static inline uint16_t spi_resolve_CR1(struct spi_transaction *t __attribute__((unused)))
{
uint16_t CR1 = 0;
#if defined(STM32F1) || defined(STM32F4) || defined(STM32F7)
#if defined(STM32F1) || defined(STM32F4)
if (t->dss == SPIDss16bit) {
CR1 |= SPI_CR1_DFF;
CR1 |= SPI_CR1_DFF; // FIXME for F7
}
#endif
#if defined(STM32F1) || defined(STM32F4) || defined(STM32F7)
if (t->bitorder == SPILSBFirst) {
CR1 |= SPI_CR1_LSBFIRST;
}
@@ -443,6 +445,45 @@ void spi3_arch_init(void)
}
#endif
#if USE_SPI4
static SEMAPHORE_DECL(spi4_sem, 0);
#if defined STM32F7
// We need a special buffer for DMA operations
static IN_DMA_SECTION(uint8_t spi4_dma_buf_out[SPI_DMA_BUF_LEN]);
static IN_DMA_SECTION(uint8_t spi4_dma_buf_in[SPI_DMA_BUF_LEN]);
static struct spi_init spi4_init_s = {
.sem = &spi4_sem,
.dma_buf_out = spi4_dma_buf_out,
.dma_buf_in = spi4_dma_buf_in
};
#else
static struct spi_init spi4_init_s = {
.sem = &spi4_sem,
};
#endif
static __attribute__((noreturn)) void thd_spi4(void *arg)
{
(void) arg;
chRegSetThreadName("spi4");
while (TRUE) {
handle_spi_thd(&spi4);
}
}
static THD_WORKING_AREA(wa_thd_spi4, 256);
void spi4_arch_init(void)
{
spi4.reg_addr = &SPID4;
spi4.init_struct = &spi4_init_s;
// Create thread
chThdCreateStatic(wa_thd_spi4, sizeof(wa_thd_spi4),
NORMALPRIO + 1, thd_spi4, NULL);
}
#endif
/**
* Submit SPI transaction
sw/airborne/boards/tawaki/baro_board.h
+19
View File
@@ -0,0 +1,19 @@
/*
* board specific functions for the tawaki board
*
*/
#ifndef BOARDS_TAWAKI_BARO_H
#define BOARDS_TAWAKI_BARO_H
// only for printing the baro type during compilation
#ifndef BARO_BOARD
#define BARO_BOARD BARO_BMP3_I2C
#endif
extern void baro_event(void);
#define BaroEvent baro_event
#endif /* BOARDS_TAWAKI_BARO_H */
sw/airborne/boards/tawaki/chibios/v1.0/Makefile
+9
View File
@@ -0,0 +1,9 @@
# file board.h is generated from file board.cfg by a script which is hosted here :
# https://github.com/alex31/chibios_enac_various_common/blob/master/TOOLS/boardGen.pl
# documentation is here :
# https://github.com/alex31/chibios_enac_various_common/blob/master/TOOLS/DOC/boardGen.pdf
board.h: board.cfg Makefile
boardGen.pl --no-pp-pin --no-pp-line $< $@
sw/airborne/boards/tawaki/chibios/v1.0/board.c
+266
View File
@@ -0,0 +1,266 @@
/*
ChibiOS - Copyright (C) 2006..2018 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
/*
* This file has been automatically generated using ChibiStudio board
* generator plugin. Do not edit manually.
*/
#include "hal.h"
#include "stm32_gpio.h"
/*===========================================================================*/
/* Driver local definitions. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported variables. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver local variables and types. */
/*===========================================================================*/
/**
* @brief Type of STM32 GPIO port setup.
*/
typedef struct {
uint32_t moder;
uint32_t otyper;
uint32_t ospeedr;
uint32_t pupdr;
uint32_t odr;
uint32_t afrl;
uint32_t afrh;
} gpio_setup_t;
/**
* @brief Type of STM32 GPIO initialization data.
*/
typedef struct {
#if STM32_HAS_GPIOA || defined(__DOXYGEN__)
gpio_setup_t PAData;
#endif
#if STM32_HAS_GPIOB || defined(__DOXYGEN__)
gpio_setup_t PBData;
#endif
#if STM32_HAS_GPIOC || defined(__DOXYGEN__)
gpio_setup_t PCData;
#endif
#if STM32_HAS_GPIOD || defined(__DOXYGEN__)
gpio_setup_t PDData;
#endif
#if STM32_HAS_GPIOE || defined(__DOXYGEN__)
gpio_setup_t PEData;
#endif
#if STM32_HAS_GPIOF || defined(__DOXYGEN__)
gpio_setup_t PFData;
#endif
#if STM32_HAS_GPIOG || defined(__DOXYGEN__)
gpio_setup_t PGData;
#endif
#if STM32_HAS_GPIOH || defined(__DOXYGEN__)
gpio_setup_t PHData;
#endif
#if STM32_HAS_GPIOI || defined(__DOXYGEN__)
gpio_setup_t PIData;
#endif
#if STM32_HAS_GPIOJ || defined(__DOXYGEN__)
gpio_setup_t PJData;
#endif
#if STM32_HAS_GPIOK || defined(__DOXYGEN__)
gpio_setup_t PKData;
#endif
} gpio_config_t;
/**
* @brief STM32 GPIO static initialization data.
*/
static const gpio_config_t gpio_default_config = {
#if STM32_HAS_GPIOA
{VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR,
VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH},
#endif
#if STM32_HAS_GPIOB
{VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR,
VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH},
#endif
#if STM32_HAS_GPIOC
{VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR,
VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH},
#endif
#if STM32_HAS_GPIOD
{VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR,
VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH},
#endif
#if STM32_HAS_GPIOE
{VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR,
VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH},
#endif
#if STM32_HAS_GPIOF
{VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR,
VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH},
#endif
#if STM32_HAS_GPIOG
{VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR,
VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH},
#endif
#if STM32_HAS_GPIOH
{VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR,
VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH},
#endif
#if STM32_HAS_GPIOI
{VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR,
VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH},
#endif
#if STM32_HAS_GPIOJ
{VAL_GPIOJ_MODER, VAL_GPIOJ_OTYPER, VAL_GPIOJ_OSPEEDR, VAL_GPIOJ_PUPDR,
VAL_GPIOJ_ODR, VAL_GPIOJ_AFRL, VAL_GPIOJ_AFRH},
#endif
#if STM32_HAS_GPIOK
{VAL_GPIOK_MODER, VAL_GPIOK_OTYPER, VAL_GPIOK_OSPEEDR, VAL_GPIOK_PUPDR,
VAL_GPIOK_ODR, VAL_GPIOK_AFRL, VAL_GPIOK_AFRH}
#endif
};
/*===========================================================================*/
/* Driver local functions. */
/*===========================================================================*/
static void gpio_init(stm32_gpio_t *gpiop, const gpio_setup_t *config) {
gpiop->OTYPER = config->otyper;
gpiop->OSPEEDR = config->ospeedr;
gpiop->PUPDR = config->pupdr;
gpiop->ODR = config->odr;
gpiop->AFRL = config->afrl;
gpiop->AFRH = config->afrh;
gpiop->MODER = config->moder;
}
static void stm32_gpio_init(void) {
/* Enabling GPIO-related clocks, the mask comes from the
registry header file.*/
rccResetAHB1(STM32_GPIO_EN_MASK);
rccEnableAHB1(STM32_GPIO_EN_MASK, true);
/* Initializing all the defined GPIO ports.*/
#if STM32_HAS_GPIOA
gpio_init(GPIOA, &gpio_default_config.PAData);
#endif
#if STM32_HAS_GPIOB
gpio_init(GPIOB, &gpio_default_config.PBData);
#endif
#if STM32_HAS_GPIOC
gpio_init(GPIOC, &gpio_default_config.PCData);
#endif
#if STM32_HAS_GPIOD
gpio_init(GPIOD, &gpio_default_config.PDData);
#endif
#if STM32_HAS_GPIOE
gpio_init(GPIOE, &gpio_default_config.PEData);
#endif
#if STM32_HAS_GPIOF
gpio_init(GPIOF, &gpio_default_config.PFData);
#endif
#if STM32_HAS_GPIOG
gpio_init(GPIOG, &gpio_default_config.PGData);
#endif
#if STM32_HAS_GPIOH
gpio_init(GPIOH, &gpio_default_config.PHData);
#endif
#if STM32_HAS_GPIOI
gpio_init(GPIOI, &gpio_default_config.PIData);
#endif
#if STM32_HAS_GPIOJ
gpio_init(GPIOJ, &gpio_default_config.PJData);
#endif
#if STM32_HAS_GPIOK
gpio_init(GPIOK, &gpio_default_config.PKData);
#endif
}
/*===========================================================================*/
/* Driver interrupt handlers. */
/*===========================================================================*/
/*===========================================================================*/
/* Driver exported functions. */
/*===========================================================================*/
/**
* @brief Early initialization code.
* @details GPIO ports and system clocks are initialized before everything
* else.
*/
void __early_init(void) {
stm32_gpio_init();
stm32_clock_init();
}
#if HAL_USE_SDC || defined(__DOXYGEN__)
/**
* @brief SDC card detection.
*/
bool sdc_lld_is_card_inserted(SDCDriver *sdcp) {
(void)sdcp;
/* assume card is inserted as there is no SD_DETECT pin
* actual detection will be done by the software
*/
return true;
}
/**
* @brief SDC card write protection detection.
*/
bool sdc_lld_is_write_protected(SDCDriver *sdcp) {
(void)sdcp;
return false;
}
#endif /* HAL_USE_SDC */
#if HAL_USE_MMC_SPI || defined(__DOXYGEN__)
/**
* @brief MMC_SPI card detection.
*/
bool mmc_lld_is_card_inserted(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
return true;
}
/**
* @brief MMC_SPI card write protection detection.
*/
bool mmc_lld_is_write_protected(MMCDriver *mmcp) {
(void)mmcp;
/* TODO: Fill the implementation.*/
return false;
}
#endif
/**
* @brief Board-specific initialization code.
* @todo Add your board-specific code, if any.
*/
void boardInit(void) {
}
sw/airborne/boards/tawaki/chibios/v1.0/board.h
+1559
View File
File diff suppressed because it is too large Load Diff
sw/airborne/boards/tawaki/chibios/v1.0/board.mk
+20
View File
@@ -0,0 +1,20 @@
#
# ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio
#
# Licensed under the Apache License, Version 2.0 (the "License");
# you may not use this file except in compliance with the License.
# You may obtain a copy of the License at
#
# http://www.apache.org/licenses/LICENSE-2.0
#
# Unless required by applicable law or agreed to in writing, software
# distributed under the License is distributed on an "AS IS" BASIS,
# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
# See the License for the specific language governing permissions and
# limitations under the License.
#
# Required include directories
BOARDINC = $(CHIBIOS_BOARD_DIR)
# List of all the board related files.
BOARDSRC = ${BOARDINC}/board.c
sw/airborne/boards/tawaki/chibios/v1.0/ffconf.h
+270
View File
@@ -0,0 +1,270 @@
/* CHIBIOS FIX */
#include "ch.h"
/*---------------------------------------------------------------------------/
/ FatFs - FAT file system module configuration file
/---------------------------------------------------------------------------*/
#define FFCONF_DEF 87030 /* Revision ID */
/*---------------------------------------------------------------------------/
/ Function Configurations
/---------------------------------------------------------------------------*/
#define FF_FS_READONLY 0
/* This option switches read-only configuration. (0:Read/Write or 1:Read-only)
/ Read-only configuration removes writing API functions, f_write(), f_sync(),
/ f_unlink(), f_mkdir(), f_chmod(), f_rename(), f_truncate(), f_getfree()
/ and optional writing functions as well. */
#define FF_FS_MINIMIZE 0
/* This option defines minimization level to remove some basic API functions.
/
/ 0: All basic functions are enabled.
/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_truncate() and f_rename()
/ are removed.
/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1.
/ 3: f_lseek() function is removed in addition to 2. */
#define FF_USE_STRFUNC 0
/* This option switches string functions, f_gets(), f_putc(), f_puts() and
/ f_printf().
/
/ 0: Disable string functions.
/ 1: Enable without LF-CRLF conversion.
/ 2: Enable with LF-CRLF conversion. */
#define FF_USE_FIND 1
/* This option switches filtered directory read functions, f_findfirst() and
/ f_findnext(). (0:Disable, 1:Enable 2:Enable with matching altname[] too) */
#define FF_USE_MKFS 1
/* This option switches f_mkfs() function. (0:Disable or 1:Enable) */
#define FF_USE_FASTSEEK 1
/* This option switches fast seek function. (0:Disable or 1:Enable) */
#define FF_USE_EXPAND 1
/* This option switches f_expand function. (0:Disable or 1:Enable) */
#define FF_USE_CHMOD 1
/* This option switches attribute manipulation functions, f_chmod() and f_utime().
/ (0:Disable or 1:Enable) Also FF_FS_READONLY needs to be 0 to enable this option. */
#define FF_USE_LABEL 1
/* This option switches volume label functions, f_getlabel() and f_setlabel().
/ (0:Disable or 1:Enable) */
#define FF_USE_FORWARD 1
/* This option switches f_forward() function. (0:Disable or 1:Enable) */
/*---------------------------------------------------------------------------/
/ Locale and Namespace Configurations
/---------------------------------------------------------------------------*/
#define FF_CODE_PAGE 850
/* This option specifies the OEM code page to be used on the target system.
/ Incorrect setting of the code page can cause a file open failure.
/
/ 1 - ASCII (No extended character. Non-LFN cfg. only)
/ 437 - U.S.
/ 720 - Arabic
/ 737 - Greek
/ 771 - KBL
/ 775 - Baltic
/ 850 - Latin 1
/ 852 - Latin 2
/ 855 - Cyrillic
/ 857 - Turkish
/ 860 - Portuguese
/ 861 - Icelandic
/ 862 - Hebrew
/ 863 - Canadian French
/ 864 - Arabic
/ 865 - Nordic
/ 866 - Russian
/ 869 - Greek 2
/ 932 - Japanese (DBCS)
/ 936 - Simplified Chinese (DBCS)
/ 949 - Korean (DBCS)
/ 950 - Traditional Chinese (DBCS)
*/
#define FF_USE_LFN 3
#define FF_MAX_LFN 255
/* The FF_USE_LFN switches the support of long file name (LFN).
/
/ 0: Disable support of LFN. _MAX_LFN has no effect.
/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe.
/ 2: Enable LFN with dynamic working buffer on the STACK.
/ 3: Enable LFN with dynamic working buffer on the HEAP.
/
/ To enable the LFN, Unicode handling functions (option/unicode.c) must be added
/ to the project. The working buffer occupies (_MAX_LFN + 1) * 2 bytes and
/ additional 608 bytes at exFAT enabled. _MAX_LFN can be in range from 12 to 255.
/ It should be set 255 to support full featured LFN operations.
/ When use stack for the working buffer, take care on stack overflow. When use heap
/ memory for the working buffer, memory management functions, ff_memalloc() and
/ ff_memfree(), must be added to the project. */
#define FF_LFN_UNICODE 0
/* This option switches character encoding on the API. (0:ANSI/OEM or 1:UTF-16)
/ To use Unicode string for the path name, enable LFN and set _LFN_UNICODE = 1.
/ This option also affects behavior of string I/O functions. */
#define FF_STRF_ENCODE 3
/* When _LFN_UNICODE == 1, this option selects the character encoding ON THE FILE to
/ be read/written via string I/O functions, f_gets(), f_putc(), f_puts and f_printf().
/
/ 0: ANSI/OEM
/ 1: UTF-16LE
/ 2: UTF-16BE
/ 3: UTF-8
/
/ This option has no effect when _LFN_UNICODE == 0. */
#define FF_FS_RPATH 1
/* This option configures support of relative path.
/
/ 0: Disable relative path and remove related functions.
/ 1: Enable relative path. f_chdir() and f_chdrive() are available.
/ 2: f_getcwd() function is available in addition to 1.
*/
/*---------------------------------------------------------------------------/
/ Drive/Volume Configurations
/---------------------------------------------------------------------------*/
#define FF_VOLUMES 1
/* Number of volumes (logical drives) to be used. */
#define FF_STR_VOLUME_ID 0
#define FF_VOLUME_STRS "RAM","NAND","CF","SD","SD2","USB","USB2","USB3"
/* _STR_VOLUME_ID switches string support of volume ID.
/ When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive
/ number in the path name. _VOLUME_STRS defines the drive ID strings for each
/ logical drives. Number of items must be equal to _VOLUMES. Valid characters for
/ the drive ID strings are: A-Z and 0-9. */
#define FF_MULTI_PARTITION 0
/* This option switches support of multi-partition on a physical drive.
/ By default (0), each logical drive number is bound to the same physical drive
/ number and only an FAT volume found on the physical drive will be mounted.
/ When multi-partition is enabled (1), each logical drive number can be bound to
/ arbitrary physical drive and partition listed in the VolToPart[]. Also f_fdisk()
/ funciton will be available. */
#define FF_MIN_SS 512
#define FF_MAX_SS 512
/* These options configure the range of sector size to be supported. (512, 1024,
/ 2048 or 4096) Always set both 512 for most systems, all type of memory cards and
/ harddisk. But a larger value may be required for on-board flash memory and some
/ type of optical media. When _MAX_SS is larger than _MIN_SS, FatFs is configured
/ to variable sector size and GET_SECTOR_SIZE command must be implemented to the
/ disk_ioctl() function. */
#define FF_USE_TRIM 0
/* This option switches support of ATA-TRIM. (0:Disable or 1:Enable)
/ To enable Trim function, also CTRL_TRIM command should be implemented to the
/ disk_ioctl() function. */
#define FF_FS_NOFSINFO 0
/* If you need to know correct free space on the FAT32 volume, set bit 0 of this
/ option, and f_getfree() function at first time after volume mount will force
/ a full FAT scan. Bit 1 controls the use of last allocated cluster number.
/
/ bit0=0: Use free cluster count in the FSINFO if available.
/ bit0=1: Do not trust free cluster count in the FSINFO.
/ bit1=0: Use last allocated cluster number in the FSINFO if available.
/ bit1=1: Do not trust last allocated cluster number in the FSINFO.
*/
/*---------------------------------------------------------------------------/
/ System Configurations
/---------------------------------------------------------------------------*/
#define FF_FS_TINY 0
/* This option switches tiny buffer configuration. (0:Normal or 1:Tiny)
/ At the tiny configuration, size of file object (FIL) is reduced _MAX_SS bytes.
/ Instead of private sector buffer eliminated from the file object, common sector
/ buffer in the file system object (FATFS) is used for the file data transfer. */
#define FF_FS_EXFAT 1
/* This option switches support of exFAT file system. (0:Disable or 1:Enable)
/ When enable exFAT, also LFN needs to be enabled. (FF_USE_LFN >= 1)
/ Note that enabling exFAT discards C89 compatibility. */
#define FF_FS_NORTC 0
#define FF_NORTC_MON 1
#define FF_NORTC_MDAY 1
#define FF_NORTC_YEAR 2016
/* The option FF_FS_NORTC switches timestamp functiton. If the system does not have
/ any RTC function or valid timestamp is not needed, set FF_FS_NORTC = 1 to disable
/ the timestamp function. All objects modified by FatFs will have a fixed timestamp
/ defined by _NORTC_MON, _NORTC_MDAY and _NORTC_YEAR in local time.
/ To enable timestamp function (FF_FS_NORTC = 0), get_fattime() function need to be
/ added to the project to get current time form real-time clock. _NORTC_MON,
/ _NORTC_MDAY and _NORTC_YEAR have no effect.
/ These options have no effect at read-only configuration (FF_FS_READONLY = 1). */
#define FF_FS_LOCK 0
/* The option FF_FS_LOCK switches file lock function to control duplicated file open
/ and illegal operation to open objects. This option must be 0 when FF_FS_READONLY
/ is 1.
/
/ 0: Disable file lock function. To avoid volume corruption, application program
/ should avoid illegal open, remove and rename to the open objects.
/ >0: Enable file lock function. The value defines how many files/sub-directories
/ can be opened simultaneously under file lock control. Note that the file
/ lock control is independent of re-entrancy. */
#define FF_FS_REENTRANT 1
#define FF_FS_TIMEOUT TIME_MS2I(1000)
#define FF_SYNC_t semaphore_t*
/* The option FF_FS_REENTRANT switches the re-entrancy (thread safe) of the FatFs
/ module itself. Note that regardless of this option, file access to different
/ volume is always re-entrant and volume control functions, f_mount(), f_mkfs()
/ and f_fdisk() function, are always not re-entrant. Only file/directory access
/ to the same volume is under control of this function.
/
/ 0: Disable re-entrancy. FF_FS_TIMEOUT and _SYNC_t have no effect.
/ 1: Enable re-entrancy. Also user provided synchronization handlers,
/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj()
/ function, must be added to the project. Samples are available in
/ option/syscall.c.
/
/ The FF_FS_TIMEOUT defines timeout period in unit of time tick.
/ The _SYNC_t defines O/S dependent sync object type. e.g. HANDLE, ID, OS_EVENT*,
/ SemaphoreHandle_t and etc.. A header file for O/S definitions needs to be
/ included somewhere in the scope of ff.h. */
/* #include <windows.h> // O/S definitions */
/*--- End of configuration options ---*/
sw/airborne/boards/tawaki/chibios/v1.0/mcuconf.h
+483
View File
@@ -0,0 +1,483 @@
/*
ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio
Licensed under the Apache License, Version 2.0 (the "License");
you may not use this file except in compliance with the License.
You may obtain a copy of the License at
http://www.apache.org/licenses/LICENSE-2.0
Unless required by applicable law or agreed to in writing, software
distributed under the License is distributed on an "AS IS" BASIS,
WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
See the License for the specific language governing permissions and
limitations under the License.
*/
#ifndef _MCUCONF_H_
#define _MCUCONF_H_
/*
* STM32F4xx drivers configuration.
* The following settings override the default settings present in
* the various device driver implementation headers.
* Note that the settings for each driver only have effect if the whole
* driver is enabled in halconf.h.
*
* IRQ priorities:
* 15...0 Lowest...Highest.
*
* DMA priorities:
* 0...3 Lowest...Highest.
*/
#define STM32F7xx_MCUCONF
/*
* HAL driver system settings.
*/
#define STM32_NO_INIT FALSE
#define STM32_PVD_ENABLE FALSE
#define STM32_PLS STM32_PLS_LEV0
#define STM32_BKPRAM_ENABLE FALSE
#define STM32_HSI_ENABLED TRUE
#if HAL_USE_RTC
#define STM32_LSI_ENABLED TRUE
#else
#define STM32_LSI_ENABLED FALSE
#endif
#define STM32_HSE_ENABLED TRUE
#define STM32_LSE_ENABLED FALSE
#define STM32_CLOCK48_REQUIRED TRUE
#define STM32_SW STM32_SW_PLL
#define STM32_PLLSRC STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE 16
#define STM32_PLLN_VALUE 432
#define STM32_PLLP_VALUE 2
#define STM32_PLLQ_VALUE 9
#define STM32_HPRE STM32_HPRE_DIV1
#define STM32_PPRE1 STM32_PPRE1_DIV4
#define STM32_PPRE2 STM32_PPRE2_DIV2
#if HAL_USE_RTC
#define STM32_RTCSEL STM32_RTCSEL_LSI
#else
#define STM32_RTCSEL STM32_RTCSEL_NOCLOCK
#endif
#define STM32_RTCPRE_VALUE 25
#define STM32_MCO1SEL STM32_MCO1SEL_HSE
#define STM32_MCO1PRE STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE STM32_MCO2PRE_DIV4
#define STM32_I2SSRC STM32_I2SSRC_PLLI2S
#define STM32_PLLI2SN_VALUE 192
#define STM32_PLLI2SP_VALUE 4
#define STM32_PLLI2SQ_VALUE 4
#define STM32_PLLI2SR_VALUE 4
#define STM32_PLLSAIN_VALUE 192
#define STM32_PLLSAIP_VALUE 4
#define STM32_PLLSAIQ_VALUE 4
#define STM32_PLLSAIR_VALUE 4
#define STM32_PLLSAIDIVR_VALUE 2
#define STM32_SAI1SEL STM32_SAI1SEL_OFF
#define STM32_SAI2SEL STM32_SAI2SEL_OFF
#define STM32_USART1SEL STM32_USART1SEL_PCLK2
#define STM32_USART2SEL STM32_USART2SEL_PCLK1
#define STM32_USART3SEL STM32_USART3SEL_PCLK1
#define STM32_UART4SEL STM32_UART4SEL_PCLK1
#define STM32_UART5SEL STM32_UART5SEL_PCLK1
#define STM32_USART6SEL STM32_USART6SEL_PCLK2
#define STM32_UART7SEL STM32_UART7SEL_PCLK1
#define STM32_UART8SEL STM32_UART8SEL_PCLK1
#define STM32_I2C1SEL STM32_I2C1SEL_PCLK1 // STM32_I2C1SEL_SYSCLK
#define STM32_I2C2SEL STM32_I2C2SEL_PCLK1
#define STM32_I2C3SEL STM32_I2C3SEL_PCLK1
#define STM32_I2C4SEL STM32_I2C4SEL_PCLK1
#define STM32_LPTIM1SEL STM32_LPTIM1SEL_PCLK1
#define STM32_CECSEL STM32_CECSEL_LSE
#define STM32_CK48MSEL STM32_CK48MSEL_PLL
#define STM32_SDMMCSEL STM32_SDMMCSEL_PLL48CLK
#define STM32_SRAM2_NOCACHE FALSE
/*
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
#define STM32_ADC_ADC1_DMA_PRIORITY 2
#define STM32_ADC_ADC2_DMA_PRIORITY 2
#define STM32_ADC_ADC3_DMA_PRIORITY 2
#define STM32_ADC_IRQ_PRIORITY 6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6
/*
* CAN driver system settings.
*/
#if USE_CAN1
#define STM32_CAN_USE_CAN1 TRUE
#else
#define STM32_CAN_USE_CAN1 FALSE
#endif
#define STM32_CAN_USE_CAN2 FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY 11
#define STM32_CAN_CAN2_IRQ_PRIORITY 11
/*
* DAC driver system settings.
*/
#define STM32_DAC_DUAL_MODE FALSE
#define STM32_DAC_USE_DAC1_CH1 FALSE
#define STM32_DAC_USE_DAC1_CH2 FALSE
#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10
#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2
#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2
//#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6)
/*
* EXT driver system settings.
*/
#define STM32_EXT_EXTI0_IRQ_PRIORITY 6
#define STM32_EXT_EXTI1_IRQ_PRIORITY 6
#define STM32_EXT_EXTI2_IRQ_PRIORITY 6
#define STM32_EXT_EXTI3_IRQ_PRIORITY 6
#define STM32_EXT_EXTI4_IRQ_PRIORITY 6
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6
#define STM32_EXT_EXTI16_IRQ_PRIORITY 6
#define STM32_EXT_EXTI17_IRQ_PRIORITY 15
#define STM32_EXT_EXTI18_IRQ_PRIORITY 6
#define STM32_EXT_EXTI19_IRQ_PRIORITY 6
#define STM32_EXT_EXTI20_IRQ_PRIORITY 6
#define STM32_EXT_EXTI21_IRQ_PRIORITY 15
#define STM32_EXT_EXTI22_IRQ_PRIORITY 15
/*
* GPT driver system settings.
*/
#define STM32_GPT_USE_TIM1 FALSE
#define STM32_GPT_USE_TIM2 FALSE // keep free if in tickless mode
#define STM32_GPT_USE_TIM3 FALSE
#define STM32_GPT_USE_TIM4 FALSE
#define STM32_GPT_USE_TIM5 FALSE
#define STM32_GPT_USE_TIM6 FALSE
#define STM32_GPT_USE_TIM7 FALSE
#define STM32_GPT_USE_TIM8 FALSE
#define STM32_GPT_USE_TIM9 FALSE
#define STM32_GPT_USE_TIM11 FALSE
#define STM32_GPT_USE_TIM12 FALSE
#define STM32_GPT_USE_TIM14 FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY 7
#define STM32_GPT_TIM2_IRQ_PRIORITY 7
#define STM32_GPT_TIM3_IRQ_PRIORITY 7
#define STM32_GPT_TIM4_IRQ_PRIORITY 7
#define STM32_GPT_TIM5_IRQ_PRIORITY 7
#define STM32_GPT_TIM6_IRQ_PRIORITY 7
#define STM32_GPT_TIM7_IRQ_PRIORITY 7
#define STM32_GPT_TIM8_IRQ_PRIORITY 7
#define STM32_GPT_TIM9_IRQ_PRIORITY 7
#define STM32_GPT_TIM11_IRQ_PRIORITY 7
#define STM32_GPT_TIM12_IRQ_PRIORITY 7
#define STM32_GPT_TIM14_IRQ_PRIORITY 7
/*
* I2C driver system settings.
*/
//#if USE_I2C1
//#define STM32_I2C_USE_I2C1 TRUE
//#else
#define STM32_I2C_USE_I2C1 FALSE // incompatible with I2C2 and I2C4
//#endif
#if USE_I2C2
#define STM32_I2C_USE_I2C2 TRUE
#else
#define STM32_I2C_USE_I2C2 FALSE
#endif
#define STM32_I2C_USE_I2C3 FALSE
#if USE_I2C4
#define STM32_I2C_USE_I2C4 TRUE
#else
#define STM32_I2C_USE_I2C4 FALSE
#endif
#define STM32_I2C_BUSY_TIMEOUT 50
#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
//#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
//#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_I2C_I2C4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) // FIXME check if 5 is really not possible
#define STM32_I2C_I2C1_IRQ_PRIORITY 5
#define STM32_I2C_I2C2_IRQ_PRIORITY 5
#define STM32_I2C_I2C3_IRQ_PRIORITY 5
#define STM32_I2C_I2C4_IRQ_PRIORITY 5
#define STM32_I2C_I2C1_DMA_PRIORITY 3
#define STM32_I2C_I2C2_DMA_PRIORITY 3
#define STM32_I2C_I2C3_DMA_PRIORITY 3
#define STM32_I2C_I2C4_DMA_PRIORITY 3
#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure")
/*
* ICU driver system settings.
*/
#define STM32_ICU_USE_TIM1 FALSE
#ifdef USE_PWM_INPUT1
#define STM32_ICU_USE_TIM2 TRUE
#else
#define STM32_ICU_USE_TIM2 FALSE // keep free if in tickless mode
#endif
#define STM32_ICU_USE_TIM3 FALSE
#define STM32_ICU_USE_TIM4 FALSE
#if RADIO_CONTROL_TYPE_PPM
#define STM32_ICU_USE_TIM5 TRUE
#else
#define STM32_ICU_USE_TIM5 FALSE
#endif
#ifdef USE_PWM_INPUT2
#define STM32_ICU_USE_TIM8 TRUE
#else
#define STM32_ICU_USE_TIM8 FALSE
#endif
#define STM32_ICU_USE_TIM9 FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY 7
#define STM32_ICU_TIM2_IRQ_PRIORITY 7
#define STM32_ICU_TIM3_IRQ_PRIORITY 7
#define STM32_ICU_TIM4_IRQ_PRIORITY 7
#define STM32_ICU_TIM5_IRQ_PRIORITY 7
#define STM32_ICU_TIM8_IRQ_PRIORITY 7
#define STM32_ICU_TIM9_IRQ_PRIORITY 7
/*
* MAC driver system settings.
*/
#define STM32_MAC_TRANSMIT_BUFFERS 2
#define STM32_MAC_RECEIVE_BUFFERS 4
#define STM32_MAC_BUFFERS_SIZE 1522
#define STM32_MAC_PHY_TIMEOUT 100
#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE
#define STM32_MAC_ETH1_IRQ_PRIORITY 13
#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0
/*
* PWM driver system settings.
*/
#define STM32_PWM_USE_ADVANCED FALSE
#ifndef STM32_PWM_USE_TIM1
#define STM32_PWM_USE_TIM1 TRUE
#endif
#ifndef STM32_PWM_USE_TIM2
#define STM32_PWM_USE_TIM2 FALSE // keep free if in tickless mode, can be used in systick mode
#endif
#define STM32_PWM_USE_TIM3 FALSE
#ifndef STM32_PWM_USE_TIM4
#define STM32_PWM_USE_TIM4 TRUE
#endif
#define STM32_PWM_USE_TIM5 FALSE
#define STM32_PWM_USE_TIM8 FALSE
#define STM32_PWM_USE_TIM9 FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY 7
#define STM32_PWM_TIM2_IRQ_PRIORITY 7
#define STM32_PWM_TIM3_IRQ_PRIORITY 7
#define STM32_PWM_TIM4_IRQ_PRIORITY 7
#define STM32_PWM_TIM5_IRQ_PRIORITY 7
#define STM32_PWM_TIM8_IRQ_PRIORITY 7
#define STM32_PWM_TIM9_IRQ_PRIORITY 7
#define STM32_PWM1_UP_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_PWM1_UP_DMA_CHANNEL 6
#define STM32_PWM1_UP_DMA_IRQ_PRIORITY 6
#define STM32_PWM1_UP_DMA_PRIORITY 2
/*
* SERIAL driver system settings.
*/
#if USE_UART1
#define STM32_SERIAL_USE_USART1 TRUE
#else
#define STM32_SERIAL_USE_USART1 FALSE
#endif
#if USE_UART2
#define STM32_SERIAL_USE_USART2 TRUE
#else
#define STM32_SERIAL_USE_USART2 FALSE
#endif
#if USE_UART3
#define STM32_SERIAL_USE_USART3 TRUE
#else
#define STM32_SERIAL_USE_USART3 FALSE
#endif
#if USE_UART4
#define STM32_SERIAL_USE_UART4 TRUE
#else
#define STM32_SERIAL_USE_UART4 FALSE
#endif
#if USE_UART5
#define STM32_SERIAL_USE_UART5 TRUE
#else
#define STM32_SERIAL_USE_UART5 FALSE
#endif
#if USE_UART6
#define STM32_SERIAL_USE_USART6 TRUE
#else
#define STM32_SERIAL_USE_USART6 FALSE
#endif
#if USE_UART7
#define STM32_SERIAL_USE_UART7 TRUE
#else
#define STM32_SERIAL_USE_UART7 FALSE
#endif
#if USE_UART8
#define STM32_SERIAL_USE_UART8 TRUE
#else
#define STM32_SERIAL_USE_UART8 FALSE
#endif
#define STM32_SERIAL_USART1_PRIORITY 12
#define STM32_SERIAL_USART2_PRIORITY 12
#define STM32_SERIAL_USART3_PRIORITY 12
#define STM32_SERIAL_UART4_PRIORITY 12
#define STM32_SERIAL_UART5_PRIORITY 12
#define STM32_SERIAL_USART6_PRIORITY 12
#define STM32_SERIAL_UART7_PRIORITY 12
#define STM32_SERIAL_UART8_PRIORITY 12
/*
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 FALSE
#if USE_SPI2
#define STM32_SPI_USE_SPI2 TRUE
#else
#define STM32_SPI_USE_SPI2 FALSE
#endif
#define STM32_SPI_USE_SPI3 FALSE
#define STM32_SPI_USE_SPI4 TRUE
#define STM32_SPI_USE_SPI5 FALSE
#define STM32_SPI_USE_SPI6 FALSE
//#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
//#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
//#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0)
//#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI4_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI4_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
//#define STM32_SPI_SPI5_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
//#define STM32_SPI_SPI5_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
//#define STM32_SPI_SPI6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
//#define STM32_SPI_SPI6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_SPI_SPI1_DMA_PRIORITY 1
#define STM32_SPI_SPI2_DMA_PRIORITY 1
#define STM32_SPI_SPI3_DMA_PRIORITY 1
#define STM32_SPI_SPI4_DMA_PRIORITY 1
#define STM32_SPI_SPI5_DMA_PRIORITY 1
#define STM32_SPI_SPI6_DMA_PRIORITY 1
#define STM32_SPI_SPI1_IRQ_PRIORITY 10
#define STM32_SPI_SPI2_IRQ_PRIORITY 10
#define STM32_SPI_SPI3_IRQ_PRIORITY 10
#define STM32_SPI_SPI4_IRQ_PRIORITY 10
#define STM32_SPI_SPI5_IRQ_PRIORITY 10
#define STM32_SPI_SPI6_IRQ_PRIORITY 10
#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure")
/*
* ST driver system settings.
*/
#define STM32_ST_IRQ_PRIORITY 8
#define STM32_ST_USE_TIMER 2
/*
* UART driver system settings.
*/
#define STM32_UART_USE_USART1 FALSE /* DMA OK */
#define STM32_UART_USE_USART2 FALSE /* NO DMA AVAIL */
#define STM32_UART_USE_USART3 FALSE /* DMA OK */
#define STM32_UART_USE_UART4 FALSE /* NO DMA AVAIL */
#define STM32_UART_USE_UART5 FALSE /* NO DMA AVAIL */
#define STM32_UART_USE_USART6 FALSE /* NO DMA AVAIL */
#define STM32_UART_USE_UART7 FALSE /* NO DMA AVAIL */
#define STM32_UART_USE_UART8 FALSE /* NO DMA AVAIL */
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7)
/* #define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) */
/* #define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) */
#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
/* #define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) */
/* #define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) */
/* #define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) */
/* #define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) */
/* #define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) */
/* #define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) */
/* #define STM32_UART_UART7_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) */
/* #define STM32_UART_UART7_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) */
/* #define STM32_UART_UART8_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) */
/* #define STM32_UART_UART8_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) */
#define STM32_UART_USART1_IRQ_PRIORITY 12
#define STM32_UART_USART2_IRQ_PRIORITY 12
#define STM32_UART_USART3_IRQ_PRIORITY 12
#define STM32_UART_UART4_IRQ_PRIORITY 12
#define STM32_UART_UART5_IRQ_PRIORITY 12
#define STM32_UART_USART6_IRQ_PRIORITY 12
#define STM32_UART_USART1_DMA_PRIORITY 0
#define STM32_UART_USART2_DMA_PRIORITY 0
#define STM32_UART_USART3_DMA_PRIORITY 0
#define STM32_UART_UART4_DMA_PRIORITY 0
#define STM32_UART_UART5_DMA_PRIORITY 0
#define STM32_UART_USART6_DMA_PRIORITY 0
#define STM32_UART_UART7_DMA_PRIORITY 0
#define STM32_UART_UART8_DMA_PRIORITY 0
#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure")
/*
* USB driver system settings.
*/
#define STM32_USB_USE_OTG1 TRUE
#define STM32_USB_USE_OTG2 FALSE
#define STM32_USB_OTG1_IRQ_PRIORITY 14
#define STM32_USB_OTG2_IRQ_PRIORITY 14
#define STM32_USB_OTG1_RX_FIFO_SIZE 512
#define STM32_USB_OTG2_RX_FIFO_SIZE 1024
#define STM32_USB_OTG_THREAD_PRIO LOWPRIO
#define STM32_USB_OTG_THREAD_STACK_SIZE 128
#define STM32_USB_OTGFIFO_FILL_BASEPRI 0
/*
* SDC driver system settings.
*/
#define STM32_SDC_USE_SDMMC1 TRUE
#define STM32_SDC_SDMMC_UNALIGNED_SUPPORT TRUE
#define STM32_SDC_SDMMC_WRITE_TIMEOUT 250
#define STM32_SDC_SDMMC_READ_TIMEOUT 25
#define STM32_SDC_SDMMC_CLOCK_DELAY 10
#define STM32_SDC_SDMMC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 6)
#define STM32_SDC_SDMMC1_DMA_PRIORITY 3
#define STM32_SDC_SDMMC1_IRQ_PRIORITY 9
/*
sdlog message buffer and queue configuration
*/
#define SDLOG_QUEUE_BUCKETS 1024
#define SDLOG_MAX_MESSAGE_LEN 300
#define SDLOG_NUM_FILES 2
#define SDLOG_ALL_BUFFERS_SIZE (SDLOG_NUM_FILES*16*1024)
/*
* WDG driver system settings.
*/
#define STM32_WDG_USE_IWDG FALSE
//#define CH_HEAP_SIZE (32*1024)
//#define CH_HEAP_USE_TLSF 1 // if 0 or undef, chAlloc will be used
#endif /* _MCUCONF_H_ */
sw/airborne/boards/tawaki/chibios/v1.0/tawaki.cfg
+139
View File
@@ -0,0 +1,139 @@
MCU_MODEL = STM32F777VIHx
CHIBIOS_VERSION = 3.0
HEADER
/*
* Board identifier.
*/
#define BOARD_TAWAKI
#define BOARD_NAME "Tawaki Autopilot"
/*
* Board oscillators-related settings.
*/
#if !defined(STM32_LSECLK)
#define STM32_LSECLK 32768U
#endif
#define STM32_LSEDRV (3U << 3U)
#if !defined(STM32_HSECLK)
#define STM32_HSECLK 16000000U
#endif
/*
* Board voltages.
* Required for performance limits calculation.
*/
#define STM32_VDD 300U
/*
* MCU type as defined in the ST header.
*/
#define STM32F777xx
CONFIG
# PIN NAME PERIPH_TYPE AF_NUMBER or
# PIN NAME FUNCTION PP_or_OPENDRAIN PIN_SPEED PULL_RESISTOR INITIAL_LEVEL AF_NUMBER
# SPEED : SPEED_VERYLOW, SPEED_LOW, SPEED_MEDIUM, SPEED_HIGH
#
# DEFAULT AND SYS
#
# 'SYS' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
# 'ADC' => ['ANALOG', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_LOW'],
# 'PWM' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_LOW'],
# 'ICU' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
# 'I2C' => ['ALTERNATE', 'OPENDRAIN', 'SPEED_HIGH', 'PULLUP', 'LEVEL_HIGH'],
# 'SPI' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
# 'UART' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'PULLUP', 'LEVEL_HIGH'],
# 'OTG' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
# 'ETH' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
# 'FSMC' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
# 'SDIO' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'PULLUP', 'LEVEL_HIGH'],
# 'SDIOCK' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
# 'CAN' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
# 'DCMI' => ['ALTERNATE', 'PUSHPULL', 'SPEED_HIGH', 'FLOATING', 'LEVEL_HIGH'],
# 'LED' => ['OUTPUT', 'PUSHPULL', 'SPEED_VERYLOW', 'FLOATING', 'LEVEL_LOW'],
# 'PASSIVE' => ['INPUT', 'PUSHPULL', 'SPEED_VERYLOW', 'FLOATING', 'LEVEL_LOW']);
#
# SYSTEM
A13 SWDIO SYS AF:SYS_JTMS-SWDIO
A14 SWCLK SYS AF:SYS_JTCK-SWCLK
C14 OSC32_IN SYS AF0
C15 OSC32_OUT SYS AF0
H00 OSC_IN SYS AF0
H01 OSC_OUT SYS AF0
#DEFAULT
DEFAULT INPUT PUSHPULL SPEED_VERYLOW PULLDOWN LEVEL_LOW AF0
# ACTIVE PINS
PA00 AUX_A1 PASSIVE #AF:USART2_CTS
PA01 AUX_A2 PASSIVE #AF:USART2_RTS
PA02 AUX_A3 PASSIVE #AF:TIM9_CH1
PA03 AUX_B1 PASSIVE #AF:TIM9_CH2
PA06 AUX_A4 PASSIVE #AF:TIM13_CH1
PA07 AUX_B2 PASSIVE #AF:TIM14_CH1
PA09 USB_VBUS INPUT PULLDOWN
PA10 LED2 LED
PA11 OTG_FS_DM OTG AF:USB_OTG_FS_DM
PA12 OTG_FS_DP OTG AF:USB_OTG_FS_DP
PA15 UART7_TX UART AF:UART7_TX
PB00 AUX_B3 PASSIVE
PB01 AUX_B4 PASSIVE
PB03 UART7_RX UART AF:UART7_RX
PB05 DSHOT_RX UART AF:UART5_RX
PB06 SRVB1 PWM AF:TIM4_CH1
PB07 SRVB2 PWM AF:TIM4_CH2
PB08 SRVB3 PWM AF:TIM4_CH3
PB09 SRVB4 PWM AF:TIM4_CH4
PB10 I2C2_SCL_EXTERNAL I2C AF:I2C2_SCL
PB11 I2C2_SDA_EXTERNAL I2C AF:I2C2_SDA
PB12 SPI2_CS_EXTERNAL OUTPUT PUSHPULL SPEED_HIGH FLOATING LEVEL_HIGH
PB14 SPI2_EXTERNAL_MISO SPI AF:SPI2_MISO
PB15 SPI2_EXTERNAL_MOSI SPI AF:SPI2_MOSI
PC00 VBAT_MEAS ADC ADC1_IN10
PC06 RC2 PASSIVE #TLMF_TX6 UART AF:USART6_TX
PC07 LED3 LED
PC08 SDMMC1_D0 SDIO AF:SDMMC1_D0
PC09 SDMMC1_D1 SDIO AF:SDMMC1_D1
PC10 SDMMC1_D2 SDIO AF:SDMMC1_D2
PC11 SDMMC1_D3 SDIO AF:SDMMC1_D3
PC12 SDMMC1_CK SDIO AF:SDMMC1_CK
PC13 APSW OUTPUT PUSHPULL SPEED_VERYLOW FLOATING LEVEL_HIGH
PD00 CAN_RX CAN AF:CAN1_RX
PD01 CAN_TX CAN AF:CAN1_TX
PD02 SDMMC1_CMD SDIO AF:SDMMC1_CMD
PD03 SPI2_EXTERNAL_CLK SPI AF:SPI2_SCK
PD05 UART_TX2 UART AF:USART2_TX
PD06 UART_RX2 UART AF:USART2_RX
PD08 UART_TX3 UART AF:USART3_TX
PD09 UART_RX3 UART AF:USART3_RX
PD10 LED4 LED
PD12 I2C4_SCL_EXTERNAL I2C AF:I2C4_SCL
PD13 I2C4_SDA_EXTERNAL I2C AF:I2C4_SDA
PD15 LED1 LED
PE00 RC1 UART AF:UART8_RX
PE02 SPI4_INTERNAL_CLK SPI AF:SPI4_SCK
PE04 SPI4_CS_INTERNAL OUTPUT PUSHPULL SPEED_HIGH FLOATING LEVEL_HIGH
PE05 SPI4_INTERNAL_MISO SPI AF:SPI4_MISO
PE06 SPI4_INTERNAL_MOSI SPI AF:SPI4_MOSI
PE09 SRVA1 PWM AF:TIM1_CH1
PE11 SRVA2 PWM AF:TIM1_CH2
PE13 SRVA3 PWM AF:TIM1_CH3
PE14 SRVA4 PWM AF:TIM1_CH4
sw/airborne/boards/tawaki/chibios/v1.0/tawaki.h
+609
View File
File diff suppressed because it is too large Load Diff
sw/airborne/mcu.c
+7 -1
View File
@@ -43,7 +43,7 @@
#define USING_UART 1
#include "mcu_periph/uart.h"
#endif
#if USE_I2C0 || USE_I2C1 || USE_I2C2 || USE_I2C3
#if USE_I2C0 || USE_I2C1 || USE_I2C2 || USE_I2C3 || USE_I2C4
#define USING_I2C 1
#include "mcu_periph/i2c.h"
#endif
@@ -173,6 +173,9 @@ void mcu_init(void)
#ifdef USE_I2C3
i2c3_init();
#endif
#ifdef USE_I2C4
i2c4_init();
#endif
#if USE_ADC
adc_init();
#endif
@@ -194,6 +197,9 @@ void mcu_init(void)
#endif
#if USE_SPI3
spi3_init();
#endif
#if USE_SPI4
spi4_init();
#endif
spi_init_slaves();
#endif // SPI_MASTER
sw/airborne/mcu_periph/i2c.c
+48
View File
@@ -206,6 +206,49 @@ static void send_i2c3_err(struct transport_tx *trans, struct link_device *dev)
#endif /* USE_I2C3 */
#if USE_I2C4
struct i2c_periph i2c4;
void i2c4_init(void)
{
i2c_init(&i2c4);
i2c4_hw_init();
}
#if PERIODIC_TELEMETRY
static void send_i2c4_err(struct transport_tx *trans, struct link_device *dev)
{
uint16_t i2c4_wd_reset_cnt = i2c4.errors->wd_reset_cnt;
uint16_t i2c4_queue_full_cnt = i2c4.errors->queue_full_cnt;
uint16_t i2c4_ack_fail_cnt = i2c4.errors->ack_fail_cnt;
uint16_t i2c4_miss_start_stop_cnt = i2c4.errors->miss_start_stop_cnt;
uint16_t i2c4_arb_lost_cnt = i2c4.errors->arb_lost_cnt;
uint16_t i2c4_over_under_cnt = i2c4.errors->over_under_cnt;
uint16_t i2c4_pec_recep_cnt = i2c4.errors->pec_recep_cnt;
uint16_t i2c4_timeout_tlow_cnt = i2c4.errors->timeout_tlow_cnt;
uint16_t i2c4_smbus_alert_cnt = i2c4.errors->smbus_alert_cnt;
uint16_t i2c4_unexpected_event_cnt = i2c4.errors->unexpected_event_cnt;
uint32_t i2c4_last_unexpected_event = i2c4.errors->last_unexpected_event;
uint8_t _bus4 = 4;
pprz_msg_send_I2C_ERRORS(trans, dev, AC_ID,
&i2c4_wd_reset_cnt,
&i2c4_queue_full_cnt,
&i2c4_ack_fail_cnt,
&i2c4_miss_start_stop_cnt,
&i2c4_arb_lost_cnt,
&i2c4_over_under_cnt,
&i2c4_pec_recep_cnt,
&i2c4_timeout_tlow_cnt,
&i2c4_smbus_alert_cnt,
&i2c4_unexpected_event_cnt,
&i2c4_last_unexpected_event,
&_bus4);
}
#endif
#endif /* USE_I2C4 */
#if PERIODIC_TELEMETRY
static void send_i2c_err(struct transport_tx *trans __attribute__((unused)),
struct link_device *dev __attribute__((unused)))
@@ -230,6 +273,11 @@ static void send_i2c_err(struct transport_tx *trans __attribute__((unused)),
case 3:
#if USE_I2C3
send_i2c3_err(trans, dev);
#endif
break;
case 4:
#if USE_I2C4
send_i2c4_err(trans, dev);
#endif
break;
default:
sw/airborne/mcu_periph/i2c.h
+8
View File
@@ -215,6 +215,14 @@ extern void i2c3_init(void);
#endif /* USE_I2C3 */
#if USE_I2C4
extern struct i2c_periph i2c4;
extern void i2c4_init(void);
#endif /* USE_I2C4 */
/** Initialize I2C peripheral */
extern void i2c_init(struct i2c_periph *p);
sw/airborne/mcu_periph/spi.c
+11
View File
@@ -75,6 +75,17 @@ void spi3_init(void)
#endif // USE_SPI3
#if USE_SPI4
struct spi_periph spi4;
void spi4_init(void)
{
spi_init(&spi4);
spi4_arch_init();
}
#endif // USE_SPI4
void spi_init(struct spi_periph *p)
{
p->trans_insert_idx = 0;
sw/airborne/mcu_periph/spi.h
+12
View File
@@ -241,6 +241,18 @@ extern void spi3_arch_init(void);
#endif // USE_SPI3
#if USE_SPI4
extern struct spi_periph spi4;
extern void spi4_init(void);
/** Architecture dependent SPI4 initialization.
* Must be implemented by underlying architecture
*/
extern void spi4_arch_init(void);
#endif // USE_SPI4
/** Initialize a spi peripheral.
* @param p spi peripheral to be configured
*/
sw/airborne/modules/sensors/baro_bmp3.c
+2 -1
View File
@@ -56,8 +56,9 @@ void baro_bmp3_event(void)
bmp3_i2c_event(&baro_bmp3);
if (baro_bmp3.data_available) {
uint32_t now_ts = get_sys_time_usec();
// send ABI message
AbiSendMsgBARO_ABS(BARO_BMP3_SENDER_ID, baro_bmp3.pressure);
AbiSendMsgBARO_ABS(BARO_BMP3_SENDER_ID, now_ts, baro_bmp3.pressure);
AbiSendMsgTEMPERATURE(BARO_BMP3_SENDER_ID, baro_bmp3.temperature);
baro_bmp3.data_available = false;
sw/airborne/peripherals/mpu60x0.c
+16
View File
@@ -59,9 +59,11 @@ const int32_t MPU60X0_ACCEL_SENS_FRAC[4][2] = {
void mpu60x0_set_default_config(struct Mpu60x0Config *c)
{
c->type = MPU60X0;
c->clk_sel = MPU60X0_DEFAULT_CLK_SEL;
c->smplrt_div = MPU60X0_DEFAULT_SMPLRT_DIV;
c->dlpf_cfg = MPU60X0_DEFAULT_DLPF_CFG;
c->dlpf_cfg_acc = MPU60X0_DEFAULT_DLPF_CFG_ACC;
c->gyro_range = MPU60X0_DEFAULT_FS_SEL;
c->accel_range = MPU60X0_DEFAULT_AFS_SEL;
c->drdy_int_enable = false;
@@ -117,6 +119,13 @@ void mpu60x0_send_config(Mpu60x0ConfigSet mpu_set, void *mpu, struct Mpu60x0Conf
mpu_set(mpu, MPU60X0_REG_ACCEL_CONFIG, (config->accel_range << 3));
config->init_status++;
break;
case MPU60X0_CONF_ACCEL2:
/* configure accelerometer DLPF (for ICM devices) */
if (config->type != MPU60X0) {
mpu_set(mpu, MPU60X0_REG_ACCEL_CONFIG2, config->dlpf_cfg_acc);
}
config->init_status++;
break;
case MPU60X0_CONF_I2C_SLAVES:
/* if any, set MPU for I2C slaves and configure them*/
if (config->nb_slaves > 0) {
@@ -133,6 +142,13 @@ void mpu60x0_send_config(Mpu60x0ConfigSet mpu_set, void *mpu, struct Mpu60x0Conf
mpu_set(mpu, MPU60X0_REG_INT_ENABLE, (config->drdy_int_enable << 0));
config->init_status++;
break;
case MPU60X0_CONF_UNDOC1:
/* configure undocumented register (for ICM devices) to remove 2.7m/s^2 y-acc bias */
if (config->type != MPU60X0) {
mpu_set(mpu, MPU60X0_REG_UNDOC1, 0xC9);
}
config->init_status++;
break;
case MPU60X0_CONF_DONE:
config->initialized = true;
break;
sw/airborne/peripherals/mpu60x0.h
+18 -2
View File
@@ -39,8 +39,10 @@
#define MPU60X0_DEFAULT_FS_SEL MPU60X0_GYRO_RANGE_2000
/// Default accel full scale range +- 16g
#define MPU60X0_DEFAULT_AFS_SEL MPU60X0_ACCEL_RANGE_16G
/// Default internal sampling (1kHz, 42Hz LP Bandwidth)
#define MPU60X0_DEFAULT_DLPF_CFG MPU60X0_DLPF_42HZ
/// Default internal sampling (1kHz, 98Hz LP Bandwidth)
#define MPU60X0_DEFAULT_DLPF_CFG MPU60X0_DLPF_98HZ
/// Default internal sampling for accelerometer ICM devices only (1kHz, 99Hz LP Bandwidth)
#define MPU60X0_DEFAULT_DLPF_CFG_ACC MPU60X0_DLPF_ACC_99HZ
/// Default interrupt config: DATA_RDY_EN
#define MPU60X0_DEFAULT_INT_CFG 1
/// Default clock: PLL with X gyro reference
@@ -97,6 +99,16 @@ extern const float MPU60X0_ACCEL_SENS[4];
// Get default sensitivity numerator and denominator from a table
extern const int32_t MPU60X0_ACCEL_SENS_FRAC[4][2];
/** MPU60x0 sensor type
*/
enum Mpu60x0Type {
MPU60X0,
ICM20600,
ICM20608,
ICM20602,
ICM20689
};
enum Mpu60x0ConfStatus {
MPU60X0_CONF_UNINIT,
MPU60X0_CONF_RESET,
@@ -106,8 +118,10 @@ enum Mpu60x0ConfStatus {
MPU60X0_CONF_DLPF,
MPU60X0_CONF_GYRO,
MPU60X0_CONF_ACCEL,
MPU60X0_CONF_ACCEL2,
MPU60X0_CONF_I2C_SLAVES,
MPU60X0_CONF_INT_ENABLE,
MPU60X0_CONF_UNDOC1,
MPU60X0_CONF_DONE
};
@@ -122,8 +136,10 @@ struct Mpu60x0I2cSlave {
};
struct Mpu60x0Config {
enum Mpu60x0Type type; ///< The type of sensor (MPU60x0, ICM20608, ...)
uint8_t smplrt_div; ///< Sample rate divider
enum Mpu60x0DLPF dlpf_cfg; ///< Digital Low Pass Filter
enum Mpu60x0ACCDLPF dlpf_cfg_acc; ///< Digital Low Pass Filter for acceleremoter (ICM devices only)
enum Mpu60x0GyroRanges gyro_range; ///< deg/s Range
enum Mpu60x0AccelRanges accel_range; ///< g Range
bool drdy_int_enable; ///< Enable Data Ready Interrupt
sw/airborne/peripherals/mpu60x0_regs.h
+26 -10
View File
@@ -43,14 +43,16 @@
// FIFO
#define MPU60X0_REG_FIFO_EN 0x23
#define MPU60X0_REG_FIFO_COUNT_H 0x72
#define MPU60X0_REG_FIFO_COUNT_L 0x73
#define MPU60X0_REG_FIFO_R_W 0x74
#define MPU60X0_REG_FIFO_COUNT_L 0x73
#define MPU60X0_REG_FIFO_R_W 0x74
// Measurement Settings
#define MPU60X0_REG_SMPLRT_DIV 0x19
#define MPU60X0_REG_CONFIG 0x1A
#define MPU60X0_REG_GYRO_CONFIG 0x1B
#define MPU60X0_REG_ACCEL_CONFIG 0x1C
#define MPU60X0_REG_ACCEL_CONFIG2 0x1D
#define MPU60X0_REG_UNDOC1 0x11
// I2C Slave settings
#define MPU60X0_REG_I2C_MST_CTRL 0x24
@@ -112,13 +114,13 @@
#define MPU60X0_EXT_SENS_DATA 0x49
#define MPU60X0_EXT_SENS_DATA_SIZE 24
// Different sensor WHOAMI replies
#define MPU60X0_REG_WHO_AM_I 0x75
#ifdef ICM20608
#define MPU60X0_WHOAMI_REPLY 0xAF
#else
#define MPU60X0_WHOAMI_REPLY 0x68
#endif
#define MPU60X0_WHOAMI_REPLY 0x68
#define ICM20600_WHOAMI_REPLY 0x11
#define ICM20608_WHOAMI_REPLY 0xAF
#define ICM20602_WHOAMI_REPLY 0x12
#define ICM20689_WHOAMI_REPLY 0x98
// Bit positions
#define MPU60X0_I2C_BYPASS_EN 1
@@ -128,14 +130,14 @@
#define MPU60X0_I2C_MST_RESET 1
#define MPU60X0_FIFO_RESET 2
#define MPU60X0_I2C_IF_DIS 4
#define MPU60X0_I2C_MST_EN 5
#define MPU60X0_I2C_MST_EN 5
#define MPU60X0_FIFO_EN 6
// in MPU60X0_REG_I2C_MST_STATUS
#define MPU60X0_I2C_SLV4_DONE 6
/** Digital Low Pass Filter Options
* DLFP is affecting both gyro and accels,
* DLFP is affecting both gyro and accels (on MPU not ICM),
* with slightly different bandwidth
*/
enum Mpu60x0DLPF {
@@ -148,6 +150,20 @@ enum Mpu60x0DLPF {
MPU60X0_DLPF_05HZ = 0x6
};
/** Digital Low Pass Filter Options
* DLFP specifically for the ICM device accelerometer
*/
enum Mpu60x0ACCDLPF {
MPU60X0_DLPF_ACC_1046HZ = 0x0, // internal sampling rate 4kHz
MPU60X0_DLPF_ACC_218HZ = 0x1, // internal sampling rate 1kHz
MPU60X0_DLPF_ACC_99HZ = 0x2,
MPU60X0_DLPF_ACC_44HZ = 0x3,
MPU60X0_DLPF_ACC_21HZ = 0x4,
MPU60X0_DLPF_ACC_10HZ = 0x5,
MPU60X0_DLPF_ACC_05HZ = 0x6,
MPU60X0_DLPF_ACC_420HZ = 0x7
};
/**
* Selectable gyro range
*/
sw/airborne/peripherals/mpu60x0_spi.c
+25 -7
View File
@@ -79,13 +79,31 @@ void mpu60x0_spi_start_configure(struct Mpu60x0_Spi *mpu)
if (mpu->config.init_status == MPU60X0_CONF_UNINIT) {
// First check if we found the chip (succesfull WHO_AM_I response)
if(mpu->spi_trans.status == SPITransSuccess && mpu->rx_buf[1] == MPU60X0_WHOAMI_REPLY) {
if (mpu->spi_trans.status == SPITransSuccess &&
(mpu->rx_buf[1] == MPU60X0_WHOAMI_REPLY ||
mpu->rx_buf[1] == ICM20600_WHOAMI_REPLY ||
mpu->rx_buf[1] == ICM20608_WHOAMI_REPLY ||
mpu->rx_buf[1] == ICM20602_WHOAMI_REPLY ||
mpu->rx_buf[1] == ICM20689_WHOAMI_REPLY)) {
if (mpu->rx_buf[1] == MPU60X0_WHOAMI_REPLY) {
mpu->config.type = MPU60X0;
} else if (mpu->rx_buf[1] == ICM20600_WHOAMI_REPLY) {
mpu->config.type = ICM20600;
} else if (mpu->rx_buf[1] == ICM20608_WHOAMI_REPLY) {
mpu->config.type = ICM20608;
} else if (mpu->rx_buf[1] == ICM20602_WHOAMI_REPLY) {
mpu->config.type = ICM20602;
} else if (mpu->rx_buf[1] == ICM20689_WHOAMI_REPLY) {
mpu->config.type = ICM20689;
}
mpu->config.init_status++;
mpu->spi_trans.status = SPITransDone;
mpu60x0_send_config(mpu60x0_spi_write_to_reg, (void *)mpu, &(mpu->config));
}
// Send WHO_AM_I to check if chip is there
else if(mpu->spi_trans.status != SPITransRunning && mpu->spi_trans.status != SPITransPending) {
else if (mpu->spi_trans.status != SPITransRunning && mpu->spi_trans.status != SPITransPending) {
mpu->spi_trans.output_length = 1;
mpu->spi_trans.input_length = 2;
mpu->tx_buf[0] = MPU60X0_REG_WHO_AM_I | MPU60X0_SPI_READ;
@@ -124,11 +142,11 @@ void mpu60x0_spi_event(struct Mpu60x0_Spi *mpu)
mpu->data_rates.rates.r = Int16FromBuf(mpu->rx_buf, 14);
int16_t temp_raw = Int16FromBuf(mpu->rx_buf, 8);
#if ICM20608
mpu->temp = (float)temp_raw / 326.8f + 25.0f;
#else
mpu->temp = (float)temp_raw / 340.0f + 36.53f;
#endif
if (mpu->config.type == MPU60X0) {
mpu->temp = (float)temp_raw / 361.0f + 35.0f;
} else {
mpu->temp = (float)temp_raw / 326.8f + 25.0f;
}
// if we are reading slaves, copy the ext_sens_data
if (mpu->config.nb_slaves > 0) {
sw/airborne/subsystems/imu/imu_mpu6000.c
+67 -5
View File
@@ -1,5 +1,6 @@
/*
* Copyright (C) 2013-2015 Felix Ruess <felix.ruess@gmail.com>
* Copyright (C) 2019 Gautier Hattenberger <gautier.hattenberger@enac.fr>
*
* This file is part of paparazzi.
*
@@ -35,30 +36,72 @@ PRINT_CONFIG_VAR(IMU_MPU_SPI_DEV)
/* MPU60x0 gyro/accel internal lowpass frequency */
#if !defined IMU_MPU_LOWPASS_FILTER && !defined IMU_MPU_SMPLRT_DIV
#if (PERIODIC_FREQUENCY == 60) || (PERIODIC_FREQUENCY == 120)
#if (PERIODIC_FREQUENCY >= 60) && (PERIODIC_FREQUENCY <= 120)
/* Accelerometer: Bandwidth 44Hz, Delay 4.9ms
* Gyroscope: Bandwidth 42Hz, Delay 4.8ms sampling 1kHz
*/
#define IMU_MPU_LOWPASS_FILTER MPU60X0_DLPF_42HZ
#define IMU_MPU_SMPLRT_DIV 9
PRINT_CONFIG_MSG("Gyro/Accel output rate is 100Hz at 1kHz internal sampling")
#elif PERIODIC_FREQUENCY == 512
#ifndef IMU_MPU_ACCEL_LOWPASS_FILTER
#define IMU_MPU_ACCEL_LOWPASS_FILTER MPU60X0_DLPF_ACC_44HZ // for ICM sensors
#endif
#elif (PERIODIC_FREQUENCY == 512) || (PERIODIC_FREQUENCY == 500)
/* Accelerometer: Bandwidth 260Hz, Delay 0ms
* Gyroscope: Bandwidth 256Hz, Delay 0.98ms sampling 8kHz
*/
#define IMU_MPU_LOWPASS_FILTER MPU60X0_DLPF_256HZ
#define IMU_MPU_SMPLRT_DIV 3
PRINT_CONFIG_MSG("Gyro/Accel output rate is 2kHz at 8kHz internal sampling")
#ifndef IMU_MPU_ACCEL_LOWPASS_FILTER
#define IMU_MPU_ACCEL_LOWPASS_FILTER MPU60X0_DLPF_ACC_218HZ // for ICM sensors
#endif
#else
#error Non-default PERIODIC_FREQUENCY: please define IMU_MPU_LOWPASS_FILTER and IMU_MPU_SMPLRT_DIV.
/* By default, don't go too fast */
#define IMU_MPU_LOWPASS_FILTER MPU60X0_DLPF_42HZ
#define IMU_MPU_SMPLRT_DIV 9
PRINT_CONFIG_MSG("Gyro/Accel output rate is 100Hz at 1kHz internal sampling")
#ifndef IMU_MPU_ACCEL_LOWPASS_FILTER
#define IMU_MPU_ACCEL_LOWPASS_FILTER MPU60X0_DLPF_ACC_44HZ // for ICM sensors
#endif
INFO("Non-default PERIODIC_FREQUENCY: using default IMU_MPU_LOWPASS_FILTER and IMU_MPU_SMPLRT_DIV.")
#endif
#endif
PRINT_CONFIG_VAR(IMU_MPU_LOWPASS_FILTER)
PRINT_CONFIG_VAR(IMU_MPU_ACCEL_LOWPASS_FILTER)
PRINT_CONFIG_VAR(IMU_MPU_SMPLRT_DIV)
PRINT_CONFIG_VAR(IMU_MPU_GYRO_RANGE)
PRINT_CONFIG_VAR(IMU_MPU_ACCEL_RANGE)
// Default channels order
#ifndef IMU_MPU_CHAN_X
#define IMU_MPU_CHAN_X 0
#endif
PRINT_CONFIG_VAR(IMU_MPU_CHAN_X)
#ifndef IMU_MPU_CHAN_Y
#define IMU_MPU_CHAN_Y 1
#endif
PRINT_CONFIG_VAR(IMU_MPU_CHAN_Y)
#ifndef IMU_MPU_CHAN_Z
#define IMU_MPU_CHAN_Z 2
#endif
PRINT_CONFIG_VAR(IMU_MPU_CHAN_Z)
// Default channel signs
#ifndef IMU_MPU_X_SIGN
#define IMU_MPU_X_SIGN 1
#endif
PRINT_CONFIG_VAR(IMU_MPU_X_SIGN)
#ifndef IMU_MPU_Y_SIGN
#define IMU_MPU_Y_SIGN 1
#endif
PRINT_CONFIG_VAR(IMU_MPU_Y_SIGN)
#ifndef IMU_MPU_Z_SIGN
#define IMU_MPU_Z_SIGN 1
#endif
PRINT_CONFIG_VAR(IMU_MPU_Z_SIGN)
struct ImuMpu6000 imu_mpu_spi;
@@ -68,6 +111,7 @@ void imu_mpu_spi_init(void)
// change the default configuration
imu_mpu_spi.mpu.config.smplrt_div = IMU_MPU_SMPLRT_DIV;
imu_mpu_spi.mpu.config.dlpf_cfg = IMU_MPU_LOWPASS_FILTER;
imu_mpu_spi.mpu.config.dlpf_cfg_acc = IMU_MPU_ACCEL_LOWPASS_FILTER; // only for ICM sensors
imu_mpu_spi.mpu.config.gyro_range = IMU_MPU_GYRO_RANGE;
imu_mpu_spi.mpu.config.accel_range = IMU_MPU_ACCEL_RANGE;
}
@@ -83,11 +127,29 @@ void imu_mpu_spi_event(void)
mpu60x0_spi_event(&imu_mpu_spi.mpu);
if (imu_mpu_spi.mpu.data_available) {
uint32_t now_ts = get_sys_time_usec();
RATES_COPY(imu.gyro_unscaled, imu_mpu_spi.mpu.data_rates.rates);
VECT3_COPY(imu.accel_unscaled, imu_mpu_spi.mpu.data_accel.vect);
// set channel order
struct Int32Vect3 accel = {
IMU_MPU_X_SIGN * (int32_t)(imu_mpu_spi.mpu.data_accel.value[IMU_MPU_CHAN_X]),
IMU_MPU_Y_SIGN * (int32_t)(imu_mpu_spi.mpu.data_accel.value[IMU_MPU_CHAN_Y]),
IMU_MPU_Z_SIGN * (int32_t)(imu_mpu_spi.mpu.data_accel.value[IMU_MPU_CHAN_Z])
};
struct Int32Rates rates = {
IMU_MPU_X_SIGN * (int32_t)(imu_mpu_spi.mpu.data_rates.value[IMU_MPU_CHAN_X]),
IMU_MPU_Y_SIGN * (int32_t)(imu_mpu_spi.mpu.data_rates.value[IMU_MPU_CHAN_Y]),
IMU_MPU_Z_SIGN * (int32_t)(imu_mpu_spi.mpu.data_rates.value[IMU_MPU_CHAN_Z])
};
// unscaled vector
VECT3_COPY(imu.accel_unscaled, accel);
RATES_COPY(imu.gyro_unscaled, rates);
imu_mpu_spi.mpu.data_available = false;
// Scale the gyro and accelerometer
imu_scale_gyro(&imu);
imu_scale_accel(&imu);
// Send the scaled values over ABI
AbiSendMsgIMU_GYRO_INT32(IMU_MPU6000_ID, now_ts, &imu.gyro);
AbiSendMsgIMU_ACCEL_INT32(IMU_MPU6000_ID, now_ts, &imu.accel);
}