diff --git a/conf/Makefile.chibios b/conf/Makefile.chibios index 0956171b1b..adf754cb52 100644 --- a/conf/Makefile.chibios +++ b/conf/Makefile.chibios @@ -23,14 +23,35 @@ # This is the common Makefile for target using chibios # # chibios directory -CHIBIOS = $(PAPARAZZI_SRC)/sw/ext/chibios +CHIBIOS = $(PAPARAZZI_SRC)/sw/ext/chibios # directory with board defines for chibios platforms (board specific) BOARD_DIR ?= $(BOARD)/chibios CHIBIOS_BOARD_DIR = $(PAPARAZZI_SRC)/sw/airborne/boards/$(BOARD_DIR) -# chibos arch directory -CHIBIOS_ARCH_DIR = $(PAPARAZZI_SRC)/sw/airborne/arch/chibios +# chibos linker scripts directory +# to keep backwards compatibility with Luftboot (Lia/Lisa M) +# and possibly other bootloaders (like PX4 bootloader) +# we need to keep a separate linker script with a memory offset +# because it is not possible to pass it dynamicaly to the linker +# hence we have two destinations for linker scripts +CHIBIOS_BOOTLOADER_SCRIPT = +# check if we used 1 to define presence of luftboot +ifeq ($(HAS_LUFTBOOT),1) + CHIBIOS_BOOTLOADER_SCRIPT = 1 +endif +# check if we used TRUE to define presence of luftboot +ifeq ($(HAS_LUFTBOOT),TRUE) + CHIBIOS_BOOTLOADER_SCRIPT = 1 +endif + +ifdef CHIBIOS_BOOTLOADER_SCRIPT +# we use the modified linker script +CHIBIOS_LINKER_DIR ?= $(PAPARAZZI_SRC)/sw/airborne/arch/chibios/ +else +# we use the original linker script +CHIBIOS_LINKER_DIR ?= $(CHIBIOS)/os/common/ports/ARMCMx/compilers/GCC/ld +endif # Launch with "make Q=''" to get full command display Q=@ @@ -39,7 +60,7 @@ Q=@ RTOS_DEBUG ?= 0 ifeq (,$(findstring $(RTOS_DEBUG),0 FALSE)) -$(info DEBUGGING ON) +$(info ChibiOS Debug mode is ON) $(TARGET).CFLAGS += \ -DCH_DBG_STATISTICS=TRUE \ -DCH_DBG_SYSTEM_STATE_CHECK=TRUE \ @@ -50,7 +71,6 @@ $(TARGET).CFLAGS += \ -DCH_DBG_FILL_THREADS=TRUE \ -DCH_DBG_THREADS_PROFILING=TRUE else -$(info DEBUGGING OFF) $(TARGET).CFLAGS += -DCH_DBG_THREADS_PROFILING=TRUE endif @@ -184,8 +204,7 @@ include $(PAPARAZZI_HOME)/conf/chibios/fatfs.mk endif # Define linker script file here -LDSCRIPT= $(CHIBIOS_ARCH_DIR)/$(CHIBIOS_BOARD_LINKER) -#LDSCRIPT= $(STARTUPLD)/$(CHIBIOS_BOARD_LINKER) +LDSCRIPT= $(CHIBIOS_LINKER_DIR)/$(CHIBIOS_BOARD_LINKER) # C sources that can be compiled in ARM or THUMB mode depending on the global # setting. @@ -285,7 +304,7 @@ CPPWARN = -Wall -Wextra UDEFS = $($(TARGET).CFLAGS) $(USER_CFLAGS) $(BOARD_CFLAGS) # Define ASM defines here -UADEFS = +UADEFS = $($(TARGET).CFLAGS) $(USER_CFLAGS) $(BOARD_CFLAGS) # List all user directories here # remove -I before include dir because ChibiOS is adding them again @@ -316,7 +335,6 @@ endif # Settings for GDB # default port configuration for BMP -BMP_PORT = /dev/ttyACM0 GDB = $(shell which arm-none-eabi-gdb) diff --git a/conf/boards/apogee_1.0_chibios.makefile b/conf/boards/apogee_1.0_chibios.makefile index 24bac874ea..7154251544 100644 --- a/conf/boards/apogee_1.0_chibios.makefile +++ b/conf/boards/apogee_1.0_chibios.makefile @@ -14,7 +14,7 @@ $(TARGET).ARCHDIR = $(ARCH) RTOS=chibios -## FPU on F4 +# FPU on F4 USE_FPU=yes HARD_FLOAT=yes @@ -28,8 +28,7 @@ PROJECT = $(TARGET) # Project specific files and paths (see Makefile.chibios for details) CHIBIOS_BOARD_PLATFORM = STM32F4xx/platform.mk -CHIBIOS_BOARD_PORT = ARMCMx/STM32F4xx/port.mk -CHIBIOS_BOARD_LINKER = STM32F407xG_ccm.ld +CHIBIOS_BOARD_LINKER = STM32F407xG.ld CHIBIOS_BOARD_STARTUP = startup_stm32f4xx.mk ############################################################################## diff --git a/conf/boards/lia_1.1_chibios.makefile b/conf/boards/lia_1.1_chibios.makefile new file mode 100644 index 0000000000..805f1d3629 --- /dev/null +++ b/conf/boards/lia_1.1_chibios.makefile @@ -0,0 +1,41 @@ +# Hey Emacs, this is a -*- makefile -*- +# +# Lia_1.1_chibios.makefile +# +# + +BOARD=lia +BOARD_VERSION=1.1 + +# +# default LED configuration +# +RADIO_CONTROL_LED ?= 4 +BARO_LED ?= none +AHRS_ALIGNER_LED ?= 2 +GPS_LED ?= 3 +SYS_TIME_LED ?= 1 + +# +# default uart configuration +# +RADIO_CONTROL_SPEKTRUM_PRIMARY_PORT ?= UART1 +RADIO_CONTROL_SPEKTRUM_SECONDARY_PORT ?= UART5 + +MODEM_PORT ?= UART2 +MODEM_BAUD ?= B57600 + +GPS_PORT ?= UART3 +GPS_BAUD ?= B38400 + +# +# default actuator configuration +# +# you can use different actuators by adding a configure option to your firmware section +# e.g. +# +ACTUATORS ?= actuators_pwm + +include $(PAPARAZZI_SRC)/conf/boards/lisa_m_common_chibios.makefile diff --git a/conf/boards/lisa_m_2.0.makefile b/conf/boards/lisa_m_2.0.makefile index 812b9f2f22..44f467ba1f 100644 --- a/conf/boards/lisa_m_2.0.makefile +++ b/conf/boards/lisa_m_2.0.makefile @@ -7,74 +7,6 @@ BOARD=lisa_m BOARD_VERSION=2.0 -BOARD_CFG=\"boards/$(BOARD)_$(BOARD_VERSION).h\" -ARCH=stm32 -$(TARGET).ARCHDIR = $(ARCH) -# not needed? -$(TARGET).OOCD_INTERFACE=flossjtag -#$(TARGET).OOCD_INTERFACE=jtagkey-tiny -$(TARGET).LDSCRIPT=$(SRC_ARCH)/lisa-m.ld - -# ----------------------------------------------------------------------- - -# default flash mode is via usb dfu bootloader (luftboot) -# other possibilities: DFU-UTIL, JTAG, SWD, STLINK, SERIAL -FLASH_MODE ?= DFU - -HAS_LUFTBOOT ?= 1 -ifeq (,$(findstring $(HAS_LUFTBOOT),0 FALSE)) -$(TARGET).CFLAGS+=-DLUFTBOOT -$(TARGET).LDFLAGS+=-Wl,-Ttext=0x8002000 -endif - -# -# -# some default values shared between different firmwares -# -# - - -# -# default LED configuration -# -RADIO_CONTROL_LED ?= 4 -BARO_LED ?= none -AHRS_ALIGNER_LED ?= 2 -GPS_LED ?= 3 -SYS_TIME_LED ?= 1 - - -# -# default uart configuration -# -RADIO_CONTROL_SPEKTRUM_PRIMARY_PORT ?= UART1 -RADIO_CONTROL_SPEKTRUM_SECONDARY_PORT ?= UART5 - -MODEM_PORT ?= UART2 -MODEM_BAUD ?= B57600 - -GPS_PORT ?= UART3 -GPS_BAUD ?= B38400 - -# -# default PPM input is on PA01 (SERVO6) -# -RADIO_CONTROL_PPM_PIN ?= PA01 -ifeq ($(RADIO_CONTROL_PPM_PIN),$(filter $(RADIO_CONTROL_PPM_PIN),PA_10 PA10 UART1_RX)) - PPM_CONFIG=1 -else ifeq ($(RADIO_CONTROL_PPM_PIN),$(filter $(RADIO_CONTROL_PPM_PIN),PA_01 PA01 PA1 SERVO6)) - PPM_CONFIG=2 -else -$(error Unknown RADIO_CONTROL_PPM_PIN, configure it to either PA01 or PA10) -endif - -# -# default actuator configuration -# -# you can use different actuators by adding a configure option to your firmware section -# e.g. -# -ACTUATORS ?= actuators_pwm +include $(PAPARAZZI_SRC)/conf/boards/lisa_m_defaults.makefile +include $(PAPARAZZI_SRC)/conf/boards/lisa_m_common.makefile diff --git a/conf/boards/lisa_m_2.0_chibios.makefile b/conf/boards/lisa_m_2.0_chibios.makefile new file mode 100644 index 0000000000..14dab95c94 --- /dev/null +++ b/conf/boards/lisa_m_2.0_chibios.makefile @@ -0,0 +1,23 @@ +# Hey Emacs, this is a -*- makefile -*- +# +# Lisa_m_2.0_chibios.makefile +# +# + +BOARD=lisa_m +BOARD_VERSION=2.0 + +# +# default PPM input is on PA01 (SERVO6) +# +RADIO_CONTROL_PPM_PIN ?= PA01 +ifeq ($(RADIO_CONTROL_PPM_PIN),$(filter $(RADIO_CONTROL_PPM_PIN),PA_10 PA10 UART1_RX)) + PPM_CONFIG=1 +else ifeq ($(RADIO_CONTROL_PPM_PIN),$(filter $(RADIO_CONTROL_PPM_PIN),PA_01 PA01 PA1 SERVO6)) + PPM_CONFIG=2 +else +$(error Unknown RADIO_CONTROL_PPM_PIN, configure it to either PA01 or PA10) +endif + +include $(PAPARAZZI_SRC)/conf/boards/lisa_m_defaults.makefile +include $(PAPARAZZI_SRC)/conf/boards/lisa_m_common_chibios.makefile diff --git a/conf/boards/lisa_m_2.1.makefile b/conf/boards/lisa_m_2.1.makefile index 019604e68d..78ece7d72e 100644 --- a/conf/boards/lisa_m_2.1.makefile +++ b/conf/boards/lisa_m_2.1.makefile @@ -7,74 +7,6 @@ BOARD=lisa_m BOARD_VERSION=2.1 -BOARD_CFG=\"boards/$(BOARD)_$(BOARD_VERSION).h\" -ARCH=stm32 -$(TARGET).ARCHDIR = $(ARCH) -# not needed? -$(TARGET).OOCD_INTERFACE=flossjtag -#$(TARGET).OOCD_INTERFACE=jtagkey-tiny -$(TARGET).LDSCRIPT=$(SRC_ARCH)/lisa-m.ld - -# ----------------------------------------------------------------------- - -# default flash mode is via usb dfu bootloader (luftboot) -# other possibilities: DFU-UTIL, JTAG, SWD, STLINK, SERIAL -FLASH_MODE ?= DFU - -HAS_LUFTBOOT ?= 1 -ifeq (,$(findstring $(HAS_LUFTBOOT),0 FALSE)) -$(TARGET).CFLAGS+=-DLUFTBOOT -$(TARGET).LDFLAGS+=-Wl,-Ttext=0x8002000 -endif - -# -# -# some default values shared between different firmwares -# -# - - -# -# default LED configuration -# -RADIO_CONTROL_LED ?= 4 -BARO_LED ?= none -AHRS_ALIGNER_LED ?= 2 -GPS_LED ?= 3 -SYS_TIME_LED ?= 1 - - -# -# default uart configuration -# -RADIO_CONTROL_SPEKTRUM_PRIMARY_PORT ?= UART1 -RADIO_CONTROL_SPEKTRUM_SECONDARY_PORT ?= UART5 - -MODEM_PORT ?= UART2 -MODEM_BAUD ?= B57600 - -GPS_PORT ?= UART3 -GPS_BAUD ?= B38400 - -# -# default PPM input is on PA01 (SERVO6) -# -RADIO_CONTROL_PPM_PIN ?= PA01 -ifeq ($(RADIO_CONTROL_PPM_PIN),$(filter $(RADIO_CONTROL_PPM_PIN),PA_10 PA10 UART1_RX)) - PPM_CONFIG=1 -else ifeq ($(RADIO_CONTROL_PPM_PIN),$(filter $(RADIO_CONTROL_PPM_PIN),PA_01 PA01 PA1 SERVO6)) - PPM_CONFIG=2 -else -$(error Unknown RADIO_CONTROL_PPM_PIN, configure it to either PA01 or PA10) -endif - -# -# default actuator configuration -# -# you can use different actuators by adding a configure option to your firmware section -# e.g. -# -ACTUATORS ?= actuators_pwm +include $(PAPARAZZI_SRC)/conf/boards/lisa_m_defaults.makefile +include $(PAPARAZZI_SRC)/conf/boards/lisa_m_common.makefile diff --git a/conf/boards/lisa_m_2.1_chibios.makefile b/conf/boards/lisa_m_2.1_chibios.makefile new file mode 100644 index 0000000000..34c37956f5 --- /dev/null +++ b/conf/boards/lisa_m_2.1_chibios.makefile @@ -0,0 +1,11 @@ +# Hey Emacs, this is a -*- makefile -*- +# +# Lisa_m_2.1_chibios.makefile +# +# + +BOARD=lisa_m +BOARD_VERSION=2.1 + +include $(PAPARAZZI_SRC)/conf/boards/lisa_m_common_chibios.makefile +include $(PAPARAZZI_SRC)/conf/boards/lisa_m_defaults.makefile diff --git a/conf/boards/lisa_m_common.makefile b/conf/boards/lisa_m_common.makefile new file mode 100644 index 0000000000..9fc1dda84a --- /dev/null +++ b/conf/boards/lisa_m_common.makefile @@ -0,0 +1,76 @@ +# Hey Emacs, this is a -*- makefile -*- +# + # Common makefile defines for Lia 1.1, Lisa M 2.0, and Lisa M 2.1 +# + +BOARD_CFG=\"boards/$(BOARD)_$(BOARD_VERSION).h\" + +ARCH=stm32 +$(TARGET).ARCHDIR = $(ARCH) +# not needed? +$(TARGET).OOCD_INTERFACE=flossjtag +#$(TARGET).OOCD_INTERFACE=jtagkey-tiny +$(TARGET).LDSCRIPT=$(SRC_ARCH)/lisa-m.ld + +# ----------------------------------------------------------------------- + +# default flash mode is via usb dfu bootloader (luftboot) +# other possibilities: DFU-UTIL, JTAG, SWD, STLINK, SERIAL +FLASH_MODE ?= DFU + +HAS_LUFTBOOT ?= 1 +ifeq (,$(findstring $(HAS_LUFTBOOT),0 FALSE)) +$(TARGET).CFLAGS+=-DLUFTBOOT +$(TARGET).LDFLAGS+=-Wl,-Ttext=0x8002000 +endif + +# +# +# some default values shared between different firmwares +# +# + + +# +# default LED configuration +# +RADIO_CONTROL_LED ?= 4 +BARO_LED ?= none +AHRS_ALIGNER_LED ?= 2 +GPS_LED ?= 3 +SYS_TIME_LED ?= 1 + + +# +# default uart configuration +# +RADIO_CONTROL_SPEKTRUM_PRIMARY_PORT ?= UART1 +RADIO_CONTROL_SPEKTRUM_SECONDARY_PORT ?= UART5 + +MODEM_PORT ?= UART2 +MODEM_BAUD ?= B57600 + +GPS_PORT ?= UART3 +GPS_BAUD ?= B38400 + +# +# default PPM input is on PA01 (SERVO6) +# +RADIO_CONTROL_PPM_PIN ?= PA01 +ifeq ($(RADIO_CONTROL_PPM_PIN),$(filter $(RADIO_CONTROL_PPM_PIN),PA_10 PA10 UART1_RX)) + PPM_CONFIG=1 +else ifeq ($(RADIO_CONTROL_PPM_PIN),$(filter $(RADIO_CONTROL_PPM_PIN),PA_01 PA01 PA1 SERVO6)) + PPM_CONFIG=2 +else +$(error Unknown RADIO_CONTROL_PPM_PIN, configure it to either PA01 or PA10) +endif + +# +# default actuator configuration +# +# you can use different actuators by adding a configure option to your firmware section +# e.g. +# +ACTUATORS ?= actuators_pwm diff --git a/conf/boards/lisa_m_common_chibios.makefile b/conf/boards/lisa_m_common_chibios.makefile new file mode 100644 index 0000000000..97c9515a79 --- /dev/null +++ b/conf/boards/lisa_m_common_chibios.makefile @@ -0,0 +1,46 @@ +# Hey Emacs, this is a -*- makefile -*- +# +# Common makefile defines for Lia 1.1, Lisa M 2.0, and Lisa M 2.1 +# (ChibiOS version) +# +BOARD_DIR=$(BOARD)/chibios/v$(BOARD_VERSION) +BOARD_CFG=\"boards/$(BOARD_DIR)/board.h\" + +ARCH=chibios +$(TARGET).ARCHDIR = $(ARCH) + +RTOS=chibios + +# FPU not present on F1 +USE_FPU=no +HARD_FLOAT=no + +$(TARGET).CFLAGS += -DSTM32F1 -DPPRZLINK_ENABLE_FD + +############################################################################## +# Architecture or project specific options +# +# Define project name here (target) +PROJECT = $(TARGET) + +# Project specific files and paths (see Makefile.chibios for details) +CHIBIOS_BOARD_PLATFORM = STM32F1xx/platform.mk +# CHIBIOS_BOARD_LINKER script depends on whether we use a bootloader or not, see below +CHIBIOS_BOARD_STARTUP = startup_stm32f1xx.mk + +############################################################################## +# Compiler settings +# +MCU = cortex-m3 + +# default flash mode is via usb dfu bootloader (luftboot) +# other possibilities: DFU-UTIL, JTAG, SWD, STLINK, SERIAL +FLASH_MODE ?= DFU + +HAS_LUFTBOOT ?= 1 +ifeq (,$(findstring $(HAS_LUFTBOOT),0 FALSE)) +$(TARGET).CFLAGS+=-DLUFTBOOT -DCORTEX_VTOR_INIT=0x00002000 +CHIBIOS_BOARD_LINKER = STM32F107xC_luftboot.ld +else +CHIBIOS_BOARD_LINKER = STM32F107xC.ld +endif diff --git a/conf/boards/lisa_m_defaults.makefile b/conf/boards/lisa_m_defaults.makefile new file mode 100644 index 0000000000..7c54d2dc0c --- /dev/null +++ b/conf/boards/lisa_m_defaults.makefile @@ -0,0 +1,36 @@ +# Hey Emacs, this is a -*- makefile -*- +# +# Defaults for Lia 1.1, Lisa M 2.0, and Lisa M 2.1 +# + +# +# default LED configuration +# +RADIO_CONTROL_LED ?= 4 +BARO_LED ?= none +AHRS_ALIGNER_LED ?= 2 +GPS_LED ?= 3 +SYS_TIME_LED ?= 1 + +# +# default uart configuration +# +RADIO_CONTROL_SPEKTRUM_PRIMARY_PORT ?= UART1 +RADIO_CONTROL_SPEKTRUM_SECONDARY_PORT ?= UART5 + +MODEM_PORT ?= UART2 +MODEM_BAUD ?= B57600 + +GPS_PORT ?= UART3 +GPS_BAUD ?= B38400 + +# +# default actuator configuration +# +# you can use different actuators by adding a configure option to your firmware section +# e.g. +# +ACTUATORS ?= actuators_pwm + diff --git a/conf/boards/lisa_mx_2.0.makefile b/conf/boards/lisa_mx_2.0.makefile index ce2ec0fd6d..09c835a200 100644 --- a/conf/boards/lisa_mx_2.0.makefile +++ b/conf/boards/lisa_mx_2.0.makefile @@ -17,10 +17,6 @@ $(TARGET).LDSCRIPT=$(SRC_ARCH)/lisa-mx.ld # ----------------------------------------------------------------------- -# default flash mode is via usb dfu bootloader (luftboot) -# other possibilities: DFU-UTIL, SWD, JTAG_BMP, STLINK, SERIAL -FLASH_MODE ?= SWD - HAS_LUFTBOOT ?= 0 ifeq (,$(findstring $(HAS_LUFTBOOT),0 FALSE)) $(TARGET).CFLAGS+=-DLUFTBOOT @@ -29,47 +25,4 @@ DFU_ADDR = 0x8004000 DFU_PRODUCT = Lisa/Lia endif - -# -# default LED configuration -# -RADIO_CONTROL_LED ?= 4 -BARO_LED ?= none -AHRS_ALIGNER_LED ?= 2 -GPS_LED ?= 3 -SYS_TIME_LED ?= 1 - - -# -# default uart configuration -# -RADIO_CONTROL_SPEKTRUM_PRIMARY_PORT ?= UART1 -RADIO_CONTROL_SPEKTRUM_SECONDARY_PORT ?= UART5 - -MODEM_PORT ?= UART2 -MODEM_BAUD ?= B57600 - -GPS_PORT ?= UART3 -GPS_BAUD ?= B38400 - -# -# default PPM input is on PA01 (SERVO6) -# -RADIO_CONTROL_PPM_PIN ?= PA01 -ifeq ($(RADIO_CONTROL_PPM_PIN),$(filter $(RADIO_CONTROL_PPM_PIN),PA_10 PA10 UART1_RX)) - PPM_CONFIG=1 -else ifeq ($(RADIO_CONTROL_PPM_PIN),$(filter $(RADIO_CONTROL_PPM_PIN),PA_01 PA01 PA1 SERVO6)) - PPM_CONFIG=2 -else -$(error Unknown RADIO_CONTROL_PPM_PIN, configure it to either PA01 or PA10) -endif - -# -# default actuator configuration -# -# you can use different actuators by adding a configure option to your firmware section -# e.g. -# -ACTUATORS ?= actuators_pwm +include $(PAPARAZZI_SRC)/conf/boards/lisa_m_defaults.makefile diff --git a/conf/boards/lisa_mx_2.1.makefile b/conf/boards/lisa_mx_2.1.makefile index 568ad562f0..c4c409ded7 100644 --- a/conf/boards/lisa_mx_2.1.makefile +++ b/conf/boards/lisa_mx_2.1.makefile @@ -17,10 +17,6 @@ $(TARGET).LDSCRIPT=$(SRC_ARCH)/lisa-mx.ld # ----------------------------------------------------------------------- -# default flash mode is via usb dfu bootloader (luftboot) -# other possibilities: DFU-UTIL, SWD, JTAG_BMP, STLINK, SERIAL -FLASH_MODE ?= SWD - HAS_LUFTBOOT ?= 0 ifeq (,$(findstring $(HAS_LUFTBOOT),0 FALSE)) $(TARGET).CFLAGS+=-DLUFTBOOT @@ -29,47 +25,4 @@ DFU_ADDR = 0x8004000 DFU_PRODUCT = Lisa/Lia endif - -# -# default LED configuration -# -RADIO_CONTROL_LED ?= 4 -BARO_LED ?= none -AHRS_ALIGNER_LED ?= 2 -GPS_LED ?= 3 -SYS_TIME_LED ?= 1 - - -# -# default uart configuration -# -RADIO_CONTROL_SPEKTRUM_PRIMARY_PORT ?= UART1 -RADIO_CONTROL_SPEKTRUM_SECONDARY_PORT ?= UART5 - -MODEM_PORT ?= UART2 -MODEM_BAUD ?= B57600 - -GPS_PORT ?= UART3 -GPS_BAUD ?= B38400 - -# -# default PPM input is on PA01 (SERVO6) -# -RADIO_CONTROL_PPM_PIN ?= PA01 -ifeq ($(RADIO_CONTROL_PPM_PIN),$(filter $(RADIO_CONTROL_PPM_PIN),PA_10 PA10 UART1_RX)) - PPM_CONFIG=1 -else ifeq ($(RADIO_CONTROL_PPM_PIN),$(filter $(RADIO_CONTROL_PPM_PIN),PA_01 PA01 PA1 SERVO6)) - PPM_CONFIG=2 -else -$(error Unknown RADIO_CONTROL_PPM_PIN, configure it to either PA01 or PA10) -endif - -# -# default actuator configuration -# -# you can use different actuators by adding a configure option to your firmware section -# e.g. -# -ACTUATORS ?= actuators_pwm +include $(PAPARAZZI_SRC)/conf/boards/lisa_m_defaults.makefile diff --git a/conf/boards/lisa_mx_2.1_chibios.makefile b/conf/boards/lisa_mx_2.1_chibios.makefile index ddacf2fa6d..48a697923d 100644 --- a/conf/boards/lisa_mx_2.1_chibios.makefile +++ b/conf/boards/lisa_mx_2.1_chibios.makefile @@ -14,7 +14,7 @@ $(TARGET).ARCHDIR = $(ARCH) RTOS=chibios -## FPU on F4 +# FPU on F4 USE_FPU=yes HARD_FLOAT=yes @@ -28,8 +28,7 @@ PROJECT = $(TARGET) # Project specific files and paths (see Makefile.chibios for details) CHIBIOS_BOARD_PLATFORM = STM32F4xx/platform.mk -CHIBIOS_BOARD_PORT = ARMCMx/STM32F4xx/port.mk -CHIBIOS_BOARD_LINKER = STM32F407xG_ccm.ld +CHIBIOS_BOARD_LINKER = STM32F407xG.ld CHIBIOS_BOARD_STARTUP = startup_stm32f4xx.mk ############################################################################## @@ -37,41 +36,6 @@ CHIBIOS_BOARD_STARTUP = startup_stm32f4xx.mk # MCU = cortex-m4 -# default flash mode is via usb dfu bootloader -# possibilities: DFU-UTIL, SWD, STLINK -FLASH_MODE ?= SWD - HAS_LUFTBOOT = FALSE -# -# default LED configuration -# -RADIO_CONTROL_LED ?= 4 -BARO_LED ?= none -AHRS_ALIGNER_LED ?= 2 -GPS_LED ?= 3 -SYS_TIME_LED ?= 1 - -# -# default UART configuration (modem, gps, spektrum) -# - -RADIO_CONTROL_SPEKTRUM_PRIMARY_PORT ?= UART1 -RADIO_CONTROL_SPEKTRUM_SECONDARY_PORT ?= UART5 - -MODEM_PORT ?= UART2 -MODEM_BAUD ?= B57600 - -GPS_PORT ?= UART3 -GPS_BAUD ?= B38400 - -# -# default actuator configuration -# -# you can use different actuators by adding a configure option to your firmware section -# e.g. -# -ACTUATORS ?= actuators_pwm - +include $(PAPARAZZI_SRC)/conf/boards/lisa_mx_defaults.makefile diff --git a/conf/boards/lisa_mx_defaults.makefile b/conf/boards/lisa_mx_defaults.makefile new file mode 100644 index 0000000000..205a35ce08 --- /dev/null +++ b/conf/boards/lisa_mx_defaults.makefile @@ -0,0 +1,54 @@ +# Hey Emacs, this is a -*- makefile -*- +# +# lisa_mx_defaults.makefile +# +# http://wiki.paparazziuav.org/wiki/Lisa/M_v20 +# + +# default flash mode is via usb dfu bootloader +# possibilities: DFU-UTIL, SWD, STLINK +FLASH_MODE ?= SWD + +# +# default LED configuration +# +RADIO_CONTROL_LED ?= 4 +BARO_LED ?= none +AHRS_ALIGNER_LED ?= 2 +GPS_LED ?= 3 +SYS_TIME_LED ?= 1 + + +# +# default uart configuration +# +RADIO_CONTROL_SPEKTRUM_PRIMARY_PORT ?= UART1 +RADIO_CONTROL_SPEKTRUM_SECONDARY_PORT ?= UART5 + +MODEM_PORT ?= UART2 +MODEM_BAUD ?= B57600 + +GPS_PORT ?= UART3 +GPS_BAUD ?= B38400 + +# +# default PPM input is on PA01 (SERVO6) +# +RADIO_CONTROL_PPM_PIN ?= PA01 +ifeq ($(RADIO_CONTROL_PPM_PIN),$(filter $(RADIO_CONTROL_PPM_PIN),PA_10 PA10 UART1_RX)) + PPM_CONFIG=1 +else ifeq ($(RADIO_CONTROL_PPM_PIN),$(filter $(RADIO_CONTROL_PPM_PIN),PA_01 PA01 PA1 SERVO6)) + PPM_CONFIG=2 +else +$(error Unknown RADIO_CONTROL_PPM_PIN, configure it to either PA01 or PA10) +endif + +# +# default actuator configuration +# +# you can use different actuators by adding a configure option to your firmware section +# e.g. +# +ACTUATORS ?= actuators_pwm diff --git a/conf/boards/px4fmu_2.4_chibios.makefile b/conf/boards/px4fmu_2.4_chibios.makefile new file mode 100644 index 0000000000..6f91816a8a --- /dev/null +++ b/conf/boards/px4fmu_2.4_chibios.makefile @@ -0,0 +1,79 @@ +# Hey Emacs, this is a -*- makefile -*- +# +# px4fmu_2.4.makefile +# +# This is for the main MCU (STM32F427) on the PX4 board +# See https://pixhawk.org/modules/pixhawk for details +# + +BOARD=px4fmu +BOARD_VERSION=2.4 +BOARD_DIR=$(BOARD)/chibios/v$(BOARD_VERSION) +BOARD_CFG=\"boards/$(BOARD_DIR)/board.h\" + +ARCH=chibios +$(TARGET).ARCHDIR = $(ARCH) + +RTOS=chibios + +# FPU on F4 +USE_FPU=yes +HARD_FLOAT=yes + +$(TARGET).CFLAGS += -DSTM32F4 -DPPRZLINK_ENABLE_FD + +############################################################################## +# Architecture or project specific options +# +# Define project name here (target) +PROJECT = $(TARGET) + +# Project specific files and paths (see Makefile.chibios for details) +CHIBIOS_BOARD_PLATFORM = STM32F4xx/platform.mk +CHIBIOS_BOARD_LINKER = STM32F407xG.ld +CHIBIOS_BOARD_STARTUP = startup_stm32f4xx.mk + +############################################################################## +# Compiler settings +# +MCU = cortex-m4 + +# default flash mode is the PX4 bootloader +# possibilities: DFU, SWD, PX4 bootloader +FLASH_MODE ?= PX4_BOOTLOADER +PX4_TARGET = "ap" +PX4_PROTOTYPE ?= "${PAPARAZZI_HOME}/sw/tools/px4/px4fmu-v2.prototype" +PX4_BL_PORT ?= "/dev/serial/by-id/usb-3D_Robotics*,/dev/serial/by-id/pci-3D_Robotics*" + + +# +# default LED configuration +# +RADIO_CONTROL_LED ?= none +BARO_LED ?= none +AHRS_ALIGNER_LED ?= none +GPS_LED ?= none +SYS_TIME_LED ?= 1 + +# +# default UART configuration (modem, gps, spektrum) +# + +#The modem serial on px4 is called serial 1, but connected to uart2 on the f4 +MODEM_PORT ?= UART2 +MODEM_BAUD ?= B57600 + +#The GPS serial on px4 is called serial 3, but connected to uart4 on the f4 +GPS_PORT ?= UART4 +GPS_BAUD ?= B38400 + +# +# default actuator configuration +# +# you can use different actuators by adding a configure option to your firmware section +# e.g. +# +ACTUATORS ?= actuators_pwm + diff --git a/conf/boards/vms_ecu_1.0_chibios.makefile b/conf/boards/vms_ecu_1.0_chibios.makefile new file mode 100644 index 0000000000..9b3ec51ffa --- /dev/null +++ b/conf/boards/vms_ecu_1.0_chibios.makefile @@ -0,0 +1,77 @@ +# Hey Emacs, this is a -*- makefile -*- +# +# VMS_ECU_1.0_chibios.makefile +# +# + +BOARD=vms_ecu +BOARD_VERSION=1.0 +BOARD_DIR=$(BOARD)/chibios/v$(BOARD_VERSION) +BOARD_CFG=\"boards/$(BOARD_DIR)/board.h\" + +ARCH=chibios +$(TARGET).ARCHDIR = $(ARCH) + +RTOS=chibios + +# FPU on F4 +USE_FPU=yes +HARD_FLOAT=yes + +$(TARGET).CFLAGS += -DSTM32F4 -DPPRZLINK_ENABLE_FD + +############################################################################## +# Architecture or project specific options +# +# Define project name here (target) +PROJECT = $(TARGET) + +# Project specific files and paths (see Makefile.chibios for details) +CHIBIOS_BOARD_PLATFORM = STM32F4xx/platform.mk +CHIBIOS_BOARD_LINKER = STM32F407xG.ld +CHIBIOS_BOARD_STARTUP = startup_stm32f4xx.mk + +############################################################################## +# Compiler settings +# +MCU = cortex-m4 + +# default flash mode is via usb dfu bootloader +# possibilities: DFU-UTIL, SWD, STLINK +FLASH_MODE ?= SWD + +HAS_LUFTBOOT = FALSE + +# +# default LED configuration +# +RADIO_CONTROL_LED ?= none +BARO_LED ?= none +AHRS_ALIGNER_LED ?= none +GPS_LED ?= none +SYS_TIME_LED ?= none + +# +# default UART configuration (modem, gps, spektrum) +# + +RADIO_CONTROL_SPEKTRUM_PRIMARY_PORT ?= UART2 + +MODEM_PORT ?= UART2 +MODEM_BAUD ?= B57600 + +GPS_PORT ?= UART6 +GPS_BAUD ?= B38400 + +SBUS_PORT ?= UART5 + +# +# default actuator configuration +# +# you can use different actuators by adding a configure option to your firmware section +# e.g. +# +ACTUATORS ?= actuators_pwm + diff --git a/conf/flash_modes.xml b/conf/flash_modes.xml index 91fc675c4c..57ba383740 100644 --- a/conf/flash_modes.xml +++ b/conf/flash_modes.xml @@ -47,6 +47,7 @@ + @@ -86,6 +87,7 @@ + diff --git a/sw/airborne/arch/chibios/STM32F407xG_ccm.ld b/sw/airborne/arch/chibios/STM32F107xC_luftboot.ld similarity index 52% rename from sw/airborne/arch/chibios/STM32F407xG_ccm.ld rename to sw/airborne/arch/chibios/STM32F107xC_luftboot.ld index 82815c9e66..d6e900613f 100644 --- a/sw/airborne/arch/chibios/STM32F407xG_ccm.ld +++ b/sw/airborne/arch/chibios/STM32F107xC_luftboot.ld @@ -1,85 +1,50 @@ -/* - ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio - - Licensed under the Apache License, Version 2.0 (the "License"); - you may not use this file except in compliance with the License. - You may obtain a copy of the License at - - http://www.apache.org/licenses/LICENSE-2.0 - - Unless required by applicable law or agreed to in writing, software - distributed under the License is distributed on an "AS IS" BASIS, - WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. - See the License for the specific language governing permissions and - limitations under the License. -*/ - -/* - * STM32F407xG memory setup. - * Note: Use of ram1 and ram2 is mutually exclusive with use of ram0. - */ -MEMORY -{ - flash : org = 0x08000000, len = 1M - ram0 : org = 0x20000000, len = 128k /* SRAM1 + SRAM2 */ - ram1 : org = 0x20000000, len = 112k /* SRAM1 */ - ram2 : org = 0x2001C000, len = 16k /* SRAM2 */ - ram3 : org = 0x00000000, len = 0 - ram4 : org = 0x10000000, len = 64k /* CCM SRAM */ - ccmram : org = 0x10000000, len = 64k /* CCM SRAM */ - ram5 : org = 0x40024000, len = 4k /* BCKP SRAM */ - ram6 : org = 0x00000000, len = 0 - ram7 : org = 0x00000000, len = 0 -} - - -/* RAM region to be used for Main stack. This stack accommodates the processing - of all exceptions and interrupts*/ -REGION_ALIAS("MAIN_STACK_RAM", ram0); - -/* RAM region to be used for the process stack. This is the stack used by - the main() function.*/ -REGION_ALIAS("PROCESS_STACK_RAM", ram0); - -/* RAM region to be used for data segment.*/ -REGION_ALIAS("DATA_RAM", ram0); - -/* RAM region to be used for BSS segment.*/ -REGION_ALIAS("BSS_RAM", ram0); - -/* RAM region to be used for the default heap.*/ -REGION_ALIAS("HEAP_RAM", ram0); - -__ccmram_start__ = ORIGIN(ccmram); -__ccmram_size__ = LENGTH(ccmram); -__ccmram_end__ = __ccmram_start__ + __ccmram_size__; - -SECTIONS -{ - .ccmram_init : ALIGN(4) - { - . = ALIGN(4); - __ccmram_init_text__ = LOADADDR(.ccmram_init); - __ccmram_init__ = .; - *(.ccmram_init) - *(.ccmram_init.*) - . = ALIGN(4); - } > ccmram AT > flash - - .ccmram (NOLOAD) : ALIGN(4) - { - . = ALIGN(4); - __ccmram_clear__ = .; - *(.ccmram_clear) - *(.ccmram_clear.*) - . = ALIGN(4); - __ccmram_noinit__ = .; - *(.ccmram) - *(.ccmram.*) - . = ALIGN(4); - __ccmram_free__ = .; - } > ccmram - -} - -INCLUDE rules.ld +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * ST32F107xC memory setup. + */ +MEMORY +{ + flash : org = 0x08002000, len = 256k + ram0 : org = 0x20000000, len = 64k + ram1 : org = 0x00000000, len = 0 + ram2 : org = 0x00000000, len = 0 + ram3 : org = 0x00000000, len = 0 + ram4 : org = 0x00000000, len = 0 + ram5 : org = 0x00000000, len = 0 + ram6 : org = 0x00000000, len = 0 + ram7 : org = 0x00000000, len = 0 +} + +/* RAM region to be used for Main stack. This stack accommodates the processing + of all exceptions and interrupts*/ +REGION_ALIAS("MAIN_STACK_RAM", ram0); + +/* RAM region to be used for the process stack. This is the stack used by + the main() function.*/ +REGION_ALIAS("PROCESS_STACK_RAM", ram0); + +/* RAM region to be used for data segment.*/ +REGION_ALIAS("DATA_RAM", ram0); + +/* RAM region to be used for BSS segment.*/ +REGION_ALIAS("BSS_RAM", ram0); + +/* RAM region to be used for the default heap.*/ +REGION_ALIAS("HEAP_RAM", ram0); + +INCLUDE rules.ld diff --git a/sw/airborne/arch/chibios/STM32F407xG.ld b/sw/airborne/arch/chibios/STM32F407xG.ld deleted file mode 100644 index c8d6466fc8..0000000000 --- a/sw/airborne/arch/chibios/STM32F407xG.ld +++ /dev/null @@ -1,162 +0,0 @@ -/* - ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010, - 2011,2012,2013 Giovanni Di Sirio. - - This file is part of ChibiOS/RT. - - ChibiOS/RT is free software; you can redistribute it and/or modify - it under the terms of the GNU General Public License as published by - the Free Software Foundation; either version 3 of the License, or - (at your option) any later version. - - ChibiOS/RT is distributed in the hope that it will be useful, - but WITHOUT ANY WARRANTY; without even the implied warranty of - MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - GNU General Public License for more details. - - You should have received a copy of the GNU General Public License - along with this program. If not, see . - - --- - - A special exception to the GPL can be applied should you wish to distribute - a combined work that includes ChibiOS/RT, without being obliged to provide - the source code for any proprietary components. See the file exception.txt - for full details of how and when the exception can be applied. -*/ - -/* - * ST32F407xG memory setup. - */ -__main_stack_size__ = 0x0400; -__process_stack_size__ = 0x0400; - -MEMORY -{ - flash : org = 0x08004000, len = 1M - ram : org = 0x20000000, len = 112k - ethram : org = 0x2001C000, len = 16k - ccmram : org = 0x10000000, len = 64k -} - -__ram_start__ = ORIGIN(ram); -__ram_size__ = LENGTH(ram); -__ram_end__ = __ram_start__ + __ram_size__; - -ENTRY(ResetHandler) - -SECTIONS -{ - . = 0; - _text = .; - - startup : ALIGN(16) SUBALIGN(16) - { - KEEP(*(vectors)) - } > flash - - constructors : ALIGN(4) SUBALIGN(4) - { - PROVIDE(__init_array_start = .); - KEEP(*(SORT(.init_array.*))) - KEEP(*(.init_array)) - PROVIDE(__init_array_end = .); - } > flash - - destructors : ALIGN(4) SUBALIGN(4) - { - PROVIDE(__fini_array_start = .); - KEEP(*(.fini_array)) - KEEP(*(SORT(.fini_array.*))) - PROVIDE(__fini_array_end = .); - } > flash - - .text : ALIGN(16) SUBALIGN(16) - { - *(.text.startup.*) - *(.text) - *(.text.*) - *(.rodata) - *(.rodata.*) - *(.glue_7t) - *(.glue_7) - *(.gcc*) - } > flash - - .ARM.extab : - { - *(.ARM.extab* .gnu.linkonce.armextab.*) - } > flash - - .ARM.exidx : { - PROVIDE(__exidx_start = .); - *(.ARM.exidx* .gnu.linkonce.armexidx.*) - PROVIDE(__exidx_end = .); - } > flash - - .eh_frame_hdr : - { - *(.eh_frame_hdr) - } > flash - - .eh_frame : ONLY_IF_RO - { - *(.eh_frame) - } > flash - - .textalign : ONLY_IF_RO - { - . = ALIGN(8); - } > flash - - . = ALIGN(4); - _etext = .; - _textdata = _etext; - - .stacks : - { - . = ALIGN(8); - __main_stack_base__ = .; - . += __main_stack_size__; - . = ALIGN(8); - __main_stack_end__ = .; - __process_stack_base__ = .; - __main_thread_stack_base__ = .; - . += __process_stack_size__; - . = ALIGN(8); - __process_stack_end__ = .; - __main_thread_stack_end__ = .; - } > ram - - .data : - { - . = ALIGN(4); - PROVIDE(_data = .); - *(.data) - . = ALIGN(4); - *(.data.*) - . = ALIGN(4); - *(.ramtext) - . = ALIGN(4); - PROVIDE(_edata = .); - } > ram AT > flash - - .bss : - { - . = ALIGN(4); - PROVIDE(_bss_start = .); - *(.bss) - . = ALIGN(4); - *(.bss.*) - . = ALIGN(4); - *(COMMON) - . = ALIGN(4); - PROVIDE(_bss_end = .); - } > ram -} - -PROVIDE(end = .); -_end = .; - -__heap_base__ = _end; -__heap_end__ = __ram_end__; diff --git a/sw/airborne/arch/chibios/mcu_arch.c b/sw/airborne/arch/chibios/mcu_arch.c index d90653ed6c..dd0bd17baf 100644 --- a/sw/airborne/arch/chibios/mcu_arch.c +++ b/sw/airborne/arch/chibios/mcu_arch.c @@ -90,18 +90,13 @@ bool recovering_from_hard_fault; /* * SCB_VTOR has to be relocated if Luftboot is used + * The new SCB_VTOR location is defined in the board makefile */ void mcu_arch_init(void) { #if LUFTBOOT PRINT_CONFIG_MSG("We are running luftboot, the interrupt vector is being relocated.") -#if defined STM32F4 - PRINT_CONFIG_MSG("STM32F4") - SCB_VTOR = 0x00004000; -#else - PRINT_CONFIG_MSG("STM32F1") - SCB_VTOR = 0x00002000; -#endif + SCB->VTOR = CORTEX_VTOR_INIT; #endif /* @@ -120,7 +115,7 @@ void mcu_arch_init(void) RCC->AHB1ENR |= RCC_AHB1ENR_BKPSRAMEN; PWR->CSR |= PWR_CSR_BRE; while ((PWR->CSR & PWR_CSR_BRR) == 0) ; /* Waits until the regulator is stable */ -#endif +#endif /* STM32F4 */ // test if last reset was a 'real' hard fault recovering_from_hard_fault = false; @@ -138,7 +133,7 @@ void mcu_arch_init(void) // *MANDATORY* clear of rcc bits RCC->CSR = RCC_CSR_RMVF; // end of reset bit probing -#endif +#endif /* USE_HARD_FAULT_RECOVERY */ } diff --git a/sw/airborne/arch/chibios/mcu_periph/adc_arch.c b/sw/airborne/arch/chibios/mcu_periph/adc_arch.c index bc6e2cf32a..d6044054f0 100644 --- a/sw/airborne/arch/chibios/mcu_periph/adc_arch.c +++ b/sw/airborne/arch/chibios/mcu_periph/adc_arch.c @@ -55,11 +55,8 @@ #include "hal.h" #include "std.h" -// From active ADC channels -//#define ADC_NUM_CHANNELS NB_ADC // Macros to automatically enable the correct ADC - // FIXME we can't use NB_ADC1_CHANNELS it is not a macro //#if NB_ADC1_CHANNELS != 0 #ifndef USE_AD1 @@ -67,6 +64,19 @@ #endif ///#endif + +// architecture dependent settings +#if defined(__STM32F10x_H) || defined(__STM32F105xC_H) || defined (__STM32F107xC_H) +// STM32F1xx +#define ADC_SAMPLE_RATE ADC_SAMPLE_41P5 +#define ADC_CR2_CFG ADC_CR2_TSVREFE +#elif defined(__STM32F4xx_H) +// STM32F4xx +#define ADC_SAMPLE_RATE ADC_SAMPLE_480 +#define ADC_CR2_CFG ADC_CR2_SWSTART +#endif // STM32F1xx vs STM32F4xx + + // Create channel map static const uint8_t adc_channel_map[ADC_NUM_CHANNELS] = { #ifdef AD1_1_CHANNEL @@ -326,21 +336,14 @@ void adc_init(void) gpio_setup_pin_analog(ADC_9_GPIO_PORT, ADC_9_GPIO_PIN); #endif - // Configurtion register + // Configuration register uint32_t sqr1, sqr2, sqr3; adc_regular_sequence(&sqr1, &sqr2, &sqr3, ADC_NUM_CHANNELS, adc_channel_map); -#ifdef __STM32F10x_H uint32_t smpr1, smpr2; - adc_sample_time_on_all_channels(&smpr1, &smpr2, ADC_SAMPLE_41P5); + adc_sample_time_on_all_channels(&smpr1, &smpr2, ADC_SAMPLE_RATE); - adcgrpcfg.cr2 = ADC_CR2_TSVREFE; -#elif defined(__STM32F4xx_H) - uint32_t smpr1, smpr2; - adc_sample_time_on_all_channels(&smpr1, &smpr2, ADC_SAMPLE_480); - - adcgrpcfg.cr2 = ADC_CR2_SWSTART; -#endif + adcgrpcfg.cr2 = ADC_CR2_CFG; #if USE_ADC_WATCHDOG adc_watchdog.adc = NULL; diff --git a/sw/airborne/arch/chibios/mcu_periph/gpio_arch.c b/sw/airborne/arch/chibios/mcu_periph/gpio_arch.c index 3a787a9182..39c5678f53 100644 --- a/sw/airborne/arch/chibios/mcu_periph/gpio_arch.c +++ b/sw/airborne/arch/chibios/mcu_periph/gpio_arch.c @@ -61,7 +61,18 @@ void gpio_setup_input_pulldown(ioportid_t port, uint16_t gpios) void gpio_setup_pin_af(ioportid_t port, uint16_t pin, uint8_t af) { chSysLock(); +// architecture dependent settings +#if defined(__STM32F10x_H) || defined(__STM32F105xC_H) || defined (__STM32F107xC_H) +// STM32F1xx +// FIXME: STM32F1xx doesn't support several alternate modes, is it needed for drivers? + (void)port; + (void)pin; + (void)af; +#elif defined(__STM32F4xx_H) +// STM32F4xx palSetPadMode(port, pin, PAL_MODE_ALTERNATE(af)); +#endif // STM32F1xx vs STM32F4xx + chSysUnlock(); } diff --git a/sw/airborne/arch/chibios/mcu_periph/spi_arch.c b/sw/airborne/arch/chibios/mcu_periph/spi_arch.c index e695fa462d..6e6e7b7876 100644 --- a/sw/airborne/arch/chibios/mcu_periph/spi_arch.c +++ b/sw/airborne/arch/chibios/mcu_periph/spi_arch.c @@ -148,7 +148,7 @@ static inline uint16_t spi_resolve_slave_pin(uint8_t slave) static inline uint16_t spi_resolve_CR1(struct spi_transaction *t) { uint16_t CR1 = 0; -#if defined(__STM32F10x_H) || defined(__STM32F4xx_H) +#if defined(__STM32F10x_H) || defined(__STM32F105xC_H) || defined (__STM32F107xC_H) || defined(__STM32F4xx_H) if (t->dss == SPIDss16bit) { CR1 |= SPI_CR1_DFF; } @@ -189,7 +189,7 @@ static inline uint16_t spi_resolve_CR1(struct spi_transaction *t) default: break; } -#endif /* STM32F10x_H || STM32F4xx_H */ +#endif /* __STM32F10x_H || __STM32F105xC_H || __STM32F107xC_H || STM32F4xx_H */ return CR1; } diff --git a/sw/airborne/arch/stm32/px4fmu_2.4.ld b/sw/airborne/arch/stm32/px4fmu_2.4.ld index e7158dbb88..2d31823fb8 100644 --- a/sw/airborne/arch/stm32/px4fmu_2.4.ld +++ b/sw/airborne/arch/stm32/px4fmu_2.4.ld @@ -25,7 +25,7 @@ MEMORY { ram (rwx) : ORIGIN = 0x20000000, LENGTH = 192K - /* Pixhawk seems to have had a bad badge of f4's, so only use the first 1mb */ + /* Pixhawk seems to have had a bad batch of f4's, so only use the first 1mb */ rom (rx) : ORIGIN = 0x08004000, LENGTH = 1008K } diff --git a/sw/airborne/boards/lia/baro_board.c b/sw/airborne/boards/lia/baro_board.c new file mode 100644 index 0000000000..daf96d61df --- /dev/null +++ b/sw/airborne/boards/lia/baro_board.c @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2013 Felix Ruess + * + * This file is part of paparazzi. + * + * paparazzi is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2, or (at your option) + * any later version. + * + * paparazzi is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with paparazzi; see the file COPYING. If not, write to + * the Free Software Foundation, 59 Temple Place - Suite 330, + * Boston, MA 02111-1307, USA. + */ + +/** @file boards/lisa_m/baro_board.c + * Baro board interface for Bosch BMP085 on LisaM I2C2 with EOC check. + */ + +#include "std.h" + +#include "subsystems/sensors/baro.h" +#include "peripherals/bmp085.h" +#include "peripherals/bmp085_regs.h" +#include +#include "subsystems/abi.h" + +#include "led.h" + + +struct Bmp085 baro_bmp085; + +static bool baro_eoc(void) +{ + return gpio_get(GPIOB, GPIO0); +} + +void baro_init(void) +{ + bmp085_init(&baro_bmp085, &i2c2, BMP085_SLAVE_ADDR); + + /* setup eoc check function */ + baro_bmp085.eoc = &baro_eoc; + + gpio_clear(GPIOB, GPIO0); + gpio_set_mode(GPIOB, GPIO_MODE_INPUT, + GPIO_CNF_INPUT_PULL_UPDOWN, GPIO0); + +#ifdef BARO_LED + LED_OFF(BARO_LED); +#endif +} + + +void baro_periodic(void) +{ + if (baro_bmp085.initialized) { + bmp085_periodic(&baro_bmp085); + } else { + bmp085_read_eeprom_calib(&baro_bmp085); + } +} + + + +void baro_event(void) +{ + bmp085_event(&baro_bmp085); + + if (baro_bmp085.data_available) { + float pressure = (float)baro_bmp085.pressure; + AbiSendMsgBARO_ABS(BARO_BOARD_SENDER_ID, pressure); + float temp = baro_bmp085.temperature / 10.0f; + AbiSendMsgTEMPERATURE(BARO_BOARD_SENDER_ID, temp); + baro_bmp085.data_available = false; +#ifdef BARO_LED + RunOnceEvery(10, LED_TOGGLE(BARO_LED)); +#endif + } +} diff --git a/sw/airborne/boards/lia/baro_board.h b/sw/airborne/boards/lia/baro_board.h new file mode 100644 index 0000000000..751fc75e91 --- /dev/null +++ b/sw/airborne/boards/lia/baro_board.h @@ -0,0 +1,18 @@ + +/* + * board specific functions for the lia board + * + */ + +#ifndef BOARDS_LIA_BARO_H +#define BOARDS_LIA_BARO_H + +// only for printing the baro type during compilation +#ifndef BARO_BOARD +#define BARO_BOARD BARO_BOARD_BMP085 +#endif + +extern void baro_event(void); +#define BaroEvent baro_event + +#endif /* BOARDS_LIA_BARO_H */ diff --git a/sw/airborne/boards/lia/chibios/v1.1/board.c b/sw/airborne/boards/lia/chibios/v1.1/board.c new file mode 100644 index 0000000000..8b8c8cbe10 --- /dev/null +++ b/sw/airborne/boards/lia/chibios/v1.1/board.c @@ -0,0 +1,54 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +#if HAL_USE_PAL || defined(__DOXYGEN__) +const PALConfig pal_default_config = +{ + {VAL_GPIOAODR, VAL_GPIOACRL, VAL_GPIOACRH}, + {VAL_GPIOBODR, VAL_GPIOBCRL, VAL_GPIOBCRH}, + {VAL_GPIOCODR, VAL_GPIOCCRL, VAL_GPIOCCRH}, + {VAL_GPIODODR, VAL_GPIODCRL, VAL_GPIODCRH}, + {VAL_GPIOEODR, VAL_GPIOECRL, VAL_GPIOECRH}, +}; +#endif + +/* + * Early initialization code. + * This initialization must be performed just after stack setup and before + * any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +/* + * Board-specific initialization code. + */ +void boardInit(void) { + /* + * Several I/O pins are re-mapped: + * JTAG TRST to LED + */ + AFIO->MAPR |= AFIO_MAPR_USART3_REMAP_PARTIALREMAP | AFIO_MAPR_SWJ_CFG_NOJNTRST | AFIO_MAPR_TIM3_REMAP_FULLREMAP; +} diff --git a/sw/airborne/boards/lia/chibios/v1.1/board.h b/sw/airborne/boards/lia/chibios/v1.1/board.h new file mode 100644 index 0000000000..887e6be179 --- /dev/null +++ b/sw/airborne/boards/lia/chibios/v1.1/board.h @@ -0,0 +1,576 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for STMicroelectronics STM32F1-Lia. + */ + +/* + * Board identifier. + */ +#define BOARD_LIA_STM32F105RC +#define BOARD_NAME "Lia 1.1 STM32F105RC" + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 0 +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 12000000 +#endif + + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 330 + +/* + * MCU type as defined in the ST header file stm32f4xx.h. + */ +#define STM32F105xC + + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * + * The digits have the following meaning: + * 0 - Analog input. + * 1 - Push Pull output 10MHz. + * 2 - Push Pull output 2MHz. + * 3 - Push Pull output 50MHz. + * 4 - Digital input. + * 5 - Open Drain output 10MHz. + * 6 - Open Drain output 2MHz. + * 7 - Open Drain output 50MHz. + * 8 - Digital input with PullUp or PullDown resistor depending on ODR. + * 9 - Alternate Push Pull output 10MHz. + * A - Alternate Push Pull output 2MHz. + * B - Alternate Push Pull output 50MHz. + * C - Reserved. + * D - Alternate Open Drain output 10MHz. + * E - Alternate Open Drain output 2MHz. + * F - Alternate Open Drain output 50MHz. + * Please refer to the STM32 Reference Manual for details. + */ + +/* + * Port A setup. + * PA0 - 4 - Digital input (PPM_IN) + * - B - Alternate Push Pull output 50MHz (SERVO5) + * PA1 - B - Alternate Push Pull output 50MHz (SERVO6) + * PA2 - B - Alternate Push Pull output 50MHz (UART2_TX) + * PA3 - 4 - Digital input (UART2_RX) + * PA4 - B - Alternate Push Pull output 50MHz (EXTSPI_SS) + * PA5 - B - Alternate Push Pull output 50MHz (EXTSPI_SCK) + * PA6 - 4 - Digital input. (EXTSPI_MISO) + * PA7 - B - Alternate Push Pull output 50MHz (EXTSPI_MOSI) + * PA8 - 7 - Open Drain output 50MHz (LED1) + * PA9 - 4 - Digital input. (USB_VBUS) + * PA10 - 4 - Digital input. (UART1_RX)/(PPM_IN TIM2_CH2) + * PA11 - 4 - Digital input (USB_DM) + * PA12 - 4 - Digital input (USB_DP) + * PA13 - 4 - Digital input (JTAG_TMS) + * PA14 - 4 - Digital input (JTAG_TCK) + * PA15 - 4 - Digital input (JTAG_TDI) + */ +#define VAL_GPIOACRL 0xB4BB4BBB /* PA7...PA0 */ +#define VAL_GPIOACRH 0x44444447 /* PA15...PA8 */ +#define VAL_GPIOAODR 0xFFFFFFFF + +/* + * Port B setup: + * PB0 - 4 - Digital input (BARO_DRDY) + * PB1 - 4 - Digital input (EXTSPI_DRDY) + * PB2 - 4 - Digital input (IMU_ACC_DRDY) + * PB3 - 4 - Digital input (JTAG_TDO) + * PB4 - 7 - Open Drain output 50MHz (LED2) + * PB5 - 4 - Digital input (IMU_MAG_DRDY) + * PB6 - B - Alternate Push Pull output 50MHz (SERVO7) + * - 7 - Open Drain output 50MHz. (I2C1_SCL) + * PB7 - B - Alternate Push Pull output 50MHz (SERVO8) + * - 7 - Open Drain output 50MHz. (I2C1_SDA) + * PB8 - 4 - Digital input. (CAN_RX) + * PB9 - 7 - Open Drain output 50MHz. (CAN_TX) + * PB10 - E - Alternate Open Drain output 2MHz.(I2C2_SCL) + * PB11 - E - Alternate Open Drain output 2MHz.(I2C2_SDA) + * PB12 - 3 - Push Pull output 50MHz. (IMU_ACC_CS) + * PB13 - B - Alternate Push Pull output 50MHz (IMU_SPI_SCK) + * PB14 - 4 - Digital input (IMU_SPI_MISO) + * PB15 - B - Alternate Push Pull output 50MHz (IMU_SPI_MOSI) + */ +#define VAL_GPIOBCRL 0xBB474444 /* PB7...PB0 */ +#define VAL_GPIOBCRH 0xB4B3EE74 /* PB15...PB8 */ +#define VAL_GPIOBODR 0xFFFFFFFF + +/* + * Port C setup: + * PC0 - 0 - Analog input (ADC2) + * PC1 - 0 - Analog input (ADC3) + * PC2 - 7 - Open Drain output 50MHz (LED3) + * PC3 - 0 - Analog input (ADC1) + * PC4 - 0 - Analog input (VBAT_MEAS) + * PC5 - 7 - Open Drain output 50MHz (LED4) + * PC6 - B - Alternate Push Pull output 50MHz (SERVO1) + * PC7 - B - Alternate Push Pull output 50MHz (SERVO2) + * PC8 - B - Alternate Push Pull output 50MHz (SERVO3) + * PC9 - B - Alternate Push Pull output 50MHz (SERVO4) + * PC10 - B - Alternate Push Pull output 50MHz (UART3_TX) + * PC11 - 4 - Digital input (UART3_RX) + * PC12 - B - Alternate Push Pull output 50MHz (PC12-UART5_TX) + * PC13 - 3 - Push Pull output 50MHz. (IMU_GYRO_SS) + * PC14 - 4 - Digital input (IMU_GYRO_DRDY) + * PC15 - 7 - Open Drain output 50MHz (LED5) + */ +#define VAL_GPIOCCRL 0xBB700700 /* PC7...PC0 */ +#define VAL_GPIOCCRH 0x743B4BBB /* PC15...PC8 */ +#define VAL_GPIOCODR 0xFFFFFFFF + +/* + * Port D setup: + * PD0 - 8 - Digital input with PullUp or PullDown resistor depending on ODR. (OSC_IN). + * PD1 - 8 - Digital input with PullUp or PullDown resistor depending on ODR. (OSC_OUT). + * PD2 - 4 - Digital input (UART5_RX). + * PD3 - 8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD4 - 8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD5 - 8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD6 - 8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD7 - 8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD8 - 8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD9 - 8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD10 - 8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD11 - 8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD12 - 8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD13 - 8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD14 - 8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD15 - 8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + */ +#define VAL_GPIODCRL 0x88888488 /* PD7...PD0 */ +#define VAL_GPIODCRH 0x88888888 /* PD15...PD8 */ +#define VAL_GPIODODR 0xFFFFFFFF + +/* + * Port E setup. + * ALL - 8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected).) + */ +#define VAL_GPIOECRL 0x88888888 /* PE7...PE0 */ +#define VAL_GPIOECRH 0x88888888 /* PE15...PE8 */ +#define VAL_GPIOEODR 0xFFFFFFFF + + +/* + * AHB_CLK + */ +#define AHB_CLK STM32_HCLK + + +/* + * LEDs + */ +/* 1 red, on PA8 */ +#ifndef USE_LED_1 +#define USE_LED_1 1 +#endif +#define LED_1_GPIO GPIOA +#define LED_1_GPIO_PIN 8 +#define LED_1_GPIO_ON gpio_clear +#define LED_1_GPIO_OFF gpio_set + +/* 2 green, shared with JTAG_TRST */ +#ifndef USE_LED_2 +#define USE_LED_2 1 +#endif +#define LED_2_GPIO GPIOB +#define LED_2_GPIO_PIN 4 +#define LED_2_GPIO_ON gpio_clear +#define LED_2_GPIO_OFF gpio_set + +/* 3 green, shared with ADC12 (ADC_6 on connector ANALOG2) */ +#ifndef USE_LED_3 +#define USE_LED_3 1 +#endif +#define LED_3_GPIO GPIOC +#define LED_3_GPIO_PIN 2 +#define LED_3_GPIO_ON gpio_clear +#define LED_3_GPIO_OFF gpio_set + +/* 4 red, shared with ADC15 (ADC_4 on connector ANALOG2) */ +#ifndef USE_LED_4 +#define USE_LED_4 1 +#endif +#define LED_4_GPIO GPIOC +#define LED_4_GPIO_PIN 5 +#define LED_4_GPIO_ON gpio_clear +#define LED_4_GPIO_OFF gpio_set + +/* 5 green, on PC15 */ +#ifndef USE_LED_5 +#define USE_LED_5 0 +#endif +#define LED_5_GPIO GPIOC +#define LED_5_GPIO_PIN 15 +#define LED_5_GPIO_ON gpio_set +#define LED_5_GPIO_OFF gpio_clear + +/* + * ADCs + */ +// AUX 1 +#if USE_ADC_1 +#define AD1_1_CHANNEL ADC_CHANNEL_IN13 +#define ADC_1 AD1_1 +#define ADC_1_GPIO_PORT GPIOC +#define ADC_1_GPIO_PIN GPIO3 +#endif + +// AUX 2 +#if USE_ADC_2 +#define AD1_2_CHANNEL ADC_CHANNEL_IN10 +#define ADC_2 AD1_2 +#define ADC_2_GPIO_PORT GPIOC +#define ADC_2_GPIO_PIN GPIO0 +#endif + +// AUX 3 +#if USE_ADC_3 +#define AD1_3_CHANNEL ADC_CHANNEL_IN11 +#define ADC_3 AD1_3 +#define ADC_3_GPIO_PORT GPIOC +#define ADC_3_GPIO_PIN GPIO1 +#endif + +// Internal ADC for battery enabled by default +#ifndef USE_ADC_4 +#define USE_ADC_4 1 +#endif +#if USE_ADC_4 +#define AD1_4_CHANNEL ADC_CHANNEL_IN14 +#define ADC_4 AD1_4 +#define ADC_4_GPIO_PORT GPIOC +#define ADC_4_GPIO_PIN GPIO4 +#endif + +// Internal Temperature sensor enabled by default +#ifndef USE_ADC_5 +#define USE_ADC_5 1 +#define USE_ADC_SENSOR 1 +#endif +#if USE_ADC_5 +#define AD1_5_CHANNEL ADC_CHANNEL_SENSOR +#define ADC_5 AD1_5 +#define ADC_5_GPIO_PORT GPIOC +#define ADC_5_GPIO_PIN GPIO4 +#endif + + + +/* allow to define ADC_CHANNEL_VSUPPLY in the airframe file*/ +#ifndef ADC_CHANNEL_VSUPPLY +#define ADC_CHANNEL_VSUPPLY ADC_4 +#endif + +#define DefaultVoltageOfAdc(adc) (0.004489*adc) + +/* + * PWM defines + */ +#ifndef USE_PWM0 +#define USE_PWM0 1 +#endif +#if USE_PWM0 +#define PWM_SERVO_0 0 +#define PWM_SERVO_0_GPIO GPIOC +#define PWM_SERVO_0_PIN GPIO6 +#define PWM_SERVO_0_AF GPIO_AF2 +#define PWM_SERVO_0_DRIVER PWMD3 +#define PWM_SERVO_0_CHANNEL 0 +#define PWM_SERVO_0_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_0_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM1 +#define USE_PWM1 1 +#endif +#if USE_PWM1 +#define PWM_SERVO_1 1 +#define PWM_SERVO_1_GPIO GPIOC +#define PWM_SERVO_1_PIN GPIO7 +#define PWM_SERVO_1_AF GPIO_AF1 +#define PWM_SERVO_1_DRIVER PWMD3 +#define PWM_SERVO_1_CHANNEL 1 +#define PWM_SERVO_1_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_1_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM2 +#define USE_PWM2 1 +#endif +#if USE_PWM2 +#define PWM_SERVO_2 2 +#define PWM_SERVO_2_GPIO GPIOC +#define PWM_SERVO_2_PIN GPIO8 +#define PWM_SERVO_2_AF GPIO_AF2 +#define PWM_SERVO_2_DRIVER PWMD3 +#define PWM_SERVO_2_CHANNEL 2 +#define PWM_SERVO_2_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_2_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM3 +#define USE_PWM3 1 +#endif +#if USE_PWM3 +#define PWM_SERVO_3 3 +#define PWM_SERVO_3_GPIO GPIOC +#define PWM_SERVO_3_PIN GPIO9 +#define PWM_SERVO_3_AF GPIO_AF2 +#define PWM_SERVO_3_DRIVER PWMD3 +#define PWM_SERVO_3_CHANNEL 3 +#define PWM_SERVO_3_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_3_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM4 +#define USE_PWM4 1 +#endif +#if USE_PWM4 +#define PWM_SERVO_4 4 +#define PWM_SERVO_4_GPIO GPIOA +#define PWM_SERVO_4_PIN GPIO0 +#define PWM_SERVO_4_AF GPIO_AF2 +#define PWM_SERVO_4_DRIVER PWMD5 +#define PWM_SERVO_4_CHANNEL 0 +#define PWM_SERVO_4_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_4_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM5 +#define USE_PWM5 1 +#endif +#if USE_PWM5 +#define PWM_SERVO_5 5 +#define PWM_SERVO_5_GPIO GPIOA +#define PWM_SERVO_5_PIN GPIO1 +#define PWM_SERVO_5_AF GPIO_AF2 +#define PWM_SERVO_5_DRIVER PWMD5 +#define PWM_SERVO_5_CHANNEL 1 +#define PWM_SERVO_5_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_5_ACTIVE PWM_OUTPUT_DISABLED +#endif + + +#if USE_SERVOS_7AND8 + #if USE_I2C1 + #error "You cannot USE_SERVOS_7AND8 and USE_I2C1 at the same time" + #else /* !USE_I2C1 */ + #if USE_PWM6 + #define PWM_SERVO_6 6 + #define PWM_SERVO_6_GPIO GPIOB + #define PWM_SERVO_6_PIN GPIO6 + #define PWM_SERVO_6_AF GPIO_AF2 + #define PWM_SERVO_6_DRIVER PWMD4 + #define PWM_SERVO_6_CHANNEL 0 + #define PWM_SERVO_6_ACTIVE PWM_OUTPUT_ACTIVE_HIGH + #else + #define PWM_SERVO_6_ACTIVE PWM_OUTPUT_DISABLED + #endif + + #if USE_PWM7 + #define PWM_SERVO_7 7 + #define PWM_SERVO_7_GPIO GPIOB + #define PWM_SERVO_7_PIN GPIO7 + #define PWM_SERVO_7_AF GPIO_AF2 + #define PWM_SERVO_7_DRIVER PWMD4 + #define PWM_SERVO_7_CHANNEL 1 + #define PWM_SERVO_7_ACTIVE PWM_OUTPUT_ACTIVE_HIGH + #else + #define PWM_SERVO_7_ACTIVE PWM_OUTPUT_DISABLED + #endif + + #define PWM_CONF_TIM3 1 + #define PWM_CONF_TIM4 1 + #define PWM_CONF_TIM5 1 + #define PWM_CONF3_DEF { \ + PWM_FREQUENCY, \ + PWM_FREQUENCY/TIM3_SERVO_HZ, \ + NULL, \ + { \ + {PWM_SERVO_0_ACTIVE, NULL}, \ + {PWM_SERVO_1_ACTIVE, NULL}, \ + {PWM_SERVO_2_ACTIVE, NULL}, \ + {PWM_SERVO_3_ACTIVE, NULL} \ + }, \ + 0, \ + 0 \ + } + #define PWM_CONF4_DEF { \ + PWM_FREQUENCY, \ + PWM_FREQUENCY/TIM4_SERVO_HZ, \ + NULL, \ + { \ + {PWM_SERVO_6_ACTIVE, NULL}, \ + {PWM_SERVO_7_ACTIVE, NULL}, \ + {PWM_OUTPUT_DISABLED, NULL}, \ + {PWM_OUTPUT_DISABLED, NULL} \ + }, \ + 0, \ + 0 \ + } + #define PWM_CONF5_DEF { \ + PWM_FREQUENCY, \ + PWM_FREQUENCY/TIM5_SERVO_HZ, \ + NULL, \ + { \ + {PWM_SERVO_4_ACTIVE, NULL}, \ + {PWM_SERVO_5_ACTIVE, NULL}, \ + {PWM_OUTPUT_DISABLED, NULL}, \ + {PWM_OUTPUT_DISABLED, NULL} \ + }, \ + 0, \ + 0 \ + } + #endif /* USE_I2C1 */ +#else /* !USE_SERVOS_7AND8 */ + #define PWM_CONF_TIM3 1 + #define PWM_CONF_TIM5 1 + #define PWM_CONF3_DEF { \ + PWM_FREQUENCY, \ + PWM_FREQUENCY/TIM3_SERVO_HZ, \ + NULL, \ + { \ + {PWM_SERVO_0_ACTIVE, NULL}, \ + {PWM_SERVO_1_ACTIVE, NULL}, \ + {PWM_SERVO_2_ACTIVE, NULL}, \ + {PWM_SERVO_3_ACTIVE, NULL} \ + }, \ + 0, \ + 0 \ + } + #define PWM_CONF5_DEF { \ + PWM_FREQUENCY, \ + PWM_FREQUENCY/TIM5_SERVO_HZ, \ + NULL, \ + { \ + {PWM_SERVO_4_ACTIVE, NULL}, \ + {PWM_SERVO_5_ACTIVE, NULL}, \ + {PWM_OUTPUT_DISABLED, NULL}, \ + {PWM_OUTPUT_DISABLED, NULL} \ + }, \ + 0, \ + 0 \ + } +#endif /* USE_SERVOS_7AND8 */ + + +/** + * PPM radio defines + */ +#define RC_PPM_TICKS_PER_USEC 6 +#define PPM_TIMER_FREQUENCY 6000000 +#define PPM_CHANNEL ICU_CHANNEL_1 +#define PPM_TIMER ICUD1 + +/** + * I2C defines + */ +#define I2C1_CLOCK_SPEED 400000 +#define I2C1_CFG_DEF { \ + OPMODE_I2C, \ + I2C1_CLOCK_SPEED, \ + FAST_DUTY_CYCLE_2, \ + } + +#define I2C2_CLOCK_SPEED 400000 +#define I2C2_CFG_DEF { \ + OPMODE_I2C, \ + I2C2_CLOCK_SPEED, \ + FAST_DUTY_CYCLE_2, \ + } + +/** + * SPI Config + */ +#define SPI_SELECT_SLAVE0_PORT GPIOA +#define SPI_SELECT_SLAVE0_PIN GPIO15 + +#define SPI_SELECT_SLAVE1_PORT GPIOA +#define SPI_SELECT_SLAVE1_PIN GPIO4 + +#define SPI_SELECT_SLAVE2_PORT GPIOB +#define SPI_SELECT_SLAVE2_PIN GPIO12 + +#define SPI_SELECT_SLAVE3_PORT GPIOC +#define SPI_SELECT_SLAVE3_PIN GPIO13 + +#define SPI_SELECT_SLAVE4_PORT GPIOC +#define SPI_SELECT_SLAVE4_PIN GPIO12 + +#define SPI_SELECT_SLAVE5_PORT GPIOC +#define SPI_SELECT_SLAVE5_PIN GPIO4 + +#define SPI1_GPIO_PORT_NSS GPIOA +#define SPI1_GPIO_NSS GPIO4 + +#define SPI2_GPIO_PORT_NSS GPIOB +#define SPI2_GPIO_NSS GPIO12 + +#define SPI3_GPIO_PORT_NSS GPIO + +/** + * Baro + * + * Apparently needed for backwards compatibility + * with the ancient onboard baro boards + */ +#ifndef USE_BARO_BOARD +#define USE_BARO_BOARD 1 +#endif + +/* + * Actuators for fixedwing + */ + /* Default actuators driver */ +#define DEFAULT_ACTUATORS "subsystems/actuators/actuators_pwm.h" +#define ActuatorDefaultSet(_x,_y) ActuatorPwmSet(_x,_y) +#define ActuatorsDefaultInit() ActuatorsPwmInit() +#define ActuatorsDefaultCommit() ActuatorsPwmCommit() + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/sw/airborne/boards/lia/chibios/v1.1/board.mk b/sw/airborne/boards/lia/chibios/v1.1/board.mk new file mode 100644 index 0000000000..5a109515f4 --- /dev/null +++ b/sw/airborne/boards/lia/chibios/v1.1/board.mk @@ -0,0 +1,20 @@ +# +# ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Required include directories +BOARDINC = $(CHIBIOS_BOARD_DIR) + +# List of all the board related files. +BOARDSRC = ${BOARDINC}/board.c diff --git a/sw/airborne/boards/lia/chibios/v1.1/mcuconf.h b/sw/airborne/boards/lia/chibios/v1.1/mcuconf.h new file mode 100644 index 0000000000..b5ee668eff --- /dev/null +++ b/sw/airborne/boards/lia/chibios/v1.1/mcuconf.h @@ -0,0 +1,278 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ +#ifndef _MCUCONF_H_ +#define _MCUCONF_H_ + + +#define STM32F107_MCUCONF + +/* + * STM32F1xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED FALSE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_PREDIV1 +#define STM32_PREDIV1_VALUE 1 +#define STM32_PLLMUL_VALUE 6 +#define STM32_PREDIV2_VALUE 3 +#define STM32_PLL2MUL_VALUE 10 +#define STM32_PLL3MUL_VALUE 12 +#define STM32_PLLXTPRE STM32_PLLXTPRE_DIV1 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV2 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_ADCPRE STM32_ADCPRE_DIV4 +#define STM32_USB_CLOCK_REQUIRED TRUE +#define STM32_USBPRE STM32_USBPRE_DIV1P5 +#define STM32_MCOSEL STM32_MCOSEL_NOCLOCK +#define STM32_RTCSEL STM32_RTCSEL_HSEDIV +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC1_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#if USE_CAN1 +#define STM32_CAN_USE_CAN1 TRUE +#else +#define STM32_CAN_USE_CAN1 FALSE +#endif +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#if USE_I2C1 +#define STM32_I2C_USE_I2C1 TRUE +#else +#define STM32_I2C_USE_I2C1 FALSE +#endif +#if USE_I2C2 +#define STM32_I2C_USE_I2C2 TRUE +#else +#define STM32_I2C_USE_I2C2 FALSE +#endif +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 TRUE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 + +/* + * RTC driver system settings. + */ +#define STM32_RTC_IRQ_PRIORITY 15 + +/* + * SERIAL driver system settings. + */ +#if USE_UART1 +#define STM32_SERIAL_USE_USART1 TRUE +#else +#define STM32_SERIAL_USE_USART1 FALSE +#endif +#if USE_UART2 +#define STM32_SERIAL_USE_USART2 TRUE +#else +#define STM32_SERIAL_USE_USART2 FALSE +#endif +#if USE_UART3 +#define STM32_SERIAL_USE_USART3 TRUE +#else +#define STM32_SERIAL_USE_USART3 FALSE +#endif +#if USE_UART4 +#define STM32_SERIAL_USE_UART4 TRUE +#else +#define STM32_SERIAL_USE_UART4 FALSE +#endif +#if USE_UART5 +#define STM32_SERIAL_USE_UART5 TRUE +#else +#define STM32_SERIAL_USE_UART5 FALSE +#endif +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#if USE_SPI1 +#define STM32_SPI_USE_SPI1 TRUE +#else +#define STM32_SPI_USE_SPI1 FALSE +#endif +#if USE_SPI2 +#define STM32_SPI_USE_SPI2 TRUE +#else +#define STM32_SPI_USE_SPI2 FALSE +#endif +#if USE_SPI3 +#define STM32_SPI_USE_SPI3 TRUE +#else +#define STM32_SPI_USE_SPI3 FALSE +#endif +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#if USE_UARTD1 +#define STM32_UART_USE_USART1 TRUE +#else +#define STM32_UART_USE_USART1 FALSE +#endif +#if USE_UARTD2 +#define STM32_UART_USE_USART2 TRUE +#else +#define STM32_UART_USE_USART2 FALSE +#endif +#if USE_UARTD3 +#define STM32_UART_USE_USART3 TRUE +#else +#define STM32_UART_USE_USART3 FALSE +#endif +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#if USE_USB_SERIAL +#define STM32_USB_USE_OTG1 TRUE +#else +#define STM32_USB_USE_OTG1 FALSE +#endif +#define STM32_USB_LOW_POWER_ON_SUSPEND FALSE +#define STM32_USB_USB1_HP_IRQ_PRIORITY 13 +#define STM32_USB_USB1_LP_IRQ_PRIORITY 14 + +/* + * WDG driver system settings. + */ +#define STM32_WDG_USE_IWDG FALSE + +#endif /* _MCUCONF_H_ */ diff --git a/sw/airborne/boards/lia_1.1.h b/sw/airborne/boards/lia_1.1.h index 280b65bd0d..01e543420d 100644 --- a/sw/airborne/boards/lia_1.1.h +++ b/sw/airborne/boards/lia_1.1.h @@ -127,9 +127,10 @@ #define DefaultVoltageOfAdc(adc) (0.0045*adc) - -// FIXME, using baro_board right now to include the appropriate header -#define USE_BARO_BOARD 0 +/* by default activate onboard baro */ +#ifndef USE_BARO_BOARD +#define USE_BARO_BOARD 1 +#endif #endif /* CONFIG_LIA_1_1_H */ diff --git a/sw/airborne/boards/lisa_m/chibios/v2.0 b/sw/airborne/boards/lisa_m/chibios/v2.0 new file mode 120000 index 0000000000..0334e2be4a --- /dev/null +++ b/sw/airborne/boards/lisa_m/chibios/v2.0 @@ -0,0 +1 @@ +../../lia/chibios/v1.1/ \ No newline at end of file diff --git a/sw/airborne/boards/lisa_m/chibios/v2.1 b/sw/airborne/boards/lisa_m/chibios/v2.1 new file mode 120000 index 0000000000..0334e2be4a --- /dev/null +++ b/sw/airborne/boards/lisa_m/chibios/v2.1 @@ -0,0 +1 @@ +../../lia/chibios/v1.1/ \ No newline at end of file diff --git a/sw/airborne/boards/px4fmu/chibios/v2.4/board.c b/sw/airborne/boards/px4fmu/chibios/v2.4/board.c new file mode 100644 index 0000000000..777c0bc89f --- /dev/null +++ b/sw/airborne/boards/px4fmu/chibios/v2.4/board.c @@ -0,0 +1,124 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} +#endif +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + return !palReadPad(GPIOB, GPIOB_SDIO_DETECT); +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} + diff --git a/sw/airborne/boards/px4fmu/chibios/v2.4/board.h b/sw/airborne/boards/px4fmu/chibios/v2.4/board.h new file mode 100644 index 0000000000..e6912ead91 --- /dev/null +++ b/sw/airborne/boards/px4fmu/chibios/v2.4/board.h @@ -0,0 +1,1379 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for STMicroelectronics STM32F4-Discovery board. + */ + +/* + * Board identifier. + */ +#define BOARD_PX4FMU_v2 +#define BOARD_NAME "Pixhawk PX4 FMU v 2.4" + +/* + * Board oscillators-related settings. + * NOTE: LSE NOT? fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 0 // originally was 32000 ? +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 24000000 +#endif + + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 330 + +/* + * MCU type as defined in the ST header file stm32f4xx.h. + */ +#define STM32F407xx + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_2M(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_25M(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_50M(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_100M(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * Port A setup. + * + * PA0 - Alternate Push Pull output 50MHz (UART4_TX) + * PA1 - Alternate Digital input (UART4_RX) + * PA2 - Analog input (BATT VOLTAGE SENS - ADC in) + * PA3 - Analog input (BATT CURRENT SENS - ADC in) + * PA4 - Analog input (VDD 5V SENS - ADC in) + * PA5 - Alternate Push Pull output 50MHz (EXTSPI1_SCK) + * PA6 - Digital input. (EXTSPI1_MISO) + * PA7 - Alternate Push Pull output 50MHz (EXTSPI1_MOSI) + * PA8 - Digital input (!VDD_5V_PERIPH_EN) + * PA9 - Digital input. (USB_VBUS) + * PA10 - Alternate Digital input (UART1_Rx) + * PA11 - Alternate input (USB_DM) + * PA12 - Alternate input (USB_DP) + * PA13 - Digital input (SWDIO) + * PA14 - Digital input (SWCLCK) + * PA15 - Digital output (ALARM) + */ +#define VAL_GPIOA_MODER (PIN_MODE_ALTERNATE(0)| \ + PIN_MODE_ALTERNATE(1) | \ + PIN_MODE_ALTERNATE(2) | \ + PIN_MODE_ALTERNATE(3) | \ + PIN_MODE_ALTERNATE(4) | \ + PIN_MODE_ALTERNATE(5) | \ + PIN_MODE_ALTERNATE(6) | \ + PIN_MODE_ALTERNATE(7) | \ + PIN_MODE_OUTPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_ALTERNATE(10) | \ + PIN_MODE_ALTERNATE(11) | \ + PIN_MODE_ALTERNATE(12) | \ + PIN_MODE_ALTERNATE(13) | \ + PIN_MODE_ALTERNATE(14) | \ + PIN_MODE_ALTERNATE(15)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_OPENDRAIN(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_50M(0) | \ + PIN_OSPEED_50M(1) | \ + PIN_OSPEED_50M(2) | \ + PIN_OSPEED_50M(3) | \ + PIN_OSPEED_50M(4) | \ + PIN_OSPEED_50M(5) | \ + PIN_OSPEED_50M(6) | \ + PIN_OSPEED_50M(7) | \ + PIN_OSPEED_50M(8) | \ + PIN_OSPEED_50M(9) | \ + PIN_OSPEED_50M(10) | \ + PIN_OSPEED_50M(11) | \ + PIN_OSPEED_50M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOA_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(0, 2) | \ + PIN_AFIO_AF(1, 2) | \ + PIN_AFIO_AF(2, 7) | \ + PIN_AFIO_AF(3, 7) | \ + PIN_AFIO_AF(4, 5) | \ + PIN_AFIO_AF(5, 5) | \ + PIN_AFIO_AF(6, 5) | \ + PIN_AFIO_AF(7, 5)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 1) | \ + PIN_AFIO_AF(11, 10) | \ + PIN_AFIO_AF(12, 10) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * Port B setup: + * PB0 - Digital input (BARO_DRDY) + * PB1 - Digital input (EXTSPI1_DRDY) + * PB2 - Digital input (IMU_ACC_DRDY) + * PB3 - Digital input (JTAG_TDO/SWD) + * PB4 - Open Drain output 50MHz (LED2) + * PB5 - Digital input (IMU_MAG_DRDY) + * PB6 - Alternate Push Pull output 50MHz (SERVO7-Timer4Ch1)/USART1_TX + * PB7 - Alternate Push Pull output 50MHz (SERVO8-Timer4Ch2)/USART1_RX + * PB8 - Digital input. (CAN_RX) + * PB9 - Open Drain output 50MHz. (CAN_TX) + * PB10 - Alternate Open Drain output 2MHz.(I2C2_SCL) + * PB11 - Alternate Open Drain output 2MHz.(I2C2_SDA) + * PB12 - Push Pull output 50MHz. (IMU_ACC_SPI2_CS) + * PB13 - Alternate Push Pull output 50MHz (IMU_SPI2_SCK) + * PB14 - Digital input (IMU_SPI2_MISO) + * PB15 - Alternate Push Pull output 50MHz (IMU_SPI_MOSI) + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_ALTERNATE(3) | \ + PIN_MODE_OUTPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_ALTERNATE(6) | \ + PIN_MODE_ALTERNATE(7) | \ + PIN_MODE_ALTERNATE(8) | \ + PIN_MODE_ALTERNATE(9) | \ + PIN_MODE_ALTERNATE(10) | \ + PIN_MODE_ALTERNATE(11) | \ + PIN_MODE_OUTPUT(12) | \ + PIN_MODE_ALTERNATE(13) | \ + PIN_MODE_ALTERNATE(14) | \ + PIN_MODE_ALTERNATE(15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_OPENDRAIN(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_OPENDRAIN(9) | \ + PIN_OTYPE_OPENDRAIN(10) | \ + PIN_OTYPE_OPENDRAIN(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_50M(0) | \ + PIN_OSPEED_50M(1) | \ + PIN_OSPEED_50M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_50M(4) | \ + PIN_OSPEED_50M(5) | \ + PIN_OSPEED_50M(6) | \ + PIN_OSPEED_50M(7) | \ + PIN_OSPEED_50M(8) | \ + PIN_OSPEED_50M(9) | \ + PIN_OSPEED_2M(10) | \ + PIN_OSPEED_2M(11) | \ + PIN_OSPEED_50M(12) | \ + PIN_OSPEED_50M(13) | \ + PIN_OSPEED_50M(14) | \ + PIN_OSPEED_50M(15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOB_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 7) | \ + PIN_AFIO_AF(7, 7)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(8, 9) | \ + PIN_AFIO_AF(9, 9) | \ + PIN_AFIO_AF(10, 4) | \ + PIN_AFIO_AF(11, 4) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 5) | \ + PIN_AFIO_AF(14, 5) | \ + PIN_AFIO_AF(15, 5)) + +/* + * Port C setup: + * PC0 - Analog input (ADC2) + * PC1 - Analog input (ADC3) + * PC2 - Open Drain output 50MHz (LED3) + * PC3 - Analog input (ADC1) + * PC4 - Analog input (VBAT_MEAS) + * PC5 - Open Drain output 50MHz (LED4) + * PC6 - Alternate Push Pull output 50MHz (SERVO1-Timer3Ch1) + * PC7 - Alternate Push Pull output 50MHz (SERVO2-Timer3Ch2) + * PC8 - Alternate Push Pull output 50MHz (SERVO3-Timer3Ch3) + * PC9 - Alternate Push Pull output 50MHz (SERVO4-Timer3Ch4) + * PC10 - Alternate Push Pull output 50MHz (UART3_TX) + * PC11 - Digital input (UART3_RX) + * PC12 - Alternate Push Pull output 50MHz (PC12-UART5_TX) + * PC13 - Push Pull output 50MHz. (IMU_GYRO_SS-Baro_SS_SPI2) + * PC14 - Digital input (IMU_GYRO_DRDY) + * PC15 - Open Drain output 50MHz (LED5) + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(0) |\ + PIN_MODE_INPUT(1) | \ + PIN_MODE_OUTPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_OUTPUT(5) | \ + PIN_MODE_ALTERNATE(6) | \ + PIN_MODE_ALTERNATE(7) | \ + PIN_MODE_ALTERNATE(8) | \ + PIN_MODE_ALTERNATE(9) | \ + PIN_MODE_ALTERNATE(10) | \ + PIN_MODE_ALTERNATE(11) | \ + PIN_MODE_ALTERNATE(12) | \ + PIN_MODE_OUTPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_OUTPUT(15)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(0) |\ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_OPENDRAIN(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_OPENDRAIN(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_OPENDRAIN(15)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_50M(0) |\ + PIN_OSPEED_50M(1) | \ + PIN_OSPEED_50M(2) | \ + PIN_OSPEED_50M(3) | \ + PIN_OSPEED_50M(4) | \ + PIN_OSPEED_50M(5) | \ + PIN_OSPEED_50M(6) | \ + PIN_OSPEED_50M(7) | \ + PIN_OSPEED_50M(8) | \ + PIN_OSPEED_50M(9) | \ + PIN_OSPEED_50M(10) | \ + PIN_OSPEED_50M(11) | \ + PIN_OSPEED_50M(12) | \ + PIN_OSPEED_50M(13) | \ + PIN_OSPEED_50M(14) | \ + PIN_OSPEED_50M(15)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(0) |\ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOC_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(0, 0) |\ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 2) | \ + PIN_AFIO_AF(7, 2)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(8, 2) | \ + PIN_AFIO_AF(9, 2) | \ + PIN_AFIO_AF(10, 7) | \ + PIN_AFIO_AF(11, 7) | \ + PIN_AFIO_AF(12, 8) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * Port D setup: + * PD0 - Digital input with PullUp or PullDown resistor depending on ODR. (OSC_IN). + * PD1 - Digital input with PullUp or PullDown resistor depending on ODR. (OSC_OUT). + * PD2 - Digital input (UART5_RX). + * PD3 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD4 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD5 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD6 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD7 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD9 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD10 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD11 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD12 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD13 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD14 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD15 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + */ +#define VAL_GPIOD_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_ALTERNATE(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) |\ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_50M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) |\ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 8) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * Port E setup. + * PE0 - PE15 - floating input + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_OUTPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_OPENDRAIN(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * GPIOF setup: + * + * PF0 - PF15 (input floating). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * GPIOG setup: + * + * PG0 - PG15 (input floating). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * GPIOH setup: + * + * PH0 - PH15 (input floating). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * GPIOI setup: + * + * PI0 - PI15 (input floating). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + + + +/* + * AHB_CLK + */ +#define AHB_CLK STM32_HCLK + +/* + * Onboard LEDs + */ +/* red, on PE12 */ +#ifndef USE_LED_1 +#define USE_LED_1 1 +#endif +#define LED_1_GPIO GPIOE +#define LED_1_GPIO_PIN GPIO12 +#define LED_1_GPIO_ON gpio_clear +#define LED_1_GPIO_OFF gpio_set +#define LED_1_AFIO_REMAP ((void)0) + +/* + * ADCs + */ +// AUX 1 +#if USE_ADC_1 +#define AD1_1_CHANNEL ADC_CHANNEL_IN9 +#define ADC_1 AD1_1 +#define ADC_1_GPIO_PORT GPIOB +#define ADC_1_GPIO_PIN GPIO1 +#endif + +// AUX 2 +#if USE_ADC_2 +#define AD1_2_CHANNEL ADC_CHANNEL_IN15 +#define ADC_2 AD1_2 +#define ADC_2_GPIO_PORT GPIOC +#define ADC_2_GPIO_PIN GPIO5 +#endif + +// AUX 3 +#if USE_ADC_3 +#define AD1_3_CHANNEL ADC_CHANNEL_IN14 +#define ADC_3 AD1_3 +#define ADC_3_GPIO_PORT GPIOC +#define ADC_3_GPIO_PIN GPIO4 +#endif + +// Internal ADC for battery enabled by default +#ifndef USE_ADC_4 +#define USE_ADC_4 1 +#endif +#if USE_ADC_4 +#define AD1_4_CHANNEL ADC_CHANNEL_IN4 +#define ADC_4 AD1_4 +#define ADC_4_GPIO_PORT GPIOA +#define ADC_4_GPIO_PIN GPIO4 +#endif + +/* allow to define ADC_CHANNEL_VSUPPLY in the airframe file*/ +#ifndef ADC_CHANNEL_VSUPPLY +#define ADC_CHANNEL_VSUPPLY ADC_4 +#endif + +#define DefaultVoltageOfAdc(adc) (0.006185*adc) + +/* + * PWM defines + */ +#ifndef USE_PWM0 +#define USE_PWM0 1 +#endif +#if USE_PWM0 +#define PWM_SERVO_0 0 +#define PWM_SERVO_0_GPIO GPIOB +#define PWM_SERVO_0_PIN GPIO0 +#define PWM_SERVO_0_AF GPIO_AF2 +#define PWM_SERVO_0_DRIVER PWMD3 +#define PWM_SERVO_0_CHANNEL 2 +#define PWM_SERVO_0_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_0_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM1 +#define USE_PWM1 1 +#endif +#if USE_PWM1 +#define PWM_SERVO_1 1 +#define PWM_SERVO_1_GPIO GPIOA +#define PWM_SERVO_1_PIN GPIO2 +#define PWM_SERVO_1_AF GPIO_AF1 +#define PWM_SERVO_1_DRIVER PWMD2 +#define PWM_SERVO_1_CHANNEL 2 +#define PWM_SERVO_1_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_1_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM2 +#define USE_PWM2 1 +#endif +#if USE_PWM2 +#define PWM_SERVO_2 2 +#define PWM_SERVO_2_GPIO GPIOB +#define PWM_SERVO_2_PIN GPIO5 +#define PWM_SERVO_2_AF GPIO_AF2 +#define PWM_SERVO_2_DRIVER PWMD3 +#define PWM_SERVO_2_CHANNEL 1 +#define PWM_SERVO_2_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_2_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM3 +#define USE_PWM3 1 +#endif +#if USE_PWM3 +#define PWM_SERVO_3 3 +#define PWM_SERVO_3_GPIO GPIOB +#define PWM_SERVO_3_PIN GPIO4 +#define PWM_SERVO_3_AF GPIO_AF2 +#define PWM_SERVO_3_DRIVER PWMD3 +#define PWM_SERVO_3_CHANNEL 0 +#define PWM_SERVO_3_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_3_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM4 +#define USE_PWM4 1 +#endif +#if USE_PWM4 +#define PWM_SERVO_4 4 +#define PWM_SERVO_4_GPIO GPIOB +#define PWM_SERVO_4_PIN GPIO3 +#define PWM_SERVO_4_AF GPIO_AF1 +#define PWM_SERVO_4_DRIVER PWMD2 +#define PWM_SERVO_4_CHANNEL 1 +#define PWM_SERVO_4_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_4_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM5 +#define USE_PWM5 1 +#endif +#if USE_PWM5 +#define PWM_SERVO_5 5 +#define PWM_SERVO_5_GPIO GPIOA +#define PWM_SERVO_5_PIN GPIO15 +#define PWM_SERVO_5_AF GPIO_AF1 +#define PWM_SERVO_5_DRIVER PWMD2 +#define PWM_SERVO_5_CHANNEL 0 +#define PWM_SERVO_5_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_5_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#if USE_PWM6 +#define PWM_SERVO_6 6 +#define PWM_SERVO_6_GPIO GPIOB +#define PWM_SERVO_6_PIN GPIO1 +#define PWM_SERVO_6_AF GPIO_AF2 +#define PWM_SERVO_6_DRIVER PWMD3 +#define PWM_SERVO_6_CHANNEL 3 +#define PWM_SERVO_6_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_6_ACTIVE PWM_OUTPUT_DISABLED +#endif + + +#ifdef STM32_PWM_USE_TIM2 +#define PWM_CONF_TIM2 STM32_PWM_USE_TIM2 +#else +#define PWM_CONF_TIM2 1 +#endif +#define PWM_CONF2_DEF { \ + PWM_FREQUENCY, \ + PWM_FREQUENCY/TIM2_SERVO_HZ, \ + NULL, \ + { \ + { PWM_SERVO_5_ACTIVE, NULL }, \ + { PWM_SERVO_4_ACTIVE, NULL }, \ + { PWM_SERVO_1_ACTIVE, NULL }, \ + { PWM_OUTPUT_DISABLED, NULL }, \ + }, \ + 0, \ + 0 \ +} + +#ifdef STM32_PWM_USE_TIM3 +#define PWM_CONF_TIM3 STM32_PWM_USE_TIM3 +#else +#define PWM_CONF_TIM3 1 +#endif +#define PWM_CONF3_DEF { \ + PWM_FREQUENCY, \ + PWM_FREQUENCY/TIM3_SERVO_HZ, \ + NULL, \ + { \ + { PWM_SERVO_3_ACTIVE, NULL }, \ + { PWM_SERVO_2_ACTIVE, NULL }, \ + { PWM_SERVO_0_ACTIVE, NULL }, \ + { PWM_SERVO_6_ACTIVE, NULL }, \ + }, \ + 0, \ + 0 \ +} + +/** + * PPM radio defines + */ +#define RC_PPM_TICKS_PER_USEC 2 +#define PPM_TIMER_FREQUENCY 2000000 +#define PPM_CHANNEL ICU_CHANNEL_1 +#define PPM_TIMER ICUD1 + +/* + * PWM input + */ +// PWM_INPUT 1 on PA8 (also PPM IN) +#define PWM_INPUT1_ICU ICUD1 +#define PWM_INPUT1_CHANNEL ICU_CHANNEL_1 +// PPM in (aka PA8) is used: not compatible with PPM RC receiver +#define PWM_INPUT1_GPIO_PORT GPIOA +#define PWM_INPUT1_GPIO_PIN GPIO8 +#define PWM_INPUT1_GPIO_AF GPIO_AF1 + +// PWM_INPUT 2 on PA3 (also SERVO 1) +#if (USE_PWM1 && USE_PWM_INPUT2) +#error "PW1 and PWM_INPUT2 are not compatible" +#endif +#define PWM_INPUT2_ICU ICUD2 +#define PWM_INPUT2_CHANNEL ICU_CHANNEL_1 +#define PWM_INPUT2_GPIO_PORT GPIOA +#define PWM_INPUT2_GPIO_PIN GPIO2 +#define PWM_INPUT2_GPIO_AF GPIO_AF3 + +/** + * I2C defines + */ +#ifndef I2C1_CLOCK_SPEED +#define I2C1_CLOCK_SPEED 400000 +#endif +#if I2C1_CLOCK_SPEED == 400000 +#define I2C1_DUTY_CYCLE FAST_DUTY_CYCLE_2 +#elif I2C1_CLOCK_SPEED == 100000 +#define I2C1_DUTY_CYCLE STD_DUTY_CYCLE +#else +#error Invalid I2C1 clock speed +#endif +#define I2C1_CFG_DEF { \ + OPMODE_I2C, \ + I2C1_CLOCK_SPEED, \ + I2C1_DUTY_CYCLE, \ + } + +#ifndef I2C2_CLOCK_SPEED +#define I2C2_CLOCK_SPEED 400000 +#endif +#if I2C2_CLOCK_SPEED == 400000 +#define I2C2_DUTY_CYCLE FAST_DUTY_CYCLE_2 +#elif I2C2_CLOCK_SPEED == 100000 +#define I2C2_DUTY_CYCLE STD_DUTY_CYCLE +#else +#error Invalid I2C2 clock speed +#endif +#define I2C2_CFG_DEF { \ + OPMODE_I2C, \ + I2C2_CLOCK_SPEED, \ + I2C2_DUTY_CYCLE, \ + } + +/** + * SPI Config + */ +#define SPI1_GPIO_AF GPIO_AF5 +#define SPI1_GPIO_PORT_MISO GPIOA +#define SPI1_GPIO_MISO GPIO6 +#define SPI1_GPIO_PORT_MOSI GPIOA +#define SPI1_GPIO_MOSI GPIO7 +#define SPI1_GPIO_PORT_SCK GPIOA +#define SPI1_GPIO_SCK GPIO5 + +// SLAVE0 on SPI connector +#define SPI_SELECT_SLAVE0_PORT GPIOB +#define SPI_SELECT_SLAVE0_PIN GPIO9 +// SLAVE1 on AUX1 +#define SPI_SELECT_SLAVE1_PORT GPIOB +#define SPI_SELECT_SLAVE1_PIN GPIO1 +// SLAVE2 on AUX2 +#define SPI_SELECT_SLAVE2_PORT GPIOC +#define SPI_SELECT_SLAVE2_PIN GPIO5 +// SLAVE3 on AUX3 +#define SPI_SELECT_SLAVE3_PORT GPIOC +#define SPI_SELECT_SLAVE3_PIN GPIO4 +// SLAVE4 on AUX4 +#define SPI_SELECT_SLAVE4_PORT GPIOB +#define SPI_SELECT_SLAVE4_PIN GPIO15 + +/** + * Baro + * + * Apparently needed for backwards compatibility + * with the ancient onboard baro boards + */ +#ifndef USE_BARO_BOARD +#define USE_BARO_BOARD 1 +#endif + +/* + * Actuators for fixedwing + */ + /* Default actuators driver */ +#define DEFAULT_ACTUATORS "subsystems/actuators/actuators_pwm.h" +#define ActuatorDefaultSet(_x,_y) ActuatorPwmSet(_x,_y) +#define ActuatorsDefaultInit() ActuatorsPwmInit() +#define ActuatorsDefaultCommit() ActuatorsPwmCommit() + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/sw/airborne/boards/px4fmu/chibios/v2.4/board.mk b/sw/airborne/boards/px4fmu/chibios/v2.4/board.mk new file mode 100644 index 0000000000..5a109515f4 --- /dev/null +++ b/sw/airborne/boards/px4fmu/chibios/v2.4/board.mk @@ -0,0 +1,20 @@ +# +# ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Required include directories +BOARDINC = $(CHIBIOS_BOARD_DIR) + +# List of all the board related files. +BOARDSRC = ${BOARDINC}/board.c diff --git a/sw/airborne/boards/px4fmu/chibios/v2.4/ffconf.h b/sw/airborne/boards/px4fmu/chibios/v2.4/ffconf.h new file mode 100644 index 0000000000..cd1c5cca30 --- /dev/null +++ b/sw/airborne/boards/px4fmu/chibios/v2.4/ffconf.h @@ -0,0 +1,239 @@ +/* CHIBIOS FIX */ +#include "ch.h" + +/*---------------------------------------------------------------------------/ +/ FatFs - FAT file system module configuration file R0.10b (C)ChaN, 2014 +/---------------------------------------------------------------------------*/ + +#ifndef _FFCONF +#define _FFCONF 8051 /* Revision ID */ + + +/*---------------------------------------------------------------------------/ +/ Functions and Buffer Configurations +/---------------------------------------------------------------------------*/ + +#define _FS_TINY 0 /* 0:Normal or 1:Tiny */ +/* When _FS_TINY is set to 1, it reduces memory consumption _MAX_SS bytes each +/ file object. For file data transfer, FatFs uses the common sector buffer in +/ the file system object (FATFS) instead of private sector buffer eliminated +/ from the file object (FIL). */ + + +#define _FS_READONLY 0 /* 0:Read/Write or 1:Read only */ +/* Setting _FS_READONLY to 1 defines read only configuration. This removes +/ writing functions, f_write(), f_sync(), f_unlink(), f_mkdir(), f_chmod(), +/ f_rename(), f_truncate() and useless f_getfree(). */ + + +#define _FS_MINIMIZE 0 /* 0 to 3 */ +/* The _FS_MINIMIZE option defines minimization level to remove API functions. +/ +/ 0: All basic functions are enabled. +/ 1: f_stat(), f_getfree(), f_unlink(), f_mkdir(), f_chmod(), f_utime(), +/ f_truncate() and f_rename() function are removed. +/ 2: f_opendir(), f_readdir() and f_closedir() are removed in addition to 1. +/ 3: f_lseek() function is removed in addition to 2. */ + + +#define _USE_STRFUNC 2 /* 0:Disable or 1-2:Enable */ +/* To enable string functions, set _USE_STRFUNC to 1 or 2. */ + + +#define _USE_MKFS 1 /* 0:Disable or 1:Enable */ +/* To enable f_mkfs() function, set _USE_MKFS to 1 and set _FS_READONLY to 0 */ + + +#define _USE_FASTSEEK 0 /* 0:Disable or 1:Enable */ +/* To enable fast seek feature, set _USE_FASTSEEK to 1. */ + + +#define _USE_LABEL 0 /* 0:Disable or 1:Enable */ +/* To enable volume label functions, set _USE_LAVEL to 1 */ + + +#define _USE_FORWARD 0 /* 0:Disable or 1:Enable */ +/* To enable f_forward() function, set _USE_FORWARD to 1 and set _FS_TINY to 1. */ + + +/*---------------------------------------------------------------------------/ +/ Locale and Namespace Configurations +/---------------------------------------------------------------------------*/ + +#define _CODE_PAGE 1252 +/* The _CODE_PAGE specifies the OEM code page to be used on the target system. +/ Incorrect setting of the code page can cause a file open failure. +/ +/ 932 - Japanese Shift_JIS (DBCS, OEM, Windows) +/ 936 - Simplified Chinese GBK (DBCS, OEM, Windows) +/ 949 - Korean (DBCS, OEM, Windows) +/ 950 - Traditional Chinese Big5 (DBCS, OEM, Windows) +/ 1250 - Central Europe (Windows) +/ 1251 - Cyrillic (Windows) +/ 1252 - Latin 1 (Windows) +/ 1253 - Greek (Windows) +/ 1254 - Turkish (Windows) +/ 1255 - Hebrew (Windows) +/ 1256 - Arabic (Windows) +/ 1257 - Baltic (Windows) +/ 1258 - Vietnam (OEM, Windows) +/ 437 - U.S. (OEM) +/ 720 - Arabic (OEM) +/ 737 - Greek (OEM) +/ 775 - Baltic (OEM) +/ 850 - Multilingual Latin 1 (OEM) +/ 858 - Multilingual Latin 1 + Euro (OEM) +/ 852 - Latin 2 (OEM) +/ 855 - Cyrillic (OEM) +/ 866 - Russian (OEM) +/ 857 - Turkish (OEM) +/ 862 - Hebrew (OEM) +/ 874 - Thai (OEM, Windows) +/ 1 - ASCII (Valid for only non-LFN configuration) */ + + +#define _USE_LFN 2 /* 0 to 3 */ +#define _MAX_LFN 255 /* Maximum LFN length to handle (12 to 255) */ +/* The _USE_LFN option switches the LFN feature. +/ +/ 0: Disable LFN feature. _MAX_LFN has no effect. +/ 1: Enable LFN with static working buffer on the BSS. Always NOT thread-safe. +/ 2: Enable LFN with dynamic working buffer on the STACK. +/ 3: Enable LFN with dynamic working buffer on the HEAP. +/ +/ When enable LFN feature, Unicode handling functions ff_convert() and ff_wtoupper() +/ function must be added to the project. +/ The LFN working buffer occupies (_MAX_LFN + 1) * 2 bytes. When use stack for the +/ working buffer, take care on stack overflow. When use heap memory for the working +/ buffer, memory management functions, ff_memalloc() and ff_memfree(), must be added +/ to the project. */ + + +#define _LFN_UNICODE 0 /* 0:ANSI/OEM or 1:Unicode */ +/* To switch the character encoding on the FatFs API (TCHAR) to Unicode, enable LFN +/ feature and set _LFN_UNICODE to 1. This option affects behavior of string I/O +/ functions. This option must be 0 when LFN feature is not enabled. */ + + +#define _STRF_ENCODE 3 /* 0:ANSI/OEM, 1:UTF-16LE, 2:UTF-16BE, 3:UTF-8 */ +/* When Unicode API is enabled by _LFN_UNICODE option, this option selects the character +/ encoding on the file to be read/written via string I/O functions, f_gets(), f_putc(), +/ f_puts and f_printf(). This option has no effect when Unicode API is not enabled. */ + + +#define _FS_RPATH 2 /* 0 to 2 */ +/* The _FS_RPATH option configures relative path feature. +/ +/ 0: Disable relative path feature and remove related functions. +/ 1: Enable relative path. f_chdrive() and f_chdir() function are available. +/ 2: f_getcwd() function is available in addition to 1. +/ +/ Note that output of the f_readdir() fnction is affected by this option. */ + + +/*---------------------------------------------------------------------------/ +/ Drive/Volume Configurations +/---------------------------------------------------------------------------*/ + +#define _VOLUMES 1 +/* Number of volumes (logical drives) to be used. */ + + +#define _STR_VOLUME_ID 0 /* 0:Use only 0-9 for drive ID, 1:Use strings for drive ID */ +#define _VOLUME_STRS "RAM","NAND","CF","SD1","SD2","USB1","USB2","USB3" +/* When _STR_VOLUME_ID is set to 1, also pre-defined strings can be used as drive +/ number in the path name. _VOLUME_STRS defines the drive ID strings for each logical +/ drives. Number of items must be equal to _VOLUMES. Valid characters for the drive ID +/ strings are: 0-9 and A-Z. */ + + +#define _MULTI_PARTITION 0 /* 0:Single partition, 1:Enable multiple partition */ +/* By default(0), each logical drive number is bound to the same physical drive number +/ and only a FAT volume found on the physical drive is mounted. When it is set to 1, +/ each logical drive number is bound to arbitrary drive/partition listed in VolToPart[]. +*/ + + +#define _MIN_SS 512 +#define _MAX_SS 512 +/* These options configure the range of sector size to be supported. (512, 1024, 2048 or +/ 4096) Always set both 512 for most systems, all memory card and harddisk. But a larger +/ value may be required for on-board flash memory and some type of optical media. +/ When _MAX_SS is larger than _MIN_SS, FatFs is configured to variable sector size and +/ GET_SECTOR_SIZE command must be implemented to the disk_ioctl() function. */ + + +#define _USE_ERASE 1 /* 0:Disable or 1:Enable */ +/* To enable sector erase feature, set _USE_ERASE to 1. Also CTRL_ERASE_SECTOR command +/ should be added to the disk_ioctl() function. */ + + +#define _FS_NOFSINFO 0 /* 0 to 3 */ +/* If you need to know correct free space on the FAT32 volume, set bit 0 of this option +/ and f_getfree() function at first time after volume mount will force a full FAT scan. +/ Bit 1 controls the last allocated cluster number as bit 0. +/ +/ bit0=0: Use free cluster count in the FSINFO if available. +/ bit0=1: Do not trust free cluster count in the FSINFO. +/ bit1=0: Use last allocated cluster number in the FSINFO if available. +/ bit1=1: Do not trust last allocated cluster number in the FSINFO. +*/ + + + +/*---------------------------------------------------------------------------/ +/ System Configurations +/---------------------------------------------------------------------------*/ + +#define _FS_REENTRANT 1 /* 0:Disable or 1:Enable */ +#define _FS_TIMEOUT MS2ST(1000) /* Timeout period in unit of time tick */ +#define _SYNC_t semaphore_t* /* O/S dependent sync object type. e.g. HANDLE, OS_EVENT*, ID, SemaphoreHandle_t and etc.. */ +/* The _FS_REENTRANT option switches the re-entrancy (thread safe) of the FatFs module. +/ +/ 0: Disable re-entrancy. _FS_TIMEOUT and _SYNC_t have no effect. +/ 1: Enable re-entrancy. Also user provided synchronization handlers, +/ ff_req_grant(), ff_rel_grant(), ff_del_syncobj() and ff_cre_syncobj() +/ function must be added to the project. +*/ + + +#define _WORD_ACCESS 1 /* 0 or 1 */ +/* The _WORD_ACCESS option is an only platform dependent option. It defines +/ which access method is used to the word data on the FAT volume. +/ +/ 0: Byte-by-byte access. Always compatible with all platforms. +/ 1: Word access. Do not choose this unless under both the following conditions. +/ +/ * Address misaligned memory access is always allowed for ALL instructions. +/ * Byte order on the memory is little-endian. +/ +/ If it is the case, _WORD_ACCESS can also be set to 1 to improve performance and +/ reduce code size. Following table shows an example of some processor types. +/ +/ ARM7TDMI 0 ColdFire 0 V850E2 0 +/ Cortex-M3 0 Z80 0/1 V850ES 0/1 +/ Cortex-M0 0 RX600(LE) 0/1 TLCS-870 0/1 +/ AVR 0/1 RX600(BE) 0 TLCS-900 0/1 +/ AVR32 0 RL78 0 R32C 0 +/ PIC18 0/1 SH-2 0 M16C 0/1 +/ PIC24 0 H8S 0 MSP430 0 +/ PIC32 0 H8/300H 0 x86 0/1 +*/ + + + + +#define _FS_LOCK 0 /* 0:Disable or >=1:Enable */ +/* To enable file lock control feature, set _FS_LOCK to non-zero value. +/ The value defines how many files/sub-directories can be opened simultaneously +/ with file lock control. This feature uses bss _FS_LOCK * 12 bytes. +/ +/ IMPORTANT NOTE: +/ For Paparazzi, we don't need file locking since all file are written sequentially +/ from one thread (thdSdLog) +/ +*/ + + + +#endif /* _FFCONF */ diff --git a/sw/airborne/boards/px4fmu/chibios/v2.4/mcuconf.h b/sw/airborne/boards/px4fmu/chibios/v2.4/mcuconf.h new file mode 100644 index 0000000000..a43c196aee --- /dev/null +++ b/sw/airborne/boards/px4fmu/chibios/v2.4/mcuconf.h @@ -0,0 +1,396 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _MCUCONF_H_ +#define _MCUCONF_H_ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 24 +#define STM32_PLLN_VALUE 336 +#define STM32_PLLP_VALUE 2 +#define STM32_PLLQ_VALUE 7 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 +#define STM32_BKPRAM_ENABLE FALSE + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV8 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#if USE_CAN1 +#define STM32_CAN_USE_CAN1 TRUE +#else +#define STM32_CAN_USE_CAN1 FALSE +#endif +#if USE_CAN2 +#define STM32_CAN_USE_CAN2 TRUE +#else +#define STM32_CAN_USE_CAN2 FALSE +#endif +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#define STM32_DAC_USE_DAC1_CH1 FALSE +#define STM32_DAC_USE_DAC1_CH2 FALSE +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#if USE_I2C1 +#define STM32_I2C_USE_I2C1 TRUE +#else +#define STM32_I2C_USE_I2C1 FALSE +#endif +#if USE_I2C2 +#define STM32_I2C_USE_I2C2 TRUE +#else +#define STM32_I2C_USE_I2C2 FALSE +#endif +#if USE_I2C3 +#define STM32_I2C_USE_I2C3 TRUE +#else +#define STM32_I2C_USE_I2C3 FALSE +#endif +#define STM32_I2C_BUSY_TIMEOUT 50 +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 TRUE +#ifdef USE_PWM_INPUT2 +#define STM32_ICU_USE_TIM2 TRUE +#else +#define STM32_ICU_USE_TIM2 FALSE +#endif +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 TRUE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#ifndef STM32_PWM_USE_TIM2 +#define STM32_PWM_USE_TIM2 TRUE +#endif +#ifndef STM32_PWM_USE_TIM3 +#define STM32_PWM_USE_TIM3 TRUE +#endif +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 FALSE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#if USE_UART1 +#define STM32_SERIAL_USE_USART1 TRUE +#else +#define STM32_SERIAL_USE_USART1 FALSE +#endif +#if USE_UART2 +#define STM32_SERIAL_USE_USART2 TRUE +#else +#define STM32_SERIAL_USE_USART2 FALSE +#endif +#if USE_UART3 +#define STM32_SERIAL_USE_USART3 TRUE +#else +#define STM32_SERIAL_USE_USART3 FALSE +#endif +#if USE_UART4 +#define STM32_SERIAL_USE_UART4 TRUE +#else +#define STM32_SERIAL_USE_UART4 FALSE +#endif +#if USE_UART5 +#define STM32_SERIAL_USE_UART5 TRUE +#else +#define STM32_SERIAL_USE_UART5 FALSE +#endif +#if USE_UART6 +#define STM32_SERIAL_USE_USART6 TRUE +#else +#define STM32_SERIAL_USE_USART6 FALSE +#endif +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 12 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#if USE_SPI1 +#define STM32_SPI_USE_SPI1 TRUE +#else +#define STM32_SPI_USE_SPI1 FALSE +#endif +#if USE_SPI2 +#define STM32_SPI_USE_SPI2 TRUE +#else +#define STM32_SPI_USE_SPI2 FALSE +#endif +#if USE_SPI3 +#define STM32_SPI_USE_SPI3 TRUE +#else +#define STM32_SPI_USE_SPI3 FALSE +#endif +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + +/* + * ST driver system settings. + */ +#define STM32_ST_IRQ_PRIORITY 8 +#define STM32_ST_USE_TIMER 2 + +/* + * UART driver system settings. + */ +#define STM32_UART_USE_USART1 FALSE +#define STM32_UART_USE_USART2 FALSE +#define STM32_UART_USE_USART3 FALSE +#define STM32_UART_USE_UART4 FALSE +#define STM32_UART_USE_UART5 FALSE +#define STM32_UART_USE_USART6 FALSE +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) // Not used: conflict SPI1 +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_UART_UART4_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_UART_UART4_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_UART5_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_UART_UART5_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 6) +#define STM32_UART_USART1_IRQ_PRIORITY 12 +#define STM32_UART_USART2_IRQ_PRIORITY 12 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_UART4_IRQ_PRIORITY 12 +#define STM32_UART_UART5_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 12 +#define STM32_UART_USART1_DMA_PRIORITY 1 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_UART4_DMA_PRIORITY 0 +#define STM32_UART_UART5_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#define STM32_USB_USE_OTG1 TRUE // FS, DFU_BOOT +#define STM32_USB_USE_OTG2 FALSE // HS +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 512 +#define STM32_USB_OTG_THREAD_PRIO HIGHPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 256 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + + +/* + * SDC driver system settings. + */ +#define STM32_SDC_SDIO_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SDC_SDIO_DMA_PRIORITY 3 +#define STM32_SDC_SDIO_IRQ_PRIORITY 9 +#define STM32_SDC_CLOCK_ACTIVATION_DELAY 10 +#define STM32_SDC_SDIO_UNALIGNED_SUPPORT FALSE +#define STM32_SDC_WRITE_TIMEOUT_MS 250 +#define STM32_SDC_READ_TIMEOUT_MS 15 +#define SDLOG_ALL_BUFFERS_SIZE 8192 +#define SDLOG_MAX_MESSAGE_LEN 252 +#define SDLOG_QUEUE_BUCKETS 1024 + +/* + * workaround hardware bug in REV.A revision of old STM32F4 (sold in 2012, early 2013) + */ + +#define STM32_USE_REVISION_A_FIX 1 + +#endif /* _MCUCONF_H_ */ diff --git a/sw/airborne/boards/vms_ecu/chibios/v1.0/board.c b/sw/airborne/boards/vms_ecu/chibios/v1.0/board.c new file mode 100644 index 0000000000..777c0bc89f --- /dev/null +++ b/sw/airborne/boards/vms_ecu/chibios/v1.0/board.c @@ -0,0 +1,124 @@ +/* + ChibiOS - Copyright (C) 2006..2015 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#include "hal.h" + +#if HAL_USE_PAL || defined(__DOXYGEN__) +/** + * @brief PAL setup. + * @details Digital I/O ports static configuration as defined in @p board.h. + * This variable is used by the HAL when initializing the PAL driver. + */ +const PALConfig pal_default_config = { +#if STM32_HAS_GPIOA + {VAL_GPIOA_MODER, VAL_GPIOA_OTYPER, VAL_GPIOA_OSPEEDR, VAL_GPIOA_PUPDR, + VAL_GPIOA_ODR, VAL_GPIOA_AFRL, VAL_GPIOA_AFRH}, +#endif +#if STM32_HAS_GPIOB + {VAL_GPIOB_MODER, VAL_GPIOB_OTYPER, VAL_GPIOB_OSPEEDR, VAL_GPIOB_PUPDR, + VAL_GPIOB_ODR, VAL_GPIOB_AFRL, VAL_GPIOB_AFRH}, +#endif +#if STM32_HAS_GPIOC + {VAL_GPIOC_MODER, VAL_GPIOC_OTYPER, VAL_GPIOC_OSPEEDR, VAL_GPIOC_PUPDR, + VAL_GPIOC_ODR, VAL_GPIOC_AFRL, VAL_GPIOC_AFRH}, +#endif +#if STM32_HAS_GPIOD + {VAL_GPIOD_MODER, VAL_GPIOD_OTYPER, VAL_GPIOD_OSPEEDR, VAL_GPIOD_PUPDR, + VAL_GPIOD_ODR, VAL_GPIOD_AFRL, VAL_GPIOD_AFRH}, +#endif +#if STM32_HAS_GPIOE + {VAL_GPIOE_MODER, VAL_GPIOE_OTYPER, VAL_GPIOE_OSPEEDR, VAL_GPIOE_PUPDR, + VAL_GPIOE_ODR, VAL_GPIOE_AFRL, VAL_GPIOE_AFRH}, +#endif +#if STM32_HAS_GPIOF + {VAL_GPIOF_MODER, VAL_GPIOF_OTYPER, VAL_GPIOF_OSPEEDR, VAL_GPIOF_PUPDR, + VAL_GPIOF_ODR, VAL_GPIOF_AFRL, VAL_GPIOF_AFRH}, +#endif +#if STM32_HAS_GPIOG + {VAL_GPIOG_MODER, VAL_GPIOG_OTYPER, VAL_GPIOG_OSPEEDR, VAL_GPIOG_PUPDR, + VAL_GPIOG_ODR, VAL_GPIOG_AFRL, VAL_GPIOG_AFRH}, +#endif +#if STM32_HAS_GPIOH + {VAL_GPIOH_MODER, VAL_GPIOH_OTYPER, VAL_GPIOH_OSPEEDR, VAL_GPIOH_PUPDR, + VAL_GPIOH_ODR, VAL_GPIOH_AFRL, VAL_GPIOH_AFRH}, +#endif +#if STM32_HAS_GPIOI + {VAL_GPIOI_MODER, VAL_GPIOI_OTYPER, VAL_GPIOI_OSPEEDR, VAL_GPIOI_PUPDR, + VAL_GPIOI_ODR, VAL_GPIOI_AFRL, VAL_GPIOI_AFRH} +#endif +}; +#endif + +/** + * @brief Early initialization code. + * @details This initialization must be performed just after stack setup + * and before any other initialization. + */ +void __early_init(void) { + + stm32_clock_init(); +} + +#if HAL_USE_SDC || defined(__DOXYGEN__) +/** + * @brief SDC card detection. + */ +bool sdc_lld_is_card_inserted(SDCDriver *sdcp) { + + (void)sdcp; + return !palReadPad(GPIOB, GPIOB_SDIO_DETECT); +} + +/** + * @brief SDC card write protection detection. + */ +bool sdc_lld_is_write_protected(SDCDriver *sdcp) { + + (void)sdcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif /* HAL_USE_SDC */ + +#if HAL_USE_MMC_SPI || defined(__DOXYGEN__) +/** + * @brief MMC_SPI card detection. + */ +bool mmc_lld_is_card_inserted(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return true; +} + +/** + * @brief MMC_SPI card write protection detection. + */ +bool mmc_lld_is_write_protected(MMCDriver *mmcp) { + + (void)mmcp; + /* TODO: Fill the implementation.*/ + return false; +} +#endif + +/** + * @brief Board-specific initialization code. + * @todo Add your board-specific code, if any. + */ +void boardInit(void) { +} + diff --git a/sw/airborne/boards/vms_ecu/chibios/v1.0/board.h b/sw/airborne/boards/vms_ecu/chibios/v1.0/board.h new file mode 100644 index 0000000000..72110cdeb7 --- /dev/null +++ b/sw/airborne/boards/vms_ecu/chibios/v1.0/board.h @@ -0,0 +1,1345 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +#ifndef _BOARD_H_ +#define _BOARD_H_ + +/* + * Setup for STMicroelectronics STM32F4-Lisa MX. + */ + +/* + * Board identifier. + */ +#define BOARD_ST_STM32F4_ECU +#define BOARD_NAME "STMicroelectronics STM32F4-Ecu" + + +/* + * Board oscillators-related settings. + * NOTE: LSE not fitted. + */ +#if !defined(STM32_LSECLK) +#define STM32_LSECLK 0 +#endif + +#if !defined(STM32_HSECLK) +#define STM32_HSECLK 25000000 +#endif + + +/* + * Board voltages. + * Required for performance limits calculation. + */ +#define STM32_VDD 330 + +/* + * MCU type as defined in the ST header file stm32f4xx.h. + */ +#define STM32F407xx + + +/* + * I/O ports initial setup, this configuration is established soon after reset + * in the initialization code. + * Please refer to the STM32 Reference Manual for details. + */ +#define PIN_MODE_INPUT(n) (0U << ((n) * 2U)) +#define PIN_MODE_OUTPUT(n) (1U << ((n) * 2U)) +#define PIN_MODE_ALTERNATE(n) (2U << ((n) * 2U)) +#define PIN_MODE_ANALOG(n) (3U << ((n) * 2U)) +#define PIN_ODR_LOW(n) (0U << (n)) +#define PIN_ODR_HIGH(n) (1U << (n)) +#define PIN_OTYPE_PUSHPULL(n) (0U << (n)) +#define PIN_OTYPE_OPENDRAIN(n) (1U << (n)) +#define PIN_OSPEED_2M(n) (0U << ((n) * 2U)) +#define PIN_OSPEED_25M(n) (1U << ((n) * 2U)) +#define PIN_OSPEED_50M(n) (2U << ((n) * 2U)) +#define PIN_OSPEED_100M(n) (3U << ((n) * 2U)) +#define PIN_PUPDR_FLOATING(n) (0U << ((n) * 2U)) +#define PIN_PUPDR_PULLUP(n) (1U << ((n) * 2U)) +#define PIN_PUPDR_PULLDOWN(n) (2U << ((n) * 2U)) +#define PIN_AFIO_AF(n, v) ((v) << (((n) % 8U) * 4U)) + +/* + * Port A setup. + * + * PA0 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PA1 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PA2 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PA3 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PA4 - Analog output (DAC1) - set up as INPUT ANALOG (per reference manual) + * PA5 - Analog output (DAC2) - set up as INPUT ANALOG (per reference manual) + * PA6 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PA7 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PA8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PA9 - Alternate output (UART1_Tx) + * PA10 - Alternate input (UART1_Rx) + * PA11 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PA12 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PA13 - Digital input (JTAG_TMS/SWDIO) + * PA14 - Digital input (JTAG_TCK/SWCLCK) + * PA15 - Digital input (JTAG_TDI) + */ +#define VAL_GPIOA_MODER (PIN_MODE_INPUT(0)| \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_ALTERNATE(9) | \ + PIN_MODE_ALTERNATE(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_ALTERNATE(13) | \ + PIN_MODE_ALTERNATE(14) | \ + PIN_MODE_ALTERNATE(15)) +#define VAL_GPIOA_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOA_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOA_PUPDR (PIN_PUPDR_PULLDOWN(0) | \ + PIN_PUPDR_PULLDOWN(1) | \ + PIN_PUPDR_PULLDOWN(2) | \ + PIN_PUPDR_PULLDOWN(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_PULLDOWN(6) | \ + PIN_PUPDR_PULLDOWN(7) | \ + PIN_PUPDR_PULLDOWN(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_PULLDOWN(11) | \ + PIN_PUPDR_PULLDOWN(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOA_ODR (PIN_ODR_LOW(0) | \ + PIN_ODR_LOW(1) | \ + PIN_ODR_LOW(2) | \ + PIN_ODR_LOW(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_LOW(6) | \ + PIN_ODR_LOW(7) | \ + PIN_ODR_LOW(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_LOW(10) | \ + PIN_ODR_LOW(11) | \ + PIN_ODR_LOW(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOA_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOA_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 7) | \ + PIN_AFIO_AF(10, 7) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * Port B setup: + * PB0 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PB1 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PB2 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PB3 - Digital input (JTAG_TDO/SWD) + * PB4 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PB5 - Alternate Digital input. (CAN2_RX) + * PB6 - Alternate Open Drain output 50MHz. (CAN2_TX) + * PB7 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PB8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PB9 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PB10 - Alternate Open Drain output 2MHz.(I2C2_SCL) + * PB11 - Alternate Open Drain output 2MHz.(I2C2_SDA) + * PB12 - Push Pull output 50MHz. (IMU_ACC_SPI2_CS) + * PB13 - Alternate Push Pull output 50MHz (IMU_SPI2_SCK) + * PB14 - Digital input (IMU_SPI2_MISO) + * PB15 - Alternate Push Pull output 50MHz (IMU_SPI2_MOSI) + */ +#define VAL_GPIOB_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_ALTERNATE(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_ALTERNATE(5) | \ + PIN_MODE_ALTERNATE(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_ALTERNATE(10) | \ + PIN_MODE_ALTERNATE(11) | \ + PIN_MODE_OUTPUT(12) | \ + PIN_MODE_ALTERNATE(13) | \ + PIN_MODE_ALTERNATE(14) | \ + PIN_MODE_ALTERNATE(15)) +#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_OPENDRAIN(10) | \ + PIN_OTYPE_OPENDRAIN(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOB_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_50M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_2M(10) | \ + PIN_OSPEED_2M(11) | \ + PIN_OSPEED_50M(12) | \ + PIN_OSPEED_50M(13) | \ + PIN_OSPEED_50M(14) | \ + PIN_OSPEED_50M(15)) +#define VAL_GPIOB_PUPDR (PIN_PUPDR_PULLDOWN(0) | \ + PIN_PUPDR_PULLDOWN(1) | \ + PIN_PUPDR_PULLDOWN(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_PULLDOWN(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_PULLDOWN(7) | \ + PIN_PUPDR_PULLDOWN(8) | \ + PIN_PUPDR_PULLDOWN(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOB_ODR (PIN_ODR_LOW(0) | \ + PIN_ODR_LOW(1) | \ + PIN_ODR_LOW(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_LOW(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_LOW(7) | \ + PIN_ODR_LOW(8) | \ + PIN_ODR_LOW(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOB_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 9) | \ + PIN_AFIO_AF(6, 9) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOB_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 4) | \ + PIN_AFIO_AF(11, 4) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 5) | \ + PIN_AFIO_AF(14, 5) | \ + PIN_AFIO_AF(15, 5)) + +/* + * Port C setup: + * PC0 - Analog input (ADC1) + * PC1 - Analog input (ADC2) + * PC2 - Analog input (ADC3) + * PC3 - Analog input (ADC4) + * PC4 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PC5 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PC6 - Alternate Push Pull output 50MHz (UART6_TX) + * PC7 - Alternate input (UART7_RX) + * PC8 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PC9 - Push Pull output 50MHz (SPI3_NSS) + * PC10 - Alternate Push Pull output 50MHz (SPI3_SCK) + * PC11 - Alternate Digital input (SPI3_MISO) + * PC12 - Alternate Push Pull output 50MHz (SPI3_MOSI) + * PC13 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PC14 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + * PC15 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected) + */ +#define VAL_GPIOC_MODER (PIN_MODE_INPUT(0) |\ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_ALTERNATE(6) | \ + PIN_MODE_ALTERNATE(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_OUTPUT(9) | \ + PIN_MODE_ALTERNATE(10) | \ + PIN_MODE_ALTERNATE(11) | \ + PIN_MODE_ALTERNATE(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOC_OTYPER (PIN_OTYPE_PUSHPULL(0) |\ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOC_OSPEEDR (PIN_OSPEED_100M(0) |\ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_50M(6) | \ + PIN_OSPEED_50M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_50M(9) | \ + PIN_OSPEED_50M(10) | \ + PIN_OSPEED_50M(11) | \ + PIN_OSPEED_50M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOC_PUPDR (PIN_PUPDR_FLOATING(0) |\ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_PULLDOWN(4) | \ + PIN_PUPDR_PULLDOWN(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_PULLDOWN(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_PULLDOWN(13) | \ + PIN_PUPDR_PULLDOWN(14) | \ + PIN_PUPDR_PULLDOWN(15)) +#define VAL_GPIOC_ODR (PIN_ODR_LOW(0) | \ + PIN_ODR_LOW(1) | \ + PIN_ODR_LOW(2) | \ + PIN_ODR_LOW(3) | \ + PIN_ODR_LOW(4) | \ + PIN_ODR_LOW(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_LOW(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_LOW(13) | \ + PIN_ODR_LOW(14) | \ + PIN_ODR_LOW(15)) +#define VAL_GPIOC_AFRL (PIN_AFIO_AF(0, 0) |\ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 8) | \ + PIN_AFIO_AF(7, 8)) +#define VAL_GPIOC_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 6) | \ + PIN_AFIO_AF(11, 6) | \ + PIN_AFIO_AF(12, 6) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * Port D setup: + * PD0 - Alternate Digital input. (CAN1_RX). + * PD1 - Alternate Open Drain output 50MHz (CAN1_TX). + * PD2 - Digital input (CARD_DETECT). + * PD3 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD4 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD5 - Alternate Push Pull output 50MHz. (UART2_TX). + * PD6 - Alternate Digital input. (UART2_RX). + * PD7 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PD8 - Alternate Push Pull output 50MHz. (UART3_TX). + * PD9 - Alternate Digital input. (UART3_RX). + * PD10 - Digital output. (DOUT_LS1). + * PD11 - Digital output. (DOUT_LS2). + * PD12 - Digital output. (DOUT_LS3). + * PD13 - Digital output. (DOUT_LS4). + * PD14 - Digital output. (DOUT_HS1). + * PD15 - Digital output. (DOUT_HS2). + */ +#define VAL_GPIOD_MODER (PIN_MODE_ALTERNATE(0) | \ + PIN_MODE_ALTERNATE(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_ALTERNATE(5) | \ + PIN_MODE_ALTERNATE(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_ALTERNATE(8) | \ + PIN_MODE_ALTERNATE(9) | \ + PIN_MODE_OUTPUT(10) | \ + PIN_MODE_OUTPUT(11) | \ + PIN_MODE_OUTPUT(12) | \ + PIN_MODE_OUTPUT(13) | \ + PIN_MODE_OUTPUT(14) | \ + PIN_MODE_OUTPUT(15)) +#define VAL_GPIOD_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) |\ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOD_OSPEEDR (PIN_OSPEED_50M(0) | \ + PIN_OSPEED_50M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_50M(5) | \ + PIN_OSPEED_50M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_50M(8) | \ + PIN_OSPEED_50M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOD_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) |\ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOD_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_LOW(3) | \ + PIN_ODR_LOW(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_LOW(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_LOW(10) | \ + PIN_ODR_LOW(11) | \ + PIN_ODR_LOW(12) | \ + PIN_ODR_LOW(13) | \ + PIN_ODR_LOW(14) | \ + PIN_ODR_LOW(15)) +#define VAL_GPIOD_AFRL (PIN_AFIO_AF(0, 9) | \ + PIN_AFIO_AF(1, 9) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 7) | \ + PIN_AFIO_AF(6, 7) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOD_AFRH (PIN_AFIO_AF(8, 7) | \ + PIN_AFIO_AF(9, 7) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * Port E setup: + * PE0 - Digital input (IMU_MAG_DRDY) + * PE1 - Digital input (IMU_ACC_DRDY) + * PE2 - Digital input (IMU_GYRO_DRDY) + * PE3 - Push Pull output 50MHz. (IMU_GYRO_SS) + * PE4 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PE5 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PE6 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + * PE7 - Digital input. (DIN1). + * PE8 - Digital input. (DIN2). + * PE9 - Digital input. (DIN3). + * PE10 - Digital input. (DIN4). + * PE11 - Digital input. (DIN5). + * PE12 - Digital input. (DIN6). + * PE13 - Digital input. (DIN7). + * PE14 - Digital input. (DIN8). + * PE15 - Digital input with PullUp or PullDown resistor depending on ODR. (unconnected). + */ +#define VAL_GPIOE_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_OUTPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOE_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOE_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_50M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOE_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOE_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOE_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOE_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * GPIOF setup: + * + * PF0 - PF15 (input floating). + */ +#define VAL_GPIOF_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOF_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOF_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOF_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOF_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOF_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOF_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * GPIOG setup: + * + * PG0 - PG15 (input floating). + */ +#define VAL_GPIOG_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOG_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOG_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOG_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOG_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOG_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOG_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * GPIOH setup: + * + * PH0 - PH15 (input floating). + */ +#define VAL_GPIOH_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOH_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOH_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOH_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOH_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOH_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOH_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + +/* + * GPIOI setup: + * + * PI0 - PI15 (input floating). + */ +#define VAL_GPIOI_MODER (PIN_MODE_INPUT(0) | \ + PIN_MODE_INPUT(1) | \ + PIN_MODE_INPUT(2) | \ + PIN_MODE_INPUT(3) | \ + PIN_MODE_INPUT(4) | \ + PIN_MODE_INPUT(5) | \ + PIN_MODE_INPUT(6) | \ + PIN_MODE_INPUT(7) | \ + PIN_MODE_INPUT(8) | \ + PIN_MODE_INPUT(9) | \ + PIN_MODE_INPUT(10) | \ + PIN_MODE_INPUT(11) | \ + PIN_MODE_INPUT(12) | \ + PIN_MODE_INPUT(13) | \ + PIN_MODE_INPUT(14) | \ + PIN_MODE_INPUT(15)) +#define VAL_GPIOI_OTYPER (PIN_OTYPE_PUSHPULL(0) | \ + PIN_OTYPE_PUSHPULL(1) | \ + PIN_OTYPE_PUSHPULL(2) | \ + PIN_OTYPE_PUSHPULL(3) | \ + PIN_OTYPE_PUSHPULL(4) | \ + PIN_OTYPE_PUSHPULL(5) | \ + PIN_OTYPE_PUSHPULL(6) | \ + PIN_OTYPE_PUSHPULL(7) | \ + PIN_OTYPE_PUSHPULL(8) | \ + PIN_OTYPE_PUSHPULL(9) | \ + PIN_OTYPE_PUSHPULL(10) | \ + PIN_OTYPE_PUSHPULL(11) | \ + PIN_OTYPE_PUSHPULL(12) | \ + PIN_OTYPE_PUSHPULL(13) | \ + PIN_OTYPE_PUSHPULL(14) | \ + PIN_OTYPE_PUSHPULL(15)) +#define VAL_GPIOI_OSPEEDR (PIN_OSPEED_100M(0) | \ + PIN_OSPEED_100M(1) | \ + PIN_OSPEED_100M(2) | \ + PIN_OSPEED_100M(3) | \ + PIN_OSPEED_100M(4) | \ + PIN_OSPEED_100M(5) | \ + PIN_OSPEED_100M(6) | \ + PIN_OSPEED_100M(7) | \ + PIN_OSPEED_100M(8) | \ + PIN_OSPEED_100M(9) | \ + PIN_OSPEED_100M(10) | \ + PIN_OSPEED_100M(11) | \ + PIN_OSPEED_100M(12) | \ + PIN_OSPEED_100M(13) | \ + PIN_OSPEED_100M(14) | \ + PIN_OSPEED_100M(15)) +#define VAL_GPIOI_PUPDR (PIN_PUPDR_FLOATING(0) | \ + PIN_PUPDR_FLOATING(1) | \ + PIN_PUPDR_FLOATING(2) | \ + PIN_PUPDR_FLOATING(3) | \ + PIN_PUPDR_FLOATING(4) | \ + PIN_PUPDR_FLOATING(5) | \ + PIN_PUPDR_FLOATING(6) | \ + PIN_PUPDR_FLOATING(7) | \ + PIN_PUPDR_FLOATING(8) | \ + PIN_PUPDR_FLOATING(9) | \ + PIN_PUPDR_FLOATING(10) | \ + PIN_PUPDR_FLOATING(11) | \ + PIN_PUPDR_FLOATING(12) | \ + PIN_PUPDR_FLOATING(13) | \ + PIN_PUPDR_FLOATING(14) | \ + PIN_PUPDR_FLOATING(15)) +#define VAL_GPIOI_ODR (PIN_ODR_HIGH(0) | \ + PIN_ODR_HIGH(1) | \ + PIN_ODR_HIGH(2) | \ + PIN_ODR_HIGH(3) | \ + PIN_ODR_HIGH(4) | \ + PIN_ODR_HIGH(5) | \ + PIN_ODR_HIGH(6) | \ + PIN_ODR_HIGH(7) | \ + PIN_ODR_HIGH(8) | \ + PIN_ODR_HIGH(9) | \ + PIN_ODR_HIGH(10) | \ + PIN_ODR_HIGH(11) | \ + PIN_ODR_HIGH(12) | \ + PIN_ODR_HIGH(13) | \ + PIN_ODR_HIGH(14) | \ + PIN_ODR_HIGH(15)) +#define VAL_GPIOI_AFRL (PIN_AFIO_AF(0, 0) | \ + PIN_AFIO_AF(1, 0) | \ + PIN_AFIO_AF(2, 0) | \ + PIN_AFIO_AF(3, 0) | \ + PIN_AFIO_AF(4, 0) | \ + PIN_AFIO_AF(5, 0) | \ + PIN_AFIO_AF(6, 0) | \ + PIN_AFIO_AF(7, 0)) +#define VAL_GPIOI_AFRH (PIN_AFIO_AF(8, 0) | \ + PIN_AFIO_AF(9, 0) | \ + PIN_AFIO_AF(10, 0) | \ + PIN_AFIO_AF(11, 0) | \ + PIN_AFIO_AF(12, 0) | \ + PIN_AFIO_AF(13, 0) | \ + PIN_AFIO_AF(14, 0) | \ + PIN_AFIO_AF(15, 0)) + + +/* + * AHB_CLK + */ +#define AHB_CLK STM32_HCLK + + +/* + * LEDs + */ +/* 1 red, on PA8 */ +#ifndef USE_LED_1 +#define USE_LED_1 1 +#endif +#define LED_1_GPIO GPIOA +#define LED_1_GPIO_PIN 8 +#define LED_1_GPIO_ON gpio_clear +#define LED_1_GPIO_OFF gpio_set + +/* 2 green, shared with JTAG_TRST */ +#ifndef USE_LED_2 +#define USE_LED_2 1 +#endif +#define LED_2_GPIO GPIOB +#define LED_2_GPIO_PIN 4 +#define LED_2_GPIO_ON gpio_clear +#define LED_2_GPIO_OFF gpio_set + +/* 3 green, shared with ADC12 (ADC_6 on connector ANALOG2) */ +#ifndef USE_LED_3 +#define USE_LED_3 1 +#endif +#define LED_3_GPIO GPIOC +#define LED_3_GPIO_PIN 2 +#define LED_3_GPIO_ON gpio_clear +#define LED_3_GPIO_OFF gpio_set + +/* 4 red, shared with ADC15 (ADC_4 on connector ANALOG2) */ +#ifndef USE_LED_4 +#define USE_LED_4 1 +#endif +#define LED_4_GPIO GPIOC +#define LED_4_GPIO_PIN 5 +#define LED_4_GPIO_ON gpio_clear +#define LED_4_GPIO_OFF gpio_set + +/* 5 green, on PC15 */ +#ifndef USE_LED_5 +#define USE_LED_5 0 +#endif +#define LED_5_GPIO GPIOC +#define LED_5_GPIO_PIN 15 +#define LED_5_GPIO_ON gpio_set +#define LED_5_GPIO_OFF gpio_clear + +/* + * ADCs + */ +// AIN1 enabled by default +#ifndef USE_ADC_1 +#define USE_ADC_1 1 +#endif +#if USE_ADC_1 +#define AD1_1_CHANNEL ADC_CHANNEL_IN10 +#define ADC_1 AD1_1 +#define ADC_1_GPIO_PORT GPIOC +#define ADC_1_GPIO_PIN GPIO0 +#endif + +// AIN2 enabled by default +#ifndef USE_ADC_2 +#define USE_ADC_2 1 +#endif +#if USE_ADC_2 +#define AD1_2_CHANNEL ADC_CHANNEL_IN11 +#define ADC_2 AD1_2 +#define ADC_2_GPIO_PORT GPIOC +#define ADC_2_GPIO_PIN GPIO1 +#endif + +// AIN3 enabled by default +#ifndef USE_ADC_3 +#define USE_ADC_3 1 +#endif +#if USE_ADC_3 +#define AD1_3_CHANNEL ADC_CHANNEL_IN12 +#define ADC_3 AD1_3 +#define ADC_3_GPIO_PORT GPIOC +#define ADC_3_GPIO_PIN GPIO2 +#endif + +// AIN4 enabled by default +#ifndef USE_ADC_4 +#define USE_ADC_4 1 +#endif +#if USE_ADC_4 +#define AD1_4_CHANNEL ADC_CHANNEL_IN13 +#define ADC_4 AD1_4 +#define ADC_4_GPIO_PORT GPIOC +#define ADC_4_GPIO_PIN GPIO3 +#endif + + +// Internal Temperature sensor enabled by default +/* +#ifndef USE_ADC_5 +#define USE_ADC_5 1 +#define USE_ADC_SENSOR 1 +#endif +#if USE_ADC_5 +#define AD1_5_CHANNEL ADC_CHANNEL_SENSOR +#define ADC_5 AD1_5 +#define ADC_5_GPIO_PORT GPIOC // dummy pin +#define ADC_5_GPIO_PIN GPIO3 // dummy pin +#endif +*/ + +// Add board defines +#define AIN_1 AD1_1_CHANNEL +#define AIN_2 AD1_2_CHANNEL +#define AIN_3 AD1_3_CHANNEL +#define AIN_4 AD1_4_CHANNEL + +/* allow to define ADC_CHANNEL_VSUPPLY in the airframe file*/ +//#ifndef ADC_CHANNEL_VSUPPLY +//#define ADC_CHANNEL_VSUPPLY ADC_1 +//#endif + +//#define ADC_CHANNEL_CURRENT ADC_2 + +#define DefaultVoltageOfAdc(adc) (0.000805664*adc)//(0.004489*adc) +#define DefaultMilliAmpereOfAdc(adc) (0.004489*adc) + +/* + * PWM defines + */ +#ifndef USE_PWM0 +#define USE_PWM0 1 +#endif +#if USE_PWM0 +#define PWM_SERVO_0 0 +#define PWM_SERVO_0_GPIO GPIOB +#define PWM_SERVO_0_PIN GPIO0 +#define PWM_SERVO_0_AF GPIO_AF2 +#define PWM_SERVO_0_DRIVER PWMD3 +#define PWM_SERVO_0_CHANNEL 2 +#define PWM_SERVO_0_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_0_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM1 +#define USE_PWM1 1 +#endif +#if USE_PWM1 +#define PWM_SERVO_1 1 +#define PWM_SERVO_1_GPIO GPIOA +#define PWM_SERVO_1_PIN GPIO2 +#define PWM_SERVO_1_AF GPIO_AF1 +#define PWM_SERVO_1_DRIVER PWMD3 +#define PWM_SERVO_1_CHANNEL 2 +#define PWM_SERVO_1_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_1_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM2 +#define USE_PWM2 1 +#endif +#if USE_PWM2 +#define PWM_SERVO_2 2 +#define PWM_SERVO_2_GPIO GPIOB +#define PWM_SERVO_2_PIN GPIO5 +#define PWM_SERVO_2_AF GPIO_AF3 +#define PWM_SERVO_2_DRIVER PWMD3 +#define PWM_SERVO_2_CHANNEL 1 +#define PWM_SERVO_2_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_2_ACTIVE PWM_OUTPUT_DISABLED +#endif + +#ifndef USE_PWM3 +#define USE_PWM3 1 +#endif +#if USE_PWM3 +#define PWM_SERVO_3 3 +#define PWM_SERVO_3_GPIO GPIOB +#define PWM_SERVO_3_PIN GPIO4 +#define PWM_SERVO_3_AF GPIO_AF2 +#define PWM_SERVO_3_DRIVER PWMD3 +#define PWM_SERVO_3_CHANNEL 0 +#define PWM_SERVO_3_ACTIVE PWM_OUTPUT_ACTIVE_HIGH +#else +#define PWM_SERVO_3_ACTIVE PWM_OUTPUT_DISABLED +#endif + + +/** + * PPM radio defines + */ +#define RC_PPM_TICKS_PER_USEC 6 +#define PPM_TIMER_FREQUENCY 6000000 +#define PPM_CHANNEL ICU_CHANNEL_3 +#define PPM_TIMER ICUD1 + +/** + * I2C defines + */ +#define I2C1_CLOCK_SPEED 400000 +#define I2C1_CFG_DEF { \ + OPMODE_I2C, \ + I2C1_CLOCK_SPEED, \ + FAST_DUTY_CYCLE_2, \ + } + +#define I2C2_CLOCK_SPEED 400000 +#define I2C2_CFG_DEF { \ + OPMODE_I2C, \ + I2C2_CLOCK_SPEED, \ + FAST_DUTY_CYCLE_2, \ + } + +/** + * SPI Config + */ +#define SPI1_GPIO_AF GPIO_AF5 +#define SPI1_GPIO_PORT_MISO GPIOA +#define SPI1_GPIO_MISO GPIO6 +#define SPI1_GPIO_PORT_MOSI GPIOA +#define SPI1_GPIO_MOSI GPIO7 +#define SPI1_GPIO_PORT_SCK GPIOA +#define SPI1_GPIO_SCK GPIO5 + +// SLAVE0 on SPI connector +#define SPI_SELECT_SLAVE0_PORT GPIOB +#define SPI_SELECT_SLAVE0_PIN 9 +// SLAVE1 on AUX1 +#define SPI_SELECT_SLAVE1_PORT GPIOB +#define SPI_SELECT_SLAVE1_PIN 1 +// SLAVE2 on AUX2 +#define SPI_SELECT_SLAVE2_PORT GPIOC +#define SPI_SELECT_SLAVE2_PIN 5 +// SLAVE3 on AUX3 +#define SPI_SELECT_SLAVE3_PORT GPIOC +#define SPI_SELECT_SLAVE3_PIN 4 +// SLAVE4 on AUX4 +#define SPI_SELECT_SLAVE4_PORT GPIOB +#define SPI_SELECT_SLAVE4_PIN 5 + +/** + * Baro + * + * Apparently needed for backwards compatibility + * with the ancient onboard baro boards + */ +#ifndef USE_BARO_BOARD +#define USE_BARO_BOARD 0 +#endif + +/* + * Actuators for fixedwing + */ + /* Default actuators driver */ +#define DEFAULT_ACTUATORS "subsystems/actuators/actuators_pwm.h" +#define ActuatorDefaultSet(_x,_y) ActuatorPwmSet(_x,_y) +#define ActuatorsDefaultInit() ActuatorsPwmInit() +#define ActuatorsDefaultCommit() ActuatorsPwmCommit() + +#if !defined(_FROM_ASM_) +#ifdef __cplusplus +extern "C" { +#endif + void boardInit(void); +#ifdef __cplusplus +} +#endif +#endif /* _FROM_ASM_ */ + +#endif /* _BOARD_H_ */ diff --git a/sw/airborne/boards/vms_ecu/chibios/v1.0/board.mk b/sw/airborne/boards/vms_ecu/chibios/v1.0/board.mk new file mode 100644 index 0000000000..5a109515f4 --- /dev/null +++ b/sw/airborne/boards/vms_ecu/chibios/v1.0/board.mk @@ -0,0 +1,20 @@ +# +# ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio +# +# Licensed under the Apache License, Version 2.0 (the "License"); +# you may not use this file except in compliance with the License. +# You may obtain a copy of the License at +# +# http://www.apache.org/licenses/LICENSE-2.0 +# +# Unless required by applicable law or agreed to in writing, software +# distributed under the License is distributed on an "AS IS" BASIS, +# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. +# See the License for the specific language governing permissions and +# limitations under the License. +# +# Required include directories +BOARDINC = $(CHIBIOS_BOARD_DIR) + +# List of all the board related files. +BOARDSRC = ${BOARDINC}/board.c diff --git a/sw/airborne/boards/vms_ecu/chibios/v1.0/mcuconf.h b/sw/airborne/boards/vms_ecu/chibios/v1.0/mcuconf.h new file mode 100644 index 0000000000..035d5259f8 --- /dev/null +++ b/sw/airborne/boards/vms_ecu/chibios/v1.0/mcuconf.h @@ -0,0 +1,374 @@ +/* + ChibiOS/RT - Copyright (C) 2006-2013 Giovanni Di Sirio + + Licensed under the Apache License, Version 2.0 (the "License"); + you may not use this file except in compliance with the License. + You may obtain a copy of the License at + + http://www.apache.org/licenses/LICENSE-2.0 + + Unless required by applicable law or agreed to in writing, software + distributed under the License is distributed on an "AS IS" BASIS, + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. + See the License for the specific language governing permissions and + limitations under the License. +*/ + +/* + * STM32F4xx drivers configuration. + * The following settings override the default settings present in + * the various device driver implementation headers. + * Note that the settings for each driver only have effect if the whole + * driver is enabled in halconf.h. + * + * IRQ priorities: + * 15...0 Lowest...Highest. + * + * DMA priorities: + * 0...3 Lowest...Highest. + */ + +#define STM32F4xx_MCUCONF + +/* + * HAL driver system settings. + */ +#define STM32_NO_INIT FALSE +#define STM32_HSI_ENABLED TRUE +#define STM32_LSI_ENABLED TRUE +#define STM32_HSE_ENABLED TRUE +#define STM32_LSE_ENABLED FALSE +#define STM32_CLOCK48_REQUIRED TRUE +#define STM32_SW STM32_SW_PLL +#define STM32_PLLSRC STM32_PLLSRC_HSE +#define STM32_PLLM_VALUE 25 +#define STM32_PLLN_VALUE 432 +#define STM32_PLLP_VALUE 4 +#define STM32_PLLQ_VALUE 9 +#define STM32_HPRE STM32_HPRE_DIV1 +#define STM32_PPRE1 STM32_PPRE1_DIV4 +#define STM32_PPRE2 STM32_PPRE2_DIV2 +#define STM32_RTCSEL STM32_RTCSEL_LSI +#define STM32_RTCPRE_VALUE 8 +#define STM32_MCO1SEL STM32_MCO1SEL_HSI +#define STM32_MCO1PRE STM32_MCO1PRE_DIV1 +#define STM32_MCO2SEL STM32_MCO2SEL_SYSCLK +#define STM32_MCO2PRE STM32_MCO2PRE_DIV5 +#define STM32_I2SSRC STM32_I2SSRC_CKIN +#define STM32_PLLI2SN_VALUE 192 +#define STM32_PLLI2SR_VALUE 5 +#define STM32_PVD_ENABLE FALSE +#define STM32_PLS STM32_PLS_LEV0 + +/* + * ADC driver system settings. + */ +#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4 +#define STM32_ADC_USE_ADC1 TRUE +#define STM32_ADC_USE_ADC2 FALSE +#define STM32_ADC_USE_ADC3 FALSE +#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4) +#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1) +#define STM32_ADC_ADC1_DMA_PRIORITY 2 +#define STM32_ADC_ADC2_DMA_PRIORITY 2 +#define STM32_ADC_ADC3_DMA_PRIORITY 2 +#define STM32_ADC_IRQ_PRIORITY 6 +#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY 6 +#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY 6 + +/* + * CAN driver system settings. + */ +#if USE_CAN1 +#define STM32_CAN_USE_CAN1 TRUE +#else +#define STM32_CAN_USE_CAN1 FALSE +#endif +#if USE_CAN2 +#define STM32_CAN_USE_CAN2 TRUE +#else +#define STM32_CAN_USE_CAN2 FALSE +#endif +#define STM32_CAN_CAN1_IRQ_PRIORITY 11 +#define STM32_CAN_CAN2_IRQ_PRIORITY 11 + +/* + * DAC driver system settings. + */ +#define STM32_DAC_DUAL_MODE FALSE +#if USE_DAC1 +#define STM32_DAC_USE_DAC1_CH1 TRUE +#else +#define STM32_DAC_USE_DAC1_CH1 FALSE +#endif +#if USE_DAC2 +#define STM32_DAC_USE_DAC1_CH2 TRUE +#else +#define STM32_DAC_USE_DAC1_CH2 FALSE +#endif +#define STM32_DAC_DAC1_CH1_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH2_IRQ_PRIORITY 10 +#define STM32_DAC_DAC1_CH1_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH2_DMA_PRIORITY 2 +#define STM32_DAC_DAC1_CH1_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_DAC_DAC1_CH2_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) + +/* + * EXT driver system settings. + */ +#define STM32_EXT_EXTI0_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI1_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI2_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI3_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI4_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI5_9_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI10_15_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI16_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI17_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI18_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI19_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI20_IRQ_PRIORITY 6 +#define STM32_EXT_EXTI21_IRQ_PRIORITY 15 +#define STM32_EXT_EXTI22_IRQ_PRIORITY 15 + +/* + * GPT driver system settings. + */ +#define STM32_GPT_USE_TIM1 FALSE +#define STM32_GPT_USE_TIM2 FALSE +#define STM32_GPT_USE_TIM3 FALSE +#define STM32_GPT_USE_TIM4 FALSE +#define STM32_GPT_USE_TIM5 FALSE +#define STM32_GPT_USE_TIM6 FALSE +#define STM32_GPT_USE_TIM7 FALSE +#define STM32_GPT_USE_TIM8 FALSE +#define STM32_GPT_USE_TIM9 FALSE +#define STM32_GPT_USE_TIM11 FALSE +#define STM32_GPT_USE_TIM12 FALSE +#define STM32_GPT_USE_TIM14 FALSE +#define STM32_GPT_TIM1_IRQ_PRIORITY 7 +#define STM32_GPT_TIM2_IRQ_PRIORITY 7 +#define STM32_GPT_TIM3_IRQ_PRIORITY 7 +#define STM32_GPT_TIM4_IRQ_PRIORITY 7 +#define STM32_GPT_TIM5_IRQ_PRIORITY 7 +#define STM32_GPT_TIM6_IRQ_PRIORITY 7 +#define STM32_GPT_TIM7_IRQ_PRIORITY 7 +#define STM32_GPT_TIM8_IRQ_PRIORITY 7 +#define STM32_GPT_TIM9_IRQ_PRIORITY 7 +#define STM32_GPT_TIM11_IRQ_PRIORITY 7 +#define STM32_GPT_TIM12_IRQ_PRIORITY 7 +#define STM32_GPT_TIM14_IRQ_PRIORITY 7 + +/* + * I2C driver system settings. + */ +#if USE_I2C1 +#define STM32_I2C_USE_I2C1 TRUE +#else +#define STM32_I2C_USE_I2C1 FALSE +#endif +#if USE_I2C2 +#define STM32_I2C_USE_I2C2 TRUE +#else +#define STM32_I2C_USE_I2C2 FALSE +#endif +#if USE_I2C3 +#define STM32_I2C_USE_I2C3 TRUE +#else +#define STM32_I2C_USE_I2C3 FALSE +#endif +#define STM32_I2C_I2C1_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_I2C_I2C1_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_I2C_I2C2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_I2C_I2C3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2) +#define STM32_I2C_I2C3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_I2C_I2C1_IRQ_PRIORITY 5 +#define STM32_I2C_I2C2_IRQ_PRIORITY 5 +#define STM32_I2C_I2C3_IRQ_PRIORITY 5 +#define STM32_I2C_I2C1_DMA_PRIORITY 3 +#define STM32_I2C_I2C2_DMA_PRIORITY 3 +#define STM32_I2C_I2C3_DMA_PRIORITY 3 +#define STM32_I2C_DMA_ERROR_HOOK(i2cp) osalSysHalt("DMA failure") + +/* + * ICU driver system settings. + */ +#define STM32_ICU_USE_TIM1 TRUE +#define STM32_ICU_USE_TIM2 FALSE +#define STM32_ICU_USE_TIM3 FALSE +#define STM32_ICU_USE_TIM4 FALSE +#define STM32_ICU_USE_TIM5 FALSE +#define STM32_ICU_USE_TIM8 FALSE +#define STM32_ICU_USE_TIM9 FALSE +#define STM32_ICU_TIM1_IRQ_PRIORITY 7 +#define STM32_ICU_TIM2_IRQ_PRIORITY 7 +#define STM32_ICU_TIM3_IRQ_PRIORITY 7 +#define STM32_ICU_TIM4_IRQ_PRIORITY 7 +#define STM32_ICU_TIM5_IRQ_PRIORITY 7 +#define STM32_ICU_TIM8_IRQ_PRIORITY 7 +#define STM32_ICU_TIM9_IRQ_PRIORITY 7 + +/* + * MAC driver system settings. + */ +#define STM32_MAC_TRANSMIT_BUFFERS 2 +#define STM32_MAC_RECEIVE_BUFFERS 4 +#define STM32_MAC_BUFFERS_SIZE 1522 +#define STM32_MAC_PHY_TIMEOUT 100 +#define STM32_MAC_ETH1_CHANGE_PHY_STATE TRUE +#define STM32_MAC_ETH1_IRQ_PRIORITY 13 +#define STM32_MAC_IP_CHECKSUM_OFFLOAD 0 + +/* + * PWM driver system settings. + */ +#define STM32_PWM_USE_ADVANCED FALSE +#define STM32_PWM_USE_TIM1 FALSE +#define STM32_PWM_USE_TIM2 FALSE +#define STM32_PWM_USE_TIM3 TRUE +#define STM32_PWM_USE_TIM4 FALSE +#define STM32_PWM_USE_TIM5 TRUE +#define STM32_PWM_USE_TIM8 FALSE +#define STM32_PWM_USE_TIM9 FALSE +#define STM32_PWM_TIM1_IRQ_PRIORITY 7 +#define STM32_PWM_TIM2_IRQ_PRIORITY 7 +#define STM32_PWM_TIM3_IRQ_PRIORITY 7 +#define STM32_PWM_TIM4_IRQ_PRIORITY 7 +#define STM32_PWM_TIM5_IRQ_PRIORITY 7 +#define STM32_PWM_TIM8_IRQ_PRIORITY 7 +#define STM32_PWM_TIM9_IRQ_PRIORITY 7 + +/* + * SERIAL driver system settings. + */ +#if USE_UART1 +#define STM32_SERIAL_USE_USART1 TRUE +#else +#define STM32_SERIAL_USE_USART1 FALSE +#endif +#if USE_UART2 +#define STM32_SERIAL_USE_USART2 TRUE +#else +#define STM32_SERIAL_USE_USART2 FALSE +#endif +#if USE_UART3 +#define STM32_SERIAL_USE_USART3 TRUE +#else +#define STM32_SERIAL_USE_USART3 FALSE +#endif +#if USE_UART4 +#define STM32_SERIAL_USE_UART4 TRUE +#else +#define STM32_SERIAL_USE_UART4 FALSE +#endif +#if USE_UART5 +#define STM32_SERIAL_USE_UART5 TRUE +#else +#define STM32_SERIAL_USE_UART5 FALSE +#endif +#if USE_UART6 +#define STM32_SERIAL_USE_USART6 TRUE +#else +#define STM32_SERIAL_USE_USART6 FALSE +#endif +#define STM32_SERIAL_USART1_PRIORITY 12 +#define STM32_SERIAL_USART2_PRIORITY 12 +#define STM32_SERIAL_USART3_PRIORITY 12 +#define STM32_SERIAL_UART4_PRIORITY 12 +#define STM32_SERIAL_UART5_PRIORITY 15 +#define STM32_SERIAL_USART6_PRIORITY 12 + +/* + * SPI driver system settings. + */ +#if USE_SPI1 +#define STM32_SPI_USE_SPI1 TRUE +#else +#define STM32_SPI_USE_SPI1 FALSE +#endif +#if USE_SPI2 +#define STM32_SPI_USE_SPI2 TRUE +#else +#define STM32_SPI_USE_SPI2 FALSE +#endif +#if USE_SPI3 +#define STM32_SPI_USE_SPI3 TRUE +#else +#define STM32_SPI_USE_SPI3 FALSE +#endif +#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 0) +#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3) +#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3) +#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 0) +#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 7) +#define STM32_SPI_SPI1_DMA_PRIORITY 1 +#define STM32_SPI_SPI2_DMA_PRIORITY 1 +#define STM32_SPI_SPI3_DMA_PRIORITY 1 +#define STM32_SPI_SPI1_IRQ_PRIORITY 10 +#define STM32_SPI_SPI2_IRQ_PRIORITY 10 +#define STM32_SPI_SPI3_IRQ_PRIORITY 10 +#define STM32_SPI_DMA_ERROR_HOOK(spip) osalSysHalt("DMA failure") + + +/* + * UART driver system settings. + */ +#if USE_UARTD1 +#define STM32_UART_USE_USART1 TRUE +#else +#define STM32_UART_USE_USART1 FALSE +#endif +#if USE_UARTD2 +#define STM32_UART_USE_USART2 TRUE +#else +#define STM32_UART_USE_USART2 FALSE +#endif +#if USE_UARTD3 +#define STM32_UART_USE_USART3 TRUE +#else +#define STM32_UART_USE_USART3 FALSE +#endif +#if USE_UARTD6 +#define STM32_UART_USE_USART6 TRUE +#else +#define STM32_UART_USE_USART6 FALSE +#endif +#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 5) +#define STM32_UART_USART1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5) +#define STM32_UART_USART2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 6) +#define STM32_UART_USART3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 1) +#define STM32_UART_USART3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4) +#define STM32_UART_USART6_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2) +#define STM32_UART_USART6_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 7) +#define STM32_UART_USART1_IRQ_PRIORITY 7 +#define STM32_UART_USART2_IRQ_PRIORITY 6 +#define STM32_UART_USART3_IRQ_PRIORITY 12 +#define STM32_UART_USART6_IRQ_PRIORITY 13 +#define STM32_UART_USART1_DMA_PRIORITY 0 +#define STM32_UART_USART2_DMA_PRIORITY 0 +#define STM32_UART_USART3_DMA_PRIORITY 0 +#define STM32_UART_USART6_DMA_PRIORITY 0 +#define STM32_UART_DMA_ERROR_HOOK(uartp) osalSysHalt("DMA failure") + +/* + * USB driver system settings. + */ +#if USE_USB_SERIAL +#define STM32_USB_USE_OTG1 TRUE +#else +#define STM32_USB_USE_OTG1 FALSE +#endif +#define STM32_USB_USE_OTG2 FALSE +#define STM32_USB_OTG1_IRQ_PRIORITY 14 +#define STM32_USB_OTG2_IRQ_PRIORITY 14 +#define STM32_USB_OTG1_RX_FIFO_SIZE 512 +#define STM32_USB_OTG2_RX_FIFO_SIZE 1024 +#define STM32_USB_OTG_THREAD_PRIO LOWPRIO +#define STM32_USB_OTG_THREAD_STACK_SIZE 128 +#define STM32_USB_OTGFIFO_FILL_BASEPRI 0 + diff --git a/sw/airborne/modules/loggers/sdlog_chibios/msg_queue.c b/sw/airborne/modules/loggers/sdlog_chibios/msg_queue.c index bf01e472ae..0ddd782815 100644 --- a/sw/airborne/modules/loggers/sdlog_chibios/msg_queue.c +++ b/sw/airborne/modules/loggers/sdlog_chibios/msg_queue.c @@ -76,9 +76,11 @@ int32_t msgqueue_send(MsgQueue *que, void *msg, const uint16_t msgLen, int32_t msgqueue_send_timeout(MsgQueue *que, void *msg, const uint16_t msgLen, const MsgQueueUrgency urgency, const systime_t timout) { - const MsgPtrLen mpl = {.ptrOfst = (uint32_t) msg - (uint32_t) tlsf_get_heap_addr(&MSGQ_HEAP), - .len = msgLen - }; + // this code prevents compiler warning about a missing initializer of mpl + MsgPtrLen m; + m.len = msgLen; + m.ptrOfst = (uint32_t) msg - (uint32_t) tlsf_get_heap_addr(&MSGQ_HEAP); + const MsgPtrLen mpl = m; #if CH_DBG_ENABLE_CHECKS if (((uint32_t) msg < (uint32_t) tlsf_get_heap_addr(&MSGQ_HEAP)) || diff --git a/sw/ext/chibios b/sw/ext/chibios index 3a6e100efc..024738d265 160000 --- a/sw/ext/chibios +++ b/sw/ext/chibios @@ -1 +1 @@ -Subproject commit 3a6e100efce969b984958f78c13f1c770e5fb730 +Subproject commit 024738d265bd3ef20dff3bb2809feabe3e24fb32 diff --git a/sw/ext/pprzlink b/sw/ext/pprzlink index de6818aaae..cb329c22a3 160000 --- a/sw/ext/pprzlink +++ b/sw/ext/pprzlink @@ -1 +1 @@ -Subproject commit de6818aaaecc0f37f83c4bbb8f12c0cbf1fb5d00 +Subproject commit cb329c22a354202ab8425aaafe2d17bbad5d2d8d