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Aspirin works with Chibios on Lisa MX (#1829)

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This commit is contained in:
Michal Podhradsky
2016-07-27 15:13:00 -07:00
committed by GitHub
parent 2d23f5fc87
commit 032c45481a
3 changed files with 26 additions and 23 deletions
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conf/airframes/AGGIEAIR/aggieair_rp3_lia.xml
+1 -1
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@@ -9,7 +9,7 @@ RP3 Lisa MX
<firmware name="fixedwing"> <firmware name="fixedwing">
<define name="CONTROL_FREQUENCY" value="100"/> <define name="CONTROL_FREQUENCY" value="100"/>
<configure name="PERIODIC_FREQUENCY" value="100"/> <configure name="PERIODIC_FREQUENCY" value="100"/>
<target name="ap" board="lisa_mx_2.0"> <target name="ap" board="lisa_mx_2.1_chibios">
<module name="radio_control" type="sbus"> <module name="radio_control" type="sbus">
<configure name="SBUS_PORT" value="UART5"/> <configure name="SBUS_PORT" value="UART5"/>
</module> </module>
conf/firmwares/subsystems/shared/imu_aspirin_v2_common.makefile
+2 -1
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@@ -57,7 +57,8 @@ include $(CFG_SHARED)/spi_master.makefile
ifeq ($(ARCH), lpc21) ifeq ($(ARCH), lpc21)
ASPIRIN_2_SPI_DEV ?= spi1 ASPIRIN_2_SPI_DEV ?= spi1
ASPIRIN_2_SPI_SLAVE_IDX ?= SPI_SLAVE0 ASPIRIN_2_SPI_SLAVE_IDX ?= SPI_SLAVE0
else ifeq ($(ARCH), stm32) #else ifeq ($(ARCH), stm32)
else ifeq ($(ARCH),$(filter $(ARCH),stm32 chibios))
# Slave select configuration # Slave select configuration
# SLAVE2 is on PB12 (NSS) (MPU600 CS) # SLAVE2 is on PB12 (NSS) (MPU600 CS)
ASPIRIN_2_SPI_DEV ?= spi2 ASPIRIN_2_SPI_DEV ?= spi2
sw/airborne/boards/lisa_mx/chibios/v2.1/board.h
+23 -21
View File
@@ -1388,29 +1388,31 @@
/** /**
* SPI Config * SPI Config
*/ */
#define SPI1_GPIO_AF GPIO_AF5 #define SPI_SELECT_SLAVE0_PORT GPIOA
#define SPI1_GPIO_PORT_MISO GPIOA #define SPI_SELECT_SLAVE0_PIN GPIO15
#define SPI1_GPIO_MISO GPIO6
#define SPI1_GPIO_PORT_MOSI GPIOA #define SPI_SELECT_SLAVE1_PORT GPIOA
#define SPI1_GPIO_MOSI GPIO7 #define SPI_SELECT_SLAVE1_PIN GPIO4
#define SPI1_GPIO_PORT_SCK GPIOA
#define SPI1_GPIO_SCK GPIO5 #define SPI_SELECT_SLAVE2_PORT GPIOB
#define SPI_SELECT_SLAVE2_PIN GPIO12
// SLAVE0 on SPI connector
#define SPI_SELECT_SLAVE0_PORT GPIOB
#define SPI_SELECT_SLAVE0_PIN 9
// SLAVE1 on AUX1
#define SPI_SELECT_SLAVE1_PORT GPIOB
#define SPI_SELECT_SLAVE1_PIN 1
// SLAVE2 on AUX2
#define SPI_SELECT_SLAVE2_PORT GPIOC
#define SPI_SELECT_SLAVE2_PIN 5
// SLAVE3 on AUX3
#define SPI_SELECT_SLAVE3_PORT GPIOC #define SPI_SELECT_SLAVE3_PORT GPIOC
#define SPI_SELECT_SLAVE3_PIN 4 #define SPI_SELECT_SLAVE3_PIN GPIO13
// SLAVE4 on AUX4
#define SPI_SELECT_SLAVE4_PORT GPIOB #define SPI_SELECT_SLAVE4_PORT GPIOC
#define SPI_SELECT_SLAVE4_PIN 5 #define SPI_SELECT_SLAVE4_PIN GPIO12
#define SPI_SELECT_SLAVE5_PORT GPIOC
#define SPI_SELECT_SLAVE5_PIN GPIO4
#define SPI1_GPIO_PORT_NSS GPIOA
#define SPI1_GPIO_NSS GPIO4
#define SPI2_GPIO_PORT_NSS GPIOB
#define SPI2_GPIO_NSS GPIO12
#define SPI3_GPIO_PORT_NSS GPIO
/** /**
* Baro * Baro