/*
    ChibiOS/RT - Copyright (C) 2006,2007,2008,2009,2010,
                 2011,2012 Giovanni Di Sirio.

    This file is part of ChibiOS/RT.

    ChibiOS/RT is free software; you can redistribute it and/or modify
    it under the terms of the GNU General Public License as published by
    the Free Software Foundation; either version 3 of the License, or
    (at your option) any later version.

    ChibiOS/RT is distributed in the hope that it will be useful,
    but WITHOUT ANY WARRANTY; without even the implied warranty of
    MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE.  See the
    GNU General Public License for more details.

    You should have received a copy of the GNU General Public License
    along with this program.  If not, see <http://www.gnu.org/licenses/>.
*/

/*
 * STM32F4xx drivers configuration.
 * The following settings override the default settings present in
 * the various device driver implementation headers.
 * Note that the settings for each driver only have effect if the whole
 * driver is enabled in halconf.h.
 *
 * IRQ priorities:
 * 15...0       Lowest...Highest.
 *
 * DMA priorities:
 * 0...3        Lowest...Highest.
 */

#define STM32F4xx_MCUCONF

/*
 * HAL driver system settings.
 */
#define STM32_NO_INIT                       FALSE
#define STM32_HSI_ENABLED                   TRUE
#define STM32_LSI_ENABLED                   FALSE
#define STM32_HSE_ENABLED                   TRUE
#define STM32_LSE_ENABLED                   TRUE
#define STM32_CLOCK48_REQUIRED              TRUE
#define STM32_SW                            STM32_SW_PLL
#define STM32_PLLSRC                        STM32_PLLSRC_HSE
#define STM32_PLLM_VALUE                    16
#define STM32_PLLN_VALUE                    336
#define STM32_PLLP_VALUE                    2
#define STM32_PLLQ_VALUE                    7
#define STM32_HPRE                          STM32_HPRE_DIV1
#define STM32_PPRE1                         STM32_PPRE1_DIV4
#define STM32_PPRE2                         STM32_PPRE2_DIV2
#define STM32_RTCSEL                        STM32_RTCSEL_LSE
#define STM32_RTCPRE_VALUE                  8
#define STM32_MCO1SEL                       STM32_MCO1SEL_HSI
#define STM32_MCO1PRE                       STM32_MCO1PRE_DIV1
#define STM32_MCO2SEL                       STM32_MCO2SEL_SYSCLK
#define STM32_MCO2PRE                       STM32_MCO2PRE_DIV5
#define STM32_I2SSRC                        STM32_I2SSRC_CKIN
#define STM32_PLLI2SN_VALUE                 192
#define STM32_PLLI2SR_VALUE                 5
#define STM32_PVD_ENABLE                    FALSE
#define STM32_PLS                           STM32_PLS_LEV0

/*
 * ADC driver system settings.
 */
#define STM32_ADC_ADCPRE                    ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1                  FALSE
#define STM32_ADC_USE_ADC2                  FALSE
#define STM32_ADC_USE_ADC3                  FALSE
#define STM32_ADC_ADC1_DMA_STREAM           STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC2_DMA_STREAM           STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC3_DMA_STREAM           STM32_DMA_STREAM_ID(2, 1)
#define STM32_ADC_ADC1_DMA_PRIORITY         2
#define STM32_ADC_ADC2_DMA_PRIORITY         2
#define STM32_ADC_ADC3_DMA_PRIORITY         2
#define STM32_ADC_IRQ_PRIORITY              6
#define STM32_ADC_ADC1_DMA_IRQ_PRIORITY     6
#define STM32_ADC_ADC2_DMA_IRQ_PRIORITY     6
#define STM32_ADC_ADC3_DMA_IRQ_PRIORITY     6

/*
 * CAN driver system settings.
 */
#define STM32_CAN_USE_CAN1                  FALSE
#define STM32_CAN_USE_CAN2                  FALSE
#define STM32_CAN_CAN1_IRQ_PRIORITY         11
#define STM32_CAN_CAN2_IRQ_PRIORITY         11

/*
 * EXT driver system settings.
 */
#define STM32_EXT_EXTI0_IRQ_PRIORITY        6
#define STM32_EXT_EXTI1_IRQ_PRIORITY        6
#define STM32_EXT_EXTI2_IRQ_PRIORITY        6
#define STM32_EXT_EXTI3_IRQ_PRIORITY        6
#define STM32_EXT_EXTI4_IRQ_PRIORITY        6
#define STM32_EXT_EXTI5_9_IRQ_PRIORITY      6
#define STM32_EXT_EXTI10_15_IRQ_PRIORITY    6
#define STM32_EXT_EXTI16_IRQ_PRIORITY       6
#define STM32_EXT_EXTI17_IRQ_PRIORITY       15
#define STM32_EXT_EXTI18_IRQ_PRIORITY       6
#define STM32_EXT_EXTI19_IRQ_PRIORITY       6
#define STM32_EXT_EXTI20_IRQ_PRIORITY       6
#define STM32_EXT_EXTI21_IRQ_PRIORITY       15
#define STM32_EXT_EXTI22_IRQ_PRIORITY       15

/*
 * GPT driver system settings.
 */
#define STM32_GPT_USE_TIM1                  FALSE
#define STM32_GPT_USE_TIM2                  FALSE
#define STM32_GPT_USE_TIM3                  FALSE
#define STM32_GPT_USE_TIM4                  FALSE
#define STM32_GPT_USE_TIM5                  FALSE
#define STM32_GPT_USE_TIM8                  FALSE
#define STM32_GPT_TIM1_IRQ_PRIORITY         7
#define STM32_GPT_TIM2_IRQ_PRIORITY         7
#define STM32_GPT_TIM3_IRQ_PRIORITY         7
#define STM32_GPT_TIM4_IRQ_PRIORITY         7
#define STM32_GPT_TIM5_IRQ_PRIORITY         7
#define STM32_GPT_TIM8_IRQ_PRIORITY         7

/*
 * I2C driver system settings.
 */
#define STM32_I2C_USE_I2C1                  FALSE
#define STM32_I2C_USE_I2C2                  FALSE
#define STM32_I2C_USE_I2C3                  FALSE
#define STM32_I2C_I2C1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
#define STM32_I2C_I2C1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 6)
#define STM32_I2C_I2C2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
#define STM32_I2C_I2C3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 2)
#define STM32_I2C_I2C3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
#define STM32_I2C_I2C1_IRQ_PRIORITY         5
#define STM32_I2C_I2C2_IRQ_PRIORITY         5
#define STM32_I2C_I2C3_IRQ_PRIORITY         5
#define STM32_I2C_I2C1_DMA_PRIORITY         3
#define STM32_I2C_I2C2_DMA_PRIORITY         3
#define STM32_I2C_I2C3_DMA_PRIORITY         3
#define STM32_I2C_I2C1_DMA_ERROR_HOOK()     chSysHalt()
#define STM32_I2C_I2C2_DMA_ERROR_HOOK()     chSysHalt()
#define STM32_I2C_I2C3_DMA_ERROR_HOOK()     chSysHalt()

/*
 * ICU driver system settings.
 */
#define STM32_ICU_USE_TIM1                  FALSE
#define STM32_ICU_USE_TIM2                  FALSE
#define STM32_ICU_USE_TIM3                  FALSE
#define STM32_ICU_USE_TIM4                  FALSE
#define STM32_ICU_USE_TIM5                  FALSE
#define STM32_ICU_USE_TIM8                  FALSE
#define STM32_ICU_TIM1_IRQ_PRIORITY         7
#define STM32_ICU_TIM2_IRQ_PRIORITY         7
#define STM32_ICU_TIM3_IRQ_PRIORITY         7
#define STM32_ICU_TIM4_IRQ_PRIORITY         7
#define STM32_ICU_TIM5_IRQ_PRIORITY         7
#define STM32_ICU_TIM8_IRQ_PRIORITY         7

/*
 * PWM driver system settings.
 */
#define STM32_PWM_USE_ADVANCED              FALSE
#define STM32_PWM_USE_TIM1                  FALSE
#define STM32_PWM_USE_TIM2                  FALSE
#define STM32_PWM_USE_TIM3                  FALSE
#define STM32_PWM_USE_TIM4                  FALSE
#define STM32_PWM_USE_TIM5                  FALSE
#define STM32_PWM_USE_TIM8                  FALSE
#define STM32_PWM_TIM1_IRQ_PRIORITY         7
#define STM32_PWM_TIM2_IRQ_PRIORITY         7
#define STM32_PWM_TIM3_IRQ_PRIORITY         7
#define STM32_PWM_TIM4_IRQ_PRIORITY         7
#define STM32_PWM_TIM5_IRQ_PRIORITY         7
#define STM32_PWM_TIM8_IRQ_PRIORITY         7

/*
 * SERIAL driver system settings.
 */
#define STM32_SERIAL_USE_USART1             FALSE
#define STM32_SERIAL_USE_USART2             FALSE
#define STM32_SERIAL_USE_USART3             FALSE
#define STM32_SERIAL_USE_UART4              FALSE
#define STM32_SERIAL_USE_UART5              FALSE
#define STM32_SERIAL_USE_USART6             FALSE
#define STM32_SERIAL_USART1_PRIORITY        12
#define STM32_SERIAL_USART2_PRIORITY        12
#define STM32_SERIAL_USART3_PRIORITY        12
#define STM32_SERIAL_UART4_PRIORITY         12
#define STM32_SERIAL_UART5_PRIORITY         12
#define STM32_SERIAL_USART6_PRIORITY        12

/*
 * SPI driver system settings.
 */
#define STM32_SPI_USE_SPI1                  FALSE
#define STM32_SPI_USE_SPI2                  FALSE
#define STM32_SPI_USE_SPI3                  FALSE
#define STM32_SPI_SPI1_RX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 0)
#define STM32_SPI_SPI1_TX_DMA_STREAM        STM32_DMA_STREAM_ID(2, 5)
#define STM32_SPI_SPI2_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 0)
#define STM32_SPI_SPI3_TX_DMA_STREAM        STM32_DMA_STREAM_ID(1, 7)
#define STM32_SPI_SPI1_DMA_PRIORITY         1
#define STM32_SPI_SPI2_DMA_PRIORITY         1
#define STM32_SPI_SPI3_DMA_PRIORITY         1
#define STM32_SPI_SPI1_IRQ_PRIORITY         10
#define STM32_SPI_SPI2_IRQ_PRIORITY         10
#define STM32_SPI_SPI3_IRQ_PRIORITY         10
#define STM32_SPI_DMA_ERROR_HOOK(spip)      chSysHalt()

/*
 * UART driver system settings.
 */
#define STM32_UART_USE_USART1               FALSE
#define STM32_UART_USE_USART2               FALSE
#define STM32_UART_USE_USART3               FALSE
#define STM32_UART_USE_USART6               FALSE
#define STM32_UART_USART1_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 5)
#define STM32_UART_USART1_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 7)
#define STM32_UART_USART2_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 5)
#define STM32_UART_USART2_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 6)
#define STM32_UART_USART3_RX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 1)
#define STM32_UART_USART3_TX_DMA_STREAM     STM32_DMA_STREAM_ID(1, 3)
#define STM32_UART_USART6_RX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 2)
#define STM32_UART_USART6_TX_DMA_STREAM     STM32_DMA_STREAM_ID(2, 6)
#define STM32_UART_USART1_IRQ_PRIORITY      12
#define STM32_UART_USART2_IRQ_PRIORITY      12
#define STM32_UART_USART3_IRQ_PRIORITY      12
#define STM32_UART_USART6_IRQ_PRIORITY      12
#define STM32_UART_USART1_DMA_PRIORITY      1
#define STM32_UART_USART2_DMA_PRIORITY      0
#define STM32_UART_USART3_DMA_PRIORITY      0
#define STM32_UART_USART6_DMA_PRIORITY      0
#define STM32_UART_DMA_ERROR_HOOK(uartp)    chSysHalt()

/*
 * USB driver system settings.
 */
#define STM32_USB_USE_OTG1                  TRUE   // FS, DFU_BOOT
#define STM32_USB_USE_OTG2                  FALSE  // HS
#define STM32_USB_OTG1_IRQ_PRIORITY         14
#define STM32_USB_OTG2_IRQ_PRIORITY         14
#define STM32_USB_OTG1_RX_FIFO_SIZE         512
#define STM32_USB_OTG2_RX_FIFO_SIZE         512
#define STM32_USB_OTG_THREAD_PRIO           HIGHPRIO
#define STM32_USB_OTG_THREAD_STACK_SIZE     256
#define STM32_USB_OTGFIFO_FILL_BASEPRI      0


/*
 * SDC SDIO driver system settings.
 */
#define STM32_SDC_SDIO_DMA_STREAM           STM32_DMA_STREAM_ID(2, 3)
#define STM32_SDC_SDIO_DMA_PRIORITY         3
#define STM32_SDC_SDIO_IRQ_PRIORITY         9
#define STM32_SDC_SDIO_UNALIGNED_SUPPORT    FALSE
#define SDC_READ_TIMEOUT_MS                 15


/*
 * OPENCM3 INTEGRATION
 */

#define DECLARE_IRQS [NVIC_NVIC_WWDG_IRQ] = NVIC_NVIC_WWDG_IRQ_VEC_OPENCM3, \
[NVIC_PVD_IRQ] = NVIC_PVD_IRQ_VEC_OPENCM3, \
[NVIC_TAMP_STAMP_IRQ] = NVIC_TAMP_STAMP_IRQ_VEC_OPENCM3, \
[NVIC_RTC_WKUP_IRQ] = NVIC_RTC_WKUP_IRQ_VEC_CHIBIOS, \
[NVIC_FLASH_IRQ] = NVIC_FLASH_IRQ_VEC_OPENCM3, \
[NVIC_RCC_IRQ] = NVIC_RCC_IRQ_VEC_OPENCM3, \
[NVIC_EXTI0_IRQ] = NVIC_EXTI0_IRQ_VEC_OPENCM3, \
[NVIC_EXTI1_IRQ] = NVIC_EXTI1_IRQ_VEC_OPENCM3, \
[NVIC_EXTI2_IRQ] = NVIC_EXTI2_IRQ_VEC_OPENCM3, \
[NVIC_EXTI3_IRQ] = NVIC_EXTI3_IRQ_VEC_OPENCM3, \
[NVIC_EXTI4_IRQ] = NVIC_EXTI4_IRQ_VEC_OPENCM3, \
[NVIC_DMA1_STREAM0_IRQ] = NVIC_DMA1_STREAM0_IRQ_VEC_OPENCM3, \
[NVIC_DMA1_STREAM1_IRQ] = NVIC_DMA1_STREAM1_IRQ_VEC_OPENCM3, \
[NVIC_DMA1_STREAM2_IRQ] = NVIC_DMA1_STREAM2_IRQ_VEC_OPENCM3, \
[NVIC_DMA1_STREAM3_IRQ] = NVIC_DMA1_STREAM3_IRQ_VEC_OPENCM3, \
[NVIC_DMA1_STREAM4_IRQ] = NVIC_DMA1_STREAM4_IRQ_VEC_OPENCM3, \
[NVIC_DMA1_STREAM5_IRQ] = NVIC_DMA1_STREAM5_IRQ_VEC_OPENCM3, \
[NVIC_DMA1_STREAM6_IRQ] = NVIC_DMA1_STREAM6_IRQ_VEC_OPENCM3, \
[NVIC_ADC_IRQ] = NVIC_ADC_IRQ_VEC_OPENCM3, \
[NVIC_CAN1_TX_IRQ] = NVIC_CAN1_TX_IRQ_VEC_OPENCM3, \
[NVIC_CAN1_RX0_IRQ] = NVIC_CAN1_RX0_IRQ_VEC_OPENCM3, \
[NVIC_CAN1_RX1_IRQ] = NVIC_CAN1_RX1_IRQ_VEC_OPENCM3, \
[NVIC_CAN1_SCE_IRQ] = NVIC_CAN1_SCE_IRQ_VEC_OPENCM3, \
[NVIC_EXTI9_5_IRQ] = NVIC_EXTI9_5_IRQ_VEC_OPENCM3, \
[NVIC_TIM1_BRK_TIM9_IRQ] = NVIC_TIM1_BRK_TIM9_IRQ_VEC_OPENCM3, \
[NVIC_TIM1_UP_TIM10_IRQ] = NVIC_TIM1_UP_TIM10_IRQ_VEC_OPENCM3, \
[NVIC_TIM1_TRG_COM_TIM11_IRQ] = NVIC_TIM1_TRG_COM_TIM11_IRQ_VEC_OPENCM3, \
[NVIC_TIM1_CC_IRQ] = NVIC_TIM1_CC_IRQ_VEC_OPENCM3, \
[NVIC_TIM2_IRQ] = NVIC_TIM2_IRQ_VEC_OPENCM3, \
[NVIC_TIM3_IRQ] = NVIC_TIM3_IRQ_VEC_OPENCM3, \
[NVIC_TIM4_IRQ] = NVIC_TIM4_IRQ_VEC_OPENCM3, \
[NVIC_I2C1_EV_IRQ] = NVIC_I2C1_EV_IRQ_VEC_OPENCM3, \
[NVIC_I2C1_ER_IRQ] = NVIC_I2C1_ER_IRQ_VEC_OPENCM3, \
[NVIC_I2C2_EV_IRQ] = NVIC_I2C2_EV_IRQ_VEC_OPENCM3, \
[NVIC_I2C2_ER_IRQ] = NVIC_I2C2_ER_IRQ_VEC_OPENCM3, \
[NVIC_SPI1_IRQ] = NVIC_SPI1_IRQ_VEC_OPENCM3, \
[NVIC_SPI2_IRQ] = NVIC_SPI2_IRQ_VEC_OPENCM3, \
[NVIC_USART1_IRQ] = NVIC_USART1_IRQ_VEC_OPENCM3, \
[NVIC_USART2_IRQ] = NVIC_USART2_IRQ_VEC_OPENCM3, \
[NVIC_USART3_IRQ] = NVIC_USART3_IRQ_VEC_OPENCM3, \
[NVIC_EXTI15_10_IRQ] = NVIC_EXTI15_10_IRQ_VEC_OPENCM3, \
[NVIC_RTC_ALARM_IRQ] = NVIC_RTC_ALARM_IRQ_VEC_CHIBIOS, \
[NVIC_USB_FS_WKUP_IRQ] = NVIC_USB_FS_WKUP_IRQ_VEC_CHIBIOS, \
[NVIC_TIM8_BRK_TIM12_IRQ] = NVIC_TIM8_BRK_TIM12_IRQ_VEC_OPENCM3, \
[NVIC_TIM8_UP_TIM13_IRQ] = NVIC_TIM8_UP_TIM13_IRQ_VEC_OPENCM3, \
[NVIC_TIM8_TRG_COM_TIM14_IRQ] = NVIC_TIM8_TRG_COM_TIM14_IRQ_VEC_OPENCM3, \
[NVIC_TIM8_CC_IRQ] = NVIC_TIM8_CC_IRQ_VEC_OPENCM3, \
[NVIC_DMA1_STREAM7_IRQ] = NVIC_DMA1_STREAM7_IRQ_VEC_OPENCM3, \
[NVIC_FSMC_IRQ] = NVIC_FSMC_IRQ_VEC_OPENCM3, \
[NVIC_SDIO_IRQ] = NVIC_SDIO_IRQ_VEC_CHIBIOS, \
[NVIC_TIM5_IRQ] = NVIC_TIM5_IRQ_VEC_OPENCM3, \
[NVIC_SPI3_IRQ] = NVIC_SPI3_IRQ_VEC_OPENCM3, \
[NVIC_UART4_IRQ] = NVIC_UART4_IRQ_VEC_OPENCM3, \
[NVIC_UART5_IRQ] = NVIC_UART5_IRQ_VEC_OPENCM3, \
[NVIC_TIM6_DAC_IRQ] = NVIC_TIM6_DAC_IRQ_VEC_OPENCM3, \
[NVIC_TIM7_IRQ] = NVIC_TIM7_IRQ_VEC_OPENCM3, \
[NVIC_DMA2_STREAM0_IRQ] = NVIC_DMA2_STREAM0_IRQ_VEC_OPENCM3, \
[NVIC_DMA2_STREAM1_IRQ] = NVIC_DMA2_STREAM1_IRQ_VEC_OPENCM3, \
[NVIC_DMA2_STREAM2_IRQ] = NVIC_DMA2_STREAM2_IRQ_VEC_OPENCM3, \
[NVIC_DMA2_STREAM3_IRQ] = NVIC_DMA2_STREAM3_IRQ_VEC_CHIBIOS, \
[NVIC_DMA2_STREAM4_IRQ] = NVIC_DMA2_STREAM4_IRQ_VEC_OPENCM3, \
[NVIC_ETH_IRQ] = NVIC_ETH_IRQ_VEC_OPENCM3, \
[NVIC_ETH_WKUP_IRQ] = NVIC_ETH_WKUP_IRQ_VEC_OPENCM3, \
[NVIC_CAN2_TX_IRQ] = NVIC_CAN2_TX_IRQ_VEC_OPENCM3, \
[NVIC_CAN2_RX0_IRQ] = NVIC_CAN2_RX0_IRQ_VEC_OPENCM3, \
[NVIC_CAN2_RX1_IRQ] = NVIC_CAN2_RX1_IRQ_VEC_OPENCM3, \
[NVIC_CAN2_SCE_IRQ] = NVIC_CAN2_SCE_IRQ_VEC_OPENCM3, \
[NVIC_OTG_FS_IRQ] = NVIC_OTG_FS_IRQ_VEC_CHIBIOS, \
[NVIC_DMA2_STREAM5_IRQ] = NVIC_DMA2_STREAM5_IRQ_VEC_OPENCM3, \
[NVIC_DMA2_STREAM6_IRQ] = NVIC_DMA2_STREAM6_IRQ_VEC_OPENCM3, \
[NVIC_DMA2_STREAM7_IRQ] = NVIC_DMA2_STREAM7_IRQ_VEC_OPENCM3, \
[NVIC_USART6_IRQ] = NVIC_USART6_IRQ_VEC_OPENCM3, \
[NVIC_I2C3_EV_IRQ] = NVIC_I2C3_EV_IRQ_VEC_OPENCM3, \
[NVIC_I2C3_ER_IRQ] = NVIC_I2C3_ER_IRQ_VEC_OPENCM3, \
[NVIC_OTG_HS_EP1_OUT_IRQ] = NVIC_OTG_HS_EP1_OUT_IRQ_VEC_OPENCM3, \
[NVIC_OTG_HS_EP1_IN_IRQ] = NVIC_OTG_HS_EP1_IN_IRQ_VEC_OPENCM3, \
[NVIC_OTG_HS_WKUP_IRQ] = NVIC_OTG_HS_WKUP_IRQ_VEC_OPENCM3, \
[NVIC_OTG_HS_IRQ] = NVIC_OTG_HS_IRQ_VEC_OPENCM3, \
[NVIC_DCMI_IRQ] = NVIC_DCMI_IRQ_VEC_OPENCM3, \
[NVIC_CRYP_IRQ] = NVIC_CRYP_IRQ_VEC_OPENCM3, \
[NVIC_HASH_RNG_IRQ] = NVIC_HASH_RNG_IRQ_VEC_OPENCM3, \
[81] = Vector184
