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patacongo
50321df42d
git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@5146 42af7a65-404d-4744-a932-0658087f49c3
275 lines
8.5 KiB
C
275 lines
8.5 KiB
C
/************************************************************************************
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* arch/hc/include/hcs12/irq.h
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*
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* Copyright (C) 2009, 2011 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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************************************************************************************/
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/* This file should never be included directed but, rather,
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* only indirectly through nuttx/irq.h
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*/
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#ifndef __ARCH_HC_INCLUDE_HCS12_IRQ_H
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#define __ARCH_HC_INCLUDE_HCS12_IRQ_H
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/************************************************************************************
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* Included Files
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************************************************************************************/
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#include <nuttx/config.h>
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#include <nuttx/irq.h>
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/************************************************************************************
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* Definitions
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************************************************************************************/
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/* CCR bit definitions */
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#define HCS12_CCR_C (1 << 0) /* Bit 0: Carry/Borrow status bit */
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#define HCS12_CCR_V (1 << 1) /* Bit 1: Two’s complement overflow status bit */
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#define HCS12_CCR_Z (1 << 2) /* Bit 2: Zero status bit */
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#define HCS12_CCR_N (1 << 3) /* Bit 3: Negative status bit */
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#define HCS12_CCR_I (1 << 4) /* Bit 4: Maskable interrupt control bit */
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#define HCS12_CCR_H (1 << 5) /* Bit 5: Half-carry status bit */
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#define HCS12_CCR_X (1 << 6) /* Bit 6: Non-maskable interrupt control bit */
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#define HCS12_CCR_S (1 << 7) /* Bit 7: STOP instruction control bit */
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/************************************************************************************
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* Register state save strucure
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* Low Address <-- SP after state save
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* [PPAGE]
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* [soft regisers]
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* XYH
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* XYL
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* ZH
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* ZL
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* TMPH
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* TMPL
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* FRAMEH
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* FRAMEL
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* SP <-- SP after interrupt
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* CCR
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* B
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* A
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* XH
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* XL
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* YH
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* YL
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* PCH
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* High Address PCL <-- SP before interrupt
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*
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************************************************************************************/
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/* Byte offsets */
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/* PPAGE register (only in banked mode) */
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#ifndef CONFIG_HCS12_NONBANKED
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# define REG_PPAGE 0
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# define REG_FIRST_SOFTREG 1
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#else
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# define REG_FIRST_SOFTREG 0
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#endif
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/* Soft registers (as configured) */
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#if CONFIG_HCS12_MSOFTREGS > 2
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# error "Need to save more registers"
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#elif CONFIG_HCS12_MSOFTREGS == 2
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# define REG_SOFTREG1 REG_FIRST_SOFTREG
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# define REG_SOFTREG2 (REG_FIRST_SOFTREG+2)
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# define REG_FIRST_HARDREG (REG_FIRST_SOFTREG+4)
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#elif CONFIG_HCS12_MSOFTREGS == 1
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# define REG_SOFTREG1 REG_FIRST_SOFTREG
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# define REG_FIRST_HARDREG (REG_FIRST_SOFTREG+2)
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#else
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# define REG_FIRST_HARDREG REG_FIRST_SOFTREG
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#endif
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#define REG_XY REG_FIRST_HARDREG
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#define REG_Z (REG_FIRST_HARDREG+2)
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# define REG_ZH (REG_FIRST_HARDREG+2)
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# define REG_ZL (REG_FIRST_HARDREG+3)
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#define REG_TMP (REG_FIRST_HARDREG+4)
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# define REG_TMPH (REG_FIRST_HARDREG+4)
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# define REG_TMPL (REG_FIRST_HARDREG+5)
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#define REG_FRAME (REG_FIRST_HARDREG+6)
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# define REG_FRAMEH (REG_FIRST_HARDREG+6)
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# define REG_FRAMEL (REG_FIRST_HARDREG+7)
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/* Stack pointer before the interrupt */
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#define REG_SP (REG_FIRST_HARDREG+8)
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# define REG_SPH (REG_FIRST_HARDREG+8)
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# define REG_SPL (REG_FIRST_HARDREG+9)
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/* On entry into an I- or X-interrupt, into an SWI, or into an undefined instruction
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* interrupt, the stack frame created by hardware looks like:
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*
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* Low Address <-- SP after interrupt
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* CCR
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* B
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* A
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* XH
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* XL
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* YH
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* YL
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* PCH
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* High Address PCL <-- SP before interrupt
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*/
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#define REG_CCR (REG_FIRST_HARDREG+10)
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#define REG_BA (REG_FIRST_HARDREG+11)
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# define REG_B (REG_FIRST_HARDREG+11)
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# define REG_A (REG_FIRST_HARDREG+12)
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#define REG_X (REG_FIRST_HARDREG+13)
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# define REG_XH (REG_FIRST_HARDREG+13)
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# define REG_XL (REG_FIRST_HARDREG+14)
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#define REG_Y (REG_FIRST_HARDREG+15)
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# define REG_YH (REG_FIRST_HARDREG+15)
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# define REG_YL (REG_FIRST_HARDREG+16)
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#define REG_PC (REG_FIRST_HARDREG+17)
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# define REG_PCH (REG_FIRST_HARDREG+17)
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# define REG_PCL (REG_FIRST_HARDREG+18)
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#define TOTALFRAME_SIZE (REG_FIRST_HARDREG+17)
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#define INTFRAME_SIZE 9
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#define XCPTCONTEXT_REGS TOTALFRAME_SIZE
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/************************************************************************************
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* Public Types
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************************************************************************************/
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/* This structure defines the way the registers are stored. */
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#ifndef __ASSEMBLY__
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struct xcptcontext
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{
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uint8_t regs[XCPTCONTEXT_REGS];
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};
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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/* Enable/Disable interrupts */
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#define ienable() __asm("cli");
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#define idisable() __asm("orcc #0x10")
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#define xenable() __asm("andcc #0xbf")
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#define xdisable() __asm("orcc #0x40")
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/* Get the current value of the stack pointer */
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static inline uint16_t up_getsp(void)
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{
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uint16_t ret;
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__asm__
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(
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"\tsts %0\n"
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: "=m"(ret) :
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);
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return ret;
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}
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/* Get the current value of the CCR */
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static inline irqstate_t up_getccr(void)
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{
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irqstate_t ccr;
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__asm__
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(
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"\ttpa\n"
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"\tstaa %0\n"
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: "=m"(ccr) :
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);
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return ccr;
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}
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/* Save the current interrupt enable state & disable IRQs */
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static inline irqstate_t irqsave(void)
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{
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irqstate_t ccr;
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__asm__
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(
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"\ttpa\n"
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"\tstaa %0\n"
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"\torcc #0x50\n"
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: "=m"(ccr) :
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);
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return ccr;
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}
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/* Restore saved interrupt state */
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static inline void irqrestore(irqstate_t flags)
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{
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/* Should interrupts be enabled? */
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if ((flags & HCS12_CCR_I) == 0)
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{
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/* Yes.. unmask I- and Z-interrupts */
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__asm("andcc #0xaf");
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}
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}
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/* System call */
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static inline void system_call3(unsigned int nbr, uintptr_t parm1,
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uintptr_t parm2, uintptr_t parm3)
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{
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/* To be provided */
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/* __asm("swi") */
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}
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/************************************************************************************
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* Public Data
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************************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C" {
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#else
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#define EXTERN extern
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#endif
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/************************************************************************************
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* Public Functions
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************************************************************************************/
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_HC_INCLUDE_HCS12_IRQ_H */
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