mirror of
https://github.com/apache/nuttx.git
synced 2026-06-05 07:12:54 +08:00
Gregory Nutt
f1c79423e1
In stm32_rtcc.c the up_rtcinitialize() logic doesn't work with the LSI. The check on RTC_MAGIC on the BK0R register lead to rtc_setup() call that rightfully enables the lsi clock; but the next times, when the rtc is already setup, the rtc_resume() call does NOT start the lsi clock! The right place to put LSE/LSI initialisation is inside stm32_stdclockconfig() in stm32fxxxxx_rcc.c. Doing this I checked the possible uses of the LSI and the LSE sources: the LSI can be used for RTC and/or the IWDG, while the LSE only for the RTC (and to output the MCO1 pin).. This change is not verifed for any other platforms. From Leo Aloe3132
696 lines
16 KiB
C
696 lines
16 KiB
C
/****************************************************************************
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* arch/arm/src/stm32/stm32f20xxx_rcc.c
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*
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* Copyright (C) 2012, 2015 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include "stm32_pwr.h"
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/* This file supports only the STM32 F2 family (although it is identical to
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* the corresponding F4 file).
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*/
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Allow up to 100 milliseconds for the high speed clock to become ready.
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* that is a very long delay, but if the clock does not become ready we are
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* hosed anyway. Normally this is very fast, but I have seen at least one
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* board that required this long, long timeout for the HSE to be ready.
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*/
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#define HSERDY_TIMEOUT (100 * CONFIG_BOARD_LOOPSPERMSEC)
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: rcc_reset
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*
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* Description:
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* Reset the RCC clock configuration to the default reset state
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*
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****************************************************************************/
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static inline void rcc_reset(void)
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{
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uint32_t regval;
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/* Enable the Internal High Speed clock (HSI) */
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_HSION;
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putreg32(regval, STM32_RCC_CR);
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/* Reset CFGR register */
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putreg32(0x00000000, STM32_RCC_CFGR);
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/* Reset HSEON, CSSON and PLLON bits */
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regval = getreg32(STM32_RCC_CR);
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regval &= ~(RCC_CR_HSEON|RCC_CR_CSSON|RCC_CR_PLLON);
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putreg32(regval, STM32_RCC_CR);
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/* Reset PLLCFGR register to reset default */
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putreg32(RCC_PLLCFG_RESET, STM32_RCC_PLLCFG);
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/* Reset HSEBYP bit */
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regval = getreg32(STM32_RCC_CR);
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regval &= ~RCC_CR_HSEBYP;
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putreg32(regval, STM32_RCC_CR);
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/* Disable all interrupts */
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putreg32(0x00000000, STM32_RCC_CIR);
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}
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/****************************************************************************
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* Name: rcc_enableahb1
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*
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* Description:
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* Enable selected AHB1 peripherals
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*
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****************************************************************************/
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static inline void rcc_enableahb1(void)
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{
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uint32_t regval;
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/* Set the appropriate bits in the AHB1ENR register to enabled the
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* selected AHB1 peripherals.
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*/
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regval = getreg32(STM32_RCC_AHB1ENR);
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/* Enable GPIOA, GPIOB, .... GPIOI*/
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#if STM32_NGPIO > 0
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regval |= (RCC_AHB1ENR_GPIOAEN
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#if STM32_NGPIO > 16
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|RCC_AHB1ENR_GPIOBEN
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#endif
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#if STM32_NGPIO > 32
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|RCC_AHB1ENR_GPIOCEN
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#endif
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#if STM32_NGPIO > 48
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|RCC_AHB1ENR_GPIODEN
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#endif
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#if STM32_NGPIO > 64
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|RCC_AHB1ENR_GPIOEEN
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#endif
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#if STM32_NGPIO > 80
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|RCC_AHB1ENR_GPIOFEN
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#endif
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#if STM32_NGPIO > 96
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|RCC_AHB1ENR_GPIOGEN
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#endif
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#if STM32_NGPIO > 112
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|RCC_AHB1ENR_GPIOHEN
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#endif
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#if STM32_NGPIO > 128
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|RCC_AHB1ENR_GPIOIEN
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#endif
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);
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#endif
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#ifdef CONFIG_STM32_CRC
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/* CRC clock enable */
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regval |= RCC_AHB1ENR_CRCEN;
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#endif
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#ifdef CONFIG_STM32_BKPSRAM
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/* Backup SRAM clock enable */
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regval |= RCC_AHB1ENR_BKPSRAMEN;
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#endif
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#ifdef CONFIG_STM32_DMA1
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/* DMA 1 clock enable */
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regval |= RCC_AHB1ENR_DMA1EN;
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#endif
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#ifdef CONFIG_STM32_DMA2
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/* DMA 2 clock enable */
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regval |= RCC_AHB1ENR_DMA2EN;
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#endif
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#ifdef CONFIG_STM32_ETHMAC
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/* Ethernet MAC clocking */
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regval |= (RCC_AHB1ENR_ETHMACEN|RCC_AHB1ENR_ETHMACTXEN|RCC_AHB1ENR_ETHMACRXEN);
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#ifdef CONFIG_STM32_ETH_PTP
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/* Precision Time Protocol (PTP) */
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regval |= RCC_AHB1ENR_ETHMACPTPEN;
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#endif
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#endif
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#ifdef CONFIG_STM32_OTGHS
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/* USB OTG HS */
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regval |= (RCC_AHB1ENR_OTGHSEN|RCC_AHB1ENR_OTGHSULPIEN);
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#endif
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putreg32(regval, STM32_RCC_AHB1ENR); /* Enable peripherals */
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}
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/****************************************************************************
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* Name: rcc_enableahb2
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*
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* Description:
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* Enable selected AHB2 peripherals
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*
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****************************************************************************/
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static inline void rcc_enableahb2(void)
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{
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uint32_t regval;
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/* Set the appropriate bits in the AHB2ENR register to enabled the
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* selected AHB2 peripherals.
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*/
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regval = getreg32(STM32_RCC_AHB2ENR);
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#ifdef CONFIG_STM32_DCMI
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/* Camera interface enable */
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regval |= RCC_AHB2ENR_DCMIEN;
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#endif
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#ifdef CONFIG_STM32_CRYP
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/* Cryptographic modules clock enable */
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regval |= RCC_AHB2ENR_CRYPEN;
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#endif
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#ifdef CONFIG_STM32_HASH
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/* Hash modules clock enable */
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regval |= RCC_AHB2ENR_HASHEN;
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#endif
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#ifdef CONFIG_STM32_RNG
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/* Random number generator clock enable */
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regval |= RCC_AHB2ENR_RNGEN;
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#endif
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#ifdef CONFIG_STM32_OTGFS
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/* USB OTG FS clock enable */
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regval |= RCC_AHB2ENR_OTGFSEN;
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#endif
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putreg32(regval, STM32_RCC_AHB2ENR); /* Enable peripherals */
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}
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/****************************************************************************
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* Name: rcc_enableahb3
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*
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* Description:
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* Enable selected AHB3 peripherals
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*
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****************************************************************************/
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static inline void rcc_enableahb3(void)
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{
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#ifdef CONFIG_STM32_FSMC
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uint32_t regval;
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/* Set the appropriate bits in the AHB3ENR register to enabled the
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* selected AHB3 peripherals.
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*/
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regval = getreg32(STM32_RCC_AHB3ENR);
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/* Flexible static memory controller module clock enable */
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regval |= RCC_AHB3ENR_FSMCEN;
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putreg32(regval, STM32_RCC_AHB3ENR); /* Enable peripherals */
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#endif
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}
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/****************************************************************************
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* Name: rcc_enableapb1
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*
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* Description:
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* Enable selected APB1 peripherals
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*
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****************************************************************************/
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static inline void rcc_enableapb1(void)
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{
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uint32_t regval;
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/* Set the appropriate bits in the APB1ENR register to enabled the
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* selected APB1 peripherals.
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*/
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regval = getreg32(STM32_RCC_APB1ENR);
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#ifdef CONFIG_STM32_TIM2
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/* TIM2 clock enable */
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regval |= RCC_APB1ENR_TIM2EN;
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#endif
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#ifdef CONFIG_STM32_TIM3
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/* TIM3 clock enable */
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regval |= RCC_APB1ENR_TIM3EN;
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#endif
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#ifdef CONFIG_STM32_TIM4
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/* TIM4 clock enable */
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regval |= RCC_APB1ENR_TIM4EN;
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#endif
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#ifdef CONFIG_STM32_TIM5
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/* TIM5 clock enable */
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regval |= RCC_APB1ENR_TIM5EN;
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#endif
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#ifdef CONFIG_STM32_TIM6
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/* TIM6 clock enable */
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regval |= RCC_APB1ENR_TIM6EN;
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#endif
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#ifdef CONFIG_STM32_TIM7
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/* TIM7 clock enable */
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regval |= RCC_APB1ENR_TIM7EN;
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#endif
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#ifdef CONFIG_STM32_TIM12
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/* TIM12 clock enable */
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regval |= RCC_APB1ENR_TIM12EN;
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#endif
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#ifdef CONFIG_STM32_TIM13
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/* TIM13 clock enable */
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regval |= RCC_APB1ENR_TIM13EN;
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#endif
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#ifdef CONFIG_STM32_TIM14
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/* TIM14 clock enable */
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regval |= RCC_APB1ENR_TIM14EN;
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#endif
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#ifdef CONFIG_STM32_WWDG
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/* Window watchdog clock enable */
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regval |= RCC_APB1ENR_WWDGEN;
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#endif
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#ifdef CONFIG_STM32_SPI2
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/* SPI2 clock enable */
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regval |= RCC_APB1ENR_SPI2EN;
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#endif
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#ifdef CONFIG_STM32_SPI3
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/* SPI3 clock enable */
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regval |= RCC_APB1ENR_SPI3EN;
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#endif
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#ifdef CONFIG_STM32_USART2
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/* USART 2 clock enable */
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regval |= RCC_APB1ENR_USART2EN;
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#endif
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#ifdef CONFIG_STM32_USART3
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/* USART3 clock enable */
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regval |= RCC_APB1ENR_USART3EN;
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#endif
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#ifdef CONFIG_STM32_UART4
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/* UART4 clock enable */
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regval |= RCC_APB1ENR_UART4EN;
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#endif
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#ifdef CONFIG_STM32_UART5
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/* UART5 clock enable */
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regval |= RCC_APB1ENR_UART5EN;
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#endif
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#ifdef CONFIG_STM32_I2C1
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/* I2C1 clock enable */
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regval |= RCC_APB1ENR_I2C1EN;
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#endif
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#ifdef CONFIG_STM32_I2C2
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/* I2C2 clock enable */
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regval |= RCC_APB1ENR_I2C2EN;
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#endif
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#ifdef CONFIG_STM32_I2C3
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/* I2C3 clock enable */
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regval |= RCC_APB1ENR_I2C3EN;
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#endif
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#ifdef CONFIG_STM32_CAN1
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/* CAN 1 clock enable */
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regval |= RCC_APB1ENR_CAN1EN;
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#endif
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#ifdef CONFIG_STM32_CAN2
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/* CAN2 clock enable. NOTE: CAN2 needs CAN1 clock as well. */
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regval |= (RCC_APB1ENR_CAN1EN | RCC_APB1ENR_CAN2EN);
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#endif
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/* Power interface clock enable. The PWR block is always enabled so that
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* we can set the internal voltage regulator for maximum performance.
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*/
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regval |= RCC_APB1ENR_PWREN;
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#if defined (CONFIG_STM32_DAC1) || defined(CONFIG_STM32_DAC2)
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/* DAC interface clock enable */
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regval |= RCC_APB1ENR_DACEN;
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#endif
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putreg32(regval, STM32_RCC_APB1ENR); /* Enable peripherals */
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}
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/****************************************************************************
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* Name: rcc_enableapb2
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*
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* Description:
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* Enable selected APB2 peripherals
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*
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****************************************************************************/
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static inline void rcc_enableapb2(void)
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{
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uint32_t regval;
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/* Set the appropriate bits in the APB2ENR register to enabled the
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* selected APB2 peripherals.
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*/
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regval = getreg32(STM32_RCC_APB2ENR);
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#ifdef CONFIG_STM32_TIM1
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/* TIM1 clock enable */
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regval |= RCC_APB2ENR_TIM1EN;
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#endif
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#ifdef CONFIG_STM32_TIM8
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/* TIM8 clock enable */
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regval |= RCC_APB2ENR_TIM8EN;
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#endif
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#ifdef CONFIG_STM32_USART1
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/* USART1 clock enable */
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regval |= RCC_APB2ENR_USART1EN;
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#endif
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#ifdef CONFIG_STM32_USART6
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/* USART6 clock enable */
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regval |= RCC_APB2ENR_USART6EN;
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#endif
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#ifdef CONFIG_STM32_ADC1
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/* ADC1 clock enable */
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regval |= RCC_APB2ENR_ADC1EN;
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#endif
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#ifdef CONFIG_STM32_ADC2
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/* ADC2 clock enable */
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regval |= RCC_APB2ENR_ADC2EN;
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#endif
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#ifdef CONFIG_STM32_ADC3
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/* ADC3 clock enable */
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regval |= RCC_APB2ENR_ADC3EN;
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#endif
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#ifdef CONFIG_STM32_SDIO
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/* SDIO clock enable */
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regval |= RCC_APB2ENR_SDIOEN;
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#endif
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#ifdef CONFIG_STM32_SPI1
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/* SPI1 clock enable */
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regval |= RCC_APB2ENR_SPI1EN;
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#endif
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#ifdef CONFIG_STM32_SYSCFG
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/* System configuration controller clock enable */
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regval |= RCC_APB2ENR_SYSCFGEN;
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#endif
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#ifdef CONFIG_STM32_TIM9
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/* TIM9 clock enable */
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regval |= RCC_APB2ENR_TIM9EN;
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#endif
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#ifdef CONFIG_STM32_TIM10
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/* TIM10 clock enable */
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regval |= RCC_APB2ENR_TIM10EN;
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#endif
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#ifdef CONFIG_STM32_TIM11
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/* TIM11 clock enable */
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regval |= RCC_APB2ENR_TIM11EN;
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#endif
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putreg32(regval, STM32_RCC_APB2ENR); /* Enable peripherals */
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}
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/****************************************************************************
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* Name: stm32_stdclockconfig
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*
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* Description:
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* Called to change to new clock based on settings in board.h
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*
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* NOTE: This logic would need to be extended if you need to select low-
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* power clocking modes!
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****************************************************************************/
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#ifndef CONFIG_ARCH_BOARD_STM32_CUSTOM_CLOCKCONFIG
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static void stm32_stdclockconfig(void)
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{
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uint32_t regval;
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volatile int32_t timeout;
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/* Enable External High-Speed Clock (HSE) */
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regval = getreg32(STM32_RCC_CR);
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regval |= RCC_CR_HSEON; /* Enable HSE */
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putreg32(regval, STM32_RCC_CR);
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/* Wait until the HSE is ready (or until a timeout elapsed) */
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for (timeout = HSERDY_TIMEOUT; timeout > 0; timeout--)
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{
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/* Check if the HSERDY flag is the set in the CR */
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if ((getreg32(STM32_RCC_CR) & RCC_CR_HSERDY) != 0)
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{
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/* If so, then break-out with timeout > 0 */
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break;
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}
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}
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/* Check for a timeout. If this timeout occurs, then we are hosed. We
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* have no real back-up plan, although the following logic makes it look
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* as though we do.
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|
*/
|
|
|
|
if (timeout > 0)
|
|
{
|
|
/* Select regulator voltage output Scale 1 mode to support system
|
|
* frequencies up to 168 MHz.
|
|
*/
|
|
|
|
regval = getreg32(STM32_RCC_APB1ENR);
|
|
regval |= RCC_APB1ENR_PWREN;
|
|
putreg32(regval, STM32_RCC_APB1ENR);
|
|
|
|
regval = getreg32(STM32_PWR_CR);
|
|
regval |= PWR_CR_VOS;
|
|
putreg32(regval, STM32_PWR_CR);
|
|
|
|
/* Set the HCLK source/divider */
|
|
|
|
regval = getreg32(STM32_RCC_CFGR);
|
|
regval &= ~RCC_CFGR_HPRE_MASK;
|
|
regval |= STM32_RCC_CFGR_HPRE;
|
|
putreg32(regval, STM32_RCC_CFGR);
|
|
|
|
/* Set the PCLK2 divider */
|
|
|
|
regval = getreg32(STM32_RCC_CFGR);
|
|
regval &= ~RCC_CFGR_PPRE2_MASK;
|
|
regval |= STM32_RCC_CFGR_PPRE2;
|
|
putreg32(regval, STM32_RCC_CFGR);
|
|
|
|
/* Set the PCLK1 divider */
|
|
|
|
regval = getreg32(STM32_RCC_CFGR);
|
|
regval &= ~RCC_CFGR_PPRE1_MASK;
|
|
regval |= STM32_RCC_CFGR_PPRE1;
|
|
putreg32(regval, STM32_RCC_CFGR);
|
|
|
|
#ifdef CONFIG_RTC_HSECLOCK
|
|
/* Set the RTC clock divisor */
|
|
|
|
regval = getreg32(STM32_RCC_CFGR);
|
|
regval &= ~RCC_CFGR_RTCPRE_MASK;
|
|
regval |= RCC_CFGR_RTCPRE(HSE_DIVISOR);
|
|
putreg32(regval, STM32_RCC_CFGR);
|
|
#endif
|
|
|
|
/* Set the PLL dividers and multipliers to configure the main PLL */
|
|
|
|
regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP |
|
|
RCC_PLLCFG_PLLSRC_HSE | STM32_PLLCFG_PLLQ);
|
|
putreg32(regval, STM32_RCC_PLLCFG);
|
|
|
|
/* Enable the main PLL */
|
|
|
|
regval = getreg32(STM32_RCC_CR);
|
|
regval |= RCC_CR_PLLON;
|
|
putreg32(regval, STM32_RCC_CR);
|
|
|
|
/* Wait until the PLL is ready */
|
|
|
|
while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0);
|
|
|
|
/* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */
|
|
|
|
#ifdef CONFIG_STM32_FLASH_PREFETCH
|
|
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN);
|
|
#else
|
|
regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN);
|
|
#endif
|
|
putreg32(regval, STM32_FLASH_ACR);
|
|
|
|
/* Select the main PLL as system clock source */
|
|
|
|
regval = getreg32(STM32_RCC_CFGR);
|
|
regval &= ~RCC_CFGR_SW_MASK;
|
|
regval |= RCC_CFGR_SW_PLL;
|
|
putreg32(regval, STM32_RCC_CFGR);
|
|
|
|
/* Wait until the PLL source is used as the system clock source */
|
|
|
|
while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL);
|
|
|
|
#if defined(CONFIG_STM32_IWDG) || defined(CONFIG_RTC_LSICLOCK)
|
|
/* Low speed internal clock source LSI */
|
|
|
|
stm32_rcc_enablelsi();
|
|
#endif
|
|
|
|
#if defined(CONFIG_RTC_LSECLOCK)
|
|
/* Low speed external clock source LSE
|
|
*
|
|
* TODO: There is another case where the LSE needs to
|
|
* be enabled: if the MCO1 pin selects LSE as source.
|
|
*/
|
|
|
|
stm32_rcc_enablelse();
|
|
#endif
|
|
}
|
|
}
|
|
#endif
|
|
|
|
/****************************************************************************
|
|
* Name: rcc_enableperiphals
|
|
****************************************************************************/
|
|
|
|
static inline void rcc_enableperipherals(void)
|
|
{
|
|
rcc_enableahb1();
|
|
rcc_enableahb2();
|
|
rcc_enableahb3();
|
|
rcc_enableapb1();
|
|
rcc_enableapb2();
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Public Functions
|
|
****************************************************************************/
|