Gregory Nutt 588d2b506f Xtensa ESP32: Oddly, an rsync barrier when writing to co-processor register corrects problem.

2016-12-21 08:04:48 -06:00

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esp32

Xtensa ESP32: Basically a redesign of the interrupt dispatch logic.

2016-12-16 15:36:52 -06:00

lx6

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xtensa

Xtensa ESP32: Oddly, an rsync barrier when writing to co-processor register corrects problem.

2016-12-21 08:04:48 -06:00

.gitignore

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arch.h

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inttypes.h

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irq.h

Fix windowspill register handling + Use r6, not r2 when passing paramters with call4

2016-12-16 09:20:36 -06:00

limits.h

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serial.h

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spinlock.h

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syscall.h

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types.h

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