Huang Qi bac2df6bc8 risc-v: replace fence.i with __ISB for instruction sync ...

Summary:
- Replace direct use of `fence.i` instruction with `__ISB()` macro for instruction synchronization
- This change improves portability while maintaining the same functionality

Impact:
- No functional changes - both `fence.i` and `__ISB()` ensure instruction
synchronization on RISC-V
- Makes the code more maintainable by using the architecture abstraction
layer

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>

2025-01-17 09:04:45 +08:00

..

arm

armv8-r/libc: optimize libc string apis with asm

2024-11-26 10:22:12 +08:00

arm64

Remove FAR from 32/64bit arch

2024-12-05 22:55:39 +08:00

renesas

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risc-v

risc-v: replace fence.i with __ISB for instruction sync

2025-01-17 09:04:45 +08:00

sim

Remove FAR from 32/64bit arch

2024-12-05 22:55:39 +08:00

sparc

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tricore

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x86

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x86_64

libc/gnu: fix typo adress -> address

2024-12-17 20:48:07 +08:00

xtensa

xtensa: change write intset register to syscall instruction

2024-12-27 00:25:55 +08:00

arch_atomic.c

fix a typo

2024-12-17 16:20:46 +08:00

arch_libc.c

kasan/kconfig: Add config CONFIG_MM_KASAN_INSTRUMENT

2025-01-14 14:01:48 +08:00

CMakeLists.txt

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Kconfig

arch_atomic : Introduce CONFIG_LIBC_ARCH_ATOMIC

2024-11-15 14:01:56 +08:00

Make.defs

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