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https://github.com/apache/nuttx.git
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Gregory Nutt
2895 lines
100 KiB
C
2895 lines
100 KiB
C
/****************************************************************************
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* arch/arm/src/tiva/tiva_adc.c
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*
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* Copyright (C) 2015 TRD2 Inc. All rights reserved.
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* Author: Calvin Maguranis <calvin.maguranis@trd2inc.com>
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*
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* References:
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*
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* TM4C123GH6PM Series Data Sheet
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* TI Tivaware driverlib ADC sample code.
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*
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* The Tivaware sample code has a BSD compatible license that requires this
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* copyright notice:
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*
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* Copyright (c) 2005-2014 Texas Instruments Incorporated. All rights reserved.
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* Software License Agreement
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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*
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* Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in the
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* documentation and/or other materials provided with the
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* distribution.
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*
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* Neither the name of Texas Instruments Incorporated nor the names of
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* its contributors may be used to endorse or promote products derived
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* from this software without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR
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* A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT
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* OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL,
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* SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT
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* LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS OF USE,
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* DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY
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* THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE
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* OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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*
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* This is part of revision 2.1.0.12573 of the Tiva Peripheral Driver Library.
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*****************************************************************************/
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/* Keep in mind that for every step there should be another entry in the
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* CONFIG_ADC_FIFOSIZE value.
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* e.g. if there are 12 steps in use; CONFIG_ADC_FIFOSIZE = 12+1 = 13
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* if there are 3 steps in use; CONFIG_ADC_FIFOSIZE = 3+1 = 4
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*/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <sys/types.h>
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#include <sys/ioctl.h>
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#include <stdio.h>
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#include <stdint.h>
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#include <stdbool.h>
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#include <semaphore.h>
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#include <errno.h>
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#include <debug.h>
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#include <assert.h>
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#include <arch/board/board.h>
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#include <nuttx/arch.h>
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#include <nuttx/wqueue.h>
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#include <nuttx/analog/adc.h>
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#include "up_internal.h"
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#include "up_arch.h"
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#include "chip.h"
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#include "tiva_gpio.h"
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#include "tiva_adc.h"
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#include "chip/tiva_pinmap.h"
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#include "chip/tiva_syscontrol.h"
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#include "chip/tiva_adc.h"
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#if defined (CONFIG_TIVA_ADC0) || defined (CONFIG_TIVA_ADC1)
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Misc utility defines *****************************************************/
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# define TIVA_ADC_ENABLE true
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# define TIVA_ADC_DISABLE false
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# define TIVA_ADC_RESOLUTION 4095
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# ifdef CONFIG_ARCH_CHIP_TM4C123
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# define TIVA_ADC_CLOCK_MAX (16000000)
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# define TIVA_ADC_CLOCK_MIN (16000000)
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# elif CONFIG_ARCH_CHIP_TM4C129
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# define TIVA_ADC_CLOCK_MAX (32000000)
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# define TIVA_ADC_CLOCK_MIN (16000000)
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# else
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# error TIVA_ADC_CLOCK: unsupported architecture
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# endif /* CONFIG_ARCH_CHIP_TM4C129 */
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/* Allow the same function call to be used for sample rate */
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# ifdef CONFIG_ARCH_CHIP_TM4C123
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# define TIVA_ADC_SAMPLE_RATE_SLOWEST (ADC_PC_SR_125K)
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# define TIVA_ADC_SAMPLE_RATE_SLOW (ADC_PC_SR_250K)
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# define TIVA_ADC_SAMPLE_RATE_FAST (ADC_PC_SR_500K)
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# define TIVA_ADC_SAMPLE_RATE_FASTEST (ADC_PC_SR_1M)
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# elif CONFIG_ARCH_CHIP_TM4C129
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# define TIVA_ADC_SAMPLE_RATE_SLOWEST (ADC_PC_MCR_1_8)
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# define TIVA_ADC_SAMPLE_RATE_SLOW (ADC_PC_MCR_1_4)
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# define TIVA_ADC_SAMPLE_RATE_FAST (ADC_PC_MCR_1_2)
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# define TIVA_ADC_SAMPLE_RATE_FASTEST (ADC_PC_MCR_FULL)
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# else
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# error TIVA_ADC_SAMPLE_RATE: unsupported architecture
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# endif /* CONFIG_ARCH_CHIP_TM4C12* */
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/* Configuration ************************************************************/
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# ifndef CONFIG_TIVA_ADC_CLOCK
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# define CONFIG_TIVA_ADC_CLOCK TIVA_ADC_CLOCK_MIN
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# endif
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# ifdef CONFIG_TIVA_ADC_VREF
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# ifndef CONFIG_ARCH_CHIP_TM4C129
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# error Voltage reference selection only supported in TM4C129 parts
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# endif /* CONFIG_ARCH_CHIP_TM4C129 */
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# endif /* CONFIG_TIVA_ADC_VREF */
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# ifdef CONFIG_TIVA_ADC_ALT_CLK
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# warning CONFIG_TIVA_ADC_ALT_CLK unsupported.
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# endif /* CONFIG_TIVA_ADC_ALT_CLK */
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/* Utility macros ***********************************************************/
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/* PWM trigger support definitions ******************************************/
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/* Decodes the PWM generator and module from trigger and converts
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* to the TSSEL_PS register
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*/
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# define ADC_TRIG_PWM_CFG(t) \
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(1<<(ADC_TSSEL_PS_SHIFT(ADC_TRIG_PWM_GEN(t))))
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/* ADC support definitions **************************************************/
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# define ADC_CHN_AIN(n) GPIO_ADC_AIN##n
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# define TIVA_ADC_PIN(n) ADC_CHN_AIN(n)
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# define SSE_PROC_TRIG(n) (1 << (n))
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# define SSE_PROC_TRIG_ALL (0xF)
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# define SSE_IDX(a,s) (((a)*SSE_PER_BASE) + (s))
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# define MAX_NORMAL_CHN 15
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# define BASE_PER_ADC 2
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# define SSE_PER_BASE 4
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# define SSE_MAX_STEP 8
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# define NUM_SSE(n) (sizeof(n)/sizeof(n[0]))
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# define GET_AIN(a,s,c) (uint8_t)((getreg32( \
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TIVA_ADC_BASE(a)+TIVA_ADC_SSMUX(s)) & ADC_SSMUX_MUX_MASK(c)) >> ADC_SSMUX_MUX_SHIFT(c))
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# define ADC_SSE_STEP_NULL 0xFF
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# define CLOCK_CONFIG(div, src) \
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( ((((div) << ADC_CC_CLKDIV_SHIFT) & ADC_CC_CLKDIV_MASK) | \
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((src) & ADC_CC_CS_MASK)) & (ADC_CC_CLKDIV_MASK + ADC_CC_CS_MASK) )
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# define SEM_PROCESS_PRIVATE 0
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# define SEM_PROCESS_SHARED 1
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/* Debug ********************************************************************/
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/* CONFIG_DEBUG_ADC + CONFIG_DEBUG enables general ADC debug output. */
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# ifdef CONFIG_DEBUG_ADC
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# define adcdbg dbg
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# define adcvdbg vdbg
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# else
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# define adcdbg(x...)
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# define adcvdbg(x...)
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# endif
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# ifndef CONFIG_DEBUG
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# undef CONFIG_TIVA_ADC_REGDEBUG
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# endif
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/* ADC event trace logic. NOTE: trace uses the internal, non-standard, low-level
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* debug interface syslog() but does not require that any other debug
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* is enabled.
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*/
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# ifndef CONFIG_ADC_TRACE
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# define tiva_adc_tracereset(p)
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# define tiva_adc_tracenew(p,s)
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# define tiva_adc_traceevent(p,e,a)
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# define tiva_adc_tracedump(p)
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# endif
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# ifndef CONFIG_ADC_NTRACE
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# define CONFIG_ADC_NTRACE 32
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# endif
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/****************************************************************************
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* Public Functions
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* **************************************************************************/
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/* Upper level ADC driver ***************************************************/
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static void tiva_adc_reset(struct adc_dev_s *dev);
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static int tiva_adc_setup(struct adc_dev_s *dev);
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static void tiva_adc_shutdown(struct adc_dev_s *dev);
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static void tiva_adc_rxint(struct adc_dev_s *dev, bool enable);
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static int tiva_adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg);
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/* ADC lower half device operations */
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static const struct adc_ops_s g_adcops =
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{
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.ao_reset = tiva_adc_reset,
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.ao_setup = tiva_adc_setup,
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.ao_shutdown = tiva_adc_shutdown,
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.ao_rxint = tiva_adc_rxint,
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.ao_ioctl = tiva_adc_ioctl,
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};
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/****************************************************************************
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* Private Types
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****************************************************************************/
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/* tracks overall ADC peripherals one-time initialization state */
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struct tiva_adc_state_s
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{
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bool init[BASE_PER_ADC];
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bool sse[BASE_PER_ADC * SSE_PER_BASE];
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};
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struct tiva_adc_s
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{
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struct adc_dev_s *dev;
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bool ena; /* Operation state */
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uint8_t devno; /* ADC device number */
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struct tiva_adc_sse_s *sse[SSE_PER_BASE]; /* Sample sequencer operation
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* state */
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/* Debug stuff */
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# ifdef CONFIG_TIVA_ADC_REGDEBUG
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bool wrlast; /* Last was a write */
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uintptr_t addrlast; /* Last address */
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uint32_t vallast; /* Last value */
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int ntimes; /* Number of times */
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# endif /* CONFIG_TIVA_ADC_REGDEBUG */
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};
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struct tiva_adc_sse_s
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{
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sem_t exclsem; /* Mutual exclusion semaphore */
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bool ena; /* Sample sequencer operation state */
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uint32_t irq; /* SSE interrupt vectors */
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uint8_t num; /* SSE number */
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};
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/****************************************************************************
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* Private Function Definitions
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****************************************************************************/
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/* Debug ADC functions **********************************************/
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# if defined(CONFIG_TIVA_ADC_REGDEBUG) && defined(CONFIG_DEBUG)
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static bool tiva_adc_checkreg(struct tiva_adc_s *priv, bool wr,
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uint32_t regval, uintptr_t address);
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# endif
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# ifdef CONFIG_TIVA_ADC_REGDEBUG
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static void tiva_adc_modifyreg(struct tiva_adc_s *priv, unsigned int addr,
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uint32_t clearbits, uint32_t setbits);
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# else
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# define tiva_adc_modifyreg(priv,addr,clearbits,setbits) modifyreg32(addr,clearbits,setbits)
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# endif
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/* TM4C-specific ADC functions **********************************************/
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/* Common peripheral level */
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static int adc_state(struct tiva_adc_s *adc, bool state);
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static void adc_clock(uint32_t freq);
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# ifdef CONFIG_ARCH_CHIP_TM4C129
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static void adc_vref(uint8_t vref);
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# endif /* CONFIG_ARCH_CHIP_TM4C129 */
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/* Peripheral (base) level */
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static void adc_sample_rate(uint8_t rate);
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static void adc_proc_trig(struct tiva_adc_s *adc, uint8_t sse_mask);
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static uint32_t adc_int_status(struct tiva_adc_s *adc);
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/* Sample Sequencer (SSE) level */
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static void sse_state(struct tiva_adc_s *adc, uint8_t sse, bool state);
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static void sse_trigger(struct tiva_adc_s *adc, uint8_t sse, uint32_t trigger);
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# ifdef CONFIG_EXPERIMENTAL
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static void sse_pwm_trig_ioctl(struct tiva_adc_s *adc, uint8_t sse,
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uint32_t cfg);
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# endif
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static int sse_data(struct tiva_adc_s *adc, uint8_t sse);
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static void sse_priority(struct tiva_adc_s *adc, uint8_t sse, uint8_t priority);
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static void sse_int_state(struct tiva_adc_s *adc, uint8_t sse, bool state);
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static bool sse_int_status(struct tiva_adc_s *adc, uint8_t sse);
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static void sse_clear_int(struct tiva_adc_s *adc, uint8_t sse);
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static void sse_register_chn(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
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uint32_t ain);
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static void sse_differential(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
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uint32_t diff);
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# ifdef CONFIG_EXPERIMENTAL
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static void sse_sample_hold_time(struct tiva_adc_s *adc, uint8_t sse,
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uint8_t chn, uint32_t shold);
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# endif
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static void sse_step_cfg(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
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uint8_t cfg);
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/* Helper functions *********************************************************/
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# ifdef CONFIG_TIVA_ADC0
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static void tiva_adc0_sse_init(void);
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static void tiva_adc0_assign_channels(void);
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static void tiva_adc0_assign_interrupts(void);
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# ifdef CONFIG_TIVA_ADC0_SSE0
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static void adc0_sse0_chn_cfg(void);
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static void adc0_sse0_interrupt(int irq, void *context);
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# endif
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# ifdef CONFIG_TIVA_ADC0_SSE1
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static void adc0_sse1_chn_cfg(void);
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static void adc0_sse1_interrupt(int irq, void *context);
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# endif
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# ifdef CONFIG_TIVA_ADC0_SSE2
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static void adc0_sse2_chn_cfg(void);
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static void adc0_sse2_interrupt(int irq, void *context);
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# endif
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# ifdef CONFIG_TIVA_ADC0_SSE3
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static void adc0_sse3_chn_cfg(void);
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static void adc0_sse3_interrupt(int irq, void *context);
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# endif
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# endif
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# ifdef CONFIG_TIVA_ADC1
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static void tiva_adc1_sse_init(void);
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static void tiva_adc1_assign_channels(void);
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static void tiva_adc1_assign_interrupts(void);
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# ifdef CONFIG_TIVA_ADC1_SSE0
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static void adc1_sse0_chn_cfg(void);
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static void adc1_sse0_interrupt(int irq, void *context);
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# endif
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# ifdef CONFIG_TIVA_ADC1_SSE1
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static void adc1_sse1_chn_cfg(void);
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static void adc1_sse1_interrupt(int irq, void *context);
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# endif
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# ifdef CONFIG_TIVA_ADC1_SSE2
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static void adc1_sse2_chn_cfg(void);
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static void adc1_sse2_interrupt(int irq, void *context);
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# endif
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# ifdef CONFIG_TIVA_ADC1_SSE3
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static void adc1_sse3_chn_cfg(void);
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static void adc1_sse3_interrupt(int irq, void *context);
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# endif
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# endif
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* Tracks overall peripheral state */
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static struct tiva_adc_state_s adc_common =
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{
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.init = {
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false,
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false},
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.sse = {
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false,
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false,
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false,
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false,
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false,
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false,
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false,
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false},
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};
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# ifdef CONFIG_TIVA_ADC0
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/* ADC device instance 0 */
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static struct adc_dev_s g_adcdev0;
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static struct tiva_adc_s adc0;
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# ifdef CONFIG_TIVA_ADC0_SSE0
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static struct tiva_adc_sse_s sse00;
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# endif
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# ifdef CONFIG_TIVA_ADC0_SSE1
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static struct tiva_adc_sse_s sse01;
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# endif
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# ifdef CONFIG_TIVA_ADC0_SSE2
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static struct tiva_adc_sse_s sse02;
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# endif
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# ifdef CONFIG_TIVA_ADC0_SSE3
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static struct tiva_adc_sse_s sse03;
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# endif
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# endif
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# ifdef CONFIG_TIVA_ADC1
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/* ADC device instance 1 */
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static struct adc_dev_s g_adcdev1;
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static struct tiva_adc_s adc1;
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# ifdef CONFIG_TIVA_ADC1_SSE0
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static struct tiva_adc_sse_s sse10;
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# endif
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# ifdef CONFIG_TIVA_ADC1_SSE1
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static struct tiva_adc_sse_s sse11;
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# endif
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# ifdef CONFIG_TIVA_ADC1_SSE2
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static struct tiva_adc_sse_s sse12;
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# endif
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# ifdef CONFIG_TIVA_ADC1_SSE3
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static struct tiva_adc_sse_s sse13;
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# endif
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# endif
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: tiva_adc_reset
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*
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* Description:
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* Reset the ADC device. Called early to initialize the hardware. This is
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* called before tiva_adc_setup() and on error conditions.
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*
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****************************************************************************/
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static void tiva_adc_reset(struct adc_dev_s *dev)
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{
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struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv;
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adcvdbg("Resetting...\n");
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/* Only if ADCs are active do we run the reset routine: - disable ADC
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* interrupts - clear interrupt bits - disable all active sequences
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* Otherwise, if the peripheral is inactive, perform no operations since
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* register access to a peripheral that is not active will result in a
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* segmentation fault.
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*/
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if (priv->ena)
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{
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tiva_adc_rxint(dev, TIVA_ADC_DISABLE);
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uint8_t s;
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for (s = 0; s < SSE_PER_BASE; ++s)
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|
{
|
|
if (adc_common.sse[SSE_IDX(priv->devno, s)])
|
|
{
|
|
sse_state(priv, s, TIVA_ADC_DISABLE);
|
|
}
|
|
}
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: tiva_adc_setup
|
|
*
|
|
* Description:
|
|
* Configure the ADC. This method is called the first time that the ADC
|
|
* device is opened. This will occur when the port is first opened.
|
|
* this setup includes configuring and attaching ADC interrupts. Interrupts
|
|
* are all disabled upon return.
|
|
*
|
|
* Returned Value:
|
|
* Non negative value on success; negative value on failure.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static int tiva_adc_setup(struct adc_dev_s *dev)
|
|
{
|
|
adcvdbg("Setup\n");
|
|
/* Only if ADCs are active do we run the reset routine: - enable ADC
|
|
* interrupts - clear interrupt bits - enable all active sequences - register
|
|
* triggers and respective interrupt handlers Otherwise, if the peripheral is
|
|
* inactive, perform no operations since register access to a peripheral that
|
|
* is not active will result in a segmentation fault.
|
|
*/
|
|
|
|
struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv;
|
|
uint8_t s = 0;
|
|
for (s = 0; s < SSE_PER_BASE; ++s)
|
|
{
|
|
if (adc_common.sse[SSE_IDX(priv->devno, s)])
|
|
{
|
|
sse_state(priv, s, true);
|
|
}
|
|
}
|
|
|
|
tiva_adc_rxint(dev, false);
|
|
return OK;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: tiva_adc_shutdown
|
|
*
|
|
* Description:
|
|
* Disable the ADC. This method is called when the ADC device is closed.
|
|
* This method reverses the operation the setup method.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void tiva_adc_shutdown(struct adc_dev_s *dev)
|
|
{
|
|
struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv;
|
|
adcvdbg("Shutdown\n");
|
|
|
|
/* Reset the ADC peripheral */
|
|
tiva_adc_reset(dev);
|
|
|
|
uint8_t s = 0;
|
|
for (s = 0; s < SSE_PER_BASE; ++s)
|
|
{
|
|
if (adc_common.sse[SSE_IDX(priv->devno, s)])
|
|
{
|
|
/* Disable ADC interrupts at the level of the AIC */
|
|
|
|
up_disable_irq(priv->sse[s]->irq);
|
|
|
|
/* Then detach the ADC interrupt handler. */
|
|
|
|
irq_detach(priv->sse[s]->irq);
|
|
}
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: tiva_adc_rxint
|
|
*
|
|
* Description:
|
|
* Call to enable or disable RX interrupts
|
|
*
|
|
* Input Parameters:
|
|
* enable - the enable state of interrupts for this device
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void tiva_adc_rxint(struct adc_dev_s *dev, bool enable)
|
|
{
|
|
struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv;
|
|
adcvdbg("rx enable=%d\n", enable);
|
|
|
|
uint8_t s = 0;
|
|
for (s = 0; s < SSE_PER_BASE; ++s)
|
|
{
|
|
uint32_t trigger =
|
|
(tiva_adc_getreg(priv, TIVA_ADC_EMUX(priv->devno)) >> s) & 0xF;
|
|
if (adc_common.sse[SSE_IDX(priv->devno, s)] && (trigger > 0))
|
|
{
|
|
sse_state(priv, s, enable);
|
|
}
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: tiva_adc_ioctl
|
|
*
|
|
* Description:
|
|
* All ioctl calls will be routed through this method.
|
|
*
|
|
* Input Parameters:
|
|
* cmd - ADC ioctl command
|
|
* arg - argument for the ioctl command
|
|
*
|
|
* Returned Value:
|
|
* Non negative value on success; negative value on failure.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static int tiva_adc_ioctl(struct adc_dev_s *dev, int cmd, unsigned long arg)
|
|
{
|
|
struct tiva_adc_s *priv = (struct tiva_adc_s *)dev->ad_priv;
|
|
int ret = OK;
|
|
uint32_t stat = 0;
|
|
uint8_t sse = (uint8_t) arg;
|
|
|
|
adcvdbg("cmd=%d arg=%ld\n", cmd, arg);
|
|
switch (cmd)
|
|
{
|
|
/* Software trigger */
|
|
|
|
case ANIOC_TRIGGER:
|
|
|
|
/* start conversion and read to buffer */
|
|
|
|
adc_proc_trig(priv, (uint8_t) SSE_PROC_TRIG(sse));
|
|
stat = adc_int_status(priv) & (1 << sse);
|
|
while (!stat)
|
|
{
|
|
stat = adc_int_status(priv) & (1 << sse);
|
|
}
|
|
|
|
sse_clear_int(priv, sse);
|
|
sse_data(priv, sse);
|
|
break;
|
|
|
|
/* TODO: Needs to be tested, needs to encode which SSE since trigger type
|
|
* isn't tracked and, needs a PWM driver to use.
|
|
*/
|
|
|
|
# if 0
|
|
/* PWM triggering */
|
|
|
|
case TIVA_ADC_PWM_TRIG_IOCTL:
|
|
for (s = 0; s < SSE_PER_BASE; ++s)
|
|
{
|
|
if (adc_common.sse[SSE_IDX(priv->devno, s)])
|
|
{
|
|
/* TODO: fixme */
|
|
if (priv, s->trigger & ADC_TRIG_PWM_MASK)
|
|
{
|
|
sse_pwm_trig_ioctl(priv, s, (uint32_t) arg);
|
|
}
|
|
}
|
|
}
|
|
break;
|
|
# endif
|
|
|
|
/* Unsupported or invalid command */
|
|
|
|
default:
|
|
ret = -ENOTTY;
|
|
break;
|
|
}
|
|
|
|
return ret;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Register Operations
|
|
****************************************************************************/
|
|
|
|
# ifdef CONFIG_TIVA_ADC_REGDEBUG
|
|
|
|
/****************************************************************************
|
|
* Name: tiva_adc_checkreg
|
|
*
|
|
* Description:
|
|
* Check if the current register access is a duplicate of the preceding.
|
|
*
|
|
* Input Parameters:
|
|
* regval - The value to be written
|
|
* address - The address of the register to write to
|
|
*
|
|
* Returned Value:
|
|
* true: This is the first register access of this type.
|
|
* flase: This is the same as the preceding register access.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static bool tiva_adc_checkreg(struct tiva_adc_s *priv, bool wr,
|
|
uint32_t regval, uintptr_t address)
|
|
{
|
|
if (wr == priv->wrlast && /* Same kind of access? */
|
|
regval == priv->vallast && /* Same value? */
|
|
address == priv->addrlast) /* Same address? */
|
|
{
|
|
/* Yes, then just keep a count of the number of times we did this. */
|
|
|
|
priv->ntimes++;
|
|
return false;
|
|
}
|
|
else
|
|
{
|
|
/* Did we do the previous operation more than once? */
|
|
|
|
if (priv->ntimes > 0)
|
|
{
|
|
/* Yes... show how many times we did it */
|
|
|
|
lldbg("...[Repeats %d times]...\n", priv->ntimes);
|
|
}
|
|
|
|
/* Save information about the new access */
|
|
|
|
priv->wrlast = wr;
|
|
priv->vallast = regval;
|
|
priv->addrlast = address;
|
|
priv->ntimes = 0;
|
|
}
|
|
|
|
/* Return true if this is the first time that we have done this operation */
|
|
|
|
return true;
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC_REGDEBUG */
|
|
|
|
/****************************************************************************
|
|
* Name: tiva_adc_modifyreg
|
|
*
|
|
* Description:
|
|
* Atomically modify the specified bits in a memory mapped register
|
|
*
|
|
* Input Parameters:
|
|
* addr - The address of the register to write to
|
|
*
|
|
****************************************************************************/
|
|
|
|
# ifdef CONFIG_TIVA_ADC_REGDEBUG
|
|
static void tiva_adc_modifyreg(struct tiva_adc_s *priv, unsigned int addr,
|
|
uint32_t clearbits, uint32_t setbits)
|
|
{
|
|
uint32_t regval = 0;
|
|
irqstate_t flags = irqsave();
|
|
regval = tiva_adc_getreg(priv, addr);
|
|
regval &= ~clearbits;
|
|
regval |= setbits;
|
|
tiva_adc_putreg(priv, addr, regval);
|
|
irqrestore(flags);
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC_REGDEBUG */
|
|
|
|
/* TM4C-specific ADC functions **********************************************/
|
|
|
|
/* Peripheral (base) level **************************************************/
|
|
|
|
/****************************************************************************
|
|
* Name: adc_state
|
|
*
|
|
* Description:
|
|
* Toggles the operational state of the ADC peripheral
|
|
*
|
|
* Input Parameters:
|
|
* state - operation state
|
|
*
|
|
****************************************************************************/
|
|
|
|
static int adc_state(struct tiva_adc_s *adc, bool state)
|
|
{
|
|
if (state == TIVA_ADC_ENABLE)
|
|
{
|
|
|
|
/* Enable clocking to the ADC peripheral */
|
|
|
|
# ifdef TIVA_SYSCON_RCGCADC
|
|
modifyreg32(TIVA_SYSCON_RCGCADC, 0, 1 << adc->devno);
|
|
# else
|
|
modifyreg32(TIVA_SYSCON_RCGC0, 0, SYSCON_RCGC0_ADC0);
|
|
# endif
|
|
return OK;
|
|
}
|
|
else if (state == TIVA_ADC_DISABLE)
|
|
{
|
|
/* Disable clocking to the ADC peripheral */
|
|
|
|
# ifdef TIVA_SYSCON_RCGCADC
|
|
modifyreg32(TIVA_SYSCON_RCGCADC, 1 << adc->devno, 0);
|
|
# else
|
|
modifyreg32(TIVA_SYSCON_RCGC0, SYSCON_RCGC0_ADC0, 0);
|
|
# endif
|
|
return OK;
|
|
}
|
|
|
|
/* ERROR! */
|
|
|
|
return -1;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: adc_clock
|
|
*
|
|
* Description:
|
|
* Sets the ADC peripherals clock to the desired frequency.
|
|
*
|
|
* Input Parameters:
|
|
* freq - ADC clock value; dependent on platform:
|
|
*
|
|
* TM4C123 - Select either MOSC or PIOSC. Both result in 16 MHz operation,
|
|
* however the PIOSC allows the ADC to operate in deep sleep mode.
|
|
*
|
|
* TM4C129 - For the 129, there is still a selection between various internal
|
|
* clocks, however the output frequency is variable (16 MHz - 32 MHz); so it
|
|
* is much more intuitive to allow the clock variable be a frequency value.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void adc_clock(uint32_t freq)
|
|
{
|
|
# if defined(CONFIG_ARCH_CHIP_TM4C123)
|
|
/* For the TM4C123, the ADC clock source does not affect the frequency, it
|
|
* runs at 16 MHz regardless. You end up selecting between the MOSC (default)
|
|
* or the PIOSC. The PIOSC allows the ADC to operate even in deep sleep mode.
|
|
* Since this is the case, the clock value for
|
|
*/
|
|
|
|
uintptr_t ccreg = (TIVA_ADC0_BASE + TIVA_ADC_CC_OFFSET);
|
|
modifyreg32(ccreg, 0, (freq & ADC_CC_CS_MASK));
|
|
# elif defined (CONFIG_ARCH_CHIP_TM4C129)
|
|
|
|
/* check clock bounds and specific match cases */
|
|
|
|
uint32_t clk_src = 0;
|
|
uint32_t div = 0;
|
|
if (clock > TIVA_ADC_CLOCK_MAX)
|
|
{
|
|
clk_src = ADC_CC_CS_SYSPLL;
|
|
div = (BOARD_FVCO_FREQUENCY / TIVA_ADC_CLOCK_MAX);
|
|
}
|
|
else if (clock < TIVA_ADC_CLOCK_MIN)
|
|
{
|
|
clk_src = ADC_CC_CS_PIOSC;
|
|
div = 1;
|
|
}
|
|
else if (clock == XTAL_FREQUENCY)
|
|
{
|
|
clk_src = ADC_CC_CS_MOSC;
|
|
div = 1;
|
|
}
|
|
else
|
|
{
|
|
clk_src = ADC_CC_CS_SYSPLL;
|
|
div = (BOARD_FVCO_FREQUENCY / freq);
|
|
}
|
|
|
|
uintptr_t ccreg = (TIVA_ADC0_BASE + TIVA_ADC_CC_OFFSET);
|
|
modifyreg32(ccreg, 0, CLOCK_CONFIG(div, clk_src));
|
|
# else
|
|
# error Unsupported architecture reported
|
|
# endif
|
|
}
|
|
|
|
# ifdef CONFIG_ARCH_CHIP_TM4C129
|
|
|
|
/****************************************************************************
|
|
* Name: adc_vref
|
|
*
|
|
* Description:
|
|
* Sets the ADC peripherals clock to the desired frequency.
|
|
*
|
|
* Input Parameters:
|
|
* vref - ADC clock voltage reference source
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void adc_vref(uint8_t vref)
|
|
{
|
|
uintptr_t ctlreg = (TIVA_ADC0_BASE + TIVA_ADC_CTL_OFFSET);
|
|
if (vref == 0)
|
|
{
|
|
modifyreg32(ctlreg, vref, 0);
|
|
}
|
|
else
|
|
{
|
|
modifyreg32(ctlreg, 0, vref);
|
|
}
|
|
}
|
|
# endif
|
|
|
|
/****************************************************************************
|
|
* Name: adc_sample_rate
|
|
*
|
|
* Description:
|
|
* Sets the ADC sample rate as follows for each processor.
|
|
* TM4C123 - by maximum samples: 125 ksps, 250 ksps, 500 ksps or 1 Msps
|
|
* TM4C129 - by a divisor either being full, half, quarter or
|
|
* an eighth.
|
|
*
|
|
* Input Parameters:
|
|
* rate - ADC sample rate divisor
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void adc_sample_rate(uint8_t rate)
|
|
{
|
|
uintptr_t pcreg = (TIVA_ADC0_BASE + TIVA_ADC_PC_OFFSET);
|
|
|
|
/*
|
|
* NOTE: ADC_PC_SR_MASK is intended for use with the TM4C123, the
|
|
* alternative is ADC_PC_MCR_MASK for the TM4C129. However both masks
|
|
* mask off the first 4 bits (0xF) so there is no need to distinguish
|
|
* between the two.
|
|
*/
|
|
|
|
modifyreg32(pcreg, 0, (rate & ADC_PC_SR_MASK));
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: adc_proc_trig
|
|
*
|
|
* Description:
|
|
* Triggers the sample sequence to start it's conversion(s) and store them
|
|
* to the FIFO. This is only required when the trigger source is set to the
|
|
* processor.
|
|
*
|
|
* Input parameters:
|
|
* adc - which ADC peripherals' sample sequencers to trigger
|
|
* sse_mask - sample sequencer bitmask, each sse is 1 shifted by the sse
|
|
* number. e.g.
|
|
* SSE0 = 1 << 0
|
|
* SSE1 = 1 << 1
|
|
* SSE2 = 1 << 2
|
|
* SSE3 = 1 << 3
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void adc_proc_trig(struct tiva_adc_s *adc, uint8_t sse_mask)
|
|
{
|
|
uintptr_t pssireg = TIVA_ADC_PSSI(adc->devno);
|
|
tiva_adc_modifyreg(adc, pssireg, 0, sse_mask);
|
|
# ifdef CONFIG_TIVA_ADC_SYNC
|
|
# warning CONFIG_TIVA_ADC_SYNC unsupported at this time.
|
|
# endif
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: adc_int_status
|
|
*
|
|
* Description:
|
|
* Returns raw interrupt status for the input ADC
|
|
*
|
|
* Input parameters:
|
|
* adc - which ADC peripherals' interrupt status to retrieve
|
|
*
|
|
****************************************************************************/
|
|
|
|
static uint32_t adc_int_status(struct tiva_adc_s *adc)
|
|
{
|
|
return tiva_adc_getreg(adc, TIVA_ADC_RIS(adc->devno));
|
|
}
|
|
|
|
/* Sample sequencer (SSE) functions *****************************************/
|
|
|
|
/****************************************************************************
|
|
* Name: sse_state
|
|
*
|
|
* Description:
|
|
* Sets the operation state of an ADC's sample sequencer (SSE). SSEs must
|
|
* be configured before being enabled.
|
|
*
|
|
* Input parameters:
|
|
* adc - peripheral state
|
|
* sse - sample sequencer
|
|
* state - sample sequencer enable/disable state
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void sse_state(struct tiva_adc_s *adc, uint8_t sse, bool state)
|
|
{
|
|
uintptr_t actssreg = TIVA_ADC_ACTSS(adc->devno);
|
|
if (state == TIVA_ADC_ENABLE)
|
|
{
|
|
tiva_adc_modifyreg(adc, actssreg, 0, (1 << sse));
|
|
}
|
|
else
|
|
{
|
|
tiva_adc_modifyreg(adc, actssreg, (1 << sse), 0);
|
|
}
|
|
|
|
adc->sse[sse]->ena = state;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: sse_trigger
|
|
*
|
|
* Description:
|
|
* Sets the trigger configuration for an ADC's sample sequencer (SSE).
|
|
* Possible triggers are the following:
|
|
* - Processor
|
|
* - PWMs, requires that one of the PWMnn_TRIG_CFG defines be OR'd
|
|
* into the trigger value.
|
|
* - Timers
|
|
* - GPIO (which GPIO is platform specific, consult the datasheet)
|
|
* - Always
|
|
* - !!UNSUPPORTED: Comparators
|
|
*
|
|
* Input parameters:
|
|
* adc - peripheral state
|
|
* sse - sample sequencer
|
|
* trigger - interrupt trigger
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void sse_trigger(struct tiva_adc_s *adc, uint8_t sse, uint32_t trigger)
|
|
{
|
|
uintptr_t emuxreg = (TIVA_ADC_EMUX(adc->devno));
|
|
uint32_t trig = 0;
|
|
if ((trigger & ADC_EMUX_MASK(0)) == 0)
|
|
{
|
|
/* The 0 value is a special case since using modifyregn() results in an
|
|
* ORing of the register value; we need to unset those bits if it's a 0.
|
|
*/
|
|
|
|
tiva_adc_modifyreg(adc, emuxreg, (0xF << sse), 0);
|
|
}
|
|
else
|
|
{
|
|
trig = ((trigger << ADC_EMUX_SHIFT(sse)) & ADC_EMUX_MASK(sse));
|
|
tiva_adc_modifyreg(adc, emuxreg, 0, trig);
|
|
}
|
|
|
|
/* NOTE: PWM triggering needs an additional register to be set (ADC_TSSEL)
|
|
* A platform specific IOCTL command is provided to configure the triggering.
|
|
*/
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: sse_pwm_trig_ioctl
|
|
*
|
|
* Description:
|
|
* Additional triggering configuration for PWM. Sets which PWM and which
|
|
* generator.
|
|
*
|
|
* Input parameters:
|
|
* adc - peripheral state
|
|
* sse - sample sequencer
|
|
* cfg - PWM and generator encoding
|
|
*
|
|
****************************************************************************/
|
|
|
|
# ifdef CONFIG_EXPERIMENTAL
|
|
static void sse_pwm_trig_ioctl(struct tiva_adc_s *adc, uint8_t sse,
|
|
uint32_t cfg)
|
|
{
|
|
if ((ADC_TRIG_PWM_MASK & cfg) > 0)
|
|
{
|
|
|
|
/* PWM triggering needs an additional register to be set (ADC_TSSEL) */
|
|
|
|
uintptr_t tsselreg = TIVA_ADC_TSSEL(adc->devno);
|
|
uint32_t pwmcfg = ADC_TRIG_PWM_CFG(cfg);
|
|
if ((cfg & ADC_EMUX_MASK(0)) == 1)
|
|
{
|
|
tiva_adc_modifyreg(adc, tsselreg, 0, pwmcfg);
|
|
}
|
|
else
|
|
{
|
|
tiva_adc_modifyreg(adc, tsselreg, pwmcfg, 0);
|
|
}
|
|
}
|
|
}
|
|
# endif
|
|
|
|
/****************************************************************************
|
|
* Name: sse_int
|
|
*
|
|
* Description:
|
|
* Sets the interrupt state of an ADC's sample sequencer (SSE). SSEs must
|
|
* be enabled before setting interrupt state.
|
|
*
|
|
* Input parameters:
|
|
* adc - peripheral state
|
|
* sse - sample sequencer
|
|
* state - sample sequencer enable/disable interrupt state
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void sse_int_state(struct tiva_adc_s *adc, uint8_t sse, bool state)
|
|
{
|
|
uintptr_t imreg = TIVA_ADC_IM(adc->devno);
|
|
if (adc->sse[sse])
|
|
{
|
|
sse_clear_int(adc, sse);
|
|
}
|
|
if (state == TIVA_ADC_ENABLE)
|
|
{
|
|
tiva_adc_modifyreg(adc, imreg, 0, (1 << sse));
|
|
}
|
|
else
|
|
{
|
|
tiva_adc_modifyreg(adc, imreg, (1 << sse), 0);
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: sse_int_status
|
|
*
|
|
* Description:
|
|
* Returns interrupt status for the specificed SSE
|
|
*
|
|
* Input parameters:
|
|
* adc - which ADC peripherals' interrupt status to retrieve
|
|
* sse - which SSE interrupt status to retrieve
|
|
*
|
|
****************************************************************************/
|
|
|
|
static bool sse_int_status(struct tiva_adc_s *adc, uint8_t sse)
|
|
{
|
|
return (adc_int_status(adc) & (1 << sse)) > 0 ? true : false;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: sse_clear_int
|
|
*
|
|
* Description:
|
|
* Clears the interrupt bit for the SSE.
|
|
*
|
|
* Input parameters:
|
|
* adc - peripheral state
|
|
* sse - sample sequencer
|
|
* state - sample sequencer
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void sse_clear_int(struct tiva_adc_s *adc, uint8_t sse)
|
|
{
|
|
uintptr_t iscreg = TIVA_ADC_ISC(adc->devno);
|
|
tiva_adc_modifyreg(adc, iscreg, 0, (1 << sse));
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: sse_data
|
|
*
|
|
* Description:
|
|
* Retrieves data from the FIFOs for all steps in the given sample sequencer.
|
|
* The input data buffer MUST be as large or larger than the sample sequencer.
|
|
* otherwise
|
|
*
|
|
* Input parameters:
|
|
* adc - peripheral state
|
|
* sse - sample sequencer
|
|
*
|
|
* Return value:
|
|
* number of steps read from FIFO.
|
|
*
|
|
****************************************************************************/
|
|
|
|
static int sse_data(struct tiva_adc_s *adc, uint8_t sse)
|
|
{
|
|
uint32_t ssfstatreg =
|
|
tiva_adc_getreg(adc, TIVA_ADC_BASE(adc->devno) + TIVA_ADC_SSFSTAT(sse));
|
|
int32_t data = 0;
|
|
uint8_t fifo_count = 0;
|
|
|
|
/* Read samples from the FIFO until it is empty */
|
|
|
|
while (!(ssfstatreg & ADC_SSFSTAT_EMPTY) && fifo_count < SSE_MAX_STEP)
|
|
{
|
|
/* Read the FIFO and copy it to the destination */
|
|
|
|
data =
|
|
tiva_adc_getreg(adc, TIVA_ADC_BASE(adc->devno) + TIVA_ADC_SSFIFO(sse));
|
|
(void)adc_receive(adc->dev, GET_AIN(adc->devno, sse, fifo_count), data);
|
|
fifo_count++;
|
|
|
|
/* refresh fifo status register state */
|
|
|
|
ssfstatreg =
|
|
tiva_adc_getreg(adc, TIVA_ADC_BASE(adc->devno) + TIVA_ADC_SSFSTAT(sse));
|
|
}
|
|
|
|
return fifo_count;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: sse_priority
|
|
*
|
|
* Description:
|
|
* Sets the priority configuration for an ADC's sample sequencer (SSE). The
|
|
* priority value ranges from 0 to 3, 0 being the highest priority, 3 being
|
|
* the lowest. There can be no duplicate values.
|
|
*
|
|
* Input parameters:
|
|
* adc - peripheral state
|
|
* sse - sample sequencer
|
|
* priority - conversion priority
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void sse_priority(struct tiva_adc_s *adc, uint8_t sse, uint8_t priority)
|
|
{
|
|
uintptr_t ssprireg = TIVA_ADC_SSPRI(adc->devno);
|
|
uint32_t sspri = 0;
|
|
if (priority == 0)
|
|
{
|
|
/* The 0 value is a special case since using modifyregn() results in an
|
|
* ORing of the register value; we need to unset those bits if it's a 0.
|
|
*/
|
|
|
|
sspri = (ADC_SSPRI_MASK(sse) & (0x3 << ADC_SSPRI_SHIFT(sse)));
|
|
tiva_adc_modifyreg(adc, ssprireg, sspri, 0);
|
|
}
|
|
else
|
|
{
|
|
sspri = (ADC_SSPRI_MASK(sse) & (priority << ADC_SSPRI_SHIFT(sse)));
|
|
tiva_adc_modifyreg(adc, ssprireg, 0, sspri);
|
|
}
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: sse_register_chn
|
|
*
|
|
* Description:
|
|
* Registers an input channel to an SSE. Channels are registered according
|
|
* to the step and channel values stored in the channel struct. If the SSE
|
|
* already has a channel registered, it is overwritten by the new channel.
|
|
*
|
|
* *SSEMUX only supported on TM4C129 devices
|
|
*
|
|
* Input parameters:
|
|
* adc - peripheral state
|
|
* sse - sample sequencer
|
|
* chn - sample sequencer step
|
|
* ain - analog input pin
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void sse_register_chn(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
|
|
uint32_t ain)
|
|
{
|
|
/* Configure SSE mux (SSMUX) with step number */
|
|
|
|
uintptr_t ssmuxreg = (TIVA_ADC_BASE(adc->devno) + TIVA_ADC_SSMUX(sse));
|
|
uint32_t step = 0;
|
|
if (ain > 0)
|
|
{
|
|
step = ((ain << ADC_SSMUX_MUX_SHIFT(chn)) & ADC_SSMUX_MUX_MASK(chn));
|
|
tiva_adc_modifyreg(adc, ssmuxreg, 0, step);
|
|
}
|
|
else
|
|
{
|
|
step = ((0xF << ADC_SSMUX_MUX_SHIFT(chn)) & ADC_SSMUX_MUX_MASK(chn));
|
|
tiva_adc_modifyreg(adc, ssmuxreg, step, 0);
|
|
}
|
|
|
|
# ifdef CONFIG_ARCH_CHIP_TM4C129
|
|
/* Configure SSE extended mux (SSEMUX) with step number and configuration */
|
|
|
|
ssmuxreg = (TIVA_ADC_BASE(adc->devno) + TIVA_ADC_SSMUX(sse));
|
|
step = ((1 << ADC_SSEMUX_MUX_SHIFT(chn)) & ADC_SSEMUX_MUX_MASK(chn));
|
|
if (chn > MAX_NORMAL_CHN)
|
|
{
|
|
tiva_adc_modifyreg(adc, ssmuxreg, 0, step);
|
|
}
|
|
else
|
|
{
|
|
tiva_adc_modifyreg(adc, ssmuxreg, step, 0);
|
|
}
|
|
# endif
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: sse_differential
|
|
*
|
|
* Description:
|
|
* Sets the differential capability for a SSE. !! UNSUPPORTED
|
|
*
|
|
* Input parameters:
|
|
* adc - peripheral state
|
|
* sse - sample sequencer
|
|
* chn - sample sequencer channel
|
|
* diff - differential configuration
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void sse_differential(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
|
|
uint32_t diff)
|
|
{
|
|
# ifdef CONFIG_TIVA_ADC_DIFFERENTIAL
|
|
# error CONFIG_TIVA_ADC_DIFFERENTIAL unsupported!!
|
|
# else
|
|
|
|
/* for now, ensure the FIFO is used and differential sampling is disabled */
|
|
|
|
uintptr_t ssopreg = (TIVA_ADC_BASE(adc->devno) + TIVA_ADC_SSOP(sse));
|
|
uint32_t sdcopcfg = (1 << chn);
|
|
tiva_adc_modifyreg(adc, ssopreg, sdcopcfg, 0);
|
|
# endif
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: sse_sample_hold_time
|
|
*
|
|
* Description:
|
|
* Set the sample and hold time for this step.
|
|
*
|
|
* This is not available on all devices, however on devices that do not
|
|
* support this feature these reserved bits are ignored on write access.
|
|
*
|
|
* Input parameters:
|
|
* adc - peripheral state
|
|
* sse - sample sequencer
|
|
* chn - sample sequencer channel
|
|
* shold - sample and hold time
|
|
*
|
|
****************************************************************************/
|
|
|
|
# ifdef CONFIG_EXPERIMENTAL
|
|
static void sse_sample_hold_time(struct tiva_adc_s *adc, uint8_t sse,
|
|
uint8_t chn, uint32_t shold)
|
|
{
|
|
uintptr_t sstshreg = (TIVA_ADC_BASE(adc->devno) + TIVA_ADC_SSTSH(sse));
|
|
if (shold > 0)
|
|
{
|
|
tiva_adc_modifyreg(adc, sstshreg, 0, (shold << ADC_SSTSH_SHIFT(sse)));
|
|
}
|
|
else
|
|
{
|
|
tiva_adc_modifyreg(adc, sstshreg, ADC_SSTSH_MASK(sse), 0);
|
|
}
|
|
}
|
|
# endif
|
|
|
|
/****************************************************************************
|
|
* Name: sse_step_cfg
|
|
*
|
|
* Description:
|
|
* Configures the given SSE step to one of the following options:
|
|
* -Temperature sensor select: this step is muxed to the internal
|
|
* temperature sensor.
|
|
* -Interrupt enabled select: this step causes the interrupt bit to
|
|
* be set and, if the MASK0 bit in ADC_IM register is set, the
|
|
* interrupt is promoted to the interrupt controller.
|
|
* -Sequence end select: This step is the last sequence to be sampled.
|
|
* This MUST be set somewhere in the SSE.
|
|
* -*Comparator/Differential select: The analog input is differentially
|
|
* sampled. The corresponding ADCSSMUXn nibble must be set to the pair
|
|
* number "i", where the paired inputs are "2i and 2i+1". Because the
|
|
* temperature sensor does not have a differential option, this bit must
|
|
* not be set when the TS3 bit is set.
|
|
*
|
|
* *Comparator/Differental functionality is unsupported and ignored.
|
|
*
|
|
* Input parameters:
|
|
* adc - peripheral state
|
|
* sse - sample sequencer
|
|
* chn - sample sequencer channel
|
|
* cfg - step configuration
|
|
*
|
|
****************************************************************************/
|
|
|
|
static void sse_step_cfg(struct tiva_adc_s *adc, uint8_t sse, uint8_t chn,
|
|
uint8_t cfg)
|
|
{
|
|
uintptr_t ssctlreg = (TIVA_ADC_BASE(adc->devno) + TIVA_ADC_SSCTL(sse));
|
|
uint32_t ctlcfg = cfg << ADC_SSCTL_SHIFT(chn);
|
|
tiva_adc_modifyreg(adc, ssctlreg, 0, ctlcfg);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Public Functions
|
|
****************************************************************************/
|
|
|
|
/****************************************************************************
|
|
* Name: tiva_adc_initialize
|
|
*
|
|
* Description:
|
|
* Initialize the ADC
|
|
*
|
|
* Returned Value:
|
|
* Valid can device structure reference on succcess; a NULL on failure
|
|
*
|
|
****************************************************************************/
|
|
|
|
struct adc_dev_s *tiva_adc_initialize(int adc_num)
|
|
{
|
|
adcvdbg("tiva_adc_initialize\n");
|
|
|
|
/* Initialize the private ADC device data structure */
|
|
|
|
struct tiva_adc_s *adc;
|
|
uint8_t s;
|
|
# ifdef CONFIG_TIVA_ADC0
|
|
if (adc_num == 0)
|
|
{
|
|
adc0.ena = false;
|
|
adc0.devno = 0;
|
|
|
|
/* Debug stuff */
|
|
|
|
# ifdef CONFIG_TIVA_ADC_REGDEBUG
|
|
adc0.wrlast = false;
|
|
adc0.addrlast = 0x0;
|
|
adc0.vallast = 0x0;
|
|
adc0.ntimes = 0;
|
|
# endif /* CONFIG_TIVA_ADC_REGDEBUG */
|
|
|
|
/* Initialize SSEs */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0
|
|
sse00.ena = false;
|
|
sse00.irq = TIVA_IRQ_ADC0;
|
|
sse00.num = 0;
|
|
sem_init(&sse00.exclsem, SEM_PROCESS_PRIVATE, 1);
|
|
adc0.sse[0] = &sse00;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE0 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE1
|
|
sse01.ena = false;
|
|
sse01.irq = TIVA_IRQ_ADC0;
|
|
sse01.num = 1;
|
|
sem_init(&sse01.exclsem, SEM_PROCESS_PRIVATE, 1);
|
|
adc0.sse[1] = &sse01;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE1 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE2
|
|
sse02.ena = false;
|
|
sse02.irq = TIVA_IRQ_ADC0;
|
|
sse02.num = 2;
|
|
sem_init(&sse02.exclsem, SEM_PROCESS_PRIVATE, 1);
|
|
adc0.sse[2] = &sse02;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE2 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE3
|
|
sse03.ena = false;
|
|
sse03.irq = TIVA_IRQ_ADC0;
|
|
sse03.num = 3;
|
|
sem_init(&sse03.exclsem, SEM_PROCESS_PRIVATE, 1);
|
|
adc0.sse[3] = &sse03;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE3 */
|
|
|
|
adc0.dev = &g_adcdev0;
|
|
adc = &adc0;
|
|
|
|
/* Initialize the public ADC device data structure */
|
|
|
|
g_adcdev0.ad_ops = &g_adcops;
|
|
g_adcdev0.ad_priv = &adc0;
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC0 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1
|
|
if (adc_num == 1)
|
|
{
|
|
adc1.ena = false;
|
|
adc1.devno = 0;
|
|
|
|
/* Debug stuff */
|
|
|
|
# ifdef CONFIG_TIVA_ADC_REGDEBUG
|
|
adc1.wrlast = false;
|
|
adc1.addrlast = 0x0;
|
|
adc1.vallast = 0x0;
|
|
adc1.ntimes = 0;
|
|
# endif /* CONFIG_TIVA_ADC_REGDEBUG */
|
|
|
|
/* Initialize SSEs */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0
|
|
sse10.ena = false;
|
|
sse10.irq = TIVA_IRQ_ADC0;
|
|
sse10.num = 0;
|
|
sem_init(&sse10.exclsem, SEM_PROCESS_PRIVATE, 1);
|
|
adc1.sse[0] = &sse10;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE0 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE1
|
|
sse11.ena = false;
|
|
sse11.irq = TIVA_IRQ_ADC0;
|
|
sse11.num = 1;
|
|
sem_init(&sse11.exclsem, SEM_PROCESS_PRIVATE, 1);
|
|
adc1.sse[1] = &sse11;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE1 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE2
|
|
sse12.ena = false;
|
|
sse12.irq = TIVA_IRQ_ADC0;
|
|
sse12.num = 2;
|
|
sem_init(&sse12.exclsem, SEM_PROCESS_PRIVATE, 1);
|
|
adc1.sse[2] = &sse12;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE2 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE3
|
|
sse13.ena = false;
|
|
sse13.irq = TIVA_IRQ_ADC0;
|
|
sse13.num = 3;
|
|
sem_init(&sse13.exclsem, SEM_PROCESS_PRIVATE, 1);
|
|
adc1.sse[3] = &sse13;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE3 */
|
|
|
|
adc1.dev = &g_adcdev1;
|
|
adc = &adc1;
|
|
|
|
/* Initialize the public ADC device data structure */
|
|
|
|
g_adcdev1.ad_ops = &g_adcops;
|
|
g_adcdev1.ad_priv = &adc1;
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC1 */
|
|
|
|
if (adc_num > 1)
|
|
{
|
|
adcvdbg("ERROR: Invalid ADV devno given, must be 0 or 1! ADC Devno: %d\n",
|
|
adc_num);
|
|
return NULL;
|
|
}
|
|
|
|
/* Have the common peripheral properties already been initialized? If yes,
|
|
* continue.
|
|
*/
|
|
|
|
if (adc_common.init[adc->devno] == false)
|
|
{
|
|
/* turn on peripheral */
|
|
|
|
if (adc_state(adc, TIVA_ADC_ENABLE) < 0)
|
|
{
|
|
adcvdbg("ERROR: failure to power ADC peripheral (devno=%d)\n",
|
|
adc_num);
|
|
return NULL;
|
|
}
|
|
|
|
/* set clock */
|
|
|
|
adc_clock(CONFIG_TIVA_ADC_CLOCK);
|
|
|
|
/* set sampling rate */
|
|
|
|
adc_sample_rate(TIVA_ADC_SAMPLE_RATE_FASTEST);
|
|
|
|
# ifdef CONFIG_ARCH_CHIP_TM4C129
|
|
/* voltage reference */
|
|
|
|
adc_vref();
|
|
# endif /* CONFIG_ARCH_CHIP_TM4C129 */
|
|
adc_common.init[adc->devno] = true;
|
|
}
|
|
|
|
/* Initialize peripheral */
|
|
|
|
/* Have we already been initialized? If yes, than just hand out the interface
|
|
* one more time.
|
|
*/
|
|
|
|
if (adc->ena == false)
|
|
{
|
|
# if CONFIG_TIVA_ADC0
|
|
if (adc_num == 0)
|
|
{
|
|
/* Configure sample sequencers */
|
|
|
|
tiva_adc0_sse_init();
|
|
|
|
/* Configure channels & register interrupts */
|
|
|
|
tiva_adc0_assign_interrupts();
|
|
tiva_adc0_assign_channels();
|
|
}
|
|
# endif
|
|
|
|
# if CONFIG_TIVA_ADC1
|
|
if (adc_num == 1)
|
|
{
|
|
/* Configure sample sequencers */
|
|
|
|
tiva_adc1_sse_init();
|
|
|
|
/* Configure channels & register interrupts */
|
|
|
|
tiva_adc1_assign_interrupts();
|
|
tiva_adc1_assign_channels();
|
|
}
|
|
# endif
|
|
|
|
/* Enable SSEs */
|
|
|
|
for (s = 0; s < SSE_PER_BASE; ++s)
|
|
{
|
|
if (adc_common.sse[SSE_IDX(adc_num, s)])
|
|
{
|
|
sse_state(adc, s, TIVA_ADC_ENABLE);
|
|
sse_clear_int(adc, s);
|
|
}
|
|
}
|
|
|
|
/* Now we are initialized */
|
|
|
|
adc->ena = true;
|
|
}
|
|
|
|
/* Return a pointer to the device structure */
|
|
|
|
adcvdbg("Returning %x\n", adc->dev);
|
|
return adc->dev;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: tiva_adc_lock
|
|
*
|
|
* Description:
|
|
* Get exclusive access to the ADC interface
|
|
*
|
|
****************************************************************************/
|
|
|
|
void tiva_adc_lock(FAR struct tiva_adc_s *priv, int sse)
|
|
{
|
|
int ret;
|
|
adcvdbg("Locking\n");
|
|
do
|
|
{
|
|
ret = sem_wait(&priv->sse[sse]->exclsem);
|
|
|
|
/* This should only fail if the wait was canceled by an signal (and the
|
|
* worker thread will receive a lot of signals).
|
|
*/
|
|
|
|
DEBUGASSERT(ret == OK || errno == EINTR);
|
|
}
|
|
while (ret < 0);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: tiva_adc_unlock
|
|
*
|
|
* Description:
|
|
* Relinquish the lock on the ADC interface
|
|
*
|
|
****************************************************************************/
|
|
|
|
void tiva_adc_unlock(FAR struct tiva_adc_s *priv, int sse)
|
|
{
|
|
adcvdbg("Unlocking\n");
|
|
sem_post(&priv->sse[sse]->exclsem);
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: tiva_adc_getreg
|
|
*
|
|
* Description:
|
|
* Read any 32-bit register using an absolute address.
|
|
*
|
|
****************************************************************************/
|
|
|
|
# ifdef CONFIG_TIVA_ADC_REGDEBUG
|
|
uint32_t tiva_adc_getreg(struct tiva_adc_s *priv, uintptr_t address)
|
|
{
|
|
uint32_t regval = getreg32(address);
|
|
|
|
if (tiva_adc_checkreg(priv, false, regval, address))
|
|
{
|
|
lldbg("%08x->%08x\n", address, regval);
|
|
}
|
|
|
|
return regval;
|
|
}
|
|
|
|
/****************************************************************************
|
|
* Name: tiva_adc_putreg
|
|
*
|
|
* Description:
|
|
* Write to any 32-bit register using an absolute address.
|
|
*
|
|
****************************************************************************/
|
|
|
|
void tiva_adc_putreg(struct tiva_adc_s *priv, uintptr_t address,
|
|
uint32_t regval)
|
|
{
|
|
if (tiva_adc_checkreg(priv, true, regval, address))
|
|
{
|
|
lldbg("%08x<-%08x\n", address, regval);
|
|
}
|
|
|
|
putreg32(regval, address);
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC_REGDEBUG */
|
|
|
|
/****************************************************************************
|
|
* Name: Verbose, generated code
|
|
*
|
|
* Description:
|
|
* Generated with a python script, the following code is used to deal with
|
|
* the defines generated from the Kconfig menu. Read at your own risk.
|
|
*
|
|
****************************************************************************/
|
|
|
|
/* Sample sequencer initialization ******************************************/
|
|
|
|
# ifdef CONFIG_TIVA_ADC0
|
|
static void tiva_adc0_sse_init(void)
|
|
{
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0
|
|
sse_state(&adc0, 0, TIVA_ADC_DISABLE);
|
|
sse_priority(&adc0, 0, CONFIG_TIVA_ADC0_SSE0_PRIORITY);
|
|
sse_trigger(&adc0, 0, CONFIG_TIVA_ADC0_SSE0_TRIGGER);
|
|
adc_common.sse[SSE_IDX(0, 0)] = true;
|
|
# endif
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE1
|
|
sse_state(&adc0, 1, TIVA_ADC_DISABLE);
|
|
sse_priority(&adc0, 1, CONFIG_TIVA_ADC0_SSE1_PRIORITY);
|
|
sse_trigger(&adc0, 1, CONFIG_TIVA_ADC0_SSE1_TRIGGER);
|
|
adc_common.sse[SSE_IDX(0, 1)] = true;
|
|
# endif
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE2
|
|
sse_state(&adc0, 2, TIVA_ADC_DISABLE);
|
|
sse_priority(&adc0, 2, CONFIG_TIVA_ADC0_SSE2_PRIORITY);
|
|
sse_trigger(&adc0, 2, CONFIG_TIVA_ADC0_SSE2_TRIGGER);
|
|
adc_common.sse[SSE_IDX(0, 2)] = true;
|
|
# endif
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE3
|
|
sse_state(&adc0, 3, TIVA_ADC_DISABLE);
|
|
sse_priority(&adc0, 3, CONFIG_TIVA_ADC0_SSE3_PRIORITY);
|
|
sse_trigger(&adc0, 3, CONFIG_TIVA_ADC0_SSE3_TRIGGER);
|
|
adc_common.sse[SSE_IDX(0, 3)] = true;
|
|
# endif
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC0 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1
|
|
static void tiva_adc1_sse_init(void)
|
|
{
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0
|
|
sse_state(&adc1, 0, TIVA_ADC_DISABLE);
|
|
sse_priority(&adc1, 0, CONFIG_TIVA_ADC1_SSE0_PRIORITY);
|
|
sse_trigger(&adc1, 0, CONFIG_TIVA_ADC1_SSE0_TRIGGER);
|
|
adc_common.sse[SSE_IDX(1, 0)] = true;
|
|
# endif
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE1
|
|
sse_state(&adc1, 1, TIVA_ADC_DISABLE);
|
|
sse_priority(&adc1, 1, CONFIG_TIVA_ADC1_SSE1_PRIORITY);
|
|
sse_trigger(&adc1, 1, CONFIG_TIVA_ADC1_SSE1_TRIGGER);
|
|
adc_common.sse[SSE_IDX(1, 1)] = true;
|
|
# endif
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE2
|
|
sse_state(&adc1, 2, TIVA_ADC_DISABLE);
|
|
sse_priority(&adc1, 2, CONFIG_TIVA_ADC1_SSE2_PRIORITY);
|
|
sse_trigger(&adc1, 2, CONFIG_TIVA_ADC1_SSE2_TRIGGER);
|
|
adc_common.sse[SSE_IDX(1, 2)] = true;
|
|
# endif
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE3
|
|
sse_state(&adc1, 3, TIVA_ADC_DISABLE);
|
|
sse_priority(&adc1, 3, CONFIG_TIVA_ADC1_SSE3_PRIORITY);
|
|
sse_trigger(&adc1, 3, CONFIG_TIVA_ADC1_SSE3_TRIGGER);
|
|
adc_common.sse[SSE_IDX(1, 3)] = true;
|
|
# endif
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC1 */
|
|
|
|
/* Sample sequencer interrupt initialization ********************************/
|
|
|
|
# ifdef CONFIG_TIVA_ADC0
|
|
static void tiva_adc0_assign_interrupts(void)
|
|
{
|
|
uint32_t ret = 0;
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0
|
|
ret = irq_attach(sse00.irq, (xcpt_t) adc0_sse0_interrupt);
|
|
if (ret < 0)
|
|
{
|
|
adbg("ERROR: Failed to attach IRQ %d: %d\n", sse00.irq, ret);
|
|
return;
|
|
}
|
|
|
|
up_enable_irq(sse00.irq);
|
|
# endif /* CONFIG_TIVA_ADC0_SSE0 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE1
|
|
ret = irq_attach(sse01.irq, (xcpt_t) adc0_sse1_interrupt);
|
|
if (ret < 0)
|
|
{
|
|
adbg("ERROR: Failed to attach IRQ %d: %d\n", sse01.irq, ret);
|
|
return;
|
|
}
|
|
|
|
up_enable_irq(sse01.irq);
|
|
# endif /* CONFIG_TIVA_ADC0_SSE1 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE2
|
|
ret = irq_attach(sse02.irq, (xcpt_t) adc0_sse2_interrupt);
|
|
if (ret < 0)
|
|
{
|
|
adbg("ERROR: Failed to attach IRQ %d: %d\n", sse02.irq, ret);
|
|
return;
|
|
}
|
|
|
|
up_enable_irq(sse02.irq);
|
|
# endif /* CONFIG_TIVA_ADC0_SSE2 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE3
|
|
ret = irq_attach(sse03.irq, (xcpt_t) adc0_sse3_interrupt);
|
|
if (ret < 0)
|
|
{
|
|
adbg("ERROR: Failed to attach IRQ %d: %d\n", sse03.irq, ret);
|
|
return;
|
|
}
|
|
|
|
up_enable_irq(sse03.irq);
|
|
# endif /* CONFIG_TIVA_ADC0_SSE3 */
|
|
};
|
|
# endif /* CONFIG_TIVA_ADC0 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1
|
|
static void tiva_adc1_assign_interrupts(void)
|
|
{
|
|
uint32_t ret = 0;
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0
|
|
ret = irq_attach(sse10.irq, (xcpt_t) adc1_sse0_interrupt);
|
|
if (ret < 0)
|
|
{
|
|
adbg("ERROR: Failed to attach IRQ %d: %d\n", sse10.irq, ret);
|
|
return;
|
|
}
|
|
|
|
up_enable_irq(sse10.irq);
|
|
# endif /* CONFIG_TIVA_ADC1_SSE0 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE1
|
|
ret = irq_attach(sse11.irq, (xcpt_t) adc1_sse1_interrupt);
|
|
if (ret < 0)
|
|
{
|
|
adbg("ERROR: Failed to attach IRQ %d: %d\n", sse11.irq, ret);
|
|
return;
|
|
}
|
|
|
|
up_enable_irq(sse11.irq);
|
|
# endif /* CONFIG_TIVA_ADC1_SSE1 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE2
|
|
ret = irq_attach(sse12.irq, (xcpt_t) adc1_sse2_interrupt);
|
|
if (ret < 0)
|
|
{
|
|
adbg("ERROR: Failed to attach IRQ %d: %d\n", sse12.irq, ret);
|
|
return;
|
|
}
|
|
|
|
up_enable_irq(sse12.irq);
|
|
# endif /* CONFIG_TIVA_ADC1_SSE2 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE3
|
|
ret = irq_attach(sse13.irq, (xcpt_t) adc1_sse3_interrupt);
|
|
if (ret < 0)
|
|
{
|
|
adbg("ERROR: Failed to attach IRQ %d: %d\n", sse13.irq, ret);
|
|
return;
|
|
}
|
|
|
|
up_enable_irq(sse13.irq);
|
|
# endif /* CONFIG_TIVA_ADC1_SSE3 */
|
|
};
|
|
# endif /* CONFIG_TIVA_ADC1 */
|
|
|
|
/* Sample sequencer interrupt declaration ********************************/
|
|
|
|
# ifdef CONFIG_TIVA_ADC0
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0
|
|
static void adc0_sse0_interrupt(int irq, void *context)
|
|
{
|
|
uint8_t fifo_count = 0;
|
|
sse_int_state(&adc0, 0, TIVA_ADC_DISABLE);
|
|
sse_clear_int(&adc0, 0);
|
|
tiva_adc_lock(&adc0, 0);
|
|
while (!(tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFSTAT(0)) &
|
|
ADC_SSFSTAT_EMPTY) && fifo_count++ < SSE_MAX_STEP)
|
|
{
|
|
uint32_t data =
|
|
tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFIFO(0));
|
|
(void)adc_receive(adc0.dev, GET_AIN(0, 0, fifo_count), data);
|
|
}
|
|
|
|
sse_int_state(&adc0, 0, TIVA_ADC_ENABLE);
|
|
tiva_adc_unlock(&adc0, 0);
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC0_SSE0 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE1
|
|
static void adc0_sse1_interrupt(int irq, void *context)
|
|
{
|
|
uint8_t fifo_count = 0;
|
|
sse_int_state(&adc0, 1, TIVA_ADC_DISABLE);
|
|
sse_clear_int(&adc0, 1);
|
|
tiva_adc_lock(&adc0, 1);
|
|
while (!(tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFSTAT(1)) &
|
|
ADC_SSFSTAT_EMPTY) && fifo_count++ < SSE_MAX_STEP)
|
|
{
|
|
uint32_t data =
|
|
tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFIFO(1));
|
|
(void)adc_receive(adc0.dev, GET_AIN(0, 1, fifo_count), data);
|
|
}
|
|
|
|
sse_int_state(&adc0, 1, TIVA_ADC_ENABLE);
|
|
tiva_adc_unlock(&adc0, 1);
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC0_SSE1 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE2
|
|
static void adc0_sse2_interrupt(int irq, void *context)
|
|
{
|
|
uint8_t fifo_count = 0;
|
|
sse_int_state(&adc0, 2, TIVA_ADC_DISABLE);
|
|
sse_clear_int(&adc0, 2);
|
|
tiva_adc_lock(&adc0, 2);
|
|
while (!(tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFSTAT(2)) &
|
|
ADC_SSFSTAT_EMPTY) && fifo_count++ < SSE_MAX_STEP)
|
|
{
|
|
uint32_t data =
|
|
tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFIFO(2));
|
|
(void)adc_receive(adc0.dev, GET_AIN(0, 2, fifo_count), data);
|
|
}
|
|
|
|
sse_int_state(&adc0, 2, TIVA_ADC_ENABLE);
|
|
tiva_adc_unlock(&adc0, 2);
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC0_SSE2 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE3
|
|
static void adc0_sse3_interrupt(int irq, void *context)
|
|
{
|
|
uint8_t fifo_count = 0;
|
|
sse_int_state(&adc0, 3, TIVA_ADC_DISABLE);
|
|
sse_clear_int(&adc0, 3);
|
|
tiva_adc_lock(&adc0, 3);
|
|
while (!(tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFSTAT(3)) &
|
|
ADC_SSFSTAT_EMPTY) && fifo_count++ < SSE_MAX_STEP)
|
|
{
|
|
uint32_t data =
|
|
tiva_adc_getreg(&adc0, TIVA_ADC_BASE(0) + TIVA_ADC_SSFIFO(3));
|
|
(void)adc_receive(adc0.dev, GET_AIN(0, 3, fifo_count), data);
|
|
}
|
|
|
|
sse_int_state(&adc0, 3, TIVA_ADC_ENABLE);
|
|
tiva_adc_unlock(&adc0, 3);
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC0_SSE3 */
|
|
# endif /* CONFIG_TIVA_ADC0 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0
|
|
static void adc1_sse0_interrupt(int irq, void *context)
|
|
{
|
|
uint8_t fifo_count = 0;
|
|
sse_int_state(&adc1, 0, TIVA_ADC_DISABLE);
|
|
sse_clear_int(&adc1, 0);
|
|
tiva_adc_lock(&adc1, 0);
|
|
while (!(tiva_adc_getreg(&adc1, TIVA_ADC_BASE(1) + TIVA_ADC_SSFSTAT(0)) &
|
|
ADC_SSFSTAT_EMPTY) && fifo_count++ < SSE_MAX_STEP)
|
|
{
|
|
uint32_t data =
|
|
tiva_adc_getreg(&adc1, TIVA_ADC_BASE(1) + TIVA_ADC_SSFIFO(0));
|
|
(void)adc_receive(adc1.dev, GET_AIN(1, 0, fifo_count), data);
|
|
}
|
|
|
|
sse_int_state(&adc1, 0, TIVA_ADC_ENABLE);
|
|
tiva_adc_unlock(&adc1, 0);
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC1_SSE0 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE1
|
|
static void adc1_sse1_interrupt(int irq, void *context)
|
|
{
|
|
uint8_t fifo_count = 0;
|
|
sse_int_state(&adc1, 1, TIVA_ADC_DISABLE);
|
|
sse_clear_int(&adc1, 1);
|
|
tiva_adc_lock(&adc1, 1);
|
|
while (!(tiva_adc_getreg(&adc1, TIVA_ADC_BASE(1) + TIVA_ADC_SSFSTAT(1)) &
|
|
ADC_SSFSTAT_EMPTY) && fifo_count++ < SSE_MAX_STEP)
|
|
{
|
|
uint32_t data =
|
|
tiva_adc_getreg(&adc1, TIVA_ADC_BASE(1) + TIVA_ADC_SSFIFO(1));
|
|
(void)adc_receive(adc1.dev, GET_AIN(1, 1, fifo_count), data);
|
|
}
|
|
|
|
sse_int_state(&adc1, 1, TIVA_ADC_ENABLE);
|
|
tiva_adc_unlock(&adc1, 1);
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC1_SSE1 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE2
|
|
static void adc1_sse2_interrupt(int irq, void *context)
|
|
{
|
|
uint8_t fifo_count = 0;
|
|
sse_int_state(&adc1, 2, TIVA_ADC_DISABLE);
|
|
sse_clear_int(&adc1, 2);
|
|
tiva_adc_lock(&adc1, 2);
|
|
while (!(tiva_adc_getreg(&adc1, TIVA_ADC_BASE(1) + TIVA_ADC_SSFSTAT(2)) &
|
|
ADC_SSFSTAT_EMPTY) && fifo_count++ < SSE_MAX_STEP)
|
|
{
|
|
uint32_t data =
|
|
tiva_adc_getreg(&adc1, TIVA_ADC_BASE(1) + TIVA_ADC_SSFIFO(2));
|
|
(void)adc_receive(adc1.dev, GET_AIN(1, 2, fifo_count), data);
|
|
}
|
|
|
|
sse_int_state(&adc1, 2, TIVA_ADC_ENABLE);
|
|
tiva_adc_unlock(&adc1, 2);
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC1_SSE2 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE3
|
|
static void adc1_sse3_interrupt(int irq, void *context)
|
|
{
|
|
uint8_t fifo_count = 0;
|
|
sse_int_state(&adc1, 3, TIVA_ADC_DISABLE);
|
|
sse_clear_int(&adc1, 3);
|
|
tiva_adc_lock(&adc1, 3);
|
|
while (!(tiva_adc_getreg(&adc1, TIVA_ADC_BASE(1) + TIVA_ADC_SSFSTAT(3)) &
|
|
ADC_SSFSTAT_EMPTY) && fifo_count++ < SSE_MAX_STEP)
|
|
{
|
|
uint32_t data =
|
|
tiva_adc_getreg(&adc1, TIVA_ADC_BASE(1) + TIVA_ADC_SSFIFO(3));
|
|
(void)adc_receive(adc1.dev, GET_AIN(1, 3, fifo_count), data);
|
|
}
|
|
|
|
sse_int_state(&adc1, 3, TIVA_ADC_ENABLE);
|
|
tiva_adc_unlock(&adc1, 3);
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC1_SSE3 */
|
|
# endif /* CONFIG_TIVA_ADC1 */
|
|
|
|
/* Channel assignment *******************************************************/
|
|
|
|
# ifdef CONFIG_TIVA_ADC0
|
|
static void tiva_adc0_assign_channels(void)
|
|
{
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0
|
|
adc0_sse0_chn_cfg();
|
|
# endif
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE1
|
|
adc0_sse1_chn_cfg();
|
|
# endif
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE2
|
|
adc0_sse2_chn_cfg();
|
|
# endif
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE3
|
|
adc0_sse3_chn_cfg();
|
|
# endif
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC0 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1
|
|
static void tiva_adc1_assign_channels(void)
|
|
{
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0
|
|
adc1_sse0_chn_cfg();
|
|
# endif
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE1
|
|
adc1_sse1_chn_cfg();
|
|
# endif
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE2
|
|
adc1_sse2_chn_cfg();
|
|
# endif
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE3
|
|
adc1_sse3_chn_cfg();
|
|
# endif
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC1 */
|
|
|
|
/* Channel config ***********************************************************/
|
|
|
|
# ifdef CONFIG_TIVA_ADC0
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0
|
|
static void adc0_sse0_chn_cfg(void)
|
|
{
|
|
uint32_t chncfg = 0;
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0_STEP0
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0_STEP0_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE0_STEP0_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP0_AIN));
|
|
sse_register_chn(&adc0, 0, 0, CONFIG_TIVA_ADC0_SSE0_STEP0_AIN);
|
|
sse_differential(&adc0, 0, 0, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc0, 0, 0, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC0_SSE0_STEP1
|
|
sse_step_cfg(&adc0, 0, 0, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC0_SSE0_STEP1 */
|
|
sse_step_cfg(&adc0, 0, 0, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC0_SSE0_STEP1 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0_STEP1
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0_STEP1_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE0_STEP1_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP1_AIN));
|
|
sse_register_chn(&adc0, 0, 1, CONFIG_TIVA_ADC0_SSE0_STEP1_AIN);
|
|
sse_differential(&adc0, 0, 1, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc0, 0, 1, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC0_SSE0_STEP2
|
|
sse_step_cfg(&adc0, 0, 1, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC0_SSE0_STEP2 */
|
|
sse_step_cfg(&adc0, 0, 1, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC0_SSE0_STEP2 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0_STEP2
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0_STEP2_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE0_STEP2_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP2_AIN));
|
|
sse_register_chn(&adc0, 0, 2, CONFIG_TIVA_ADC0_SSE0_STEP2_AIN);
|
|
sse_differential(&adc0, 0, 2, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc0, 0, 2, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC0_SSE0_STEP3
|
|
sse_step_cfg(&adc0, 0, 2, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC0_SSE0_STEP3 */
|
|
sse_step_cfg(&adc0, 0, 2, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC0_SSE0_STEP3 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0_STEP3
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0_STEP3_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE0_STEP3_TS */
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP3_AIN));
|
|
sse_register_chn(&adc0, 0, 3, CONFIG_TIVA_ADC0_SSE0_STEP3_AIN);
|
|
sse_differential(&adc0, 0, 3, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc0, 0, 3, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC0_SSE0_STEP4
|
|
sse_step_cfg(&adc0, 0, 3, chncfg | ADC_SSCTL_END);
|
|
# else /* CONFIG_TIVA_ADC0_SSE0_STEP4 */
|
|
sse_step_cfg(&adc0, 0, 3, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC0_SSE0_STEP4 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0_STEP4
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0_STEP4_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE0_STEP4_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP4_AIN));
|
|
sse_register_chn(&adc0, 0, 4, CONFIG_TIVA_ADC0_SSE0_STEP4_AIN);
|
|
sse_differential(&adc0, 0, 4, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc0, 0, 4, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC0_SSE0_STEP5
|
|
sse_step_cfg(&adc0, 0, 4, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC0_SSE0_STEP5 */
|
|
sse_step_cfg(&adc0, 0, 4, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC0_SSE0_STEP5 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0_STEP5
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0_STEP5_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE0_STEP5_TS */
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP5_AIN));
|
|
sse_register_chn(&adc0, 0, 5, CONFIG_TIVA_ADC0_SSE0_STEP5_AIN);
|
|
sse_differential(&adc0, 0, 5, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc0, 0, 5, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC0_SSE0_STEP6
|
|
sse_step_cfg(&adc0, 0, 5, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC0_SSE0_STEP6 */
|
|
sse_step_cfg(&adc0, 0, 5, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC0_SSE0_STEP6 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0_STEP6
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0_STEP6_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE0_STEP6_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP6_AIN));
|
|
sse_register_chn(&adc0, 0, 6, CONFIG_TIVA_ADC0_SSE0_STEP6_AIN);
|
|
sse_differential(&adc0, 0, 6, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc0, 0, 6, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC0_SSE0_STEP7
|
|
sse_step_cfg(&adc0, 0, 6, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC0_SSE0_STEP7 */
|
|
sse_step_cfg(&adc0, 0, 6, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC0_SSE0_STEP7 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0_STEP7
|
|
# ifdef CONFIG_TIVA_ADC0_SSE0_STEP7_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE0_STEP7_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE0_STEP7_AIN));
|
|
sse_register_chn(&adc0, 0, 7, CONFIG_TIVA_ADC0_SSE0_STEP7_AIN);
|
|
sse_differential(&adc0, 0, 7, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE0_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc0, 0, 7, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC0_SSE0_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
sse_step_cfg(&adc0, 0, 7, chncfg | ADC_SSCTL_END);
|
|
|
|
# endif /* CONFIG_TIVA_ADC0_SSE0_STEP7 */
|
|
# endif /* CONFIG_TIVA_ADC0_SSE0_STEP6 */
|
|
# endif /* CONFIG_TIVA_ADC0_SSE0_STEP5 */
|
|
# endif /* CONFIG_TIVA_ADC0_SSE0_STEP4 */
|
|
# endif /* CONFIG_TIVA_ADC0_SSE0_STEP3 */
|
|
# endif /* CONFIG_TIVA_ADC0_SSE0_STEP2 */
|
|
# endif /* CONFIG_TIVA_ADC0_SSE0_STEP1 */
|
|
# endif /* CONFIG_TIVA_ADC0_SSE0_STEP0 */
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC0_SSE0 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE1
|
|
static void adc0_sse1_chn_cfg(void)
|
|
{
|
|
uint32_t chncfg = 0;
|
|
# ifdef CONFIG_TIVA_ADC0_SSE1_STEP0
|
|
# ifdef CONFIG_TIVA_ADC0_SSE1_STEP0_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE1_STEP0_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE1_STEP0_AIN));
|
|
sse_register_chn(&adc0, 1, 0, CONFIG_TIVA_ADC0_SSE1_STEP0_AIN);
|
|
sse_differential(&adc0, 1, 0, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE1_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc0, 1, 0, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC0_SSE1_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC0_SSE1_STEP1
|
|
sse_step_cfg(&adc0, 1, 0, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC0_SSE1_STEP1 */
|
|
sse_step_cfg(&adc0, 1, 0, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC0_SSE1_STEP1 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE1_STEP1
|
|
# ifdef CONFIG_TIVA_ADC0_SSE1_STEP1_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE1_STEP1_TS */
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE1_STEP1_AIN));
|
|
sse_register_chn(&adc0, 1, 1, CONFIG_TIVA_ADC0_SSE1_STEP1_AIN);
|
|
sse_differential(&adc0, 1, 1, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE1_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc0, 1, 1, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC0_SSE1_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC0_SSE1_STEP2
|
|
sse_step_cfg(&adc0, 1, 1, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC0_SSE1_STEP2 */
|
|
sse_step_cfg(&adc0, 1, 1, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC0_SSE1_STEP2 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE1_STEP2
|
|
# ifdef CONFIG_TIVA_ADC0_SSE1_STEP2_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE1_STEP2_TS */
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE1_STEP2_AIN));
|
|
sse_register_chn(&adc0, 1, 2, CONFIG_TIVA_ADC0_SSE1_STEP2_AIN);
|
|
sse_differential(&adc0, 1, 2, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE1_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc0, 1, 2, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC0_SSE1_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC0_SSE1_STEP3
|
|
sse_step_cfg(&adc0, 1, 2, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC0_SSE1_STEP3 */
|
|
sse_step_cfg(&adc0, 1, 2, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC0_SSE1_STEP3 */
|
|
# ifdef CONFIG_TIVA_ADC0_SSE1_STEP3
|
|
# ifdef CONFIG_TIVA_ADC0_SSE1_STEP3_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE1_STEP3_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE1_STEP3_AIN));
|
|
sse_register_chn(&adc0, 1, 3, CONFIG_TIVA_ADC0_SSE1_STEP3_AIN);
|
|
sse_differential(&adc0, 1, 3, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE1_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc0, 1, 3, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC0_SSE1_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
sse_step_cfg(&adc0, 1, 3, chncfg | ADC_SSCTL_END);
|
|
|
|
# endif /* CONFIG_TIVA_ADC0_SSE1_STEP3 */
|
|
# endif /* CONFIG_TIVA_ADC0_SSE1_STEP2 */
|
|
# endif /* CONFIG_TIVA_ADC0_SSE1_STEP1 */
|
|
# endif /* CONFIG_TIVA_ADC0_SSE1_STEP0 */
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC0_SSE1 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE2
|
|
static void adc0_sse2_chn_cfg(void)
|
|
{
|
|
uint32_t chncfg = 0;
|
|
# ifdef CONFIG_TIVA_ADC0_SSE2_STEP0
|
|
# ifdef CONFIG_TIVA_ADC0_SSE2_STEP0_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE2_STEP0_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE2_STEP0_AIN));
|
|
sse_register_chn(&adc0, 2, 0, CONFIG_TIVA_ADC0_SSE2_STEP0_AIN);
|
|
sse_differential(&adc0, 2, 0, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE2_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc0, 2, 0, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC0_SSE2_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC0_SSE2_STEP1
|
|
sse_step_cfg(&adc0, 2, 0, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC0_SSE2_STEP1 */
|
|
sse_step_cfg(&adc0, 2, 0, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC0_SSE2_STEP1 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE2_STEP1
|
|
# ifdef CONFIG_TIVA_ADC0_SSE2_STEP1_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE2_STEP1_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE2_STEP1_AIN));
|
|
sse_register_chn(&adc0, 2, 1, CONFIG_TIVA_ADC0_SSE2_STEP1_AIN);
|
|
sse_differential(&adc0, 2, 1, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE2_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc0, 2, 1, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC0_SSE2_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC0_SSE2_STEP2
|
|
sse_step_cfg(&adc0, 2, 1, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC0_SSE2_STEP2 */
|
|
sse_step_cfg(&adc0, 2, 1, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC0_SSE2_STEP2 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE2_STEP2
|
|
# ifdef CONFIG_TIVA_ADC0_SSE2_STEP2_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE2_STEP2_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE2_STEP2_AIN));
|
|
sse_register_chn(&adc0, 2, 2, CONFIG_TIVA_ADC0_SSE2_STEP2_AIN);
|
|
sse_differential(&adc0, 2, 2, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE2_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc0, 2, 2, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC0_SSE2_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC0_SSE2_STEP3
|
|
sse_step_cfg(&adc0, 2, 2, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC0_SSE2_STEP3 */
|
|
sse_step_cfg(&adc0, 2, 2, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC0_SSE2_STEP3 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE2_STEP3
|
|
# ifdef CONFIG_TIVA_ADC0_SSE2_STEP3_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE2_STEP3_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE2_STEP3_AIN));
|
|
sse_register_chn(&adc0, 2, 3, CONFIG_TIVA_ADC0_SSE2_STEP3_AIN);
|
|
sse_differential(&adc0, 2, 3, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE2_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc0, 2, 3, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC0_SSE2_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
sse_step_cfg(&adc0, 2, 3, chncfg | ADC_SSCTL_END);
|
|
|
|
# endif /* CONFIG_TIVA_ADC0_SSE2_STEP3 */
|
|
# endif /* CONFIG_TIVA_ADC0_SSE2_STEP2 */
|
|
# endif /* CONFIG_TIVA_ADC0_SSE2_STEP1 */
|
|
# endif /* CONFIG_TIVA_ADC0_SSE2_STEP0 */
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC0_SSE2 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC0_SSE3
|
|
static void adc0_sse3_chn_cfg(void)
|
|
{
|
|
uint32_t chncfg = 0;
|
|
# ifdef CONFIG_TIVA_ADC0_SSE3_STEP0
|
|
# ifdef CONFIG_TIVA_ADC0_SSE3_STEP0_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC0_SSE3_STEP0_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC0_SSE3_STEP0_AIN));
|
|
sse_register_chn(&adc0, 3, 0, CONFIG_TIVA_ADC0_SSE3_STEP0_AIN);
|
|
sse_differential(&adc0, 3, 0, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC0_SSE3_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc0, 3, 0, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC0_SSE3_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
sse_step_cfg(&adc0, 3, 0, chncfg | ADC_SSCTL_END);
|
|
|
|
# endif /* CONFIG_TIVA_ADC0_SSE3_STEP0 */
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC0_SSE3 */
|
|
|
|
# endif /* CONFIG_TIVA_ADC0 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0
|
|
static void adc1_sse0_chn_cfg(void)
|
|
{
|
|
uint32_t chncfg = 0;
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0_STEP0
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0_STEP0_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE0_STEP0_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP0_AIN));
|
|
sse_register_chn(&adc1, 0, 0, CONFIG_TIVA_ADC1_SSE0_STEP0_AIN);
|
|
sse_differential(&adc1, 0, 0, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc1, 0, 0, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC1_SSE0_STEP1
|
|
sse_step_cfg(&adc1, 0, 0, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC1_SSE0_STEP1 */
|
|
sse_step_cfg(&adc1, 0, 0, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC1_SSE0_STEP1 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0_STEP1
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0_STEP1_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE0_STEP1_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP1_AIN));
|
|
sse_register_chn(&adc1, 0, 1, CONFIG_TIVA_ADC1_SSE0_STEP1_AIN);
|
|
sse_differential(&adc1, 0, 1, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc1, 0, 1, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC1_SSE0_STEP2
|
|
sse_step_cfg(&adc1, 0, 1, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC1_SSE0_STEP2 */
|
|
sse_step_cfg(&adc1, 0, 1, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC1_SSE0_STEP2 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0_STEP2
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0_STEP2_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE0_STEP2_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP2_AIN));
|
|
sse_register_chn(&adc1, 0, 2, CONFIG_TIVA_ADC1_SSE0_STEP2_AIN);
|
|
sse_differential(&adc1, 0, 2, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc1, 0, 2, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC1_SSE0_STEP3
|
|
sse_step_cfg(&adc1, 0, 2, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC1_SSE0_STEP3 */
|
|
sse_step_cfg(&adc1, 0, 2, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC1_SSE0_STEP3 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0_STEP3
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0_STEP3_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE0_STEP3_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP3_AIN));
|
|
sse_register_chn(&adc1, 0, 3, CONFIG_TIVA_ADC1_SSE0_STEP3_AIN);
|
|
sse_differential(&adc1, 0, 3, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc1, 0, 3, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC1_SSE0_STEP4
|
|
sse_step_cfg(&adc1, 0, 3, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC1_SSE0_STEP4 */
|
|
sse_step_cfg(&adc1, 0, 3, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC1_SSE0_STEP4 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0_STEP4
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0_STEP4_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE0_STEP4_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP4_AIN));
|
|
sse_register_chn(&adc1, 0, 4, CONFIG_TIVA_ADC1_SSE0_STEP4_AIN);
|
|
sse_differential(&adc1, 0, 4, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc1, 0, 4, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC1_SSE0_STEP5
|
|
sse_step_cfg(&adc1, 0, 4, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC1_SSE0_STEP5 */
|
|
sse_step_cfg(&adc1, 0, 4, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC1_SSE0_STEP5 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0_STEP5
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0_STEP5_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE0_STEP5_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP5_AIN));
|
|
sse_register_chn(&adc1, 0, 5, CONFIG_TIVA_ADC1_SSE0_STEP5_AIN);
|
|
sse_differential(&adc1, 0, 5, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc1, 0, 5, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC1_SSE0_STEP6
|
|
sse_step_cfg(&adc1, 0, 5, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC1_SSE0_STEP6 */
|
|
sse_step_cfg(&adc1, 0, 5, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC1_SSE0_STEP6 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0_STEP6
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0_STEP6_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE0_STEP6_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP6_AIN));
|
|
sse_register_chn(&adc1, 0, 6, CONFIG_TIVA_ADC1_SSE0_STEP6_AIN);
|
|
sse_differential(&adc1, 0, 6, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc1, 0, 6, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC1_SSE0_STEP7
|
|
sse_step_cfg(&adc1, 0, 6, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC1_SSE0_STEP7 */
|
|
sse_step_cfg(&adc1, 0, 6, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC1_SSE0_STEP7 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0_STEP7
|
|
# ifdef CONFIG_TIVA_ADC1_SSE0_STEP7_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE0_STEP7_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE0_STEP7_AIN));
|
|
sse_register_chn(&adc1, 0, 7, CONFIG_TIVA_ADC1_SSE0_STEP7_AIN);
|
|
sse_differential(&adc1, 0, 7, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE0_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc1, 0, 7, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC1_SSE0_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
sse_step_cfg(&adc1, 0, 7, chncfg | ADC_SSCTL_END);
|
|
|
|
# endif /* CONFIG_TIVA_ADC1_SSE0_STEP7 */
|
|
# endif /* CONFIG_TIVA_ADC1_SSE0_STEP6 */
|
|
# endif /* CONFIG_TIVA_ADC1_SSE0_STEP5 */
|
|
# endif /* CONFIG_TIVA_ADC1_SSE0_STEP4 */
|
|
# endif /* CONFIG_TIVA_ADC1_SSE0_STEP3 */
|
|
# endif /* CONFIG_TIVA_ADC1_SSE0_STEP2 */
|
|
# endif /* CONFIG_TIVA_ADC1_SSE0_STEP1 */
|
|
# endif /* CONFIG_TIVA_ADC1_SSE0_STEP0 */
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC1_SSE0 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE1
|
|
static void adc1_sse1_chn_cfg(void)
|
|
{
|
|
uint32_t chncfg = 0;
|
|
# ifdef CONFIG_TIVA_ADC1_SSE1_STEP0
|
|
# ifdef CONFIG_TIVA_ADC1_SSE1_STEP0_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE1_STEP0_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE1_STEP0_AIN));
|
|
sse_register_chn(&adc1, 1, 0, CONFIG_TIVA_ADC1_SSE1_STEP0_AIN);
|
|
sse_differential(&adc1, 1, 0, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE1_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc1, 1, 0, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC1_SSE1_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC1_SSE1_STEP1
|
|
sse_step_cfg(&adc1, 1, 0, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC1_SSE1_STEP1 */
|
|
sse_step_cfg(&adc1, 1, 0, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC1_SSE1_STEP1 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE1_STEP1
|
|
# ifdef CONFIG_TIVA_ADC1_SSE1_STEP1_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE1_STEP1_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE1_STEP1_AIN));
|
|
sse_register_chn(&adc1, 1, 1, CONFIG_TIVA_ADC1_SSE1_STEP1_AIN);
|
|
sse_differential(&adc1, 1, 1, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE1_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc1, 1, 1, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC1_SSE1_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC1_SSE1_STEP2
|
|
sse_step_cfg(&adc1, 1, 1, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC1_SSE1_STEP2 */
|
|
sse_step_cfg(&adc1, 1, 1, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC1_SSE1_STEP2 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE1_STEP2
|
|
# ifdef CONFIG_TIVA_ADC1_SSE1_STEP2_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE1_STEP2_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE1_STEP2_AIN));
|
|
sse_register_chn(&adc1, 1, 2, CONFIG_TIVA_ADC1_SSE1_STEP2_AIN);
|
|
sse_differential(&adc1, 1, 2, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE1_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc1, 1, 2, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC1_SSE1_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC1_SSE1_STEP3
|
|
sse_step_cfg(&adc1, 1, 2, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC1_SSE1_STEP3 */
|
|
sse_step_cfg(&adc1, 1, 2, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC1_SSE1_STEP3 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE1_STEP3
|
|
# ifdef CONFIG_TIVA_ADC1_SSE1_STEP3_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE1_STEP3_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE1_STEP3_AIN));
|
|
sse_register_chn(&adc1, 1, 3, CONFIG_TIVA_ADC1_SSE1_STEP3_AIN);
|
|
sse_differential(&adc1, 1, 3, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE1_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc1, 1, 3, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC1_SSE1_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
sse_step_cfg(&adc1, 1, 3, chncfg | ADC_SSCTL_END);
|
|
|
|
# endif /* CONFIG_TIVA_ADC1_SSE1_STEP3 */
|
|
# endif /* CONFIG_TIVA_ADC1_SSE1_STEP2 */
|
|
# endif /* CONFIG_TIVA_ADC1_SSE1_STEP1 */
|
|
# endif /* CONFIG_TIVA_ADC1_SSE1_STEP0 */
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC1_SSE1 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE2
|
|
static void adc1_sse2_chn_cfg(void)
|
|
{
|
|
uint32_t chncfg = 0;
|
|
# ifdef CONFIG_TIVA_ADC1_SSE2_STEP0
|
|
# ifdef CONFIG_TIVA_ADC1_SSE2_STEP0_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE2_STEP0_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE2_STEP0_AIN));
|
|
sse_register_chn(&adc1, 2, 0, CONFIG_TIVA_ADC1_SSE2_STEP0_AIN);
|
|
sse_differential(&adc1, 2, 0, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE2_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc1, 2, 0, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC1_SSE2_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC1_SSE2_STEP1
|
|
sse_step_cfg(&adc1, 2, 0, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC1_SSE2_STEP1 */
|
|
sse_step_cfg(&adc1, 2, 0, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC1_SSE2_STEP1 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE2_STEP1
|
|
# ifdef CONFIG_TIVA_ADC1_SSE2_STEP1_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE2_STEP1_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE2_STEP1_AIN));
|
|
sse_register_chn(&adc1, 2, 1, CONFIG_TIVA_ADC1_SSE2_STEP1_AIN);
|
|
sse_differential(&adc1, 2, 1, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE2_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc1, 2, 1, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC1_SSE2_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC1_SSE2_STEP2
|
|
sse_step_cfg(&adc1, 2, 1, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC1_SSE2_STEP2 */
|
|
sse_step_cfg(&adc1, 2, 1, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC1_SSE2_STEP2 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE2_STEP2
|
|
# ifdef CONFIG_TIVA_ADC1_SSE2_STEP2_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE2_STEP2_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE2_STEP2_AIN));
|
|
sse_register_chn(&adc1, 2, 2, CONFIG_TIVA_ADC1_SSE2_STEP2_AIN);
|
|
sse_differential(&adc1, 2, 2, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE2_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc1, 2, 2, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC1_SSE2_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
# ifndef CONFIG_TIVA_ADC1_SSE2_STEP3
|
|
sse_step_cfg(&adc1, 2, 2, chncfg | ADC_SSCTL_END);
|
|
|
|
# else /* CONFIG_TIVA_ADC1_SSE2_STEP3 */
|
|
sse_step_cfg(&adc1, 2, 2, chncfg);
|
|
# endif /* !CONFIG_TIVA_ADC1_SSE2_STEP3 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE2_STEP3
|
|
# ifdef CONFIG_TIVA_ADC1_SSE2_STEP3_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE2_STEP3_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE2_STEP3_AIN));
|
|
sse_register_chn(&adc1, 2, 3, CONFIG_TIVA_ADC1_SSE2_STEP3_AIN);
|
|
sse_differential(&adc1, 2, 3, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE2_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc1, 2, 3, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC1_SSE2_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
sse_step_cfg(&adc1, 2, 3, chncfg | ADC_SSCTL_END);
|
|
|
|
# endif /* CONFIG_TIVA_ADC1_SSE2_STEP3 */
|
|
# endif /* CONFIG_TIVA_ADC1_SSE2_STEP2 */
|
|
# endif /* CONFIG_TIVA_ADC1_SSE2_STEP1 */
|
|
# endif /* CONFIG_TIVA_ADC1_SSE2_STEP0 */
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC1_SSE2 */
|
|
|
|
# ifdef CONFIG_TIVA_ADC1_SSE3
|
|
static void adc1_sse3_chn_cfg(void)
|
|
{
|
|
uint32_t chncfg = 0;
|
|
# ifdef CONFIG_TIVA_ADC1_SSE3_STEP0
|
|
# ifdef CONFIG_TIVA_ADC1_SSE3_STEP0_TS
|
|
chncfg = ADC_SSCTL_IE | ADC_SSCTL_TS;
|
|
# else /* ADC_SSCTL_IE */
|
|
chncfg = ADC_SSCTL_IE;
|
|
# endif /* CONFIG_TIVA_ADC1_SSE3_STEP0_TS */
|
|
|
|
tiva_configgpio(TIVA_ADC_PIN(CONFIG_TIVA_ADC1_SSE3_STEP0_AIN));
|
|
sse_register_chn(&adc1, 3, 0, CONFIG_TIVA_ADC1_SSE3_STEP0_AIN);
|
|
sse_differential(&adc1, 3, 0, 0);
|
|
# if defined (CONFIG_ARCH_CHIP_TM4C129) && (CONFIG_TIVA_ADC1_SSE3_TRIGGER == ADC_EMUX_PROC)
|
|
sse_sample_hold_time(&adc1, 3, 0, ADC_SSTH_SHOLD_16);
|
|
# endif /* (CONFIG_TIVA_ADC1_SSE3_TRIGGER ==
|
|
* ADC_EMUX_PROC) && defined
|
|
* (CONFIG_ARCH_CHIP_TM4C129) */
|
|
|
|
sse_step_cfg(&adc1, 3, 0, chncfg | ADC_SSCTL_END);
|
|
|
|
# endif /* CONFIG_TIVA_ADC1_SSE3_STEP0 */
|
|
}
|
|
# endif /* CONFIG_TIVA_ADC1_SSE3 */
|
|
# endif /* CONFIG_TIVA_ADC1 */
|
|
|
|
#endif /* CONFIG_TIVA_ADC0 | CONFIG_TIVA_ADC1 */
|