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David Sidrane
0c57351f78
mmcsd:Remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT stm32h7:sdmmc remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT stm32f7:sdmmc remove CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT stm32f7:sdmmc WRITE COMPLETE prevent false triggers stm32h7:sdmmc WRITE COMPLETE prevent false triggers While testing PR #2989 on the H7 I noticed that the cards were staying in 1-bit mode. The root cause was that the scr read path was using DMA without an invlidate. This was caused by CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT, but the sdmmc driver, did not use the delayed invalidate nor would it work on 8 bytes. The driver fully supported dcache mgt on runt buffers, but the #ifdef CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT blocked it. Reviewing the PR that added CONFIG_ARCH_HAVE_SDIO_DELAYED_INVLDT it may have been valid at the time. But after the dcache operations we fixed. It is not necessary and offers no benefit.