mirror of
https://github.com/apache/nuttx.git
synced 2026-06-04 14:53:47 +08:00
Alin Jerpelea
8c1456da6b
Nxstyle fixes to pass CI Signed-off-by: Alin Jerpelea <alin.jerpelea@sony.com>
285 lines
9.6 KiB
C
285 lines
9.6 KiB
C
/****************************************************************************
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* arch/x86/include/i486/irq.h
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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/* This file should never be included directly but, rather, only indirectly
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* through nuttx/irq.h
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*/
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#ifndef __ARCH_X86_INCLUDE_I486_IRQ_H
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#define __ARCH_X86_INCLUDE_I486_IRQ_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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# include <stdbool.h>
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# include <arch/arch.h>
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#endif
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* ISR and IRQ numbers */
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#define ISR0 0 /* Division by zero exception */
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#define ISR1 1 /* Debug exception */
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#define ISR2 2 /* Non maskable interrupt */
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#define ISR3 3 /* Breakpoint exception */
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#define ISR4 4 /* 'Into detected overflow' */
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#define ISR5 5 /* Out of bounds exception */
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#define ISR6 6 /* Invalid opcode exception */
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#define ISR7 7 /* No coprocessor exception */
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#define ISR8 8 /* Double fault (pushes an error code) */
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#define ISR9 9 /* Coprocessor segment overrun */
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#define ISR10 10 /* Bad TSS (pushes an error code) */
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#define ISR11 11 /* Segment not present (pushes an error code) */
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#define ISR12 12 /* Stack fault (pushes an error code) */
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#define ISR13 13 /* General protection fault (pushes an error code) */
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#define ISR14 14 /* Page fault (pushes an error code) */
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#define ISR15 15 /* Unknown interrupt exception */
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#define ISR16 16 /* Coprocessor fault */
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#define ISR17 17 /* Alignment check exception */
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#define ISR18 18 /* Machine check exception */
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#define ISR19 19 /* Reserved */
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#define ISR20 20 /* Reserved */
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#define ISR21 21 /* Reserved */
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#define ISR22 22 /* Reserved */
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#define ISR23 23 /* Reserved */
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#define ISR24 24 /* Reserved */
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#define ISR25 25 /* Reserved */
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#define ISR26 26 /* Reserved */
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#define ISR27 27 /* Reserved */
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#define ISR28 28 /* Reserved */
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#define ISR29 29 /* Reserved */
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#define ISR30 30 /* Reserved */
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#define ISR31 31 /* Reserved */
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#define IRQ0 32 /* System timer (cannot be changed) */
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#define IRQ1 33 /* Keyboard controller (cannot be changed) */
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#define IRQ2 34 /* Cascaded signals from IRQs 8–15 */
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#define IRQ3 35 /* Serial port controller for COM2/4 */
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#define IRQ4 36 /* serial port controller for COM1/3 */
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#define IRQ5 37 /* LPT port 2 or sound card */
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#define IRQ6 38 /* Floppy disk controller */
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#define IRQ7 39 /* LPT port 1 or sound card */
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#define IRQ8 40 /* Real time clock (RTC) */
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#define IRQ9 41 /* Open interrupt/available or SCSI host adapter */
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#define IRQ10 42 /* Open interrupt/available or SCSI or NIC */
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#define IRQ11 43 /* Open interrupt/available or SCSI or NIC */
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#define IRQ12 44 /* Mouse on PS/2 connector */
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#define IRQ13 45 /* Math coprocessor */
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#define IRQ14 46 /* Primary ATA channel */
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#define IRQ15 47 /* Secondary ATA channel */
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#define NR_IRQS 48
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/* Common register save structure created by up_saveusercontext() and by
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* ISR/IRQ interrupt processing.
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*/
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#define REG_DS (0) /* Data segment selector */
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#define REG_EDI (1) /* Saved by pusha */
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#define REG_ESI (2) /* " " "" " " */
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#define REG_EBP (3) /* " " "" " " */
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#define REG_ESP (4) /* " " "" " " (NOTE 1)*/
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#define REG_EBX (5) /* " " "" " " */
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#define REG_EDX (6) /* " " "" " " */
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#define REG_ECX (7) /* " " "" " " */
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#define REG_EAX (8) /* " " "" " " */
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#define REG_IRQNO (9) /* Interrupt number (NOTE 2) */
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#define REG_ERRCODE (10) /* Error code (NOTE 2) */
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#define REG_EIP (11) /* Pushed by process on interrupt processing */
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#define REG_CS (12) /* " " "" " " "" " " " " */
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#define REG_EFLAGS (13) /* " " "" " " "" " " " " */
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#define REG_SP (14) /* " " "" " " "" " " " " */
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#define REG_SS (15) /* " " "" " " "" " " " " */
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/* NOTE 1: Two versions of the ESP are saved: One from the interrupt
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* processing and one from pusha. Only the interrupt ESP (REG_SP) is used.
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* NOTE 2: This is not really state data. Rather, this is just a convenient
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* way to pass parameters from the interrupt handler to C cod.
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*/
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#define XCPTCONTEXT_REGS (16)
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#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS)
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/* Some special landmarks in the stack frame:
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*
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* TOP_PUSHA - The offset (in 32-bit words) from the beginning of the
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* save area on the stack to the value that should be in REG_ESP.
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* BOTTOM_PUSHA - The offset (in 32-bit words) from the stack position before
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* the interrupt occurred to the value that should be in REG_ESP.
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* save area on the stack to the value that should be in REG_ESP.
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* OFFSET_PRIO - The offset from the value of REG_ESP to the value of the
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* stack pointer before the interrupt occurred (assuming that a priority
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* change occurred.
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* OFFSET_PRIO - The offset from the value of REG_ESP to the value of the
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* stack pointer before the interrupt occurred (assuming that NO priority
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* change occurred.
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*/
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#define TOP_PUSHA REG_IRQNO
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#define BOTTOM_PRIO (XCPTCONTEXT_REGS-REG_IRQNO)
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#define BOTTOM_NOPRIO (REG_SP-REG_IRQNO)
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/****************************************************************************
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* Public Types
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****************************************************************************/
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/* This struct defines the way the registers are stored */
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#ifndef __ASSEMBLY__
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struct xcptcontext
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{
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/* The following function pointer is non-zero if there are pending signals
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* to be processed.
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*/
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void *sigdeliver; /* Actual type is sig_deliver_t */
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/* These are saved copies of instruction pointer and EFLAGS used during
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* signal processing.
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*
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* REVISIT: Because there is only one copy of these save areas,
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* only a single signal handler can be active. This precludes
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* queuing of signal actions. As a result, signals received while
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* another signal handler is executing will be ignored!
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*/
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uint32_t saved_eip;
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uint32_t saved_eflags;
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/* Register save area */
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uint32_t regs[XCPTCONTEXT_REGS];
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};
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#endif
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/****************************************************************************
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* Inline functions
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****************************************************************************/
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#ifndef __ASSEMBLY__
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/* Name: up_irq_save, up_irq_restore, and friends.
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*
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* NOTE: This function should never be called from application code and,
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* as a general rule unless you really know what you are doing, this
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* function should not be called directly from operation system code either:
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* Typically, the wrapper functions, enter_critical_section() and
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* leave_critical section(), are probably what you really want.
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*/
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/* Get the current FLAGS register contents */
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static inline irqstate_t irqflags()
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{
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irqstate_t flags;
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asm volatile(
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"\tpushf\n"
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"\tpop %0\n"
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: "=rm" (flags)
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:
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: "memory");
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return flags;
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}
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/* Get a sample of the FLAGS register, determine if interrupts are disabled.
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* If the X86_FLAGS_IF is cleared by cli, then interrupts are disabled. If
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* if the X86_FLAGS_IF is set by sti, then interrupts are enable.
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*/
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static inline bool up_irq_disabled(irqstate_t flags)
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{
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return ((flags & X86_FLAGS_IF) == 0);
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}
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static inline bool up_irq_enabled(irqstate_t flags)
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{
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return ((flags & X86_FLAGS_IF) != 0);
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}
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/* Disable interrupts unconditionally */
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static inline void up_irq_disable(void)
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{
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asm volatile("cli": : :"memory");
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}
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/* Enable interrupts unconditionally */
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static inline void up_irq_enable(void)
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{
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asm volatile("sti": : :"memory");
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}
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/* Disable interrupts, but return previous interrupt state */
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static inline irqstate_t up_irq_save(void)
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{
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irqstate_t flags = irqflags();
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up_irq_disable();
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return flags;
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}
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/* Conditionally disable interrupts */
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static inline void up_irq_restore(irqstate_t flags)
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{
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if (up_irq_enabled(flags))
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{
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up_irq_enable();
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}
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}
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static inline void system_call3(unsigned int nbr, uintptr_t parm1,
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uintptr_t parm2, uintptr_t parm3)
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{
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/* To be provided */
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}
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/****************************************************************************
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* Public Data
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****************************************************************************/
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#ifdef __cplusplus
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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#undef EXTERN
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#ifdef __cplusplus
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __ARCH_X86_INCLUDE_I486_IRQ_H */
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