tjwu1217 4969f8faf9 risc-v Toolchain.defs compatibility. ...

Reference:https://xpack.github.io/blog/2022/05/18/riscv-none-elf-gcc-v12-1-0-2-released/

RISC-V ISA updates

Compared to previous releases, starting from 12.x, the compiler implements the new RISC-V ISA, which introduces an incompatibility issue, and builds might throw error messages like unrecognized opcode csrr.

The reason is that csr read/write (csrr*/csrw*) instructions and fence.i instruction were separated from the I extension, becoming two standalone extensions: Zicsr and Zifencei.

The solution is to add _zicsr and/or _zifencei to the -march option, e.g. -march=rv32imac becomes -march=rv32imac_zicsr_zifencei.

2023-07-01 13:19:30 +08:00

..

include

arch/risc-v/espressif: Add full GPIO support

2023-06-24 13:11:45 +08:00

src

risc-v Toolchain.defs compatibility.

2023-07-01 13:19:30 +08:00

Kconfig

boards/litex/arty_a7: Support building fully linked executables.

2023-06-28 15:16:28 +08:00