mirror of
https://github.com/apache/nuttx.git
synced 2026-06-06 08:22:32 +08:00
Gregory Nutt
475 lines
15 KiB
C
475 lines
15 KiB
C
/****************************************************************************
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* arch/xtensa/src/esp32/esp32_irq.c
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*
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* Copyright (C) 2016 Gregory Nutt. All rights reserved.
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* Author: Gregory Nutt <gnutt@nuttx.org>
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*
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* Redistribution and use in source and binary forms, with or without
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* modification, are permitted provided that the following conditions
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* are met:
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*
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* 1. Redistributions of source code must retain the above copyright
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* notice, this list of conditions and the following disclaimer.
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* 2. Redistributions in binary form must reproduce the above copyright
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* notice, this list of conditions and the following disclaimer in
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* the documentation and/or other materials provided with the
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* distribution.
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* 3. Neither the name NuttX nor the names of its contributors may be
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* used to endorse or promote products derived from this software
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* without specific prior written permission.
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*
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* THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
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* "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
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* LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
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* FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
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* COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
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* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
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* BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
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* OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
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* AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
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* LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
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* ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
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* POSSIBILITY OF SUCH DAMAGE.
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*
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****************************************************************************/
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#include <stdint.h>
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#include <assert.h>
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#include <errno.h>
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#include <debug.h>
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#include <nuttx/arch.h>
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#include <nuttx/irq.h>
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#include <arch/irq.h>
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#include "chip/esp32_dport.h"
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#include "esp32_cpuint.h"
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#include "xtensa.h"
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Mapping Peripheral IDs to map register addresses
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*
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* PERIPHERAL ID DPORT REGISTER OFFSET
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* MNEMONIC VAL PRO CPU APP CPU
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* -------------------------- --- ------- -------
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* ESP32_PERIPH_MAC 0 0x104 0x218
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* ESP32_PERIPH_MAC_NMI 1 0x108 0x21c
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* ESP32_PERIPH_BB 2 0x10c 0x220
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* ESP32_PERIPH_BB_MAC 3 0x110 0x224
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* ESP32_PERIPH_BT_BB 4 0x114 0x228
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* ESP32_PERIPH_BT_BB_NMI 5 0x118 0x22c
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* ESP32_PERIPH_RWBT_IRQ 6 0x11c 0x230
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* ESP32_PERIPH_RWBLE_IRQ 7 0x120 0x234
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* ESP32_PERIPH_RWBT_NMI 8 0x124 0x238
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* ESP32_PERIPH_RWBLE_NMI 9 0x128 0x23c
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* ESP32_PERIPH_SLC0 10 0x12c 0x240
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* ESP32_PERIPH_SLC1 11 0x130 0x244
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* ESP32_PERIPH_UHCI0 12 0x134 0x248
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* ESP32_PERIPH_UHCI1 13 0x138 0x24c
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* ESP32_PERIPH_TG_T0_LEVEL 14 0x13c 0x250
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* ESP32_PERIPH_TG_T1_LEVEL 15 0x140 0x254
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* ESP32_PERIPH_TG_WDT_LEVEL 16 0x144 0x258
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* ESP32_PERIPH_TG_LACT_LEVEL 17 0x148 0x25c
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* ESP32_PERIPH_TG1_T0_LEVEL 18 0x14c 0x260
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* ESP32_PERIPH_TG1_T1_LEVEL 19 0x150 0x264
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* ESP32_PERIPH_TG1_WDT_LEVEL 20 0x154 0x268
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* ESP32_PERIPH_G1_LACT_LEVEL 21 0x158 0x26c
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* ESP32_PERIPH_CPU_GPIO 22 0x15c 0x270
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* ESP32_PERIPH_CPU_NMI 23 0x160 0x274
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* ESP32_PERIPH_CPU_CPU0 24 0x164 0x278
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* ESP32_PERIPH_CPU_CPU1 25 0x168 0x27c
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* ESP32_PERIPH_CPU_CPU2 26 0x16c 0x280
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* ESP32_PERIPH_CPU_CPU3 27 0x170 0x284
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* ESP32_PERIPH_SPI0 28 0x174 0x288
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* ESP32_PERIPH_SPI1 29 0x178 0x28c
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* ESP32_PERIPH_SPI2 30 0x17c 0x290
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* ESP32_PERIPH_SPI3 31 0x180 0x294
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* ESP32_PERIPH_I2S0 32 0x184 0x298
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* ESP32_PERIPH_I2S1 33 0x188 0x29c
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* ESP32_PERIPH_UART 34 0x18c 0x2a0
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* ESP32_PERIPH_UART1 35 0x190 0x2a4
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* ESP32_PERIPH_UART2 36 0x194 0x2a8
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* ESP32_PERIPH_SDIO_HOST 37 0x198 0x2ac
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* ESP32_PERIPH_EMAC 38 0x19c 0x2b0
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* ESP32_PERIPH_PWM0 39 0x1a0 0x2b4
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* ESP32_PERIPH_PWM1 40 0x1a4 0x2b8
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* ESP32_PERIPH_PWM2 41 0x1a8 0x2bc
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* ESP32_PERIPH_PWM3 42 0x1ac 0x2c0
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* ESP32_PERIPH_LEDC 43 0x1b0 0x2c4
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* ESP32_PERIPH_EFUSE 44 0x1b4 0x2c8
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* ESP32_PERIPH_CAN 45 0x1b8 0x2cc
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* ESP32_PERIPH_RTC_CORE 46 0x1bc 0x2d0
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* ESP32_PERIPH_RMT 47 0x1c0 0x2d4
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* ESP32_PERIPH_PCNT 48 0x1c4 0x2d8
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* ESP32_PERIPH_I2C_EXT0 49 0x1c8 0x2dc
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* ESP32_PERIPH_I2C_EXT1 50 0x1cc 0x2e0
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* ESP32_PERIPH_RSA 51 0x1d0 0x2e4
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* ESP32_PERIPH_SPI1_DMA 52 0x1d4 0x2e8
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* ESP32_PERIPH_SPI2_DMA 53 0x1d8 0x2ec
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* ESP32_PERIPH_SPI3_DMA 54 0x1dc 0x2f0
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* ESP32_PERIPH_WDG 55 0x1e0 0x2f4
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* ESP32_PERIPH_TIMER1 56 0x1e4 0x2f8
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* ESP32_PERIPH_TIMER2 57 0x1e8 0x2fc
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* ESP32_PERIPH_TG_T0_EDGE 58 0x1ec 0x300
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* ESP32_PERIPH_TG_T1_EDGE 59 0x1f0 0x304
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* ESP32_PERIPH_TG_WDT_EDGE 60 0x1F4 0x308
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* ESP32_PERIPH_TG_LACT_EDGE 61 0x1F8 0x30c
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* ESP32_PERIPH_TG1_T0_EDGE 62 0x1fc 0x310
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* ESP32_PERIPH_TG1_T1_EDGE 63 0x200 0x314
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* ESP32_PERIPH_TG1_WDT_EDGE 64 0x204 0x318
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* ESP32_PERIPH_TG1_LACT_EDGE 65 0x208 0x31c
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* ESP32_PERIPH_MMU_IA 66 0x20c 0x320
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* ESP32_PERIPH_MPU_IA 67 0x210 0x324
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* ESP32_PERIPH_CACHE_IA 68 0x214 0x328
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*/
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#define DPORT_PRO_MAP_REGADDR(n) (DR_REG_DPORT_BASE + 0x104 + ((n) << 2))
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#define DPORT_APP_MAP_REGADDR(n) (DR_REG_DPORT_BASE + 0x218 + ((n) << 2))
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/* CPU interrupts can be detached from any peripheral source by setting the
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* map register to an internal CPU interrupt (6, 7, 11, 15, 16, or 29).
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*/
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#define NO_CPUINT ESP32_CPUINT_TIMER0
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/* Priority range is 1-5 */
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#define ESP32_MIN_PRIORITY 1
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#define ESP32_MAX_PRIORITY 5
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#define ESP32_PRIO_INDEX(p) ((p) - ESP32_MIN_PRIORITY)
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/****************************************************************************
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* Private Data
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****************************************************************************/
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/* g_intenable[] is a shadow copy of the per-CPU INTENABLE register
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* content.
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*/
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#ifdef CONFIG_SMP
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static uint32_t g_intenable[CONFIG_SMP_NCPUS];
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#else
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static uint32_t g_intenable[1];
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#endif
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/* Bitsets for free, unallocated CPU interrupts */
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static uint32_t g_free_cpuints = 0xffffffff;
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/* Bitsets for each interrupt priority 1-5 */
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static const uint32_t g_priority[5] =
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{
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ESP32_INTPRI1_MASK,
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ESP32_INTPRI2_MASK,
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ESP32_INTPRI3_MASK,
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ESP32_INTPRI4_MASK,
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ESP32_INTPRI5_MASK
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};
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/****************************************************************************
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* Private Functions
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****************************************************************************/
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/****************************************************************************
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* Name: esp32_alloc_cpuint
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*
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* Description:
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* Allocate a CPU interrupt
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*
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* Input Parameters:
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* intmask - mask of candidate CPU interrupts. The CPU interrupt will be
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* be allocated from free interrupts within this set
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*
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* Returned Value:
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* On success, the allocated level-sensitive, CPU interrupt numbr is
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* returned. A negated errno is returned on failure. The only possible
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* failure is that all level-sensitive CPU interrupts have already been
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* allocated.
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*
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****************************************************************************/
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int esp32_alloc_cpuint(uint32_t intmask)
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{
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irqstate_t flags;
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uint32_t bitmask;
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uint32_t intset;
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int cpuint;
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int ret = -ENOMEM;
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/* Check if there are is CPU interrupts with the requrested properties
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* available.
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*/
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flags = enter_critical_section();
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intset = g_free_cpuints & intmask;
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if (intset != 0)
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{
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/* Skip over initial unavailable CPU interrupts quickly in groups
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* of 8 interrupt.
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*/
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for (cpuint = 0, bitmask = 0xff;
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cpuint <= ESP32_CPUINT_MAX;
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cpuint += 8, bitmask <<= 8);
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/* Search for an unallocated CPU interrupt number in the remaining
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* intset.
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*/
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for (; cpuint <= ESP32_CPUINT_MAX; cpuint++)
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{
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/* If the bit corresponding to the CPU interrupt is '1', then
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* that CPU interrupt is available.
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*/
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bitmask = (1ul << cpuint);
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if ((intset & bitmask) != 0)
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{
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/* Got it! */
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g_free_cpuints &= ~bitmask;
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ret = cpuint;
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break;
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}
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}
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}
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leave_critical_section(flags);
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return ret;
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}
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/****************************************************************************
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* Public Functions
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****************************************************************************/
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/****************************************************************************
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* Name: up_disable_irq
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*
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* Description:
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* Disable the CPU interrupt specified by 'cpuint'
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*
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****************************************************************************/
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void up_disable_irq(int cpuint)
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{
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#ifdef CONFIG_SMP
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int cpu;
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#endif
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DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX);
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#ifdef CONFIG_SMP
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cpu = up_cpu_index();
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(void)xtensa_disable_cpuint(&g_intenable[cpu], (1ul << cpuint));
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#else
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(void)xtensa_disable_cpuint(&g_intenable[0], (1ul << cpuint));
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#endif
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}
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/****************************************************************************
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* Name: up_enable_irq
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*
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* Description:
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* Ensable the CPU interrupt specified by 'cpuint'
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*
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****************************************************************************/
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void up_enable_irq(int cpuint)
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{
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#ifdef CONFIG_SMP
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int cpu;
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#endif
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DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX);
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#ifdef CONFIG_SMP
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cpu = up_cpu_index();
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(void)xtensa_enable_cpuint(&g_intenable[cpu], (1ul << cpuint));
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#else
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(void)xtensa_enable_cpuint(&g_intenable[0], (1ul << cpuint));
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#endif
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}
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/****************************************************************************
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* Name: esp32_alloc_levelint
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*
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* Description:
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* Allocate a level CPU interrupt
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*
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* Input Parameters:
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* priority - Priority of the CPU interrupt (1-5)
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*
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* Returned Value:
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* On success, the allocated level-sensitive, CPU interrupt numbr is
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* returned. A negated errno is returned on failure. The only possible
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* failure is that all level-sensitive CPU interrupts have already been
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* allocated.
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*
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****************************************************************************/
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int esp32_alloc_levelint(int priority)
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{
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uint32_t intmask;
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DEBUGASSERT(priority >= ESP32_MIN_PRIORITY &&
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priority <= ESP32_MAX_PRIORITY);
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/* Check if there are any level CPU interrupts available at the requested
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* interrupt priority.
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*/
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intmask = g_priority[ESP32_PRIO_INDEX(priority)] & EPS32_CPUINT_LEVELSET;
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return esp32_alloc_cpuint(intmask);
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}
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/****************************************************************************
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* Name: esp32_alloc_edgeint
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*
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* Description:
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* Allocate an edge CPU interrupt
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*
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* Input Parameters:
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* priority - Priority of the CPU interrupt (1-5)
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*
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* Returned Value:
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* On success, the allocated edge-sensitive, CPU interrupt numbr is
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* returned. A negated errno is returned on failure. The only possible
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* failure is that all edge-sensitive CPU interrupts have already been
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* allocated.
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*
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****************************************************************************/
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int esp32_alloc_edgeint(int priority)
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{
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uint32_t intmask;
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DEBUGASSERT(priority >= ESP32_MIN_PRIORITY &&
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priority <= ESP32_MAX_PRIORITY);
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/* Check if there are any edge CPU interrupts available at the requested
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* interrupt priority.
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*/
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intmask = g_priority[ESP32_PRIO_INDEX(priority)] & EPS32_CPUINT_EDGESET;
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return esp32_alloc_cpuint(intmask);
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}
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/****************************************************************************
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* Name: esp32_free_cpuint
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*
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* Description:
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* Free a previoulsy allocated CPU interrupt
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*
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* Input Parameters:
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* The CPU interrupt number to be freed
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void esp32_free_cpuint(int cpuint)
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{
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irqstate_t flags;
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uint32_t bitmask;
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DEBUGASSERT(cpuint >= 0 && cpuint < ESP32_CPUINT_NEDGEPERIPHS);
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/* Mark the CPU interrupt as available */
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bitmask = (1ul << cpuint);
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flags = enter_critical_section();
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DEBUGASSERT((g_free_cpuints & bitmask) == 0);
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g_free_cpuints |= bitmask;
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leave_critical_section(flags);
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}
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/****************************************************************************
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* Name: esp32_attach_peripheral
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*
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* Description:
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* Attach a peripheral interupt to a CPU interrupt.
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*
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* Input Parameters:
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* cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
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* periphid - The peripheral number from ira.h to be assigned.
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* cpuint - The CPU interrupt to receive the peripheral interrupt
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void esp32_attach_peripheral(int cpu, int periphid, int cpuint)
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{
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uintptr_t regaddr;
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DEBUGASSERT(periphid >= 0 && periphid < ESP32_NPERIPHERALS);
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DEBUGASSERT(cpuint >= 0 && cpuint <= ESP32_CPUINT_MAX);
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#ifdef CONFIG_SMP
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DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS);
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if (cpu != 0)
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{
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regaddr = DPORT_APP_MAP_REGADDR(periphid);
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}
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else
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#endif
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{
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regaddr = DPORT_PRO_MAP_REGADDR(periphid);
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}
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putreg32(cpuint, regaddr);
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}
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/****************************************************************************
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* Name: esp32_detach_peripheral
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*
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* Description:
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* Detach a peripheral interupt from a CPU interrupt.
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*
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* Input Parameters:
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* cpu - The CPU to receive the interrupt 0=PRO CPU 1=APP CPU
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* periphid - The peripheral number from ira.h to be assigned.
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*
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* Returned Value:
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* None
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*
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****************************************************************************/
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void esp32_detach_peripheral(int cpu, int periphid)
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{
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uintptr_t regaddr;
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DEBUGASSERT(periphid >= 0 && periphid < ESP32_NPERIPHERALS);
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#ifdef CONFIG_SMP
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DEBUGASSERT(cpu >= 0 && cpu < CONFIG_SMP_NCPUS);
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if (cpu != 0)
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{
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regaddr = DPORT_APP_MAP_REGADDR(periphid);
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}
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else
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#endif
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{
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regaddr = DPORT_PRO_MAP_REGADDR(periphid);
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}
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putreg32(NO_CPUINT, regaddr);
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}
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