Xiang Xiao 96d1f018c4 build.yml: Switch avr-mips-riscv-x86-xtensa.dat to other.dat ...

Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>

2020-10-29 01:06:57 -07:00

..

workflows

build.yml: Switch avr-mips-riscv-x86-xtensa.dat to other.dat

2020-10-29 01:06:57 -07:00

gcc.json

Add problem matching for gcc and nxstyle to github actions

2020-06-11 00:52:55 +08:00

nxstyle.json

Add problem matching for gcc and nxstyle to github actions

2020-06-11 00:52:55 +08:00

PULL_REQUEST_TEMPLATE.md

Remove boilerplate from the PR template.

2020-04-26 23:09:09 +01:00