Huang Qi f93964ad3c riscv: Dump trap val in exception handler ...

Signed-off-by: Huang Qi <huangqi3@xiaomi.com>

2022-08-30 14:55:33 +08:00

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bl602

arch: Remove the inclusion of arch/irq.h from chip/irq.h

2022-07-04 13:03:47 +03:00

c906

arch: Remove the inclusion of arch/irq.h from chip/irq.h

2022-07-04 13:03:47 +03:00

esp32c3

arch: Remove the inclusion of arch/irq.h from chip/irq.h

2022-07-04 13:03:47 +03:00

fe310

arch: Remove the inclusion of arch/irq.h from chip/irq.h

2022-07-04 13:03:47 +03:00

k210

arch: Remove the inclusion of arch/irq.h from chip/irq.h

2022-07-04 13:03:47 +03:00

litex

arch: Remove the inclusion of arch/irq.h from chip/irq.h

2022-07-04 13:03:47 +03:00

mpfs

Remove executable permission from source and build files.

2022-08-04 12:48:18 -03:00

qemu-rv

arch: Remove the inclusion of arch/irq.h from chip/irq.h

2022-07-04 13:03:47 +03:00

rv32m1

arch: Remove the inclusion of arch/irq.h from chip/irq.h

2022-07-04 13:03:47 +03:00

.gitignore

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arch.h

arch/risc-v: Move __XSTR, FLOAD/FSTORE and REGLOAD/REGSTORE to the right place

2022-07-04 13:25:56 +03:00

barriers.h

RISC-V: Add common data memory and instruction barriers

2022-03-18 18:20:12 +08:00

csr.h

arch/riscv: Align the macro definition in csr.h

2022-04-02 14:08:37 +03:00

elf.h

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inttypes.h

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irq.h

arch/risc-v: Move __XSTR, FLOAD/FSTORE and REGLOAD/REGSTORE to the right place

2022-07-04 13:25:56 +03:00

limits.h

arch: Define WCHAR_[MIN|MAX] in arch/include/limits.h

2022-06-03 22:25:49 +03:00

mode.h

riscv: Dump trap val in exception handler

2022-08-30 14:55:33 +08:00

setjmp.h

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spinlock.h

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stdarg.h

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syscall.h

arch/risc-v: Move __XSTR, FLOAD/FSTORE and REGLOAD/REGSTORE to the right place

2022-07-04 13:25:56 +03:00

types.h

…