Dave Marples 681609ad51 arch/arm/src/imxrt/imxrt_enet.c: The board would not come up if I ran Nuttx from cold. I dumped the PHY registers to see what the differences were and the PHY was coming up in NANDTree mode. This is a mode for testing connectivity between the PHY and the MAC. Switching this mode off in the PHY registers has fixed the problem.

2018-09-25 06:52:07 -06:00

..

a1x

…

arm

…

armv6-m

…

armv7-a

…

armv7-m

…

armv7-r

…

bcm2708

…

c5471

…

common

…

dm320

…

efm32

…

imx1

…

imx6

…

imxrt

arch/arm/src/imxrt/imxrt_enet.c: The board would not come up if I ran Nuttx from cold. I dumped the PHY registers to see what the differences were and the PHY was coming up in NANDTree mode. This is a mode for testing connectivity between the PHY and the MAC. Switching this mode off in the PHY registers has fixed the problem.

2018-09-25 06:52:07 -06:00

kinetis

arch/arm/src: Correct all ARMv7-M architectures. Interrupts were not be disabled correctly on power up. Writing zero to the NVIC SET-ENABLE registers has no effect. In order to disable interrupts, it is necessary to write all ones to the NVIC CLEAR-ENABLE register. Noted by David Sidrane.

2018-09-21 21:32:50 -06:00

kl

…

lc823450

arch/arm/src: Correct all ARMv7-M architectures. Interrupts were not be disabled correctly on power up. Writing zero to the NVIC SET-ENABLE registers has no effect. In order to disable interrupts, it is necessary to write all ones to the NVIC CLEAR-ENABLE register. Noted by David Sidrane.

2018-09-21 21:32:50 -06:00

lpc11xx

…

lpc17xx

arch/arm/src: Correct all ARMv7-M architectures. Interrupts were not be disabled correctly on power up. Writing zero to the NVIC SET-ENABLE registers has no effect. In order to disable interrupts, it is necessary to write all ones to the NVIC CLEAR-ENABLE register. Noted by David Sidrane.

2018-09-21 21:32:50 -06:00

lpc31xx

…

lpc43xx

…

lpc54xx

…

lpc214x

…

lpc2378

…

moxart

…

nrf52

…

nuc1xx

…

sam34

arch/arm/src: Correct all ARMv7-M architectures. Interrupts were not be disabled correctly on power up. Writing zero to the NVIC SET-ENABLE registers has no effect. In order to disable interrupts, it is necessary to write all ones to the NVIC CLEAR-ENABLE register. Noted by David Sidrane.

2018-09-21 21:32:50 -06:00

sama5

…

samd2l2

…

samd5e5

arch/arm/src: Correct all ARMv7-M architectures. Interrupts were not be disabled correctly on power up. Writing zero to the NVIC SET-ENABLE registers has no effect. In order to disable interrupts, it is necessary to write all ones to the NVIC CLEAR-ENABLE register. Noted by David Sidrane.

2018-09-21 21:32:50 -06:00

samv7

arch/arm/src: Correct all ARMv7-M architectures. Interrupts were not be disabled correctly on power up. Writing zero to the NVIC SET-ENABLE registers has no effect. In order to disable interrupts, it is necessary to write all ones to the NVIC CLEAR-ENABLE register. Noted by David Sidrane.

2018-09-21 21:32:50 -06:00

stm32

…

stm32f0

…

stm32f7

arch/arm/src: Correct all ARMv7-M architectures. Interrupts were not be disabled correctly on power up. Writing zero to the NVIC SET-ENABLE registers has no effect. In order to disable interrupts, it is necessary to write all ones to the NVIC CLEAR-ENABLE register. Noted by David Sidrane.

2018-09-21 21:32:50 -06:00

stm32h7

arch/arm/src: Correct all ARMv7-M architectures. Interrupts were not be disabled correctly on power up. Writing zero to the NVIC SET-ENABLE registers has no effect. In order to disable interrupts, it is necessary to write all ones to the NVIC CLEAR-ENABLE register. Noted by David Sidrane.

2018-09-21 21:32:50 -06:00

stm32l4

…

str71x

…

tiva

arch/arm/src: Correct all ARMv7-M architectures. Interrupts were not be disabled correctly on power up. Writing zero to the NVIC SET-ENABLE registers has no effect. In order to disable interrupts, it is necessary to write all ones to the NVIC CLEAR-ENABLE register. Noted by David Sidrane.

2018-09-21 21:32:50 -06:00

tms570

…

xmc4

arch/arm/src: Correct all ARMv7-M architectures. Interrupts were not be disabled correctly on power up. Writing zero to the NVIC SET-ENABLE registers has no effect. In order to disable interrupts, it is necessary to write all ones to the NVIC CLEAR-ENABLE register. Noted by David Sidrane.

2018-09-21 21:32:50 -06:00

.gitignore

…

Makefile

…