Jukka Laitinen 6a5d00f68c arch/risc-v/src/mpfs: Add CFG_DDR_SGMII_PHY_RPC156 register setting for DDR training ...

Decreasing the value may increase DQ/DQS window size. Keep the default value
(1) for the existing board configurations.

Signed-off-by: Jukka Laitinen <jukkax@ssrc.tii.ae>

2023-08-17 17:50:37 +08:00

..

include

arch/risc-v: Add support for StarFive JH7110 SoC

2023-08-03 22:55:55 -07:00

src

arch/risc-v/src/mpfs: Add CFG_DDR_SGMII_PHY_RPC156 register setting for DDR training

2023-08-17 17:50:37 +08:00

Kconfig

arch/risc-v/litex: Add platform specific tickless implementation.

2023-08-16 16:59:27 +08:00