mirror of
https://github.com/apache/nuttx.git
synced 2026-06-02 01:21:26 +08:00
Huang Qi
e09048cc88
Correct duplicate "is is" word found in 181 files throughout the codebase. In most cases "is is" was changed to "is", but in contexts like "MCU is is sleep mode" it was corrected to "MCU in sleep mode". Also fixes a "the the" typo in net/inet/inet_sockif.c. This is a pure style/documentation fix that improves code readability. Signed-off-by: Huang Qi <huangqi3@xiaomi.com>
519 lines
19 KiB
C
519 lines
19 KiB
C
/****************************************************************************
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* boards/arm/stm32h7/nucleo-h743zi/include/board.h
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*
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* SPDX-License-Identifier: Apache-2.0
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_INCLUDE_BOARD_H
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#define __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_INCLUDE_BOARD_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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#ifndef __ASSEMBLY__
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# include <stdint.h>
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#endif
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/* Do not include STM32 H7 header files here */
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* Clocking *****************************************************************/
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/* The Nucleo-144 board provides the following clock sources:
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*
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* MCO: 8 MHz from MCO output of ST-LINK is used as input clock (default)
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* X2: 32.768 KHz crystal for LSE
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* X3: HSE crystal oscillator (not provided)
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*
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* So we have these clock source available within the STM32
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*
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* HSI: 16 MHz RC factory-trimmed
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* LSI: 32 KHz RC
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* HSE: 8 MHz from MCO output of ST-LINK
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* LSE: 32.768 kHz
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*/
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#define STM32_BOARD_XTAL 8000000ul /* ST-LINK MCO */
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#define STM32_HSI_FREQUENCY 16000000ul
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#define STM32_LSI_FREQUENCY 32000
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#define STM32_HSE_FREQUENCY STM32_BOARD_XTAL
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#define STM32_LSE_FREQUENCY 32768
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/* Main PLL Configuration.
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*
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* PLL source is HSE = 8,000,000
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*
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* To use HSE, configure the solder bridges on the board:
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*
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* - SB148, SB8 and SB9 OFF
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* - SB112 and SB149 ON
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*
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* When STM32_HSE_FREQUENCY / PLLM <= 2MHz VCOL must be selected.
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* VCOH otherwise.
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*
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* PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN
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* Subject to:
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*
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* 1 <= PLLM <= 63
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* 4 <= PLLN <= 512
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* 150 MHz <= PLL_VCOL <= 420MHz
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* 192 MHz <= PLL_VCOH <= 836MHz
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*
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* SYSCLK = PLL_VCO / PLLP
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* CPUCLK = SYSCLK / D1CPRE
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* Subject to
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*
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* PLLP1 = {2, 4, 6, 8, ..., 128}
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* PLLP2,3 = {2, 3, 4, ..., 128}
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* CPUCLK <= 400 MHz
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*/
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#define STM32_BOARD_USEHSE
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#define STM32_HSEBYP_ENABLE
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#define STM32_PLLCFG_PLLSRC RCC_PLLCKSELR_PLLSRC_HSE
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/* PLL1, wide 4 - 8 MHz input, enable DIVP, DIVQ, DIVR
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*
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* PLL1_VCO = (8,000,000 / 2) * 200 = 800 MHz
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*
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* PLL1P = PLL1_VCO/2 = 800 MHz / 2 = 400 MHz
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* PLL1Q = PLL1_VCO/4 = 800 MHz / 4 = 200 MHz
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* PLL1R = PLL1_VCO/8 = 800 MHz / 8 = 100 MHz
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*/
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#define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE | \
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RCC_PLLCFGR_PLL1RGE_4_8_MHZ | \
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RCC_PLLCFGR_DIVP1EN | \
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RCC_PLLCFGR_DIVQ1EN | \
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RCC_PLLCFGR_DIVR1EN)
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#define STM32_PLLCFG_PLL1M RCC_PLLCKSELR_DIVM1(2)
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#define STM32_PLLCFG_PLL1N RCC_PLL1DIVR_N1(200)
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#define STM32_PLLCFG_PLL1P RCC_PLL1DIVR_P1(2)
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#define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4)
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#define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(8)
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#define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 200)
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#define STM32_PLL1P_FREQUENCY (STM32_VCO1_FREQUENCY / 2)
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#define STM32_PLL1Q_FREQUENCY (STM32_VCO1_FREQUENCY / 4)
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#define STM32_PLL1R_FREQUENCY (STM32_VCO1_FREQUENCY / 8)
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/* PLL2 */
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#define STM32_PLLCFG_PLL2CFG (RCC_PLLCFGR_PLL2VCOSEL_WIDE | \
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RCC_PLLCFGR_PLL2RGE_4_8_MHZ | \
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RCC_PLLCFGR_DIVP2EN)
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#define STM32_PLLCFG_PLL2M RCC_PLLCKSELR_DIVM2(2)
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#define STM32_PLLCFG_PLL2N RCC_PLL2DIVR_N2(200)
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#define STM32_PLLCFG_PLL2P RCC_PLL2DIVR_P2(40)
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#define STM32_PLLCFG_PLL2Q 0
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#define STM32_PLLCFG_PLL2R 0
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#define STM32_VCO2_FREQUENCY ((STM32_HSE_FREQUENCY / 2) * 200)
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#define STM32_PLL2P_FREQUENCY (STM32_VCO2_FREQUENCY / 2)
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#define STM32_PLL2Q_FREQUENCY
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#define STM32_PLL2R_FREQUENCY
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/* PLL3 */
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#define STM32_PLLCFG_PLL3CFG 0
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#define STM32_PLLCFG_PLL3M 0
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#define STM32_PLLCFG_PLL3N 0
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#define STM32_PLLCFG_PLL3P 0
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#define STM32_PLLCFG_PLL3Q 0
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#define STM32_PLLCFG_PLL3R 0
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#define STM32_VCO3_FREQUENCY
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#define STM32_PLL3P_FREQUENCY
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#define STM32_PLL3Q_FREQUENCY
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#define STM32_PLL3R_FREQUENCY
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/* SYSCLK = PLL1P = 400 MHz
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* CPUCLK = SYSCLK / 1 = 400 MHz
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*/
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#define STM32_RCC_D1CFGR_D1CPRE (RCC_D1CFGR_D1CPRE_SYSCLK)
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#define STM32_SYSCLK_FREQUENCY (STM32_PLL1P_FREQUENCY)
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#define STM32_CPUCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 1)
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/* Configure Clock Assignments */
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/* AHB clock (HCLK) is SYSCLK/2 (200 MHz max)
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* HCLK1 = HCLK2 = HCLK3 = HCLK4
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*/
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#define STM32_RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_SYSCLKd2 /* HCLK = SYSCLK / 2 */
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#define STM32_ACLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 2) /* ACLK in D1, HCLK3 in D1 */
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#define STM32_HCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 2) /* HCLK in D2, HCLK4 in D3 */
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/* APB1 clock (PCLK1) is HCLK/4 (54 MHz) */
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#define STM32_RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */
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#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* APB2 clock (PCLK2) is HCLK/4 (54 MHz) */
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#define STM32_RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_HCLKd4 /* PCLK2 = HCLK / 4 */
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#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* APB3 clock (PCLK3) is HCLK/4 (54 MHz) */
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#define STM32_RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_HCLKd4 /* PCLK3 = HCLK / 4 */
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#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* APB4 clock (PCLK4) is HCLK/4 (54 MHz) */
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#define STM32_RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_HCLKd4 /* PCLK4 = HCLK / 4 */
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#define STM32_PCLK4_FREQUENCY (STM32_HCLK_FREQUENCY/4)
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/* Timer clock frequencies */
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/* Timers driven from APB1 will be twice PCLK1 */
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#define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM3_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM4_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM5_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM12_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM13_CLKIN (2*STM32_PCLK1_FREQUENCY)
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#define STM32_APB1_TIM14_CLKIN (2*STM32_PCLK1_FREQUENCY)
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/* Timers driven from APB2 will be twice PCLK2 */
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#define STM32_APB2_TIM1_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM8_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM15_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM16_CLKIN (2*STM32_PCLK2_FREQUENCY)
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#define STM32_APB2_TIM17_CLKIN (2*STM32_PCLK2_FREQUENCY)
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/* Kernel Clock Configuration
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*
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* Note: look at Table 54 in ST Manual
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*/
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/* I2C123 clock source - HSI */
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#define STM32_RCC_D2CCIP2R_I2C123SRC RCC_D2CCIP2R_I2C123SEL_HSI
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/* I2C4 clock source - HSI */
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#define STM32_RCC_D3CCIPR_I2C4SRC RCC_D3CCIPR_I2C4SEL_HSI
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/* SPI123 clock source - PLL1Q */
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#define STM32_RCC_D2CCIP1R_SPI123SRC RCC_D2CCIP1R_SPI123SEL_PLL1
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/* SPI45 clock source - APB (PCLK2?) */
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#define STM32_RCC_D2CCIP1R_SPI45SRC RCC_D2CCIP1R_SPI45SEL_APB
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/* SPI6 clock source - APB (PCLK4) */
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#define STM32_RCC_D3CCIPR_SPI6SRC RCC_D3CCIPR_SPI6SEL_PCLK4
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/* USB 1 and 2 clock source - HSI48 */
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#define STM32_RCC_D2CCIP2R_USBSRC RCC_D2CCIP2R_USBSEL_HSI48
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/* ADC 1 2 3 clock source - pll2_pclk */
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#define STM32_RCC_D3CCIPR_ADCSRC RCC_D3CCIPR_ADCSEL_PLL2
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/* FLASH wait states
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*
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* ------------ ---------- -----------
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* Vcore MAX ACLK WAIT STATES
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* ------------ ---------- -----------
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* 1.15-1.26 V 70 MHz 0
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* (VOS1 level) 140 MHz 1
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* 210 MHz 2
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* 1.05-1.15 V 55 MHz 0
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* (VOS2 level) 110 MHz 1
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* 165 MHz 2
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* 220 MHz 3
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* 0.95-1.05 V 45 MHz 0
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* (VOS3 level) 90 MHz 1
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* 135 MHz 2
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* 180 MHz 3
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* 225 MHz 4
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* ------------ ---------- -----------
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*/
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#define BOARD_FLASH_WAITSTATES 4
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/* SDMMC definitions ********************************************************/
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/* Init 400kHz, PLL1Q/(2*250) */
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#define STM32_SDMMC_INIT_CLKDIV (250 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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/* Just set these to 25 MHz for now,
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* PLL1Q/(2*4), for default speed 12.5MB/s
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*/
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#define STM32_SDMMC_MMCXFR_CLKDIV (4 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#define STM32_SDMMC_SDXFR_CLKDIV (4 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT)
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#define STM32_SDMMC_CLKCR_EDGE STM32_SDMMC_CLKCR_NEGEDGE
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/* Ethernet definitions *****************************************************/
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#define GPIO_ETH_RMII_TXD0 (GPIO_ETH_RMII_TXD0_2 | GPIO_SPEED_100MHz) /* PG13 */
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#define GPIO_ETH_RMII_TXD1 (GPIO_ETH_RMII_TXD1_1 | GPIO_SPEED_100MHz) /* PB13 */
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#define GPIO_ETH_RMII_TX_EN (GPIO_ETH_RMII_TX_EN_2 | GPIO_SPEED_100MHz) /* PG11 */
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#define GPIO_ETH_MDC (GPIO_ETH_MDC_0 | GPIO_SPEED_100MHz) /* PC1 */
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#define GPIO_ETH_MDIO (GPIO_ETH_MDIO_0 | GPIO_SPEED_100MHz) /* PA2 */
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#define GPIO_ETH_RMII_RXD0 (GPIO_ETH_RMII_RXD0_0 | GPIO_SPEED_100MHz) /* PC4 */
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#define GPIO_ETH_RMII_RXD1 (GPIO_ETH_RMII_RXD1_0 | GPIO_SPEED_100MHz) /* PC5 */
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#define GPIO_ETH_RMII_CRS_DV (GPIO_ETH_RMII_CRS_DV_0 | GPIO_SPEED_100MHz) /* PA7 */
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#define GPIO_ETH_RMII_REF_CLK (GPIO_ETH_RMII_REF_CLK_0 | GPIO_SPEED_100MHz) /* PA1 */
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/* LED definitions **********************************************************/
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/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED,
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* LD2 a Blue LED and LD3 a Red LED, that can be controlled by software.
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* The following definitions assume the default Solder Bridges are installed.
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*
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* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in
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* any way.
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* The following definitions are used to access individual LEDs.
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*/
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/* LED index values for use with board_userled() */
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#define BOARD_LED1 0
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#define BOARD_LED2 1
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#define BOARD_LED3 2
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#define BOARD_NLEDS 3
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#define BOARD_LED_GREEN BOARD_LED1
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#define BOARD_LED_BLUE BOARD_LED2
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#define BOARD_LED_RED BOARD_LED3
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/* LED bits for use with board_userled_all() */
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#define BOARD_LED1_BIT (1 << BOARD_LED1)
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#define BOARD_LED2_BIT (1 << BOARD_LED2)
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#define BOARD_LED3_BIT (1 << BOARD_LED3)
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/* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in
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* include/board.h and src/stm32_leds.c.
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* The LEDs are used to encode OS-related events as follows:
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*
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*
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* SYMBOL Meaning LED state
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* Red Green Blue
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* ---------------------- -------------------------- ------ ------ ---
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*/
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#define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */
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#define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */
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#define LED_IRQSENABLED 2 /* Interrupts enabled OFF ON OFF */
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#define LED_STACKCREATED 3 /* Idle stack created OFF ON ON */
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#define LED_INIRQ 4 /* In an interrupt N/C N/C GLOW */
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#define LED_SIGNAL 5 /* In a signal handler N/C GLOW N/C */
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#define LED_ASSERTION 6 /* An assertion failed GLOW N/C GLOW */
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#define LED_PANIC 7 /* The system has crashed Blink OFF N/C */
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#define LED_IDLE 8 /* MCU is in sleep mode ON OFF OFF */
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/* Thus if the Green LED is statically on, NuttX has successfully booted and
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* is, apparently, running normally. If the Red LED is flashing at
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* approximately 2Hz, then a fatal error has been detected and the system
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* has halted.
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*/
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/* Button definitions *******************************************************/
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/* The NUCLEO board supports one button: Pushbutton B1, labeled "User", is
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* connected to GPIO PI11.
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* A high value will be sensed when the button is depressed.
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*/
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#define BUTTON_USER 0
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#define NUM_BUTTONS 1
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#define BUTTON_USER_BIT (1 << BUTTON_USER)
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/* Alternate function pin selections ****************************************/
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/* ADC */
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#define GPIO_ADC12_INP5 GPIO_ADC12_INP5_0 /* PB1, channel 5 */
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#define GPIO_ADC123_INP10 GPIO_ADC123_INP10_0 /* PC0, channel 10 */
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#define GPIO_ADC123_INP12 GPIO_ADC123_INP12_0 /* PC2, channel 12 */
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#define GPIO_ADC12_INP13 GPIO_ADC12_INP13_0 /* PC3, channel 13 */
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#define GPIO_ADC12_INP15 GPIO_ADC12_INP15_0 /* PA3, channel 15 */
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#define GPIO_ADC12_INP18 GPIO_ADC12_INP18_0 /* PA4, channel 18 */
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#define GPIO_ADC12_INP19 GPIO_ADC12_INP19_0 /* PA5, channel 19 */
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#define GPIO_ADC123_INP7 GPIO_ADC12_INP7_0 /* PA7, channel 7 */
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#define GPIO_ADC123_INP11 GPIO_ADC123_INP11_0 /* PC1, channel 11 */
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#define GPIO_ADC2_INP2 GPIO_ADC2_INP2_0 /* PF13, channel 2 */
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#define GPIO_ADC12_INP3 GPIO_ADC12_INP3_0 /* PA6, channel 3 */
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#define GPIO_ADC12_INP14 GPIO_ADC12_INP14_0 /* PA2, channel 14 */
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#define GPIO_ADC12_INP4 GPIO_ADC12_INP4_0 /* PC4, channel 4 */
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#define GPIO_ADC12_INP8 GPIO_ADC12_INP8_0 /* PC5, channel 8 */
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/* USART3 (Nucleo Virtual Console) */
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#define GPIO_USART3_RX (GPIO_USART3_RX_3 | GPIO_SPEED_100MHz) /* PD9 */
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#define GPIO_USART3_TX (GPIO_USART3_TX_3 | GPIO_SPEED_100MHz) /* PD8 */
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#define DMAMAP_USART3_RX DMAMAP_DMA12_USART3RX_0
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#define DMAMAP_USART3_TX DMAMAP_DMA12_USART3TX_1
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/* USART6 (Arduino Serial Shield) */
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#define GPIO_USART6_RX (GPIO_USART6_RX_2 | GPIO_SPEED_100MHz) /* PG9 */
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#define GPIO_USART6_TX (GPIO_USART6_TX_2 | GPIO_SPEED_100MHz) /* PG14 */
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/* I2C1 Use Nucleo I2C1 pins */
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#define GPIO_I2C1_SCL (GPIO_I2C1_SCL_2 | GPIO_SPEED_50MHz) /* PB8 - D15 */
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#define GPIO_I2C1_SDA (GPIO_I2C1_SDA_2 | GPIO_SPEED_50MHz) /* PB9 - D14 */
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/* I2C2 Use Nucleo I2C2 pins */
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#define GPIO_I2C2_SCL (GPIO_I2C2_SCL_2 | GPIO_SPEED_50MHz) /* PF1 - D69 */
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#define GPIO_I2C2_SDA (GPIO_I2C2_SDA_2 | GPIO_SPEED_50MHz) /* PF0 - D68 */
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#define GPIO_I2C2_SMBA (GPIO_I2C2_SMBA_2 | GPIO_SPEED_50MHz) /* PF2 - D70 */
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/* SPI3 */
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#define GPIO_SPI3_MISO (GPIO_SPI3_MISO_1 | GPIO_SPEED_50MHz) /* PB4 */
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#define GPIO_SPI3_MOSI (GPIO_SPI3_MOSI_4 | GPIO_SPEED_50MHz) /* PB5 */
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#define GPIO_SPI3_SCK (GPIO_SPI3_SCK_1 | GPIO_SPEED_50MHz) /* PB3 */
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#define GPIO_SPI3_NSS (GPIO_SPI3_NSS_2 | GPIO_SPEED_50MHz) /* PA4 */
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/* TIM1 - Advanced Timer 16-bit (4 channels) */
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#define GPIO_TIM1_CH1IN (GPIO_TIM1_CH1IN_2) /* PE9 */
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#define GPIO_TIM1_CH2IN (GPIO_TIM1_CH2IN_2) /* PE11 */
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#define GPIO_TIM1_CH3IN (GPIO_TIM1_CH3IN_2) /* PE13 */
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#define GPIO_TIM1_CH4IN (GPIO_TIM1_CH4IN_2) /* PE14 */
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#define GPIO_TIM1_CH1OUT (GPIO_TIM1_CH1OUT_2) /* PE9 - D6 */
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#define GPIO_TIM1_CH1NOUT (GPIO_TIM1_CH1NOUT_3) /* PE8 - D42 */
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#define GPIO_TIM1_CH2OUT (GPIO_TIM1_CH2OUT_2) /* PE11 - D5 */
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#define GPIO_TIM1_CH2NOUT (GPIO_TIM1_CH2NOUT_3) /* PE10 - D40 */
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#define GPIO_TIM1_CH3OUT (GPIO_TIM1_CH3OUT_2) /* PE13 - D3 */
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#define GPIO_TIM1_CH3NOUT (GPIO_TIM1_CH3NOUT_3) /* PE12 - D39 */
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#define GPIO_TIM1_CH4OUT (GPIO_TIM1_CH4OUT_2) /* PE14 - D38 */
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/* TIM2 - General Purpose 32-bit Timer (4 channels) */
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#define GPIO_TIM2_CH1IN (GPIO_TIM2_CH1IN_2) /* PA15 */
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#define GPIO_TIM2_CH2IN (GPIO_TIM2_CH2IN_1) /* PB3 */
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#define GPIO_TIM2_CH3IN (GPIO_TIM2_CH3IN_1) /* PB10 */
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#define GPIO_TIM2_CH4IN (GPIO_TIM2_CH4IN_1) /* PB11 */
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/* TIM3 - General Purpose 16-bit Timer (4 channels) */
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#define GPIO_TIM3_CH1IN (GPIO_TIM3_CH1IN_1) /* PA6 */
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#define GPIO_TIM3_CH2IN (GPIO_TIM3_CH2IN_1) /* PA7 */
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#define GPIO_TIM3_CH3IN (GPIO_TIM3_CH3IN_1) /* PB0 */
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#define GPIO_TIM3_CH4IN (GPIO_TIM3_CH4IN_1) /* PB1 */
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/* TIM4 - General Purpose 16-bit Timer (4 channels) */
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#define GPIO_TIM4_CH1IN (GPIO_TIM4_CH1IN_2) /* PD12 */
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#define GPIO_TIM4_CH2IN (GPIO_TIM4_CH2IN_2) /* PD13 */
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#define GPIO_TIM4_CH3IN (GPIO_TIM4_CH3IN_2) /* PD14 */
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#define GPIO_TIM4_CH4IN (GPIO_TIM4_CH4IN_2) /* PD15 */
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/* TIM5 - General Purpose 32-bit Timer (4 channels) */
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#define GPIO_TIM5_CH1IN (GPIO_TIM5_CH1IN_2)
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#define GPIO_TIM5_CH2IN (GPIO_TIM5_CH2IN_2)
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#define GPIO_TIM5_CH3IN (GPIO_TIM5_CH3IN_2)
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#define GPIO_TIM5_CH4IN (GPIO_TIM5_CH4IN_2)
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/* TIM6 - Basic 16-bit Timer (0 channels) */
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/* TIM7 - Basic 16-bit Timer (0 channels) */
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/* TIM8 - Advanced 16-bit Timer (4 channels) */
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#define GPIO_TIM8_CH1IN (GPIO_TIM8_CH1IN_1)
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#define GPIO_TIM8_CH2IN (GPIO_TIM8_CH2IN_1)
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#define GPIO_TIM8_CH3IN (GPIO_TIM8_CH3IN_1)
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#define GPIO_TIM8_CH4IN (GPIO_TIM8_CH4IN_1)
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/* TIM12 - General purpose 16-bit Timer (2 channels) */
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#define GPIO_TIM12_CH1IN (GPIO_TIM12_CH1IN_1)
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#define GPIO_TIM12_CH2IN (GPIO_TIM12_CH2IN_1)
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/* TIM13 - General purpose 16-bit Timer (1 channels) */
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#define GPIO_TIM13_CH1IN (GPIO_TIM13_CH1IN_1)
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/* TIM14 - General purpose 16-bit Timer (1 channels) */
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#define GPIO_TIM14_CH1IN (GPIO_TIM14_CH1IN_1)
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/* TIM15 - General purpose 16-bit Timer (2 channels) */
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#define GPIO_TIM15_CH1IN (GPIO_TIM15_CH1IN_1)
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#define GPIO_TIM15_CH2IN (GPIO_TIM15_CH2IN_1)
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/* TIM16 - General purpose 16-bit Timer (1 channels) */
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#define GPIO_TIM16_CH1IN (GPIO_TIM16_CH1IN_1)
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/* TIM17 - General purpose 16-bit Timer (1 channels) */
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#define GPIO_TIM17_CH1IN (GPIO_TIM17_CH1IN_1)
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/* OTGFS */
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#define GPIO_OTGFS_DM (GPIO_OTGFS_DM_0 | GPIO_SPEED_100MHz)
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#define GPIO_OTGFS_DP (GPIO_OTGFS_DP_0 | GPIO_SPEED_100MHz)
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#define GPIO_OTGFS_ID (GPIO_OTGFS_ID_0 | GPIO_SPEED_100MHz)
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/* DMA **********************************************************************/
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#define DMAMAP_SPI3_RX DMAMAP_DMA12_SPI3RX_0 /* DMA1 */
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#define DMAMAP_SPI3_TX DMAMAP_DMA12_SPI3TX_0 /* DMA1 */
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#define DMAMAP_USART6_RX DMAMAP_DMA12_USART6RX_1
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#define DMAMAP_USART6_TX DMAMAP_DMA12_USART6TX_0
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/****************************************************************************
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* Public Data
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****************************************************************************/
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#ifndef __ASSEMBLY__
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#undef EXTERN
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#if defined(__cplusplus)
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#define EXTERN extern "C"
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extern "C"
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{
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#else
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#define EXTERN extern
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#endif
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/****************************************************************************
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* Public Function Prototypes
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****************************************************************************/
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#undef EXTERN
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#if defined(__cplusplus)
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}
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#endif
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#endif /* __ASSEMBLY__ */
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#endif /* __BOARDS_ARM_STM32H7_NUCLEO_H743ZI_INCLUDE_BOARD_H */
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