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https://github.com/apache/nuttx.git
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Peter van der Perk
79ce1647da
Adds support to select irq line 1 to share the same GPIO with Linux Also added GPIO5 definiton for IRQ Signed-off-by: Peter van der Perk <peter.vanderperk@nxp.com>
53 lines
2.2 KiB
C
53 lines
2.2 KiB
C
/****************************************************************************
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* arch/arm/include/imx9/chip.h
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*
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* SPDX-License-Identifier: Apache-2.0
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* SPDX-FileCopyrightText: 2024 NXP
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*
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* Licensed to the Apache Software Foundation (ASF) under one or more
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* contributor license agreements. See the NOTICE file distributed with
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* this work for additional information regarding copyright ownership. The
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* ASF licenses this file to you under the Apache License, Version 2.0 (the
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* "License"); you may not use this file except in compliance with the
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* License. You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS, WITHOUT
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* WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the
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* License for the specific language governing permissions and limitations
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* under the License.
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*
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****************************************************************************/
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#ifndef __ARCH_ARM_INCLUDE_IMX9_CHIP_H
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#define __ARCH_ARM_INCLUDE_IMX9_CHIP_H
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/****************************************************************************
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* Included Files
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****************************************************************************/
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#include <nuttx/config.h>
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/****************************************************************************
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* Pre-processor Definitions
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****************************************************************************/
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/* NVIC priority levels *****************************************************/
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/* Each priority field holds an 8-bit priority value, 0-15. The lower the
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* value, the greater the priority of the corresponding interrupt. The i.MX
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* RT processor implements only bits[7:4] of each field, bits[3:0] read as
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* zero and ignore writes.
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*/
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#define NVIC_SYSH_PRIORITY_MIN 0xf0 /* All bits[7:4] set is min pri */
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#define NVIC_SYSH_PRIORITY_DEFAULT 0x80 /* Midpoint is the default */
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#define NVIC_SYSH_PRIORITY_MAX 0x00 /* Zero is maximum priority */
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#define NVIC_SYSH_PRIORITY_STEP 0x40 /* Two bits of interrupt pri used */
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#define IMX9_GPIO_NPORTS 5
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#endif /* __ARCH_ARM_INCLUDE_IMX9_CHIP_H */
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