prepare for 0.2.6 release

git-svn-id: svn://svn.code.sf.net/p/nuttx/code/trunk@255 42af7a65-404d-4744-a932-0658087f49c3

ChangeLog

@@ -121,6 +121,34 @@
 	  arch/c5471 and arch/dm320 are deprecated and will be removed
 	  when the new c5471 and dm320 logic is verified.
 
-0.2.5 2007-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
+0.2.5 2007-05-19 Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* Corrected some build/configuration issues introduced with the
+	  last release.
+	* Added support for the NXP 214x processor on the mcu123.com lpc214x
+	  development board (untested)
+	* Added support for block devices.
+	* Simulated target now exports a VFAT filesystem
+	* Begin support for VFAT filesystem (missing functionalit)
+	* Added mount() and umount()
+	* Fix bug in memcmp return value
+	* Fix errors in timeslice calculation (several places)
+	* Added missing irqrestore() in timer_deletall().
+	* close() was not closing the underlying device.
+	* Added fsync()
+	* Added strspn() and strcspn()
+
+0.2.6 2007-05-26 Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* Added unlink(), mkdir(), rmdir(), and rename()
+	* Fixed several serious FAT errors with oflags handling (&& instead of &)
+	* Added FAT support for unlink(), mkdir(), rmdir(), and rename
+	* Added FAT support for opendir(), closedir(), readdir(), seekdir(),
+	  telldir(), rewindir().
+	* Fixed ARM compilation errors introduced in 0.2.5 (that is what I get
+	  for only testing on the simulation).
+
+0.2.7 2007-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
 
 	* Started m68322
+

Documentation/NuttX.html

@@ -8,7 +8,7 @@
   <tr align="center" bgcolor="#e4e4e4">
     <td>
       <h1><big><font color="#3c34ec"><i>NuttX RTOS</i></font></big></h1>
-      <p>Last Updated: March 28, 2007</p>
+      <p>Last Updated: May 26, 2007</p>
     </td>
   </tr>
 </table>
@@ -97,10 +97,13 @@
   <td>
     <p>
       The goal is to provide most standard POSIX OS interfaces to support
-      a rich multi-threaded development environment.
+      a rich, multi-threaded development environment for deeply embedded
+      processors.
     </p>
-      NON-GOALS: (1) It is not a goal to provide OS subsystems such
+      NON-GOALS: (1) It is not a goal to provide the rich level of OS
-      as network or USB (but these could obviously be added).
+      features like those provided with Linux.
+      Small footprint is more important than features.
+      Standard compliance is more important than small footprint.
       (2) There is no MMU-based support for processes.
       At present, NuttX assumes a flat address space.
     </p>
@@ -180,9 +183,12 @@
 </table>
 
 <p>
-   The seventh release of NuttX (nuttx-0.2.4) is available for download
+   The 9th release of NuttX (nuttx-0.2.6) is available for download
    from the <a href="http://sourceforge.net/project/showfiles.php?group_id=189573">SourceForge</a>
    website.
+   The change log associated with the release is available <a href="#currentrelease">here</a>.
+   Unreleased changes after this release are avalable in CVS.
+   These unreleased changes are listed <a href="#pendingchanges">here</a>.
 </p>
 
 <table width ="100%">
@@ -234,6 +240,21 @@
     </p>
    </td>
 </tr>
+<tr>
+  <td><br></td>
+  <td>
+    <p>
+      <b>NXP LPC214x</b>.
+      Support is provided for the NXP LPC214x family of processors.  In particular,
+      support is provided for the mcu123.com lpc214x evaluation board (LPC2148).
+      This port also used the GNU arm-eld toolchain*.
+    </p>
+    <p>
+      <b>STATUS:</b>
+        This port is in progress and should be available in the nuttx-0.2.7 release.
+    </p>
+  </td>
+</tr>
 <tr>
   <td valign="top"><img src="favicon.ico"></td>
   <td bgcolor="#5eaee1">
@@ -358,6 +379,35 @@ Other memory:
   </tr>
 </table>
 
+<center><table width ="80%">
+<tr>
+  <td><img src="favicon.ico"></td>
+   <td>
+      <a href="#olderreleases">Change Logs for Older Releases</a><br>
+   </td>
+</tr>
+<tr>
+  <td><img src="favicon.ico"></td>
+   <td>
+      <a href="#currentrelease">ChangeLog for Current Release</a><br>
+   </td>
+</tr>
+<tr>
+  <td><img src="favicon.ico"></td>
+   <td>
+      <a href="#pendingchanges">Unreleased Changes</a>
+   </td>
+</tr>
+</table></center>
+
+<table width ="100%">
+  <tr bgcolor="#e4e4e4">
+  <td>
+    <a name="olderreleases>Change Logs for Older Releases</a>
+  </td>
+  </tr>
+</table>
+
 <ul><pre>
 0.1.0 2007-03-09  Gregory Nutt <spudmonkey@racsa.co.cr>
 
@@ -482,7 +532,55 @@ Other memory:
 	  arch/c5471 and arch/dm320 are deprecated and will be removed
 	  when the new c5471 and dm320 logic is verified.
 
-0.2.5 2007-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
+0.2.5 2007-05-19 Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* Corrected some build/configuration issues introduced with the
+	  last release.
+	* Added support for the NXP 214x processor on the mcu123.com lpc214x
+	  development board (untested)
+	* Added support for block devices.
+	* Simulated target now exports a VFAT filesystem
+	* Begin support for VFAT filesystem (missing functionalit)
+	* Added mount() and umount()
+	* Fix bug in memcmp return value
+	* Fix errors in timeslice calculation (several places)
+	* Added missing irqrestore() in timer_deletall().
+	* close() was not closing the underlying device.
+	* Added fsync()
+	* Added strspn() and strcspn()
+</pre></ul>
+
+<table width ="100%">
+  <tr bgcolor="#e4e4e4">
+  <td>
+    <a name="currentrelease">ChangeLog for Current Release</a>
+  </td>
+  </tr>
+</table>
+
+<pre><ul>
+0.2.6 2007-05-26 Gregory Nutt <spudmonkey@racsa.co.cr>
+
+	* Added unlink(), mkdir(), rmdir(), and rename()
+	* Fixed several serious FAT errors with oflags handling (&& instead of &)
+	* Added FAT support for unlink(), mkdir(), rmdir(), and rename
+	* Added FAT support for opendir(), closedir(), readdir(), seekdir(),
+	  telldir(), rewindir().
+	* Fixed ARM compilation errors introduced in 0.2.5 (that is what I get
+	  for only testing on the simulation).
+</pre></ul>
+
+<table width ="100%">
+  <tr bgcolor="#e4e4e4">
+  <td>
+    <a name="pendingchanges">Unreleased Changes</a>
+  </td>
+  </tr>
+</table>
+
+<pre><ul>
+
+0.2.7 2007-xx-xx Gregory Nutt <spudmonkey@racsa.co.cr>
 
 	* Started m68322
 </pre></ul>

Documentation/NuttxPortingGuide.html

@@ -16,21 +16,21 @@
   </b></big>
   <p><small>by</small></p>
   <p>Gregory Nutt</p>
-  <p><small>Last Update: April 30, 2007</small></p>
+  <p><small>Last Update: May 26, 2007</small></p>
 </center>
 
 <center><h1>Table of Contents</h1></center>
-<li>1.0 <a href="#Introduction">1.0 Introduction</a></li>
+<li><a href="#Introduction">1.0 Introduction</a></li>
-<li>2.0 <a href="#DirectoryStructure">Directory Structure</a></li>
+<li><a href="#DirectoryStructure">2.0 Directory Structure</a></li>
 <ul>
-  <li>2.1 <a href="#DirStructDocumentation">Documentation</a></li>
+  <li><a href="#DirStructDocumentation">2.1 Documentation</a></li>
-  <l1>2.2 <a href="#DirStructArch">arch</a></li>
+  <l1><a href="#DirStructArch">2.2 arch/</a></li>
   <ul>
     <li><a href="#archdirectorystructure">2.2.1 Subdirectory Structure</a></li>
     <li><a href="#summaryofarchfiles">2.2.2 Summary of Files</a></li>
     <li><a href="#supportedarchitectures">2.2.3 Supported Architectures</a></li>
   </ul>
-  <li>2.3 <a href="#DirStructConfigs">configs/</a></li>
+  <li><a href="#DirStructConfigs">2.3 configs/</a></li>
   <ul>
     <li><a href="#configsdirectorystructure">2.3.1 Subdirectory Structure</a></li>
     <li><a href="#summaryofconfigfiles">2.3.2 Summary of Files</a></li>
@@ -40,22 +40,22 @@
     </ul>
     <li><a href="#supportedboards">2.3.3 Supported Boards</a></li>
   </ul>
-  <li>2.4 <a href="#DirStructDrivers">drivers</a></li>
+  <li><a href="#DirStructDrivers">2.4 drivers/</a></li>
-  <li>2.5 <a href="#DirStructExamples">examples</a></li>
+  <li><a href="#DirStructExamples">2.5 examples/</a></li>
-  <li>2.6 <a href="#DirStructFs">fs</a></li>
+  <li><a href="#DirStructFs">2.6 fs/</a></li>
-  <li>2.7 <a href="#DirStructInclude">include</a></li>
+  <li><a href="#DirStructInclude">2.7 include/</a></li>
-  <li>2.8 <a href="#DirStructLib">lib</a></li>
+  <li><a href="#DirStructLib">2.8 lib/</a></li>
-  <li>2.9 <a href="#DirStructMm">mm</a></li>
+  <li><a href="#DirStructMm">2.9 mm/</a></li>
-  <li>2.10 <a href="#DirStructSched">sched</a></li>
+  <li><a href="#DirStructSched">2.10 sched/</a></li>
-  <li>2.11 <a href="#DirStructTools">tools</a></li>
+  <li><a href="#DirStructTools">2.11 tools/</a></li>
-  <li>2.12 <a href="#topmakefile">Makefile</a></li>
+  <li><a href="#topmakefile">2.12 Makefile</a></li>
 </ul>
-<li>3.0 <a href="#configandbuild">Configuring and Building</a></li>
+<li><a href="#configandbuild">3.0 Configuring and Building</a></li>
 <ul>
   <li><a href="#configuringnuttx">3.1 Configuring NuttX</a></li>
   <li><a href="#buildingnuttx">3.2 Building NuttX</a></li>
 </ul>
-<li>4.0 <a href="#ArchAPIs">Architecture APIs</a></li>
+<li><a href="#ArchAPIs">4.0 Architecture APIs</a></li>
 <ul>
   <li><a href="#imports">4.1 APIs Exported by Architecture-Specific Logic to NuttX</a></li>
   <ul>
@@ -86,6 +86,7 @@
     <li><a href="#irqdispatch">4.2.4 <code>irq_dispatch()</code></a></li>
   </ul>
 </ul>
+<li><a href="#apndxconfigs">Appendix A: NuttX Configuration Settings</a></li>
 
 <hr>
 <h1>1.0 <a name="Introduction">Introduction</a></h1>
@@ -361,6 +362,14 @@
         NuttX operates on the ARM9EJS of this dual core processor.
         This port complete, verified, and included in the NuttX release 0.2.1.
       </li>
+
+      <li><code>arch/arm/include/lpc214x</code> and <code>arch/arm/src/lpc214x</code>:
+        These directories provide support for NXP LPC214x family of
+        processors.
+        STATUS: This port is in progress and should be available in the
+        nuttx-0.2.5 release.
+      </li>
+
     </ul>
   </li>
 
@@ -505,18 +514,24 @@
     A user-mode port of NuttX to the x86 Linux platform is available.
     The purpose of this port is primarily to support OS feature developement.
     This port does not support interrupts or a real timer (and hence no
-    round robin scheduler)  Otherwise, it is complete.</li>
+    round robin scheduler)  Otherwise, it is complete.
+  </li>
 
   <li><code>configs/c5471evm</code>:
     This is a port to the Spectrum Digital C5471 evaluation board.  The
     C5471 is a dual core processor from TI with an ARM7TDMI general purpose
     processor and a c54 SDP.  NuttX runs on the ARM core and is built with
     with a GNU arm-elf toolchain*. This port is complete, verified, and
-    included in the NuttX release.</li>
+    included in the NuttX release.
+  </li>
 
   <li><code>configs/mcu123-lpc214x</code>:
-    This is a port to the mcu123.com lpc214x development board.
+    This port is for the NXP LPC2148 as provided on the mcu123.com
-    This OS is also built with the arm-elf toolchain*.</li>
+    lpc214x development board.
+    This OS is also built with the arm-elf toolchain*.
+    STATUS: This port is in progress and should be available in the
+    nuttx-0.2.5 release.
+  </li>
 
   <li><code>configs/ntosd-dm320</code>:
     This port uses the Neuros OSD with a GNU arm-elf toolchain*.
@@ -524,15 +539,18 @@
     for futher information.
     NuttX operates on the ARM9EJS of this dual core processor.
     STATUS: This port is code complete, verified, and included in the
-    NuttX 0.2.1 release.</li>
+    NuttX 0.2.1 release.
+  </li>
 
   <li><code>configs/m68322evb</code>:
     This is a work in progress for the venerable m68322evb board from
-    Motorola.</li>
+    Motorola.
+  </li>
 
   <li><code>configs/pjrc-8051</code>:
     8051 Microcontroller.  This port uses the PJRC 87C52 development system
-    and the SDCC toolchain.   This port is not quite ready for prime time.</li>
+    and the SDCC toolchain.   This port is not quite ready for prime time.
+  </li>
 </ul>
 
 <p><small><blockquote>
@@ -1106,6 +1124,8 @@ The system can be re-made subsequently by just typing <code>make</code>.
      the particular chip or SoC.</li>
   <li><code>CONFIG_ARCH_BOARD_name</code>:
      For use in C code</li>
+  <li><code>CONFIG_ENDIAN_BIG</code>:
+     Define if big endian (default is little endian).</li>
 </ul>
 
 <p>
@@ -1191,8 +1211,9 @@ The system can be re-made subsequently by just typing <code>make</code>.
 </ul>
 
 <ul>
-    <code>CONFIG_DISABLE_CLOCK</code>, <code>CONFI_DISABLE_POSIX_TIMERS</code>, <code>CONFIG_DISABLE_PTHREAD</code>,
+    <code>CONFIG_DISABLE_CLOCK</code>, <code>CONFI_DISABLE_POSIX_TIMERS</code>,
-    <code>CONFIG_DISABLE_SIGNALS</code>, <code>CONFIG_DISABLE_MQUEUE</code>,
+    <code>CONFIG_DISABLE_PTHREAD</code>, <code>CONFIG_DISABLE_SIGNALS</code>,
+    <code>CONFIG_DISABLE_MQUEUE</code>, <code>CONFIG_DISABLE_MOUNTPOUNT</code>
 </ul>
 
 <h2>Miscellaneous libc settings</h2>

Makefile

@@ -63,10 +63,10 @@ include/nuttx/config.h: $(TOPDIR)/.config tools/mkconfig
 
 # link the arch/<arch-name>/include dir to include/arch
 include/arch: Make.defs
-	@if [ -e include/arch ]; then \
+	@if [ -h include/arch ]; then \
-		if [ -h include/arch ]; then \
+		rm -f include/arch ; \
-			rm -f include/arch ; \
+	else \
-		else \
+		if [ -e include/arch ]; then \
 			echo "include/arch exists but is not a symbolic link" ; \
 			exit 1 ; \
 		fi ; \
@@ -75,10 +75,10 @@ include/arch: Make.defs
 
 # Link the configs/<board-name>/include dir to include/arch/board
 include/arch/board: Make.defs include/arch
-	@if [ -e include/arch/board ]; then \
+	@if [ -h include/arch/board ]; then \
-		if [ -h include/arch/board ]; then \
 			rm -f include/arch/board ; \
-		else \
+	else \
+		if [ -e include/arch/board ]; then \
 			echo "include/arch/board exists but is not a symbolic link" ; \
 			exit 1 ; \
 		fi ; \

ReleaseNotes

@@ -1,20 +1,15 @@
-nuttx-0.2.4
+nuttx-0.2.6
-^^^^^^^^^^^^
+^^^^^^^^^^^
 
-This is the 7th release of NuttX.  This release is only to roll out
+This is the 9th release of NuttX.  This is primarily a bugfix release
-build changes to better support different SoC's that use the same
+to correct a number of problems introduced with the 0.2.5 release. This release
-processor architecture.  In particular, the two existing ARM architectures,
+does include some FAT filesystem extensions including unlink(), mkdir(),
-c5471 and DM320 were combined into a single ARM directory.  This was done
+rmdir(), rename(), opendir(), closedir(), readdir(), seekdir(),  telldir(),
-in preparation for an LPC2148 port that is currently in progress.  There
+rewindir().  There are some pending FAT changes that did not make it into
-is NO new functionality or significant bufixes in this release.
+this release including stat(), truncate(), and long file names.
 
 See the ChangeLog for a complete list of changes.
 
-This release has been verified on the Linux user-mode platform
+This release has been verified only on the Linux user-mode platform.
-and the Neuros OSD using the test program under examples/ostest.
-The results of the testing is available in the source tree under
-configs/ntosd-dm320/doc/test-results and under configs/sim/doc/test-results.
-There are no known, critical defects but the project development status
-remains at 'beta' status pending further test and evaluation.
 
-This tarball contains a complete CVS snapshot from April 28, 2007.
+This tarball contains a complete CVS snapshot from May 26, 2007.

TODO

@@ -18,6 +18,10 @@ o Task/Scheduler
 o Memory Managment
 - Add an option to free all memory allocated by a task when the task exits.
   This is probably not be worth the overhead for a deeply embedded system.
+- Current logic adapts size_t for 16-bit address machines vs. 32-bit address
+  machines.  But a small memory option should also be provided so that
+  the small offset option can be used with 32-bit machines that have small
+  RAM memories (like the lpc2148)
 
 o Signals
 - 'Standard' signals and signal actions are not supported.
@@ -31,9 +35,11 @@ o Network
 o USB
 
 o Libraries
+- sscanf() and lib_vsprintf() do not support floating point values.
 
 o File system
-- Add some concept like mount points to handle mounted "real" filesystems.
+- Add disk usage stats, stat(), chmod(), truncate().
+- FAT32: long file names
 
 o Console Output
 
@@ -42,12 +48,12 @@ o Documentation
 - Document C-library APIs
 
 o Build system
-- Names under arch are incorrect.  These should hold processor architectures.
+- Some names under arch are still incorrect.  These should be processor architecture
-  c5471 and dm320 should be arm
+  names:  pjrc-8051 should be 805x
-  pjrc-8051 should be 805x
-- SoC-specific logic should be in subdirectories under arch/<processor-name>.
-  Eg. arm/include/c5471 should hold c5471 specific header files
 - configs/pjrc-8051 should be configs/pjrc-87c52
+- Last change to create the arch/arm directory breaks dependencies in arch/arm/src.
+  Probably need to add the path to the chip or common subdirectorys when
+  running tools/mkdeps.sh
 
 o Applications & Tests
 
@@ -55,6 +61,9 @@ o C5471
 
 o DM320
 
+o LPC214x
+- Finish
+
 o pjrc-8052 / MCS51
 - Current status:
   - Basic OS task management seems OK

arch/README.txt

@@ -146,8 +146,15 @@ arch/arm
         NuttX operates on the ARM9EJS of this dual core processor.  This port
         complete, verified, and included in the NuttX release 0.2.1.
 
+    arch/arm/include/lpc214x and arch/arm/src/lpc214x
+        These directories provide support for NXP LPC214x family of
+        processors.
+        STATUS: This port is in progress and should be available in the
+        nuttx-0.2.5 release.
+
 arch/m68322
     A work in progress.
+    STATUS:  Stalled for the moment.
 
 arch/pjrc-8051
     8051 Microcontroller.  This port is not quite ready for prime time.

arch/arm/include/lpc214x/irq.h

@@ -0,0 +1,126 @@
+/****************************************************************************
+ * arch/lpc214x/irq.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/* This file should never be included directed but, rather,
+ * only indirectly through nuttx/irq.h
+ */
+
+#ifndef __ARCH_LPC214X_IRQ_H
+#define __ARCH_LPC214X_IRQ_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/* LPC214X Interrupts */
+
+#define LPC214X_WDT_IRQ        0 /* Watchdog */
+#define LPC214X_RESERVED_IRQ   1 /* SWI only */
+#define LPC214X_DBGCOMMRX_IRQ  2 /* Embedded debug */
+#define LPC214X_DBGCOMMTX_IRQ  3 /* Embedded debug */
+#define LPC214X_TIMER0_IRQ     4 /* Timer 0 */
+#define LPC214X_TIMER1_IRQ     5 /* Timer 1 */
+#define LPC214X_UART0_IRQ      6 /* UART 0 */
+#define LPC214X_UART1_IRQ      7 /* UART 1 */
+#define LPC214X_PWM0_IRQ       8 /* PWM 0 */
+#define LPC214X_I2C0_IRQ       9 /* I2C 0 */
+#define LPC214X_SPI0_IRQ      10 /* SPI 0 */
+#define LPC214X_SPI1_IRQ      11 /* SPI 1 */
+#define LPC214X_PLL_IRQ       12 /* PLL Lock IRQ */
+#define LPC214X_RTC_IRQ       13 /* Real Time Clock */
+#define LPC214X_EINT0_IRQ     14 /* External interrupt 0 */
+#define LPC214X_EINT1_IRQ     15 /* External interrupt 1 */
+#define LPC214X_EINT2_IRQ     16 /* External interrupt 2 */
+#define LPC214X_EINT3_IRQ     17 /* External interrupt 3 */
+#define LPC214X_ADC0_IRQ      18 /* ADC 0 */
+#define LPC214X_I2C1_IRQ      19 /* I2C 1 */
+#define LPC214X_BOD_IRQ       20 /* Brown Out Detect */
+#define LPC214X_ADC1_IRQ      21 /* ADC 1 */
+#define LPC214X_USB_IRQ       22 /* USB */
+
+#define LPC214X_IRQ_SYSTIMER  LPC214X_TIMER0_IRQ
+#define NR_IRQS               23
+
+/* There are 16 vectored interrupts.  If vectored interrupts are enabled, the
+ * following will be used by the system.
+ */
+
+#define LPC214X_SYSTEMER_VEC  0 /* System timer */
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+typedef void (*vic_vector_t)(uint32 *regs);
+#endif
+
+/****************************************************************************
+ * Inline functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Variables
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Function Prototypes
+ ****************************************************************************/
+
+#ifndef __ASSEMBLY__
+#ifdef __cplusplus
+#define EXTERN extern "C"
+extern "C" {
+#else
+#define EXTERN extern
+#endif
+
+#ifndef CONFIG_VECTORED_INTERRUPTS
+EXTERN void up_attach_vector(int irq, int vector, vic_vector_t handler);
+EXTERN void up_detach_vector(int vector);
+#endif
+
+#undef EXTERN
+#ifdef __cplusplus
+}
+#endif
+#endif
+
+#endif /* __ARCH_LPC214X_IRQ_H */
+

arch/arm/src/Makefile

@@ -99,10 +99,10 @@ ifeq ($(CONFIG_RRLOAD_BINARY),y)
 	fi
 endif
 
-.depend: Makefile $(SRCS)
+.depend: Makefile chip/Make.defs $(SRCS)
 	@if [ -e board/Makefile ]; then \
 		$(MAKE) -C board TOPDIR=$(TOPDIR) depend ; \
-	if
+	fi
 	$(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep
 	@touch $@
 

arch/arm/src/c5471/Make.defs

@@ -37,12 +37,12 @@ HEAD_ASRC	= up_nommuhead.S
 
 CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S
 CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
-		  up_createstack.c up_dataabort.c up_delay.c up_exit.c up_idle.c \
+		  up_createstack.c up_dataabort.c up_delay.c up_doirq.c \
-		  up_initialize.c up_initialstate.c up_interruptcontext.c \
+		  up_exit.c up_idle.c up_initialize.c up_initialstate.c \
-		  up_prefetchabort.c up_releasepending.c up_releasestack.c \
+		  up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
-		  up_reprioritizertr.c up_schedulesigaction.c up_sigdeliver.c \
+		  up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \
-		  up_syscall.c up_unblocktask.c up_undefinedinsn.c up_usestack.c
+		  up_sigdeliver.c up_syscall.c up_unblocktask.c \
+		  up_undefinedinsn.c up_usestack.c
 
 CHIP_ASRCS	= c5471_lowputc.S c5471_vectors.S
-CHIP_CSRCS	= c5471_doirq.c c5471_irq.c c5471_serial.c c5471_timerisr.c \
+CHIP_CSRCS	= c5471_irq.c c5471_serial.c c5471_timerisr.c c5471_watchdog.c
-		  c5471_watchdog.c

arch/arm/src/c5471/c5471_vectors.S

@@ -156,7 +156,7 @@ up_vectorirq:
 
 	mov	fp, #0			/* Init frame pointer */
 	mov	r1, sp			/* Get r1=xcp */
-	bl	c5471_doirq		/* Call the handler */
+	bl	up_doirq		/* Call the handler */
 
 	/* Restore the CPSR, SVC modr registers and return */
 .Lnoirqset:

arch/arm/src/c5471/c5471_watchdog.c

@@ -365,7 +365,7 @@ int up_wdtinit(void)
 
   /* Register as /dev/wdt */
 
-  ret = register_inode("/dev/wdt", &g_wdtops, 0666, NULL);
+  ret = register_driver("/dev/wdt", &g_wdtops, 0666, NULL);
   if (ret)
     {
       return ERROR;
@@ -384,7 +384,7 @@ int up_wdtinit(void)
   ret = irq_attach(C5471_IRQ_WATCHDOG, wdt_interrupt);
   if (ret)
     {
-      unregister_inode("/dev/wdt");
+      unregister_driver("/dev/wdt");
       return ERROR;
     }
 

arch/arm/src/c5471/chip.h

@@ -316,8 +316,4 @@
  * Public Function Prototypes
  ************************************************************/
 
-#ifndef __ASSEMBLY__
-extern void c5471_doirq(int irq, uint32* regs);
-#endif
-
 #endif  /* __C5471_CHIP_H */

arch/arm/src/common/up_internal.h

@@ -101,7 +101,8 @@ extern void up_boot(void);
 extern void up_copystate(uint32 *dest, uint32 *src);
 extern void up_dataabort(uint32 *regs);
 extern void up_delay(int milliseconds);
-extern void up_doirq(uint32 *regs);
+extern void up_decodeirq(uint32 *regs);
+extern void up_doirq(int irq, uint32 *regs);
 extern void up_fullcontextrestore(uint32 *regs) __attribute__ ((noreturn));
 extern void up_irqinitialize(void);
 extern void up_prefetchabort(uint32 *regs);

arch/arm/src/common/up_unblocktask.c

@@ -43,6 +43,7 @@
 #include <debug.h>
 #include <nuttx/arch.h>
 #include "os_internal.h"
+#include "clock_internal.h"
 #include "up_internal.h"
 
 /************************************************************
@@ -101,7 +102,7 @@ void up_unblock_task(_TCB *tcb)
        */
 
 #if CONFIG_RR_INTERVAL > 0
-      tcb->timeslice = CONFIG_RR_INTERVAL;
+      tcb->timeslice = CONFIG_RR_INTERVAL / MSEC_PER_TICK;
 #endif
 
       /* Add the task in the correct location in the prioritized

arch/arm/src/common/up_vectors.S

@@ -128,7 +128,7 @@ up_vectorirq:
 
 	mov	fp, #0			/* Init frame pointer */
 	mov	r0, sp			/* Get r0=xcp */
-	bl	up_doirq		/* Call the handler */
+	bl	up_decodeirq		/* Call the handler */
 
 	/* Restore the CPSR, SVC modr registers and return */
 .Lnoirqset:
@@ -138,6 +138,7 @@ up_vectorirq:
 
 .Lirqtmp:
 	.word	g_irqtmp
+	.size	up_vectorirq, . - up_vectorirq
 
 	.align	5
 
@@ -183,6 +184,7 @@ up_vectorswi:
 	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
 	msr	spsr, r0
 	ldmia	sp, {r0-r15}^		/* Return */
+	.size	up_vectorswi, . - up_vectorswi
 
 	.align	5
 
@@ -251,6 +253,7 @@ up_vectordata:
 
 .Ldaborttmp:
 	.word	g_aborttmp
+	.size	up_vectordata, . - up_vectordata
 
 	.align	5
 
@@ -317,6 +320,7 @@ up_vectorprefetch:
 
 .Lpaborttmp:
 	.word	g_aborttmp
+	.size	up_vectorprefetch, . - up_vectorprefetch
 
 	.align	5
 
@@ -383,6 +387,7 @@ up_vectorundefinsn:
 
 .Lundeftmp:
 	.word	g_undeftmp
+	.size	up_vectorundefinsn, . - up_vectorundefinsn
 
 	.align	5
 
@@ -397,6 +402,9 @@ up_vectorundefinsn:
 	.type	up_vectorfiq, %function
 up_vectorfiq:
 	subs	pc, lr, #4
+	.size	up_vectofiq, . - up_vectorfiq
+
+	.align	5
 
 /********************************************************************
  *  Name: up_vectoraddrexcption
@@ -410,40 +418,5 @@ up_vectorfiq:
 	.type	up_vectoraddrexcptn, %function
 up_vectoraddrexcptn:
 	b	up_vectoraddrexcptn
-
+	.size	up_vectoaddrexcptn, . - up_vectoraddrexcptn
-/**************************************************************************
- * Vector initialization block.
- **************************************************************************/
-
-/* These will be relocated to VECTOR_BASE. */
-
-	.globl	_vector_start
-_vector_start:
-	ldr	pc, .Lresethandler		/* 0x00: Reset */
-	ldr	pc, .Lundefinedhandler		/* 0x04: Undefined instruction */
-	ldr	pc, .Lswihandler		/* 0x08: Software interrupt */
-	ldr	pc, .Lprefetchaborthandler	/* 0x0c: Prefetch abort */
-	ldr	pc, .Ldataaborthandler		/* 0x10: Data abort */
-	ldr	pc, .Laddrexcptnhandler		/* 0x14: Address exception */
-	ldr	pc, .Lirqhandler		/* 0x18: IRQ */
-	ldr	pc, .Lfiqhandler		/* 0x1c: FIQ */
-
-.Lresethandler:
-	.long   __start
-.Lundefinedhandler:
-	.long	up_vectorundefinsn
-.Lswihandler:
-	.long	up_vectorswi
-.Lprefetchaborthandler:
-	.long	up_vectorprefetch
-.Ldataaborthandler:
-	.long	up_vectordata
-.Laddrexcptnhandler:
-	.long	up_vectoraddrexcptn
-.Lirqhandler:
-	.long	up_vectorirq
-.Lfiqhandler:
-	.long	up_vectorfiq
-	.globl	_vector_end
-_vector_end:
 	.end

arch/arm/src/common/up_vectortab.S

@@ -0,0 +1,103 @@
+/********************************************************************
+ * common/up_vectortab.S
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************/
+
+/********************************************************************
+ * Included Files
+ ********************************************************************/
+
+#include <nuttx/config.h>
+
+/********************************************************************
+ * Definitions
+ ********************************************************************/
+
+/********************************************************************
+ * Global Data
+ ********************************************************************/
+
+/********************************************************************
+ * Assembly Macros
+ ********************************************************************/
+
+/********************************************************************
+ * Name: _vector_start
+ *
+ * Description:
+ *   Vector initialization block
+ ********************************************************************/
+
+	.globl	_vector_start
+
+/* These will be relocated to VECTOR_BASE. */
+
+_vector_start:
+	ldr	pc, .Lresethandler		/* 0x00: Reset */
+	ldr	pc, .Lundefinedhandler		/* 0x04: Undefined instruction */
+	ldr	pc, .Lswihandler		/* 0x08: Software interrupt */
+	ldr	pc, .Lprefetchaborthandler	/* 0x0c: Prefetch abort */
+	ldr	pc, .Ldataaborthandler		/* 0x10: Data abort */
+	ldr	pc, .Laddrexcptnhandler		/* 0x14: Address exception */
+	ldr	pc, .Lirqhandler		/* 0x18: IRQ */
+	ldr	pc, .Lfiqhandler		/* 0x1c: FIQ */
+
+	.globl   __start
+	.globl	up_vectorundefinsn
+	.globl	up_vectorswi
+	.globl	up_vectorprefetch
+	.globl	up_vectordata
+	.globl	up_vectoraddrexcptn
+	.globl	up_vectorirq
+	.globl	up_vectorfiq
+
+.Lresethandler:
+	.long   __start
+.Lundefinedhandler:
+	.long	up_vectorundefinsn
+.Lswihandler:
+	.long	up_vectorswi
+.Lprefetchaborthandler:
+	.long	up_vectorprefetch
+.Ldataaborthandler:
+	.long	up_vectordata
+.Laddrexcptnhandler:
+	.long	up_vectoraddrexcptn
+.Lirqhandler:
+	.long	up_vectorirq
+.Lfiqhandler:
+	.long	up_vectorfiq
+
+	.globl	_vector_end
+_vector_end:
+	.end

arch/arm/src/dm320/Make.defs

@@ -35,7 +35,8 @@
 
 HEAD_ASRC	= up_head.S
 
-CMN_ASRCS	= up_cache.S up_fullcontextrestore.S up_saveusercontext.S
+CMN_ASRCS	= up_cache.S up_fullcontextrestore.S up_saveusercontext.S \
+		  up_vectors.S up_vectortab.S
 CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
 		  up_dataabort.c up_delay.c up_exit.c up_idle.c \
 		  up_initialize.c up_initialstate.c up_interruptcontext.c \
@@ -44,7 +45,7 @@ CMN_CSRCS	= up_assert.c up_blocktask.c up_copystate.c up_createstack.c \
 		  up_sigdeliver.c up_syscall.c up_unblocktask.c \
 		  up_undefinedinsn.c up_usestack.c
 
-CHIP_ASRCS	= dm320_lowputc.S dm320_restart.S dm320_vectors.S
+CHIP_ASRCS	= dm320_lowputc.S dm320_restart.S
-CHIP_CSRCS	= dm320_allocateheap.c dm320_boot.c dm320_doirq.c dm320_irq.c \
+CHIP_CSRCS	= dm320_allocateheap.c dm320_boot.c dm320_decodeirq.c \
-		  dm320_serial.c dm320_timerisr.c
+		  dm320_irq.c dm320_serial.c dm320_timerisr.c
 

arch/arm/src/dm320/dm320_decodeirq.c

@@ -1,5 +1,5 @@
 /********************************************************************************
- * dm320/dm320_doirq.c
+ * dm320/dm320_decodeirq.c
  *
  *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
  *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
@@ -67,7 +67,7 @@
  * Public Funtions
  ********************************************************************************/
 
-void up_doirq(uint32* regs)
+void up_decodeirq(uint32* regs)
 {
 #ifdef CONFIG_SUPPRESS_INTERRUPTS
   lib_lowprintf("Unexpected IRQ\n");

arch/arm/src/dm320/dm320_vectors.S

@@ -1,449 +0,0 @@
-/********************************************************************
- * dm320/dm320_vectors.S
- *
- *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
- *
- * Redistribution and use in source and binary forms, with or without
- * modification, are permitted provided that the following conditions
- * are met:
- *
- * 1. Redistributions of source code must retain the above copyright
- *    notice, this list of conditions and the following disclaimer.
- * 2. Redistributions in binary form must reproduce the above copyright
- *    notice, this list of conditions and the following disclaimer in
- *    the documentation and/or other materials provided with the
- *    distribution.
- * 3. Neither the name Gregory Nutt nor the names of its contributors may be
- *    used to endorse or promote products derived from this software
- *    without specific prior written permission.
- *
- * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
- * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
- * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
- * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
- * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
- * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
- * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
- * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
- * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
- * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
- * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
- * POSSIBILITY OF SUCH DAMAGE.
- *
- ********************************************************************/
-
-/********************************************************************
- * Included Files
- ********************************************************************/
-
-#include <nuttx/config.h>
-#include <nuttx/irq.h>
-#include "up_arch.h"
-
-/********************************************************************
- * Definitions
- ********************************************************************/
-
-/********************************************************************
- * Global Data
- ********************************************************************/
-
-	.data
-g_irqtmp:
-	.word	0		/* Saved lr */
-	.word	0		/* Saved spsr */
-g_undeftmp:
-	.word	0		/* Saved lr */
-	.word	0		/* Saved spsr */
-g_aborttmp:
-	.word	0		/* Saved lr */
-	.word	0		/* Saved spsr */
-
-/********************************************************************
- * Assembly Macros
- ********************************************************************/
-
-/********************************************************************
- * Private Functions
- ********************************************************************/
-
-	.text
-
-/********************************************************************
- * Public Functions
- ********************************************************************/
-
-	.text
-
-/********************************************************************
- * Name: up_vectorirq
- *
- * Description:
- *   Interrupt excetpion. Entered in IRQ mode with spsr = SVC
- *   CPSR, lr = SVC PC
- ********************************************************************/
-
-	.globl	up_vectorirq
-	.type	up_vectorirq, %function
-up_vectorirq:
-	/* On entry, we are in IRQ mode.  We are free to use
-	 * the IRQ mode r13 and r14.
-         *
-	 */
-
-	ldr	r13, .Lirqtmp
-	sub	lr, lr, #4
-	str	lr, [r13]			@ save lr_IRQ
-	mrs	lr, spsr
-	str	lr, [r13, #4]			@ save spsr_IRQ
-
-	/* Then switch back to SVC mode */
-
-	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
-	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
-	msr	cpsr_c, lr		/* Switch to SVC mode */
-
-	/* Create a context structure.  First set aside a stack frame
-	 * and store r0-r12 into the frame.
-	 */
-
-	sub	sp, sp, #XCPTCONTEXT_SIZE
-	stmia	sp, {r0-r12}		/* Save the SVC mode regs */
-
-	/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
-
-	add	r1, sp, #XCPTCONTEXT_SIZE
-	mov	r2, r14
-
-	/* Get the values for r15(pc) and CPSR in r3 and r4 */
-
-	ldr	r0, .Lirqtmp		/* Points to temp storage */
-	ldmia	r0, {r3, r4}		/* Recover r1=lr_IRQ, r2=spsr_IRQ */
-
-	add	r0, sp, #(4*REG_SP)	/* Offset to pc, cpsr storage */
-	stmia	r0, {r1-r4}
-
-	/* Then call the IRQ handler with interrupts disabled. */
-
-	mov	fp, #0			/* Init frame pointer */
-	mov	r0, sp			/* Get r0=xcp */
-	bl	up_doirq		/* Call the handler */
-
-	/* Restore the CPSR, SVC modr registers and return */
-.Lnoirqset:
-	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
-	msr	spsr, r0
-	ldmia	sp, {r0-r15}^		/* Return */
-
-.Lirqtmp:
-	.word	g_irqtmp
-
-	.align	5
-
-/********************************************************************
- * Function: up_vectorswi
- * 
- * Description:
- *   SWI interrupt. We enter the SWI in SVC mode
- ********************************************************************/
-
-	.globl	up_vectorswi
-	.type	up_vectorswi, %function
-up_vectorswi:
-
-	/* Create a context structure.  First set aside a stack frame
-	 * and store r0-r12 into the frame.
-	 */
-
-	sub	sp, sp, #XCPTCONTEXT_SIZE
-	stmia	sp, {r0-r12}		/* Save the SVC mode regs */
-
-	/* Get the correct values of r13(sp), r14(lr), r15(pc)
-	 * and CPSR in r1-r4 */
-
-	add	r1, sp, #XCPTCONTEXT_SIZE
-	mov	r2, r14			/* R14 is altered on return from SWI */
-	mov	r3, r14			/* Save r14 as the PC as well */
-	mrs	r4, spsr		/* Get the saved CPSR */
-
-	add	r0, sp, #(4*REG_SP)	/* Offset to pc, cpsr storage */
-	stmia	r0, {r1-r4}
-
-	/* Then call the SWI handler with interrupt disabled.
-	 * void up_syscall(struct xcptcontext *xcp)
-	 */
-
-	mov	fp, #0			/* Init frame pointer */
-	mov	r0, sp			/* Get r0=xcp */
-	bl	up_syscall		/* Call the handler */
-
-	/* Restore the CPSR, SVC modr registers and return */
-
-	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
-	msr	spsr, r0
-	ldmia	sp, {r0-r15}^		/* Return */
-
-	.align	5
-
-/********************************************************************
- * Name: up_vectordata
- *
- * Description:
- *   Data abort Exception dispatcher. Give control to data
- *   abort handler.  This function is entered in ABORT mode
- *   with spsr = SVC CPSR, lr = SVC PC
- *
- ********************************************************************/
-	
-	.globl	up_vectordata
-	.type	up_vectordata, %function
-up_vectordata:
-	/* On entry we are free to use the ABORT mode registers
-	 * r13 and r14
-	 */
-
-	ldr	r13, .Ldaborttmp	/* Points to temp storage */
-	sub	lr, lr, #8		/* Fixup return */
-	str	lr, [r13]		/* Save in temp storage */
-	mrs	lr, spsr		/* Get SPSR */
-	str	lr, [r13, #4]		/* Save in temp storage */
-
-	/* Then switch back to SVC mode */
-
-	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
-	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
-	msr	cpsr_c, lr		/* Switch to SVC mode */
-
-	/* Create a context structure.  First set aside a stack frame
-	 * and store r0-r12 into the frame.
-	 */
-
-	sub	sp, sp, #XCPTCONTEXT_SIZE
-	stmia	sp, {r0-r12}		/* Save the SVC mode regs */
-
-	/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
-
-	add	r1, sp, #XCPTCONTEXT_SIZE
-	mov	r2, r14
-
-	/* Get the values for r15(pc) and CPSR in r3 and r4 */
-
-	ldr	r0, .Ldaborttmp		/* Points to temp storage */
-	ldmia	r0, {r3, r4}		/* Recover r1=lr_IRQ, r2=spsr_IRQ */
-
-	add	r0, sp, #(4*REG_SP)	/* Offset to pc, cpsr storage */
-	stmia	r0, {r1-r4}
-
-	/* Then call the data abort handler with interrupt disabled.
-	 * void up_dataabort(struct xcptcontext *xcp)
-	 */
-
-	mov	fp, #0			/* Init frame pointer */
-	mov	r0, sp			/* Get r0=xcp */
-	bl	up_dataabort		/* Call the handler */
-
-	/* Restore the CPSR, SVC modr registers and return */
-
-	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
-	msr	spsr_cxsf, r0
-	ldmia	sp, {r0-r15}^		/* Return */
-
-.Ldaborttmp:
-	.word	g_aborttmp
-
-	.align	5
-
-/********************************************************************
- * Name: up_vectorprefetch
- *
- * Description:
- *    Prefetch abort exception.  Entered in ABT mode with
- *    spsr = SVC CPSR, lr = SVC PC
- ********************************************************************/
-	
-	.globl	up_vectorprefetch
-	.type	up_vectorprefetch, %function
-up_vectorprefetch:
-	/* On entry we are free to use the ABORT mode registers
-	 * r13 and r14
-	 */
-
-	ldr	r13, .Lpaborttmp	/* Points to temp storage */
-	sub	lr, lr, #4		/* Fixup return */
-	str	lr, [r13]		/* Save in temp storage */
-	mrs	lr, spsr		/* Get SPSR */
-	str	lr, [r13, #4]		/* Save in temp storage */
-
-	/* Then switch back to SVC mode */
-
-	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
-	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
-	msr	cpsr_c, lr		/* Switch to SVC mode */
-
-	/* Create a context structure.  First set aside a stack frame
-	 * and store r0-r12 into the frame.
-	 */
-
-	sub	sp, sp, #XCPTCONTEXT_SIZE
-	stmia	sp, {r0-r12}		/* Save the SVC mode regs */
-
-	/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
-
-	add	r1, sp, #XCPTCONTEXT_SIZE
-	mov	r2, r14
-
-	/* Get the values for r15(pc) and CPSR in r3 and r4 */
-
-	ldr	r0, .Lpaborttmp		/* Points to temp storage */
-	ldmia	r0, {r3, r4}		/* Recover r1=lr_IRQ, r2=spsr_IRQ */
-
-	add	r0, sp, #(4*REG_SP)	/* Offset to pc, cpsr storage */
-	stmia	r0, {r1-r4}
-
-	/* Then call the prefetch abort handler with interrupt disabled.
-	 * void up_prefetchabort(struct xcptcontext *xcp)
-	 */
-
-	mov	fp, #0			/* Init frame pointer */
-	mov	r0, sp			/* Get r0=xcp */
-	bl	up_prefetchabort	/* Call the handler */
-
-	/* Restore the CPSR, SVC modr registers and return */
-
-	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
-	msr	spsr_cxsf, r0
-	ldmia	sp, {r0-r15}^		/* Return */
-
-.Lpaborttmp:
-	.word	g_aborttmp
-
-	.align	5
-
-/********************************************************************
- * Name: up_vectorundefinsn
- *
- * Description:
- *   Undefined instruction entry exception.  Entered in
- *   UND mode, spsr = SVC  CPSR, lr = SVC PC
- *
- ********************************************************************/
-	
-	.globl	up_vectorundefinsn
-	.type	up_vectorundefinsn, %function
-up_vectorundefinsn:
-	/* On entry we are free to use the UND mode registers
-	 * r13 and r14
-	 */
-
-	ldr	r13, .Lundeftmp		/* Points to temp storage */
-	str	lr, [r13]		/* Save in temp storage */
-	mrs	lr, spsr		/* Get SPSR */
-	str	lr, [r13, #4]		/* Save in temp storage */
-
-	/* Then switch back to SVC mode */
-
-	bic	lr, lr, #MODE_MASK	/* Keep F and T bits */
-	orr	lr, lr, #(SVC_MODE | PSR_I_BIT)
-	msr	cpsr_c, lr		/* Switch to SVC mode */
-
-	/* Create a context structure.  First set aside a stack frame
-	 * and store r0-r12 into the frame.
-	 */
-
-	sub	sp, sp, #XCPTCONTEXT_SIZE
-	stmia	sp, {r0-r12}		/* Save the SVC mode regs */
-
-	/* Get the correct values of r13(sp) and r14(lr) in r1 and r2 */
-
-	add	r1, sp, #XCPTCONTEXT_SIZE
-	mov	r2, r14
-
-	/* Get the values for r15(pc) and CPSR in r3 and r4 */
-
-	ldr	r0, .Lundeftmp		/* Points to temp storage */
-	ldmia	r0, {r3, r4}		/* Recover r1=lr_IRQ, r2=spsr_IRQ */
-
-	add	r0, sp, #(4*REG_SP)	/* Offset to pc, cpsr storage */
-	stmia	r0, {r1-r4}
-
-	/* Then call the undef insn handler with interrupt disabled.
-	 * void up_undefinedinsn(struct xcptcontext *xcp)
-	 */
-
-	mov	fp, #0			/* Init frame pointer */
-	mov	r0, sp			/* Get r0=xcp */
-	bl	up_undefinedinsn	/* Call the handler */
-
-	/* Restore the CPSR, SVC modr registers and return */
-
-	ldr	r0, [sp, #(4*REG_CPSR)]	/* Setup the SVC mode SPSR */
-	msr	spsr_cxsf, r0
-	ldmia	sp, {r0-r15}^		/* Return */
-
-.Lundeftmp:
-	.word	g_undeftmp
-
-	.align	5
-
-/********************************************************************
- * Name: up_vectorfiq
- *
- * Description:
- *   Shouldn't happen
- ********************************************************************/
-
-	.globl	up_vectorfiq
-	.type	up_vectorfiq, %function
-up_vectorfiq:
-	subs	pc, lr, #4
-
-/********************************************************************
- *  Name: up_vectoraddrexcption
- *
- * Description:
- *   Shouldn't happen
- *
- ********************************************************************/
-
-	.globl	up_vectoraddrexcptn
-	.type	up_vectoraddrexcptn, %function
-up_vectoraddrexcptn:
-	b	up_vectoraddrexcptn
-
-/**************************************************************************
- * Vector initialization block.
- **************************************************************************/
-
-/* These will be relocated to VECTOR_BASE. */
-
-	.globl	_vector_start
-_vector_start:
-	ldr	pc, .Lresethandler		/* 0x00: Reset */
-	ldr	pc, .Lundefinedhandler		/* 0x04: Undefined instruction */
-	ldr	pc, .Lswihandler		/* 0x08: Software interrupt */
-	ldr	pc, .Lprefetchaborthandler	/* 0x0c: Prefetch abort */
-	ldr	pc, .Ldataaborthandler		/* 0x10: Data abort */
-	ldr	pc, .Laddrexcptnhandler		/* 0x14: Address exception */
-	ldr	pc, .Lirqhandler		/* 0x18: IRQ */
-	ldr	pc, .Lfiqhandler		/* 0x1c: FIQ */
-
-.Lresethandler:
-	.long   __start
-.Lundefinedhandler:
-	.long	up_vectorundefinsn
-.Lswihandler:
-	.long	up_vectorswi
-.Lprefetchaborthandler:
-	.long	up_vectorprefetch
-.Ldataaborthandler:
-	.long	up_vectordata
-.Laddrexcptnhandler:
-	.long	up_vectoraddrexcptn
-.Lirqhandler:
-	.long	up_vectorirq
-.Lfiqhandler:
-	.long	up_vectorfiq
-	.globl	_vector_end
-_vector_end:
-	.end

arch/arm/src/lpc214x/Make.defs

@@ -0,0 +1,50 @@
+############################################################################
+# lpc214x/Make.defs
+#
+#   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name Gregory Nutt nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################################
+
+HEAD_ASRC	= lpc214x_head.S
+
+CMN_ASRCS	= up_saveusercontext.S up_fullcontextrestore.S up_vectors.S
+CMN_CSRCS	= up_allocateheap.c up_assert.c up_blocktask.c up_copystate.c \
+		  up_createstack.c up_dataabort.c up_delay.c up_exit.c \
+		  up_idle.c up_initialize.c up_initialstate.c \
+		  up_interruptcontext.c up_prefetchabort.c up_releasepending.c \
+		  up_releasestack.c up_reprioritizertr.c up_schedulesigaction.c \
+		  up_sigdeliver.c up_syscall.c up_unblocktask.c \
+		  up_undefinedinsn.c up_usestack.c
+
+CHIP_ASRCS	= lpc214x_lowputc.S
+CHIP_CSRCS	= lpc214x_decodeirq.c lpc214x_irq.c lpc214x_timerisr.c \
+		  lpc214x_serial.c
+	

arch/arm/src/lpc214x/README.txt

@@ -0,0 +1,61 @@
+General Description
+^^^^^^^^^^^^^^^^^^^
+
+http://www.nxp.com/pip/LPC2141FBD64.html:
+
+The LPC2141/42/44/46/48 microcontrollers are based on a 16-bit/32-bit ARM7TDMI-S
+CPU with real-time emulation and embedded trace support, that combine
+microcontroller with embedded high-speed flash memory ranging from 32 kB to
+512 kB. A 128-bit wide memory interface and a unique accelerator architecture
+enable 32-bit code execution at the maximum clock rate. For critical code size
+applications, the alternative 16-bit Thumb mode reduces code by more than 30 pct
+with minimal performance penalty. 
+
+Due to their tiny size and low power consumption, LPC2141/42/44/46/48 are ideal
+for applications where miniaturization is a key requirement, such as access
+control and point-of-sale. Serial communications interfaces ranging from a USB 2.0
+Full-speed device, multiple UARTs, SPI, SSP to I2C-bus and on-chip SRAM of 8 kB
+up to 40 kB, make these devices very well suited for communication gateways and
+protocol converters, soft modems, voice recognition and low end imaging, providing
+both large buffer size and high processing power. Various 32-bit timers, single
+or dual 10-bit ADC(s), 10-bit DAC, PWM channels and 45 fast GPIO lines with up
+to nine edge or level sensitive external interrupt pins make these microcontrollers
+suitable for industrial control and medical systems. 
+
+
+Features
+^^^^^^^^
+
+o 16-bit/32-bit ARM7TDMI-S microcontroller in a tiny LQFP64 package. 
+o 8 kB to 40 kB of on-chip static RAM and 32 kB to 512 kB of on-chip flash memory.
+  128-bit wide interface/accelerator enables high-speed 60 MHz operation. 
+o In-System Programming/In-Application Programming (ISP/IAP) via on-chip boot
+  loader software. Single flash sector or full chip erase in 400 ms and programming
+  of 256 B in 1 ms. 
+o EmbeddedICE RT and Embedded Trace interfaces offer real-time debugging with the
+  on-chip RealMonitor software and high-speed tracing of instruction execution. 
+o USB 2.0 Full-speed compliant device controller with 2 kB of endpoint RAM. In addition,
+  the LPC2146/48 provides 8 kB of on-chip RAM accessible to USB by DMA. 
+o One or two (LPC2141/42 vs. LPC2144/46/48) 10-bit ADCs provide a total of 6/14 analog
+  inputs, with conversion times as low as 2.44 us per channel. 
+o Single 10-bit DAC provides variable analog output (LPC2142/44/46/48 only). 
+o Two 32-bit timers/external event counters (with four capture and four compare
+  channels each), PWM unit (six outputs) and watchdog. 
+o Low power Real-Time Clock (RTC) with independent power and 32 kHz clock input. 
+o Multiple serial interfaces including two UARTs (16C550), two Fast I2C-bus (400
+  kbit/s), SPI and SSP with buffering and variable data length capabilities. 
+o Vectored Interrupt Controller (VIC) with configurable priorities and vector addresses. 
+o Up to 45 of 5 V tolerant fast general purpose I/O pins in a tiny LQFP64 package. 
+o Up to 21 external interrupt pins available. 
+o 60 MHz maximum CPU clock available from programmable on-chip PLL with settling
+  time of 100 us. 
+o On-chip integrated oscillator operates with an external crystal from 1 MHz to 25 MHz. 
+o Power saving modes include Idle and Power-down. 
+o Individual enable/disable of peripheral functions as well as peripheral clock scaling
+  for additional power optimization. 
+o Processor wake-up from Power-down mode via external interrupt or BOD. 
+o Single power supply chip with POR and BOD circuits: 
+o CPU operating voltage range of 3.0 V to 3.6 V (3.3 V +- 10 pct) with 5 V tolerant
+  I/O pads. 
+
+ 

arch/arm/src/lpc214x/Startup.s

@@ -0,0 +1,80 @@
+/*
+ *  The STARTUP.S code is executed after CPU Reset. This file may be 
+ *  translated with the following SET symbols. In uVision these SET 
+ *  symbols are entered under Options - ASM - Set.
+ *
+ *  REMAP: when set the startup code initializes the register MEMMAP 
+ *  which overwrites the settings of the CPU configuration pins. The 
+ *  startup and interrupt vectors are remapped from:
+ *     0x00000000  default setting (not remapped)
+ *     0x80000000  when EXTMEM_MODE is used
+ *     0x40000000  when RAM_MODE is used
+ *
+ *  EXTMEM_MODE: when set the device is configured for code execution
+ *  from external memory starting at address 0x80000000. The startup
+ *  vectors are located to 0x80000000.
+ *
+ *  RAM_MODE: when set the device is configured for code execution
+ *  from on-chip RAM starting at address 0x40000000. The startup
+ *  vectors are located to 0x40000000.
+ */
+
+Reset_Handler:  
+
+
+
+/* Memory Mapping */
+
+
+/* Setup Stack for each mode */
+	ldr	r0, =Top_Stack
+
+/* Enter Undefined Instruction Mode and set its Stack Pointer */
+	msr     CPSR_c, #UND_MODE | PSR_I_BIT | PSR_F_BIT
+	mov     SP, r0
+	sub	r0, r0, #UND_Stack_Size
+
+/* Enter Abort Mode and set its Stack Pointer */
+	msr     CPSR_c, #ABT_MODE | PSR_I_BIT | PSR_F_BIT
+	mov     SP, r0
+	sub	r0, r0, #ABT_Stack_Size
+
+/* Enter FIQ Mode and set its Stack Pointer */
+	msr     CPSR_c, #FIQ_MODE | PSR_I_BIT | PSR_F_BIT
+	mov     SP, r0
+	sub	r0, r0, #FIQ_Stack_Size
+
+/* Enter IRQ Mode and set its Stack Pointer */
+	msr     CPSR_c, #IRQ_MODE | PSR_I_BIT | PSR_F_BIT
+	mov     SP, r0
+	sub	r0, r0, #IRQ_Stack_Size
+
+/* Enter Supervisor Mode and set its Stack Pointer */
+	msr     CPSR_c, #SVC_MODE | PSR_I_BIT | PSR_F_BIT
+	mov     SP, r0
+	sub	r0, r0, #SVC_Stack_Size
+
+/* Enter User Mode and set its Stack Pointer */
+	msr     CPSR_c, #USR_MODE
+	mov     SP, r0
+
+/* Enter the C code */
+	ldr	r0,=?C?INIT
+	tst	r0,#1	; Bit-0 set: INIT is Thumb
+	ldreq   LR,=exit?A  ; ARM Mode
+	ldrne   LR,=exit?T  ; Thumb Mode
+	bx	r0
+	ENDP
+
+PUBLIC exit?A
+exit?A	   PROC    CODE32
+	B	exit?A
+	ENDP
+
+PUBLIC exit?T
+exit?T	   PROC    CODE16
+exit:	    B	exit?T
+	ENDP
+
+
+	END

arch/arm/src/lpc214x/chip.h

@@ -0,0 +1,337 @@
+/****************************************************************************************************
+ * lpc214x/chip.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************************************/
+
+#ifndef __LPC214X_CHIP_H
+#define __LPC214X_CHIP_H
+
+/****************************************************************************************************
+ * Included Files
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Definitions
+ ****************************************************************************************************/
+
+/* Memory Map ***************************************************************************************/
+
+#define LPC214X_FLASH_BASE              0x00000000
+#define LPC214X_ONCHIP_RAM_BASE         0x40000000
+#define LPC214X_USBDMA_RAM_BASE         0x7fd00000
+#define LPC214X_BOOT_BLOCK              0x7fffd000
+#define LPC214X_EXTMEM_BASE             0x80000000
+#define LPC214X_APB_BASE                0xe0000000
+#define LPC214X_AHB_BASE                0xf0000000
+
+/* Peripheral Registers ****************************************************************************/
+
+/* Register block base addresses */
+
+#define LPC214X_WD_BASE                 0xe0000000  /* Watchdog base address */
+#define LPC214X_TMR0_BASE               0xe0004000  /* Timer 0 base address*/
+#define LPC214X_TMR1_BASE               0xe0008000  /* Timer 1 base address */
+#define LPC214X_UART0_BASE              0xe000c000  /* UART0 base address */
+#define LPC214X_UART1_BASE              0xe0010000  /* UART1 base address */
+#define LPC214X_PWM_BASE                0xe0014000  /* Pulse width modulator (PWM) base address */
+#define LPC214X_I2C_BASE                0xe001C000  /* I2C base address */
+#define LPC214X_SPI0_BASE               0xe0020000  /* Serial Peripheral Interface 0 (SPI0) base */
+#define LPC214X_RTC_BASE                0xe0024000  /* Real Time Clock (RTC) base address */
+#define LPC214X_GPIO0_BASE              0xe0028000  /* General Purpose I/O (GPIO) 0 base address */
+#define LPC214X_GPIO1_BASE              0xe0028010  /* General Purpose I/O (GPIO) 0 base address */
+#define LPC214X_PINSEL_BASE             0xe002c000  /* Pin function select registers */
+#define LPC214X_SPI1_BASE               0xe0030000  /* Serial Peripheral Interface 1 (SPI1) base */
+#define LPC214X_AD0_BASE                0xe0034000  /* Analog to Digital Converter 0 base address*/
+#define LPC214X_AD1_BASE                0xe0060000  /* Analog to Digital Converter 1 base address */
+
+#define LPC214X_SCB_BASE                0xe01fc000  /* System Control Block (SBC) base address */
+#define   LPC214X_MAM_BASE              0xe01fc000  /* Memory Accelerator Module (MAM) base address */
+#define   LPC214X_MEMMAP                0xe01fc040  /* Memory Mapping Control */
+#define   LPC214X_PLL_BASE              0xe01fc080  /* Phase Locked Loop (PLL) base address */
+#define   LPC214X_PCON_BASE             0xe01fc0c0  /* Power Control (PCON) base address */
+#define   LPC214X_VPBDIV                0xe01fc100  /* VPBDIV Address */
+#define   LPC214X_EXT_BASE              0xe01fc140  /* External Interrupt base address */       
+
+#define LPC214X_EMC_BASE                0xffe00000  /* External Memory Controller (EMC) base address */
+#define LPC214X_VIC_BASE                0xfffff000  /* Vectored Interrupt Controller (VIC) Base */
+
+/* Watchdog Register Offsets */
+
+#define LPC214X_WD_MOD_OFFSET           0x00 /* Watchdog Mode Register */
+#define LPC214X_WD_TC_OFFSET            0x04 /* Watchdog Time Constant Register */
+#define LPC214X_WD_FEED_OFFSET          0x08 /* Watchdog Feed Register */
+#define LPC214X_WD_TV_OFFSET            0x0C /* Watchdog Time Value Register */
+
+/* Timer 0/1 register offsets */
+
+#define LPC214X_TMR_IR_OFFSET           0x00   /* RW:Interrupt Register */
+#define LPC214X_TMR_TCR_OFFSET          0x04   /* RW: Timer Control Register */
+#define LPC214X_TMR_TC_OFFSET           0x08   /* RW: Timer Counter */
+#define LPC214X_TMR_PR_OFFSET           0x0c   /* RW: Prescale Register */
+#define LPC214X_TMR_PC_OFFSET           0x10   /* RW: Prescale Counter Register */
+#define LPC214X_TMR_MCR_OFFSET          0x14   /* RW: Match Control Register */
+#define LPC214X_TMR_MR0_OFFSET          0x18   /* RW: Match Register 0 */
+#define LPC214X_TMR_MR1_OFFSET          0x1c   /* RW: Match Register 1 */
+#define LPC214X_TMR_MR2_OFFSET          0x20   /* RW: Match Register 2 */
+#define LPC214X_TMR_MR3_OFFSET          0x24   /* RW: Match Register 3 */
+#define LPC214X_TMR_CCR_OFFSET          0x28   /* RW: Capture Control Register */
+#define LPC214X_TMR_CR0_OFFSET          0x2c   /* R: Capture Register 0 */
+#define LPC214X_TMR_CR1_OFFSET          0x30   /* R: Capture Register 1 */
+#define LPC214X_TMR_CR2_OFFSET          0x34   /* R: Capture Register 2 */
+#define LPC214X_TMR_CR3_OFFSET          0x38   /* RW: Capture Register 3 */
+#define LPC214X_TMR_EMR_OFFSET          0x3c   /* RW: External Match Register */
+
+#define LPC214X_TMR_CTCR_OFFSET         0x70   /* RW: Count Control Register */
+
+/* UART0/1 Register Offsets */
+
+#define LPC214X_UART_RBR_OFFSET         0x00   /* R: Receive Buffer Register (DLAB=0) */
+#define LPC214X_UART_THR_OFFSET         0x00   /* W: Transmit Holding Register (DLAB=0) */
+#define LPC214X_UART_DLL_OFFSET         0x00   /* W: Divisor Latch Register (LSB, DLAB=1) */
+#define LPC214X_UART_IER_OFFSET         0x04   /* W: Interrupt Enable Register (DLAB=0) */
+#define LPC214X_UART_DLM_OFFSET         0x04   /* RW: Divisor Latch Register (MSB, DLAB=1) */
+#define LPC214X_UART_IIR_OFFSET         0x08   /* R: Interrupt ID Register */
+#define LPC214X_UART_FCR_OFFSET         0x08   /* W: FIFO Control Register */
+#define LPC214X_UART_LCR_OFFSET         0x0c   /* RW: Line Control Register */
+#define LPC214X_UART_MCR_OFFSET         0x10   /* RW: Modem Control REgister (2146/6/8 UART1 Only) */
+#define LPC214X_UART_LSR_OFFSET         0x14   /* R: Scratch Pad Register */
+#define LPC214X_UART_MSR_OFFSET         0x18   /* RW: MODEM Status Register (2146/6/8 UART1 Only) */
+#define LPC214X_UART_SCR_OFFSET         0x1c   /* RW: Line Status Register */
+#define LPC214X_UART_ACR_OFFSET         0x20   /* RW: Autobaud Control Register */
+#define LPC214X_UART_FDR_OFFSET         0x28   /* RW: Fractional Divider Register */
+#define LPC214X_UART_TER_OFFSET         0x30   /* RW: Transmit Enable Register */
+
+/* PWM register offsets */
+
+#define LPC214X_PWM_IR_OFFSET           0x00   /* Interrupt Register */
+#define LPC214X_PWM_TCR_OFFSET          0x04   /* Timer Control Register */
+#define LPC214X_PWM_TC_OFFSET           0x08   /* Timer Counter */
+#define LPC214X_PWM_PR_OFFSET           0x0c   /* Prescale Register */
+#define LPC214X_PWM_PC_OFFSET           0x10   /* Prescale Counter Register */
+#define LPC214X_PWM_MCR_OFFSET          0x14   /* Match Control Register */
+#define LPC214X_PWM_MR0_OFFSET          0x18   /* Match Register 0 */
+#define LPC214X_PWM_MR1_OFFSET          0x1c   /* Match Register 1 */
+#define LPC214X_PWM_MR2_OFFSET          0x20   /* Match Register 2 */
+#define LPC214X_PWM_MR3_OFFSET          0x24   /* Match Register 3 */
+#define LPC214X_PWM_MR4_OFFSET          0x40   /* Match Register 4 */
+#define LPC214X_PWM_MR5_OFFSET          0x44   /* Match Register 5 */
+#define LPC214X_PWM_MR6_OFFSET          0x48   /* Match Register 6 */
+#define LPC214X_PWM_PCR_OFFSET          0x4c   /* Control Register */
+#define LPC214X_PWM_LER_OFFSET          0x50   /* Latch Enable Register */
+
+/* I2C register offsets */
+
+#define LPC214X_I2C_ONSET_OFFSET        0x00   /* Control Set Register */
+#define LPC214X_I2C_STAT_OFFSET         0x04   /* Status Register */
+#define LPC214X_I2C_DAT_OFFSET          0x08   /* Data Register */
+#define LPC214X_I2C_ADR_OFFSET          0x0c   /* Slave Address Register */
+#define LPC214X_I2C_SCLH_OFFSET         0x10   /* SCL Duty Cycle Register (high half word) */
+#define LPC214X_I2C_SCLL_OFFSET         0x14   /* SCL Duty Cycle Register (low half word) */
+#define LPC214X_I2C_ONCLR_OFFSET        0x18   /* Control Clear Register */
+
+/* Pin function select register offsets */
+
+#define LPC214X_PINSEL0_OFFSET          0x00   /* Pin function select register 0 */
+#define LPC214X_PINSEL1_OFFSET          0x04   /* Pin function select register 1 */
+#define LPC214X_PINSEL2_OFFSET          0x14   /* Pin function select register 2 */
+
+/* Analog to Digital (AD) Converter registger offsets */
+#define LPC214X_AD_ADCR_OFFSET          0x00   /* A/D Control Register */
+#define LPC214X_AD_ADGDR_OFFSET         0x04   /* A/D Global Data Register (only one common register!) */
+#define LPC214X_AD_ADGSR_OFFSET         0x08   /* A/D Global Start Register */
+#define LPC214X_AD_ADINTEN_OFFSET       0x0c   /* A/D Interrupt Enable Register */
+#define LPC214X_AD_ADDR0_OFFSET         0x10   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR1_OFFSET         0x14   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR2_OFFSET         0x18   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR3_OFFSET         0x1c   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR4_OFFSET         0x20   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR5_OFFSET         0x24   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR6_OFFSET         0x28   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADDR7_OFFSET         0x2c   /* A/D Chanel 0 Data Register */
+#define LPC214X_AD_ADSTAT_OFFSET        0x30   /* A/D Status Register */
+
+/* Pin function select registers (these are normally referenced as offsets) */
+
+#define LPC214X_PINSEL0                 (LPC214X_PINSEL_BASE + LPC214X_PINSEL0_OFFSET)
+#define LPC214X_PINSEL1                 (LPC214X_PINSEL_BASE + LPC214X_PINSEL1_OFFSET)
+#define LPC214X_PINSEL2                 (LPC214X_PINSEL_BASE + LPC214X_PINSEL2_OFFSET)
+
+/* SPI register offsets */
+
+#define LPC214X_SPI_CR0_OFFSET          0x00   /* Control Register 0 */
+#define LPC214X_SPI_CR1_OFFSET          0x04   /* Control Register 1 */
+#define LPC214X_SPI_DR_OFFSET           0x08   /* Data Register */
+#define LPC214X_SPI_SR_OFFSET           0x0c   /* Status Register */
+#define LPC214X_SPI_CPSR_OFFSET         0x10   /* Clock Pre-Scale Regisrer */
+#define LPC214X_SPI_IMSC_OFFSET         0x14   /* Interrupt Mask Set and Clear Register */
+#define LPC214X_SPI_RIS_OFFSET          0x18   /* Raw Interrupt Status Register */
+#define LPC214X_SPI_MIS_OFFSET          0x1c   /* Masked Interrupt Status Register */
+#define LPC214X_SPI_ICR_OFFSET          0x20   /* Interrupt Clear Register */
+
+/* RTC register offsets */
+
+#define LPC214X_RTC_ILR_OFFSET          0x00   /* Interrupt Location Register */
+#define LPC214X_RTC_CTC_OFFSET          0x04   /* Clock Tick Counter */
+#define LPC214X_RTC_CCR_OFFSET          0x08   /* Clock Control Register */
+#define LPC214X_RTC_CIIR_OFFSET         0x0c   /* Counter Increment Interrupt Register */
+#define LPC214X_RTC_AMR_OFFSET          0x10   /* Alarm Mask Register */
+#define LPC214X_RTC_CTIME0_OFFSET       0x14   /* Consolidated Time Register 0 */
+#define LPC214X_RTC_CTIME1_OFFSET       0x18   /* Consolidated Time Register 1 */
+#define LPC214X_RTC_CTIME2_OFFSET       0x1c   /* Consolidated Time Register 2 */
+#define LPC214X_RTC_SEC_OFFSET          0x20   /* Seconds Register */
+#define LPC214X_RTC_MIN_OFFSET          0x24   /* Minutes Register */
+#define LPC214X_RTC_HOUR_OFFSET         0x28   /* Hours Register */
+#define LPC214X_RTC_DOM_OFFSET          0x2c   /* Day Of Month Register */
+#define LPC214X_RTC_DOW_OFFSET          0x30   /* Day Of Week Register */
+#define LPC214X_RTC_DOY_OFFSET          0x34   /* Day Of Year Register */
+#define LPC214X_RTC_MONTH_OFFSET        0x38   /* Months Register */
+#define LPC214X_RTC_YEAR_OFFSET         0x3c   /* Years Register */
+
+#define LPC214X_RTC_ALSEC_OFFSET        0x60   /* Alarm Seconds Register */
+#define LPC214X_RTC_ALMIN_OFFSET        0x64   /* Alarm Minutes Register */
+#define LPC214X_RTC_ALHOUR_OFFSET       0x68   /* Alarm Hours Register */
+#define LPC214X_RTC_ALDOM_OFFSET        0x6c   /* Alarm Day Of Month Register */
+#define LPC214X_RTC_ALDOW_OFFSET        0x70   /* Alarm Day Of Week Register */
+#define LPC214X_RTC_ALDOY_OFFSET        0x74   /* Alarm Day Of Year Register */
+#define LPC214X_RTC_ALMON_OFFSET        0x78   /* Alarm Months Register */
+#define LPC214X_RTC_ALYEAR_OFFSET       0x7c   /* Alarm Years Register */
+#define LPC214X_RTC_PREINT_OFFSET       0x80   /* Prescale Value Register (integer) */
+#define LPC214X_RTC_PREFRAC_OFFSET      0x84   /* Prescale Value Register (fraction) */
+
+/* GPIO register offsets */
+
+#define LPC214X_GPIO_PIN_OFFSET         0x00   /* Pin Value Register */
+#define LPC214X_GPIO_SET_OFFSET         0x04   /* Pin Output Set Register */
+#define LPC214X_GPIO_DIR_OFFSET         0x08   /* Pin Direction Register */
+#define LPC214X_GPIO_CLR_OFFSET         0x0c   /* Pin Output Clear Register */
+
+/* Memory Accelerator Module (MAM) Regiser Offsets */
+
+#define LPC214X_MAM_CR_OFFSET           0x00   /* MAM Control Offset*/
+#define LPC214x_MAM_TIM_OFFSET          0x04   /* MAM Timing Offset */
+
+/* Phase Locked Loop (PLL) Register Offsets */
+
+#define LPC214X_PLL_CON_OFFSET          0x00   /* PLL Control Offset*/
+#define LPC214X_PLL_CFG_OFFSET          0x04   /* PLL Configuration Offset */
+#define LPC214X_PLL_STAT_OFFSET         0x08   /* PLL Status Offset */
+#define LPC214X_PLL_FEED_OFFSET         0x0c   /* PLL Feed Offset */
+
+/* PLL Control Register Bit Settings */
+
+#define LPC214X_PLL_CON_PLLE            (1 << 0) /* PLL Enable */
+#define LPC214X_PLL_CON_PLLC            (1 << 1) /* PLL Connect */
+
+/* PLL Configuration Register Bit Settings */
+
+#define LPC214X_PLL_CFG_MSEL            (0x1f << 0) /* PLL Multiplier */
+#define LPC214X_PLL_CFG_PSEL            (0x03 << 5) /* PLL Divider */
+#define LPC214X_PLL_STAT_PLOCK          (1 << 10)   /* PLL Lock Status */
+
+/* Power Control register offsets */
+
+#define LPC214X_PCON_OFFSET             0x00   /* Control Register */
+#define LPC214X_PCONP_OFFSET            0x04   /* Peripherals Register */
+
+/* External Interrupt register offsets */
+
+#define LPC214X_EXT_INT_OFFSET          0x00   /* Flag Register */
+#define LPC214X_EXT_WAKE_OFFSET         0x04   /* Wakeup Register */
+#define LPC214X_EXT_MODE_OFFSET         0x08   /* Mode Register */
+#define LPC214X_EXT_POLAR_OFFSET        0x0c   /* Polarity Register */
+
+/* External Memory Controller (EMC) definitions */
+
+#define LPC214X_BCFG0_OFFSET            0x00   /* BCFG0 Offset */
+#define LPC214X_BCFG1_OFFSET            0x04   /* BCFG1 Offset */
+#define LPC214X_BCFG2_OFFSET            0x08   /* BCFG2 Offset */
+#define LPC214X_BCFG3_OFFSET            0x0c   /* BCFG3 Offset */
+
+/* Vectored Interrupt Controller (VIC) register offsets */
+
+#define LPC214X_VIC_IRQSTATUS_OFFSET    0x00   /* R: IRQ Status Register */
+#define LPC214X_VIC_FIQSTATUS_OFFSET    0x04   /* R: FIQ Status Register */
+#define LPC214X_VIC_RAWINTR_OFFSET      0x08   /* R: Raw Interrupt Status Register */
+#define LPC214X_VIC_INTSELECT_OFFSET    0x0c   /* RW: Interrupt Select Register */
+#define LPC214X_VIC_INTENABLE_OFFSET    0x10   /* RW: Interrupt Enable Register */
+#define LPC214X_VIC_INTENCLEAR_OFFSET   0x14   /* W: Interrupt Enable Clear Register */
+#define LPC214X_VIC_SOFTINT_OFFSET      0x18   /* RW: Software Interrupt Register */
+#define LPC214X_VIC_SOFTINTCLEAR_OFFSET 0x1c   /* W: Software Interrupt Clear Register */
+#define LPC214X_VIC_PROTECTION_OFFSET   0x20   /* Protection Enable Register */
+
+#define LPC214X_VIC_VECTADDR_OFFSET     0x30   /* RW: Vector Address Register */
+#define LPC214X_VIC_DEFVECTADDR_OFFSET  0x34   /* RW: Default Vector Address Register */
+
+#define LPC214X_VIC_VECTADDR0_OFFSET    0x100  /* RW: Vector Address 0 Register */
+#define LPC214X_VIC_VECTADDR1_OFFSET    0x104  /* RW: Vector Address 1 Register */
+#define LPC214X_VIC_VECTADDR2_OFFSET    0x108  /* RW: Vector Address 2 Register */
+#define LPC214X_VIC_VECTADDR3_OFFSET    0x10c  /* RW: Vector Address 3 Register */
+#define LPC214X_VIC_VECTADDR4_OFFSET    0x110  /* RW: Vector Address 4 Register */
+#define LPC214X_VIC_VECTADDR5_OFFSET    0x114  /* RW: Vector Address 5 Register */
+#define LPC214X_VIC_VECTADDR6_OFFSET    0x118  /* RW: Vector Address 6 Register */
+#define LPC214X_VIC_VECTADDR7_OFFSET    0x11c  /* RW: Vector Address 7 Register */
+#define LPC214X_VIC_VECTADDR8_OFFSET    0x120  /* RW: Vector Address 8 Register */
+#define LPC214X_VIC_VECTADDR9_OFFSET    0x124  /* RW: Vector Address 9 Register */
+#define LPC214X_VIC_VECTADDR10_OFFSET   0x128  /* RW: Vector Address 10 Register */
+#define LPC214X_VIC_VECTADDR11_OFFSET   0x12c  /* RW: Vector Address 11 Register */
+#define LPC214X_VIC_VECTADDR12_OFFSET   0x130  /* RW: Vector Address 12 Register */
+#define LPC214X_VIC_VECTADDR13_OFFSET   0x134  /* RW: Vector Address 13 Register */
+#define LPC214X_VIC_VECTADDR14_OFFSET   0x138  /* RW: Vector Address 14 Register */
+#define LPC214X_VIC_VECTADDR15_OFFSET   0x13c  /* RW: Vector Address 15 Register */
+
+#define LPC214X_VIC_VECTCNTL0_OFFSET    0x200  /* RW: Vector Control 0 Register */
+#define LPC214X_VIC_VECTCNTL1_OFFSET    0x204  /* RW: Vector Control 1 Register */
+#define LPC214X_VIC_VECTCNTL2_OFFSET    0x208  /* RW: Vector Control 2 Register */
+#define LPC214X_VIC_VECTCNTL3_OFFSET    0x20c  /* RW: Vector Control 3 Register */
+#define LPC214X_VIC_VECTCNTL4_OFFSET    0x210  /* RW: Vector Control 4 Register */
+#define LPC214X_VIC_VECTCNTL5_OFFSET    0x214  /* RW: Vector Control 5 Register */
+#define LPC214X_VIC_VECTCNTL6_OFFSET    0x218  /* RW: Vector Control 6 Register */
+#define LPC214X_VIC_VECTCNTL7_OFFSET    0x21c  /* RW: Vector Control 7 Register */
+#define LPC214X_VIC_VECTCNTL8_OFFSET    0x220  /* RW: Vector Control 8 Register */
+#define LPC214X_VIC_VECTCNTL9_OFFSET    0x224  /* RW: Vector Control 9 Register */
+#define LPC214X_VIC_VECTCNTL10_OFFSET   0x228  /* RW: Vector Control 10 Register */
+#define LPC214X_VIC_VECTCNTL11_OFFSET   0x22c  /* RW: Vector Control 11 Register */
+#define LPC214X_VIC_VECTCNTL12_OFFSET   0x230  /* RW: Vector Control 12 Register */
+#define LPC214X_VIC_VECTCNTL13_OFFSET   0x234  /* RW: Vector Control 13 Register */
+#define LPC214X_VIC_VECTCNTL14_OFFSET   0x238  /* RW: Vector Control 14 Register */
+#define LPC214X_VIC_VECTCNTL15_OFFSET   0x23c  /* RW: Vector Control 15 Register */
+
+/****************************************************************************************************
+ * Inline Functions
+ ****************************************************************************************************/
+
+/****************************************************************************************************
+ * Global Function Prototypes
+ ****************************************************************************************************/
+
+#endif  /* __LPC214X_CHIP_H */

arch/arm/src/lpc214x/lpc214x_decodeirq.c

@@ -0,0 +1,166 @@
+/********************************************************************************
+ * lpc214x/lpc214x_decodeirq.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ********************************************************************************/
+
+/********************************************************************************
+ * Included Files
+ ********************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <nuttx/irq.h>
+#include <nuttx/arch.h>
+#include <assert.h>
+#include <debug.h>
+
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+#include "lpc214x_vic.h"
+
+/********************************************************************************
+ * Definitions
+ ********************************************************************************/
+
+/********************************************************************************
+ * Private Types
+ ********************************************************************************/
+
+/********************************************************************************
+ * Public Data
+ ********************************************************************************/
+
+/********************************************************************************
+ * Private Data
+ ********************************************************************************/
+
+/* This type arry maps 4 bits into the bit number of the lowest bit that it set */
+
+static uint8 g_nibblemap[16] = { 0, 0, 1, 0, 2, 0, 1, 0, 3, 0, 1, 0, 2, 0, 1, 0 };
+
+/********************************************************************************
+ * Private Functions
+ ********************************************************************************/
+
+/********************************************************************************
+ * Public Funstions
+ ********************************************************************************/
+
+/********************************************************************************
+ * up_decodeirq() and/or lpc214x_decodeirq()
+ *
+ * Description:
+ *   The vectored interrupt controller (VIC) takes 32 interrupt request inputs
+ *   and programmatically assigns them into 3 categories:  FIQ, vectored IRQ,
+ *   and non-vectored IRQ.
+ *
+ *   - FIQs have the highest priority.  There is a single FIQ vector, but multiple
+ *     interrupt sources can be ORed to this FIQ vector.
+ *
+ *   - Vectored IRQs have the middle priority.  Any 16 of the 32 interrupt sources
+ *     can be assigned to vectored IRQs.
+ *
+ *   - Non-vectored IRQs have the lowest priority.
+ *
+ *   The general flow of IRQ processing is to simply read the VIC vector address
+ *   and jump to the address of the vector provided in the register.  The VIC will
+ *   provide the address of the highest priority vectored IRQ.  If a non-vectored
+ *   IRQ is requesting, the address of a default handler is provided.
+ *
+ ********************************************************************************/
+
+#ifndef CONFIG_VECTORED_INTERRUPTS
+void up_decodeirq(uint32 *regs)
+#else
+static void lpc214x_decodeirq( uint32 *regs)
+#endif
+{
+#ifdef CONFIG_SUPPRESS_INTERRUPTS
+  lib_lowprintf("Unexpected IRQ\n");
+  current_regs = regs;
+  PANIC(OSERR_ERREXCEPTION);
+#else
+
+  /* Decode the interrupt. We have to do this by search for the lowest numbered
+   * non-zero bit in the interrupt status register.
+   */
+
+  uint32 pending = vic_getreg(LPC214X_VIC_IRQSTATUS_OFFSET) & 0x007fffff;
+  unsigned int nibble;
+  unsigned int irq_base;
+  unsigned int irq = NR_IRQS;
+
+  /* Search in groups of four bits.  For 22 sources, this is at most six
+   * times through the loop.
+   */
+
+  for (nibble = pending & 0xff, irq_base = 0;
+       pending && irq < NR_IRQS;
+       pending >>= 4, nibble = pending & 0xff, irq_base += 4)
+    {
+      if (nibble)
+        {
+          irq = irq_base + g_nibblemap[nibble];
+          break;
+        }
+    }
+
+  /* Verify that the resulting IRQ number is valid */
+
+  if (irq < NR_IRQS)
+    {
+      /* Current regs non-zero indicates that we are processing an interrupt;
+       * current_regs is also used to manage interrupt level context switches.
+       */
+
+      current_regs = regs;
+
+      /* Deliver the IRQ */
+
+      irq_dispatch(irq, regs);
+
+      /* Indicate that we are no long in an interrupt handler */
+
+      current_regs = NULL;
+    }
+#endif
+}
+
+#ifdef CONFIG_VECTORED_INTERRUPTS
+void up_decodeirq(uint32 *regs)
+{
+  vic_vector_t vector = (vic_vector)vic_getreg(LPC214X_VIC_VECTADDR_OFFSET);
+  vector(regs);
+}
+#endif

arch/arm/src/lpc214x/lpc214x_irq.c

@@ -0,0 +1,219 @@
+/****************************************************************************
+ * lpc214x/lpc214x_irq.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <nuttx/irq.h>
+
+#include "up_arch.h"
+#include "os_internal.h"
+#include "up_internal.h"
+#include "lpc214x_vic.h"
+
+/****************************************************************************
+ * Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+uint32 *current_regs;
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Funtions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_irqinitialize
+ ****************************************************************************/
+
+void up_irqinitialize(void)
+{
+  int reg;
+
+  /* Disable all interrupts.  We do this by writing zero to the IntEnable
+   * register.  This is equivalent to writing all ones to the IntClearEnable
+   * register.
+   */
+
+  vic_putreg(0, LPC214X_VIC_INTENABLE_OFFSET);
+
+  /* Select all IRQs, no FIQs */
+
+  vic_putreg(0, LPC214X_VIC_INTSELECT_OFFSET);
+
+  /* Set the default vector */
+
+  vic_putreg((uint32)up_decodeirq, LPC214X_VIC_DEFVECTADDR_OFFSET);
+
+  /* Disable all vectored interrupts */
+
+  for (reg = LPC214X_VIC_VECTCNTL0_OFFSET;
+       reg <= LPC214X_VIC_VECTCNTL15_OFFSET;
+       reg += 4)
+    {
+      vic_putreg(0, reg);
+    }
+
+  /* currents_regs is non-NULL only while processing an interrupt */
+
+  current_regs = NULL;
+
+  /* And finally, enable interrupts */
+
+#ifndef CONFIG_SUPPRESS_INTERRUPTS
+  irqrestore(SVC_MODE | PSR_F_BIT);
+#endif
+}
+
+/****************************************************************************
+ * Name: up_disable_irq
+ *
+ * Description:
+ *   Disable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_disable_irq(int irq)
+{
+  /* Verify that the IRQ number is within range */
+
+  if (irq < NR_IRQS)
+    {
+      /* Disable the irq by setting the corresponding bit in the VIC
+       * Interrupt Enable Clear register.
+       */
+
+      vic_putreg((1 << irq), LPC214X_VIC_INTENCLEAR_OFFSET);
+    }
+}
+
+/****************************************************************************
+ * Name: up_enable_irq
+ *
+ * Description:
+ *   Enable the IRQ specified by 'irq'
+ *
+ ****************************************************************************/
+
+void up_enable_irq(int irq)
+{
+  /* Verify that the IRQ number is within range */
+
+  if (irq < NR_IRQS)
+    {
+      /* Disable all interrupts */
+
+      irqstate_t flags = irqsave();
+
+      /* Enable the irq by setting the corresponding bit in the VIC
+       * Interrupt Enable register.
+       */
+
+      uint32 val = vic_getreg(LPC214X_VIC_INTENABLE_OFFSET);
+      vic_putreg(val | (1 << irq), LPC214X_VIC_INTENCLEAR_OFFSET);
+      irqrestore(flags);
+    }
+}
+
+/****************************************************************************
+ * Name: up_attach_vector
+ *
+ * Description:
+ *   Attach a user-supplied handler to a vectored interrupt
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_VECTORED_INTERRUPTS
+void up_attach_vector(int irq, int vector, vic_vector_t handler)
+{
+  /* Verify that the IRQ number and vector number are within range */
+
+  if (irq < NR_IRQS && vector < 16 && handler)
+    {
+      int offset = vector << 2;
+
+      /* Disable all interrupts */
+
+      irqstate_t flags = irqsave();
+
+      /* Save the vector address */
+
+      vic_putreg((uint32)handler, LPC214X_VIC_VECTADDR0_OFFSET + offset);
+
+      /* Enable the vectored interrupt */
+
+      vic_putreg(((irq << LPC214X_VECTCNTL_IRQSHIFT) | LPC214X_VECTCNTL_ENABLE),
+		 LPC214X_VIC_VECTCNTL0_OFFSET + offset);
+      irqrestore(flags);
+    }
+}
+#endif
+
+/****************************************************************************
+ * Name: up_detach_vector
+ *
+ * Description:
+ *   Detach a user-supplied handler from a vectored interrupt
+ *
+ ****************************************************************************/
+
+#ifndef CONFIG_VECTORED_INTERRUPTS
+void up_detach_vector(int vector)
+{
+  /* Verify that the vector number is within range */
+
+  if (vector < 16)
+    {
+      /* Disable the vectored interrupt */
+
+      int offset = vector << 2;
+      vic_putreg(0, LPC214X_VIC_VECTCNTL0_OFFSET + offset);
+    }
+}
+#endif

arch/arm/src/lpc214x/lpc214x_lowputc.S

@@ -0,0 +1,198 @@
+/**************************************************************************
+ * lpc214x/lpc214X_lowputc.S
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ **************************************************************************/
+
+/**************************************************************************
+ * Included Files
+ **************************************************************************/
+
+#include <nuttx/config.h>
+#include "up_internal.h"
+#include "up_arch.h"
+#include "lpc214x_uart.h"
+
+/**************************************************************************
+ * Private Definitions
+ **************************************************************************/
+
+#if defined(CONFIG_UART0_SERIAL_CONSOLE)
+#  define LPC214X_UART_BASE    LPC214X_UART0_BASE
+#  define LPC214X_UART_PINSEL  LPC214X_UART0_PINSEL
+#  define LPC214X_UART_PINMASK LPC214X_UART0_PINMASK
+#  define LPC214X_UART_BAUD    CONFIG_UART0_BAUD
+#  define LPC214X_UART_BITS    CONFIG_UART0_BITS
+#  define LPC214X_UART_PARITY  CONFIG_UART0_PARITY
+#  define LPC214X_UART_2STOP   CONFIG_UART0_2STOP
+#elif defined(CONFIG_UART1_SERIAL_CONSOLE)
+#  define LPC214X_UART_BASE    LPC214X_UART1_BASE
+#  define LPC214X_UART_PINSEL  LPC214X_UART1_PINSEL
+#  define LPC214X_UART_PINMASK LPC214X_UART1_PINMASK
+#  define LPC214X_UART_BAUD    CONFIG_UART1_BAUD
+#  define LPC214X_UART_BITS    CONFIG_UART1_BITS
+#  define LPC214X_UART_PARITY  CONFIG_UART1_PARITY
+#  define LPC214X_UART_2STOP   CONFIG_UART1_2STOP
+#else
+#  error "No CONFIG_UARTn_SERIAL_CONSOLE Setting"
+#endif
+
+#if LPC214X_UART_BITS == 5
+#  define LPC214X_LCR_CHAR LPC214X_LCR_CHAR_5
+#elif LPC214X_UART_BITS == 6
+#  define LPC214X_LCR_CHAR LPC214X_LCR_CHAR_6
+#elif LPC214X_UART_BITS == 7
+#  define LPC214X_LCR_CHAR LPC214X_LCR_CHAR_7
+#elif LPC214X_UART_BITS == 8
+#  define LPC214X_LCR_CHAR LPC214X_LCR_CHAR_8
+#else
+#  error "No CONFIG_UARTn_BITS Setting"
+#endif
+
+#if LPC214X_UART_PARITY == 0
+#  define LPC214X_LCR_PAR LPC214X_LCR_PAR_NONE
+#elif LPC214X_UART_PARITY == 1
+#  define LPC214X_LCR_PAR LPC214X_LCR_PAR_ODD
+#elif LPC214X_UART_PARITY == 2
+#  define LPC214X_LCR_PAR LPC214X_LCR_PAR_EVEN
+#elif LPC214X_UART_PARITY == 3
+#  define LPC214X_LCR_PAR LPC214X_LCR_PAR_MARK
+#elif LPC214X_UART_PARITY == 4
+#  define LPC214X_LCR_PAR LPC214X_LCR_PAR_SPACE
+#else
+#  error "No CONFIG_UARTn_PARITY Setting"
+#endif
+
+#ifdef LPC214X_UART_2STOP != 0
+#  define LPC214X_LCR_STOP LPC214X_LCR_STOP_2
+#else
+#  define LPC214X_LCR_STOP LPC214X_LCR_STOP_1
+#endif
+
+#define LPC214X_LCR_VALUE (LPC214X_LCR_CHAR | LPC214X_LCR_PAR | LPC214X_LCR_STOP)
+
+/**************************************************************************
+ * Private Types
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Function Prototypes
+ **************************************************************************/
+
+/**************************************************************************
+ * Global Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Variables
+ **************************************************************************/
+
+/**************************************************************************
+ * Private Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Public Functions
+ **************************************************************************/
+
+/**************************************************************************
+ * Name: up_lowputc
+ **************************************************************************/
+
+/* This assembly language version has the advantage that it can does not
+ * require a C stack and uses only r0-r1.  Hence it can be used during
+ * early boot phases.
+ */
+
+	.text
+	.global	up_lowputc
+	.type	up_lowputc, function
+up_lowputc:
+	/* On entry, r0 holds the character to be printed */
+
+	ldr	r1, =LPC214X_UART_BASE
+	strb	r0, [r1, #LPC214X_UART_THR_OFFSET]
+
+	/* Wait for the byte to be transferred */
+
+1:	ldr	r0, [r1, #LPC214X_UART_LSR_OFFSET]
+	ands	r0, #LPC214X_LSR_TEMT  /* Transmitter empty */
+	beq	1b
+
+	/* And return */
+
+	mov     pc, lr
+	.size	up_lowputc, . - up_lowputc
+
+/* This performs basic initialization of the UART.  This can be called very
+ * early in initialization because it does not depend on having a stack.  It
+ * modifies r0-r2 and r14.
+ */
+
+	.text
+	.globl	up_lowsetup
+	.type	up_lowsetup, function
+up_lowsetup:
+	/* Configure PINSEL0 */
+
+	ldr	r0, =LPC214X_PINSEL0
+	ldr	r1, [r0]
+	ldr	r2, =~LPC214X_UART_PINMASK
+	and	r1, r2
+	ldr	r2, =LPC214X_UART_PINSEL
+	orr	r1, r2
+	str	r1, [r0]
+
+	/* Configure parity, data bits, stop bits and set DLAB=1 */
+
+	ldr	r0, =LPC214X_UART0_BASE
+	mov	r1, #(LPC214X_LCR_VALUE | LPC214X_LCR_DLAB_ENABLE)
+	strb	r1, [r0, #LPC214X_UART_LCR_OFFSET]
+
+	/* Set the BAUD divisor */
+
+	mov	r1, #(UART_BAUD(LPC214X_UART_BAUD) >> 8)
+	strb	r1, [r0, #LPC214X_UART_DLM_OFFSET]
+
+	mov	r1, #(UART_BAUD(LPC214X_UART_BAUD) & 0xff)
+	strb	r1, [r0, #LPC214X_UART_DLL_OFFSET]
+
+	/* Clear DLAB */
+	
+	mov	r1, #LPC214X_LCR_VALUE
+	strb	r1, [r0, #LPC214X_UART_LCR_OFFSET]
+
+	/* And return */
+
+	mov	pc, lr
+	.size	up_lowsetup, . - up_lowsetup
+	.end

arch/arm/src/lpc214x/lpc214x_timer.h

@@ -0,0 +1,152 @@
+/************************************************************************************
+ * lpc214x/lpc214x_timer.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __LPC214X_TIMER_H
+#define __LPC214X_TIMER_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* Timer registers are 8-, 16-bit and 32-bits wide */
+
+/* Timer Interrupt Register Bit Definitions (8-bit) */
+
+#define LPC214X_TMR_IR_MR0I          (1 << 0)  /* Interrupt flag for match channel 0 */
+#define LPC214X_TMR_IR_MR1I          (1 << 1)  /* Interrupt flag for match channel 1 */
+#define LPC214X_TMR_IR_MR2I          (1 << 2)  /* Interrupt flag for match channel 2 */
+#define LPC214X_TMR_IR_MR3I          (1 << 3)  /* Interrupt flag for match channel 3 */
+#define LPC214X_TMR_IR_CR0I          (1 << 4)  /* Interrupt flag for capture channel 0 event */
+#define LPC214X_TMR_IR_CR1I          (1 << 5)  /* Interrupt flag for capture channel 1 event */
+#define LPC214X_TMR_IR_CR2I          (1 << 6)  /* Interrupt flag for capture channel 2 event */
+#define LPC214X_TMR_IR_CR3I          (1 << 7)  /* Interrupt flag for capture channel 3 event */
+#define LPC214X_TMR_IR_ALLI          (0xff)    /* All timer interrupts */
+
+/* Timer Control Register Bit Definitions (8-bits) */
+
+#define LPC214X_TMR_CR_ENABLE        (1 << 0)  /* Counter Enable */
+#define LPC214X_TMR_CR_RESET         (1 << 1)  /* Countger Reset */
+
+/* Timer Counter (32-bits, no bit fields) */
+
+/* Timer Prescale Register Bit Definitions (32-bits, no bit fields) */
+
+/* Timer Prescale Counter Register Bit Definitions */
+
+/* Timer Match Control Register Bit Definitions (16-bit) */
+
+#define LPC214X_TMR_MCR_MR0I         (1 <<  0) /* Enable Interrupt when MR0 matches TC */
+#define LPC214X_TMR_MCR_MR0R         (1 <<  1) /* Enable Reset of TC upon MR0 match */
+#define LPC214X_TMR_MCR_MR0S         (1 <<  2) /* Enable Stop of TC upon MR0 match */
+#define LPC214X_TMR_MCR_MR1I         (1 <<  3) /* Enable Interrupt when MR1 matches TC */
+#define LPC214X_TMR_MCR_MR1R         (1 <<  4) /* Enable Reset of TC upon MR1 match */
+#define LPC214X_TMR_MCR_MR1S         (1 <<  5) /* Enable Stop of TC upon MR1 match */
+#define LPC214X_TMR_MCR_MR2I         (1 <<  6) /* Enable Interrupt when MR2 matches TC */
+#define LPC214X_TMR_MCR_MR2R         (1 <<  7) /* Enable Reset of TC upon MR2 match */
+#define LPC214X_TMR_MCR_MR2S         (1 <<  8) /* Enable Stop of TC upon MR2 match */
+#define LPC214X_TMR_MCR_MR3I         (1 <<  9) /* Enable Interrupt when MR3 matches TC */
+#define LPC214X_TMR_MCR_MR3R         (1 << 10) /* Enable Reset of TC upon MR3 match */
+#define LPC214X_TMR_MCR_MR3S         (1 << 11) /* Enable Stop of TC upon MR3 match */
+
+/* Timer Match Register 0/1/2/3 (32-bits, no bit fields) */
+
+/* Timer Capture Control Register Bit Definitions */
+
+#define LPC214X_TMR_CCR_CAP0RE       (1 <<  0) /* Enable Rising edge on CAPn.0 will load TC to CR0 */
+#define LPC214X_TMR_CCR_CAP0FE       (1 <<  1) /* Enable Falling edge on CAPn.0 will load TC to CR0 */
+#define LPC214X_TMR_CCR_CAP0I        (1 <<  2) /* Enable Interrupt on load of CR0 */
+#define LPC214X_TMR_CCR_CAP1RE       (1 <<  3) /* Enable Rising edge on CAPn.1 will load TC to CR1 */
+#define LPC214X_TMR_CCR_CAP1FE       (1 <<  4) /* Enable Falling edge on CAPn.1 will load TC to CR1 */
+#define LPC214X_TMR_CCR_CAP1I        (1 <<  5) /* Enable Interrupt on load of CR1 */
+#define LPC214X_TMR_CCR_CAP2RE       (1 <<  6) /* Enable Rising edge on CAPn.2 will load TC to CR2 */
+#define LPC214X_TMR_CCR_CAP2FE       (1 <<  7) /* Enable Falling edge on CAPn.2 will load TC to CR2 */
+#define LPC214X_TMR_CCR_CAP2I        (1 <<  8) /* Enable Interrupt on load of CR2 */
+#define LPC214X_TMR_CCR_CAP3RE       (1 <<  9) /* Enable Rising edge on CAPn.3 will load TC to CR3 */
+#define LPC214X_TMR_CCR_CAP3FE       (1 << 10) /* Enable Falling edge on CAPn.3 will load TC to CR3 */
+#define LPC214X_TMR_CCR_CAP3I        (1 << 11) /* Enable Interrupt on load of CR3 */
+
+/* Timer Capture Register 0/1/2/3 (32-bits, no bit fields) */
+
+/* Timer External Match Register Bit Definitions */
+
+#define LPC214X_TMR_EMR_EM0          (1 <<  0) /* External Match 0 */
+#define LPC214X_TMR_EMR_EM1          (1 <<  1) /* External Match 1 */
+#define LPC214X_TMR_EMR_EM2          (1 <<  2) /* External Match 2 */
+#define LPC214X_TMR_EMR_EM3          (1 <<  3) /* External Match 3 */
+
+#define LPC214X_TMR_EMR_EMC0(b)      ((b) <<  4)  /* External match control 0 (see below) */
+#define LPC214X_TMR_EMR_EMC1(b)      ((b) <<  6)  /* External match control 1 (see below) */
+#define LPC214X_TMR_EMR_EMC2(b)      ((b) <<  8)  /* External match control 2 (see below) */
+#define LPC214X_TMR_EMR_EMC3(b)      ((b) << 10)  /* External match control 3 (see below) */
+
+/* EMR External Match Control (EMCn) Field Falues */
+
+#define LPC214X_TMR_EMR_MASK         (3)       /* Mask for all bits */
+#define LPC214X_TMR_EMR_NOOP         (0)       /* Do nothing */
+#define LPC214X_TMR_EMR_CLEAR        (1)       /* Clear corresponding EMn bit/output to 0 */
+#define LPC214X_TMR_EMR_SET          (2)       /* Set corresponding EMn bit/output to 1 */
+#define LPC214X_TMR_EMR_TOGGLE       (3)       /* Toggle corresponding EMn bit/output */
+
+/* Timer Count Control Register Bit Definitions (8-bit) */
+
+#define LPC214X_TMR_
+#define LPC214X_TMR_CTCR_MODE_MASK   (3 << 0) /* Counter/Timer Mode */
+#define   LPC214X_TMR_CTCR_PCLK      (0 << 0) /*   Rising edge of PCLK */
+#define   LPC214X_TMR_CTCR_RISING    (1 << 0) /*   Rising edge of CAP input */
+#define   LPC214X_TMR_CTDR_FALLING   (2 << 0) /*   Failing edge of CAP input */
+#define   LPC214X_TMR_CTCR_BOTH      (3 << 0) /*   Both edges of CAP input */
+#define LPC214X_TMR_CTCR_INPUT_MASK  (3 << 2) /* Counter Input Select */
+#define   LPC214X_TMR_CTCR_CR0       (0 << 2) /*   CAPn.0 */
+#define   LPC214X_TMR_CTCR_CR1       (1 << 2) /*   CAPn.1 */
+#define   LPC214X_TMR_CTCR_CR2       (2 << 2) /*   CAPn.2 */
+#define   LPC214X_TMR_CTCR_CR3       (3 << 2) /*   CAPn.3 */
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif  /* __LPC214X_TIMER_H */

arch/arm/src/lpc214x/lpc214x_timerisr.c

@@ -0,0 +1,162 @@
+/************************************************************
+ * lpc214x/lpc214x_timerisr.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************/
+
+/************************************************************
+ * Included Files
+ ************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <debug.h>
+#include <nuttx/arch.h>
+#include <arch/board/board.h>
+
+#include "clock_internal.h"
+#include "up_internal.h"
+#include "up_arch.h"
+
+#include "lpc214x_timer.h"
+#include "lpc214x_vic.h"
+
+/************************************************************
+ * Definitions
+ ************************************************************/
+
+#define PCLKFREQ (LPC214X_FOSC/4) /* PCLK must be FOSC/4 */
+
+#define tmr_getreg8(o)    getreg8(LPC214X_TMR0_BASE+(o))
+#define tmr_getreg16(o)   getreg16(LPC214X_TMR0_BASE+(o))
+#define tmr_getreg32(o)   getreg32(LPC214X_TMR0_BASE+(o))
+
+#define tmr_putreg8(o,v)  putreg8((v), LPC214X_TMR0_BASE+(o))
+#define tmr_putreg16(o,v) putreg16((v), LPC214X_TMR0_BASE+(o))
+#define tmr_putreg32(o,v) putreg32((v), LPC214X_TMR0_BASE+(o))
+
+/************************************************************
+ * Private Types
+ ************************************************************/
+
+/************************************************************
+ * Private Function Prototypes
+ ************************************************************/
+
+/************************************************************
+ * Global Functions
+ ************************************************************/
+
+/************************************************************
+ * Function:  up_timerisr
+ *
+ * Description:
+ *   The timer ISR will perform a variety of services for
+ *   various portions of the systems.
+ *
+ ************************************************************/
+
+#ifdef CONFIG_VECTORED_INTERRUPTS
+int up_timerisr(uint32 *regs)
+#else
+int up_timerisr(int irq, uint32 *regs)
+#endif
+{
+   /* Process timer interrupt */
+
+   sched_process_timer();
+
+   /* Clear the MR0 match interrupt */
+
+   tmr_putreg8(LPC214X_TMR_IR_MR0I, LPC214X_TMR_IR_OFFSET);
+
+   /* Reset the VIC as well */
+
+#ifdef CONFIG_VECTORED_INTERRUPTS
+   vic_putreg(0, LPC214X_VIC_VECTADDR_OFFSET);
+#endif
+   return 0;
+}
+
+/************************************************************
+ * Function:  up_timerinit
+ *
+ * Description:
+ *   This function is called during start-up to initialize
+ *   the timer interrupt.
+ *
+ ************************************************************/
+
+void up_timerinit(void)
+{
+  uint16 mcr;
+
+  /* Clear all match and capture event interrupts */
+
+  tmr_putreg8(LPC214X_TMR_IR_ALLI, LPC214X_TMR_IR_OFFSET);
+
+  /* Clear the timer counter */
+
+  tmr_putreg32(0, LPC214X_TMR_TC_OFFSET);
+
+  /* No pre-scaler */
+
+  tmr_putreg32(0, LPC214X_TMR_PR_OFFSET);
+
+  /* Set timer match registger to get a TICK_PER_SEC rate
+   * See arch/board.h and sched/os_internal.h
+   */
+
+  tmr_putreg32(LPC214X_PCLKFREQ/TICK_PER_SEC, LPC214X_TMR_MR0_OFFSET);
+
+  /* Reset timer counter regiser and interrupt on match */
+  mcr = tmr_getreg16(LPC214X_TMR_MCR_OFFSET);
+  mcr &= ~LPC214X_TMR_MCR_MR1I;
+  mcr |= (LPC214X_TMR_MCR_MR0I | LPC214X_TMR_MCR_MR0R);
+  tmr_putreg16(mcr, LPC214X_TMR_MCR_OFFSET);
+
+  /* Enable counting */
+
+  tmr_putreg8(LPC214X_TMR_CR_ENABLE, LPC214X_TMR_TCR_OFFSET);
+
+  /* Attach the timer interrupt vector */
+
+#ifdef CONFIG_VECTORED_INTERRUPTS
+  up_attach_vector(LPC214X_IRQ_SYSTIMER, LPC214X_SYSTEMER_VEC, (vic_vector_t)up_timerisr);
+#else
+  (void)irq_attach(LPC214X_IRQ_SYSTIMER, (xcpt_t)up_timerisr);
+#endif
+
+  /* And enable the timer interrupt */
+
+  up_enable_irq(LPC214X_IRQ_SYSTIMER);
+}

arch/arm/src/lpc214x/lpc214x_uart.h

@@ -0,0 +1,142 @@
+/************************************************************************************
+ * lpc214x/uart.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __LPC214X_UART_H
+#define __LPC214X_UART_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <arch/board/board.h> /* For clock settings */
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* PINSEL0 bit definitions for UART0/1 */
+
+#define LPC214X_UART0_PINSEL       0x00000005  /* PINSEL0 value for UART0 */
+#define LPC214X_UART0_PINMASK      0x0000000f  /* PINSEL0 mask for UART0 */
+
+#define LPC214X_UART1_PINSEL       0x00050000  /* PINSEL0 value for UART1 */
+#define LPC214X_UART1_PINMASK      0x000f0000  /* PINSEL0 mask for UART1 */
+
+/* Derive baud divisor setting from clock settings (see board.h) */
+
+#define UART_BAUD(baud)            ((LPC214X_FOSC * LPC214X_PLL_M) / (baud * 16))
+
+/* Interrupt Enable Register (IER) bit definitions */
+
+#define LPC214X_IER_ERBFI          (1 << 0)    /* Enable receive data available int */
+#define LPC214X_IER_ETBEI          (1 << 1)    /* Enable THR empty Interrupt */
+#define LPC214X_IER_ELSI           (1 << 2)    /* Enable receive line status int */
+#define LPC214X_IER_EDSSI          (1 << 3)    /* Enable MODEM atatus interrupt (2146/6/8 UART1 Only) */
+#define LPC214X_IER_ALLIE          0x0f        /* All interrupts */
+
+/* Interrupt ID Register(IIR) bit definitions */
+
+#define LPC214X_IIR_NO_INT         (1 << 0)    /* No interrupts pending  */
+#define LPC214X_IIR_MS_INT         (0 << 1)    /* MODEM Status */
+#define LPC214X_IIR_THRE_INT       (1 << 1)    /* Transmit Holding Register Empty */
+#define LPC214X_IIR_RDA_INT        (2 << 1)    /* Receive Data Available */
+#define LPC214X_IIR_RLS_INT        (3 << 1)    /* Receive Line Status */
+#define LPC214X_IIR_CTI_INT        (6 << 1)    /* Character Timeout Indicator */
+#define LPC214X_IIR_MASK           0x0e
+
+/* FIFO Control Register (FCR) bit definitions */
+
+#define LPC214X_FCR_FIFO_ENABLE    (1 << 0)    /* FIFO wnable */
+#define LPC214X_FCR_RX_FIFO_RESET  (1 << 1)    /* Reset receive FIFO */
+#define LPC214X_FCR_TX_FIFO_RESET  (1 << 2)    /* Reset transmit FIFO */
+#define LPC214X_FCR_FIFO_TRIG1     (0 << 6)    /* Trigger @1 character in FIFO */
+#define LPC214X_FCR_FIFO_TRIG4     (1 << 6)    /* Trigger @4 characters in FIFO */
+#define LPC214X_FCR_FIFO_TRIG8     (2 << 6)    /* Trigger @8 characters in FIFO */
+#define LPC214X_FCR_FIFO_TRIG14    (3 << 6)    /* Trigger @14 characters in FIFO */
+
+/* Line Control Register (LCR) bit definitions */
+
+#define LPC214X_LCR_CHAR_5         (0 << 0)    /* 5-bit character length */
+#define LPC214X_LCR_CHAR_6         (1 << 0)    /* 6-bit character length */
+#define LPC214X_LCR_CHAR_7         (2 << 0)    /* 7-bit character length */
+#define LPC214X_LCR_CHAR_8         (3 << 0)    /* 8-bit character length */
+#define LPC214X_LCR_STOP_1         (0 << 2)    /* 1 stop bit */
+#define LPC214X_LCR_STOP_2         (1 << 2)    /* 2 stop bits */
+#define LPC214X_LCR_PAR_NONE       (0 << 3)    /* No parity */
+#define LPC214X_LCR_PAR_ODD        (1 << 3)    /* Odd parity */
+#define LPC214X_LCR_PAR_EVEN       (3 << 3)    /* Even parity */
+#define LPC214X_LCR_PAR_MARK       (5 << 3)    /* Mark "1" parity */
+#define LPC214X_LCR_PAR_SPACE      (7 << 3)    /* Space "0" parity */
+#define LPC214X_LCR_BREAK_ENABLE   (1 << 6)    /* Output BREAK */
+#define LPC214X_LCR_DLAB_ENABLE    (1 << 7)    /* Enable divisor latch access */
+
+/* Modem Control Register (MCR) bit definitions */
+
+#define LPC214X_MCR_DTR            (1 << 0)    /* Data terminal ready */
+#define LPC214X_MCR_RTS            (1 << 1)    /* Request to send */
+#define LPC214X_MCR_LB             (1 << 4)    /* Loopback */
+
+/* Line Status Register (LSR) bit definitions */
+
+#define LPC214X_LSR_RDR            (1 << 0)    /* Receive data ready */
+#define LPC214X_LSR_OE             (1 << 1)    /* Overrun error */
+#define LPC214X_LSR_PE             (1 << 2)    /* Parity error */
+#define LPC214X_LSR_FE             (1 << 3)    /* Framing error */
+#define LPC214X_LSR_BI             (1 << 4)    /* Break interrupt */
+#define LPC214X_LSR_THRE           (1 << 5)    /* THR empty */
+#define LPC214X_LSR_TEMT           (1 << 6)    /* Transmitter empty */
+#define LPC214X_LSR_RXFE           (1 << 7)    /* Error in receive FIFO */
+#define LPC214X_LSR_ERR_MASK       0x1e
+
+/* Modem Status Register (MSR) bit definitions */
+
+#define LPC214X_MSR_DCTS           (1 << 0)    /* Delta clear to send */
+#define LPC214X_MSR_DDSR           (1 << 1)    /* Delta data set ready */
+#define LPC214X_MSR_TERI           (1 << 2)    /* Trailing edge ring indicator */
+#define LPC214X_MSR_DDCD           (1 << 3)    /* Delta data carrier detect */
+#define LPC214X_MSR_CTS            (1 << 4)    /* Clear to send */
+#define LPC214X_MSR_DSR            (1 << 5)    /* Data set ready */
+#define LPC214X_MSR_RI             (1 << 6)    /* Ring indicator */
+#define LPC214X_MSR_DCD            (1 << 7)    /* Data carrier detect */
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Global Function Prototypes
+ ************************************************************************************/
+
+#endif  /* __LPC214X_UART_H */

arch/arm/src/lpc214x/lpc214x_vic.h

@@ -0,0 +1,70 @@
+/************************************************************************************
+ * lpc214x/lpc214x_vic.h
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __LPC214X_VIC_H
+#define __LPC214X_VIC_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+/************************************************************************************
+ * Definitions
+ ************************************************************************************/
+
+/* All VIC registers are 32-bits wide */
+
+#define vic_getreg(o)   getreg32(LPC214X_VIC_BASE+(o))
+#define vic_putreg(v,o) putreg32((v),LPC214X_VIC_BASE+(o))
+
+/* Vector Control Register bit definitions */
+
+#define LPC214X_VECTCNTL_IRQMASK  (0x0000001f)
+#define LPC214X_VECTCNTL_IRQSHIFT (0)
+#define LPC214X_VECTCNTL_ENABLE   (1 << 5)
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+/************************************************************************************
+ * Inline Functions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Function Prototypes
+ ************************************************************************************/
+
+#endif  /* __LPC214X_VIC_H */

arch/c5471/src/up_unblocktask.c

@@ -101,7 +101,7 @@ void up_unblock_task(_TCB *tcb)
       */
 
 #if CONFIG_RR_INTERVAL > 0
-     tcb->timeslice = CONFIG_RR_INTERVAL;
+     tcb->timeslice = CONFIG_RR_INTERVAL / MSEC_PER_SEC;
 #endif
 
      /* Add the task in the correct location in the prioritized

arch/c5471/src/up_watchdog.c

@@ -365,7 +365,7 @@ int up_wdtinit(void)
 
   /* Register as /dev/wdt */
 
-  ret = register_inode("/dev/wdt", &g_wdtops, 0666, NULL);
+  ret = register_driver("/dev/wdt", &g_wdtops, 0666, NULL);
   if (ret)
     {
       return ERROR;
@@ -384,7 +384,7 @@ int up_wdtinit(void)
   ret = irq_attach(C5471_IRQ_WATCHDOG, wdt_interrupt);
   if (ret)
     {
-      unregister_inode("/dev/wdt");
+      unregister_driver("/dev/wdt");
       return ERROR;
     }
 

arch/dm320/src/up_unblocktask.c

@@ -100,7 +100,7 @@ void up_unblock_task(_TCB *tcb)
       */
 
 #if CONFIG_RR_INTERVAL > 0
-     tcb->timeslice = CONFIG_RR_INTERVAL;
+     tcb->timeslice = CONFIG_RR_INTERVAL / MSEC_PER_SEC;
 #endif
 
      /* Add the task in the correct location in the prioritized

arch/pjrc-8051/src/up_unblocktask.c

@@ -42,6 +42,7 @@
 #include <sched.h>
 #include <debug.h>
 #include <nuttx/arch.h>
+#include "clock_internal.h"
 #include "os_internal.h"
 #include "up_internal.h"
 
@@ -101,7 +102,7 @@ void up_unblock_task(FAR _TCB *tcb)
       */
 
 #if CONFIG_RR_INTERVAL > 0
-     tcb->timeslice = CONFIG_RR_INTERVAL;
+     tcb->timeslice = CONFIG_RR_INTERVAL / MSEC_PER_TICK;
 #endif
 
      /* Add the task in the correct location in the prioritized

arch/sim/src/Makefile

@@ -46,6 +46,10 @@ CSRCS		= up_initialize.c up_idle.c up_interruptcontext.c \
 		  up_releasepending.c up_reprioritizertr.c \
 		  up_exit.c up_schedulesigaction.c up_allocateheap.c \
 		  up_devconsole.c
+ifeq ($(CONFIG_FS_FAT),y)
+CSRCS		+= up_blockdevice.c up_deviceimage.c
+endif
+
 COBJS		= $(CSRCS:.c=$(OBJEXT))
 
 SRCS		= $(ASRCS) $(CSRCS)
@@ -53,6 +57,9 @@ OBJS		= $(AOBJS) $(COBJS)
 
 LDFLAGS		= $(ARCHSCRIPT)
 EXTRA_LIBS	= -lc
+ifeq ($(CONFIG_FS_FAT),y)
+EXTRA_LIBS	+= -lz
+endif
 
 LINKOBJS	= up_head$(OBJEXT)
 LINKLIBS	=

arch/sim/src/up_blockdevice.c

@@ -0,0 +1,201 @@
+/****************************************************************************
+ * up_blockdevice.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include <sys/types.h>
+#include <string.h>
+#include <nuttx/fs.h>
+#include <errno.h>
+
+#include "up_internal.h"
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+#define NSECTORS            2048
+#define LOGICAL_SECTOR_SIZE 512
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+static int     up_open(FAR struct inode *inode);
+static int     up_close(FAR struct inode *inode);
+static ssize_t up_read(FAR struct inode *inode, unsigned char *buffer,
+                       size_t start_sector, unsigned int nsectors);
+static ssize_t up_write(FAR struct inode *inode, const unsigned char *buffer,
+                        size_t start_sector, unsigned int nsectors);
+static int     up_geometry(FAR struct inode *inode, struct geometry *geometry);
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+static const struct block_operations g_bops =
+{
+  .open     = up_open,
+  .close    = up_close,
+  .read     = up_read,
+  .write    = up_write,
+  .geometry = up_geometry,
+};
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_open
+ *
+ * Description: Open the block device
+ *
+ ****************************************************************************/
+
+static int up_open(FAR struct inode *inode)
+{
+  return OK;
+}
+
+/****************************************************************************
+ * Name: up_closel
+ *
+ * Description: close the block device
+ *
+ ****************************************************************************/
+
+static int up_close(FAR struct inode *inode)
+{
+  return OK;
+}
+
+/****************************************************************************
+ * Name: up_read
+ *
+ * Description:  Read the specified numer of sectors
+ *
+ ****************************************************************************/
+
+static ssize_t up_read(FAR struct inode *inode, unsigned char *buffer,
+                       size_t start_sector, unsigned int nsectors)
+{
+  if (inode)
+    {
+      char *src = inode->i_private;
+      if (src &&
+          start_sector < NSECTORS &&
+          start_sector + nsectors < NSECTORS)
+        {
+          memcpy(buffer,
+                 &src[start_sector*LOGICAL_SECTOR_SIZE],
+                 nsectors*LOGICAL_SECTOR_SIZE);
+          return nsectors;
+        }
+    }
+  return -EINVAL;
+}
+
+/****************************************************************************
+ * Name: up_write
+ *
+ * Description: Write the specified number of sectors
+ *
+ ****************************************************************************/
+
+static ssize_t up_write(FAR struct inode *inode, const unsigned char *buffer,
+                        size_t start_sector, unsigned int nsectors)
+{
+  if (inode)
+    {
+      char *dest = inode->i_private;
+      if (dest &&
+          start_sector < NSECTORS &&
+          start_sector + nsectors < NSECTORS)
+        {
+          memcpy(&dest[start_sector*LOGICAL_SECTOR_SIZE],
+                 buffer,
+                 nsectors*LOGICAL_SECTOR_SIZE);
+          return nsectors;
+        }
+    }
+  return -EINVAL;
+}
+
+/****************************************************************************
+ * Name: up_geometry
+ *
+ * Description: Return device geometry
+ *
+ ****************************************************************************/
+
+static int up_geometry(FAR struct inode *inode, struct geometry *geometry)
+ {
+   if (geometry)
+     {
+       geometry->geo_available     = (inode->i_private != NULL);
+       geometry->geo_mediachanged  = FALSE;
+       geometry->geo_writeenabled  = TRUE;
+       geometry->geo_nsectors      = NSECTORS;
+       geometry->geo_sectorsize    = LOGICAL_SECTOR_SIZE;
+       return OK;
+     }
+   return -EINVAL;
+ }
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_registerblockdevice
+ *
+ * Description: Register the simulated block device
+
+ ****************************************************************************/
+
+void up_registerblockdevice(void)
+{
+  /* Inode private data is a filesystem image */
+  void *priv = (void*)up_deviceimage();
+  (void)register_blockdriver("/dev/blkdev", &g_bops, 0, priv);
+}

arch/sim/src/up_devconsole.c

@@ -125,7 +125,7 @@ static ssize_t devconsole_write(struct file *filp, const char *buffer, size_t le
 
 void up_devconsole(void)
 {
-  (void)register_inode("/dev/console", &devconsole_fops, 0666, NULL);
+  (void)register_driver("/dev/console", &devconsole_fops, 0666, NULL);
 }
 
 int up_putc(int ch)

arch/sim/src/up_deviceimage.c

@@ -0,0 +1,357 @@
+/****************************************************************************
+ * up_deviceimage.c
+ *
+ *   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name Gregory Nutt nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#ifdef VFAT_STANDALONE
+# include <stdio.h>
+# include <stdlib.h>
+# include <zlib.h>
+#else
+# include <nuttx/config.h>
+# include <sys/types.h>
+# include <stdlib.h>
+# include <debug.h>
+# include <zlib.h>
+# include "up_internal.h"
+#endif
+
+/****************************************************************************
+ * Private Definitions
+ ****************************************************************************/
+
+#ifdef VFAT_STANDALONE
+# define dbg(format, arg...) printf(format, ##arg)
+#endif
+
+/****************************************************************************
+ * Private Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Function Prototypes
+ ****************************************************************************/
+
+/****************************************************************************
+ * Private Data
+ ****************************************************************************/
+
+/* This array holds a compressed VFAT file system created with:
+ *
+ *   /sbin/mkdosfs -C -F 32 -I -n "NuttXTestVol" -S 512 -v nuttx-test.vfat 1024
+ *   sudo mkdir /mnt/loop
+ *   sudo mount -o loop nuttx-test.vfat /mnt/loop
+ *   mkdir /mnt/loop/TestDir
+ *   echo "This is a test" >/mnt/loop/TestDir/TestFile.txt
+ *   sudo umount /mnt/loop
+ *   gzip nuttx-test.vfat
+ *   xxd -g 1 nuttx-test.vfat.gz >some-file
+ *
+ * Then manually massaged from the gzip xxd output to zlib format.  See
+ * http://www.faqs.org/rfcs/rfc1952.html.  This amounts to:
+ *
+ *   Remove all of the leading bytes through the null terminator of the file name
+ *   Remove the last 8 bytes
+ *   Add 0x08, 0x1d to the beginning.
+ */
+
+static const unsigned char g_vfatdata[] =
+{
+    0x08, 0x1d, 0xed, 0xdd, 0xcf, 0x6a, 0x13, 0x41, 0x18, 0x00, 0xf0, 0xa9, 0x16, 0x5b, 0x2a, 0x6d,
+    0x73, 0x12, 0x3c, 0x39, 0x78, 0xf3, 0xb2, 0x87, 0x0a, 0x3d, 0x78, 0x32, 0xd0, 0x06, 0x0a, 0xa2,
+    0xa5, 0xa6, 0xa5, 0x17, 0x95, 0x2d, 0xd9, 0x6a, 0x68, 0x4c, 0xda, 0xec, 0x8a, 0x2d, 0x78, 0xf3,
+    0x01, 0xf4, 0x39, 0x8a, 0xb7, 0x7a, 0x13, 0xc5, 0x17, 0xe8, 0x5b, 0x78, 0xcb, 0xc5, 0x63, 0x4f,
+    0xc6, 0x8d, 0x69, 0x8b, 0x45, 0xc4, 0x3f, 0x20, 0x51, 0xfc, 0xfd, 0xd8, 0xe1, 0xdb, 0xd9, 0x8f,
+    0x81, 0x59, 0xe6, 0x63, 0x59, 0xd8, 0x85, 0xe9, 0xad, 0xbf, 0x7c, 0xbc, 0xd5, 0xe8, 0xe4, 0x9b,
+    0x79, 0x08, 0xe7, 0xc6, 0x62, 0x38, 0x17, 0x42, 0x98, 0x3c, 0x0a, 0x21, 0x86, 0x9b, 0xe1, 0x44,
+    0xe5, 0x38, 0x0e, 0x72, 0x63, 0xe1, 0x42, 0x38, 0xeb, 0xda, 0xf2, 0xbd, 0x3b, 0xb5, 0xdb, 0x4f,
+    0x8a, 0x62, 0xbd, 0x9e, 0xe5, 0xc5, 0x5a, 0xa7, 0x56, 0xad, 0x5f, 0x9f, 0x8b, 0x31, 0xce, 0x5c,
+    0x79, 0xf7, 0xf4, 0xd9, 0xab, 0xab, 0xef, 0x8b, 0x8b, 0x6b, 0xaf, 0x67, 0xde, 0x4c, 0x84, 0xc3,
+    0xca, 0xfd, 0xde, 0xc7, 0xb9, 0x0f, 0x87, 0x97, 0x0e, 0x2f, 0xf7, 0x3e, 0xd5, 0x1f, 0x35, 0xf3,
+    0x58, 0x1e, 0xed, 0x4e, 0x11, 0xd3, 0xb8, 0xd1, 0xe9, 0x14, 0xe9, 0x46, 0x2b, 0x8b, 0x8d, 0x66,
+    0xbe, 0x95, 0xc4, 0xb8, 0xdc, 0xca, 0xd2, 0x3c, 0x8b, 0xcd, 0x76, 0x9e, 0x75, 0xcf, 0xe4, 0x37,
+    0x5b, 0x9d, 0xed, 0xed, 0xbd, 0x98, 0xb6, 0x1b, 0xd3, 0x53, 0xdb, 0xdd, 0x2c, 0xcf, 0xcb, 0xd3,
+    0xbd, 0xb8, 0x95, 0xed, 0xc5, 0xa2, 0x13, 0x8b, 0x6e, 0x99, 0x79, 0x98, 0x36, 0xdb, 0x31, 0x49,
+    0x92, 0x38, 0x3d, 0x15, 0xf8, 0x91, 0xd5, 0xfd, 0x95, 0x95, 0xb4, 0x3a, 0xea, 0x59, 0xf0, 0x67,
+    0x75, 0xbb, 0xd5, 0xf4, 0xed, 0x44, 0x08, 0xe3, 0xdf, 0x64, 0x56, 0xf7, 0x47, 0x30, 0x1d, 0x00,
+    0x60, 0xc4, 0x7a, 0xde, 0xff, 0xff, 0x63, 0xde, 0xff, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0xfe, 0x76, 0x47, 0xfd, 0xfe, 0x6c, 0xbf, 0x6c, 0x27, 0x71, 0xd0,
+    0x46, 0x3d, 0x27, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0xd7, 0xf8, 0xfe, 0x0f, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0xff, 0xbe, 0xaf, 0x36, 0xee, 0x9c, 0x0c, 0xe1, 0xc6, 0xf3,
+    0x83, 0xf9, 0x83, 0xf9, 0x61, 0x1c, 0xe6, 0xab, 0xf5, 0x90, 0x85, 0x3c, 0x14, 0x61, 0x21, 0xcc,
+    0x86, 0x07, 0xcd, 0xd0, 0x2d, 0xaf, 0xf5, 0xbf, 0x18, 0xc6, 0xfa, 0xe2, 0xdd, 0xfa, 0xc2, 0xd2,
+    0x4a, 0x2c, 0x55, 0x42, 0xe3, 0xc5, 0xf1, 0xf8, 0x41, 0x3c, 0x3f, 0xd2, 0xfb, 0xe2, 0xe7, 0x24,
+    0xf1, 0x54, 0x25, 0x84, 0x9d, 0xe3, 0xf5, 0xdb, 0x39, 0x5d, 0xbf, 0x24, 0xf9, 0x5e, 0x7e, 0x38,
+    0xfe, 0xb4, 0x3e, 0x6a, 0x65, 0x7d, 0xec, 0x36, 0x43, 0xab, 0xec, 0x26, 0x65, 0x77, 0xb7, 0xcc,
+    0x15, 0x65, 0x1b, 0xd4, 0x47, 0x6d, 0xe9, 0xd6, 0x62, 0x7d, 0xbd, 0x1e, 0xcf, 0xd6, 0xc7, 0x78,
+    0xf0, 0xa3, 0xc9, 0xe8, 0x9d, 0x6c, 0xc4, 0x9b, 0xc6, 0xa2, 0x7c, 0x08, 0xd8, 0x33, 0x17, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00, 0x00,
+    0x00, 0x00, 0x00, 0x00, 0x00, 0xe0, 0x77, 0x7d, 0x06
+};
+
+
+/****************************************************************************
+ * Private Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Name: up_deviceimage
+ *
+ * Description: Return an allocated buffer representing an in-memory VFAT
+ *   file system.
+ *
+ ****************************************************************************/
+
+char *up_deviceimage(void)
+{
+    char    *pbuffer;
+    int      bufsize = 1024*1024;
+    int      offset  = 0;
+    z_stream strm;
+    int      ret;
+
+    /* Ininitilize inflate state */
+
+    strm.zalloc   = Z_NULL;
+    strm.zfree    = Z_NULL;
+    strm.opaque   = Z_NULL;
+    strm.avail_in = 0;
+    strm.next_in  = Z_NULL;
+    ret           = inflateInit(&strm);
+    if (ret != Z_OK)
+      {
+        dbg("inflateInit FAILED: ret=%d msg=\"%s\"\n", ret, strm.msg ? strm.msg : "No message" );
+        return NULL;
+      }
+
+    /* Allocate a buffer to hold the decompressed buffer.  We may have
+     * to reallocate this a few times to get the size right.
+     */
+    pbuffer = (char*)malloc(bufsize);
+
+    /* Set up the input buffer */
+
+    strm.avail_in = sizeof(g_vfatdata);
+    strm.next_in = (Bytef*)g_vfatdata;
+
+    /* Run inflate() on input until output buffer not full */
+
+    do {
+        /* Set up to catch the next output chunk in the output buffer */
+
+        strm.avail_out = bufsize - offset;
+        strm.next_out  = (Bytef*)&pbuffer[offset];
+
+        /* inflate */
+
+        ret = inflate(&strm, Z_NO_FLUSH);
+
+        /* Handle inflate() error return values */
+
+        switch (ret)
+          {
+            case Z_NEED_DICT:
+            case Z_DATA_ERROR:
+            case Z_MEM_ERROR:
+            case Z_STREAM_ERROR:
+                dbg("inflate FAILED: ret=%d msg=\"%s\"\n", ret, strm.msg ? strm.msg : "No message" );
+                (void)inflateEnd(&strm);
+                free(pbuffer);
+                return NULL;
+          }
+
+        /* If avail_out is zero, then inflate() returned only
+         * because it is out of buffer space.  In this case, we
+         * will have to reallocate the buffer and try again.
+         */
+
+        if (strm.avail_out == 0)
+          {
+            int newbufsize = bufsize + 128*1024;
+            char *newbuffer = realloc(pbuffer, newbufsize);
+            if (!newbuffer)
+              {
+                free(pbuffer);
+                return NULL;
+              }
+            else
+              {
+                pbuffer = newbuffer;
+                offset  = bufsize;
+                bufsize = newbufsize;
+              }
+          }
+        else
+          {
+             /* There are unused bytes in the buffer, reallocate to
+              * correct size.
+              */
+
+             int newbufsize = bufsize - strm.avail_out;
+             char *newbuffer = realloc(pbuffer, newbufsize);
+             if (!newbuffer)
+               {
+                free(pbuffer);
+                return NULL;
+              }
+            else
+              {
+                pbuffer = newbuffer;
+                bufsize = newbufsize;
+              }
+          }
+    } while (strm.avail_out == 0 && ret != Z_STREAM_END);
+
+    (void)inflateEnd(&strm);
+    return pbuffer;
+}
+
+/****************************************************************************
+ * Name: main
+ *
+ * Description: Used to test decompression logic
+ *
+ *  gcc -g -Wall -DVFAT_STANDALONE -lz -o vfat-test up_deviceimage.c
+ *
+ ****************************************************************************/
+
+#ifdef VFAT_STANDALONE
+int main(int argc, char **argv, char **envp)
+{
+    char *deviceimage;
+    int cmf;
+    int fdict;
+    int flg;
+    int check;
+
+    cmf = g_vfatdata[0];
+    printf("CMF=%02x: CM=%d CINFO=%d\n", cmf, cmf &0x0f, cmf >> 4);
+
+    flg   = g_vfatdata[1];
+    fdict = (flg >> 5) & 1;
+
+    printf("FLG=%02x: FCHECK=%d FDICT=%d FLEVEL=%d\n", flg, flg &0x1f, fdict, flg >> 6);
+
+    /* The FCHECK value must be such that CMF and FLG, when viewed as
+     * a 16-bit unsigned integer stored in MSB order (CMF*256 + FLG),
+     * is a multiple of 31.
+     */
+
+    check = cmf*256 + flg;
+    if (check % 31 != 0)
+    {
+        printf("Fails check: %04x is not a multiple of 31\n", check);
+    }
+
+    deviceimage = up_deviceimage();
+    if (deviceimage)
+    {
+        printf("Inflate SUCCEEDED\n");
+        free(deviceimage);
+        return 0;
+    }
+    else
+    {
+        printf("Inflate FAILED\n");
+        return 1;
+    }
+}
+#endif

arch/sim/src/up_initialize.c

@@ -83,6 +83,7 @@ void up_initialize(void)
 {
   /* Register devices */
 
-  devnull_register();   /* Standard /dev/null */
+  devnull_register();       /* Standard /dev/null */
-  up_devconsole();      /* Our private /dev/console */
+  up_devconsole();          /* Our private /dev/console */
+  up_registerblockdevice(); /* Our simulated block device /dev/blkdev */
 }

arch/sim/src/up_internal.h

@@ -65,6 +65,20 @@
 
 #define SIM_HEAP_SIZE (4*1024*1024)
 
+/* These definitions characterize the compressed filesystem image */
+
+#define BLOCK_COUNT         1024
+#define SECTOR_OF_BACKUPT   6
+#define NUMBER_OF_FATS      2
+#define FAT_SIZE            32
+#define NUM_HIDDEN_SECTORS  0
+#define VOLUME_NAME         "NuttXTestVol"
+#define USE_WHOLE_DEVICE    1
+#define ROOT_DIR_ENTRIES    512
+#define RESERVED_SECTORS    32
+#define SECTORS_PER_CLUSTER 4
+#define LOGICAL_SECTOR_SIZE 512
+
 /**************************************************************************
  * Public Types
  **************************************************************************/
@@ -78,14 +92,20 @@
  **************************************************************************/
 
 #ifndef __ASSEMBLY__
+
 /* up_setjmp.S ************************************************************/
 
 extern int  up_setjmp(int *jb);
 extern void up_longjmp(int *jb, int val) __attribute__ ((noreturn));
 
-/* up_devconsole **********************************************************/
+/* up_devconsole.c ********************************************************/
 
 extern void up_devconsole(void);
+extern void up_registerblockdevice(void);
+
+/* up_deviceimage.c *******************************************************/
+
+extern char *up_deviceimage(void);
 
 #endif /* __ASSEMBLY__ */
 #endif /* __ARCH_UP_INTERNAL_H */

arch/sim/src/up_unblocktask.c

@@ -42,6 +42,7 @@
 #include <sched.h>
 #include <debug.h>
 #include <nuttx/arch.h>
+#include "clock_internal.h"
 #include "os_internal.h"
 #include "up_internal.h"
 
@@ -100,7 +101,7 @@ void up_unblock_task(_TCB *tcb)
       */
 
 #if CONFIG_RR_INTERVAL > 0
-     tcb->timeslice = CONFIG_RR_INTERVAL;
+     tcb->timeslice = CONFIG_RR_INTERVAL / MSEC_PER_TICK;
 #endif
 
      /* Add the task in the correct location in the prioritized

configs/README.txt

@@ -111,6 +111,8 @@ defconfig -- This is a configuration file similar to the Linux
 		CONFIG_ARCH_BOARD - Identifies the configs subdirectory and
 		   hence, the board that supports the particular chip or SoC.
 		CONFIG_ARCH_BOARD_name - For use in C code
+                CONFIG_ENDIAN_BIG - define if big endian (default is little
+                   endian)
 
 	Some architectures require a description of the the RAM configuration:
 
@@ -157,7 +159,7 @@ defconfig -- This is a configuration file similar to the Linux
 	  up waiting tasks.
 
 		CONFIG_DISABLE_CLOCK, CONFIG_DISABLE_POSIX_TIMERS, CONFIG_DISABLE_PTHREAD.
-		CONFIG_DISABLE_SIGNALS, CONFIG_DISABLE_MQUEUE
+		CONFIG_DISABLE_SIGNALS, CONFIG_DISABLE_MQUEUE, CONFIG_DISABLE_MOUNTPOUNT
 
 
 	Misc libc settings
@@ -242,9 +244,15 @@ configs/ntosd-dm320
     STATUS: This port is code complete, verified, and included in the
     NuttX 0.2.1 release.
 
+configs/mcu123-lpc214x
+    This port is for the NXP LPC2148 as provided on the mcu123.com
+    lpc214x development board.
+    STATUS: This port is in progress and should be available in the
+    nuttx-0.2.5 release.
+
 configs/m68322evb
     This is a work in progress for the venerable m68322evb board from
-    Motorola.
+    Motorola. This OS is also built with the the arm-elf toolchain*.
 
 configs/pjrc-8051
     8051 Microcontroller.  This port uses the PJRC 87C52 development system

configs/c5471evm/defconfig

@@ -46,6 +46,7 @@
 #   the board that supports the particular chip or SoC.
 # CONFIG_ARCH_BOARD_name - for use in C code
 # CONFIG_BOARD_LOOPSPERMSEC - for delay loops
+# CONFIG_ENDIAN_BIG - define if big endian (default is little endian)
 # CONFIG_ROM_VECTORS - unique to c5471
 # CONFIG_DRAM_END - the size of installed DRAM.
 #   Unique to c5471
@@ -156,6 +157,7 @@ CONFIG_DISABLE_POSIX_TIMERS=n
 CONFIG_DISABLE_PTHREAD=n
 CONFIG_DISABLE_SIGNALS=n
 CONFIG_DISABLE_MQUEUE=n
+CONFIG_DISABLE_MOUNTPOINT=y
 
 #
 # Misc libc settings

configs/m68332evb/defconfig

@@ -43,6 +43,7 @@
 # CONFIG_ARCH_BOARD - identifies the configs subdirectory and, hence,
 #   the board that supports the particular chip or SoC.
 # CONFIG_ARCH_BOARD_name - for use in C code
+# CONFIG_ENDIAN_BIG - define if big endian (default is little endian)
 # CONFIG_DRAM_SIZE - Describes the installed DRAM.
 # CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
 #
@@ -145,6 +146,7 @@ CONFIG_DISABLE_POSIX_TIMERS=n
 CONFIG_DISABLE_PTHREAD=n
 CONFIG_DISABLE_SIGNALS=n
 CONFIG_DISABLE_MQUEUE=n
+CONFIG_DISABLE_MOUNTPOINT=y
 
 #
 # Misc libc settings

configs/mcu123-lpc214x/Make.defs

@@ -0,0 +1,71 @@
+############################################################
+# Make.defs
+#
+#   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name Gregory Nutt nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################
+
+include ${TOPDIR}/.config
+
+ifeq ("${CONFIG_DEBUG}","y")
+  ARCHOPTIMIZATION	= -g
+else
+  ARCHOPTIMIZATION	= -Os -fno-strict-aliasing -fno-strength-reduce \
+			  -fomit-frame-pointer
+endif
+
+ARCHCPUFLAGS		= -mapcs-32 -mcpu=arm7tdmi -msoft-float -fno-builtin
+ARCHPICFLAGS		= -fpic
+ARCHWARNINGS		= -Wall -Wstrict-prototypes -Wshadow
+ARCHDEFINES		=
+ARCHINCLUDES		= -I. -isystem $(TOPDIR)/include
+ARCHSCRIPT		= -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/ld.script
+
+CROSSDEV		= arm-elf-
+CC			= $(CROSSDEV)gcc
+LD			= $(CROSSDEV)ld
+AR			= $(CROSSDEV)ar rcs
+NM			= $(CROSSDEV)nm
+OBJCOPY			= $(CROSSDEV)objcopy
+OBJDUMP			= $(CROSSDEV)objdump
+
+CFLAGS			= $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \
+			  $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) -pipe
+
+OBJEXT			= .o
+LIBEXT			= .a
+EXEEXT			=
+
+ifeq ("${CONFIG_DEBUG}","y")
+  LDFLAGS		+= -g
+endif
+
+

configs/mcu123-lpc214x/defconfig

@@ -0,0 +1,280 @@
+############################################################
+# defconfig
+#
+#   Copyright (C) 2007 Gregory Nutt. All rights reserved.
+#   Author: Gregory Nutt <spudmonkey@racsa.co.cr>
+#
+# Redistribution and use in source and binary forms, with or without
+# modification, are permitted provided that the following conditions
+# are met:
+#
+# 1. Redistributions of source code must retain the above copyright
+#    notice, this list of conditions and the following disclaimer.
+# 2. Redistributions in binary form must reproduce the above copyright
+#    notice, this list of conditions and the following disclaimer in
+#    the documentation and/or other materials provided with the
+#    distribution.
+# 3. Neither the name Gregory Nutt nor the names of its contributors may be
+#    used to endorse or promote products derived from this software
+#    without specific prior written permission.
+#
+# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+# POSSIBILITY OF SUCH DAMAGE.
+#
+############################################################
+#
+# architecture selection
+#
+# CONFIG_ARCH - identifies the arch subdirectory and, hence, the
+#   processor architecture.
+# CONFIG_ARCH_name - for use in C code.  This identifies the
+#   particular chip or SoC that the architecture is implemented
+#   in.
+# CONFIG_ARCH_CHIP - Identifies the arch/*/chip subdirectory
+# CONFIG_ARCH_CHIP_name - For use in C code
+# CONFIG_ARCH_BOARD - identifies the configs subdirectory and, hence,
+#   the board that supports the particular chip or SoC.
+# CONFIG_ENDIAN_BIG - define if big endian (default is little endian)
+# CONFIG_ARCH_BOARD_name - for use in C code
+# CONFIG_BOARD_LOOPSPERMSEC - for delay loops
+# CONFIG_ARCH_LEDS - Use LEDs to show state. Unique to lpc2148.
+# CONFIG_DRAM_SIZE - Describes the internal DRAM.
+# CONFIG_DRAM_START - The start address of internal DRAM
+# CONFIG_ARCH_STACKDUMP - Do stack dumps after assertions
+#
+CONFIG_ARCH=arm
+CONFIG_ARCH_CHIP=lpc214x
+CONFIG_ARCH_LPC2148=y
+CONFIG_ARCH_BOARD=mcu123-lpc214x
+CONFIG_ARCH_BOARD_MCU123=y
+CONFIG_BOARD_LOOPSPERMSEC=1250
+CONFIG_ARCH_LEDS=n
+CONFIG_DRAM_SIZE=0x02000000
+CONFIG_DRAM_START=0x40000000
+CONFIG_DRAM_END=(CONFIG_DRAM_START+CONFIG_DRAM_SIZE)
+CONFIG_ARCH_STACKDUMP=y
+
+#
+# LPC2148 specific chip initialization
+#
+CONFIG_EXTMEM_MODE=n
+CONFIG_RAM_MODE=n
+CONFIG_CODE_BASE=0x00000000
+CONFIG_PLL_SETUP=y
+CONFIG_MAM_SETUP=y
+CONFIG_VPBDIV_SETUP=y
+CONFIG_EMC_SETUP=n
+CONFIG_BCFG0_SETUP=n
+CONFIG_BCFG1_SETUP=n
+CONFIG_BCFG2_SETUP=n
+CONFIG_BCFG3_SETUP=n
+CONFIG_ADC_SETUP=y
+
+#
+# LPC214X specific device driver settings
+#
+# CONFIG_UARTn_SERIAL_CONSOLE - selects the UARTn for the
+#   console and ttys0 (default is the UART0).
+# CONFIG_UARTn_RXBUFSIZE - Characters are buffered as received.
+#   This specific the size of the receive buffer
+# CONFIG_UARTn_TXBUFSIZE - Characters are buffered before
+#   being sent.  This specific the size of the transmit buffer
+# CONFIG_UARTn_BAUD - The configure BAUD of the UART.  Must be
+# CONFIG_UARTn_BITS - The number of bits.  Must be either 7 or 8.
+# CONFIG_UARTn_PARTIY - 0=no parity, 1=odd parity, 2=even parity, 3=mark 1, 4=space 0
+# CONFIG_UARTn_2STOP - Two stop bits
+#
+CONFIG_UART0_SERIAL_CONSOLE=y
+CONFIG_UART1_SERIAL_CONSOLE=n
+CONFIG_UART0_TXBUFSIZE=256
+CONFIG_UART1_TXBUFSIZE=256
+CONFIG_UART0_RXBUFSIZE=256
+CONFIG_UART1_RXBUFSIZE=256
+CONFIG_UART0_BAUD=115200
+CONFIG_UART1_BAUD=115200
+CONFIG_UART0_BITS=8
+CONFIG_UART1_BITS=8
+CONFIG_UART0_PARITY=0
+CONFIG_UART1_PARITY=0
+CONFIG_UART0_2STOP=0
+CONFIG_UART1_2STOP=0
+
+#
+# General OS setup
+#
+# CONFIG_EXAMPLE - identifies the subdirectory in examples
+#   that will be used in the build
+# CONFIG_DEBUG - enables built-in debug options
+# CONFIG_DEBUG_VERBOSE - enables verbose debug output
+# CONFIG_MM_REGIONS - If the architecture includes multiple
+#   regions of memory to allocate from, this specifies the
+#   number of memory regions that the memory manager must
+#   handle and enables the API mm_addregion(start, end);
+# CONFIG_HAVE_LOWPUTC - architecture supports low-level, boot
+#   time console output
+# CONFIG_RR_INTERVAL - The round robin timeslice will be set
+#   this number of milliseconds;  Round robin scheduling can
+#   be disabled by setting this value to zero.
+# CONFIG_SCHED_INSTRUMENTATION - enables instrumentation in 
+#   scheduler to monitor system performance
+# CONFIG_TASK_NAME_SIZE - Spcifies that maximum size of a
+#   task name to save in the TCB.  Useful if scheduler
+#   instrumentation is selected.  Set to zero to disable.
+# CONFIG_START_YEAR, CONFIG_START_MONTH, CONFIG_START_DAY -
+#   Used to initialize the internal time logic.
+# CONFIG_JULIAN_TIME - Enables Julian time conversions
+# CONFIG_DEV_CONSOLE - Set if architecture-specific logic
+#   provides /dev/console.  Enables stdout, stderr, stdin.
+#
+CONFIG_EXAMPLE=ostest
+CONFIG_DEBUG=n
+CONFIG_DEBUG_VERBOSE=n
+CONFIG_MM_REGIONS=1
+CONFIG_ARCH_LOWPUTC=y
+CONFIG_RR_INTERVAL=200
+CONFIG_SCHED_INSTRUMENTATION=n
+CONFIG_TASK_NAME_SIZE=0
+CONFIG_START_YEAR=2007
+CONFIG_START_MONTH=2
+CONFIG_START_DAY=13
+CONFIG_JULIAN_TIME=n
+CONFIG_DEV_CONSOLE=y
+
+#
+# The following can be used to disable categories of
+# APIs supported by the OS.  If the compiler supports
+# weak functions, then it should not be necessary to
+# disable functions unless you want to restrict usage
+# of those APIs.
+#
+# There are certain dependency relationships in these
+# features.
+#
+# o mq_notify logic depends on signals to awaken tasks
+#   waiting for queues to become full or empty.
+# o pthread_condtimedwait() depends on signals to wake
+#   up waiting tasks.
+#
+CONFIG_DISABLE_CLOCK=n
+CONFIG_DISABLE_POSIX_TIMERS=n
+CONFIG_DISABLE_PTHREAD=n
+CONFIG_DISABLE_SIGNALS=n
+CONFIG_DISABLE_MQUEUE=n
+CONFIG_DISABLE_MOUNTPOINT=y
+
+#
+# Misc libc settings
+#
+# CONFIG_NOPRINTF_FIELDWIDTH - sprintf-related logic is a
+#   little smaller if we do not support fieldwidthes
+#
+CONFIG_NOPRINTF_FIELDWIDTH=n
+
+#
+# Allow for architecture optimized implementations
+#
+# The architecture can provide optimized versions of the
+# following to improve sysem performance
+#
+CONFIG_ARCH_MEMCPY=n
+CONFIG_ARCH_MEMCMP=n
+CONFIG_ARCH_MEMMOVE=n
+CONFIG_ARCH_MEMSET=n
+CONFIG_ARCH_STRCMP=n
+CONFIG_ARCH_STRCPY=n
+CONFIG_ARCH_STRNCPY=n
+CONFIG_ARCH_STRLEN=n
+CONFIG_ARCH_BZERO=n
+CONFIG_ARCH_KMALLOC=n
+CONFIG_ARCH_KZMALLOC=n
+CONFIG_ARCH_KFREE=n
+
+#
+# General build options
+#
+# CONFIG_RRLOAD_BINARY - make the rrload binary format used with
+#   BSPs from www.ridgerun.com
+#
+CONFIG_RRLOAD_BINARY=y
+
+#
+# Sizes of configurable things (0 disables)
+#
+# CONFIG_MAX_TASKS - The maximum number of simultaneously
+#   active tasks.  This value must be a power of two.
+# CONFIG_MAX_TASK_ARGS - This controls the maximum number of
+#   of parameters that a task may receive (i.e., maxmum value
+#   of 'argc')
+# CONFIG_NPTHREAD_KEYS - The number of items of thread-
+#   specific data that can be retained
+# CONFIG_NFILE_DESCRIPTORS - The maximum number of file
+#   descriptors (one for each open)
+# CONFIG_NFILE_STREAMS - The maximum number of streams that
+#   can be fopen'ed
+# CONFIG_NAME_MAX - The maximum size of a file name.
+# CONFIG_STDIO_BUFFER_SIZE - Size of the buffer to allocate
+#   on fopen. (Only if CONFIG_NFILE_STREAMS > 0)
+# CONFIG_NUNGET_CHARS - Number of characters that can be
+#   buffered by ungetc() (Only if CONFIG_NFILE_STREAMS > 0)
+# CONFIG_PREALLOC_MQ_MSGS - The number of pre-allocated message
+#   structures.  The system manages a pool of preallocated
+#   message structures to minimize dynamic allocations
+# CONFIG_MQ_MAXMSGSIZE - Message structures are allocated with
+#   a fixed payload size given by this settin (does not include
+#   other message structure overhead.
+# CONFIG_MAX_WDOGPARMS - Maximum number of parameters that
+#   can be passed to a watchdog handler
+# CONFIG_PREALLOC_WDOGS - The number of pre-allocated watchdog
+#   structures.  The system manages a pool of preallocated
+#   watchdog structures to minimize dynamic allocations
+# CONFIG_PREALLOC_TIMERS - The number of pre-allocated POSIX
+#   timer structures.  The system manages a pool of preallocated
+#   timer structures to minimize dynamic allocations.  Set to
+#   zero for all dynamic allocations.
+#
+CONFIG_MAX_TASKS=64
+CONFIG_MAX_TASK_ARGS=4
+CONFIG_NPTHREAD_KEYS=4
+CONFIG_NFILE_DESCRIPTORS=32
+CONFIG_NFILE_STREAMS=16
+CONFIG_NAME_MAX=32
+CONFIG_STDIO_BUFFER_SIZE=1024
+CONFIG_NUNGET_CHARS=2
+CONFIG_PREALLOC_MQ_MSGS=32
+CONFIG_MQ_MAXMSGSIZE=32
+CONFIG_MAX_WDOGPARMS=4
+CONFIG_PREALLOC_WDOGS=32
+CONFIG_PREALLOC_TIMERS=8
+
+#
+# Stack and heap information
+#
+# CONFIG_BOOT_FROM_FLASH - Some configurations support XIP
+#   operation from FLASH.
+# CONFIG_CUSTOM_STACK - The up_ implementation will handle
+#   all stack operations outside of the nuttx model.
+# CONFIG_STACK_POINTER - The initial stack pointer (arm7tdmi only)
+# CONFIG_PROC_STACK_SIZE - The size of the initial stack
+# CONFIG_PTHREAD_STACK_MIN - Minimum pthread stack size
+# CONFIG_PTHREAD_STACK_DEFAULT - Default pthread stack size
+# CONFIG_HEAP_BASE - The beginning of the heap
+# CONFIG_HEAP_SIZE - The size of the heap
+#
+CONFIG_BOOT_FROM_FLASH=n
+CONFIG_CUSTOM_STACK=n
+CONFIG_STACK_POINTER=
+CONFIG_PROC_STACK_SIZE=4096
+CONFIG_PTHREAD_STACK_MIN=256
+CONFIG_PTHREAD_STACK_DEFAULT=4096
+CONFIG_HEAP_BASE=
+CONFIG_HEAP_SIZE=

configs/mcu123-lpc214x/include/README.txt

@@ -0,0 +1 @@
+This directory contains header files unique to the MCU123 LPC2148 board.