 Gregory Nutt
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190cbc766e
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Need to enable FIQ in initial task state; Improve H32/64 test in IRQ handling
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2014-06-21 09:55:09 -06:00 |
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Gregory Nutt
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3f6b1642ca
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SAMA5D4: Add support for secure/FIQ interrupts; SAIC supports need to be be enabled unconditionally
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2014-06-20 18:16:41 -06:00 |
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Gregory Nutt
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f8024cf409
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More trailing whilespace removal
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2014-04-13 16:22:22 -06:00 |
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Gregory Nutt
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ab729802be
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Oops. Mnemonic changed from SWI to SVC in cortex A
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2014-01-05 15:59:49 -06:00 |
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Gregory Nutt
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8bc6125b3c
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Add ARMv7-A syscall.h header file
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2014-01-05 15:49:06 -06:00 |
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Gregory Nutt
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7dfef5e22e
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SAMA5: Modification of some CPSR-related inline functions
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2013-07-31 09:11:24 -06:00 |
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Gregory Nutt
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2c6b370c4a
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Add ARMv7-A irqdisable() inline function
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2013-07-30 11:37:09 -06:00 |
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Gregory Nutt
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535048a73c
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Improve some ARMv7-A/M floating point register save time; Add floating point register save logic for ARMv7-A
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2013-07-23 17:52:06 -06:00 |
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Gregory Nutt
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5bbc86f894
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SAMA5/Cortex-A: Improve irqsave/restore inlines + add irqenable. Add skeleton file for SAMA5 interrupt management. Also change from last commit that was left in the editor
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2013-07-21 17:08:40 -06:00 |
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Gregory Nutt
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8f2ad7eec1
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Some initial frame for Cortex-A5 support. No much yet
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2013-07-18 15:20:47 -06:00 |
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