* arch/arm/src/tiva/Make.defs: Compile only when enabled by configuration CONFIG_ARM_SEMIHOSTING_HOSTFS
* arch/arm/src/common/up_hostfs.c: Remove the ifdef conditional because it's redundant with the make logic.
Largely copy-and-paste from stm32f4discovery.
Also arch/arm/src/armv7-m/mpu.h: Ensure RBAR alignment
Fix crashes on init task startup I observed on qemu-system-arm -M lm3s6965evb.
And remove syslog_init_e because all initialization is later now and we don't
distinguish the initialition phase anymore after ramlog don't need special
initialize.
Because we can get the same function by CONSOLE_SYSLOG/syslog_console_init.
BTW, it isn't a good choice to use g_ramlogfops as /dev/console since nsh
will read back what it send out which will surprise most people.
it doesn't make sense that iob initialization is in up_initialize
but other memory components initialization is called in nx_start
Change-Id: Id43aeaa995f340c5943f59a0067a483ff3ac34a2
Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
To ensure size_t same as toolchain definition in the first place and rename CXX_NEWLONG to ARCH_SIZET_LONG. The change also check whether __SIZE_TYPE__ exist before CONFIG_ARCH_SIZET_LONG so our definition can align with toolchain(gcc/clang) definition automatically.
Currently up_allocate_heap() assumes that g_idle_topstack points
top of the heap memory. However, g_idle_topstack pointed incorrect
address in SMP mode which resulted in heap corruption. This PR
moves g_idle_topstack at the end of .noinit to avoid this issue.
Signed-off-by: Masayuki Ishikawa <Masayuki.Ishikawa@jp.sony.com>
Call xxx_timer_initialize from clock subsystem to make timer ready for use as soon as possiblei and revert the workaround:
commit 0863e771a9
Author: Gregory Nutt <gnutt@nuttx.org>
Date: Fri Apr 26 07:24:57 2019 -0600
Revert "sched/clock/clock_initialize.c: clock_inittime() needs to be done with CONFIG_SCHED_TICKLESS and clock_initialize should skip clock_inittime() for external RTC case since the RTC isn't ready yet."
This reverts commit 2bc709d4b9.
Commit 2bc709d4b9 was intended to handle the case where up_timer_gettime may not start from zero case. However, this change has the side-effect of breaking every implementation of tickless mode: After this change the tickless timer structures are used before they are initialized in clock_inittime(). Initialization happens later when up_initialize is called() when arm_timer_initialize().
Since the tickless mode timer is very special, one solution might be to
1. Rename xxx_timer_initialize to up_timer_initialize
2 Move up_timer_initialize to include/nuttx/arch.h
3. Call it from clock subsystem instead up_initialize
Basically, this change make timer initialization almost same as rtc initialization(up_rtc_initialize).
For now, however, we just need to revert the change.
* S32K add support for Nxp drone boards
* Update arch/arm/src/s32k1xx/hardware/s32k1xx_rtc.h codestyle
Co-Authored-By: David Sidrane <David.Sidrane@Nscdg.com>
Co-authored-by: Jari van Ewijk <jari.vanewijk@nxp.com>
Co-authored-by: David Sidrane <David.Sidrane@Nscdg.com>
* Serial Fixed interrupt storm
The target would randomly hang in the serial isr.
The priv->ie and the hardware were inconsistent.
The isr used the priv->ie to gate offloading
the RX data. Bang! Hung.
imxrt_disableuartint(priv, &ie);
ret = imxrt_setup(dev);
/* Restore the interrupt state */
imxrt_restoreuartint(priv, ie);
interrupt-> Of no return
priv->ie = ie;
On a fast cpu with FIFO, this will not work
with out proper protections.
* Serial: Conditionally enable 9 bit mode
* armv7-mi/mpu.hi: Restructure API
Preserve the existing API and enabled better granualriy on
setting.
* Enable MPU for non protected builds to set cache
* mpuinit use symbolic values for addresses
* Allow DTCM on HEAP
* allocateheap Fix Coding style
All STM32L4 MPUs have FLASH_CR_PNB bits (8 bits), and some MPUs have FLASH_CR_BKER bit to change bank if page >= 256.
The code wasn't setting or clearing FLASH_CR_BKER correctly.
Author: Gregory Nutt <gnutt@nuttx.org>
Run .c modified by the PR through tools/nxstyle and correct all reporting coding style problems noted in the file.
Author: Satoshi Togawa <togawa@develcb210.centurysys.co.jp>
STM32L4: Add workaround of data cache corruption on RWW.
Some STM32L4 chips has eratta "Data cache might be corrupted during Flash Read While Write operation". This is also in STM32, and arch/arm/src/stm32/stm32f20xxf40xx_flash.c has workaround.
To enable this workaround, define CONFIG_STM32L4_FLASH_WORKAROUND_DATA_CACHE_CORRUPTION_ON_RWW.
Gregory Nutt
klmchp
YAMAMOTO Takashi
Masayuki Ishikawa
Xiang Xiao
Nathan Hartman
Juha Niskanen
Nicholas Chin
Nicholas C
liuguo09
Peter van der Perk
David Sidrane
Peter van der Perk
Alan Carvalho de Assis
Beat Küng
Dave Marples
taikoyaP
Satoshi Togawa