Toolchain.defs file was treating all supported chips as AVR128DA28,
which became apparent while testing changes in USART handling.
Signed-off-by: Kerogit <kr.git@kerogit.eu>
This commit adds support for SPI_SETDELAY operation on SAMv7 QSPI
peripheral running in SPI mode. The logic is the same as for standard
SPI peripheral, just different registers. The change allows to set
custom delays between transfers, chip selects and so on.
Signed-off-by: Michal Lenc <michallenc@seznam.cz>
This add support for using the cryptographic accelerator
within the ESP32 for HMAC-SHA operations. The supported
algorithms are: SHA1 and SHA512.
Signed-off-by: Vlad Pruteanu <pruteanuvlad1611@yahoo.com>
During I2C read, one-too-many byte is read, which can lead to the I2C bus
getting stuck. This is likely due to the STOP condition being set at the
wrong time or being missed completely. The chip offers a shortcut, such
that the STOP condition is set automatically after the last byte is being
written/read.
Signed-off-by: Max Kriegleder <max.kriegleder@gmail.com>
Since the bl602 do not support the atomic extention, we should compile
it with `-march=rv32imfc`, or it will fail to boot when executing the
`lr.w` instruction.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
When TICKLESS not enabled, up_alarm_set_lowerhalf will call start, if we
overwrite the compare register will cause TICK mode no longer isr.
Signed-off-by: buxiasen <buxiasen@xiaomi.com>
In multi-core environment where NuttX runs on each core, if one core
sets the RTC time, the RTC value gotten on other cores is incorrect.
This is caused by clock_gettime(CLOCK_MONOTONIC) function used to get
elapsed time, which uses a core-specific global varaiable g_basetime
as the base time.
To fix this, update the g_basetime from the backup SRAM that can be
shared between cores in setting/getting the RTC time.
Signed-off-by: SPRESENSE <41312067+SPRESENSE@users.noreply.github.com>
Add a function imx9_lpspi_select_cs to assert CS at the start of
an SPI transfer and keep it asserted until called again to
de-assert it. This can be called by board-provided imx9_lpspi_select,
in case the CS needs to be controlled via the LPSPI block and not
GPIO.
The TCR register CONT (continue) bit is asserted to prevent CS toggling
during the transfer, and the PCS bits are set to mark the correct CS
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
According to the TRM, only bits 24-25 are reserved for chip select, and
the maximum number of internal chip selects is 3 (on LPSPI4 bus only).
Fix the TCR_PCS_MASK and remove extra definitions.
Signed-off-by: Jukka Laitinen <jukka.laitinen@tii.ae>
Directly downloading the Git repository is inconvenient for local debugging.
This will allow to automatically download external packages from the Internet.
If not set, the repo need to be download will need to provide them manually,
otherwise an error will occur and the build will be aborted.
Add `USE_NXTMPDIR_ESP_REPO_DIRECTLY`, with this we can use
`USE_NXTMPDIR_ESP_REPO_DIRECTLY=y make` which can directly use esp-hal-3rdparty
under nxtmpdir without CLONE, CHECK_COMMITSHA, reset, checkout and update. Just
`cp -rf nxtmpdir/esp-hal-3rdparty chip/$(ESP_HAL_3RDPARTY_REPO)`.
Signed-off-by: v-tangmeng <v-tangmeng@xiaomi.com>
- Added PWM driver support for the RA4M1 microcontroller using the GPT timer.
- This driver supports Saw-wave mode and one of the two output channels (A or B).
- Added necessary configurations in CMakeLists.txt, Kconfig, and Make.defs.
- Created new header file for GPT.
Signed-off-by: leocafonso <leocafonso@gmail.com>
If the initial value of the MSR_IA32_TSC_ADJUST register is not 0 (may be modified by BIOS or bootloader), it may cause timing errors. This commit addressed the issue.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
On newer x86 CPUs, the MSR_IA32_TSC_ADJUST register is utilized to fine-tune the offset of the Time Stamp Counter (TSC). This commit introduces support for MSR_IA32_TSC_ADJUST and enhances the TSC tickless
driver, optimizing its performance.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
This commit aligned the arm64 generic timer count to the tick boundary. Notice that this is just a work-around. We should pass both the current system ticks and the delay ticks as input parameters. But we only have the delay tick here due to the oneshot interfaces.
Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
