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configs/metro-m4: Fix problem with SysTick timer running too fast. This turned out to be a dumb typo in board.h that was providing the wrong CPU frequency to the SysTick setup logic.
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@@ -32,15 +32,11 @@ STATUS
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======
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2018-07-26: The basic port was merged into master. It is still
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2018-07-26: The basic port was merged into master. It is still
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incomplete and untested. It is missing the clock configuration logic.
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incomplete and untested.
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There is a placeholder from the SAML21, but it is currently stubbed out
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in the Make.defs file. Configuration options in the board.h header
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file are bogus and also just cloned from the SAML21.
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2018-07-29: Clock configuration logic now complete. board.h
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2018-07-29: Code complete. Clock configuration complete. Unverified
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configuration options still need to be verified. Unverified SERCOM
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SERCOM USART, SPI, I2C, Port configuration, and DMA support have been
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USART, SPI, I2C, Port configuration, and DMA support have been added.
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added. I still have no hardware in hand to test.
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I still have no hardware in hand to test.
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2018-07-20: Brought in the USB driver from the SAML21. It is the same
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2018-07-20: Brought in the USB driver from the SAML21. It is the same
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USB IP with only small differences. There a a few, small open issues
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USB IP with only small differences. There a a few, small open issues
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@@ -54,14 +50,9 @@ STATUS
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Unfortunately, the board seems to have become unusable after the first
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Unfortunately, the board seems to have become unusable after the first
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NuttX image was written to FLASH. I am unable to connect the JTAG
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NuttX image was written to FLASH. I am unable to connect the JTAG
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debugger and so am dead in the water on this unless I get replacement
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debugger. The primary JTAG problem seems to be that it is now unable
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hardware. The primary JTAG problem seems to be that it is now unable
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to halt the CPU.
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to halt the CPU.
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This is most likely a consequence of something happening in the NuttX
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boot-up sequence that interferes with JTAG operation. There must be
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be some way around this, but I don't know what it is.
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Future me: This boot-up failure was do to bad clock initialization
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Future me: This boot-up failure was do to bad clock initialization
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logic that caused infinite loops during clock configuration. Unlocking
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logic that caused infinite loops during clock configuration. Unlocking
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and erasing the FLASH is innocuous, but the JTAG will apparently not
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and erasing the FLASH is innocuous, but the JTAG will apparently not
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@@ -72,12 +63,12 @@ STATUS
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write to FLASH.
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write to FLASH.
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2018-08-03: Added a configuration option to run out of SRAM vs FLASH.
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2018-08-03: Added a configuration option to run out of SRAM vs FLASH.
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This should be a safer way to do the initial board bring-up since
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This is a safer way to do the initial board bring-up since it does
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it does not modify the FLASH image nor does it require unlocking
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not modify the FLASH image nor does it require unlocking the FLASH
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the FLASH pages.
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pages.
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2018-08-31: I finally have a new Metro M4 and have been successfully
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2018-08-31: I finally have a new Metro M4 and have successfully
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debugging from SRAM (with FLASH unlocked and erased). Several
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debugged from SRAM (with FLASH unlocked and erased). Several
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errors in clock configuration logic have been corrected and it now
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errors in clock configuration logic have been corrected and it now
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gets through clock configuration okay. It now hangs in the low-level
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gets through clock configuration okay. It now hangs in the low-level
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USART initialization.
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USART initialization.
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@@ -93,43 +84,20 @@ STATUS
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This hangs when I try to enable the peripheral clock.
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This hangs when I try to enable the peripheral clock.
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2018-09-01: I found a workaround by substituting OSCULP32K for XOSC32
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2018-09-01: I found a workaround by substituting OSCULP32K for XOSC32
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as the source to GCLK3:
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as the source to GCLK3. With that workaround, the port gets past all
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clock and USART configuration. A new configuration option was added,
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-#define BOARD_GCLK3_SOURCE 5 /* Select XOSC32K as GCLK3 source */
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+#define BOARD_GCLK3_SOURCE 4 /* Select OSCULP32K as GCLK3 source */
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With that workaround, the port gets past all clock and USART
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configuration. A new configuration option was added,
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CONFIG_METRO_M4_32KHZXTAL. By default this workaround is in place.
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CONFIG_METRO_M4_32KHZXTAL. By default this workaround is in place.
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But you can enable CONFIG_METRO_M4_32KHZXTAL if you want to further
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But you can enable CONFIG_METRO_M4_32KHZXTAL if you want to further
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study the XOSC32K problem.
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study the XOSC32K problem.
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With that workaround (and a bunch of other fixes), the basic NSH
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With that workaround (and a bunch of other fixes), the basic NSH
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configuration appears fully function, indicating the the board bring-
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configuration appears fully function, indicating the the board bring-
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up is complete:
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up is complete.
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NuttShell (NSH) NuttX-7.25
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nsh> help
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help usage: help [-v] [<cmd>]
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[ cmp false mkdir set uname
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? dirname help mh sh usleep
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basename dd hexdump mv sleep xd
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break echo kill mw test
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cat exec ls rm time
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cp exit mb rmdir true
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Builtin Apps:
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nsh>
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There are additional drivers ported from SAML21 which has, in most cases,
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There are additional drivers ported from SAML21 which has, in most cases,
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identical peripherals. None of these drivers have been verified on the
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identical peripherals. None of these drivers have been verified on the
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SAMD51, However. These include: DMAC, I2C, SPI, and USB.
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SAMD51, However. These include: DMAC, I2C, SPI, and USB.
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The timer interrupt appears to be running too fast. From the NSH console,
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I see that sleep 5 seems to take about 1 second, sleep 10 seems to take
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about 2 seconds.
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Unlocking FLASH
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Unlocking FLASH
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===============
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===============
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@@ -102,7 +102,8 @@
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#define BOARD_GCLK6_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
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#define BOARD_GCLK6_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
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#define BOARD_GCLK7_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
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#define BOARD_GCLK7_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
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#define BOARD_GCLK8_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
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#define BOARD_GCLK8_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
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#define BOARD_GCLK0_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
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#define BOARD_GCLK9_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
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#define BOARD_GCLK10_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
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#define BOARD_GCLK11_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
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#define BOARD_GCLK11_FREQUENCY BOARD_XOSC1_FREQUENCY /* Disabled */
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#define BOARD_CPU_FREQUENCY BOARD_GCLK0_FREQUENCY /* CPU frequency 120MHz */
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#define BOARD_CPU_FREQUENCY BOARD_GCLK0_FREQUENCY /* CPU frequency 120MHz */
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