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configs/lpcxpresso-lpc54628: Correct SRAM base address in all configurations.

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This commit is contained in:
Gregory Nutt
2018-01-13 08:34:58 -06:00
parent de8f3ebedb
commit fdf4e40b6a
6 changed files with 7 additions and 7 deletions
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configs/lpcxpresso-lpc54628/fb/defconfig
+1 -1
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@@ -64,7 +64,7 @@ CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=4 CONFIG_PREALLOC_WDOGS=4
CONFIG_RAM_SIZE=163840 CONFIG_RAM_SIZE=163840
CONFIG_RAM_START=0x10000000 CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200 CONFIG_RR_INTERVAL=200
CONFIG_SCHED_HPWORK=y CONFIG_SCHED_HPWORK=y
configs/lpcxpresso-lpc54628/netnsh/defconfig
+1 -1
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@@ -55,7 +55,7 @@ CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=4 CONFIG_PREALLOC_WDOGS=4
CONFIG_RAM_SIZE=163840 CONFIG_RAM_SIZE=163840
CONFIG_RAM_START=0x10000000 CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200 CONFIG_RR_INTERVAL=200
CONFIG_SCHED_HPWORK=y CONFIG_SCHED_HPWORK=y
configs/lpcxpresso-lpc54628/nsh/defconfig
+1 -1
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@@ -42,7 +42,7 @@ CONFIG_PREALLOC_MQ_MSGS=4
CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=4 CONFIG_PREALLOC_WDOGS=4
CONFIG_RAM_SIZE=163840 CONFIG_RAM_SIZE=163840
CONFIG_RAM_START=0x10000000 CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200 CONFIG_RR_INTERVAL=200
CONFIG_RTC_ALARM=y CONFIG_RTC_ALARM=y
configs/lpcxpresso-lpc54628/nxwm/defconfig
+1 -1
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@@ -87,7 +87,7 @@ CONFIG_NXWM=y
CONFIG_PREALLOC_TIMERS=4 CONFIG_PREALLOC_TIMERS=4
CONFIG_PREALLOC_WDOGS=8 CONFIG_PREALLOC_WDOGS=8
CONFIG_RAM_SIZE=163840 CONFIG_RAM_SIZE=163840
CONFIG_RAM_START=0x10000000 CONFIG_RAM_START=0x20000000
CONFIG_RAW_BINARY=y CONFIG_RAW_BINARY=y
CONFIG_RR_INTERVAL=200 CONFIG_RR_INTERVAL=200
CONFIG_SCHED_HPWORK=y CONFIG_SCHED_HPWORK=y
configs/lpcxpresso-lpc54628/scripts/flash.ld
+1 -1
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@@ -33,7 +33,7 @@
* *
****************************************************************************/ ****************************************************************************/
/* The LPC54628 on the LPCXPressio has 512Kb of FLASH at address 0x0000:0000. /* The LPC54628 on the LPCXPresso has 512Kb of FLASH at address 0x0000:0000.
* The Main SRAM is comprised of up to a total 160 KB of contiguous, on-chip * The Main SRAM is comprised of up to a total 160 KB of contiguous, on-chip
* static RAM memory beginning at address 0x2000:0000 (this is in addition * static RAM memory beginning at address 0x2000:0000 (this is in addition
* to SRAMX aso the total device SRAM can be up to 200 KB). * to SRAMX aso the total device SRAM can be up to 200 KB).
sched/init/os_start.c
+2 -2
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@@ -229,7 +229,7 @@ struct pidhash_s g_pidhash[CONFIG_MAX_TASKS];
/* This is a table of task lists. This table is indexed by the task stat /* This is a table of task lists. This table is indexed by the task stat
* enumeration type (tstate_t) and provides a pointer to the associated * enumeration type (tstate_t) and provides a pointer to the associated
* static task list (if there is one) as well as a a set of attribute flags * static task list (if there is one) as well as a a set of attribute flags
* indicating properities of the list, for example, if the list is an * indicating properties of the list, for example, if the list is an
* ordered list or not. * ordered list or not.
*/ */
@@ -311,7 +311,7 @@ uint8_t g_os_initstate; /* See enum os_initstate_e */
/**************************************************************************** /****************************************************************************
* Private Data * Private Data
****************************************************************************/ ****************************************************************************/
/* This is an arry of task control block (TCB) for the IDLE thread of each /* This is an array of task control block (TCB) for the IDLE thread of each
* CPU. For the non-SMP case, this is a a single TCB; For the SMP case, * CPU. For the non-SMP case, this is a a single TCB; For the SMP case,
* there is one TCB per CPU. NOTE: The system boots on CPU0 into the IDLE * there is one TCB per CPU. NOTE: The system boots on CPU0 into the IDLE
* task. The IDLE task later starts the other CPUs and spawns the user * task. The IDLE task later starts the other CPUs and spawns the user