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arch/risc-v: Ensure the timer setting atomicity on 32-bit platforms.

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This commit guaranteed the timer setting atomicity on 32-bit platforms.

Signed-off-by: ouyangxiangzhen <ouyangxiangzhen@xiaomi.com>
This commit is contained in:
ouyangxiangzhen
2025-10-24 10:37:25 +08:00
committed by Xiang Xiao
parent c4fd6f9636
commit fd4d93e928
1 changed files with 4 additions and 0 deletions
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4
arch/risc-v/src/common/riscv_mtimer.h
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@@ -77,9 +77,11 @@ void riscv_mtimer_set(uintreg_t mtime_addr,
else
# endif
{
irqstate_t flags = up_irq_save();
putreg32(UINT32_MAX, mtimecmp_addr + 4);
putreg32(value, mtimecmp_addr);
putreg32(value >> 32, mtimecmp_addr + 4);
up_irq_restore(flags);
}
UP_DSB();
@@ -93,8 +95,10 @@ static inline void riscv_write_stime(uint64_t value)
# ifdef CONFIG_ARCH_RV64
WRITE_CSR(CSR_STIMECMP, value);
# else
irqstate_t flags = up_irq_save();
WRITE_CSR(CSR_STIMECMP, (uint32_t)value);
WRITE_CSR(CSR_STIMECMPH, (uint32_t)(value >> 32));
up_irq_restore(flags);
# endif /* CONFIG_ARCH_RV64 */
}
# endif /* CONFIG_ARCH_RV_EXT_SSTC */