diff --git a/arch/arm/src/cxd56xx/cxd56_clock.c b/arch/arm/src/cxd56xx/cxd56_clock.c
index 4b7e3d578b4..ef62efdd7ef 100644
--- a/arch/arm/src/cxd56xx/cxd56_clock.c
+++ b/arch/arm/src/cxd56xx/cxd56_clock.c
@@ -69,6 +69,8 @@
 #define PDID_SCU         0
 #define PDID_APP_DSP     9
 #define PDID_APP_SUB    10
+#define PDID_GNSS_ITP   12
+#define PDID_GNSS       13
 #define PDID_APP_AUD    14
 
 /* For enable_apwd, disable_apwd (analog domain) */
@@ -2602,6 +2604,41 @@ int cxd56_hostseq_clock_disable(void)
   return ret;
 }
 
+int cxd56_gnssram_clock_enable(void)
+{
+  uint32_t stat;
+
+  stat = getreg32(CXD56_TOPREG_PWD_STAT);
+  if ((stat & (1u << PDID_GNSS)) && (stat & (1u << PDID_GNSS_ITP)))
+    {
+      /* Already power on */
+
+      return OK;
+    }
+
+  /* Enable all of GNSS RAM memory power. */
+
+  putreg32(0xff00ffff, CXD56_TOPREG_GNSS_RAMMODE_SEL);
+  enable_pwd(PDID_GNSS_ITP);
+  enable_pwd(PDID_GNSS);
+  putreg32(0x143, CXD56_TOPREG_GNSDSP_CKEN);
+  busy_wait(10);
+  putreg32(0x103, CXD56_TOPREG_GNSDSP_CKEN);
+  putreg32(0x10000, CXD56_TOPREG_SWRESET_GNSDSP);
+  putreg32(0x153, CXD56_TOPREG_GNSDSP_CKEN);
+  return OK;
+}
+
+int cxd56_gnssram_clock_disable(void)
+{
+  putreg32(0x0, CXD56_TOPREG_GNSDSP_CKEN);
+  putreg32(0x0, CXD56_TOPREG_SWRESET_GNSDSP);
+  putreg32(0xff000000, CXD56_TOPREG_GNSS_RAMMODE_SEL);
+  disable_pwd(PDID_GNSS);
+  disable_pwd(PDID_GNSS_ITP);
+  return OK;
+}
+
 int up_pmramctrl(int cmd, uintptr_t addr, size_t size)
 {
   int startidx;
diff --git a/arch/arm/src/cxd56xx/cxd56_clock.h b/arch/arm/src/cxd56xx/cxd56_clock.h
index 81014ca1fb8..0968a4a4d77 100644
--- a/arch/arm/src/cxd56xx/cxd56_clock.h
+++ b/arch/arm/src/cxd56xx/cxd56_clock.h
@@ -724,6 +724,26 @@ int cxd56_hostseq_clock_enable(void);
 
 int cxd56_hostseq_clock_disable(void);
 
+/****************************************************************************
+ * Name: cxd56_gnssram_clock_enable
+ *
+ * Description:
+ *   Enable clock of the GNSS RAM
+ *
+ ****************************************************************************/
+
+int cxd56_gnssram_clock_enable(void);
+
+/****************************************************************************
+ * Name: cxd56_gnssram_clock_disable
+ *
+ * Description:
+ *   Disable clock of the GNSS RAM
+ *
+ ****************************************************************************/
+
+int cxd56_gnssram_clock_disable(void);
+
 #undef EXTERN
 #if defined(__cplusplus)
 }
diff --git a/arch/arm/src/cxd56xx/hardware/cxd5602_topreg.h b/arch/arm/src/cxd56xx/hardware/cxd5602_topreg.h
index 73504f5ab4d..a14a2b7e62b 100644
--- a/arch/arm/src/cxd56xx/hardware/cxd5602_topreg.h
+++ b/arch/arm/src/cxd56xx/hardware/cxd5602_topreg.h
@@ -241,6 +241,7 @@
 #define CXD56_TOPREG_FUSEWRAD                   (CXD56_TOPREG_BASE + 0x0a04)
 #define CXD56_TOPREG_FUSEWRDT                   (CXD56_TOPREG_BASE + 0x0a08)
 #define CXD56_TOPREG_FUSEWRPG                   (CXD56_TOPREG_BASE + 0x0a0c)
+#define CXD56_TOPREG_GNSS_RAMMODE_SEL           (CXD56_TOPREG_BASE + 0x0c00)
 #define CXD56_TOPREG_ADSP1_BOOT_ENTRY_POINT     (CXD56_TOPREG_BASE + 0x1010)
 #define CXD56_TOPREG_ADSP2_BOOT_ENTRY_POINT     (CXD56_TOPREG_BASE + 0x1014)
 #define CXD56_TOPREG_ADSP3_BOOT_ENTRY_POINT     (CXD56_TOPREG_BASE + 0x1018)