arch/arm/src/s32k1xx/s32k1xx_clockconfig.h: Add data structures that will eventually be used to configure clocking.

arch/arm/src/s32k1xx/hardware/s32k1xx_scg.h

@@ -222,7 +222,7 @@
 #define SCG_SOSCCFG_RANGE_MASK         (3 << SCG_SOSCCFG_RANGE_SHIFT)
 #  define SCG_SOSCCFG_RANGE_LOW        (1 << SCG_SOSCCFG_RANGE_SHIFT)  /* Low frequency range */
 #  define SCG_SOSCCFG_RANGE_MED        (2 << SCG_SOSCCFG_RANGE_SHIFT)  /* Medium frequency range */
-#  define SCG_SOSCCFG_RANGE_HIGH       (3 << SCG_SOSCCFG_RANGE_SHIFT)  /* High frequency range
+#  define SCG_SOSCCFG_RANGE_HIGH       (3 << SCG_SOSCCFG_RANGE_SHIFT)  /* High frequency range */
 
 /* Slow IRC Control Status Register */
 

arch/arm/src/s32k1xx/s32k11x/s32k11x_clocknames.h

@@ -0,0 +1,154 @@
+/************************************************************************************
+ * arch/arm/src/s32k1xx/s32k11x/s32k11x_clocknames.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Some of the definitions within this file derivesfrom NXP sample code for
+ * the S32K1xx MCUs.  That sample code has this licensing information:
+ *
+ *   Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ *   Copyright 2016-2018 NXP
+ *   All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_S32K1XX_S32K11X_S32K11X_CLOCKNAMES_H
+#define __ARCH_ARM_SRC_S32K1XX_S32K11X_S32K11X_CLOCKNAMES_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+enum clock_names_e
+{
+  /* Main clocks */
+
+  CORE_CLK                     = 0,       /* Core clock    */
+  BUS_CLK                      = 1,       /* Bus clock     */
+  SLOW_CLK                     = 2,       /* Slow clock    */
+  CLKOUT_CLK                   = 3,       /* CLKOUT clock  */
+
+  /* Other internal clocks used by peripherals. */
+
+  SIRC_CLK                     = 4,       /* SIRC clock    */
+  FIRC_CLK                     = 5,       /* FIRC clock    */
+  SOSC_CLK                     = 6,       /* SOSC clock    */
+  RTC_CLKIN_CLK                = 8,       /* RTC_CLKIN clock */
+  SCG_CLKOUT_CLK               = 9,       /* SCG CLK_OUT clock */
+  SIRCDIV1_CLK                 = 10,      /* SIRCDIV1 functional clock */
+  SIRCDIV2_CLK                 = 11,      /* SIRCDIV2 functional clock */
+  FIRCDIV1_CLK                 = 12,      /* FIRCDIV1 functional clock */
+  FIRCDIV2_CLK                 = 13,      /* FIRCDIV2 functional clock */
+  SOSCDIV1_CLK                 = 14,      /* SOSCDIV1 functional clock */
+  SOSCDIV2_CLK                 = 15,      /* SOSCDIV2 functional clock */
+
+  SCG_END_OF_CLOCKS            = 18,      /* End of SCG clocks */
+
+  /* SIM clocks */
+
+  SIM_FTM0_CLOCKSEL            = 21,      /* FTM0 External Clock Pin Select */
+  SIM_FTM1_CLOCKSEL            = 22,      /* FTM1 External Clock Pin Select */
+  SIM_CLKOUTSELL               = 23,      /* CLKOUT Select */
+  SIM_RTCCLK_CLK               = 24,      /* RTCCLK clock  */
+  SIM_LPO_CLK                  = 25,      /* LPO clock     */
+  SIM_LPO_1K_CLK               = 26,      /* LPO 1KHz clock */
+  SIM_LPO_32K_CLK              = 27,      /* LPO 32KHz clock */
+  SIM_LPO_128K_CLK             = 28,      /* LPO 128KHz clock */
+  SIM_EIM_CLK                  = 29,      /* EIM clock source */
+  SIM_ERM_CLK                  = 30,      /* ERM clock source */
+  SIM_DMA_CLK                  = 31,      /* DMA clock source */
+  SIM_MPU_CLK                  = 32,      /* MPU clock source */
+  SIM_MSCM_CLK                 = 33,      /* MSCM clock source */
+  SIM_END_OF_CLOCKS            = 34,      /* End of SIM clocks */
+
+  CMP0_CLK                     = 41,      /* CMP0 clock source */
+  CRC0_CLK                     = 42,      /* CRC0 clock source */
+  DMAMUX0_CLK                  = 43,      /* DMAMUX0 clock source */
+  PORTA_CLK                    = 44,      /* PORTA clock source */
+  PORTB_CLK                    = 45,      /* PORTB clock source */
+  PORTC_CLK                    = 46,      /* PORTC clock source */
+  PORTD_CLK                    = 47,      /* PORTD clock source */
+  PORTE_CLK                    = 48,      /* PORTE clock source */
+  RTC0_CLK                     = 49,      /* RTC0 clock source */
+  PCC_END_OF_BUS_CLOCKS        = 50,      /* End of BUS clocks */
+  FlexCAN0_CLK                 = 51,      /* FlexCAN0 clock source */
+  PDB0_CLK                     = 52,      /* PDB0 clock source */
+  PCC_END_OF_SYS_CLOCKS        = 53,      /* End of SYS clocks */
+  FTFC0_CLK                    = 54,      /* FTFC0 clock source */
+  PCC_END_OF_SLOW_CLOCKS       = 55,      /* End of SLOW clocks */
+  FTM0_CLK                     = 56,      /* FTM0 clock source */
+  FTM1_CLK                     = 57,      /* FTM1 clock source */
+  PCC_END_OF_ASYNCH_DIV1_CLOCKS= 58,      /* End of ASYNCH DIV1 clocks */
+  ADC0_CLK                     = 59,      /* ADC0 clock source */
+  FLEXIO0_CLK                  = 60,      /* FLEXIO0 clock source */
+  LPI2C0_CLK                   = 61,      /* LPI2C0 clock source */
+  LPIT0_CLK                    = 62,      /* LPIT0 clock source */
+  LPSPI0_CLK                   = 63,      /* LPSPI0 clock source */
+  LPSPI1_CLK                   = 64,      /* LPSPI1 clock source */
+  LPTMR0_CLK                   = 65,      /* LPTMR0 clock source */
+  LPUART0_CLK                  = 66,      /* LPUART0 clock source */
+  LPUART1_CLK                  = 67,      /* LPUART1 clock source */
+  PCC_END_OF_ASYNCH_DIV2_CLOCKS= 68,      /* End of ASYNCH DIV2 clocks */
+  PCC_END_OF_CLOCKS            = 69,      /* End of PCC clocks */
+  CLOCK_NAME_COUNT             = 70,      /* The total number of entries */
+};
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_S32K1XX_S32K11X_S32K11X_CLOCKNAMES_H */

arch/arm/src/s32k1xx/s32k14x/s32k14x_clocknames.h

@@ -0,0 +1,185 @@
+/************************************************************************************
+ * arch/arm/src/s32k1xx/s32k14x/s32k14x_clocknames.h
+ *
+ *   Copyright (C) 2019 Gregory Nutt. All rights reserved.
+ *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ * Some of the definitions within this file derivesfrom NXP sample code for
+ * the S32K1xx MCUs.  That sample code has this licensing information:
+ *
+ *   Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ *   Copyright 2016-2018 NXP
+ *   All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
+ ************************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_S32K1XX_S32K14X_S32K14X_CLOCKNAMES_H
+#define __ARCH_ARM_SRC_S32K1XX_S32K14X_S32K14X_CLOCKNAMES_H
+
+/************************************************************************************
+ * Included Files
+ ************************************************************************************/
+
+#include <nuttx/config.h>
+
+/************************************************************************************
+ * Pre-processor Definitions
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Types
+ ************************************************************************************/
+
+enum clock_names_e
+{
+  /* Main clocks */
+
+  CORE_CLK                      = 0,       /* Core clock */
+  BUS_CLK                       = 1,       /* Bus clock */
+  SLOW_CLK                      = 2,       /* Slow clock */
+  CLKOUT_CLK                    = 3,       /* CLKOUT clock */
+
+  /* Other internal clocks used by peripherals */
+
+  SIRC_CLK                      = 4,       /* SIRC clock */
+  FIRC_CLK                      = 5,       /* FIRC clock */
+  SOSC_CLK                      = 6,       /* SOSC clock */
+  SPLL_CLK                      = 7,       /* SPLL clock */
+  RTC_CLKIN_CLK                 = 8,       /* RTC_CLKIN clock */
+  SCG_CLKOUT_CLK                = 9,       /* SCG CLK_OUT clock */
+  SIRCDIV1_CLK                  = 10,      /* SIRCDIV1 functional clock */
+  SIRCDIV2_CLK                  = 11,      /* SIRCDIV2 functional clock */
+  FIRCDIV1_CLK                  = 12,      /* FIRCDIV1 functional clock */
+  FIRCDIV2_CLK                  = 13,      /* FIRCDIV2 functional clock */
+  SOSCDIV1_CLK                  = 14,      /* SOSCDIV1 functional clock */
+  SOSCDIV2_CLK                  = 15,      /* SOSCDIV2 functional clock */
+  SPLLDIV1_CLK                  = 16,      /* SPLLDIV1 functional clock */
+  SPLLDIV2_CLK                  = 17,      /* SPLLDIV2 functional clock */
+
+  SCG_END_OF_CLOCKS             = 18,      /* End of SCG clocks */
+
+  /* SIM clocks */
+
+  SIM_FTM0_CLOCKSEL             = 21,      /* FTM0 External Clock Pin Select */
+  SIM_FTM1_CLOCKSEL             = 22,      /* FTM1 External Clock Pin Select */
+  SIM_FTM2_CLOCKSEL             = 23,      /* FTM2 External Clock Pin Select */
+  SIM_FTM3_CLOCKSEL             = 24,      /* FTM3 External Clock Pin Select */
+  SIM_FTM4_CLOCKSEL             = 25,      /* FTM4 External Clock Pin Select */
+  SIM_FTM5_CLOCKSEL             = 26,      /* FTM5 External Clock Pin Select */
+  SIM_FTM6_CLOCKSEL             = 27,      /* FTM6 External Clock Pin Select */
+  SIM_FTM7_CLOCKSEL             = 28,      /* FTM7 External Clock Pin Select */
+  SIM_CLKOUTSELL                = 29,      /* CLKOUT Select */
+  SIM_RTCCLK_CLK                = 30,      /* RTCCLK clock */
+  SIM_LPO_CLK                   = 31,      /* LPO clock */
+  SIM_LPO_1K_CLK                = 32,      /* LPO 1KHz clock */
+  SIM_LPO_32K_CLK               = 33,      /* LPO 32KHz clock */
+  SIM_LPO_128K_CLK              = 34,      /* LPO 128KHz clock */
+  SIM_EIM_CLK                   = 35,      /* EIM clock source */
+  SIM_ERM_CLK                   = 36,      /* ERM clock source */
+  SIM_DMA_CLK                   = 37,      /* DMA clock source */
+  SIM_MPU_CLK                   = 38,      /* MPU clock source */
+  SIM_MSCM_CLK                  = 39,      /* MSCM clock source */
+  QSPI_MODULE_SFIF_CLK_HYP      = 40,      /* QSPI module SFIF clock source */
+  QSPI_MODULE_CLK               = 41,      /* QSPI module clock source */
+  QSPI_MODULE_CLK_SFIF          = 42,      /* QSPI module clock source SFIF */
+  QSPI_MODULE_CLK_2XSFIF        = 43,      /* QSPI module clock source 2XSFIF*/
+  SIM_END_OF_CLOCKS             = 44,      /* End of SIM clocks */
+
+  CMP0_CLK                      = 45,      /* CMP0 clock source */
+  CRC0_CLK                      = 46,      /* CRC0 clock source */
+  DMAMUX0_CLK                   = 47,      /* DMAMUX0 clock source */
+  EWM0_CLK                      = 48,      /* EWM0 clock source */
+  PORTA_CLK                     = 49,      /* PORTA clock source */
+  PORTB_CLK                     = 50,      /* PORTB clock source */
+  PORTC_CLK                     = 51,      /* PORTC clock source */
+  PORTD_CLK                     = 52,      /* PORTD clock source */
+  PORTE_CLK                     = 53,      /* PORTE clock source */
+  RTC0_CLK                      = 54,      /* RTC0 clock source */
+  SAI0_CLK                      = 55,      /* SAI0 clock source */
+  SAI1_CLK                      = 56,      /* SAI1 clock source */
+  PCC_END_OF_BUS_CLOCKS         = 57,      /* End of BUS clocks */
+  FlexCAN0_CLK                  = 58,      /* FlexCAN0 clock source */
+  FlexCAN1_CLK                  = 59,      /* FlexCAN1 clock source */
+  FlexCAN2_CLK                  = 60,      /* FlexCAN2 clock source */
+  PDB0_CLK                      = 61,      /* PDB0 clock source */
+  PDB1_CLK                      = 62,      /* PDB1 clock source */
+  PCC_END_OF_SYS_CLOCKS         = 63,      /* End of SYS clocks */
+  FTFC0_CLK                     = 64,      /* FTFC0 clock source */
+  PCC_END_OF_SLOW_CLOCKS        = 65,      /* End of SLOW clocks */
+  ENET0_CLK                     = 66,      /* ENET0 clock source */
+  FTM0_CLK                      = 67,      /* FTM0 clock source */
+  FTM1_CLK                      = 68,      /* FTM1 clock source */
+  FTM2_CLK                      = 69,      /* FTM2 clock source */
+  FTM3_CLK                      = 70,      /* FTM3 clock source */
+  FTM4_CLK                      = 71,      /* FTM4 clock source */
+  FTM5_CLK                      = 72,      /* FTM5 clock source */
+  FTM6_CLK                      = 73,      /* FTM6 clock source */
+  FTM7_CLK                      = 74,      /* FTM7 clock source */
+  PCC_END_OF_ASYNCH_DIV1_CLOCKS = 75,      /* End of ASYNCH DIV1 clocks */
+  ADC0_CLK                      = 76,      /* ADC0 clock source */
+  ADC1_CLK                      = 77,      /* ADC1 clock source */
+  FLEXIO0_CLK                   = 78,      /* FLEXIO0 clock source */
+  LPI2C0_CLK                    = 79,      /* LPI2C0 clock source */
+  LPI2C1_CLK                    = 80,      /* LPI2C1 clock source */
+  LPIT0_CLK                     = 81,      /* LPIT0 clock source */
+  LPSPI0_CLK                    = 82,      /* LPSPI0 clock source */
+  LPSPI1_CLK                    = 83,      /* LPSPI1 clock source */
+  LPSPI2_CLK                    = 84,      /* LPSPI2 clock source */
+  LPTMR0_CLK                    = 85,      /* LPTMR0 clock source */
+  LPUART0_CLK                   = 86,      /* LPUART0 clock source */
+  LPUART1_CLK                   = 87,      /* LPUART1 clock source */
+  LPUART2_CLK                   = 88,      /* LPUART2 clock source */
+  QSPI0_CLK                     = 89,      /* QSPI0 clock source */
+  PCC_END_OF_ASYNCH_DIV2_CLOCKS = 90,      /* End of ASYNCH DIV2 clocks */
+  PCC_END_OF_CLOCKS             = 91,      /* End of PCC clocks */
+  CLOCK_NAME_COUNT              = 92,      /* The total number of entries */
+};
+
+/************************************************************************************
+ * Public Data
+ ************************************************************************************/
+
+/************************************************************************************
+ * Public Functions
+ ************************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_S32K1XX_S32K14X_S32K14X_CLOCKNAMES_H */

arch/arm/src/s32k1xx/s32k1xx_clockconfig.c

@@ -31,6 +31,25 @@
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
+ * Portions of the logic within this file derives from NXP sample code for
+ * the S32K1xx MCUs.  That sample code has this licensing information:
+ *
+ *   Copyright (c) 2013 - 2015, Freescale Semiconductor, Inc.
+ *   Copyright 2016-2018 NXP
+ *   All rights reserved.
+ *
+ * THIS SOFTWARE IS PROVIDED BY NXP "AS IS" AND ANY EXPRESSED OR
+ * IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
+ * OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED.
+ * IN NO EVENT SHALL NXP OR ITS CONTRIBUTORS BE LIABLE FOR ANY DIRECT,
+ * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES
+ * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
+ * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION)
+ * HOWEVER CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT,
+ * STRICT LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING
+ * IN ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF
+ * THE POSSIBILITY OF SUCH DAMAGE.
+ *
  ****************************************************************************/
 
 /****************************************************************************
@@ -43,13 +62,15 @@
 #include <debug.h>
 
 #include <nuttx/arch.h>
-#include <arch/board/board.h>
 
 #include "up_arch.h"
 #include "up_internal.h"
 
+#include "hardware/s32k1xx_scg.h"
 #include "s32k1xx_clockconfig.h"
 
+#include <arch/board/board.h>  /* Include last.  May have dependencies */
+
 /****************************************************************************
  * Private Functions
  ****************************************************************************/
@@ -69,7 +90,91 @@
  *
  *****************************************************************************/
 
-void s32k1xx_clockconfig(FAR const struct pll_setup_s *pllsetup)
+void s32k1xx_clockconfig(FAR const struct clock_configuration_s *clkcfg)
 {
 #warning Missing logic
 }
+
+/****************************************************************************
+ * Name: s32k1xx_get_coreclk
+ *
+ * Description:
+ *   Return the current value of the CORE clock frequency.
+ *
+ * Input Parameters:
+ *   None
+ *
+ * Returned Values:
+ *   The current value of the CORE clock frequency.  Zero is returned on any
+ *   failure.
+ *
+ *****************************************************************************/
+
+uint32_t s32k1xx_get_coreclk(void)
+{
+  uint32_t coreclk = 0;
+  uint32_t regval;
+  uint32_t divider;
+#ifdef CONFIG_ARCH_CHIP_S32K14X
+  uint32_t prediv;
+  uint32_t mult;
+#endif
+
+  /* Get the core clock divider */
+
+  regval  = getreg32(S32K1XX_SCG_CSR);
+  divider = ((regval & SCG_CSR_DIVCORE_MASK) >> SCG_CSR_DIVCORE_SHIFT) + 1;
+
+  /* Handle according to the selection clock source */
+
+  switch (regval & SCG_CSR_SCS_MASK)
+    {
+      case SCG_CSR_SCS_SOSC:  /* System OSC */
+
+        coreclk = BOARD_XTAL_FREQUENCY;
+        break;
+
+      case SCG_CSR_SCS_SIRC:  /* Slow IRC */
+        regval = getreg32(S32K1XX_SCG_SIRCCFG) & SCG_SIRCCFG_RANGE;
+        if (regval == SCG_SIRCCFG_LOWRANGE)
+          {
+            /* Slow IRC low range clock (2 MHz) */
+
+            return 0;
+          }
+
+        /* Slow IRC high range clock (8 MHz ) */
+
+        coreclk = SCG_SIRQ_HIGHRANGE_FREQUENCY;
+        break;
+
+      case SCG_CSR_SCS_FIRC:  /* Fast IRC */
+        regval = getreg32(S32K1XX_SCG_FIRCCFG) & SCG_FIRCCFG_RANGE;
+        if (regval != SCG_FIRCCFG_48MHZ)
+          {
+            return 0;
+          }
+
+        /* Fast IRC is trimmed to 48 MHz */
+
+        coreclk = SCG_FIRQ_FREQUENCY0;
+        break;
+
+#ifdef CONFIG_ARCH_CHIP_S32K14X
+      case 0x6SCG_CSR_SPLL_FIRC:  /* System PLL */
+        /* Coreclock = Fxtal * mult / (2 * prediv) */
+
+        regval  = getreg32(S32K1XX_SCG_SPLLCFG);
+        prediv  = ((regval & SCG_SPLLCFG_PREDIV_MASK) >> SCG_SPLLCFG_PREDIV_SHIFT) + 1;
+        mult    = ((regval & SCG_SPLLCFG_MULT_MASK) >> SCG_SPLLCFG_MULT_SHIFT) + 16;
+
+          coreclk = BOARD_XTAL_FREQUENCY * mult / (2 * prediv);
+        break;
+#endif
+
+      default:
+        return 0;
+    }
+
+  return coreclk / divider;
+}

arch/arm/src/s32k1xx/s32k1xx_start.c

@@ -80,7 +80,7 @@
 
 /* This describes the initial PLL configuration */
 
-static const struct pll_setup_s g_initial_pll_setup =
+static const struct clock_configuration_s g_initial_clkconfig =
 {
   0  /* REVISIT */
 #warning Missing logic
@@ -202,7 +202,7 @@ void __start(void)
    * .bss or .data have beeninitialized.
    */
 
-  s32k1xx_clockconfig(&g_initial_pll_setup);
+  s32k1xx_clockconfig(&g_initial_clkconfig);
   s32k1xx_lowsetup();
   showprogress('A');
 

boards/arm/s32k1xx/s32k118evb/scripts/flash.ld

@@ -72,6 +72,7 @@ SECTIONS
     _etext = ABSOLUTE(.);
   } > flash
 
+  . = ALIGN(4);
   .init_section :
   {
     _sinit = ABSOLUTE(.);
@@ -79,11 +80,13 @@ SECTIONS
     _einit = ABSOLUTE(.);
   } > flash
 
+  . = ALIGN(4);
   .ARM.extab :
   {
     *(.ARM.extab*)
   } >flash
 
+  . = ALIGN(4);
   __exidx_start = ABSOLUTE(.);
   .ARM.exidx :
   {
@@ -91,6 +94,7 @@ SECTIONS
   } >flash
   __exidx_end = ABSOLUTE(.);
 
+  . = ALIGN(4);
   .data :
   {
     _sdata = ABSOLUTE(.);