diff --git a/arch/renesas/Kconfig b/arch/renesas/Kconfig index c8818030d79..7b605d3e06c 100644 --- a/arch/renesas/Kconfig +++ b/arch/renesas/Kconfig @@ -22,12 +22,47 @@ config ARCH_CHIP_M30262F8 ---help--- Renesas M30262F8 (M16C) +config ARCH_CHIP_R5F565NEDDFC + bool "R5F565NEDDFC" + select ARCH_RX65N_RSK1MB + select ARCH_RX65N + ---help--- + Renesas RX65N on RSKRX65N-1MB + +config ARCH_CHIP_R5F565NEHDFC + bool "R5F565NEHDFC" + select ARCH_RX65N_RSK2MB + ---help--- + Renesas RX65N on RSKRX65N-2MB + +config ARCH_CHIP_R5F565NEHDFP + bool "R5F565NEHDFP" + select ARCH_RX65N_GRROSE + ---help--- + Renesas RX65N on GR-ROSE + endchoice config ARCH_SH1 bool default n +config ARCH_RX65N + bool + default n + +config ARCH_RX65N_RSK1MB + bool + default n + +config ARCH_RX65N_RSK2MB + bool + default n + +config ARCH_RX65N_GRROSE + bool + default n + config ARCH_M16C bool default n @@ -36,9 +71,14 @@ config ARCH_CHIP string default "sh1" if ARCH_SH1 default "m16c" if ARCH_M16C + default "rx65n" if ARCH_RX65N + default "rx65n" if ARCH_RX65N_RSK1MB + default "rx65n" if ARCH_RX65N_RSK2MB + default "rx65n" if ARCH_RX65N_GRROSE source arch/renesas/src/common/Kconfig source arch/renesas/src/m16c/Kconfig source arch/renesas/src/sh1/Kconfig +source arch/renesas/src/rx65n/Kconfig endif # ARCH_RENESAS diff --git a/arch/renesas/include/rx65n/inttypes.h b/arch/renesas/include/rx65n/inttypes.h new file mode 100644 index 00000000000..9688525c17e --- /dev/null +++ b/arch/renesas/include/rx65n/inttypes.h @@ -0,0 +1,240 @@ +/**************************************************************************** + * arch/renesas/include/rx65n/inttypes.h + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + ****************************************************************************/ + +#ifndef __ARCH_RENESAS_INCLUDE_RX65N_INTTYPES_H +#define __ARCH_RENESAS_INCLUDE_RX65N_INTTYPES_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define PRId8 "d" +#define PRId16 "d" +#define PRId32 "d" +#define PRId64 "lld" + +#define PRIdLEAST8 "d" +#define PRIdLEAST16 "d" +#define PRIdLEAST32 "d" +#define PRIdLEAST64 "lld" + +#define PRIdFAST8 "d" +#define PRIdFAST16 "d" +#define PRIdFAST32 "d" +#define PRIdFAST64 "lld" + +#define PRIdMAX "lld" +#define PRIdPTR "d" + +#define PRIi8 "i" +#define PRIi16 "i" +#define PRIi32 "i" +#define PRIi64 "lli" + +#define PRIiLEAST8 "i" +#define PRIiLEAST16 "i" +#define PRIiLEAST32 "i" +#define PRIiLEAST64 "lli" + +#define PRIiFAST8 "i" +#define PRIiFAST16 "i" +#define PRIiFAST32 "i" +#define PRIiFAST64 "lli" + +#define PRIiMAX "lli" +#define PRIiPTR "i" + +#define PRIo8 "o" +#define PRIo16 "o" +#define PRIo32 "o" +#define PRIo64 "llo" + +#define PRIoLEAST8 "o" +#define PRIoLEAST16 "o" +#define PRIoLEAST32 "o" +#define PRIoLEAST64 "llo" + +#define PRIoFAST8 "o" +#define PRIoFAST16 "o" +#define PRIoFAST32 "o" +#define PRIoFAST64 "llo" + +#define PRIoMAX "llo" +#define PRIoPTR "o" + +#define PRIu8 "u" +#define PRIu16 "u" +#define PRIu32 "u" +#define PRIu64 "llu" + +#define PRIuLEAST8 "u" +#define PRIuLEAST16 "u" +#define PRIuLEAST32 "u" +#define PRIuLEAST64 "llu" + +#define PRIuFAST8 "u" +#define PRIuFAST16 "u" +#define PRIuFAST32 "u" +#define PRIuFAST64 "llu" + +#define PRIuMAX "llu" +#define PRIuPTR "u" + +#define PRIx8 "x" +#define PRIx16 "x" +#define PRIx32 "x" +#define PRIx64 "llx" + +#define PRIxLEAST8 "x" +#define PRIxLEAST16 "x" +#define PRIxLEAST32 "x" +#define PRIxLEAST64 "llx" + +#define PRIxFAST8 "x" +#define PRIxFAST16 "x" +#define PRIxFAST32 "x" +#define PRIxFAST64 "llx" + +#define PRIxMAX "llx" +#define PRIxPTR "x" + +#define PRIX8 "X" +#define PRIX16 "X" +#define PRIX32 "X" +#define PRIX64 "llX" + +#define PRIXLEAST8 "X" +#define PRIXLEAST16 "X" +#define PRIXLEAST32 "X" +#define PRIXLEAST64 "llX" + +#define PRIXFAST8 "X" +#define PRIXFAST16 "X" +#define PRIXFAST32 "X" +#define PRIXFAST64 "llX" + +#define PRIXMAX "llX" +#define PRIXPTR "X" + +#define SCNd8 "hhd" +#define SCNd16 "hd" +#define SCNd32 "d" +#define SCNd64 "lld" + +#define SCNdLEAST8 "hhd" +#define SCNdLEAST16 "hd" +#define SCNdLEAST32 "d" +#define SCNdLEAST64 "lld" + +#define SCNdFAST8 "hhd" +#define SCNdFAST16 "hd" +#define SCNdFAST32 "d" +#define SCNdFAST64 "lld" + +#define SCNdMAX "lld" +#define SCNdPTR "d" + +#define SCNi8 "hhi" +#define SCNi16 "hi" +#define SCNi32 "i" +#define SCNi64 "lli" + +#define SCNiLEAST8 "hhi" +#define SCNiLEAST16 "hi" +#define SCNiLEAST32 "i" +#define SCNiLEAST64 "lli" + +#define SCNiFAST8 "hhi" +#define SCNiFAST16 "hi" +#define SCNiFAST32 "i" +#define SCNiFAST64 "lli" + +#define SCNiMAX "lli" +#define SCNiPTR "i" + +#define SCNo8 "hho" +#define SCNo16 "ho" +#define SCNo32 "o" +#define SCNo64 "llo" + +#define SCNoLEAST8 "hho" +#define SCNoLEAST16 "ho" +#define SCNoLEAST32 "o" +#define SCNoLEAST64 "llo" + +#define SCNoFAST8 "hho" +#define SCNoFAST16 "ho" +#define SCNoFAST32 "o" +#define SCNoFAST64 "llo" + +#define SCNoMAX "llo" +#define SCNoPTR "o" + +#define SCNu8 "hhu" +#define SCNu16 "hu" +#define SCNu32 "u" +#define SCNu64 "llu" + +#define SCNuLEAST8 "hhu" +#define SCNuLEAST16 "hu" +#define SCNuLEAST32 "u" +#define SCNuLEAST64 "llu" + +#define SCNuFAST8 "hhu" +#define SCNuFAST16 "hu" +#define SCNuFAST32 "u" +#define SCNuFAST64 "llu" + +#define SCNuMAX "llu" +#define SCNuPTR "u" + +#define SCNx8 "hhx" +#define SCNx16 "hx" +#define SCNx32 "x" +#define SCNx64 "llx" + +#define SCNxLEAST8 "hhx" +#define SCNxLEAST16 "hx" +#define SCNxLEAST32 "x" +#define SCNxLEAST64 "llx" + +#define SCNxFAST8 "hhx" +#define SCNxFAST16 "hx" +#define SCNxFAST32 "x" +#define SCNxFAST64 "llx" + +#define SCNxMAX "llx" +#define SCNxPTR "x" + +#endif /* __ARCH_RENESAS_INCLUDE_RX65N_INTTYPES_H */ diff --git a/arch/renesas/include/rx65n/iodefine.h b/arch/renesas/include/rx65n/iodefine.h new file mode 100644 index 00000000000..5dab7d0d66e --- /dev/null +++ b/arch/renesas/include/rx65n/iodefine.h @@ -0,0 +1,18050 @@ +/***************************************************************************** + * arch/renesas/include/rx65n/iodefine.h + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + *****************************************************************************/ + +#ifndef __RX65NIODEFINE_HEADER__ +#define __RX65NIODEFINE_HEADER__ + +/**************************************************************************** + * Pre-processor Definitions + ***************************************************************************/ + +#define IEN_BSC_BUSERR IEN0 +#define IEN_RAM_RAMERR IEN2 +#define IEN_FCU_FIFERR IEN5 +#define IEN_FCU_FRDYI IEN7 +#define IEN_ICU_SWINT2 IEN2 +#define IEN_ICU_SWINT IEN3 +#define IEN_CMT0_CMI0 IEN4 +#define IEN_CMT1_CMI1 IEN5 +#define IEN_CMTW0_CMWI0 IEN6 +#define IEN_CMTW1_CMWI1 IEN7 +#define IEN_USB0_D0FIFO0 IEN2 +#define IEN_USB0_D1FIFO0 IEN3 +#define IEN_RSPI0_SPRI0 IEN6 +#define IEN_RSPI0_SPTI0 IEN7 +#define IEN_RSPI1_SPRI1 IEN0 +#define IEN_RSPI1_SPTI1 IEN1 +#define IEN_QSPI_SPRI IEN2 +#define IEN_QSPI_SPTI IEN3 +#define IEN_SDHI_SBFAI IEN4 +#define IEN_MMCIF_MBFAI IEN5 +#define IEN_RIIC1_RXI1 IEN2 +#define IEN_RIIC1_TXI1 IEN3 +#define IEN_RIIC0_RXI0 IEN4 +#define IEN_RIIC0_TXI0 IEN5 +#define IEN_RIIC2_RXI2 IEN6 +#define IEN_RIIC2_TXI2 IEN7 +#define IEN_SCI0_RXI0 IEN2 +#define IEN_SCI0_TXI0 IEN3 +#define IEN_SCI1_RXI1 IEN4 +#define IEN_SCI1_TXI1 IEN5 +#define IEN_SCI2_RXI2 IEN6 +#define IEN_SCI2_TXI2 IEN7 +#define IEN_ICU_IRQ0 IEN0 +#define IEN_ICU_IRQ1 IEN1 +#define IEN_ICU_IRQ2 IEN2 +#define IEN_ICU_IRQ3 IEN3 +#define IEN_ICU_IRQ4 IEN4 +#define IEN_ICU_IRQ5 IEN5 +#define IEN_ICU_IRQ6 IEN6 +#define IEN_ICU_IRQ7 IEN7 +#define IEN_ICU_IRQ8 IEN0 +#define IEN_ICU_IRQ9 IEN1 +#define IEN_ICU_IRQ10 IEN2 +#define IEN_ICU_IRQ11 IEN3 +#define IEN_ICU_IRQ12 IEN4 +#define IEN_ICU_IRQ13 IEN5 +#define IEN_ICU_IRQ14 IEN6 +#define IEN_ICU_IRQ15 IEN7 +#define IEN_SCI3_RXI3 IEN0 +#define IEN_SCI3_TXI3 IEN1 +#define IEN_SCI4_RXI4 IEN2 +#define IEN_SCI4_TXI4 IEN3 +#define IEN_SCI5_RXI5 IEN4 +#define IEN_SCI5_TXI5 IEN5 +#define IEN_SCI6_RXI6 IEN6 +#define IEN_SCI6_TXI6 IEN7 +#define IEN_LVD1_LVD1 IEN0 +#define IEN_LVD2_LVD2 IEN1 +#define IEN_USB0_USBR0 IEN2 +#define IEN_RTC_ALM IEN4 +#define IEN_RTC_PRD IEN5 +#define IEN_IWDT_IWUNI IEN7 +#define IEN_WDT_WUNI IEN0 +#define IEN_PDC_PCDFI IEN1 +#define IEN_SCI7_RXI7 IEN2 +#define IEN_SCI7_TXI7 IEN3 +#define IEN_SCI8_RXI8 IEN4 +#define IEN_SCI8_TXI8 IEN5 +#define IEN_SCI9_RXI9 IEN6 +#define IEN_SCI9_TXI9 IEN7 +#define IEN_SCI10_RXI10 IEN0 +#define IEN_SCI10_TXI10 IEN1 +#define IEN_ICU_GROUPBE0 IEN2 +#define IEN_ICU_GROUPBL2 IEN3 +#define IEN_RSPI2_SPRI2 IEN4 +#define IEN_RSPI2_SPTI2 IEN5 +#define IEN_ICU_GROUPBL0 IEN6 +#define IEN_ICU_GROUPBL1 IEN7 +#define IEN_ICU_GROUPAL0 IEN0 +#define IEN_ICU_GROUPAL1 IEN1 +#define IEN_SCI11_RXI11 IEN2 +#define IEN_SCI11_TXI11 IEN3 +#define IEN_SCI12_RXI12 IEN4 +#define IEN_SCI12_TXI12 IEN5 +#define IEN_DMAC_DMAC0I IEN0 +#define IEN_DMAC_DMAC1I IEN1 +#define IEN_DMAC_DMAC2I IEN2 +#define IEN_DMAC_DMAC3I IEN3 +#define IEN_DMAC_DMAC74I IEN4 +#define IEN_OST_OSTDI IEN5 +#define IEN_EXDMAC_EXDMAC0I IEN6 +#define IEN_EXDMAC_EXDMAC1I IEN7 +#define IEN_PERIB_INTB128 IEN0 +#define IEN_PERIB_INTB129 IEN1 +#define IEN_PERIB_INTB130 IEN2 +#define IEN_PERIB_INTB131 IEN3 +#define IEN_PERIB_INTB132 IEN4 +#define IEN_PERIB_INTB133 IEN5 +#define IEN_PERIB_INTB134 IEN6 +#define IEN_PERIB_INTB135 IEN7 +#define IEN_PERIB_INTB136 IEN0 +#define IEN_PERIB_INTB137 IEN1 +#define IEN_PERIB_INTB138 IEN2 +#define IEN_PERIB_INTB139 IEN3 +#define IEN_PERIB_INTB140 IEN4 +#define IEN_PERIB_INTB141 IEN5 +#define IEN_PERIB_INTB142 IEN6 +#define IEN_PERIB_INTB143 IEN7 +#define IEN_PERIB_INTB144 IEN0 +#define IEN_PERIB_INTB145 IEN1 +#define IEN_PERIB_INTB146 IEN2 +#define IEN_PERIB_INTB147 IEN3 +#define IEN_PERIB_INTB148 IEN4 +#define IEN_PERIB_INTB149 IEN5 +#define IEN_PERIB_INTB150 IEN6 +#define IEN_PERIB_INTB151 IEN7 +#define IEN_PERIB_INTB152 IEN0 +#define IEN_PERIB_INTB153 IEN1 +#define IEN_PERIB_INTB154 IEN2 +#define IEN_PERIB_INTB155 IEN3 +#define IEN_PERIB_INTB156 IEN4 +#define IEN_PERIB_INTB157 IEN5 +#define IEN_PERIB_INTB158 IEN6 +#define IEN_PERIB_INTB159 IEN7 +#define IEN_PERIB_INTB160 IEN0 +#define IEN_PERIB_INTB161 IEN1 +#define IEN_PERIB_INTB162 IEN2 +#define IEN_PERIB_INTB163 IEN3 +#define IEN_PERIB_INTB164 IEN4 +#define IEN_PERIB_INTB165 IEN5 +#define IEN_PERIB_INTB166 IEN6 +#define IEN_PERIB_INTB167 IEN7 +#define IEN_PERIB_INTB168 IEN0 +#define IEN_PERIB_INTB169 IEN1 +#define IEN_PERIB_INTB170 IEN2 +#define IEN_PERIB_INTB171 IEN3 +#define IEN_PERIB_INTB172 IEN4 +#define IEN_PERIB_INTB173 IEN5 +#define IEN_PERIB_INTB174 IEN6 +#define IEN_PERIB_INTB175 IEN7 +#define IEN_PERIB_INTB176 IEN0 +#define IEN_PERIB_INTB177 IEN1 +#define IEN_PERIB_INTB178 IEN2 +#define IEN_PERIB_INTB179 IEN3 +#define IEN_PERIB_INTB180 IEN4 +#define IEN_PERIB_INTB181 IEN5 +#define IEN_PERIB_INTB182 IEN6 +#define IEN_PERIB_INTB183 IEN7 +#define IEN_PERIB_INTB184 IEN0 +#define IEN_PERIB_INTB185 IEN1 +#define IEN_PERIB_INTB186 IEN2 +#define IEN_PERIB_INTB187 IEN3 +#define IEN_PERIB_INTB188 IEN4 +#define IEN_PERIB_INTB189 IEN5 +#define IEN_PERIB_INTB190 IEN6 +#define IEN_PERIB_INTB191 IEN7 +#define IEN_PERIB_INTB192 IEN0 +#define IEN_PERIB_INTB193 IEN1 +#define IEN_PERIB_INTB194 IEN2 +#define IEN_PERIB_INTB195 IEN3 +#define IEN_PERIB_INTB196 IEN4 +#define IEN_PERIB_INTB197 IEN5 +#define IEN_PERIB_INTB198 IEN6 +#define IEN_PERIB_INTB199 IEN7 +#define IEN_PERIB_INTB200 IEN0 +#define IEN_PERIB_INTB201 IEN1 +#define IEN_PERIB_INTB202 IEN2 +#define IEN_PERIB_INTB203 IEN3 +#define IEN_PERIB_INTB204 IEN4 +#define IEN_PERIB_INTB205 IEN5 +#define IEN_PERIB_INTB206 IEN6 +#define IEN_PERIB_INTB207 IEN7 +#define IEN_PERIA_INTA208 IEN0 +#define IEN_PERIA_INTA209 IEN1 +#define IEN_PERIA_INTA210 IEN2 +#define IEN_PERIA_INTA211 IEN3 +#define IEN_PERIA_INTA212 IEN4 +#define IEN_PERIA_INTA213 IEN5 +#define IEN_PERIA_INTA214 IEN6 +#define IEN_PERIA_INTA215 IEN7 +#define IEN_PERIA_INTA216 IEN0 +#define IEN_PERIA_INTA217 IEN1 +#define IEN_PERIA_INTA218 IEN2 +#define IEN_PERIA_INTA219 IEN3 +#define IEN_PERIA_INTA220 IEN4 +#define IEN_PERIA_INTA221 IEN5 +#define IEN_PERIA_INTA222 IEN6 +#define IEN_PERIA_INTA223 IEN7 +#define IEN_PERIA_INTA224 IEN0 +#define IEN_PERIA_INTA225 IEN1 +#define IEN_PERIA_INTA226 IEN2 +#define IEN_PERIA_INTA227 IEN3 +#define IEN_PERIA_INTA228 IEN4 +#define IEN_PERIA_INTA229 IEN5 +#define IEN_PERIA_INTA230 IEN6 +#define IEN_PERIA_INTA231 IEN7 +#define IEN_PERIA_INTA232 IEN0 +#define IEN_PERIA_INTA233 IEN1 +#define IEN_PERIA_INTA234 IEN2 +#define IEN_PERIA_INTA235 IEN3 +#define IEN_PERIA_INTA236 IEN4 +#define IEN_PERIA_INTA237 IEN5 +#define IEN_PERIA_INTA238 IEN6 +#define IEN_PERIA_INTA239 IEN7 +#define IEN_PERIA_INTA240 IEN0 +#define IEN_PERIA_INTA241 IEN1 +#define IEN_PERIA_INTA242 IEN2 +#define IEN_PERIA_INTA243 IEN3 +#define IEN_PERIA_INTA244 IEN4 +#define IEN_PERIA_INTA245 IEN5 +#define IEN_PERIA_INTA246 IEN6 +#define IEN_PERIA_INTA247 IEN7 +#define IEN_PERIA_INTA248 IEN0 +#define IEN_PERIA_INTA249 IEN1 +#define IEN_PERIA_INTA250 IEN2 +#define IEN_PERIA_INTA251 IEN3 +#define IEN_PERIA_INTA252 IEN4 +#define IEN_PERIA_INTA253 IEN5 +#define IEN_PERIA_INTA254 IEN6 +#define IEN_PERIA_INTA255 IEN7 + +#define VECT_BSC_BUSERR 16 +#define VECT_RAM_RAMERR 18 +#define VECT_FCU_FIFERR 21 +#define VECT_FCU_FRDYI 23 +#define VECT_ICU_SWINT2 26 +#define VECT_ICU_SWINT 27 +#define VECT_CMT0_CMI0 28 +#define VECT_CMT1_CMI1 29 +#define VECT_CMTW0_CMWI0 30 +#define VECT_CMTW1_CMWI1 31 +#define VECT_USB0_D0FIFO0 34 +#define VECT_USB0_D1FIFO0 35 +#define VECT_RSPI0_SPRI0 38 +#define VECT_RSPI0_SPTI0 39 +#define VECT_RSPI1_SPRI1 40 +#define VECT_RSPI1_SPTI1 41 +#define VECT_QSPI_SPRI 42 +#define VECT_QSPI_SPTI 43 +#define VECT_SDHI_SBFAI 44 +#define VECT_MMCIF_MBFAI 45 +#define VECT_RIIC1_RXI1 50 +#define VECT_RIIC1_TXI1 51 +#define VECT_RIIC0_RXI0 52 +#define VECT_RIIC0_TXI0 53 +#define VECT_RIIC2_RXI2 54 +#define VECT_RIIC2_TXI2 55 +#define VECT_SCI0_RXI0 58 +#define VECT_SCI0_TXI0 59 +#define VECT_SCI1_RXI1 60 +#define VECT_SCI1_TXI1 61 +#define VECT_SCI2_RXI2 62 +#define VECT_SCI2_TXI2 63 +#define VECT_ICU_IRQ0 64 +#define VECT_ICU_IRQ1 65 +#define VECT_ICU_IRQ2 66 +#define VECT_ICU_IRQ3 67 +#define VECT_ICU_IRQ4 68 +#define VECT_ICU_IRQ5 69 +#define VECT_ICU_IRQ6 70 +#define VECT_ICU_IRQ7 71 +#define VECT_ICU_IRQ8 72 +#define VECT_ICU_IRQ9 73 +#define VECT_ICU_IRQ10 74 +#define VECT_ICU_IRQ11 75 +#define VECT_ICU_IRQ12 76 +#define VECT_ICU_IRQ13 77 +#define VECT_ICU_IRQ14 78 +#define VECT_ICU_IRQ15 79 +#define VECT_SCI3_RXI3 80 +#define VECT_SCI3_TXI3 81 +#define VECT_SCI4_RXI4 82 +#define VECT_SCI4_TXI4 83 +#define VECT_SCI5_RXI5 84 +#define VECT_SCI5_TXI5 85 +#define VECT_SCI6_RXI6 86 +#define VECT_SCI6_TXI6 87 +#define VECT_LVD1_LVD1 88 +#define VECT_LVD2_LVD2 89 +#define VECT_USB0_USBR0 90 +#define VECT_RTC_ALM 92 +#define VECT_RTC_PRD 93 +#define VECT_IWDT_IWUNI 95 +#define VECT_WDT_WUNI 96 +#define VECT_PDC_PCDFI 97 +#define VECT_SCI7_RXI7 98 +#define VECT_SCI7_TXI7 99 +#define VECT_SCI8_RXI8 100 +#define VECT_SCI8_TXI8 101 +#define VECT_SCI9_RXI9 102 +#define VECT_SCI9_TXI9 103 +#define VECT_SCI10_RXI10 104 +#define VECT_SCI10_TXI10 105 +#define VECT_ICU_GROUPBE0 106 +#define VECT_ICU_GROUPBL2 107 +#define VECT_RSPI2_SPRI2 108 +#define VECT_RSPI2_SPTI2 109 +#define VECT_ICU_GROUPBL0 110 +#define VECT_ICU_GROUPBL1 111 +#define VECT_ICU_GROUPAL0 112 +#define VECT_ICU_GROUPAL1 113 +#define VECT_SCI11_RXI11 114 +#define VECT_SCI11_TXI11 115 +#define VECT_SCI12_RXI12 116 +#define VECT_SCI12_TXI12 117 +#define VECT_DMAC_DMAC0I 120 +#define VECT_DMAC_DMAC1I 121 +#define VECT_DMAC_DMAC2I 122 +#define VECT_DMAC_DMAC3I 123 +#define VECT_DMAC_DMAC74I 124 +#define VECT_OST_OSTDI 125 +#define VECT_EXDMAC_EXDMAC0I 126 +#define VECT_EXDMAC_EXDMAC1I 127 +#define VECT_PERIB_INTB128 128 +#define VECT_PERIB_INTB129 129 +#define VECT_PERIB_INTB130 130 +#define VECT_PERIB_INTB131 131 +#define VECT_PERIB_INTB132 132 +#define VECT_PERIB_INTB133 133 +#define VECT_PERIB_INTB134 134 +#define VECT_PERIB_INTB135 135 +#define VECT_PERIB_INTB136 136 +#define VECT_PERIB_INTB137 137 +#define VECT_PERIB_INTB138 138 +#define VECT_PERIB_INTB139 139 +#define VECT_PERIB_INTB140 140 +#define VECT_PERIB_INTB141 141 +#define VECT_PERIB_INTB142 142 +#define VECT_PERIB_INTB143 143 +#define VECT_PERIB_INTB144 144 +#define VECT_PERIB_INTB145 145 +#define VECT_PERIB_INTB146 146 +#define VECT_PERIB_INTB147 147 +#define VECT_PERIB_INTB148 148 +#define VECT_PERIB_INTB149 149 +#define VECT_PERIB_INTB150 150 +#define VECT_PERIB_INTB151 151 +#define VECT_PERIB_INTB152 152 +#define VECT_PERIB_INTB153 153 +#define VECT_PERIB_INTB154 154 +#define VECT_PERIB_INTB155 155 +#define VECT_PERIB_INTB156 156 +#define VECT_PERIB_INTB157 157 +#define VECT_PERIB_INTB158 158 +#define VECT_PERIB_INTB159 159 +#define VECT_PERIB_INTB160 160 +#define VECT_PERIB_INTB161 161 +#define VECT_PERIB_INTB162 162 +#define VECT_PERIB_INTB163 163 +#define VECT_PERIB_INTB164 164 +#define VECT_PERIB_INTB165 165 +#define VECT_PERIB_INTB166 166 +#define VECT_PERIB_INTB167 167 +#define VECT_PERIB_INTB168 168 +#define VECT_PERIB_INTB169 169 +#define VECT_PERIB_INTB170 170 +#define VECT_PERIB_INTB171 171 +#define VECT_PERIB_INTB172 172 +#define VECT_PERIB_INTB173 173 +#define VECT_PERIB_INTB174 174 +#define VECT_PERIB_INTB175 175 +#define VECT_PERIB_INTB176 176 +#define VECT_PERIB_INTB177 177 +#define VECT_PERIB_INTB178 178 +#define VECT_PERIB_INTB179 179 +#define VECT_PERIB_INTB180 180 +#define VECT_PERIB_INTB181 181 +#define VECT_PERIB_INTB182 182 +#define VECT_PERIB_INTB183 183 +#define VECT_PERIB_INTB184 184 +#define VECT_PERIB_INTB185 185 +#define VECT_PERIB_INTB186 186 +#define VECT_PERIB_INTB187 187 +#define VECT_PERIB_INTB188 188 +#define VECT_PERIB_INTB189 189 +#define VECT_PERIB_INTB190 190 +#define VECT_PERIB_INTB191 191 +#define VECT_PERIB_INTB192 192 +#define VECT_PERIB_INTB193 193 +#define VECT_PERIB_INTB194 194 +#define VECT_PERIB_INTB195 195 +#define VECT_PERIB_INTB196 196 +#define VECT_PERIB_INTB197 197 +#define VECT_PERIB_INTB198 198 +#define VECT_PERIB_INTB199 199 +#define VECT_PERIB_INTB200 200 +#define VECT_PERIB_INTB201 201 +#define VECT_PERIB_INTB202 202 +#define VECT_PERIB_INTB203 203 +#define VECT_PERIB_INTB204 204 +#define VECT_PERIB_INTB205 205 +#define VECT_PERIB_INTB206 206 +#define VECT_PERIB_INTB207 207 +#define VECT_PERIA_INTA208 208 +#define VECT_PERIA_INTA209 209 +#define VECT_PERIA_INTA210 210 +#define VECT_PERIA_INTA211 211 +#define VECT_PERIA_INTA212 212 +#define VECT_PERIA_INTA213 213 +#define VECT_PERIA_INTA214 214 +#define VECT_PERIA_INTA215 215 +#define VECT_PERIA_INTA216 216 +#define VECT_PERIA_INTA217 217 +#define VECT_PERIA_INTA218 218 +#define VECT_PERIA_INTA219 219 +#define VECT_PERIA_INTA220 220 +#define VECT_PERIA_INTA221 221 +#define VECT_PERIA_INTA222 222 +#define VECT_PERIA_INTA223 223 +#define VECT_PERIA_INTA224 224 +#define VECT_PERIA_INTA225 225 +#define VECT_PERIA_INTA226 226 +#define VECT_PERIA_INTA227 227 +#define VECT_PERIA_INTA228 228 +#define VECT_PERIA_INTA229 229 +#define VECT_PERIA_INTA230 230 +#define VECT_PERIA_INTA231 231 +#define VECT_PERIA_INTA232 232 +#define VECT_PERIA_INTA233 233 +#define VECT_PERIA_INTA234 234 +#define VECT_PERIA_INTA235 235 +#define VECT_PERIA_INTA236 236 +#define VECT_PERIA_INTA237 237 +#define VECT_PERIA_INTA238 238 +#define VECT_PERIA_INTA239 239 +#define VECT_PERIA_INTA240 240 +#define VECT_PERIA_INTA241 241 +#define VECT_PERIA_INTA242 242 +#define VECT_PERIA_INTA243 243 +#define VECT_PERIA_INTA244 244 +#define VECT_PERIA_INTA245 245 +#define VECT_PERIA_INTA246 246 +#define VECT_PERIA_INTA247 247 +#define VECT_PERIA_INTA248 248 +#define VECT_PERIA_INTA249 249 +#define VECT_PERIA_INTA250 250 +#define VECT_PERIA_INTA251 251 +#define VECT_PERIA_INTA252 252 +#define VECT_PERIA_INTA253 253 +#define VECT_PERIA_INTA254 254 +#define VECT_PERIA_INTA255 255 + +#ifndef __ASSEMBLER__ + +#define MSTP_EXDMAC SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_EXDMAC0 SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_EXDMAC1 SYSTEM.MSTPCRA.BIT.MSTPA29 +#define MSTP_DMAC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC0 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC1 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC2 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC3 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC4 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC5 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC6 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DMAC7 SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DTC SYSTEM.MSTPCRA.BIT.MSTPA28 +#define MSTP_DA SYSTEM.MSTPCRA.BIT.MSTPA19 +#define MSTP_S12AD SYSTEM.MSTPCRA.BIT.MSTPA17 +#define MSTP_S12AD1 SYSTEM.MSTPCRA.BIT.MSTPA16 +#define MSTP_CMT0 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT1 SYSTEM.MSTPCRA.BIT.MSTPA15 +#define MSTP_CMT2 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_CMT3 SYSTEM.MSTPCRA.BIT.MSTPA14 +#define MSTP_TPU0 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU1 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU2 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU3 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU4 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPU5 SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_TPUA SYSTEM.MSTPCRA.BIT.MSTPA13 +#define MSTP_PPG0 SYSTEM.MSTPCRA.BIT.MSTPA11 +#define MSTP_PPG1 SYSTEM.MSTPCRA.BIT.MSTPA10 +#define MSTP_MTU SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU0 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU1 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU2 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU3 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU4 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU5 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU6 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU7 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_MTU8 SYSTEM.MSTPCRA.BIT.MSTPA9 +#define MSTP_TMR0 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR1 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR01 SYSTEM.MSTPCRA.BIT.MSTPA5 +#define MSTP_TMR2 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR3 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_TMR23 SYSTEM.MSTPCRA.BIT.MSTPA4 +#define MSTP_CMTW0 SYSTEM.MSTPCRA.BIT.MSTPA1 +#define MSTP_CMTW1 SYSTEM.MSTPCRA.BIT.MSTPA0 +#define MSTP_SCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SMCI0 SYSTEM.MSTPCRB.BIT.MSTPB31 +#define MSTP_SCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SMCI1 SYSTEM.MSTPCRB.BIT.MSTPB30 +#define MSTP_SCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SMCI2 SYSTEM.MSTPCRB.BIT.MSTPB29 +#define MSTP_SCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SMCI3 SYSTEM.MSTPCRB.BIT.MSTPB28 +#define MSTP_SCI4 SYSTEM.MSTPCRB.BIT.MSTPB27 +#define MSTP_SMCI4 SYSTEM.MSTPCRB.BIT.MSTPB27 +#define MSTP_SCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SMCI5 SYSTEM.MSTPCRB.BIT.MSTPB26 +#define MSTP_SCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SMCI6 SYSTEM.MSTPCRB.BIT.MSTPB25 +#define MSTP_SCI7 SYSTEM.MSTPCRB.BIT.MSTPB24 +#define MSTP_SMCI7 SYSTEM.MSTPCRB.BIT.MSTPB24 +#define MSTP_CRC SYSTEM.MSTPCRB.BIT.MSTPB23 +#define MSTP_PDC SYSTEM.MSTPCRB.BIT.MSTPB22 +#define MSTP_RIIC0 SYSTEM.MSTPCRB.BIT.MSTPB21 +#define MSTP_RIIC1 SYSTEM.MSTPCRB.BIT.MSTPB20 +#define MSTP_USB0 SYSTEM.MSTPCRB.BIT.MSTPB19 +#define MSTP_RSPI0 SYSTEM.MSTPCRB.BIT.MSTPB17 +#define MSTP_RSPI1 SYSTEM.MSTPCRB.BIT.MSTPB16 +#define MSTP_EDMAC0 SYSTEM.MSTPCRB.BIT.MSTPB15 +#define MSTP_ETHERC0 SYSTEM.MSTPCRB.BIT.MSTPB15 +#define MSTP_ELC SYSTEM.MSTPCRB.BIT.MSTPB9 +#define MSTP_TEMPS SYSTEM.MSTPCRB.BIT.MSTPB8 +#define MSTP_DOC SYSTEM.MSTPCRB.BIT.MSTPB6 +#define MSTP_SCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_SMCI12 SYSTEM.MSTPCRB.BIT.MSTPB4 +#define MSTP_CAN1 SYSTEM.MSTPCRB.BIT.MSTPB1 +#define MSTP_CAN0 SYSTEM.MSTPCRB.BIT.MSTPB0 +#define MSTP_GLCDC SYSTEM.MSTPCRC.BIT.MSTPC29 +#define MSTP_DRW2D SYSTEM.MSTPCRC.BIT.MSTPC28 +#define MSTP_SCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SMCI8 SYSTEM.MSTPCRC.BIT.MSTPC27 +#define MSTP_SCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SMCI9 SYSTEM.MSTPCRC.BIT.MSTPC26 +#define MSTP_SCI10 SYSTEM.MSTPCRC.BIT.MSTPC25 +#define MSTP_SMCI10 SYSTEM.MSTPCRC.BIT.MSTPC25 +#define MSTP_SCI11 SYSTEM.MSTPCRC.BIT.MSTPC24 +#define MSTP_SMCI11 SYSTEM.MSTPCRC.BIT.MSTPC24 +#define MSTP_QSPI SYSTEM.MSTPCRC.BIT.MSTPC23 +#define MSTP_RSPI2 SYSTEM.MSTPCRC.BIT.MSTPC22 +#define MSTP_CAC SYSTEM.MSTPCRC.BIT.MSTPC19 +#define MSTP_RIIC2 SYSTEM.MSTPCRC.BIT.MSTPC17 +#define MSTP_STBYRAM SYSTEM.MSTPCRC.BIT.MSTPC7 +#define MSTP_RAM2 SYSTEM.MSTPCRC.BIT.MSTPC2 +#define MSTP_RAM0 SYSTEM.MSTPCRC.BIT.MSTPC0 +#define MSTP_MMCIF SYSTEM.MSTPCRD.BIT.MSTPD21 +#define MSTP_SDHI SYSTEM.MSTPCRD.BIT.MSTPD19 +#define MSTP_SDSI SYSTEM.MSTPCRD.BIT.MSTPD13 + +#define IS_CAN0_ERS0 IS0 +#define IS_CAN1_ERS1 IS1 +#define IS_SCI0_TEI0 IS0 +#define IS_SCI0_ERI0 IS1 +#define IS_SCI1_TEI1 IS2 +#define IS_SCI1_ERI1 IS3 +#define IS_SCI2_TEI2 IS4 +#define IS_SCI2_ERI2 IS5 +#define IS_SCI3_TEI3 IS6 +#define IS_SCI3_ERI3 IS7 +#define IS_SCI4_TEI4 IS8 +#define IS_SCI4_ERI4 IS9 +#define IS_SCI5_TEI5 IS10 +#define IS_SCI5_ERI5 IS11 +#define IS_SCI6_TEI6 IS12 +#define IS_SCI6_ERI6 IS13 +#define IS_SCI7_TEI7 IS14 +#define IS_SCI7_ERI7 IS15 +#define IS_SCI12_TEI12 IS16 +#define IS_SCI12_ERI12 IS17 +#define IS_SCI12_SCIX0 IS18 +#define IS_SCI12_SCIX1 IS19 +#define IS_SCI12_SCIX2 IS20 +#define IS_SCI12_SCIX3 IS21 +#define IS_QSPI_QSPSSLI IS24 +#define IS_CAC_FERRI IS26 +#define IS_CAC_MENDI IS27 +#define IS_CAC_OVFI IS28 +#define IS_DOC_DOPCI IS29 +#define IS_PDC_PCFEI IS30 +#define IS_PDC_PCERI IS31 +#define IS_SDHI_CDETI IS3 +#define IS_SDHI_CACI IS4 +#define IS_SDHI_SDACI IS5 +#define IS_MMCIF_CDETIO IS6 +#define IS_MMCIF_ERRIO IS7 +#define IS_MMCIF_ACCIO IS8 +#define IS_POE3_OEI1 IS9 +#define IS_POE3_OEI2 IS10 +#define IS_POE3_OEI3 IS11 +#define IS_POE3_OEI4 IS12 +#define IS_RIIC0_TEI0 IS13 +#define IS_RIIC0_EEI0 IS14 +#define IS_RIIC2_TEI2 IS15 +#define IS_RIIC2_EEI2 IS16 +#define IS_S12AD_S12CMPAI IS20 +#define IS_S12AD_S12CMPBI IS21 +#define IS_S12AD1_S12CMPAI1 IS22 +#define IS_S12AD1_S12CMPBI1 IS23 +#define IS_SCI8_TEI8 IS24 +#define IS_SCI8_ERI8 IS25 +#define IS_SCI9_TEI9 IS26 +#define IS_SCI9_ERI9 IS27 +#define IS_RIIC1_TEI1 IS28 +#define IS_RIIC1_EEI1 IS29 +#define IS_SDSI_SDIOI IS0 +#define IS_SCI10_TEI10 IS8 +#define IS_SCI10_ERI10 IS9 +#define IS_SCI11_TEI11 IS12 +#define IS_SCI11_ERI11 IS13 +#define IS_RSPI0_SPII0 IS16 +#define IS_RSPI0_SPEI0 IS17 +#define IS_RSPI1_SPII1 IS18 +#define IS_RSPI1_SPEI1 IS19 +#define IS_RSPI2_SPII2 IS20 +#define IS_RSPI2_SPEI2 IS21 +#define IS_EDMAC0_EINT0 IS4 +#define IS_GLCDC_VPOS IS8 +#define IS_GLCDC_GR1UF IS9 +#define IS_GLCDC_GR2UF IS10 +#define IS_DRW2D_DRWIRQ IS11 + +#define EN_CAN0_ERS0 EN0 +#define EN_CAN1_ERS1 EN1 +#define EN_SCI0_TEI0 EN0 +#define EN_SCI0_ERI0 EN1 +#define EN_SCI1_TEI1 EN2 +#define EN_SCI1_ERI1 EN3 +#define EN_SCI2_TEI2 EN4 +#define EN_SCI2_ERI2 EN5 +#define EN_SCI3_TEI3 EN6 +#define EN_SCI3_ERI3 EN7 +#define EN_SCI4_TEI4 EN8 +#define EN_SCI4_ERI4 EN9 +#define EN_SCI5_TEI5 EN10 +#define EN_SCI5_ERI5 EN11 +#define EN_SCI6_TEI6 EN12 +#define EN_SCI6_ERI6 EN13 +#define EN_SCI7_TEI7 EN14 +#define EN_SCI7_ERI7 EN15 +#define EN_SCI12_TEI12 EN16 +#define EN_SCI12_ERI12 EN17 +#define EN_SCI12_SCIX0 EN18 +#define EN_SCI12_SCIX1 EN19 +#define EN_SCI12_SCIX2 EN20 +#define EN_SCI12_SCIX3 EN21 +#define EN_QSPI_QSPSSLI EN24 +#define EN_CAC_FERRI EN26 +#define EN_CAC_MENDI EN27 +#define EN_CAC_OVFI EN28 +#define EN_DOC_DOPCI EN29 +#define EN_PDC_PCFEI EN30 +#define EN_PDC_PCERI EN31 +#define EN_SDHI_CDETI EN3 +#define EN_SDHI_CACI EN4 +#define EN_SDHI_SDACI EN5 +#define EN_MMCIF_CDETIO EN6 +#define EN_MMCIF_ERRIO EN7 +#define EN_MMCIF_ACCIO EN8 +#define EN_POE3_OEI1 EN9 +#define EN_POE3_OEI2 EN10 +#define EN_POE3_OEI3 EN11 +#define EN_POE3_OEI4 EN12 +#define EN_RIIC0_TEI0 EN13 +#define EN_RIIC0_EEI0 EN14 +#define EN_RIIC2_TEI2 EN15 +#define EN_RIIC2_EEI2 EN16 +#define EN_S12AD_S12CMPAI EN20 +#define EN_S12AD_S12CMPBI EN21 +#define EN_S12AD1_S12CMPAI1 EN22 +#define EN_S12AD1_S12CMPBI1 EN23 +#define EN_SCI8_TEI8 EN24 +#define EN_SCI8_ERI8 EN25 +#define EN_SCI9_TEI9 EN26 +#define EN_SCI9_ERI9 EN27 +#define EN_RIIC1_TEI1 EN28 +#define EN_RIIC1_EEI1 EN29 +#define EN_SDSI_SDIOI EN0 +#define EN_SCI10_TEI10 EN8 +#define EN_SCI10_ERI10 EN9 +#define EN_SCI11_TEI11 EN12 +#define EN_SCI11_ERI11 EN13 +#define EN_RSPI0_SPII0 EN16 +#define EN_RSPI0_SPEI0 EN17 +#define EN_RSPI1_SPII1 EN18 +#define EN_RSPI1_SPEI1 EN19 +#define EN_RSPI2_SPII2 EN20 +#define EN_RSPI2_SPEI2 EN21 +#define EN_EDMAC0_EINT0 EN4 +#define EN_GLCDC_VPOS EN8 +#define EN_GLCDC_GR1UF EN9 +#define EN_GLCDC_GR2UF EN10 +#define EN_DRW2D_DRWIRQ EN11 + +#define CLR_CAN0_ERS0 CLR0 +#define CLR_CAN1_ERS1 CLR1 + +#define GEN_CAN0_ERS0 GENBE0 +#define GEN_CAN1_ERS1 GENBE0 +#define GEN_SCI0_TEI0 GENBL0 +#define GEN_SCI0_ERI0 GENBL0 +#define GEN_SCI1_TEI1 GENBL0 +#define GEN_SCI1_ERI1 GENBL0 +#define GEN_SCI2_TEI2 GENBL0 +#define GEN_SCI2_ERI2 GENBL0 +#define GEN_SCI3_TEI3 GENBL0 +#define GEN_SCI3_ERI3 GENBL0 +#define GEN_SCI4_TEI4 GENBL0 +#define GEN_SCI4_ERI4 GENBL0 +#define GEN_SCI5_TEI5 GENBL0 +#define GEN_SCI5_ERI5 GENBL0 +#define GEN_SCI6_TEI6 GENBL0 +#define GEN_SCI6_ERI6 GENBL0 +#define GEN_SCI7_TEI7 GENBL0 +#define GEN_SCI7_ERI7 GENBL0 +#define GEN_SCI12_TEI12 GENBL0 +#define GEN_SCI12_ERI12 GENBL0 +#define GEN_SCI12_SCIX0 GENBL0 +#define GEN_SCI12_SCIX1 GENBL0 +#define GEN_SCI12_SCIX2 GENBL0 +#define GEN_SCI12_SCIX3 GENBL0 +#define GEN_QSPI_QSPSSLI GENBL0 +#define GEN_CAC_FERRI GENBL0 +#define GEN_CAC_MENDI GENBL0 +#define GEN_CAC_OVFI GENBL0 +#define GEN_DOC_DOPCI GENBL0 +#define GEN_PDC_PCFEI GENBL0 +#define GEN_PDC_PCERI GENBL0 +#define GEN_SDHI_CDETI GENBL1 +#define GEN_SDHI_CACI GENBL1 +#define GEN_SDHI_SDACI GENBL1 +#define GEN_MMCIF_CDETIO GENBL1 +#define GEN_MMCIF_ERRIO GENBL1 +#define GEN_MMCIF_ACCIO GENBL1 +#define GEN_POE3_OEI1 GENBL1 +#define GEN_POE3_OEI2 GENBL1 +#define GEN_POE3_OEI3 GENBL1 +#define GEN_POE3_OEI4 GENBL1 +#define GEN_RIIC0_TEI0 GENBL1 +#define GEN_RIIC0_EEI0 GENBL1 +#define GEN_RIIC2_TEI2 GENBL1 +#define GEN_RIIC2_EEI2 GENBL1 +#define GEN_S12AD_S12CMPAI GENBL1 +#define GEN_S12AD_S12CMPBI GENBL1 +#define GEN_S12AD1_S12CMPAI1 GENBL1 +#define GEN_S12AD1_S12CMPBI1 GENBL1 +#define GEN_SCI8_TEI8 GENBL1 +#define GEN_SCI8_ERI8 GENBL1 +#define GEN_SCI9_TEI9 GENBL1 +#define GEN_SCI9_ERI9 GENBL1 +#define GEN_RIIC1_TEI1 GENBL1 +#define GEN_RIIC1_EEI1 GENBL1 +#define GEN_SDSI_SDIOI GENBL2 +#define GEN_SCI10_TEI10 GENAL0 +#define GEN_SCI10_ERI10 GENAL0 +#define GEN_SCI11_TEI11 GENAL0 +#define GEN_SCI11_ERI11 GENAL0 +#define GEN_RSPI0_SPII0 GENAL0 +#define GEN_RSPI0_SPEI0 GENAL0 +#define GEN_RSPI1_SPII1 GENAL0 +#define GEN_RSPI1_SPEI1 GENAL0 +#define GEN_RSPI2_SPII2 GENAL0 +#define GEN_RSPI2_SPEI2 GENAL0 +#define GEN_EDMAC0_EINT0 GENAL1 +#define GEN_GLCDC_VPOS GENAL1 +#define GEN_GLCDC_GR1UF GENAL1 +#define GEN_GLCDC_GR2UF GENAL1 +#define GEN_DRW2D_DRWIRQ GENAL1 + +#define GRP_CAN0_ERS0 GRPBE0 +#define GRP_CAN1_ERS1 GRPBE0 +#define GRP_SCI0_TEI0 GRPBL0 +#define GRP_SCI0_ERI0 GRPBL0 +#define GRP_SCI1_TEI1 GRPBL0 +#define GRP_SCI1_ERI1 GRPBL0 +#define GRP_SCI2_TEI2 GRPBL0 +#define GRP_SCI2_ERI2 GRPBL0 +#define GRP_SCI3_TEI3 GRPBL0 +#define GRP_SCI3_ERI3 GRPBL0 +#define GRP_SCI4_TEI4 GRPBL0 +#define GRP_SCI4_ERI4 GRPBL0 +#define GRP_SCI5_TEI5 GRPBL0 +#define GRP_SCI5_ERI5 GRPBL0 +#define GRP_SCI6_TEI6 GRPBL0 +#define GRP_SCI6_ERI6 GRPBL0 +#define GRP_SCI7_TEI7 GRPBL0 +#define GRP_SCI7_ERI7 GRPBL0 +#define GRP_SCI12_TEI12 GRPBL0 +#define GRP_SCI12_ERI12 GRPBL0 +#define GRP_SCI12_SCIX0 GRPBL0 +#define GRP_SCI12_SCIX1 GRPBL0 +#define GRP_SCI12_SCIX2 GRPBL0 +#define GRP_SCI12_SCIX3 GRPBL0 +#define GRP_QSPI_QSPSSLI GRPBL0 +#define GRP_CAC_FERRI GRPBL0 +#define GRP_CAC_MENDI GRPBL0 +#define GRP_CAC_OVFI GRPBL0 +#define GRP_DOC_DOPCI GRPBL0 +#define GRP_PDC_PCFEI GRPBL0 +#define GRP_PDC_PCERI GRPBL0 +#define GRP_SDHI_CDETI GRPBL1 +#define GRP_SDHI_CACI GRPBL1 +#define GRP_SDHI_SDACI GRPBL1 +#define GRP_MMCIF_CDETIO GRPBL1 +#define GRP_MMCIF_ERRIO GRPBL1 +#define GRP_MMCIF_ACCIO GRPBL1 +#define GRP_POE3_OEI1 GRPBL1 +#define GRP_POE3_OEI2 GRPBL1 +#define GRP_POE3_OEI3 GRPBL1 +#define GRP_POE3_OEI4 GRPBL1 +#define GRP_RIIC0_TEI0 GRPBL1 +#define GRP_RIIC0_EEI0 GRPBL1 +#define GRP_RIIC2_TEI2 GRPBL1 +#define GRP_RIIC2_EEI2 GRPBL1 +#define GRP_S12AD_S12CMPAI GRPBL1 +#define GRP_S12AD_S12CMPBI GRPBL1 +#define GRP_S12AD1_S12CMPAI1 GRPBL1 +#define GRP_S12AD1_S12CMPBI1 GRPBL1 +#define GRP_SCI8_TEI8 GRPBL1 +#define GRP_SCI8_ERI8 GRPBL1 +#define GRP_SCI9_TEI9 GRPBL1 +#define GRP_SCI9_ERI9 GRPBL1 +#define GRP_RIIC1_TEI1 GRPBL1 +#define GRP_RIIC1_EEI1 GRPBL1 +#define GRP_SDSI_SDIOI GRPBL2 +#define GRP_SCI10_TEI10 GRPAL0 +#define GRP_SCI10_ERI10 GRPAL0 +#define GRP_SCI11_TEI11 GRPAL0 +#define GRP_SCI11_ERI11 GRPAL0 +#define GRP_RSPI0_SPII0 GRPAL0 +#define GRP_RSPI0_SPEI0 GRPAL0 +#define GRP_RSPI1_SPII1 GRPAL0 +#define GRP_RSPI1_SPEI1 GRPAL0 +#define GRP_RSPI2_SPII2 GRPAL0 +#define GRP_RSPI2_SPEI2 GRPAL0 +#define GRP_EDMAC0_EINT0 GRPAL1 +#define GRP_GLCDC_VPOS GRPAL1 +#define GRP_GLCDC_GR1UF GRPAL1 +#define GRP_GLCDC_GR2UF GRPAL1 +#define GRP_DRW2D_DRWIRQ GRPAL1 + +#define GCR_CAN0_ERS0 GCRBE0 +#define GCR_CAN1_ERS1 GCRBE0 + +#define __IR( x ) ICU.IR[ IR ## x ].BIT.IR +#define _IR( x ) __IR( x ) +#define IR( x , y ) _IR( _ ## x ## _ ## y ) +#define __DTCE( x ) ICU.DTCER[ DTCE ## x ].BIT.DTCE +#define _DTCE( x ) __DTCE( x ) +#define DTCE( x , y ) _DTCE( _ ## x ## _ ## y ) +#define __IEN( x ) ICU.IER[ IER ## x ].BIT.IEN ## x +#define _IEN( x ) __IEN( x ) +#define IEN( x , y ) _IEN( _ ## x ## _ ## y ) +#define __IPR( x ) ICU.IPR[ IPR ## x ].BIT.IPR +#define _IPR( x ) __IPR( x ) +#define IPR( x , y ) _IPR( _ ## x ## _ ## y ) +#define __VECT( x ) VECT ## x +#define _VECT( x ) __VECT( x ) +#define VECT( x , y ) _VECT( _ ## x ## _ ## y ) +#define __MSTP( x ) MSTP ## x +#define _MSTP( x ) __MSTP( x ) +#define MSTP( x ) _MSTP( _ ## x ) + +#define __IS( x ) ICU.GRP ## x.BIT.IS ## x +#define _IS( x ) __IS( x ) +#define IS( x , y ) _IS( _ ## x ## _ ## y ) +#define __EN( x ) ICU.GEN ## x.BIT.EN ## x +#define _EN( x ) __EN( x ) +#define EN( x , y ) _EN( _ ## x ## _ ## y ) +#define __CLR( x ) ICU.GCR ## x.BIT.CLR ## x +#define _CLR( x ) __CLR( x ) +#define CLR( x , y ) _CLR( _ ## x ## _ ## y ) + +#define BSC (*(volatile struct st_bsc *)0x81300) +#define CAC (*(volatile struct st_cac *)0x8b000) +#define CMT (*(volatile struct st_cmt *)0x88000) +#define CMT0 (*(volatile struct st_cmt0 *)0x88002) +#define CMT1 (*(volatile struct st_cmt0 *)0x88008) +#define CMT2 (*(volatile struct st_cmt0 *)0x88012) +#define CMT3 (*(volatile struct st_cmt0 *)0x88018) +#define CMTW0 (*(volatile struct st_cmtw *)0x94200) +#define ICU (*(volatile struct st_icu *)0x87000) +#define MPC (*(volatile struct st_mpc *)0x8c100) +#define PORT0 (*(volatile struct st_port0 *)0x8c000) +#define PORT1 (*(volatile struct st_port1 *)0x8c001) +#define PORT2 (*(volatile struct st_port2 *)0x8c002) +#define PORT3 (*(volatile struct st_port3 *)0x8c003) +#define PORT5 (*(volatile struct st_port5 *)0x8c005) +#define PORT6 (*(volatile struct st_port6 *)0x8c006) +#define PORT7 (*(volatile struct st_port7 *)0x8c007) +#define PORT8 (*(volatile struct st_port8 *)0x8c008) +#define PORT9 (*(volatile struct st_port9 *)0x8c009) +#define PORTA (*(volatile struct st_porta *)0x8c00a) +#define PORTB (*(volatile struct st_portb *)0x8c00b) +#define PORTC (*(volatile struct st_portc *)0x8c00c) +#define PORTE (*(volatile struct st_porte *)0x8c00e) +#define PORTF (*(volatile struct st_portf *)0x8c00f) +#define PORTG (*(volatile struct st_portg *)0x8c010) +#define PORTJ (*(volatile struct st_portj *)0x8c012) +#define RTC (*(volatile struct st_rtc *)0x8c400) +#define SCI0 (*(volatile struct st_sci0 *)0x8a000) +#define SCI1 (*(volatile struct st_sci0 *)0x8a020) +#define SCI2 (*(volatile struct st_sci0 *)0x8a040) +#define SCI3 (*(volatile struct st_sci0 *)0x8a060) +#define SCI4 (*(volatile struct st_sci0 *)0x8a080) +#define SCI5 (*(volatile struct st_sci0 *)0x8a0a0) +#define SCI6 (*(volatile struct st_sci0 *)0x8a0c0) +#define SCI7 (*(volatile struct st_sci0 *)0x8a0e0) +#define SCI8 (*(volatile struct st_sci0 *)0x8a100) +#define SCI9 (*(volatile struct st_sci0 *)0x8a120) +#define SCI10 (*(volatile struct st_sci10 *)0xd0040) +#define SCI11 (*(volatile struct st_sci10 *)0xd0060) +#define SCI12 (*(volatile struct st_sci12 *)0x8b300) + +#define SYSTEM (*(volatile struct st_system *)0x80000) + +/**************************************************************************** + * Public Types + ***************************************************************************/ +typedef enum enum_ir +{ + IR_BSC_BUSERR = 16, + IR_RAM_RAMERR = 18, + IR_FCU_FIFERR = 21, + IR_FCU_FRDYI = 23, + IR_ICU_SWINT2 = 26, + IR_ICU_SWINT, + IR_CMT0_CMI0, + IR_CMT1_CMI1, + IR_CMTW0_CMWI0, + IR_CMTW1_CMWI1, + IR_USB0_D0FIFO0 = 34, + IR_USB0_D1FIFO0, + IR_RSPI0_SPRI0 = 38, + IR_RSPI0_SPTI0, + IR_RSPI1_SPRI1, + IR_RSPI1_SPTI1, + IR_QSPI_SPRI, + IR_QSPI_SPTI, + IR_SDHI_SBFAI, + IR_MMCIF_MBFAI, + IR_RIIC1_RXI1 = 50, + IR_RIIC1_TXI1, + IR_RIIC0_RXI0, + IR_RIIC0_TXI0, + IR_RIIC2_RXI2, + IR_RIIC2_TXI2, + IR_SCI0_RXI0 = 58, + IR_SCI0_TXI0, + IR_SCI1_RXI1, + IR_SCI1_TXI1, + IR_SCI2_RXI2, + IR_SCI2_TXI2, + IR_ICU_IRQ0, + IR_ICU_IRQ1, + IR_ICU_IRQ2, + IR_ICU_IRQ3, + IR_ICU_IRQ4, + IR_ICU_IRQ5, + IR_ICU_IRQ6, + IR_ICU_IRQ7, + IR_ICU_IRQ8, + IR_ICU_IRQ9, + IR_ICU_IRQ10, + IR_ICU_IRQ11, + IR_ICU_IRQ12, + IR_ICU_IRQ13, + IR_ICU_IRQ14, + IR_ICU_IRQ15, + IR_SCI3_RXI3, + IR_SCI3_TXI3, + IR_SCI4_RXI4, + IR_SCI4_TXI4, + IR_SCI5_RXI5, + IR_SCI5_TXI5, + IR_SCI6_RXI6, + IR_SCI6_TXI6, + IR_LVD1_LVD1, + IR_LVD2_LVD2, + IR_USB0_USBR0, + IR_RTC_ALM = 92, + IR_RTC_PRD, + IR_IWDT_IWUNI = 95, + IR_WDT_WUNI, + IR_PDC_PCDFI, + IR_SCI7_RXI7, + IR_SCI7_TXI7, + IR_SCI8_RXI8, + IR_SCI8_TXI8, + IR_SCI9_RXI9, + IR_SCI9_TXI9, + IR_SCI10_RXI10, + IR_SCI10_TXI10, + IR_ICU_GROUPBE0, + IR_ICU_GROUPBL2, + IR_RSPI2_SPRI2, + IR_RSPI2_SPTI2, + IR_ICU_GROUPBL0, + IR_ICU_GROUPBL1, + IR_ICU_GROUPAL0, + IR_ICU_GROUPAL1, + IR_SCI11_RXI11, + IR_SCI11_TXI11, + IR_SCI12_RXI12, + IR_SCI12_TXI12, + IR_DMAC_DMAC0I = 120, + IR_DMAC_DMAC1I, + IR_DMAC_DMAC2I, + IR_DMAC_DMAC3I, + IR_DMAC_DMAC74I, + IR_OST_OSTDI, + IR_EXDMAC_EXDMAC0I, + IR_EXDMAC_EXDMAC1I, + IR_PERIB_INTB128, + IR_PERIB_INTB129, + IR_PERIB_INTB130, + IR_PERIB_INTB131, + IR_PERIB_INTB132, + IR_PERIB_INTB133, + IR_PERIB_INTB134, + IR_PERIB_INTB135, + IR_PERIB_INTB136, + IR_PERIB_INTB137, + IR_PERIB_INTB138, + IR_PERIB_INTB139, + IR_PERIB_INTB140, + IR_PERIB_INTB141, + IR_PERIB_INTB142, + IR_PERIB_INTB143, + IR_PERIB_INTB144, + IR_PERIB_INTB145, + IR_PERIB_INTB146, + IR_PERIB_INTB147, + IR_PERIB_INTB148, + IR_PERIB_INTB149, + IR_PERIB_INTB150, + IR_PERIB_INTB151, + IR_PERIB_INTB152, + IR_PERIB_INTB153, + IR_PERIB_INTB154, + IR_PERIB_INTB155, + IR_PERIB_INTB156, + IR_PERIB_INTB157, + IR_PERIB_INTB158, + IR_PERIB_INTB159, + IR_PERIB_INTB160, + IR_PERIB_INTB161, + IR_PERIB_INTB162, + IR_PERIB_INTB163, + IR_PERIB_INTB164, + IR_PERIB_INTB165, + IR_PERIB_INTB166, + IR_PERIB_INTB167, + IR_PERIB_INTB168, + IR_PERIB_INTB169, + IR_PERIB_INTB170, + IR_PERIB_INTB171, + IR_PERIB_INTB172, + IR_PERIB_INTB173, + IR_PERIB_INTB174, + IR_PERIB_INTB175, + IR_PERIB_INTB176, + IR_PERIB_INTB177, + IR_PERIB_INTB178, + IR_PERIB_INTB179, + IR_PERIB_INTB180, + IR_PERIB_INTB181, + IR_PERIB_INTB182, + IR_PERIB_INTB183, + IR_PERIB_INTB184, + IR_PERIB_INTB185, + IR_PERIB_INTB186, + IR_PERIB_INTB187, + IR_PERIB_INTB188, + IR_PERIB_INTB189, + IR_PERIB_INTB190, + IR_PERIB_INTB191, + IR_PERIB_INTB192, + IR_PERIB_INTB193, + IR_PERIB_INTB194, + IR_PERIB_INTB195, + IR_PERIB_INTB196, + IR_PERIB_INTB197, + IR_PERIB_INTB198, + IR_PERIB_INTB199, + IR_PERIB_INTB200, + IR_PERIB_INTB201, + IR_PERIB_INTB202, + IR_PERIB_INTB203, + IR_PERIB_INTB204, + IR_PERIB_INTB205, + IR_PERIB_INTB206, + IR_PERIB_INTB207, + IR_PERIA_INTA208, + IR_PERIA_INTA209, + IR_PERIA_INTA210, + IR_PERIA_INTA211, + IR_PERIA_INTA212, + IR_PERIA_INTA213, + IR_PERIA_INTA214, + IR_PERIA_INTA215, + IR_PERIA_INTA216, + IR_PERIA_INTA217, + IR_PERIA_INTA218, + IR_PERIA_INTA219, + IR_PERIA_INTA220, + IR_PERIA_INTA221, + IR_PERIA_INTA222, + IR_PERIA_INTA223, + IR_PERIA_INTA224, + IR_PERIA_INTA225, + IR_PERIA_INTA226, + IR_PERIA_INTA227, + IR_PERIA_INTA228, + IR_PERIA_INTA229, + IR_PERIA_INTA230, + IR_PERIA_INTA231, + IR_PERIA_INTA232, + IR_PERIA_INTA233, + IR_PERIA_INTA234, + IR_PERIA_INTA235, + IR_PERIA_INTA236, + IR_PERIA_INTA237, + IR_PERIA_INTA238, + IR_PERIA_INTA239, + IR_PERIA_INTA240, + IR_PERIA_INTA241, + IR_PERIA_INTA242, + IR_PERIA_INTA243, + IR_PERIA_INTA244, + IR_PERIA_INTA245, + IR_PERIA_INTA246, + IR_PERIA_INTA247, + IR_PERIA_INTA248, + IR_PERIA_INTA249, + IR_PERIA_INTA250, + IR_PERIA_INTA251, + IR_PERIA_INTA252, + IR_PERIA_INTA253, + IR_PERIA_INTA254, + IR_PERIA_INTA255 +} enum_ir_t; + +typedef enum enum_dtce +{ + DTCE_ICU_SWINT2 = 26, + DTCE_ICU_SWINT, + DTCE_CMT0_CMI0, + DTCE_CMT1_CMI1, + DTCE_CMTW0_CMWI0, + DTCE_CMTW1_CMWI1, + DTCE_USB0_D0FIFO0 = 34, + DTCE_USB0_D1FIFO0, + DTCE_RSPI0_SPRI0 = 38, + DTCE_RSPI0_SPTI0, + DTCE_RSPI1_SPRI1, + DTCE_RSPI1_SPTI1, + DTCE_QSPI_SPRI, + DTCE_QSPI_SPTI, + DTCE_SDHI_SBFAI, + DTCE_MMCIF_MBFAI, + DTCE_RIIC1_RXI1 = 50, + DTCE_RIIC1_TXI1, + DTCE_RIIC0_RXI0, + DTCE_RIIC0_TXI0, + DTCE_RIIC2_RXI2, + DTCE_RIIC2_TXI2, + DTCE_SCI0_RXI0 = 58, + DTCE_SCI0_TXI0, + DTCE_SCI1_RXI1, + DTCE_SCI1_TXI1, + DTCE_SCI2_RXI2, + DTCE_SCI2_TXI2, + DTCE_ICU_IRQ0, + DTCE_ICU_IRQ1, + DTCE_ICU_IRQ2, + DTCE_ICU_IRQ3, + DTCE_ICU_IRQ4, + DTCE_ICU_IRQ5, + DTCE_ICU_IRQ6, + DTCE_ICU_IRQ7, + DTCE_ICU_IRQ8, + DTCE_ICU_IRQ9, + DTCE_ICU_IRQ10, + DTCE_ICU_IRQ11, + DTCE_ICU_IRQ12, + DTCE_ICU_IRQ13, + DTCE_ICU_IRQ14, + DTCE_ICU_IRQ15, + DTCE_SCI3_RXI3, + DTCE_SCI3_TXI3, + DTCE_SCI4_RXI4, + DTCE_SCI4_TXI4, + DTCE_SCI5_RXI5, + DTCE_SCI5_TXI5, + DTCE_SCI6_RXI6, + DTCE_SCI6_TXI6, + DTCE_PDC_PCDFI = 97, + DTCE_SCI7_RXI7, + DTCE_SCI7_TXI7, + DTCE_SCI8_RXI8, + DTCE_SCI8_TXI8, + DTCE_SCI9_RXI9, + DTCE_SCI9_TXI9, + DTCE_SCI10_RXI10, + DTCE_SCI10_TXI10, + DTCE_RSPI2_SPRI2 = 108, + DTCE_RSPI2_SPTI2, + DTCE_SCI11_RXI11 = 114, + DTCE_SCI11_TXI11, + DTCE_SCI12_RXI12, + DTCE_SCI12_TXI12, + DTCE_DMAC_DMAC0I = 120, + DTCE_DMAC_DMAC1I, + DTCE_DMAC_DMAC2I, + DTCE_DMAC_DMAC3I, + DTCE_EXDMAC_EXDMAC0I = 126, + DTCE_EXDMAC_EXDMAC1I, + DTCE_PERIB_INTB128, + DTCE_PERIB_INTB129, + DTCE_PERIB_INTB130, + DTCE_PERIB_INTB131, + DTCE_PERIB_INTB132, + DTCE_PERIB_INTB133, + DTCE_PERIB_INTB134, + DTCE_PERIB_INTB135, + DTCE_PERIB_INTB136, + DTCE_PERIB_INTB137, + DTCE_PERIB_INTB138, + DTCE_PERIB_INTB139, + DTCE_PERIB_INTB140, + DTCE_PERIB_INTB141, + DTCE_PERIB_INTB142, + DTCE_PERIB_INTB143, + DTCE_PERIB_INTB144, + DTCE_PERIB_INTB145, + DTCE_PERIB_INTB146, + DTCE_PERIB_INTB147, + DTCE_PERIB_INTB148, + DTCE_PERIB_INTB149, + DTCE_PERIB_INTB150, + DTCE_PERIB_INTB151, + DTCE_PERIB_INTB152, + DTCE_PERIB_INTB153, + DTCE_PERIB_INTB154, + DTCE_PERIB_INTB155, + DTCE_PERIB_INTB156, + DTCE_PERIB_INTB157, + DTCE_PERIB_INTB158, + DTCE_PERIB_INTB159, + DTCE_PERIB_INTB160, + DTCE_PERIB_INTB161, + DTCE_PERIB_INTB162, + DTCE_PERIB_INTB163, + DTCE_PERIB_INTB164, + DTCE_PERIB_INTB165, + DTCE_PERIB_INTB166, + DTCE_PERIB_INTB167, + DTCE_PERIB_INTB168, + DTCE_PERIB_INTB169, + DTCE_PERIB_INTB170, + DTCE_PERIB_INTB171, + DTCE_PERIB_INTB172, + DTCE_PERIB_INTB173, + DTCE_PERIB_INTB174, + DTCE_PERIB_INTB175, + DTCE_PERIB_INTB176, + DTCE_PERIB_INTB177, + DTCE_PERIB_INTB178, + DTCE_PERIB_INTB179, + DTCE_PERIB_INTB180, + DTCE_PERIB_INTB181, + DTCE_PERIB_INTB182, + DTCE_PERIB_INTB183, + DTCE_PERIB_INTB184, + DTCE_PERIB_INTB185, + DTCE_PERIB_INTB186, + DTCE_PERIB_INTB187, + DTCE_PERIB_INTB188, + DTCE_PERIB_INTB189, + DTCE_PERIB_INTB190, + DTCE_PERIB_INTB191, + DTCE_PERIB_INTB192, + DTCE_PERIB_INTB193, + DTCE_PERIB_INTB194, + DTCE_PERIB_INTB195, + DTCE_PERIB_INTB196, + DTCE_PERIB_INTB197, + DTCE_PERIB_INTB198, + DTCE_PERIB_INTB199, + DTCE_PERIB_INTB200, + DTCE_PERIB_INTB201, + DTCE_PERIB_INTB202, + DTCE_PERIB_INTB203, + DTCE_PERIB_INTB204, + DTCE_PERIB_INTB205, + DTCE_PERIB_INTB206, + DTCE_PERIB_INTB207, + DTCE_PERIA_INTA208, + DTCE_PERIA_INTA209, + DTCE_PERIA_INTA210, + DTCE_PERIA_INTA211, + DTCE_PERIA_INTA212, + DTCE_PERIA_INTA213, + DTCE_PERIA_INTA214, + DTCE_PERIA_INTA215, + DTCE_PERIA_INTA216, + DTCE_PERIA_INTA217, + DTCE_PERIA_INTA218, + DTCE_PERIA_INTA219, + DTCE_PERIA_INTA220, + DTCE_PERIA_INTA221, + DTCE_PERIA_INTA222, + DTCE_PERIA_INTA223, + DTCE_PERIA_INTA224, + DTCE_PERIA_INTA225, + DTCE_PERIA_INTA226, + DTCE_PERIA_INTA227, + DTCE_PERIA_INTA228, + DTCE_PERIA_INTA229, + DTCE_PERIA_INTA230, + DTCE_PERIA_INTA231, + DTCE_PERIA_INTA232, + DTCE_PERIA_INTA233, + DTCE_PERIA_INTA234, + DTCE_PERIA_INTA235, + DTCE_PERIA_INTA236, + DTCE_PERIA_INTA237, + DTCE_PERIA_INTA238, + DTCE_PERIA_INTA239, + DTCE_PERIA_INTA240, + DTCE_PERIA_INTA241, + DTCE_PERIA_INTA242, + DTCE_PERIA_INTA243, + DTCE_PERIA_INTA244, + DTCE_PERIA_INTA245, + DTCE_PERIA_INTA246, + DTCE_PERIA_INTA247, + DTCE_PERIA_INTA248, + DTCE_PERIA_INTA249, + DTCE_PERIA_INTA250, + DTCE_PERIA_INTA251, + DTCE_PERIA_INTA252, + DTCE_PERIA_INTA253, + DTCE_PERIA_INTA254, + DTCE_PERIA_INTA255 +} enum_dtce_t; + +typedef enum enum_ier +{ + IER_BSC_BUSERR = 0x02, + IER_RAM_RAMERR = 0x02, + IER_FCU_FIFERR = 0x02, + IER_FCU_FRDYI = 0x02, + IER_ICU_SWINT2 = 0x03, + IER_ICU_SWINT = 0x03, + IER_CMT0_CMI0 = 0x03, + IER_CMT1_CMI1 = 0x03, + IER_CMTW0_CMWI0 = 0x03, + IER_CMTW1_CMWI1 = 0x03, + IER_USB0_D0FIFO0 = 0x04, + IER_USB0_D1FIFO0 = 0x04, + IER_RSPI0_SPRI0 = 0x04, + IER_RSPI0_SPTI0 = 0x04, + IER_RSPI1_SPRI1 = 0x05, + IER_RSPI1_SPTI1 = 0x05, + IER_QSPI_SPRI = 0x05, + IER_QSPI_SPTI = 0x05, + IER_SDHI_SBFAI = 0x05, + IER_MMCIF_MBFAI = 0x05, + IER_RIIC1_RXI1 = 0x06, + IER_RIIC1_TXI1 = 0x06, + IER_RIIC0_RXI0 = 0x06, + IER_RIIC0_TXI0 = 0x06, + IER_RIIC2_RXI2 = 0x06, + IER_RIIC2_TXI2 = 0x06, + IER_SCI0_RXI0 = 0x07, + IER_SCI0_TXI0 = 0x07, + IER_SCI1_RXI1 = 0x07, + IER_SCI1_TXI1 = 0x07, + IER_SCI2_RXI2 = 0x07, + IER_SCI2_TXI2 = 0x07, + IER_ICU_IRQ0 = 0x08, + IER_ICU_IRQ1 = 0x08, + IER_ICU_IRQ2 = 0x08, + IER_ICU_IRQ3 = 0x08, + IER_ICU_IRQ4 = 0x08, + IER_ICU_IRQ5 = 0x08, + IER_ICU_IRQ6 = 0x08, + IER_ICU_IRQ7 = 0x08, + IER_ICU_IRQ8 = 0x09, + IER_ICU_IRQ9 = 0x09, + IER_ICU_IRQ10 = 0x09, + IER_ICU_IRQ11 = 0x09, + IER_ICU_IRQ12 = 0x09, + IER_ICU_IRQ13 = 0x09, + IER_ICU_IRQ14 = 0x09, + IER_ICU_IRQ15 = 0x09, + IER_SCI3_RXI3 = 0x0a, + IER_SCI3_TXI3 = 0x0a, + IER_SCI4_RXI4 = 0x0a, + IER_SCI4_TXI4 = 0x0a, + IER_SCI5_RXI5 = 0x0a, + IER_SCI5_TXI5 = 0x0a, + IER_SCI6_RXI6 = 0x0a, + IER_SCI6_TXI6 = 0x0a, + IER_LVD1_LVD1 = 0x0b, + IER_LVD2_LVD2 = 0x0b, + IER_USB0_USBR0 = 0x0b, + IER_RTC_ALM = 0x0b, + IER_RTC_PRD = 0x0b, + IER_IWDT_IWUNI = 0x0b, + IER_WDT_WUNI = 0x0c, + IER_PDC_PCDFI = 0x0c, + IER_SCI7_RXI7 = 0x0c, + IER_SCI7_TXI7 = 0x0c, + IER_SCI8_RXI8 = 0x0c, + IER_SCI8_TXI8 = 0x0c, + IER_SCI9_RXI9 = 0x0c, + IER_SCI9_TXI9 = 0x0c, + IER_SCI10_RXI10 = 0x0d, + IER_SCI10_TXI10 = 0x0d, + IER_ICU_GROUPBE0 = 0x0d, + IER_ICU_GROUPBL2 = 0x0d, + IER_RSPI2_SPRI2 = 0x0d, + IER_RSPI2_SPTI2 = 0x0d, + IER_ICU_GROUPBL0 = 0x0d, + IER_ICU_GROUPBL1 = 0x0d, + IER_ICU_GROUPAL0 = 0x0e, + IER_ICU_GROUPAL1 = 0x0e, + IER_SCI11_RXI11 = 0x0e, + IER_SCI11_TXI11 = 0x0e, + IER_SCI12_RXI12 = 0x0e, + IER_SCI12_TXI12 = 0x0e, + IER_DMAC_DMAC0I = 0x0f, + IER_DMAC_DMAC1I = 0x0f, + IER_DMAC_DMAC2I = 0x0f, + IER_DMAC_DMAC3I = 0x0f, + IER_DMAC_DMAC74I = 0x0f, + IER_OST_OSTDI = 0x0f, + IER_EXDMAC_EXDMAC0I = 0x0f, + IER_EXDMAC_EXDMAC1I = 0x0f, + IER_PERIB_INTB128 = 0x10, + IER_PERIB_INTB129 = 0x10, + IER_PERIB_INTB130 = 0x10, + IER_PERIB_INTB131 = 0x10, + IER_PERIB_INTB132 = 0x10, + IER_PERIB_INTB133 = 0x10, + IER_PERIB_INTB134 = 0x10, + IER_PERIB_INTB135 = 0x10, + IER_PERIB_INTB136 = 0x11, + IER_PERIB_INTB137 = 0x11, + IER_PERIB_INTB138 = 0x11, + IER_PERIB_INTB139 = 0x11, + IER_PERIB_INTB140 = 0x11, + IER_PERIB_INTB141 = 0x11, + IER_PERIB_INTB142 = 0x11, + IER_PERIB_INTB143 = 0x11, + IER_PERIB_INTB144 = 0x12, + IER_PERIB_INTB145 = 0x12, + IER_PERIB_INTB146 = 0x12, + IER_PERIB_INTB147 = 0x12, + IER_PERIB_INTB148 = 0x12, + IER_PERIB_INTB149 = 0x12, + IER_PERIB_INTB150 = 0x12, + IER_PERIB_INTB151 = 0x12, + IER_PERIB_INTB152 = 0x13, + IER_PERIB_INTB153 = 0x13, + IER_PERIB_INTB154 = 0x13, + IER_PERIB_INTB155 = 0x13, + IER_PERIB_INTB156 = 0x13, + IER_PERIB_INTB157 = 0x13, + IER_PERIB_INTB158 = 0x13, + IER_PERIB_INTB159 = 0x13, + IER_PERIB_INTB160 = 0x14, + IER_PERIB_INTB161 = 0x14, + IER_PERIB_INTB162 = 0x14, + IER_PERIB_INTB163 = 0x14, + IER_PERIB_INTB164 = 0x14, + IER_PERIB_INTB165 = 0x14, + IER_PERIB_INTB166 = 0x14, + IER_PERIB_INTB167 = 0x14, + IER_PERIB_INTB168 = 0x15, + IER_PERIB_INTB169 = 0x15, + IER_PERIB_INTB170 = 0x15, + IER_PERIB_INTB171 = 0x15, + IER_PERIB_INTB172 = 0x15, + IER_PERIB_INTB173 = 0x15, + IER_PERIB_INTB174 = 0x15, + IER_PERIB_INTB175 = 0x15, + IER_PERIB_INTB176 = 0x16, + IER_PERIB_INTB177 = 0x16, + IER_PERIB_INTB178 = 0x16, + IER_PERIB_INTB179 = 0x16, + IER_PERIB_INTB180 = 0x16, + IER_PERIB_INTB181 = 0x16, + IER_PERIB_INTB182 = 0x16, + IER_PERIB_INTB183 = 0x16, + IER_PERIB_INTB184 = 0x17, + IER_PERIB_INTB185 = 0x17, + IER_PERIB_INTB186 = 0x17, + IER_PERIB_INTB187 = 0x17, + IER_PERIB_INTB188 = 0x17, + IER_PERIB_INTB189 = 0x17, + IER_PERIB_INTB190 = 0x17, + IER_PERIB_INTB191 = 0x17, + IER_PERIB_INTB192 = 0x18, + IER_PERIB_INTB193 = 0x18, + IER_PERIB_INTB194 = 0x18, + IER_PERIB_INTB195 = 0x18, + IER_PERIB_INTB196 = 0x18, + IER_PERIB_INTB197 = 0x18, + IER_PERIB_INTB198 = 0x18, + IER_PERIB_INTB199 = 0x18, + IER_PERIB_INTB200 = 0x19, + IER_PERIB_INTB201 = 0x19, + IER_PERIB_INTB202 = 0x19, + IER_PERIB_INTB203 = 0x19, + IER_PERIB_INTB204 = 0x19, + IER_PERIB_INTB205 = 0x19, + IER_PERIB_INTB206 = 0x19, + IER_PERIB_INTB207 = 0x19, + IER_PERIA_INTA208 = 0x1a, + IER_PERIA_INTA209 = 0x1a, + IER_PERIA_INTA210 = 0x1a, + IER_PERIA_INTA211 = 0x1a, + IER_PERIA_INTA212 = 0x1a, + IER_PERIA_INTA213 = 0x1a, + IER_PERIA_INTA214 = 0x1a, + IER_PERIA_INTA215 = 0x1a, + IER_PERIA_INTA216 = 0x1b, + IER_PERIA_INTA217 = 0x1b, + IER_PERIA_INTA218 = 0x1b, + IER_PERIA_INTA219 = 0x1b, + IER_PERIA_INTA220 = 0x1b, + IER_PERIA_INTA221 = 0x1b, + IER_PERIA_INTA222 = 0x1b, + IER_PERIA_INTA223 = 0x1b, + IER_PERIA_INTA224 = 0x1c, + IER_PERIA_INTA225 = 0x1c, + IER_PERIA_INTA226 = 0x1c, + IER_PERIA_INTA227 = 0x1c, + IER_PERIA_INTA228 = 0x1c, + IER_PERIA_INTA229 = 0x1c, + IER_PERIA_INTA230 = 0x1c, + IER_PERIA_INTA231 = 0x1c, + IER_PERIA_INTA232 = 0x1d, + IER_PERIA_INTA233 = 0x1d, + IER_PERIA_INTA234 = 0x1d, + IER_PERIA_INTA235 = 0x1d, + IER_PERIA_INTA236 = 0x1d, + IER_PERIA_INTA237 = 0x1d, + IER_PERIA_INTA238 = 0x1d, + IER_PERIA_INTA239 = 0x1d, + IER_PERIA_INTA240 = 0x1e, + IER_PERIA_INTA241 = 0x1e, + IER_PERIA_INTA242 = 0x1e, + IER_PERIA_INTA243 = 0x1e, + IER_PERIA_INTA244 = 0x1e, + IER_PERIA_INTA245 = 0x1e, + IER_PERIA_INTA246 = 0x1e, + IER_PERIA_INTA247 = 0x1e, + IER_PERIA_INTA248 = 0x1f, + IER_PERIA_INTA249 = 0x1f, + IER_PERIA_INTA250 = 0x1f, + IER_PERIA_INTA251 = 0x1f, + IER_PERIA_INTA252 = 0x1f, + IER_PERIA_INTA253 = 0x1f, + IER_PERIA_INTA254 = 0x1f, + IER_PERIA_INTA255 = 0x1f +} enum_ier_t; + +typedef enum enum_ipr +{ + IPR_BSC_BUSERR = 0, + IPR_RAM_RAMERR = 0, + IPR_FCU_FIFERR = 1, + IPR_FCU_FRDYI = 2, + IPR_ICU_SWINT2 = 3, + IPR_ICU_SWINT = 3, + IPR_CMT0_CMI0 = 4, + IPR_CMT1_CMI1 = 5, + IPR_CMTW0_CMWI0 = 6, + IPR_CMTW1_CMWI1 = 7, + IPR_USB0_D0FIFO0 = 34, + IPR_USB0_D1FIFO0 = 35, + IPR_RSPI0_SPRI0 = 38, + IPR_RSPI0_SPTI0 = 39, + IPR_RSPI1_SPRI1 = 40, + IPR_RSPI1_SPTI1 = 41, + IPR_QSPI_SPRI = 42, + IPR_QSPI_SPTI = 43, + IPR_SDHI_SBFAI = 44, + IPR_MMCIF_MBFAI = 45, + IPR_RIIC1_RXI1 = 50, + IPR_RIIC1_TXI1 = 51, + IPR_RIIC0_RXI0 = 52, + IPR_RIIC0_TXI0 = 53, + IPR_RIIC2_RXI2 = 54, + IPR_RIIC2_TXI2 = 55, + IPR_SCI0_RXI0 = 58, + IPR_SCI0_TXI0 = 59, + IPR_SCI1_RXI1 = 60, + IPR_SCI1_TXI1 = 61, + IPR_SCI2_RXI2 = 62, + IPR_SCI2_TXI2 = 63, + IPR_ICU_IRQ0 = 64, + IPR_ICU_IRQ1 = 65, + IPR_ICU_IRQ2 = 66, + IPR_ICU_IRQ3 = 67, + IPR_ICU_IRQ4 = 68, + IPR_ICU_IRQ5 = 69, + IPR_ICU_IRQ6 = 70, + IPR_ICU_IRQ7 = 71, + IPR_ICU_IRQ8 = 72, + IPR_ICU_IRQ9 = 73, + IPR_ICU_IRQ10 = 74, + IPR_ICU_IRQ11 = 75, + IPR_ICU_IRQ12 = 76, + IPR_ICU_IRQ13 = 77, + IPR_ICU_IRQ14 = 78, + IPR_ICU_IRQ15 = 79, + IPR_SCI3_RXI3 = 80, + IPR_SCI3_TXI3 = 81, + IPR_SCI4_RXI4 = 82, + IPR_SCI4_TXI4 = 83, + IPR_SCI5_RXI5 = 84, + IPR_SCI5_TXI5 = 85, + IPR_SCI6_RXI6 = 86, + IPR_SCI6_TXI6 = 87, + IPR_LVD1_LVD1 = 88, + IPR_LVD2_LVD2 = 89, + IPR_USB0_USBR0 = 90, + IPR_RTC_ALM = 92, + IPR_RTC_PRD = 93, + IPR_IWDT_IWUNI = 95, + IPR_WDT_WUNI = 96, + IPR_PDC_PCDFI = 97, + IPR_SCI7_RXI7 = 98, + IPR_SCI7_TXI7 = 99, + IPR_SCI8_RXI8 = 100, + IPR_SCI8_TXI8 = 101, + IPR_SCI9_RXI9 = 102, + IPR_SCI9_TXI9 = 103, + IPR_SCI10_RXI10 = 104, + IPR_SCI10_TXI10 = 105, + IPR_ICU_GROUPBE0 = 106, + IPR_ICU_GROUPBL2 = 107, + IPR_RSPI2_SPRI2 = 108, + IPR_RSPI2_SPTI2 = 109, + IPR_ICU_GROUPBL0 = 110, + IPR_ICU_GROUPBL1 = 111, + IPR_ICU_GROUPAL0 = 112, + IPR_ICU_GROUPAL1 = 113, + IPR_SCI11_RXI11 = 114, + IPR_SCI11_TXI11 = 115, + IPR_SCI12_RXI12 = 116, + IPR_SCI12_TXI12 = 117, + IPR_DMAC_DMAC0I = 120, + IPR_DMAC_DMAC1I = 121, + IPR_DMAC_DMAC2I = 122, + IPR_DMAC_DMAC3I = 123, + IPR_DMAC_DMAC74I = 124, + IPR_OST_OSTDI = 125, + IPR_EXDMAC_EXDMAC0I = 126, + IPR_EXDMAC_EXDMAC1I = 127, + IPR_PERIB_INTB128 = 128, + IPR_PERIB_INTB129 = 129, + IPR_PERIB_INTB130 = 130, + IPR_PERIB_INTB131 = 131, + IPR_PERIB_INTB132 = 132, + IPR_PERIB_INTB133 = 133, + IPR_PERIB_INTB134 = 134, + IPR_PERIB_INTB135 = 135, + IPR_PERIB_INTB136 = 136, + IPR_PERIB_INTB137 = 137, + IPR_PERIB_INTB138 = 138, + IPR_PERIB_INTB139 = 139, + IPR_PERIB_INTB140 = 140, + IPR_PERIB_INTB141 = 141, + IPR_PERIB_INTB142 = 142, + IPR_PERIB_INTB143 = 143, + IPR_PERIB_INTB144 = 144, + IPR_PERIB_INTB145 = 145, + IPR_PERIB_INTB146 = 146, + IPR_PERIB_INTB147 = 147, + IPR_PERIB_INTB148 = 148, + IPR_PERIB_INTB149 = 149, + IPR_PERIB_INTB150 = 150, + IPR_PERIB_INTB151 = 151, + IPR_PERIB_INTB152 = 152, + IPR_PERIB_INTB153 = 153, + IPR_PERIB_INTB154 = 154, + IPR_PERIB_INTB155 = 155, + IPR_PERIB_INTB156 = 156, + IPR_PERIB_INTB157 = 157, + IPR_PERIB_INTB158 = 158, + IPR_PERIB_INTB159 = 159, + IPR_PERIB_INTB160 = 160, + IPR_PERIB_INTB161 = 161, + IPR_PERIB_INTB162 = 162, + IPR_PERIB_INTB163 = 163, + IPR_PERIB_INTB164 = 164, + IPR_PERIB_INTB165 = 165, + IPR_PERIB_INTB166 = 166, + IPR_PERIB_INTB167 = 167, + IPR_PERIB_INTB168 = 168, + IPR_PERIB_INTB169 = 169, + IPR_PERIB_INTB170 = 170, + IPR_PERIB_INTB171 = 171, + IPR_PERIB_INTB172 = 172, + IPR_PERIB_INTB173 = 173, + IPR_PERIB_INTB174 = 174, + IPR_PERIB_INTB175 = 175, + IPR_PERIB_INTB176 = 176, + IPR_PERIB_INTB177 = 177, + IPR_PERIB_INTB178 = 178, + IPR_PERIB_INTB179 = 179, + IPR_PERIB_INTB180 = 180, + IPR_PERIB_INTB181 = 181, + IPR_PERIB_INTB182 = 182, + IPR_PERIB_INTB183 = 183, + IPR_PERIB_INTB184 = 184, + IPR_PERIB_INTB185 = 185, + IPR_PERIB_INTB186 = 186, + IPR_PERIB_INTB187 = 187, + IPR_PERIB_INTB188 = 188, + IPR_PERIB_INTB189 = 189, + IPR_PERIB_INTB190 = 190, + IPR_PERIB_INTB191 = 191, + IPR_PERIB_INTB192 = 192, + IPR_PERIB_INTB193 = 193, + IPR_PERIB_INTB194 = 194, + IPR_PERIB_INTB195 = 195, + IPR_PERIB_INTB196 = 196, + IPR_PERIB_INTB197 = 197, + IPR_PERIB_INTB198 = 198, + IPR_PERIB_INTB199 = 199, + IPR_PERIB_INTB200 = 200, + IPR_PERIB_INTB201 = 201, + IPR_PERIB_INTB202 = 202, + IPR_PERIB_INTB203 = 203, + IPR_PERIB_INTB204 = 204, + IPR_PERIB_INTB205 = 205, + IPR_PERIB_INTB206 = 206, + IPR_PERIB_INTB207 = 207, + IPR_PERIA_INTA208 = 208, + IPR_PERIA_INTA209 = 209, + IPR_PERIA_INTA210 = 210, + IPR_PERIA_INTA211 = 211, + IPR_PERIA_INTA212 = 212, + IPR_PERIA_INTA213 = 213, + IPR_PERIA_INTA214 = 214, + IPR_PERIA_INTA215 = 215, + IPR_PERIA_INTA216 = 216, + IPR_PERIA_INTA217 = 217, + IPR_PERIA_INTA218 = 218, + IPR_PERIA_INTA219 = 219, + IPR_PERIA_INTA220 = 220, + IPR_PERIA_INTA221 = 221, + IPR_PERIA_INTA222 = 222, + IPR_PERIA_INTA223 = 223, + IPR_PERIA_INTA224 = 224, + IPR_PERIA_INTA225 = 225, + IPR_PERIA_INTA226 = 226, + IPR_PERIA_INTA227 = 227, + IPR_PERIA_INTA228 = 228, + IPR_PERIA_INTA229 = 229, + IPR_PERIA_INTA230 = 230, + IPR_PERIA_INTA231 = 231, + IPR_PERIA_INTA232 = 232, + IPR_PERIA_INTA233 = 233, + IPR_PERIA_INTA234 = 234, + IPR_PERIA_INTA235 = 235, + IPR_PERIA_INTA236 = 236, + IPR_PERIA_INTA237 = 237, + IPR_PERIA_INTA238 = 238, + IPR_PERIA_INTA239 = 239, + IPR_PERIA_INTA240 = 240, + IPR_PERIA_INTA241 = 241, + IPR_PERIA_INTA242 = 242, + IPR_PERIA_INTA243 = 243, + IPR_PERIA_INTA244 = 244, + IPR_PERIA_INTA245 = 245, + IPR_PERIA_INTA246 = 246, + IPR_PERIA_INTA247 = 247, + IPR_PERIA_INTA248 = 248, + IPR_PERIA_INTA249 = 249, + IPR_PERIA_INTA250 = 250, + IPR_PERIA_INTA251 = 251, + IPR_PERIA_INTA252 = 252, + IPR_PERIA_INTA253 = 253, + IPR_PERIA_INTA254 = 254, + IPR_PERIA_INTA255 = 255, + IPR_ICU_SWI = 3, + IPR_CMT0_ = 4, + IPR_CMT1_ = 5, + IPR_CMTW0_ = 6, + IPR_CMTW1_ = 7, + IPR_SDHI_ = 44, + IPR_MMCIF_ = 45, + IPR_LVD1_ = 88, + IPR_LVD2_ = 89, + IPR_IWDT_ = 95, + IPR_WDT_ = 96, + IPR_PDC_ = 97, + IPR_OST_ = 125 +} enum_ipr_t; + +#pragma pack(4) + +struct st_bsc_berclr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char STSCLR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char STSCLR : 1; +#endif +}; + +union un_berclr +{ + unsigned char BYTE; + struct st_bsc_berclr_bit BIT; +}; + +struct st_bsc_beren_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IGAEN : 1; + unsigned char TOEN : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char TOEN : 1; + unsigned char IGAEN : 1; +#endif +}; + +union un_beren +{ + unsigned char BYTE; + struct st_bsc_beren_bit BIT; +}; + +struct st_bsc_bersr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IA : 1; + unsigned char TO : 1; + unsigned char : 2; + unsigned char MST : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MST : 3; + unsigned char : 2; + unsigned char TO : 1; + unsigned char IA : 1; +#endif +}; + +union un_bersr1 +{ + unsigned char BYTE; + struct st_bsc_bersr1_bit BIT; +}; + +struct st_bsc_bersr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 3; + unsigned short ADDR : 13; +#else + unsigned short ADDR : 13; + unsigned short : 3; +#endif +}; + +union un_bersr2 +{ + unsigned short WORD; + struct st_bsc_bersr2_bit BIT; +}; + +struct st_bsc_buspri_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short BPRA : 2; + unsigned short BPRO : 2; + unsigned short BPIB : 2; + unsigned short BPGB : 2; + unsigned short BPHB : 2; + unsigned short BPFB : 2; + unsigned short BPEB : 2; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short BPEB : 2; + unsigned short BPFB : 2; + unsigned short BPHB : 2; + unsigned short BPGB : 2; + unsigned short BPIB : 2; + unsigned short BPRO : 2; + unsigned short BPRA : 2; +#endif +}; + +union un_buspri +{ + unsigned short WORD; + struct st_bsc_buspri_bit BIT; +}; + +struct st_bsc_cs0mod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif +}; + +union un_cs0mod +{ + unsigned short WORD; + struct st_bsc_cs0mod_bit BIT; +}; + +struct st_bsc_cs0wcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif +}; + +union un_cs0wcr1 +{ + unsigned long LONG; + struct st_bsc_cs0wcr1_bit BIT; +}; + +struct st_bsc_cs1mod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif +}; + +union un_cs1mod +{ + unsigned short WORD; + struct st_bsc_cs1mod_bit BIT; +}; + +struct st_bsc_cs1wcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif +}; + +union un_cs1wcr1 +{ + unsigned long LONG; + struct st_bsc_cs1wcr1_bit BIT; +}; + +struct st_bsc_cs1wcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif +}; + +union un_cs1wcr2 +{ + unsigned long LONG; + struct st_bsc_cs1wcr2_bit BIT; +}; + +struct st_bsc_cs2mod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif +}; + +union un_cs2mod +{ + unsigned short WORD; + struct st_bsc_cs2mod_bit BIT; +}; + +struct st_bsc_cs2wcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif +}; + +union un_cs2wcr1 +{ + unsigned long LONG; + struct st_bsc_cs2wcr1_bit BIT; +}; + +struct st_bsc_cs2wcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif +}; + +union un_cs2wcr2 +{ + unsigned long LONG; + struct st_bsc_cs2wcr2_bit BIT; +}; + +struct st_bsc_cs3mod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif +}; + +union un_cs3mod +{ + unsigned short WORD; + struct st_bsc_cs3mod_bit BIT; +}; + +struct st_bsc_cs3wcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif +}; + +union un_cs3wcr1 +{ + unsigned long LONG; + struct st_bsc_cs3wcr1_bit BIT; +}; + +struct st_bsc_cs3wcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif +}; + +union un_cs3wcr2 +{ + unsigned long LONG; + struct st_bsc_cs3wcr2_bit BIT; +}; + +struct st_bsc_cs4mod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif +}; + +union un_cs4mod +{ + unsigned short WORD; + struct st_bsc_cs4mod_bit BIT; +}; + +struct st_bsc_cs4wcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif +}; + +union un_cs4wcr1 +{ + unsigned long LONG; + struct st_bsc_cs4wcr1_bit BIT; +}; + +struct st_bsc_cs4wcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif +}; + +union un_cs4wcr2 +{ + unsigned long LONG; + struct st_bsc_cs4wcr2_bit BIT; +}; + +struct st_bsc_cs5mod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif +}; + +union un_cs5mod +{ + unsigned short WORD; + struct st_bsc_cs5mod_bit BIT; +}; + +struct st_bsc_cs5wcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif +}; + +union un_cs5wcr1 +{ + unsigned long LONG; + struct st_bsc_cs5wcr1_bit BIT; +}; + +struct st_bsc_cs5wcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif +}; + +union un_cs5wcr2 +{ + unsigned long LONG; + struct st_bsc_cs5wcr2_bit BIT; +}; + +struct st_bsc_cs6mod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif +}; + +union un_cs6mod +{ + unsigned short WORD; + struct st_bsc_cs6mod_bit BIT; +}; + +struct st_bsc_cs6wcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif +}; + +union un_cs6wcr1 +{ + unsigned long LONG; + struct st_bsc_cs6wcr1_bit BIT; +}; + +struct st_bsc_cs6wcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif +}; + +union un_cs6wcr2 +{ + unsigned long LONG; + struct st_bsc_cs6wcr2_bit BIT; +}; + +struct st_bsc_cs7mod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short WRMOD : 1; + unsigned short : 2; + unsigned short EWENB : 1; + unsigned short : 4; + unsigned short PRENB : 1; + unsigned short PWENB : 1; + unsigned short : 5; + unsigned short PRMOD : 1; +#else + unsigned short PRMOD : 1; + unsigned short : 5; + unsigned short PWENB : 1; + unsigned short PRENB : 1; + unsigned short : 4; + unsigned short EWENB : 1; + unsigned short : 2; + unsigned short WRMOD : 1; +#endif +}; + +union un_cs7mod +{ + unsigned short WORD; + struct st_bsc_cs7mod_bit BIT; +}; + +struct st_bsc_cs7wcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSPWWAIT : 3; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSWWAIT : 5; + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; +#else + unsigned long : 3; + unsigned long CSRWAIT : 5; + unsigned long : 3; + unsigned long CSWWAIT : 5; + unsigned long : 5; + unsigned long CSPRWAIT : 3; + unsigned long : 5; + unsigned long CSPWWAIT : 3; +#endif +}; + +union un_cs7wcr1 +{ + unsigned long LONG; + struct st_bsc_cs7wcr1_bit BIT; +}; + +struct st_bsc_cs7wcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CSROFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long AWAIT : 2; + unsigned long : 2; + unsigned long RDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; +#else + unsigned long : 1; + unsigned long CSON : 3; + unsigned long : 1; + unsigned long WDON : 3; + unsigned long : 1; + unsigned long WRON : 3; + unsigned long : 1; + unsigned long RDON : 3; + unsigned long : 2; + unsigned long AWAIT : 2; + unsigned long : 1; + unsigned long WDOFF : 3; + unsigned long : 1; + unsigned long CSWOFF : 3; + unsigned long : 1; + unsigned long CSROFF : 3; +#endif +}; + +union un_cs7wcr2 +{ + unsigned long LONG; + struct st_bsc_cs7wcr2_bit BIT; +}; + +struct st_bsc_cs0cr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif +}; + +union un_cs0cr +{ + unsigned short WORD; + struct st_bsc_cs0cr_bit BIT; +}; + +struct st_bsc_cs0rec_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif +}; + +union un_cs0rec +{ + unsigned short WORD; + struct st_bsc_cs0rec_bit BIT; +}; + +struct st_bsc_cs1cr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif +}; + +union un_cs1cr +{ + unsigned short WORD; + struct st_bsc_cs1cr_bit BIT; +}; + +struct st_bsc_cs1rec_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif +}; + +union un_cs1rec +{ + unsigned short WORD; + struct st_bsc_cs1rec_bit BIT; +}; + +struct st_bsc_cs2cr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif +}; + +union un_cs2cr +{ + unsigned short WORD; + struct st_bsc_cs2cr_bit BIT; +}; + +struct st_bsc_cs2rec_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif +}; + +union un_cs2rec +{ + unsigned short WORD; + struct st_bsc_cs2rec_bit BIT; +}; + +struct st_bsc_cs3cr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif +}; + +union un_cs3cr +{ + unsigned short WORD; + struct st_bsc_cs3cr_bit BIT; +}; + +struct st_bsc_cs3rec_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif +}; + +union un_cs3rec +{ + unsigned short WORD; + struct st_bsc_cs3rec_bit BIT; +}; + +struct st_bsc_cs4cr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif +}; + +union un_cs4cr +{ + unsigned short WORD; + struct st_bsc_cs4cr_bit BIT; +}; + +struct st_bsc_cs4rec_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif +}; + +union un_cs4rec +{ + unsigned short WORD; + struct st_bsc_cs4rec_bit BIT; +}; + +struct st_bsc_cs5cr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif +}; + +union un_cs5cr +{ + unsigned short WORD; + struct st_bsc_cs5cr_bit BIT; +}; + +struct st_bsc_cs5rec_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif +}; + +union un_cs5rec +{ + unsigned short WORD; + struct st_bsc_cs5rec_bit BIT; +}; + +struct st_bsc_cs6cr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif +}; + +union un_cs6cr +{ + unsigned short WORD; + struct st_bsc_cs6cr_bit BIT; +}; + +struct st_bsc_cs6rec_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif +}; + +union un_cs6rec +{ + unsigned short WORD; + struct st_bsc_cs6rec_bit BIT; +}; + +struct st_bsc_cs7cr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short EXENB : 1; + unsigned short : 3; + unsigned short BSIZE : 2; + unsigned short : 2; + unsigned short EMODE : 1; + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short MPXEN : 1; + unsigned short : 3; + unsigned short EMODE : 1; + unsigned short : 2; + unsigned short BSIZE : 2; + unsigned short : 3; + unsigned short EXENB : 1; +#endif +}; + +union un_cs7cr +{ + unsigned short WORD; + struct st_bsc_cs7cr_bit BIT; +}; + +struct st_bsc_cs7rec_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RRCV : 4; + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; +#else + unsigned short : 4; + unsigned short WRCV : 4; + unsigned short : 4; + unsigned short RRCV : 4; +#endif +}; + +union un_cs7rec +{ + unsigned short WORD; + struct st_bsc_cs7rec_bit BIT; +}; + +struct st_bsc_csrecen_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RCVEN0 : 1; + unsigned short RCVEN1 : 1; + unsigned short RCVEN2 : 1; + unsigned short RCVEN3 : 1; + unsigned short RCVEN4 : 1; + unsigned short RCVEN5 : 1; + unsigned short RCVEN6 : 1; + unsigned short RCVEN7 : 1; + unsigned short RCVENM0 : 1; + unsigned short RCVENM1 : 1; + unsigned short RCVENM2 : 1; + unsigned short RCVENM3 : 1; + unsigned short RCVENM4 : 1; + unsigned short RCVENM5 : 1; + unsigned short RCVENM6 : 1; + unsigned short RCVENM7 : 1; +#else + unsigned short RCVENM7 : 1; + unsigned short RCVENM6 : 1; + unsigned short RCVENM5 : 1; + unsigned short RCVENM4 : 1; + unsigned short RCVENM3 : 1; + unsigned short RCVENM2 : 1; + unsigned short RCVENM1 : 1; + unsigned short RCVENM0 : 1; + unsigned short RCVEN7 : 1; + unsigned short RCVEN6 : 1; + unsigned short RCVEN5 : 1; + unsigned short RCVEN4 : 1; + unsigned short RCVEN3 : 1; + unsigned short RCVEN2 : 1; + unsigned short RCVEN1 : 1; + unsigned short RCVEN0 : 1; +#endif +}; + +union un_csrecen +{ + unsigned short WORD; + struct st_bsc_csrecen_bit BIT; +}; + +struct st_bsc_sdccr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EXENB : 1; + unsigned char : 3; + unsigned char BSIZE : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char BSIZE : 2; + unsigned char : 3; + unsigned char EXENB : 1; +#endif +}; + +union un_sdccr +{ + unsigned char BYTE; + struct st_bsc_sdccr_bit BIT; +}; + +struct st_bsc_sdcmod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char EMODE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char EMODE : 1; +#endif +}; + +union un_sdcmod +{ + unsigned char BYTE; + struct st_bsc_sdcmod_bit BIT; +}; + +struct st_bsc_sdamod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BE : 1; +#endif +}; + +union un_sdamod +{ + unsigned char BYTE; + struct st_bsc_sdamod_bit BIT; +}; + +struct st_bsc_sdself_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SFEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SFEN : 1; +#endif +}; + +union un_sdself +{ + unsigned char BYTE; + struct st_bsc_sdself_bit BIT; +}; + +struct st_bsc_sdrfcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFC : 12; + unsigned short REFW : 4; +#else + unsigned short REFW : 4; + unsigned short RFC : 12; +#endif +}; + +union un_sdrfcr +{ + unsigned short WORD; + struct st_bsc_sdrfcr_bit BIT; +}; + +struct st_bsc_sdrfen_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RFEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RFEN : 1; +#endif +}; + +union un_sdrfen +{ + unsigned char BYTE; + struct st_bsc_sdrfen_bit BIT; +}; + +struct st_bsc_sdicr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char INIRQ : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char INIRQ : 1; +#endif +}; + +union un_sdicr +{ + unsigned char BYTE; + struct st_bsc_sdicr_bit BIT; +}; + +struct st_bsc_sdir_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ARFI : 4; + unsigned short ARFC : 4; + unsigned short PRC : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short PRC : 3; + unsigned short ARFC : 4; + unsigned short ARFI : 4; +#endif +}; + +union un_sdir +{ + unsigned short WORD; + struct st_bsc_sdir_bit BIT; +}; + +struct st_bsc_sdar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MXC : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char MXC : 2; +#endif +}; + +union un_sdar +{ + unsigned char BYTE; + struct st_bsc_sdar_bit BIT; +}; + +struct st_bsc_sdtr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CL : 3; + unsigned long : 5; + unsigned long WR : 1; + unsigned long RP : 3; + unsigned long RCD : 2; + unsigned long : 2; + unsigned long RAS : 3; + unsigned long : 13; +#else + unsigned long : 13; + unsigned long RAS : 3; + unsigned long : 2; + unsigned long RCD : 2; + unsigned long RP : 3; + unsigned long WR : 1; + unsigned long : 5; + unsigned long CL : 3; +#endif +}; + +union un_sdtr +{ + unsigned long LONG; + struct st_bsc_sdtr_bit BIT; +}; + +struct st_bsc_sdmod_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MR : 15; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short MR : 15; +#endif +}; + +union un_sdmod +{ + unsigned short WORD; + struct st_bsc_sdmod_bit BIT; +}; + +struct st_bsc_sdsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MRSST : 1; + unsigned char : 2; + unsigned char INIST : 1; + unsigned char SRFST : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SRFST : 1; + unsigned char INIST : 1; + unsigned char : 2; + unsigned char MRSST : 1; +#endif +}; + +union un_sdsr +{ + unsigned char BYTE; + struct st_bsc_sdsr_bit BIT; +}; + +struct st_bsc_ebmapcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PR1SEL : 3; + unsigned long : 1; + unsigned long PR2SEL : 3; + unsigned long : 1; + unsigned long PR3SEL : 3; + unsigned long : 1; + unsigned long PR4SEL : 3; + unsigned long : 1; + unsigned long PR5SEL : 3; + unsigned long : 10; + unsigned long RPSTOP : 1; + unsigned long : 1; + unsigned long PRERR : 1; +#else + unsigned long PRERR : 1; + unsigned long : 1; + unsigned long RPSTOP : 1; + unsigned long : 10; + unsigned long PR5SEL : 3; + unsigned long : 1; + unsigned long PR4SEL : 3; + unsigned long : 1; + unsigned long PR3SEL : 3; + unsigned long : 1; + unsigned long PR2SEL : 3; + unsigned long : 1; + unsigned long PR1SEL : 3; +#endif +}; + +union un_ebmapcr +{ + unsigned long LONG; + struct st_bsc_ebmapcr_bit BIT; +}; + +struct st_cac_cacr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CFME : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CFME : 1; +#endif +}; + +union un_cacr0 +{ + unsigned char BYTE; + struct st_cac_cacr0_bit BIT; +}; + +struct st_cac_cacr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CACREFE : 1; + unsigned char FMCS : 3; + unsigned char TCSS : 2; + unsigned char EDGES : 2; +#else + unsigned char EDGES : 2; + unsigned char TCSS : 2; + unsigned char FMCS : 3; + unsigned char CACREFE : 1; +#endif +}; + +union un_cacr1 +{ + unsigned char BYTE; + struct st_cac_cacr1_bit BIT; +}; + +struct st_cac_cacr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RPS : 1; + unsigned char RSCS : 3; + unsigned char RCDS : 2; + unsigned char DFS : 2; +#else + unsigned char DFS : 2; + unsigned char RCDS : 2; + unsigned char RSCS : 3; + unsigned char RPS : 1; +#endif +}; + +union un_cacr2 +{ + unsigned char BYTE; + struct st_cac_cacr2_bit BIT; +}; + +struct st_cac_caicr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FERRIE : 1; + unsigned char MENDIE : 1; + unsigned char OVFIE : 1; + unsigned char : 1; + unsigned char FERRFCL : 1; + unsigned char MENDFCL : 1; + unsigned char OVFFCL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char OVFFCL : 1; + unsigned char MENDFCL : 1; + unsigned char FERRFCL : 1; + unsigned char : 1; + unsigned char OVFIE : 1; + unsigned char MENDIE : 1; + unsigned char FERRIE : 1; +#endif +}; + +union un_caicr +{ + unsigned char BYTE; + struct st_cac_caicr_bit BIT; +}; + +struct st_cac_castr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FERRF : 1; + unsigned char MENDF : 1; + unsigned char OVFF : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char OVFF : 1; + unsigned char MENDF : 1; + unsigned char FERRF : 1; +#endif +}; + +union un_castr +{ + unsigned char BYTE; + struct st_cac_castr_bit BIT; +}; + +struct st_cmt_cmstr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR0 : 1; + unsigned short STR1 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short STR1 : 1; + unsigned short STR0 : 1; +#endif +}; + +union un_cmstr0 +{ + unsigned short WORD; + struct st_cmt_cmstr0_bit BIT; +}; + +struct st_cmt_cmstr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR2 : 1; + unsigned short STR3 : 1; + unsigned short : 14; +#else + unsigned short : 14; + unsigned short STR3 : 1; + unsigned short STR2 : 1; +#endif +}; + +union un_cmstr1 +{ + unsigned short WORD; + struct st_cmt_cmstr1_bit BIT; +}; + +struct st_cmt0_cmcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CKS : 2; + unsigned short : 4; + unsigned short CMIE : 1; + unsigned short : 9; +#else + unsigned short : 9; + unsigned short CMIE : 1; + unsigned short : 4; + unsigned short CKS : 2; +#endif +}; + +union un_cmcr +{ + unsigned short WORD; + struct st_cmt0_cmcr_bit BIT; +}; + +struct st_cmtw_cmwstr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short STR : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short STR : 1; +#endif +}; + +union un_cmtw_cmwstr +{ + unsigned short WORD; + struct st_cmtw_cmwstr_bit BIT; +}; + +struct st_cmtw_cmwcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CKS : 2; + unsigned short : 1; + unsigned short CMWIE : 1; + unsigned short IC0IE : 1; + unsigned short IC1IE : 1; + unsigned short OC0IE : 1; + unsigned short OC1IE : 1; + unsigned short : 1; + unsigned short CMS : 1; + unsigned short : 3; + unsigned short CCLR : 3; +#else + unsigned short CCLR : 3; + unsigned short : 3; + unsigned short CMS : 1; + unsigned short : 1; + unsigned short OC1IE : 1; + unsigned short OC0IE : 1; + unsigned short IC1IE : 1; + unsigned short IC0IE : 1; + unsigned short CMWIE : 1; + unsigned short : 1; + unsigned short CKS : 2; +#endif +}; + +union un_cmtw_cmwcr +{ + unsigned short WORD; + struct st_cmtw_cmwcr_bit BIT; +}; + +struct st_cmtw_cmwior_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short IC0 : 2; + unsigned short IC1 : 2; + unsigned short IC0E : 1; + unsigned short IC1E : 1; + unsigned short : 2; + unsigned short OC0 : 2; + unsigned short OC1 : 2; + unsigned short OC0E : 1; + unsigned short OC1E : 1; + unsigned short : 1; + unsigned short CMWE : 1; +#else + unsigned short CMWE : 1; + unsigned short : 1; + unsigned short OC1E : 1; + unsigned short OC0E : 1; + unsigned short OC1 : 2; + unsigned short OC0 : 2; + unsigned short : 2; + unsigned short IC1E : 1; + unsigned short IC0E : 1; + unsigned short IC1 : 2; + unsigned short IC0 : 2; +#endif +}; + +union un_cmtw_cmwior +{ + unsigned short WORD; + struct st_cmtw_cmwior_bit BIT; +}; + +struct st_icu_ier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IEN0 : 1; + unsigned char IEN1 : 1; + unsigned char IEN2 : 1; + unsigned char IEN3 : 1; + unsigned char IEN4 : 1; + unsigned char IEN5 : 1; + unsigned char IEN6 : 1; + unsigned char IEN7 : 1; +#else + unsigned char IEN7 : 1; + unsigned char IEN6 : 1; + unsigned char IEN5 : 1; + unsigned char IEN4 : 1; + unsigned char IEN3 : 1; + unsigned char IEN2 : 1; + unsigned char IEN1 : 1; + unsigned char IEN0 : 1; +#endif +}; + +union un_ier32 +{ + unsigned char BYTE; + struct st_icu_ier_bit BIT; +}; + +struct st_icu_irqcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char IRQMD : 2; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char IRQMD : 2; + unsigned char : 2; +#endif +}; + +union un_irqcr16 +{ + unsigned char BYTE; + struct st_icu_irqcr_bit BIT; +}; + +struct st_icu_swintr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWINT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SWINT : 1; +#endif +}; + +union un_swintr +{ + unsigned char BYTE; + struct st_icu_swintr_bit BIT; +}; + +struct st_icu_swint2r_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SWINT2 : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SWINT2 : 1; +#endif +}; + +union un_swint2r +{ + unsigned char BYTE; + struct st_icu_swint2r_bit BIT; +}; + +struct st_icu_grpbl0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif +}; + +union un_grpbl0 +{ + unsigned long LONG; + struct st_icu_grpbl0_bit BIT; +}; + +struct st_icu_genbl0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif +}; + +union un_genbl0 +{ + unsigned long LONG; + struct st_icu_genbl0_bit BIT; +}; + +struct st_mpc_pwpr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char PFSWE : 1; + unsigned char B0WI : 1; +#else + unsigned char B0WI : 1; + unsigned char PFSWE : 1; + unsigned char : 6; +#endif +}; + +struct st_icu_grpbl1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif +}; + +union un_grpbl1 +{ + unsigned long LONG; + struct st_icu_grpbl1_bit BIT; +}; + +struct st_icu_genbl1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif +}; + +union un_genbl1 +{ + unsigned long LONG; + struct st_icu_genbl1_bit BIT; +}; + +struct st_icu_grpal0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif +}; + +union un_grpal0 +{ + unsigned long LONG; + struct st_icu_grpal0_bit BIT; +}; + +struct st_icu_genal0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif +}; + +union un_genal0 +{ + unsigned long LONG; + struct st_icu_genal0_bit BIT; +}; + +struct st_icu_grpal1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif +}; + +union un_grpal1 +{ + unsigned long LONG; + struct st_icu_grpal1_bit BIT; +}; + +struct st_icu_genal1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif +}; + +union un_genal1 +{ + unsigned long LONG; + struct st_icu_genal1_bit BIT; +}; + +union un_pwpr +{ + unsigned char BYTE; + struct st_mpc_pwpr_bit BIT; +}; + +struct st_icu_ir256_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IR : 1; +#endif +}; + +union un_icu_ir256 +{ + unsigned char BYTE; + struct st_icu_ir256_bit BIT; +}; + +struct st_icu_dtcer256_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DTCE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DTCE : 1; +#endif +}; + +union un_icu_dtcer256 +{ + unsigned char BYTE; + struct st_icu_dtcer256_bit BIT; +}; + +struct st_icu_fir_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FVCT : 8; + unsigned short : 7; + unsigned short FIEN : 1; +#else + unsigned short FIEN : 1; + unsigned short : 7; + unsigned short FVCT : 8; +#endif +}; + +union un_icu_fir +{ + unsigned short WORD; + struct st_icu_fir_bit BIT; +}; + +struct st_icu_ipr256_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IPR : 4; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char IPR : 4; +#endif +}; + +union un_icu_ipr256 +{ + unsigned char BYTE; + struct st_icu_ipr256_bit BIT; +}; + +struct st_icu_irqflte0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FLTEN0 : 1; + unsigned char FLTEN1 : 1; + unsigned char FLTEN2 : 1; + unsigned char FLTEN3 : 1; + unsigned char FLTEN4 : 1; + unsigned char FLTEN5 : 1; + unsigned char FLTEN6 : 1; + unsigned char FLTEN7 : 1; +#else + unsigned char FLTEN7 : 1; + unsigned char FLTEN6 : 1; + unsigned char FLTEN5 : 1; + unsigned char FLTEN4 : 1; + unsigned char FLTEN3 : 1; + unsigned char FLTEN2 : 1; + unsigned char FLTEN1 : 1; + unsigned char FLTEN0 : 1; +#endif +}; + +union un_irqflte0 +{ + unsigned char BYTE; + struct st_icu_irqflte0_bit BIT; +}; + +struct st_icu_irqflte1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char FLTEN8 : 1; + unsigned char FLTEN9 : 1; + unsigned char FLTEN10 : 1; + unsigned char FLTEN11 : 1; + unsigned char FLTEN12 : 1; + unsigned char FLTEN13 : 1; + unsigned char FLTEN14 : 1; + unsigned char FLTEN15 : 1; +#else + unsigned char FLTEN15 : 1; + unsigned char FLTEN14 : 1; + unsigned char FLTEN13 : 1; + unsigned char FLTEN12 : 1; + unsigned char FLTEN11 : 1; + unsigned char FLTEN10 : 1; + unsigned char FLTEN9 : 1; + unsigned char FLTEN8 : 1; +#endif +}; + +union un_irqflte1 +{ + unsigned char BYTE; + struct st_icu_irqflte1_bit BIT; +}; + +struct st_icu_irqfltc0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FCLKSEL0 : 2; + unsigned short FCLKSEL1 : 2; + unsigned short FCLKSEL2 : 2; + unsigned short FCLKSEL3 : 2; + unsigned short FCLKSEL4 : 2; + unsigned short FCLKSEL5 : 2; + unsigned short FCLKSEL6 : 2; + unsigned short FCLKSEL7 : 2; +#else + unsigned short FCLKSEL7 : 2; + unsigned short FCLKSEL6 : 2; + unsigned short FCLKSEL5 : 2; + unsigned short FCLKSEL4 : 2; + unsigned short FCLKSEL3 : 2; + unsigned short FCLKSEL2 : 2; + unsigned short FCLKSEL1 : 2; + unsigned short FCLKSEL0 : 2; +#endif +}; + +union un_icu_irqfltc0 +{ + unsigned short WORD; + struct st_icu_irqfltc0_bit BIT; +}; + +struct st_icu_irqfltc1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FCLKSEL8 : 2; + unsigned short FCLKSEL9 : 2; + unsigned short FCLKSEL10 : 2; + unsigned short FCLKSEL11 : 2; + unsigned short FCLKSEL12 : 2; + unsigned short FCLKSEL13 : 2; + unsigned short FCLKSEL14 : 2; + unsigned short FCLKSEL15 : 2; +#else + unsigned short FCLKSEL15 : 2; + unsigned short FCLKSEL14 : 2; + unsigned short FCLKSEL13 : 2; + unsigned short FCLKSEL12 : 2; + unsigned short FCLKSEL11 : 2; + unsigned short FCLKSEL10 : 2; + unsigned short FCLKSEL9 : 2; + unsigned short FCLKSEL8 : 2; +#endif +}; + +union un_icu_irqfltc1 +{ + unsigned short WORD; + struct st_icu_irqfltc1_bit BIT; +}; + +struct st_icu_nmisr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMIST : 1; + unsigned char OSTST : 1; + unsigned char WDTST : 1; + unsigned char IWDTST : 1; + unsigned char LVD1ST : 1; + unsigned char LVD2ST : 1; + unsigned char RAMST : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char RAMST : 1; + unsigned char LVD2ST : 1; + unsigned char LVD1ST : 1; + unsigned char IWDTST : 1; + unsigned char WDTST : 1; + unsigned char OSTST : 1; + unsigned char NMIST : 1; +#endif +}; + +union un_icu_nmisr +{ + unsigned char BYTE; + struct st_icu_nmisr_bit BIT; +}; + +struct st_icu_nmier_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMIEN : 1; + unsigned char OSTEN : 1; + unsigned char WDTEN : 1; + unsigned char IWDTEN : 1; + unsigned char LVD1EN : 1; + unsigned char LVD2EN : 1; + unsigned char RAMEN : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char RAMEN : 1; + unsigned char LVD2EN : 1; + unsigned char LVD1EN : 1; + unsigned char IWDTEN : 1; + unsigned char WDTEN : 1; + unsigned char OSTEN : 1; + unsigned char NMIEN : 1; +#endif +}; + +union un_icu_nmier +{ + unsigned char BYTE; + struct st_icu_nmier_bit BIT; +}; + +struct st_icu_nmiclr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NMICLR : 1; + unsigned char OSTCLR : 1; + unsigned char WDTCLR : 1; + unsigned char IWDTCLR : 1; + unsigned char LVD1CLR : 1; + unsigned char LVD2CLR : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char LVD2CLR : 1; + unsigned char LVD1CLR : 1; + unsigned char IWDTCLR : 1; + unsigned char WDTCLR : 1; + unsigned char OSTCLR : 1; + unsigned char NMICLR : 1; +#endif +}; + +union un_icu_nmiclr +{ + unsigned char BYTE; + struct st_icu_nmiclr_bit BIT; +}; + +struct st_icu_nmicr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 3; + unsigned char NMIMD : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char NMIMD : 1; + unsigned char : 3; +#endif +}; + +union un_icu_nmicr +{ + unsigned char BYTE; + struct st_icu_nmicr_bit BIT; +}; + +struct st_icu_nmiflte_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFLTEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char NFLTEN : 1; +#endif +}; + +union un_icu_nmiflte +{ + unsigned char BYTE; + struct st_icu_nmiflte_bit BIT; +}; + +struct st_icu_nmifltc_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCLKSEL : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char NFCLKSEL : 2; +#endif +}; + +union un_icu_nmifltc +{ + unsigned char BYTE; + struct st_icu_nmifltc_bit BIT; +}; + +struct st_icu_grpbe0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif +}; + +union un_icu_grpbe0 +{ + unsigned long LONG; + struct st_icu_grpbe0_bit BIT; +}; + +struct st_icu_grpbl2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long IS0 : 1; + unsigned long IS1 : 1; + unsigned long IS2 : 1; + unsigned long IS3 : 1; + unsigned long IS4 : 1; + unsigned long IS5 : 1; + unsigned long IS6 : 1; + unsigned long IS7 : 1; + unsigned long IS8 : 1; + unsigned long IS9 : 1; + unsigned long IS10 : 1; + unsigned long IS11 : 1; + unsigned long IS12 : 1; + unsigned long IS13 : 1; + unsigned long IS14 : 1; + unsigned long IS15 : 1; + unsigned long IS16 : 1; + unsigned long IS17 : 1; + unsigned long IS18 : 1; + unsigned long IS19 : 1; + unsigned long IS20 : 1; + unsigned long IS21 : 1; + unsigned long IS22 : 1; + unsigned long IS23 : 1; + unsigned long IS24 : 1; + unsigned long IS25 : 1; + unsigned long IS26 : 1; + unsigned long IS27 : 1; + unsigned long IS28 : 1; + unsigned long IS29 : 1; + unsigned long IS30 : 1; + unsigned long IS31 : 1; +#else + unsigned long IS31 : 1; + unsigned long IS30 : 1; + unsigned long IS29 : 1; + unsigned long IS28 : 1; + unsigned long IS27 : 1; + unsigned long IS26 : 1; + unsigned long IS25 : 1; + unsigned long IS24 : 1; + unsigned long IS23 : 1; + unsigned long IS22 : 1; + unsigned long IS21 : 1; + unsigned long IS20 : 1; + unsigned long IS19 : 1; + unsigned long IS18 : 1; + unsigned long IS17 : 1; + unsigned long IS16 : 1; + unsigned long IS15 : 1; + unsigned long IS14 : 1; + unsigned long IS13 : 1; + unsigned long IS12 : 1; + unsigned long IS11 : 1; + unsigned long IS10 : 1; + unsigned long IS9 : 1; + unsigned long IS8 : 1; + unsigned long IS7 : 1; + unsigned long IS6 : 1; + unsigned long IS5 : 1; + unsigned long IS4 : 1; + unsigned long IS3 : 1; + unsigned long IS2 : 1; + unsigned long IS1 : 1; + unsigned long IS0 : 1; +#endif +}; + +union un_icu_grpbl2 +{ + unsigned long LONG; + struct st_icu_grpbl2_bit BIT; +}; + +struct st_icu_genbe0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif +}; + +union un_icu_genbe0 +{ + unsigned long LONG; + struct st_icu_genbe0_bit BIT; +}; + +struct st_icu_genbl2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long EN0 : 1; + unsigned long EN1 : 1; + unsigned long EN2 : 1; + unsigned long EN3 : 1; + unsigned long EN4 : 1; + unsigned long EN5 : 1; + unsigned long EN6 : 1; + unsigned long EN7 : 1; + unsigned long EN8 : 1; + unsigned long EN9 : 1; + unsigned long EN10 : 1; + unsigned long EN11 : 1; + unsigned long EN12 : 1; + unsigned long EN13 : 1; + unsigned long EN14 : 1; + unsigned long EN15 : 1; + unsigned long EN16 : 1; + unsigned long EN17 : 1; + unsigned long EN18 : 1; + unsigned long EN19 : 1; + unsigned long EN20 : 1; + unsigned long EN21 : 1; + unsigned long EN22 : 1; + unsigned long EN23 : 1; + unsigned long EN24 : 1; + unsigned long EN25 : 1; + unsigned long EN26 : 1; + unsigned long EN27 : 1; + unsigned long EN28 : 1; + unsigned long EN29 : 1; + unsigned long EN30 : 1; + unsigned long EN31 : 1; +#else + unsigned long EN31 : 1; + unsigned long EN30 : 1; + unsigned long EN29 : 1; + unsigned long EN28 : 1; + unsigned long EN27 : 1; + unsigned long EN26 : 1; + unsigned long EN25 : 1; + unsigned long EN24 : 1; + unsigned long EN23 : 1; + unsigned long EN22 : 1; + unsigned long EN21 : 1; + unsigned long EN20 : 1; + unsigned long EN19 : 1; + unsigned long EN18 : 1; + unsigned long EN17 : 1; + unsigned long EN16 : 1; + unsigned long EN15 : 1; + unsigned long EN14 : 1; + unsigned long EN13 : 1; + unsigned long EN12 : 1; + unsigned long EN11 : 1; + unsigned long EN10 : 1; + unsigned long EN9 : 1; + unsigned long EN8 : 1; + unsigned long EN7 : 1; + unsigned long EN6 : 1; + unsigned long EN5 : 1; + unsigned long EN4 : 1; + unsigned long EN3 : 1; + unsigned long EN2 : 1; + unsigned long EN1 : 1; + unsigned long EN0 : 1; +#endif +}; + +union un_icu_genbl2 +{ + unsigned long LONG; + struct st_icu_genbl2_bit BIT; +}; + +struct st_icu_gcrbe0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long CLR0 : 1; + unsigned long CLR1 : 1; + unsigned long CLR2 : 1; + unsigned long CLR3 : 1; + unsigned long CLR4 : 1; + unsigned long CLR5 : 1; + unsigned long CLR6 : 1; + unsigned long CLR7 : 1; + unsigned long CLR8 : 1; + unsigned long CLR9 : 1; + unsigned long CLR10 : 1; + unsigned long CLR11 : 1; + unsigned long CLR12 : 1; + unsigned long CLR13 : 1; + unsigned long CLR14 : 1; + unsigned long CLR15 : 1; + unsigned long CLR16 : 1; + unsigned long CLR17 : 1; + unsigned long CLR18 : 1; + unsigned long CLR19 : 1; + unsigned long CLR20 : 1; + unsigned long CLR21 : 1; + unsigned long CLR22 : 1; + unsigned long CLR23 : 1; + unsigned long CLR24 : 1; + unsigned long CLR25 : 1; + unsigned long CLR26 : 1; + unsigned long CLR27 : 1; + unsigned long CLR28 : 1; + unsigned long CLR29 : 1; + unsigned long CLR30 : 1; + unsigned long CLR31 : 1; +#else + unsigned long CLR31 : 1; + unsigned long CLR30 : 1; + unsigned long CLR29 : 1; + unsigned long CLR28 : 1; + unsigned long CLR27 : 1; + unsigned long CLR26 : 1; + unsigned long CLR25 : 1; + unsigned long CLR24 : 1; + unsigned long CLR23 : 1; + unsigned long CLR22 : 1; + unsigned long CLR21 : 1; + unsigned long CLR20 : 1; + unsigned long CLR19 : 1; + unsigned long CLR18 : 1; + unsigned long CLR17 : 1; + unsigned long CLR16 : 1; + unsigned long CLR15 : 1; + unsigned long CLR14 : 1; + unsigned long CLR13 : 1; + unsigned long CLR12 : 1; + unsigned long CLR11 : 1; + unsigned long CLR10 : 1; + unsigned long CLR9 : 1; + unsigned long CLR8 : 1; + unsigned long CLR7 : 1; + unsigned long CLR6 : 1; + unsigned long CLR5 : 1; + unsigned long CLR4 : 1; + unsigned long CLR3 : 1; + unsigned long CLR2 : 1; + unsigned long CLR1 : 1; + unsigned long CLR0 : 1; +#endif +}; + +union un_icu_gcrbe0 +{ + unsigned long LONG; + struct st_icu_gcrbe0_bit BIT; +}; + +struct st_icu_pibr0_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibr0 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibr0_bit BIT; +#endif +}; + +struct st_icu_pibr1_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibr1 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibr1_bit BIT; +#endif +}; + +struct st_icu_pibr2_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibr2 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibr2_bit BIT; +#endif +}; + +struct st_icu_pibr3_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibr3 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibr3_bit BIT; +#endif +}; + +struct st_icu_pibr4_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibr4 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibr4_bit BIT; +#endif +}; + +struct st_icu_pibr5_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibr5 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibr5_bit BIT; +#endif +}; + +struct st_icu_pibr6_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibr6 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_prib6_bit BIT; +#endif +}; + +struct st_icu_pibr7_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibr7 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibr7_bit BIT; +#endif +}; + +struct st_icu_pibr8_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibr8 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibr8_bit BIT; +#endif +}; + +struct st_icu_pibr9_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibr9 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibr9_bit BIT; +#endif +}; + +struct st_icu_pibra_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibra +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibra_bit BIT; +#endif +}; + +struct st_icu_pibrb_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_pibrb +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_pibrb_bit BIT; +#endif +}; + +struct st_icu_slibxr128_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr128 +{ + unsigned char BYTE; + struct st_icu_slibxr128_bit BIT; +}; + +struct st_icu_slibxr129_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr129 +{ + unsigned char BYTE; + struct st_icu_slibxr129_bit BIT; +}; + +struct st_icu_slibxr130_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr130 +{ + unsigned char BYTE; + struct st_icu_slibxr130_bit BIT; +}; + +struct st_icu_slibxr131_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr131 +{ + unsigned char BYTE; + struct st_icu_slibxr131_bit BIT; +}; + +struct st_icu_slibxr132_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr132 +{ + unsigned char BYTE; + struct st_icu_slibxr132_bit BIT; +}; + +struct st_icu_slibxr133_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr133 +{ + unsigned char BYTE; + struct st_icu_slibxr133_bit BIT; +}; + +struct st_icu_slibxr134_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr134 +{ + unsigned char BYTE; + struct st_icu_slibxr134_bit BIT; +}; + +struct st_icu_slibxr135_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr135 +{ + unsigned char BYTE; + struct st_icu_slibxr135_bit BIT; +}; + +struct st_icu_slibxr136_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr136 +{ + unsigned char BYTE; + struct st_icu_slibxr136_bit BIT; +}; + +struct st_icu_slibxr137_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr137 +{ + unsigned char BYTE; + struct st_icu_slibxr137_bit BIT; +}; + +struct st_icu_slibxr138_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr138 +{ + unsigned char BYTE; + struct st_icu_slibxr138_bit BIT; +}; + +struct st_icu_slibxr139_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr139 +{ + unsigned char BYTE; + struct st_icu_slibxr139_bit BIT; +}; + +struct st_icu_slibxr140_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr140 +{ + unsigned char BYTE; + struct st_icu_slibxr140_bit BIT; +}; + +struct st_icu_slibxr141_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr141 +{ + unsigned char BYTE; + struct st_icu_slibxr141_bit BIT; +}; + +struct st_icu_slibxr142_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr142 +{ + unsigned char BYTE; + struct st_icu_slibxr142_bit BIT; +}; + +struct st_icu_slibxr143_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibxr143 +{ + unsigned char BYTE; + struct st_icu_slibxr143_bit BIT; +}; + +struct st_icu_slibr144_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr144 +{ + unsigned char BYTE; + struct st_icu_slibr144_bit BIT; +}; + +struct st_icu_slibr145_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr145 +{ + unsigned char BYTE; + struct st_icu_slibr145_bit BIT; +}; + +struct st_icu_slibr146_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr146 +{ + unsigned char BYTE; + struct st_icu_slibr146_bit BIT; +}; + +struct st_icu_slibr147_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr147 +{ + unsigned char BYTE; + struct st_icu_slibr147_bit BIT; +}; + +struct st_icu_slibr148_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr148 +{ + unsigned char BYTE; + struct st_icu_slibr148_bit BIT; +}; + +struct st_icu_slibr149_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr149 +{ + unsigned char BYTE; + struct st_icu_slibr149_bit BIT; +}; + +struct st_icu_slibr150_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr150 +{ + unsigned char BYTE; + struct st_icu_slibr150_bit BIT; +}; + +struct st_icu_slibr151_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr151 +{ + unsigned char BYTE; + struct st_icu_slibr151_bit BIT; +}; + +struct st_icu_slibr152_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr152 +{ + unsigned char BYTE; + struct st_icu_slibr152_bit BIT; +}; + +struct st_icu_slibr153_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr153 +{ + unsigned char BYTE; + struct st_icu_slibr153_bit BIT; +}; + +struct st_icu_slibr154_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr154 +{ + unsigned char BYTE; + struct st_icu_slibr154_bit BIT; +}; + +struct st_icu_slibr155_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr155 +{ + unsigned char BYTE; + struct st_icu_slibr155_bit BIT; +}; + +struct st_icu_slibr156_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr156 +{ + unsigned char BYTE; + struct st_icu_slibr156_bit BIT; +}; + +struct st_icu_slibr157_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr157 +{ + unsigned char BYTE; + struct st_icu_slibr157_bit BIT; +}; + +struct st_icu_slibr158_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr158 +{ + unsigned char BYTE; + struct st_icu_slibr158_bit BIT; +}; + +struct st_icu_slibr159_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr159 +{ + unsigned char BYTE; + struct st_icu_slibr159_bit BIT; +}; + +struct st_icu_slibr160_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr160 +{ + unsigned char BYTE; + struct st_icu_slibr160_bit BIT; +}; + +struct st_icu_slibr161_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr161 +{ + unsigned char BYTE; + struct st_icu_slibr161_bit BIT; +}; + +struct st_icu_slibr162_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr162 +{ + unsigned char BYTE; + struct st_icu_slibr162_bit BIT; +}; + +struct st_icu_slibr163_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr163 +{ + unsigned char BYTE; + struct st_icu_slibr163_bit BIT; +}; + +struct st_icu_slibr164_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr164 +{ + unsigned char BYTE; + struct st_icu_slibr164_bit BIT; +}; + +struct st_icu_slibr165_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr165 +{ + unsigned char BYTE; + struct st_icu_slibr165_bit BIT; +}; + +struct st_icu_slibr166_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr166 +{ + unsigned char BYTE; + struct st_icu_slibr166_bit BIT; +}; + +struct st_icu_slibr167_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr167 +{ + unsigned char BYTE; + struct st_icu_slibr167_bit BIT; +}; + +struct st_icu_slibr168_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr168 +{ + unsigned char BYTE; + struct st_icu_slibr168_bit BIT; +}; + +struct st_icu_slibr169_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr169 +{ + unsigned char BYTE; + struct st_icu_slibr169_bit BIT; +}; + +struct st_icu_slibr170_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr170 +{ + unsigned char BYTE; + struct st_icu_slibr170_bit BIT; +}; + +struct st_icu_slibr171_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr171 +{ + unsigned char BYTE; + struct st_icu_slibr171_bit BIT; +}; + +struct st_icu_slibr172_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr172 +{ + unsigned char BYTE; + struct st_icu_slibr172_bit BIT; +}; + +struct st_icu_slibr173_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr173 +{ + unsigned char BYTE; + struct st_icu_slibr173_bit BIT; +}; + +struct st_icu_slibr174_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr174 +{ + unsigned char BYTE; + struct st_icu_slibr174_bit BIT; +}; + +struct st_icu_slibr175_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr175 +{ + unsigned char BYTE; + struct st_icu_slibr175_bit BIT; +}; + +struct st_icu_slibr176_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr176 +{ + unsigned char BYTE; + struct st_icu_slibr176_bit BIT; +}; + +struct st_icu_slibr177_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr177 +{ + unsigned char BYTE; + struct st_icu_slibr177_bit BIT; +}; + +struct st_icu_slibr178_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr178 +{ + unsigned char BYTE; + struct st_icu_slibr178_bit BIT; +}; + +struct st_icu_slibr179_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr179 +{ + unsigned char BYTE; + struct st_icu_slibr179_bit BIT; +}; + +struct st_icu_slibr180_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr180 +{ + unsigned char BYTE; + struct st_icu_slibr180_bit BIT; +}; + +struct st_icu_slibr181_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr181 +{ + unsigned char BYTE; + struct st_icu_slibr181_bit BIT; +}; + +struct st_icu_slibr182_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr182 +{ + unsigned char BYTE; + struct st_icu_slibr182_bit BIT; +}; + +struct st_icu_slibr183_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr183 +{ + unsigned char BYTE; + struct st_icu_slibr183_bit BIT; +}; + +struct st_icu_slibr184_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr184 +{ + unsigned char BYTE; + struct st_icu_slibr184_bit BIT; +}; + +struct st_icu_slibr185_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr185 +{ + unsigned char BYTE; + struct st_icu_slibr185_bit BIT; +}; + +struct st_icu_slibr186_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr186 +{ + unsigned char BYTE; + struct st_icu_slibr186_bit BIT; +}; + +struct st_icu_slibr187_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr187 +{ + unsigned char BYTE; + struct st_icu_slibr187_bit BIT; +}; + +struct st_icu_slibr188_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr188 +{ + unsigned char BYTE; + struct st_icu_slibr188_bit BIT; +}; + +struct st_icu_slibr189_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr189 +{ + unsigned char BYTE; + struct st_icu_slibr189_bit BIT; +}; + +struct st_icu_slibr190_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr190 +{ + unsigned char BYTE; + struct st_icu_slibr190_bit BIT; +}; + +struct st_icu_slibr191_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr191 +{ + unsigned char BYTE; + struct st_icu_slibr191_bit BIT; +}; + +struct st_icu_slibr192_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr192 +{ + unsigned char BYTE; + struct st_icu_slibr192_bit BIT; +}; + +struct st_icu_slibr193_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr193 +{ + unsigned char BYTE; + struct st_icu_slibr193_bit BIT; +}; + +struct st_icu_slibr194_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr194 +{ + unsigned char BYTE; + struct st_icu_slibr194_bit BIT; +}; + +struct st_icu_slibr195_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr195 +{ + unsigned char BYTE; + struct st_icu_slibr195_bit BIT; +}; + +struct st_icu_slibr196_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr196 +{ + unsigned char BYTE; + struct st_icu_slibr196_bit BIT; +}; + +struct st_icu_slibr197_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr197 +{ + unsigned char BYTE; + struct st_icu_slibr197_bit BIT; +}; + +struct st_icu_slibr198_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr198 +{ + unsigned char BYTE; + struct st_icu_slibr198_bit BIT; +}; + +struct st_icu_slibr199_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr199 +{ + unsigned char BYTE; + struct st_icu_slibr199_bit BIT; +}; + +struct st_icu_slibr200_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr200 +{ + unsigned char BYTE; + struct st_icu_slibr200_bit BIT; +}; + +struct st_icu_slibr201_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr201 +{ + unsigned char BYTE; + struct st_icu_slibr201_bit BIT; +}; + +struct st_icu_slibr202_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr202 +{ + unsigned char BYTE; + struct st_icu_slibr202_bit BIT; +}; + +struct st_icu_slibr203_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr203 +{ + unsigned char BYTE; + struct st_icu_slibr203_bit BIT; +}; + +struct st_icu_slibr204_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr204 +{ + unsigned char BYTE; + struct st_icu_slibr204_bit BIT; +}; + +struct st_icu_slibr205_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr205 +{ + unsigned char BYTE; + struct st_icu_slibr205_bit BIT; +}; + +struct st_icu_slibr206_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr206 +{ + unsigned char BYTE; + struct st_icu_slibr206_bit BIT; +}; + +struct st_icu_slibr207_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SLI : 8; +#else + unsigned char SLI : 8; +#endif +}; + +union un_icu_slibr207 +{ + unsigned char BYTE; + struct st_icu_slibr207_bit BIT; +}; + +struct st_icu_piar0_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_piar0 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_piar0_bit BIT; +#endif +}; + +struct st_icu_piar1_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_piar1 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_piar1_bit BIT; +#endif +}; + +struct st_icu_piar2_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_piar2 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_piar2_bit BIT; +#endif +}; + +struct st_icu_piar3_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_piar3 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_piar3_bit BIT; +#endif +}; + +struct st_icu_piar4_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_piar4 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_piar4_bit BIT; +#endif +}; + +struct st_icu_piar5_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_piar5 +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_piar5_bit BIT; +#endif +}; + +struct st_icu_piarb_bit +{ + unsigned char PIR7:1; + unsigned char PIR6:1; + unsigned char PIR5:1; + unsigned char PIR4:1; + unsigned char PIR3:1; + unsigned char PIR2:1; + unsigned char PIR1:1; + unsigned char PIR0:1; +}; + +union un_icu_piarb +{ + unsigned char BYTE; +#ifdef IODEFINE_H_HISTORY + struct st_icu_piarb_bit BIT; +#endif +}; + +union un_icu_sliar208 +{ + unsigned char BYTE; +}; + +union un_icu_sliar209 +{ + unsigned char BYTE; +}; + +union un_icu_sliar210 +{ + unsigned char BYTE; +}; + +union un_icu_sliar211 +{ + unsigned char BYTE; +}; + +union un_icu_sliar212 +{ + unsigned char BYTE; +}; + +union un_icu_sliar213 +{ + unsigned char BYTE; +}; + +union un_icu_sliar214 +{ + unsigned char BYTE; +}; + +union un_icu_sliar215 +{ + unsigned char BYTE; +}; + +union un_icu_sliar216 +{ + unsigned char BYTE; +}; + +union un_icu_sliar217 +{ + unsigned char BYTE; +}; + +union un_icu_sliar218 +{ + unsigned char BYTE; +}; + +union un_icu_sliar219 +{ + unsigned char BYTE; +}; + +union un_icu_sliar220 +{ + unsigned char BYTE; +}; + +union un_icu_sliar221 +{ + unsigned char BYTE; +}; + +union un_icu_sliar222 +{ + unsigned char BYTE; +}; + +union un_icu_sliar223 +{ + unsigned char BYTE; +}; + +union un_icu_sliar224 +{ + unsigned char BYTE; +}; + +union un_icu_sliar225 +{ + unsigned char BYTE; +}; + +union un_icu_sliar226 +{ + unsigned char BYTE; +}; + +union un_icu_sliar227 +{ + unsigned char BYTE; +}; + +union un_icu_sliar228 +{ + unsigned char BYTE; +}; + +union un_icu_sliar229 +{ + unsigned char BYTE; +}; + +union un_icu_sliar230 +{ + unsigned char BYTE; +}; + +union un_icu_sliar231 +{ + unsigned char BYTE; +}; + +union un_icu_sliar232 +{ + unsigned char BYTE; +}; + +union un_icu_sliar233 +{ + unsigned char BYTE; +}; + +union un_icu_sliar234 +{ + unsigned char BYTE; +}; + +union un_icu_sliar235 +{ + unsigned char BYTE; +}; + +union un_icu_sliar236 +{ + unsigned char BYTE; +}; + +union un_icu_sliar237 +{ + unsigned char BYTE; +}; + +union un_icu_sliar238 +{ + unsigned char BYTE; +}; + +union un_icu_sliar239 +{ + unsigned char BYTE; +}; + +union un_icu_sliar240 +{ + unsigned char BYTE; +}; + +union un_icu_sliar241 +{ + unsigned char BYTE; +}; + +union un_icu_sliar242 +{ + unsigned char BYTE; +}; + +union un_icu_sliar243 +{ + unsigned char BYTE; +}; + +union un_icu_sliar244 +{ + unsigned char BYTE; +}; + +union un_icu_sliar245 +{ + unsigned char BYTE; +}; + +union un_icu_sliar246 +{ + unsigned char BYTE; +}; + +union un_icu_sliar247 +{ + unsigned char BYTE; +}; + +union un_icu_sliar248 +{ + unsigned char BYTE; +}; + +union un_icu_sliar249 +{ + unsigned char BYTE; +}; + +union un_icu_sliar250 +{ + unsigned char BYTE; +}; + +union un_icu_sliar251 +{ + unsigned char BYTE; +}; + +union un_icu_sliar252 +{ + unsigned char BYTE; +}; + +union un_icu_sliar253 +{ + unsigned char BYTE; +}; + +union un_icu_sliar254 +{ + unsigned char BYTE; +}; + +union un_icu_sliar255 +{ + unsigned char BYTE; +}; + +struct st_icu_sliprcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WPRC : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char WPRC : 1; +#endif +}; + +union un_icu_sliprcr +{ + unsigned char BYTE; + struct st_icu_sliprcr_bit BIT; +}; + +struct st_icu_slexdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SELEXD0 : 1; + unsigned char SELEXD1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char SELEXD1 : 1; + unsigned char SELEXD0 : 1; +#endif +}; + +union un_icu_slexdr +{ + unsigned char BYTE; + struct st_icu_slexdr_bit BIT; +}; + +struct st_rtc_r64cnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char F64HZ : 1; + unsigned char F32HZ : 1; + unsigned char F16HZ : 1; + unsigned char F8HZ : 1; + unsigned char F4HZ : 1; + unsigned char F2HZ : 1; + unsigned char F1HZ : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char F1HZ : 1; + unsigned char F2HZ : 1; + unsigned char F4HZ : 1; + unsigned char F8HZ : 1; + unsigned char F16HZ : 1; + unsigned char F32HZ : 1; + unsigned char F64HZ : 1; +#endif +}; + +union un_rtc_r64cnt +{ + unsigned char BYTE; + struct st_rtc_r64cnt_bit BIT; +}; + +struct st_rtc_rseccnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif +}; + +union un_rtc_rseccnt +{ + unsigned char BYTE; + struct st_rtc_rseccnt_bit BIT; +}; + +struct st_rtc_bcnt0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif +}; + +union un_rtc_bcnt0 +{ + unsigned char BYTE; + struct st_rtc_bcnt0_bit BIT; +}; + +struct st_rtc_rmincnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif +}; + +union un_rtc_rmincnt +{ + unsigned char BYTE; + struct st_rtc_rmincnt_bit BIT; +} ; + +struct st_rtc_bcnt1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif +}; + +union un_rtc_bcnt1 +{ + unsigned char BYTE; + struct st_rtc_bcnt1_bit BIT; +}; + +struct st_rtc_rhrcnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif +}; + +union un_rtc_rhrcnt +{ + unsigned char BYTE; + struct st_rtc_rhrcnt_bit BIT; +}; + +struct st_rtc_bcnt2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif +}; + +union un_rtc_bcnt2 +{ + unsigned char BYTE; + struct st_rtc_bcnt2_bit BIT; +}; + +struct st_rtc_rwkcnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAYW : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char DAYW : 3; +#endif +}; + +union un_rtc_rwkcnt +{ + unsigned char BYTE; + struct st_rtc_rwkcnt_bit BIT; +}; + +struct st_rtc_bcnt3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNT : 8; +#else + unsigned char BCNT : 8; +#endif +}; + +union un_rtc_bcnt3 +{ + unsigned char BYTE; + struct st_rtc_bcnt3_bit BIT; +}; + +struct st_rtc_rdaycnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif +}; + +union un_rtc_rdaycnt +{ + unsigned char BYTE; + struct st_rtc_rdaycnt_bit BIT; +}; + +struct st_rtc_rmoncnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif +}; + +union un_rtc_rmoncnt +{ + unsigned char BYTE; + struct st_rtc_rmoncnt_bit BIT; +}; + +struct st_rtc_ryrcnt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short YR1 : 4; + unsigned short YR10 : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short YR10 : 4; + unsigned short YR1 : 4; +#endif +}; + +union un_rtc_ryrcnt +{ + unsigned short WORD; + struct st_rtc_ryrcnt_bit BIT; +}; + +struct st_rtc_rsecar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif +}; + +union un_rtc_rsecar +{ + unsigned char BYTE; + struct st_rtc_rsecar_bit BIT; +}; + +struct st_rtc_bcnt0ar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif +}; + +union un_rtc_bcnt0ar +{ + unsigned char BYTE; + struct st_rtc_bcnt0ar_bit BIT; +}; + +struct st_rtc_rminar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif +}; + +union un_rtc_rminar +{ + unsigned char BYTE; + struct st_rtc_rminar_bit BIT; +}; + +struct st_rtc_bcnt1ar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif +}; + +union un_rtc_bcnt1ar +{ + unsigned char BYTE; + struct st_rtc_bcnt1ar_bit BIT; +}; + +struct st_rtc_rhrar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif +}; + +union un_rtc_rhrar +{ + unsigned char BYTE; + struct st_rtc_rhrar_bit BIT; +}; + +struct st_rtc_bcnt2ar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif +}; + +union un_rtc_bcnt2ar +{ + unsigned char BYTE; + struct st_rtc_bcnt2ar_bit BIT; +}; + +struct st_rtc_rwkar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DAYW : 3; + unsigned char : 4; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 4; + unsigned char DAYW : 3; +#endif +}; + +union un_rtc_rwkar +{ + unsigned char BYTE; + struct st_rtc_rwkar_bit BIT; +}; + +struct st_rtc_bcnt3ar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTAR : 8; +#else + unsigned char BCNTAR : 8; +#endif +}; + +union un_rtc_bcnt3ar +{ + unsigned char BYTE; + struct st_rtc_bcnt3ar_bit BIT; +}; + +struct st_rtc_rdayar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 1; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 1; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif +}; + +union un_rtc_rdayar +{ + unsigned char BYTE; + struct st_rtc_rdayar_bit BIT; +}; + +struct st_rtc_bcnt0aer_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif +}; + +union un_rtc_bcnt0aer +{ + unsigned char BYTE; + struct st_rtc_bcnt0aer_bit BIT; +}; + +struct st_rtc_rmonar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 2; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 2; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif +}; + +union un_rtc_rmonar +{ + unsigned char BYTE; + struct st_rtc_rmonar_bit BIT; +}; + +struct st_rtc_bcnt1aer_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif +}; + +union un_rtc_bcnt1aer +{ + unsigned char BYTE; + struct st_rtc_bcnt1aer_bit BIT; +}; + +struct st_rtc_ryrar_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short YR1 : 4; + unsigned short YR10 : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short YR10 : 4; + unsigned short YR1 : 4; +#endif +}; + +union un_rtc_ryrar +{ + unsigned short WORD; + struct st_rtc_ryrar_bit BIT; +}; + +struct st_rtc_bcnt2aer_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ENB : 8; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short ENB : 8; +#endif +}; + +union un_rtc_bcnt2aer +{ + unsigned short WORD; + struct st_rtc_bcnt2aer_bit BIT; +}; + +struct st_rtc_bcnt3aer_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ENB : 8; +#else + unsigned char ENB : 8; +#endif +}; + +union un_rtc_bcnt3aer +{ + unsigned char BYTE; + struct st_rtc_bcnt3aer_bit BIT; +}; + +struct st_rtc_ryraren_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char ENB : 1; +#else + unsigned char ENB : 1; + unsigned char : 7; +#endif +}; + +union un_rtc_ryraren +{ + unsigned char BYTE; + struct st_rtc_ryraren_bit BIT; +}; + +struct st_rtc_rcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char AIE : 1; + unsigned char CIE : 1; + unsigned char PIE : 1; + unsigned char RTCOS : 1; + unsigned char PES : 4; +#else + unsigned char PES : 4; + unsigned char RTCOS : 1; + unsigned char PIE : 1; + unsigned char CIE : 1; + unsigned char AIE : 1; +#endif +}; + +union un_rtc_rcr1 +{ + unsigned char BYTE; + struct st_rtc_rcr1_bit BIT; +}; + +struct st_rtc_rcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char START : 1; + unsigned char RESET : 1; + unsigned char ADJ30 : 1; + unsigned char RTCOE : 1; + unsigned char AADJE : 1; + unsigned char AADJP : 1; + unsigned char HR24 : 1; + unsigned char CNTMD : 1; +#else + unsigned char CNTMD : 1; + unsigned char HR24 : 1; + unsigned char AADJP : 1; + unsigned char AADJE : 1; + unsigned char RTCOE : 1; + unsigned char ADJ30 : 1; + unsigned char RESET : 1; + unsigned char START : 1; +#endif +}; + +union un_rtc_rcr2 +{ + unsigned char BYTE; + struct st_rtc_rcr2_bit BIT; +}; + +struct st_rtc_rcr4_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RCKSEL : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char RCKSEL : 1; +#endif +}; + +union un_rtc_rcr4 +{ + unsigned char BYTE; + struct st_rtc_rcr4_bit BIT; +}; + +struct st_rtc_rfrh_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFC : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short RFC : 1; +#endif +}; + +union un_rtc_rfrh +{ + unsigned short WORD; + struct st_rtc_rfrh_bit BIT; +}; + +struct st_rtc_rfrl_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RFC : 16; +#else + unsigned short RFC : 16; +#endif +}; + +union un_rtc_rfrl +{ + unsigned short WORD; + struct st_rtc_rfrl_bit BIT; +}; + +struct st_rtc_radj_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADJ : 6; + unsigned char PMADJ : 2; +#else + unsigned char PMADJ : 2; + unsigned char ADJ : 6; +#endif +}; + +union un_rtc_radj +{ + unsigned char BYTE; + struct st_rtc_radj_bit BIT; +}; + +struct st_rtc_rtccr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCCT : 2; + unsigned char TCST : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCEN : 1; +#else + unsigned char TCEN : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCST : 1; + unsigned char TCCT : 2; +#endif +}; + +union un_rtc_rtccr0 +{ + unsigned char BYTE; + struct st_rtc_rtccr0_bit BIT; +}; + +struct st_rtc_rtccr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCCT : 2; + unsigned char TCST : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCEN : 1; +#else + unsigned char TCEN : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCST : 1; + unsigned char TCCT : 2; +#endif +}; + +union un_rtc_rtccr1 +{ + unsigned char BYTE; + struct st_rtc_rtccr1_bit BIT; +}; + +struct st_rtc_rtccr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCCT : 2; + unsigned char TCST : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCEN : 1; +#else + unsigned char TCEN : 1; + unsigned char : 1; + unsigned char TCNF : 2; + unsigned char : 1; + unsigned char TCST : 1; + unsigned char TCCT : 2; +#endif +}; + +union un_rtc_rtccr2 +{ + unsigned char BYTE; + struct st_rtc_rtccr2_bit BIT; +}; + +struct st_rtc_rseccp0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif +}; + +union un_rtc_rseccp0 +{ + unsigned char BYTE; + struct st_rtc_rseccp0_bit BIT; +}; + +struct st_rtc_bcnt0cp0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP0 : 8; +#else + unsigned char BCNTCP0 : 8; +#endif +}; + +union un_rtc_bcnt0cp0 +{ + unsigned char BYTE; + struct st_rtc_bcnt0cp0_bit BIT; +}; + +struct st_rtc_rmincp0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif +}; + +union un_rtc_rmincp0 +{ + unsigned char BYTE; + struct st_rtc_rmincp0_bit BIT; +}; + +struct st_rtc_bcnt1cp0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP0 : 8; +#else + unsigned char BCNTCP0 : 8; +#endif +}; + +union un_rtc_bcnt1cp0 +{ + unsigned char BYTE; + struct st_rtc_bcnt1cp0_bit BIT; +}; + +struct st_rtc_rhrcp0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif +}; + +union un_rtc_rhrcp0 +{ + unsigned char BYTE; + struct st_rtc_rhrcp0_bit BIT; +}; + +struct st_rtc_bcnt2cp0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP0 : 8; +#else + unsigned char BCNTCP0 : 8; +#endif +}; + +union un_rtc_bcnt2cp0 +{ + unsigned char BYTE; + struct st_rtc_bcnt2cp0_bit BIT; +}; + +struct st_rtc_rdaycp0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif +}; + +union un_rtc_rdaycp0 +{ + unsigned char BYTE; + struct st_rtc_rdaycp0_bit BIT; +}; + +struct st_rtc_bcnt3cp0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP0 : 8; +#else + unsigned char BCNTCP0 : 8; +#endif +}; + +union un_rtc_bcnt3cp0 +{ + unsigned char BYTE; + struct st_rtc_bcnt3cp0_bit BIT; +}; + +struct st_rtc_rmoncp0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif +}; + +union un_rtc_rmoncp0 +{ + unsigned char BYTE; + struct st_rtc_rmoncp0_bit BIT; +}; + +struct st_rtc_rseccp1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif +}; + +union un_rtc_rseccp1 +{ + unsigned char BYTE; + struct st_rtc_rseccp1_bit BIT; +}; + +struct st_rtc_bcnt0cp1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP1 : 8; +#else + unsigned char BCNTCP1 : 8; +#endif +}; + +union un_rtc_bcnt0cp1 +{ + unsigned char BYTE; + struct st_rtc_bcnt0cp1_bit BIT; +}; + +struct st_rtc_rmincp1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif +}; + +union un_rtc_rmincp1 +{ + unsigned char BYTE; + struct st_rtc_rmincp1_bit BIT; +}; + +struct st_rtc_bcnt1cp1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP1 : 8; +#else + unsigned char BCNTCP1 : 8; +#endif +}; + +union un_rtc_bcnt1cp1 +{ + unsigned char BYTE; + struct st_rtc_bcnt1cp1_bit BIT; +}; + +struct st_rtc_rhrcp1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif +}; + +union un_rtc_rhrcp1 +{ + unsigned char BYTE; + struct st_rtc_rhrcp1_bit BIT; +}; + +struct st_rtc_bcnt2cp1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP1 : 8; +#else + unsigned char BCNTCP1 : 8; +#endif +}; + +union un_rtc_bcnt2cp1 +{ + unsigned char BYTE; + struct st_rtc_bcnt2cp1_bit BIT; +}; + +struct st_rtc_rdaycp1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif +}; + +union un_rtc_rdaycp1 +{ + unsigned char BYTE; + struct st_rtc_rdaycp1_bit BIT; +}; + +struct st_rtc_bcnt3cp1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP1 : 8; +#else + unsigned char BCNTCP1 : 8; +#endif +}; + +union un_rtc_bcnt3cp1 +{ + unsigned char BYTE; + struct st_rtc_bcnt3cp1_bit BIT; +}; + +struct st_rtc_rmoncp1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif +}; + +union un_rtc_rmoncp1 +{ + unsigned char BYTE; + struct st_rtc_rmoncp1_bit BIT; +}; + +struct st_rtc_rseccp2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SEC1 : 4; + unsigned char SEC10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char SEC10 : 3; + unsigned char SEC1 : 4; +#endif +}; + +union un_rtc_rseccp2 +{ + unsigned char BYTE; + struct st_rtc_rseccp2_bit BIT; +}; + +struct st_rtc_bcnt0cp2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP2 : 8; +#else + unsigned char BCNTCP2 : 8; +#endif +}; + +union un_rtc_bcnt0cp2 +{ + unsigned char BYTE; + struct st_rtc_bcnt0cp2_bit BIT; +}; + +struct st_rtc_rmincp2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MIN1 : 4; + unsigned char MIN10 : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MIN10 : 3; + unsigned char MIN1 : 4; +#endif +}; + +union un_rtc_rmincp2 +{ + unsigned char BYTE; + struct st_rtc_rmincp2_bit BIT; +}; + +struct st_rtc_bcnt1cp2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP2 : 8; +#else + unsigned char BCNTCP2 : 8; +#endif +}; + +union un_rtc_bcnt1cp2 +{ + unsigned char BYTE; + struct st_rtc_bcnt1cp2_bit BIT; +}; + +struct st_rtc_rhrcp2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HR1 : 4; + unsigned char HR10 : 2; + unsigned char PM : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char PM : 1; + unsigned char HR10 : 2; + unsigned char HR1 : 4; +#endif +}; + +union un_rtc_rhrcp2 +{ + unsigned char BYTE; + struct st_rtc_rhrcp2_bit BIT; +}; + +struct st_rtc_bcnt2cp2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP2 : 8; +#else + unsigned char BCNTCP2 : 8; +#endif +}; + +union un_rtc_bcnt2cp2 +{ + unsigned char BYTE; + struct st_rtc_bcnt2cp2_bit BIT; +}; + +struct st_rtc_rdaycp2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DATE1 : 4; + unsigned char DATE10 : 2; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char DATE10 : 2; + unsigned char DATE1 : 4; +#endif +}; + +union un_rtc_rdaycp2 +{ + unsigned char BYTE; + struct st_rtc_rdaycp2_bit BIT; +}; + +struct st_rtc_bcnt3cp2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCNTCP2 : 8; +#else + unsigned char BCNTCP2 : 8; +#endif +}; + +union un_rtc_bcnt3cp2 +{ + unsigned char BYTE; + struct st_rtc_bcnt3cp2_bit BIT; +}; + +struct st_rtc_rmoncp2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MON1 : 4; + unsigned char MON10 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char MON10 : 1; + unsigned char MON1 : 4; +#endif +}; + +union un_rtc_rmoncp2 +{ + unsigned char BYTE; + struct st_rtc_rmoncp2_bit BIT; +}; + +struct st_mpc_p00pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_p00pfs +{ + unsigned char BYTE; + struct st_mpc_p00pfs_bit BIT; +}; + +struct st_mpc_p01pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_p01pfs +{ + unsigned char BYTE; + struct st_mpc_p01pfs_bit BIT; +}; + +struct st_mpc_pfcse_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CS0E : 1; + unsigned char CS1E : 1; + unsigned char CS2E : 1; + unsigned char CS3E : 1; + unsigned char CS4E : 1; + unsigned char CS5E : 1; + unsigned char CS6E : 1; + unsigned char CS7E : 1; +#else + unsigned char CS7E : 1; + unsigned char CS6E : 1; + unsigned char CS5E : 1; + unsigned char CS4E : 1; + unsigned char CS3E : 1; + unsigned char CS2E : 1; + unsigned char CS1E : 1; + unsigned char CS0E : 1; +#endif +}; + +union un_mpc_pfcse +{ + unsigned char BYTE; + struct st_mpc_pfcse_bit BIT; +}; + +struct st_mpc_pfcss0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CS0S : 1; + unsigned char : 1; + unsigned char CS1S : 2; + unsigned char CS2S : 2; + unsigned char CS3S : 2; +#else + unsigned char CS3S : 2; + unsigned char CS2S : 2; + unsigned char CS1S : 2; + unsigned char : 1; + unsigned char CS0S : 1; +#endif +}; + +union un_mpc_pfcss0 +{ + unsigned char BYTE; + struct st_mpc_pfcss0_bit BIT; +}; + +struct st_mpc_pfcss1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CS4S : 2; + unsigned char CS5S : 2; + unsigned char CS6S : 2; + unsigned char CS7S : 2; +#else + unsigned char CS7S : 2; + unsigned char CS6S : 2; + unsigned char CS5S : 2; + unsigned char CS4S : 2; +#endif +}; + +union un_mpc_pfcss1 +{ + unsigned char BYTE; + struct st_mpc_pfcss1_bit BIT; +}; + +struct st_mpc_pfa0e0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char A8E : 1; + unsigned char A9E : 1; + unsigned char A10E : 1; + unsigned char A11E : 1; + unsigned char A12E : 1; + unsigned char A13E : 1; + unsigned char A14E : 1; + unsigned char A15E : 1; +#else + unsigned char A15E : 1; + unsigned char A14E : 1; + unsigned char A13E : 1; + unsigned char A12E : 1; + unsigned char A11E : 1; + unsigned char A10E : 1; + unsigned char A9E : 1; + unsigned char A8E : 1; +#endif +}; + +union un_mpc_pfa0e0 +{ + unsigned char BYTE; + struct st_mpc_pfa0e0_bit BIT; +}; + +struct st_mpc_pfa0e1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char A16E : 1; + unsigned char A17E : 1; + unsigned char A18E : 1; + unsigned char A19E : 1; + unsigned char A20E : 1; + unsigned char A21E : 1; + unsigned char A22E : 1; + unsigned char A23E : 1; +#else + unsigned char A23E : 1; + unsigned char A22E : 1; + unsigned char A21E : 1; + unsigned char A20E : 1; + unsigned char A19E : 1; + unsigned char A18E : 1; + unsigned char A17E : 1; + unsigned char A16E : 1; +#endif +}; + +union un_mpc_pfa0e1 +{ + unsigned char BYTE; + struct st_mpc_pfa0e1_bit BIT; +}; + +struct st_mpc_pfbcr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ADRLE : 1; + unsigned char ADRHMS : 1; + unsigned char ADRHMS2 : 1; + unsigned char BCLKO : 1; + unsigned char DHE : 1; + unsigned char DH32E : 1; + unsigned char WR1BC1E : 1; + unsigned char WR32BC32E : 1; +#else + unsigned char WR32BC32E : 1; + unsigned char WR1BC1E : 1; + unsigned char DH32E : 1; + unsigned char DHE : 1; + unsigned char BCLKO : 1; + unsigned char ADRHMS2 : 1; + unsigned char ADRHMS : 1; + unsigned char ADRLE : 1; +#endif +}; + +union un_mpc_pfbcr0 +{ + unsigned char BYTE; + struct st_mpc_pfbcr0_bit BIT; +}; + +struct st_mpc_pfbcr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char WAITS : 2; + unsigned char ALEOE : 1; + unsigned char ALES : 1; + unsigned char MDSDE : 1; + unsigned char : 1; + unsigned char DQM1E : 1; + unsigned char SDCLKE : 1; +#else + unsigned char SDCLKE : 1; + unsigned char DQM1E : 1; + unsigned char : 1; + unsigned char MDSDE : 1; + unsigned char ALES : 1; + unsigned char ALEOE : 1; + unsigned char WAITS : 2; +#endif +}; + +union un_mpc_pfbcr1 +{ + unsigned char BYTE; + struct st_mpc_pfbcr1_bit BIT; +}; + +struct st_mpc_pfbcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char D0S : 2; + unsigned char D1S : 2; + unsigned char D2S : 2; + unsigned char D3S : 2; +#else + unsigned char D3S : 2; + unsigned char D2S : 2; + unsigned char D1S : 2; + unsigned char D0S : 2; +#endif +}; + +union un_mpc_pfbcr2 +{ + unsigned char BYTE; + struct st_mpc_pfbcr2_bit BIT; +}; + +struct st_mpc_pfbcr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DLHS : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DLHS : 1; +#endif +}; + +union un_mpc_pfbcr3 +{ + unsigned char BYTE; + struct st_mpc_pfbcr3_bit BIT; +}; + +struct st_mpc_pfenet_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 4; + unsigned char PHYMODE0 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char PHYMODE0 : 1; + unsigned char : 4; +#endif +}; + +union un_mpc_pfenet +{ + unsigned char BYTE; + struct st_mpc_pfenet_bit BIT; +}; + +struct st_mpc_p02pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p02pfs +{ + unsigned char BYTE; + struct st_mpc_p02pfs_bit BIT; +}; + +struct st_mpc_p03pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_p03pfs +{ + unsigned char BYTE; + struct st_mpc_p03pfs_bit BIT; +}; + +struct st_mpc_p05pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_p05pfs +{ + unsigned char BYTE; + struct st_mpc_p05pfs_bit BIT; +}; + +struct st_mpc_p07pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p07pfs +{ + unsigned char BYTE; + struct st_mpc_p07pfs_bit BIT; +}; + +struct st_mpc_p10pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p10pfs +{ + unsigned char BYTE; + struct st_mpc_p10pfs_bit BIT; +}; + +struct st_mpc_p11pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p11pfs +{ + unsigned char BYTE; + struct st_mpc_p11pfs_bit BIT; +}; + +struct st_system_mdmonr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short MD : 1; + unsigned short : 15; +#else + unsigned short : 15; + unsigned short MD : 1; +#endif +}; + +struct st_mpc_p12pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p12pfs +{ + unsigned char BYTE; + struct st_mpc_p12pfs_bit BIT; +}; + +struct st_mpc_p13pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p13pfs +{ + unsigned char BYTE; + struct st_mpc_p13pfs_bit BIT; +}; + +struct st_mpc_p14pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p14pfs +{ + unsigned char BYTE; + struct st_mpc_p14pfs_bit BIT; +}; + +struct st_mpc_p15pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p15pfs +{ + unsigned char BYTE; + struct st_mpc_p15pfs_bit BIT; +}; + +struct st_mpc_p16pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p16pfs +{ + unsigned char BYTE; + struct st_mpc_p16pfs_bit BIT; +}; + +struct st_mpc_p17pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p17pfs +{ + unsigned char BYTE; + struct st_mpc_p17pfs_bit BIT; +}; + +struct st_mpc_p20pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p20pfs +{ + unsigned char BYTE; + struct st_mpc_p20pfs_bit BIT; +}; + +struct st_mpc_p21pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p21pfs +{ + unsigned char BYTE; + struct st_mpc_p21pfs_bit BIT; +}; + +struct st_mpc_p22pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p22pfs +{ + unsigned char BYTE; + struct st_mpc_p22pfs_bit BIT; +}; + +struct st_mpc_p23pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p23pfs +{ + unsigned char BYTE; + struct st_mpc_p23pfs_bit BIT; +}; + +struct st_mpc_p24pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p24pfs +{ + unsigned char BYTE; + struct st_mpc_p24pfs_bit BIT; +}; + +struct st_mpc_p25pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p25pfs +{ + unsigned char BYTE; + struct st_mpc_p25pfs_bit BIT; +}; + +struct st_mpc_p26pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p26pfs +{ + unsigned char BYTE; + struct st_mpc_p26pfs_bit BIT; +}; + +struct st_mpc_p27pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p27pfs +{ + unsigned char BYTE; + struct st_mpc_p27pfs_bit BIT; +}; + +struct st_mpc_p30pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p30pfs +{ + unsigned char BYTE; + struct st_mpc_p30pfs_bit BIT; +}; + +struct st_mpc_p31pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p31pfs +{ + unsigned char BYTE; + struct st_mpc_p31pfs_bit BIT; +}; + +struct st_mpc_p32pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p32pfs +{ + unsigned char BYTE; + struct st_mpc_p32pfs_bit BIT; +}; + +struct st_mpc_p33pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p33pfs +{ + unsigned char BYTE; + struct st_mpc_p33pfs_bit BIT; +}; + +struct st_mpc_p34pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p34pfs +{ + unsigned char BYTE; + struct st_mpc_p34pfs_bit BIT; +}; + +struct st_mpc_p40pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_p40pfs +{ + unsigned char BYTE; + struct st_mpc_p40pfs_bit BIT; +}; + +struct st_mpc_p41pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_p41pfs +{ + unsigned char BYTE; + struct st_mpc_p41pfs_bit BIT; +}; + +struct st_mpc_p42pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_p42pfs +{ + unsigned char BYTE; + struct st_mpc_p42pfs_bit BIT; +}; + +struct st_mpc_p43pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_p43pfs +{ + unsigned char BYTE; + struct st_mpc_p43pfs_bit BIT; +}; + +struct st_mpc_p44pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_p44pfs +{ + unsigned char BYTE; + struct st_mpc_p44pfs_bit BIT; +}; + +struct st_mpc_p45pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_p45pfs +{ + unsigned char BYTE; + struct st_mpc_p45pfs_bit BIT; +}; + +struct st_mpc_p46pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_p46pfs +{ + unsigned char BYTE; + struct st_mpc_p46pfs_bit BIT; +}; + +struct st_mpc_p47pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_p47pfs +{ + unsigned char BYTE; + struct st_mpc_p47pfs_bit BIT; +}; + +struct st_mpc_p50pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p50pfs +{ + unsigned char BYTE; + struct st_mpc_p50pfs_bit BIT; +}; + +struct st_mpc_p51pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p51pfs +{ + unsigned char BYTE; + struct st_mpc_p51pfs_bit BIT; +}; + +struct st_mpc_p52pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p52pfs +{ + unsigned char BYTE; + struct st_mpc_p52pfs_bit BIT; +}; + +struct st_mpc_p54pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p54pfs +{ + unsigned char BYTE; + struct st_mpc_p54pfs_bit BIT; +}; + +struct st_mpc_p55pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p55pfs +{ + unsigned char BYTE; + struct st_mpc_p55pfs_bit BIT; +}; + +struct st_mpc_p56pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p56pfs +{ + unsigned char BYTE; + struct st_mpc_p56pfs_bit BIT; +}; + +struct st_mpc_p57pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p57pfs +{ + unsigned char BYTE; + struct st_mpc_p57pfs_bit BIT; +}; + +struct st_mpc_p66pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p66pfs +{ + unsigned char BYTE; + struct st_mpc_p66pfs_bit BIT; +}; + +struct st_mpc_p67pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p67pfs +{ + unsigned char BYTE; + struct st_mpc_p67pfs_bit BIT; +}; + +struct st_mpc_p71pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p71pfs +{ + unsigned char BYTE; + struct st_mpc_p71pfs_bit BIT; +}; + +struct st_mpc_p72pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p72pfs +{ + unsigned char BYTE; + struct st_mpc_p72pfs_bit BIT; +}; + +struct st_mpc_p73pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p73pfs +{ + unsigned char BYTE; + struct st_mpc_p73pfs_bit BIT; +}; + +struct st_mpc_p74pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p74pfs +{ + unsigned char BYTE; + struct st_mpc_p74pfs_bit BIT; +}; + +struct st_mpc_p75pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p75pfs +{ + unsigned char BYTE; + struct st_mpc_p75pfs_bit BIT; +}; + +struct st_mpc_p76pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p76pfs +{ + unsigned char BYTE; + struct st_mpc_p76pfs_bit BIT; +}; + +struct st_mpc_p77pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p77pfs +{ + unsigned char BYTE; + struct st_mpc_p77pfs_bit BIT; +}; + +struct st_mpc_p80pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p80pfs +{ + unsigned char BYTE; + struct st_mpc_p80pfs_bit BIT; +}; + +struct st_mpc_p81pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p81pfs +{ + unsigned char BYTE; + struct st_mpc_p81pfs_bit BIT; +}; + +struct st_mpc_p82pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p82pfs +{ + unsigned char BYTE; + struct st_mpc_p82pfs_bit BIT; +}; + +struct st_mpc_p83pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p83pfs +{ + unsigned char BYTE; + struct st_mpc_p83pfs_bit BIT; +}; + +struct st_mpc_p84pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p84pfs +{ + unsigned char BYTE; + struct st_mpc_p84pfs_bit BIT; +}; + +struct st_mpc_p85pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p85pfs +{ + unsigned char BYTE; + struct st_mpc_p85pfs_bit BIT; +}; + +struct st_mpc_p86pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p86pfs +{ + unsigned char BYTE; + struct st_mpc_p86pfs_bit BIT; +}; + +struct st_mpc_p87pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p87pfs +{ + unsigned char BYTE; + struct st_mpc_p87pfs_bit BIT; +}; + +struct st_mpc_p90pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p90pfs +{ + unsigned char BYTE; + struct st_mpc_p90pfs_bit BIT; +}; + +struct st_mpc_p91pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p91pfs +{ + unsigned char BYTE; + struct st_mpc_p91pfs_bit BIT; +}; + +struct st_mpc_p92pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p92pfs +{ + unsigned char BYTE; + struct st_mpc_p92pfs_bit BIT; +}; + +struct st_mpc_p93pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_p93pfs +{ + unsigned char BYTE; + struct st_mpc_p93pfs_bit BIT; +}; + +struct st_mpc_pa0pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pa0pfs +{ + unsigned char BYTE; + struct st_mpc_pa0pfs_bit BIT; +}; + +struct st_mpc_pa1pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pa1pfs +{ + unsigned char BYTE; + struct st_mpc_pa1pfs_bit BIT; +}; + +struct st_mpc_pa2pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pa2pfs +{ + unsigned char BYTE; + struct st_mpc_pa2pfs_bit BIT; +}; + +struct st_mpc_pa3pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pa3pfs +{ + unsigned char BYTE; + struct st_mpc_pa3pfs_bit BIT; +}; + +struct st_mpc_pa4pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pa4pfs +{ + unsigned char BYTE; + struct st_mpc_pa4pfs_bit BIT; +}; + +struct st_mpc_pa5pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pa5pfs +{ + unsigned char BYTE; + struct st_mpc_pa5pfs_bit BIT; +}; + +struct st_mpc_pa6pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; +union un_mpc_pa6pfs +{ + unsigned char BYTE; + struct st_mpc_pa6pfs_bit BIT; +}; + +struct st_mpc_pa7pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pa7pfs +{ + unsigned char BYTE; + struct st_mpc_pa7pfs_bit BIT; +}; + +struct st_mpc_pb0pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pb0pfs +{ + unsigned char BYTE; + struct st_mpc_pb0pfs_bit BIT; +}; + +struct st_mpc_pb1pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pb1pfs +{ + unsigned char BYTE; + struct st_mpc_pb1pfs_bit BIT; +}; + +struct st_mpc_pb2pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pb2pfs +{ + unsigned char BYTE; + struct st_mpc_pb2pfs_bit BIT; +}; + +struct st_mpc_pb3pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pb3pfs +{ + unsigned char BYTE; + struct st_mpc_pb3pfs_bit BIT; +}; + +struct st_mpc_pb4pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pb4pfs +{ + unsigned char BYTE; + struct st_mpc_pb4pfs_bit BIT; +}; + +struct st_mpc_pb5pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pb5pfs +{ + unsigned char BYTE; + struct st_mpc_pb5pfs_bit BIT; +}; + +struct st_mpc_pb6pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pb6pfs +{ + unsigned char BYTE; + struct st_mpc_pb6pfs_bit BIT; +}; + +struct st_mpc_pb7pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pb7pfs +{ + unsigned char BYTE; + struct st_mpc_pb7pfs_bit BIT; +}; + +struct st_mpc_pc0pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pc0pfs +{ + unsigned char BYTE; + struct st_mpc_pc0pfs_bit BIT; +}; + +struct st_mpc_pc1pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pc1pfs +{ + unsigned char BYTE; + struct st_mpc_pc1pfs_bit BIT; +}; + +struct st_mpc_pc2pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pc2pfs +{ + unsigned char BYTE; + struct st_mpc_pc2pfs_bit BIT; +}; + +struct st_mpc_pc3pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pc3pfs +{ + unsigned char BYTE; + struct st_mpc_pc3pfs_bit BIT; +}; + +struct st_mpc_pc4pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pc4pfs +{ + unsigned char BYTE; + struct st_mpc_pc4pfs_bit BIT; +}; + +struct st_mpc_pc5pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pc5pfs +{ + unsigned char BYTE; + struct st_mpc_pc5pfs_bit BIT; +}; + +struct st_mpc_pc6pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pc6pfs +{ + unsigned char BYTE; + struct st_mpc_pc6pfs_bit BIT; +}; + +struct st_mpc_pc7pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pc7pfs +{ + unsigned char BYTE; + struct st_mpc_pc7pfs_bit BIT; +}; + +struct st_mpc_pd0pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pd0pfs +{ + unsigned char BYTE; + struct st_mpc_pd0pfs_bit BIT; +}; + +struct st_mpc_pd1pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pd1pfs +{ + unsigned char BYTE; + struct st_mpc_pd1pfs_bit BIT; +}; + +struct st_mpc_pd2pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pd2pfs +{ + unsigned char BYTE; + struct st_mpc_pd2pfs_bit BIT; +}; + +struct st_mpc_pd3pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pd3pfs +{ + unsigned char BYTE; + struct st_mpc_pd3pfs_bit BIT; +}; + +struct st_mpc_pd4pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pd4pfs +{ + unsigned char BYTE; + struct st_mpc_pd4pfs_bit BIT; +}; + +struct st_mpc_pd5pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pd5pfs +{ + unsigned char BYTE; + struct st_mpc_pd5pfs_bit BIT; +}; + +struct st_mpc_pd6pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pd6pfs +{ + unsigned char BYTE; + struct st_mpc_pd6pfs_bit BIT; +}; + +struct st_mpc_pd7pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pd7pfs +{ + unsigned char BYTE; + struct st_mpc_pd7pfs_bit BIT; +}; + +struct st_mpc_pe0pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pe0pfs +{ + unsigned char BYTE; + struct st_mpc_pe0pfs_bit BIT; +}; + +struct st_mpc_pe1pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pe1pfs +{ + unsigned char BYTE; + struct st_mpc_pe1pfs_bit BIT; +}; + +struct st_mpc_pe2pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pe2pfs +{ + unsigned char BYTE; + struct st_mpc_pe2pfs_bit BIT; +}; + +struct st_mpc_pe3pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pe3pfs +{ + unsigned char BYTE; + struct st_mpc_pe3pfs_bit BIT; +}; + +struct st_mpc_pe4pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pe4pfs +{ + unsigned char BYTE; + struct st_mpc_pe4pfs_bit BIT; +}; + +struct st_mpc_pe5pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pe5pfs +{ + unsigned char BYTE; + struct st_mpc_pe5pfs_bit BIT; +}; + +struct st_mpc_pe6pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pe6pfs +{ + unsigned char BYTE; + struct st_mpc_pe6pfs_bit BIT; +}; + +struct st_mpc_pe7pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char ISEL : 1; + unsigned char ASEL : 1; +#else + unsigned char ASEL : 1; + unsigned char ISEL : 1; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pe7pfs +{ + unsigned char BYTE; + struct st_mpc_pe7pfs_bit BIT; +}; + +struct st_mpc_pf0pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pf0pfs +{ + unsigned char BYTE; + struct st_mpc_pf0pfs_bit BIT; +}; + +struct st_mpc_pf1pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pf1pfs +{ + unsigned char BYTE; + struct st_mpc_pf1pfs_bit BIT; +}; + +struct st_mpc_pf2pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pf2pfs +{ + unsigned char BYTE; + struct st_mpc_pf2pfs_bit BIT; +}; + +struct st_mpc_pf5pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 6; + unsigned char ISEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char ISEL : 1; + unsigned char : 6; +#endif +}; + +union un_mpc_pf5pfs +{ + unsigned char BYTE; + struct st_mpc_pf5pfs_bit BIT; +}; + +struct st_mpc_pj0pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pj0pfs +{ + unsigned char BYTE; + struct st_mpc_pj0pfs_bit BIT; +}; + +struct st_mpc_pj1pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pj1pfs +{ + unsigned char BYTE; + struct st_mpc_pj1pfs_bit BIT; +}; + +struct st_mpc_pj2pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pj2pfs +{ + unsigned char BYTE; + struct st_mpc_pj2pfs_bit BIT; +}; + +struct st_mpc_pj3pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pj3pfs +{ + unsigned char BYTE; + struct st_mpc_pj3pfs_bit BIT; +}; + +struct st_mpc_pj5pfs_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PSEL : 6; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char PSEL : 6; +#endif +}; + +union un_mpc_pj5pfs +{ + unsigned char BYTE; + struct st_mpc_pj5pfs_bit BIT; +}; + +union un_mdmonr +{ + unsigned short WORD; + struct st_system_mdmonr_bit BIT; +}; + +struct st_system_syscr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ROME : 1; + unsigned short EXBE : 1; + unsigned short : 6; + unsigned short KEY : 8; +#else + unsigned short KEY : 8; + unsigned short : 6; + unsigned short EXBE : 1; + unsigned short ROME : 1; +#endif +}; + +union un_syscr0 +{ + unsigned short WORD; + struct st_system_syscr0_bit BIT; +}; + +struct st_system_syscr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RAME : 1; + unsigned short : 6; + unsigned short SBYRAME : 1; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short SBYRAME : 1; + unsigned short : 6; + unsigned short RAME : 1; +#endif +}; + +union un_syscr1 +{ + unsigned short WORD; + struct st_system_syscr1_bit BIT; +}; + +struct st_system_sbycr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 14; + unsigned short OPE : 1; + unsigned short SSBY : 1; +#else + unsigned short SSBY : 1; + unsigned short OPE : 1; + unsigned short : 14; +#endif +}; + +union un_sbycr +{ + unsigned short WORD; + struct st_system_sbycr_bit BIT; +}; + +struct st_system_mstpcra_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPA0 : 1; + unsigned long MSTPA1 : 1; + unsigned long : 2; + unsigned long MSTPA4 : 1; + unsigned long MSTPA5 : 1; + unsigned long : 3; + unsigned long MSTPA9 : 1; + unsigned long MSTPA10 : 1; + unsigned long MSTPA11 : 1; + unsigned long : 1; + unsigned long MSTPA13 : 1; + unsigned long MSTPA14 : 1; + unsigned long MSTPA15 : 1; + unsigned long MSTPA16 : 1; + unsigned long MSTPA17 : 1; + unsigned long : 1; + unsigned long MSTPA19 : 1; + unsigned long : 4; + unsigned long MSTPA24 : 1; + unsigned long : 2; + unsigned long MSTPA27 : 1; + unsigned long MSTPA28 : 1; + unsigned long MSTPA29 : 1; + unsigned long : 1; + unsigned long ACSE : 1; +#else + unsigned long ACSE : 1; + unsigned long : 1; + unsigned long MSTPA29 : 1; + unsigned long MSTPA28 : 1; + unsigned long MSTPA27 : 1; + unsigned long : 2; + unsigned long MSTPA24 : 1; + unsigned long : 4; + unsigned long MSTPA19 : 1; + unsigned long : 1; + unsigned long MSTPA17 : 1; + unsigned long MSTPA16 : 1; + unsigned long MSTPA15 : 1; + unsigned long MSTPA14 : 1; + unsigned long MSTPA13 : 1; + unsigned long : 1; + unsigned long MSTPA11 : 1; + unsigned long MSTPA10 : 1; + unsigned long MSTPA9 : 1; + unsigned long : 3; + unsigned long MSTPA5 : 1; + unsigned long MSTPA4 : 1; + unsigned long : 2; + unsigned long MSTPA1 : 1; + unsigned long MSTPA0 : 1; +#endif +}; + +union un_mstpcra +{ + unsigned long LONG; + struct st_system_mstpcra_bit BIT; +}; + +struct st_system_mstpcrb_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPB0 : 1; + unsigned long MSTPB1 : 1; + unsigned long : 2; + unsigned long MSTPB4 : 1; + unsigned long : 1; + unsigned long MSTPB6 : 1; + unsigned long : 1; + unsigned long MSTPB8 : 1; + unsigned long MSTPB9 : 1; + unsigned long : 5; + unsigned long MSTPB15 : 1; + unsigned long MSTPB16 : 1; + unsigned long MSTPB17 : 1; + unsigned long : 1; + unsigned long MSTPB19 : 1; + unsigned long MSTPB20 : 1; + unsigned long MSTPB21 : 1; + unsigned long MSTPB22 : 1; + unsigned long MSTPB23 : 1; + unsigned long MSTPB24 : 1; + unsigned long MSTPB25 : 1; + unsigned long MSTPB26 : 1; + unsigned long MSTPB27 : 1; + unsigned long MSTPB28 : 1; + unsigned long MSTPB29 : 1; + unsigned long MSTPB30 : 1; + unsigned long MSTPB31 : 1; +#else + unsigned long MSTPB31 : 1; + unsigned long MSTPB30 : 1; + unsigned long MSTPB29 : 1; + unsigned long MSTPB28 : 1; + unsigned long MSTPB27 : 1; + unsigned long MSTPB26 : 1; + unsigned long MSTPB25 : 1; + unsigned long MSTPB24 : 1; + unsigned long MSTPB23 : 1; + unsigned long MSTPB22 : 1; + unsigned long MSTPB21 : 1; + unsigned long MSTPB20 : 1; + unsigned long MSTPB19 : 1; + unsigned long : 1; + unsigned long MSTPB17 : 1; + unsigned long MSTPB16 : 1; + unsigned long MSTPB15 : 1; + unsigned long : 5; + unsigned long MSTPB9 : 1; + unsigned long MSTPB8 : 1; + unsigned long : 1; + unsigned long MSTPB6 : 1; + unsigned long : 1; + unsigned long MSTPB4 : 1; + unsigned long : 2; + unsigned long MSTPB1 : 1; + unsigned long MSTPB0 : 1; +#endif +}; + +union un_mstpcrb +{ + unsigned long LONG; + struct st_system_mstpcrb_bit BIT; +}; + +struct st_system_mstpcrc_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPC0 : 1; + unsigned long : 1; + unsigned long MSTPC2 : 1; + unsigned long : 4; + unsigned long MSTPC7 : 1; + unsigned long : 9; + unsigned long MSTPC17 : 1; + unsigned long : 1; + unsigned long MSTPC19 : 1; + unsigned long : 2; + unsigned long MSTPC22 : 1; + unsigned long MSTPC23 : 1; + unsigned long MSTPC24 : 1; + unsigned long MSTPC25 : 1; + unsigned long MSTPC26 : 1; + unsigned long MSTPC27 : 1; + unsigned long MSTPC28 : 1; + unsigned long MSTPC29 : 1; + unsigned long : 2; +#else + unsigned long : 2; + unsigned long MSTPC29 : 1; + unsigned long MSTPC28 : 1; + unsigned long MSTPC27 : 1; + unsigned long MSTPC26 : 1; + unsigned long MSTPC25 : 1; + unsigned long MSTPC24 : 1; + unsigned long MSTPC23 : 1; + unsigned long MSTPC22 : 1; + unsigned long : 2; + unsigned long MSTPC19 : 1; + unsigned long : 1; + unsigned long MSTPC17 : 1; + unsigned long : 9; + unsigned long MSTPC7 : 1; + unsigned long : 4; + unsigned long MSTPC2 : 1; + unsigned long : 1; + unsigned long MSTPC0 : 1; +#endif +}; + +union un_mstpcrc +{ + unsigned long LONG; + struct st_system_mstpcrc_bit BIT; +}; + +struct st_system_mstpcrd_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long MSTPD0 : 1; + unsigned long MSTPD1 : 1; + unsigned long MSTPD2 : 1; + unsigned long MSTPD3 : 1; + unsigned long MSTPD4 : 1; + unsigned long MSTPD5 : 1; + unsigned long MSTPD6 : 1; + unsigned long MSTPD7 : 1; + unsigned long : 5; + unsigned long MSTPD13 : 1; + unsigned long : 5; + unsigned long MSTPD19 : 1; + unsigned long : 1; + unsigned long MSTPD21 : 1; + unsigned long : 5; + unsigned long MSTPD27 : 1; + unsigned long : 4; +#else + unsigned long : 4; + unsigned long MSTPD27 : 1; + unsigned long : 5; + unsigned long MSTPD21 : 1; + unsigned long : 1; + unsigned long MSTPD19 : 1; + unsigned long : 5; + unsigned long MSTPD13 : 1; + unsigned long : 5; + unsigned long MSTPD7 : 1; + unsigned long MSTPD6 : 1; + unsigned long MSTPD5 : 1; + unsigned long MSTPD4 : 1; + unsigned long MSTPD3 : 1; + unsigned long MSTPD2 : 1; + unsigned long MSTPD1 : 1; + unsigned long MSTPD0 : 1; +#endif +}; + +union un_mstpcrd +{ + unsigned long LONG; + struct st_system_mstpcrd_bit BIT; +}; + +struct st_system_sckcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned long PCKD : 4; + unsigned long PCKC : 4; + unsigned long PCKB : 4; + unsigned long PCKA : 4; + unsigned long BCK : 4; + unsigned long : 2; + unsigned long PSTOP0 : 1; + unsigned long PSTOP1 : 1; + unsigned long ICK : 4; + unsigned long FCK : 4; +#else + unsigned long FCK : 4; + unsigned long ICK : 4; + unsigned long PSTOP1 : 1; + unsigned long PSTOP0 : 1; + unsigned long : 2; + unsigned long BCK : 4; + unsigned long PCKA : 4; + unsigned long PCKB : 4; + unsigned long PCKC : 4; + unsigned long PCKD : 4; +#endif +}; + +union un_sckcr +{ + unsigned long LONG; + struct st_system_sckcr_bit BIT; +}; + +struct st_system_sckcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 4; + unsigned short UCK : 4; + unsigned short : 8; +#else + unsigned short : 8; + unsigned short UCK : 4; + unsigned short : 4; +#endif +}; + +union un_sckcr2 +{ + unsigned short WORD; + struct st_system_sckcr2_bit BIT; +}; + +struct st_system_sckcr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short : 8; + unsigned short CKSEL : 3; + unsigned short : 5; +#else + unsigned short : 5; + unsigned short CKSEL : 3; + unsigned short : 8; +#endif +}; + +union un_sckcr3 +{ + unsigned short WORD; + struct st_system_sckcr3_bit BIT; +}; + +struct st_system_pllcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PLIDIV : 2; + unsigned short : 2; + unsigned short PLLSRCSEL : 1; + unsigned short : 3; + unsigned short STC : 6; + unsigned short : 2; +#else + unsigned short : 2; + unsigned short STC : 6; + unsigned short : 3; + unsigned short PLLSRCSEL : 1; + unsigned short : 2; + unsigned short PLIDIV : 2; +#endif +}; + +union un_pllcr +{ + unsigned short WORD; + struct st_system_pllcr_bit BIT; +}; + +struct st_system_pllcr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PLLEN : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char PLLEN : 1; +#endif +}; + +union un_pllcr2 +{ + unsigned char BYTE; + struct st_system_pllcr2_bit BIT; +}; + +struct st_system_bckcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BCLKDIV : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char BCLKDIV : 1; +#endif +}; + +union un_bckcr +{ + unsigned char BYTE; + struct st_system_bckcr_bit BIT; +}; + +struct st_system_mosccr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char MOSTP : 1; +#endif +}; + +union un_mosccr +{ + unsigned char BYTE; + struct st_system_mosccr_bit BIT; +}; + +struct st_system_sosccr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SOSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SOSTP : 1; +#endif +}; + +union un_sosccr +{ + unsigned char BYTE; + struct st_system_sosccr_bit BIT; +}; + +struct st_system_lococcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char LCSTP : 1; +#endif +}; + +union un_lococr +{ + unsigned char BYTE; + struct st_system_lococcr_bit BIT; +}; + +struct st_system_ilococr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ILCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ILCSTP : 1; +#endif +}; + +union un_ilococr +{ + unsigned char BYTE; + struct st_system_ilococr_bit BIT; +}; + +struct st_system_hococr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HCSTP : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char HCSTP : 1; +#endif +}; + +union un_hococr +{ + unsigned char BYTE; + struct st_system_hococr_bit BIT; +}; + +struct st_system_hococr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HCFRQ : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char HCFRQ : 2; +#endif +}; + +union un_hococr2 +{ + unsigned char BYTE; + struct st_system_hococr2_bit BIT; +}; + +struct st_system_oscovfsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOOVF : 1; + unsigned char SOOVF : 1; + unsigned char PLOVF : 1; + unsigned char HCOVF : 1; + unsigned char ILCOVF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char ILCOVF : 1; + unsigned char HCOVF : 1; + unsigned char PLOVF : 1; + unsigned char SOOVF : 1; + unsigned char MOOVF : 1; +#endif +}; + +union un_oscovfsr +{ + unsigned char BYTE; + struct st_system_oscovfsr_bit BIT; +}; + +struct st_system_ostdcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSTDIE : 1; + unsigned char : 6; + unsigned char OSTDE : 1; +#else + unsigned char OSTDE : 1; + unsigned char : 6; + unsigned char OSTDIE : 1; +#endif +}; + +union un_ostdcr +{ + unsigned char BYTE; + struct st_system_ostdcr_bit BIT; +}; + +struct st_system_ostdsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OSTDF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char OSTDF : 1; +#endif +}; + +union un_ostdsr +{ + unsigned char BYTE; + struct st_system_ostdsr_bit BIT; +}; + +struct st_system_opccr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char OPCM : 3; + unsigned char : 1; + unsigned char OPCMTSF : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char OPCMTSF : 1; + unsigned char : 1; + unsigned char OPCM : 3; +#endif +}; + +struct st_system_rstckcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RSTCKSEL : 3; + unsigned char : 4; + unsigned char RSTCKEN : 1; +#else + unsigned char RSTCKEN : 1; + unsigned char : 4; + unsigned char RSTCKSEL : 3; +#endif +}; + +union un_rstckcr +{ + unsigned char BYTE; + struct st_system_rstckcr_bit BIT; +}; + +union un_opccr +{ + unsigned char BYTE; + struct st_system_opccr_bit BIT; +}; + +struct st_system_moscwtcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MSTS : 8; +#else + unsigned char MSTS : 8; +#endif +}; + +union un_moscwtcr +{ + unsigned char BYTE; + struct st_system_moscwtcr_bit BIT; +}; + +struct st_system_soscwtcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSTS : 8; +#else + unsigned char SSTS : 8; +#endif +}; + +union un_soscwtcr +{ + unsigned char BYTE; + struct st_system_soscwtcr_bit BIT; +}; + +struct st_system_rstsr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IWDTRF : 1; + unsigned char WDTRF : 1; + unsigned char SWRF : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SWRF : 1; + unsigned char WDTRF : 1; + unsigned char IWDTRF : 1; +#endif +}; + +union un_rstsr2 +{ + unsigned char BYTE; + struct st_system_rstsr2_bit BIT; +}; + +struct st_system_lvd1cr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1IDTSEL : 2; + unsigned char LVD1IRQSEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LVD1IRQSEL : 1; + unsigned char LVD1IDTSEL : 2; +#endif +}; + +union un_lvd1cr1 +{ + unsigned char BYTE; + struct st_system_lvd1cr1_bit BIT; +}; + +struct st_system_lvd1sr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1DET : 1; + unsigned char LVD1MON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LVD1MON : 1; + unsigned char LVD1DET : 1; +#endif +}; + +union un_lvd1sr +{ + unsigned char BYTE; + struct st_system_lvd1sr_bit BIT; +}; + +struct st_system_lvd2cr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2IDTSEL : 2; + unsigned char LVD2IRQSEL : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char LVD2IRQSEL : 1; + unsigned char LVD2IDTSEL : 2; +#endif +}; + +union un_lvd2cr1 +{ + unsigned char BYTE; + struct st_system_lvd2cr1_bit BIT; +}; + +struct st_system_lvd2sr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2DET : 1; + unsigned char LVD2MON : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char LVD2MON : 1; + unsigned char LVD2DET : 1; +#endif +}; + +union un_lvd2sr +{ + unsigned char BYTE; + struct st_system_lvd2sr_bit BIT; +}; + +struct st_system_prcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short PRC0 : 1; + unsigned short PRC1 : 1; + unsigned short : 1; + unsigned short PRC3 : 1; + unsigned short : 4; + unsigned short PRKEY : 8; +#else + unsigned short PRKEY : 8; + unsigned short : 4; + unsigned short PRC3 : 1; + unsigned short : 1; + unsigned short PRC1 : 1; + unsigned short PRC0 : 1; +#endif +}; + +union un_prcr +{ + unsigned short WORD; + struct st_system_prcr_bit BIT; +}; + +struct st_system_romwt_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ROMWT : 2; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char ROMWT : 2; +#endif +}; + +union un_romwt +{ + unsigned char BYTE; + struct st_system_romwt_bit BIT; +}; + +struct st_system_dpsbycr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DEEPCUT : 2; + unsigned char : 4; + unsigned char IOKEEP : 1; + unsigned char DPSBY : 1; +#else + unsigned char DPSBY : 1; + unsigned char IOKEEP : 1; + unsigned char : 4; + unsigned char DEEPCUT : 2; +#endif +}; + +union un_dpsbycr +{ + unsigned char BYTE; + struct st_system_dpsbycr_bit BIT; +}; + +struct st_system_dpsier0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ0E : 1; + unsigned char DIRQ1E : 1; + unsigned char DIRQ2E : 1; + unsigned char DIRQ3E : 1; + unsigned char DIRQ4E : 1; + unsigned char DIRQ5E : 1; + unsigned char DIRQ6E : 1; + unsigned char DIRQ7E : 1; +#else + unsigned char DIRQ7E : 1; + unsigned char DIRQ6E : 1; + unsigned char DIRQ5E : 1; + unsigned char DIRQ4E : 1; + unsigned char DIRQ3E : 1; + unsigned char DIRQ2E : 1; + unsigned char DIRQ1E : 1; + unsigned char DIRQ0E : 1; +#endif +}; + +union un_dpsier0 +{ + unsigned char BYTE; + struct st_system_dpsier0_bit BIT; +}; + +struct st_system_dpsier1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ8E : 1; + unsigned char DIRQ9E : 1; + unsigned char DIRQ10E : 1; + unsigned char DIRQ11E : 1; + unsigned char DIRQ12E : 1; + unsigned char DIRQ13E : 1; + unsigned char DIRQ14E : 1; + unsigned char DIRQ15E : 1; +#else + unsigned char DIRQ15E : 1; + unsigned char DIRQ14E : 1; + unsigned char DIRQ13E : 1; + unsigned char DIRQ12E : 1; + unsigned char DIRQ11E : 1; + unsigned char DIRQ10E : 1; + unsigned char DIRQ9E : 1; + unsigned char DIRQ8E : 1; +#endif +}; + +union un_dpsier1 +{ + unsigned char BYTE; + struct st_system_dpsier1_bit BIT; +}; + +struct st_system_dpsier2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DLVD1IE : 1; + unsigned char DLVD2IE : 1; + unsigned char DRTCIIE : 1; + unsigned char DRTCAIE : 1; + unsigned char DNMIE : 1; + unsigned char DRIICDIE : 1; + unsigned char DRIICCIE : 1; + unsigned char DUSBIE : 1; +#else + unsigned char DUSBIE : 1; + unsigned char DRIICCIE : 1; + unsigned char DRIICDIE : 1; + unsigned char DNMIE : 1; + unsigned char DRTCAIE : 1; + unsigned char DRTCIIE : 1; + unsigned char DLVD2IE : 1; + unsigned char DLVD1IE : 1; +#endif +}; + +union un_dpsier2 +{ + unsigned char BYTE; + struct st_system_dpsier2_bit BIT; +}; + +struct st_system_dpsier3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DCANIE : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DCANIE : 1; +#endif +}; + +union un_dpsier3 +{ + unsigned char BYTE; + struct st_system_dpsier3_bit BIT; +}; + +struct st_system_dpsifr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ0F : 1; + unsigned char DIRQ1F : 1; + unsigned char DIRQ2F : 1; + unsigned char DIRQ3F : 1; + unsigned char DIRQ4F : 1; + unsigned char DIRQ5F : 1; + unsigned char DIRQ6F : 1; + unsigned char DIRQ7F : 1; +#else + unsigned char DIRQ7F : 1; + unsigned char DIRQ6F : 1; + unsigned char DIRQ5F : 1; + unsigned char DIRQ4F : 1; + unsigned char DIRQ3F : 1; + unsigned char DIRQ2F : 1; + unsigned char DIRQ1F : 1; + unsigned char DIRQ0F : 1; +#endif +}; + +union un_dpsifr0 +{ + unsigned char BYTE; + struct st_system_dpsifr0_bit BIT; +}; + +struct st_system_dpsifr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ8F : 1; + unsigned char DIRQ9F : 1; + unsigned char DIRQ10F : 1; + unsigned char DIRQ11F : 1; + unsigned char DIRQ12F : 1; + unsigned char DIRQ13F : 1; + unsigned char DIRQ14F : 1; + unsigned char DIRQ15F : 1; +#else + unsigned char DIRQ15F : 1; + unsigned char DIRQ14F : 1; + unsigned char DIRQ13F : 1; + unsigned char DIRQ12F : 1; + unsigned char DIRQ11F : 1; + unsigned char DIRQ10F : 1; + unsigned char DIRQ9F : 1; + unsigned char DIRQ8F : 1; +#endif +}; + +union un_dpsifr1 +{ + unsigned char BYTE; + struct st_system_dpsifr1_bit BIT; +}; + +struct st_system_dpsifr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DLVD1IF : 1; + unsigned char DLVD2IF : 1; + unsigned char DRTCIIF : 1; + unsigned char DRTCAIF : 1; + unsigned char DNMIF : 1; + unsigned char DRIICDIF : 1; + unsigned char DRIICCIF : 1; + unsigned char DUSBIF : 1; +#else + unsigned char DUSBIF : 1; + unsigned char DRIICCIF : 1; + unsigned char DRIICDIF : 1; + unsigned char DNMIF : 1; + unsigned char DRTCAIF : 1; + unsigned char DRTCIIF : 1; + unsigned char DLVD2IF : 1; + unsigned char DLVD1IF : 1; +#endif +}; + +union un_dpsifr2 +{ + unsigned char BYTE; + struct st_system_dpsifr2_bit BIT; +}; + +struct st_system_dpsifr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DCANIF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DCANIF : 1; +#endif +}; + +union un_dpsifr3 +{ + unsigned char BYTE; + struct st_system_dpsifr3_bit BIT; +}; + +struct st_system_dpsiegr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ0EG : 1; + unsigned char DIRQ1EG : 1; + unsigned char DIRQ2EG : 1; + unsigned char DIRQ3EG : 1; + unsigned char DIRQ4EG : 1; + unsigned char DIRQ5EG : 1; + unsigned char DIRQ6EG : 1; + unsigned char DIRQ7EG : 1; +#else + unsigned char DIRQ7EG : 1; + unsigned char DIRQ6EG : 1; + unsigned char DIRQ5EG : 1; + unsigned char DIRQ4EG : 1; + unsigned char DIRQ3EG : 1; + unsigned char DIRQ2EG : 1; + unsigned char DIRQ1EG : 1; + unsigned char DIRQ0EG : 1; +#endif +}; + +union un_dpsiegr0 +{ + unsigned char BYTE; + struct st_system_dpsiegr0_bit BIT; +}; + +struct st_system_dpsiegr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DIRQ8EG : 1; + unsigned char DIRQ9EG : 1; + unsigned char DIRQ10EG : 1; + unsigned char DIRQ11EG : 1; + unsigned char DIRQ12EG : 1; + unsigned char DIRQ13EG : 1; + unsigned char DIRQ14EG : 1; + unsigned char DIRQ15EG : 1; +#else + unsigned char DIRQ15EG : 1; + unsigned char DIRQ14EG : 1; + unsigned char DIRQ13EG : 1; + unsigned char DIRQ12EG : 1; + unsigned char DIRQ11EG : 1; + unsigned char DIRQ10EG : 1; + unsigned char DIRQ9EG : 1; + unsigned char DIRQ8EG : 1; +#endif +}; + +union un_dpsiegr1 +{ + unsigned char BYTE; + struct st_system_dpsiegr1_bit BIT; +}; + +struct st_system_dpsiegr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DLVD1EG : 1; + unsigned char DLVD2EG : 1; + unsigned char : 2; + unsigned char DNMIEG : 1; + unsigned char DRIICDEG : 1; + unsigned char DRIICCEG : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char DRIICCEG : 1; + unsigned char DRIICDEG : 1; + unsigned char DNMIEG : 1; + unsigned char : 2; + unsigned char DLVD2EG : 1; + unsigned char DLVD1EG : 1; +#endif +}; + +union un_dpsiegr2 +{ + unsigned char BYTE; + struct st_system_dpsiegr2_bit BIT; +}; + +struct st_system_dpsiegr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DCANIEG : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char DCANIEG : 1; +#endif +}; + +union un_dpsiegr3 +{ + unsigned char BYTE; + struct st_system_dpsiegr3_bit BIT; +}; + +struct st_system_rstsr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char PORF : 1; + unsigned char LVD0RF : 1; + unsigned char LVD1RF : 1; + unsigned char LVD2RF : 1; + unsigned char : 3; + unsigned char DPSRSTF : 1; +#else + unsigned char DPSRSTF : 1; + unsigned char : 3; + unsigned char LVD2RF : 1; + unsigned char LVD1RF : 1; + unsigned char LVD0RF : 1; + unsigned char PORF : 1; +#endif +}; + +union un_rstsr0 +{ + unsigned char BYTE; + struct st_system_rstsr0_bit BIT; +}; + +struct st_system_rstr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CWSF : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char CWSF : 1; +#endif +}; + +union un_rstsr1 +{ + unsigned char BYTE; + struct st_system_rstr1_bit BIT; +}; + +struct st_system_mofcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MOFXIN : 1; + unsigned char : 3; + unsigned char MODRV2 : 2; + unsigned char MOSEL : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char MOSEL : 1; + unsigned char MODRV2 : 2; + unsigned char : 3; + unsigned char MOFXIN : 1; +#endif +}; + +union un_mofcr +{ + unsigned char BYTE; + struct st_system_mofcr_bit BIT; +}; + +struct st_system_hocopcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char HOCOPCNT : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char HOCOPCNT : 1; +#endif +}; + +union un_hocopcr +{ + unsigned char BYTE; + struct st_system_hocopcr_bit BIT; +}; + +struct st_system_lvcmpcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 5; + unsigned char LVD1E : 1; + unsigned char LVD2E : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char LVD2E : 1; + unsigned char LVD1E : 1; + unsigned char : 5; +#endif +}; + +union un_lvcmpcr +{ + unsigned char BYTE; + struct st_system_lvcmpcr_bit BIT; +}; + +struct st_system_lvdlvlr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1LVL : 4; + unsigned char LVD2LVL : 4; +#else + unsigned char LVD2LVL : 4; + unsigned char LVD1LVL : 4; +#endif +}; + +union un_lvdlvlr +{ + unsigned char BYTE; + struct st_system_lvdlvlr_bit BIT; +}; + +struct st_system_lvd1cr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD1RIE : 1; + unsigned char LVD1DFDIS : 1; + unsigned char LVD1CMPE : 1; + unsigned char : 1; + unsigned char LVD1FSAMP : 2; + unsigned char LVD1RI : 1; + unsigned char LVD1RN : 1; +#else + unsigned char LVD1RN : 1; + unsigned char LVD1RI : 1; + unsigned char LVD1FSAMP : 2; + unsigned char : 1; + unsigned char LVD1CMPE : 1; + unsigned char LVD1DFDIS : 1; + unsigned char LVD1RIE : 1; +#endif +}; + +union un_lvd1cr0 +{ + unsigned char BYTE; + struct st_system_lvd1cr0_bit BIT; +}; + +struct st_system_lvd2cr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char LVD2RIE : 1; + unsigned char LVD2DFDIS : 1; + unsigned char LVD2CMPE : 1; + unsigned char : 1; + unsigned char LVD2FSAMP : 2; + unsigned char LVD2RI : 1; + unsigned char LVD2RN : 1; +#else + unsigned char LVD2RN : 1; + unsigned char LVD2RI : 1; + unsigned char LVD2FSAMP : 2; + unsigned char : 1; + unsigned char LVD2CMPE : 1; + unsigned char LVD2DFDIS : 1; + unsigned char LVD2RIE : 1; +#endif +}; + +union un_lvd2cr0 +{ + unsigned char BYTE; + struct st_system_lvd2cr0_bit BIT; +}; + +struct st_rtc_rcr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RTCEN : 1; + unsigned char RTCDV : 3; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char RTCDV : 3; + unsigned char RTCEN : 1; +#endif +}; + +union un_rcr3 +{ + unsigned char BYTE; + struct st_rtc_rcr3_bit BIT; +}; + +struct st_port0_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_pdr +{ + unsigned char BYTE; + struct st_port0_pdr_bit BIT; +}; + +struct st_port0_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_podr +{ + unsigned char BYTE; + struct st_port0_podr_bit BIT; +}; + +struct st_port0_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_pidr +{ + unsigned char BYTE; + struct st_port0_pidr_bit BIT; +}; + +struct st_port0_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_pmr +{ + unsigned char BYTE; + struct st_port0_pmr_bit BIT; +}; + +struct st_port0_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_odr0 +{ + unsigned char BYTE; + struct st_port0_odr0_bit BIT; +}; + +struct st_port0_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char : 3; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 3; + unsigned char B2 : 1; + unsigned char : 2; +#endif +}; + +union un_odr1 +{ + unsigned char BYTE; + struct st_port0_odr1_bit BIT; +}; + +struct st_port0_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_pcr +{ + unsigned char BYTE; + struct st_port0_pcr_bit BIT; +}; + +struct st_port0_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_dscr +{ + unsigned char BYTE; + struct st_port0_dscr_bit BIT; +}; + +struct st_port0_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_dscr2 +{ + unsigned char BYTE; + struct st_port0_dscr2_bit BIT; +}; + +struct st_port1_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port1_pdr +{ + unsigned char BYTE; + struct st_port1_pdr_bit BIT; +}; + +struct st_port1_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port1_podr +{ + unsigned char BYTE; + struct st_port1_podr_bit BIT; +}; + +struct st_port1_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port1_pidr +{ + unsigned char BYTE; + struct st_port1_pidr_bit BIT; +}; + +struct st_port1_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port1_pmr +{ + unsigned char BYTE; + struct st_port1_pmr_bit BIT; +}; + +struct st_port1_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port1_odr0 +{ + unsigned char BYTE; + struct st_port1_odr0_bit BIT; +}; + +struct st_port1_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port1_odr1 +{ + unsigned char BYTE; + struct st_port1_odr1_bit BIT; +}; + +struct st_port1_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port1_pcr +{ + unsigned char BYTE; + struct st_port1_pcr_bit BIT; +}; + +struct st_port1_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char : 1; +#endif +}; + +union un_port1_dscr +{ + unsigned char BYTE; + struct st_port1_dscr_bit BIT; +}; + +struct st_port1_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 2; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 2; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char : 1; +#endif +}; + +union un_port1_dscr2 +{ + unsigned char BYTE; + struct st_port1_dscr2_bit BIT; +}; + +struct st_port2_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port2_pdr +{ + unsigned char BYTE; + struct st_port2_pdr_bit BIT; +}; + +struct st_port2_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port2_podr +{ + unsigned char BYTE; + struct st_port2_podr_bit BIT; +}; + +struct st_port2_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port2_pidr +{ + unsigned char BYTE; + struct st_port2_pidr_bit BIT; +}; + +struct st_port2_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port2_pmr +{ + unsigned char BYTE; + struct st_port2_pmr_bit BIT; +}; + +struct st_port2_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port2_odr0 +{ + unsigned char BYTE; + struct st_port2_odr0_bit BIT; +}; + +struct st_port2_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port2_odr1 +{ + unsigned char BYTE; + struct st_port2_odr1_bit BIT; +}; + +struct st_port2_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port2_pcr +{ + unsigned char BYTE; + struct st_port2_pcr_bit BIT; +}; + +struct st_port2_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 7; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 7; +#endif +}; + +union un_port2_dscr +{ + unsigned char BYTE; + struct st_port2_dscr_bit BIT; +}; + +struct st_port2_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 3; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 3; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port2_dscr2 +{ + unsigned char BYTE; + struct st_port2_dscr2_bit BIT; +}; + +struct st_port3_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port3_pdr +{ + unsigned char BYTE; + struct st_port3_pdr_bit BIT; +}; + +struct st_port3_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port3_podr +{ + unsigned char BYTE; + struct st_port3_podr_bit BIT; +}; + +struct st_port3_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port3_pidr +{ + unsigned char BYTE; + struct st_port3_pidr_bit BIT; +}; + +struct st_port3_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port3_pmr +{ + unsigned char BYTE; + struct st_port3_pmr_bit BIT; +}; + +struct st_port3_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port3_odr0 +{ + unsigned char BYTE; + struct st_port3_odr0_bit BIT; +}; + +struct st_port3_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 3; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 3; + unsigned char BT0 : 1; +#endif +}; + +union un_port3_odr1 +{ + unsigned char BYTE; + struct st_port3_odr1_bit BIT; +}; + +struct st_port3_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port3_pcr +{ + unsigned char BYTE; + struct st_port3_pcr_bit BIT; +}; + +struct st_port3_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port3_dscr2 +{ + unsigned char BYTE; + struct st_port3_dscr2_bit BIT; +}; + +struct st_port5_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port5_pdr +{ + unsigned char BYTE; + struct st_port5_pdr_bit BIT; +}; + +struct st_port5_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port5_podr +{ + unsigned char BYTE; + struct st_port5_podr_bit BIT; +}; + +struct st_port5_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port5_pidr +{ + unsigned char BYTE; + struct st_port5_pidr_bit BIT; +}; + +struct st_port5_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port5_pmr +{ + unsigned char BYTE; + struct st_port5_pmr_bit BIT; +}; + +struct st_port5_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port5_odr0 +{ + unsigned char BYTE; + struct st_port5_odr0_bit BIT; +}; + +struct st_port5_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port5_odr1 +{ + unsigned char BYTE; + struct st_port5_odr1_bit BIT; +}; + +struct st_port5_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port5_pcr +{ + unsigned char BYTE; + struct st_port5_pcr_bit BIT; +}; + +struct st_port5_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port5_dscr +{ + unsigned char BYTE; + struct st_port5_dscr_bit BIT; +}; + +struct st_port5_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port5_dscr2 +{ + unsigned char BYTE; + struct st_port5_dscr2_bit BIT; +}; + +struct st_port7_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port7_pdr +{ + unsigned char BYTE; + struct st_port7_pdr_bit BIT; +}; + +struct st_port7_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port7_podr +{ + unsigned char BYTE; + struct st_port7_podr_bit BIT; +}; + +struct st_port7_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port7_pidr +{ + unsigned char BYTE; + struct st_port7_pidr_bit BIT; +}; + +struct st_port7_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port7_pmr +{ + unsigned char BYTE; + struct st_port7_pmr_bit BIT; +}; + +struct st_port7_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port7_odr0 +{ + unsigned char BYTE; + struct st_port7_odr0_bit BIT; +}; + +struct st_port7_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port7_odr1 +{ + unsigned char BYTE; + struct st_port7_odr1_bit BIT; +}; + +struct st_port7_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port7_pcr +{ + unsigned char BYTE; + struct st_port7_pcr_bit BIT; +}; + +struct st_port7_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 2; +#endif +}; + +union un_port7_dscr +{ + unsigned char BYTE; + struct st_port7_dscr_bit BIT; +}; + +struct st_port7_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port7_dscr2 +{ + unsigned char BYTE; + struct st_port7_dscr2_bit BIT; +}; + +struct st_port8_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port8_pdr +{ + unsigned char BYTE; + struct st_port8_pdr_bit BIT; +}; + +struct st_port8_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port8_podr +{ + unsigned char BYTE; + struct st_port8_podr_bit BIT; +}; + +struct st_port8_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port8_pidr +{ + unsigned char BYTE; + struct st_port8_pidr_bit BIT; +}; + +struct st_port8_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port8_pmr +{ + unsigned char BYTE; + struct st_port8_pmr_bit BIT; +}; + +struct st_port8_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port8_odr0 +{ + unsigned char BYTE; + struct st_port8_odr0_bit BIT; +}; + +struct st_port8_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port8_odr1 +{ + unsigned char BYTE; + struct st_port8_odr1_bit BIT; +}; + +struct st_port8_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port8_pcr +{ + unsigned char BYTE; + struct st_port8_pcr_bit BIT; +}; + +struct st_port8_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port8_dscr +{ + unsigned char BYTE; + struct st_port8_dscr_bit BIT; +}; + +struct st_port8_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port8_dscr2 +{ + unsigned char BYTE; + struct st_port8_dscr2_bit BIT; +}; + +struct st_port9_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port9_pdr +{ + unsigned char BYTE; + struct st_port9_pdr_bit BIT; +}; + +struct st_port9_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port9_podr +{ + unsigned char BYTE; + struct st_port9_podr_bit BIT; +}; + +struct st_port9_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port9_pidr +{ + unsigned char BYTE; + struct st_port9_pidr_bit BIT; +}; + +struct st_port9_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port9_pmr +{ + unsigned char BYTE; + struct st_port9_pmr_bit BIT; +}; + +struct st_port9_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port9_odr0 +{ + unsigned char BYTE; + struct st_port9_odr0_bit BIT; +}; + +struct st_port9_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port9_odr1 +{ + unsigned char BYTE; + struct st_port9_odr1_bit BIT; +}; + +struct st_port9_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port9_pcr +{ + unsigned char BYTE; + struct st_port9_pcr_bit BIT; +}; + +struct st_port9_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port9_dscr +{ + unsigned char BYTE; + struct st_port9_dscr_bit BIT; +}; + +struct st_port9_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_port9_dscr2 +{ + unsigned char BYTE; + struct st_port9_dscr2_bit BIT; +}; + +struct st_porta_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porta_pdr +{ + unsigned char BYTE; + struct st_porta_pdr_bit BIT; +}; + +struct st_porta_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porta_podr +{ + unsigned char BYTE; + struct st_porta_podr_bit BIT; +}; + +struct st_porta_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porta_pidr +{ + unsigned char BYTE; + struct st_porta_pidr_bit BIT; +}; + +struct st_porta_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porta_pmr +{ + unsigned char BYTE; + struct st_porta_pmr_bit BIT; +}; + +struct st_porta_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porta_odr0 +{ + unsigned char BYTE; + struct st_porta_odr0_bit BIT; +}; + +struct st_porta_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porta_odr1 +{ + unsigned char BYTE; + struct st_porta_odr1_bit BIT; +}; + +struct st_porta_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porta_pcr +{ + unsigned char BYTE; + struct st_porta_pcr_bit BIT; +}; + +struct st_porta_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porta_dscr +{ + unsigned char BYTE; + struct st_porta_dscr_bit BIT; +}; + +struct st_porta_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porta_dscr2 +{ + unsigned char BYTE; + struct st_porta_dscr2_bit BIT; +}; + +struct st_portb_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portb_pdr +{ + unsigned char BYTE; + struct st_portb_pdr_bit BIT; +}; + +struct st_portb_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portb_podr +{ + unsigned char BYTE; + struct st_portb_podr_bit BIT; +}; + +struct st_portb_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portb_pidr +{ + unsigned char BYTE; + struct st_portb_pidr_bit BIT; +}; + +struct st_portb_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portb_pmr +{ + unsigned char BYTE; + struct st_portb_pmr_bit BIT; +}; + +struct st_portb_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portb_odr0 +{ + unsigned char BYTE; + struct st_portb_odr0_bit BIT; +}; + +struct st_portb_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portb_odr1 +{ + unsigned char BYTE; + struct st_portb_odr1_bit BIT; +}; + +struct st_portb_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portb_pcr +{ + unsigned char BYTE; + struct st_portb_pcr_bit BIT; +}; + +struct st_portb_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portb_dscr +{ + unsigned char BYTE; + struct st_portb_dscr_bit BIT; +}; + +struct st_portb_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portb_dscr2 +{ + unsigned char BYTE; + struct st_portb_dscr2_bit BIT; +}; + +struct st_portc_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portc_pdr +{ + unsigned char BYTE; + struct st_portc_pdr_bit BIT; +}; + +struct st_portc_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portc_podr +{ + unsigned char BYTE; + struct st_portc_podr_bit BIT; +}; + +struct st_portc_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portc_pidr +{ + unsigned char BYTE; + struct st_portc_pidr_bit BIT; +}; + +struct st_portc_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portc_pmr +{ + unsigned char BYTE; + struct st_portc_pmr_bit BIT; +}; + +struct st_portc_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portc_odr0 +{ + unsigned char BYTE; + struct st_portc_odr0_bit BIT; +}; + +struct st_portc_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portc_odr1 +{ + unsigned char BYTE; + struct st_portc_odr1_bit BIT; +}; + +struct st_portc_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portc_pcr +{ + unsigned char BYTE; + struct st_portc_pcr_bit BIT; +}; + +struct st_portc_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portc_dscr +{ + unsigned char BYTE; + struct st_portc_dscr_bit BIT; +}; + +struct st_portc_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portc_dscr2 +{ + unsigned char BYTE; + struct st_portc_dscr2_bit BIT; +}; + +struct st_porte_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porte_pdr +{ + unsigned char BYTE; + struct st_porte_pdr_bit BIT; +}; + +struct st_porte_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porte_podr +{ + unsigned char BYTE; + struct st_porte_podr_bit BIT; +}; + +struct st_porte_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porte_pidr +{ + unsigned char BYTE; + struct st_porte_pidr_bit BIT; +}; + +struct st_porte_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porte_pmr +{ + unsigned char BYTE; + struct st_porte_pmr_bit BIT; +}; + +struct st_porte_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porte_odr0 +{ + unsigned char BYTE; + struct st_porte_odr0_bit BIT; +}; + +struct st_porte_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porte_odr1 +{ + unsigned char BYTE; + struct st_porte_odr1_bit BIT; +}; + +struct st_porte_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porte_pcr +{ + unsigned char BYTE; + struct st_porte_pcr_bit BIT; +}; + +struct st_porte_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porte_dscr +{ + unsigned char BYTE; + struct st_porte_dscr_bit BIT; +}; + +struct st_porte_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +struct st_portf_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_porte_dscr2 +{ + unsigned char BYTE; + struct st_porte_dscr2_bit BIT; +}; + +union un_portf_pdr +{ + unsigned char BYTE; + struct st_portf_pdr_bit BIT; +}; + +struct st_portf_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portf_podr +{ + unsigned char BYTE; + struct st_portf_podr_bit BIT; +}; + +struct st_portf_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portf_pidr +{ + unsigned char BYTE; + struct st_portf_pidr_bit BIT; +}; + +struct st_portf_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portf_pmr +{ + unsigned char BYTE; + struct st_portf_pmr_bit BIT; +}; + +struct st_portf_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portf_odr0 +{ + unsigned char BYTE; + struct st_portf_odr0_bit BIT; +}; + +struct st_portf_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portf_odr1 +{ + unsigned char BYTE; + struct st_portf_odr1_bit BIT; +}; + +struct st_portf_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portf_pcr +{ + unsigned char BYTE; + struct st_portf_pcr_bit BIT; +}; + +struct st_portg_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portg_pdr +{ + unsigned char BYTE; + struct st_portg_pdr_bit BIT; +}; + +struct st_portg_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portg_podr +{ + unsigned char BYTE; + struct st_portg_podr_bit BIT; +}; + +struct st_portg_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portg_pidr +{ + unsigned char BYTE; + struct st_portg_pidr_bit BIT; +}; + +struct st_portg_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portg_pmr +{ + unsigned char BYTE; + struct st_portg_pmr_bit BIT; +}; + +struct st_portg_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portg_odr0 +{ + unsigned char BYTE; + struct st_portg_odr0_bit BIT; +}; + +struct st_portg_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portg_odr1 +{ + unsigned char BYTE; + struct st_portg_odr1_bit BIT; +}; + +struct st_portg_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portg_pcr +{ + unsigned char BYTE; + struct st_portg_pcr_bit BIT; +}; + +struct st_portg_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char : 6; +#else + unsigned char : 6; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portg_dscr +{ + unsigned char BYTE; + struct st_portg_dscr_bit BIT; +}; + +struct st_portg_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char B4 : 1; + unsigned char B5 : 1; + unsigned char B6 : 1; + unsigned char B7 : 1; +#else + unsigned char B7 : 1; + unsigned char B6 : 1; + unsigned char B5 : 1; + unsigned char B4 : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portg_dscr2 +{ + unsigned char BYTE; + struct st_portg_dscr2_bit BIT; +}; + +struct st_portj_pdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portj_pdr +{ + unsigned char BYTE; + struct st_portj_pdr_bit BIT; +}; + +struct st_portj_podr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portj_podr +{ + unsigned char BYTE; + struct st_portj_podr_bit BIT; +}; + +struct st_portj_pidr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portj_pidr +{ + unsigned char BYTE; + struct st_portj_pidr_bit BIT; +}; + +struct st_portj_pmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portj_pmr +{ + unsigned char BYTE; + struct st_portj_pmr_bit BIT; +}; + +struct st_portj_odr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char B6 : 1; + unsigned char : 1; + unsigned char B4 : 1; + unsigned char : 1; + unsigned char B2 : 1; + unsigned char : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portj_odr0 +{ + unsigned char BYTE; + struct st_portj_odr0_bit BIT; +}; + +struct st_portj_odr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 2; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char : 2; +#endif +}; + +union un_portj_odr1 +{ + unsigned char BYTE; + struct st_portj_odr1_bit BIT; +}; + +struct st_portj_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char B3 : 1; + unsigned char : 1; + unsigned char B5 : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char B5 : 1; + unsigned char : 1; + unsigned char B3 : 1; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portj_pcr +{ + unsigned char BYTE; + struct st_portj_pcr_bit BIT; +}; + +struct st_portj_dscr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portj_dscr +{ + unsigned char BYTE; + struct st_portj_dscr_bit BIT; +}; + +struct st_portj_dscr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BT0 : 1; + unsigned char B1 : 1; + unsigned char B2 : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char B2 : 1; + unsigned char B1 : 1; + unsigned char BT0 : 1; +#endif +}; + +union un_portj_dscr2 +{ + unsigned char BYTE; + struct st_portj_dscr2_bit BIT; +}; + +struct st_sci0_smr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif +}; + +union un_sci0_smr +{ + unsigned char BYTE; + struct st_sci0_smr_bit BIT; +}; + +struct st_sci0_scr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif +}; + +union un_sci0_scr +{ + unsigned char BYTE; + struct st_sci0_scr_bit BIT; +}; + +struct st_sci0_ssr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif +}; + +union un_sci0_ssr +{ + unsigned char BYTE; + struct st_sci0_ssr_bit BIT; +}; + +struct st_sci0_scmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif +}; + +union un_sci0_scmr +{ + unsigned char BYTE; + struct st_sci0_scmr_bit BIT; +}; + +struct st_sci0_semr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ACS0 : 1; +#endif +}; + +union un_sci0_semr +{ + unsigned char BYTE; + struct st_sci0_semr_bit BIT; +}; + +struct st_sci0_snfr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif +}; + +union un_sci0_snfr +{ + unsigned char BYTE; + struct st_sci0_snfr_bit BIT; +}; + +struct st_sci0_simr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif +}; + +union un_sci0_simr1 +{ + unsigned char BYTE; + struct st_sci0_simr1_bit BIT; +}; + +struct st_sci0_simr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif +}; + +union un_sci0_simr2 +{ + unsigned char BYTE; + struct st_sci0_simr2_bit BIT; +}; + +struct st_sci0_simr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif +}; + +union un_sci0_simr3 +{ + unsigned char BYTE; + struct st_sci0_simr3_bit BIT; +}; + +struct st_sci0_sisr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif +}; + +union un_sci0_sisr +{ + unsigned char BYTE; + struct st_sci0_sisr_bit BIT; +}; + +struct st_sci0_spmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif +}; + +union un_sci0_spmr +{ + unsigned char BYTE; + struct st_sci0_spmr_bit BIT; +}; + +struct st_sci0_tdrhl_byte +{ + unsigned char TDRH; + unsigned char TDRL; +}; + +union un_sci0_tdrhl +{ + unsigned short WORD; + struct st_sci0_tdrhl_byte BYTE; +}; + +struct st_sci0_rdrhl_byte +{ + unsigned char RDRH; + unsigned char RDRL; +}; + +union un_sci0_rdrhl +{ + unsigned short WORD; + struct st_sci0_rdrhl_byte BYTE; +}; + +struct st_sci10_smr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif +}; + +union un_sci10_smr +{ + unsigned char BYTE; + struct st_sci10_smr_bit BIT; +}; + +struct st_sci10_scr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif +}; + +union un_sci10_scr +{ + unsigned char BYTE; + struct st_sci10_scr_bit BIT; +}; + +struct st_sci10_ssr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif +}; + +union un_sci10_ssr +{ + unsigned char BYTE; + struct st_sci10_ssr_bit BIT; +}; + +struct st_sci10_ssrfifo_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DR : 1; + unsigned char : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDF : 1; + unsigned char TDFE : 1; +#else + unsigned char TDFE : 1; + unsigned char RDF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char : 1; + unsigned char DR : 1; +#endif +}; + +union un_sci10_ssrfifo +{ + unsigned char BYTE; + struct st_sci10_ssrfifo_bit BIT; +}; + +struct st_sci10_scmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif +}; + +union un_sci10_scmr +{ + unsigned char BYTE; + struct st_sci10_scmr_bit BIT; +}; + +struct st_sci10_semr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ACS0 : 1; +#endif +}; + +union un_sci10_semr +{ + unsigned char BYTE; + struct st_sci10_semr_bit BIT; +}; + +struct st_sci10_snfr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif +}; + +union un_sci10_snfr +{ + unsigned char BYTE; + struct st_sci10_snfr_bit BIT; +}; + +struct st_sci10_simr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif +}; + +union un_sci10_simr1 +{ + unsigned char BYTE; + struct st_sci10_simr1_bit BIT; +}; + +struct st_sci10_simr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif +}; + +union un_sci10_simr2 +{ + unsigned char BYTE; + struct st_sci10_simr2_bit BIT; +}; + +struct st_sci10_simr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif +}; + +union un_sci10_simr3 +{ + unsigned char BYTE; + struct st_sci10_simr3_bit BIT; +}; + +struct st_sci10_sisr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif +}; + +union un_sci10_sisr +{ + unsigned char BYTE; + struct st_sci10_sisr_bit BIT; +}; + +struct st_sci10_spmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif +}; + +union un_sci10_spmr +{ + unsigned char BYTE; + struct st_sci10_spmr_bit BIT; +}; + +struct st_sci10_tdrhl_byte +{ + unsigned char TDRH; + unsigned char TDRL; +}; + +union un_sci10_tdrhl +{ + unsigned short WORD; + struct st_sci10_tdrhl_byte BYTE; +}; + +struct st_sci10_byte +{ + unsigned char H; + unsigned char L; +}; + +struct st_sci10_ftdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short TDAT : 9; + unsigned short MPBT : 1; + unsigned short : 6; +#else + unsigned short : 6; + unsigned short MPBT : 1; + unsigned short TDAT : 9; +#endif +}; + +union un_sci10_ftdr_bit_byte +{ + unsigned short WORD; + struct st_sci10_byte BYTE; + struct st_sci10_ftdr_bit BIT; +}; + +struct st_sci10_rdrhl_byte +{ + unsigned char RDRH; + unsigned char RDRL; +}; + +union un_sci10_rdrhl_byte +{ + unsigned short WORD; + struct st_sci10_rdrhl_byte BYTE; +}; + +struct st_sci10_frdr_bit_byte +{ + unsigned char H; + unsigned char L; +}; + +struct st_sci10_frdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short RDAT : 9; + unsigned short MPB : 1; + unsigned short DR : 1; + unsigned short PER : 1; + unsigned short FER : 1; + unsigned short ORER : 1; + unsigned short RDF : 1; + unsigned short : 1; +#else + unsigned short : 1; + unsigned short RDF : 1; + unsigned short ORER : 1; + unsigned short FER : 1; + unsigned short PER : 1; + unsigned short DR : 1; + unsigned short MPB : 1; + unsigned short RDAT : 9; +#endif +}; + +union un_sci10_frdr_bit_byte +{ + unsigned short WORD; + struct st_sci10_frdr_bit_byte BYTE; + struct st_sci10_frdr_bit BIT; +}; + +struct st_sci10_dccr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DCMF : 1; + unsigned char : 2; + unsigned char DPER : 1; + unsigned char DFER : 1; + unsigned char : 1; + unsigned char IDSEL : 1; + unsigned char DCME : 1; +#else + unsigned char DCME : 1; + unsigned char IDSEL : 1; + unsigned char : 1; + unsigned char DFER : 1; + unsigned char DPER : 1; + unsigned char : 2; + unsigned char DCMF : 1; +#endif +}; + +union un_sci10_dccr +{ + unsigned char BYTE; + struct st_sci10_dccr_bit BIT; +}; + +struct st_sci10_fcr_bit_byte +{ + unsigned char H; + unsigned char L; +}; + +struct st_sci10_fcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short FM : 1; + unsigned short RFRST : 1; + unsigned short TFRST : 1; + unsigned short DRES : 1; + unsigned short TTRG : 4; + unsigned short RTRG : 4; + unsigned short RSTRG : 4; +#else + unsigned short RSTRG : 4; + unsigned short RTRG : 4; + unsigned short TTRG : 4; + unsigned short DRES : 1; + unsigned short TFRST : 1; + unsigned short RFRST : 1; + unsigned short FM : 1; +#endif +}; + +union un_sci10_fcr +{ + unsigned short WORD; + struct st_sci10_fcr_bit_byte BYTE; + struct st_sci10_fcr_bit BIT; +}; + +struct st_sci10_fdr_bit_byte +{ + unsigned char H; + unsigned char L; +}; + +struct st_sci10_fdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short R : 5; + unsigned short : 3; + unsigned short T : 5; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short T : 5; + unsigned short : 3; + unsigned short R : 5; +#endif +}; + +union un_sci10_fdr +{ + unsigned short WORD; + struct st_sci10_fdr_bit_byte BYTE; + struct st_sci10_fdr_bit BIT; +}; + +struct st_sci10_lsr_bit_byte +{ + unsigned char H; + unsigned char L; +}; + +struct st_sci10_lsr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short ORER : 1; + unsigned short : 1; + unsigned short FNUM : 5; + unsigned short : 1; + unsigned short PNUM : 5; + unsigned short : 3; +#else + unsigned short : 3; + unsigned short PNUM : 5; + unsigned short : 1; + unsigned short FNUM : 5; + unsigned short : 1; + unsigned short ORER : 1; +#endif +}; + +union un_sci10_lsr +{ + unsigned short WORD; + struct st_sci10_lsr_bit_byte BYTE; + struct st_sci10_lsr_bit BIT; +}; + +struct st_sci10_cdr_bit_byte +{ + unsigned char H; + unsigned char L; +}; + +struct st_sci10_cdr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned short CMPD : 9; + unsigned short : 7; +#else + unsigned short : 7; + unsigned short CMPD : 9; +#endif +}; + +union un_sci10_cdr +{ + unsigned short WORD; + struct st_sci10_cdr_bit_byte BYTE; + struct st_sci10_cdr_bit BIT; +}; + +struct st_sci10_sptr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char RXDMON : 1; + unsigned char SPB2DT : 1; + unsigned char SPB2IO : 1; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char SPB2IO : 1; + unsigned char SPB2DT : 1; + unsigned char RXDMON : 1; +#endif +}; + +union st_sci10_sptr +{ + unsigned char BYTE; + struct st_sci10_sptr_bit BIT; +}; + +struct st_sci12_smr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKS : 2; + unsigned char MP : 1; + unsigned char STOP : 1; + unsigned char PM : 1; + unsigned char PE : 1; + unsigned char CHR : 1; + unsigned char CM : 1; +#else + unsigned char CM : 1; + unsigned char CHR : 1; + unsigned char PE : 1; + unsigned char PM : 1; + unsigned char STOP : 1; + unsigned char MP : 1; + unsigned char CKS : 2; +#endif +}; + +union un_sci12_smr +{ + unsigned char BYTE; + struct st_sci12_smr_bit BIT; +}; + +struct st_sci12_scr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CKE : 2; + unsigned char TEIE : 1; + unsigned char MPIE : 1; + unsigned char RE : 1; + unsigned char TE : 1; + unsigned char RIE : 1; + unsigned char TIE : 1; +#else + unsigned char TIE : 1; + unsigned char RIE : 1; + unsigned char TE : 1; + unsigned char RE : 1; + unsigned char MPIE : 1; + unsigned char TEIE : 1; + unsigned char CKE : 2; +#endif +}; + +union un_sci12_scr +{ + unsigned char BYTE; + struct st_sci12_scr_bit BIT; +}; + +struct st_sci12_ssr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char MPBT : 1; + unsigned char MPB : 1; + unsigned char TEND : 1; + unsigned char PER : 1; + unsigned char FER : 1; + unsigned char ORER : 1; + unsigned char RDRF : 1; + unsigned char TDRE : 1; +#else + unsigned char TDRE : 1; + unsigned char RDRF : 1; + unsigned char ORER : 1; + unsigned char FER : 1; + unsigned char PER : 1; + unsigned char TEND : 1; + unsigned char MPB : 1; + unsigned char MPBT : 1; +#endif +}; + +union un_sci12_ssr +{ + unsigned char BYTE; + struct st_sci12_ssr_bit BIT; +}; + +struct st_sci12_scmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SMIF : 1; + unsigned char : 1; + unsigned char SINV : 1; + unsigned char SDIR : 1; + unsigned char CHR1 : 1; + unsigned char : 2; + unsigned char BCP2 : 1; +#else + unsigned char BCP2 : 1; + unsigned char : 2; + unsigned char CHR1 : 1; + unsigned char SDIR : 1; + unsigned char SINV : 1; + unsigned char : 1; + unsigned char SMIF : 1; +#endif +}; + +union un_sci12_scmr +{ + unsigned char BYTE; + struct st_sci12_scmr_bit BIT; +}; + +struct st_sci12_semr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ACS0 : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ABCS : 1; + unsigned char NFEN : 1; + unsigned char BGDM : 1; + unsigned char RXDESEL : 1; +#else + unsigned char RXDESEL : 1; + unsigned char BGDM : 1; + unsigned char NFEN : 1; + unsigned char ABCS : 1; + unsigned char : 1; + unsigned char BRME : 1; + unsigned char : 1; + unsigned char ACS0 : 1; +#endif +}; + +union un_sci12_semr +{ + unsigned char BYTE; + struct st_sci12_semr_bit BIT; +}; + +struct st_sci12_snfr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char NFCS : 3; + unsigned char : 5; +#else + unsigned char : 5; + unsigned char NFCS : 3; +#endif +}; + +union un_sci12_snfr +{ + unsigned char BYTE; + struct st_sci12_snfr_bit BIT; +}; + +struct st_sci12_simr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICM : 1; + unsigned char : 2; + unsigned char IICDL : 5; +#else + unsigned char IICDL : 5; + unsigned char : 2; + unsigned char IICM : 1; +#endif +}; + +union un_sci12_simr1 +{ + unsigned char BYTE; + struct st_sci12_simr1_bit BIT; +}; + +struct st_sci12_simr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICINTM : 1; + unsigned char IICCSC : 1; + unsigned char : 3; + unsigned char IICACKT : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char IICACKT : 1; + unsigned char : 3; + unsigned char IICCSC : 1; + unsigned char IICINTM : 1; +#endif +}; + +union un_sci12_simr2 +{ + unsigned char BYTE; + struct st_sci12_simr2_bit BIT; +}; + +struct st_sci12_simr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICSTAREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICSTIF : 1; + unsigned char IICSDAS : 2; + unsigned char IICSCLS : 2; +#else + unsigned char IICSCLS : 2; + unsigned char IICSDAS : 2; + unsigned char IICSTIF : 1; + unsigned char IICSTPREQ : 1; + unsigned char IICRSTAREQ : 1; + unsigned char IICSTAREQ : 1; +#endif +}; + +union un_sci12_simr3 +{ + unsigned char BYTE; + struct st_sci12_simr3_bit BIT; +}; + +struct st_sci12_sisr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char IICACKR : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char IICACKR : 1; +#endif +}; + +union un_sci12_sisr +{ + unsigned char BYTE; + struct st_sci12_sisr_bit BIT; +}; + +struct st_sci12_spmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SSE : 1; + unsigned char CTSE : 1; + unsigned char MSS : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char CKPOL : 1; + unsigned char CKPH : 1; +#else + unsigned char CKPH : 1; + unsigned char CKPOL : 1; + unsigned char : 1; + unsigned char MFF : 1; + unsigned char : 1; + unsigned char MSS : 1; + unsigned char CTSE : 1; + unsigned char SSE : 1; +#endif +}; + +union un_sci12_spmr +{ + unsigned char BYTE; + struct st_sci12_spmr_bit BIT; +}; + +struct st_sci12_tdrhl_byte +{ + unsigned char TDRH; + unsigned char TDRL; +}; + +union un_sci12_tdrhl +{ + unsigned short WORD; + struct st_sci12_tdrhl_byte BYTE; +}; + +struct st_sci12_rdrhl_byte +{ + unsigned char RDRH; + unsigned char RDRL; +}; + +union un_sci12_rdrhl +{ + unsigned short WORD; + struct st_sci12_rdrhl_byte BYTE; +}; + +struct st_sci12_esmer_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char ESME : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char ESME : 1; +#endif +}; + +union un_sci12_esmer +{ + unsigned char BYTE; + struct st_sci12_esmer_bit BIT; +}; + +struct st_sci12_ctr0_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char : 1; + unsigned char SFSF : 1; + unsigned char RXDSF : 1; + unsigned char BRME : 1; + unsigned char : 4; +#else + unsigned char : 4; + unsigned char BRME : 1; + unsigned char RXDSF : 1; + unsigned char SFSF : 1; + unsigned char : 1; +#endif +}; + +union un_sci12_ctr0 +{ + unsigned char BYTE; + struct st_sci12_ctr0_bit BIT; +}; + +struct st_sci12_ctr1_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFE : 1; + unsigned char CF0RE : 1; + unsigned char CF1DS : 2; + unsigned char PIBE : 1; + unsigned char PIBS : 3; +#else + unsigned char PIBS : 3; + unsigned char PIBE : 1; + unsigned char CF1DS : 2; + unsigned char CF0RE : 1; + unsigned char BFE : 1; +#endif +}; + +union un_sci12_ctr1 +{ + unsigned char BYTE; + struct st_sci12_ctr1_bit BIT; +}; + +struct st_sci12_ctr2_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char DFCS : 3; + unsigned char : 1; + unsigned char BCCS : 2; + unsigned char RTS : 2; +#else + unsigned char RTS : 2; + unsigned char BCCS : 2; + unsigned char : 1; + unsigned char DFCS : 3; +#endif +}; + +union un_sci12_ctr2 +{ + unsigned char BYTE; + struct st_sci12_ctr2_bit BIT; +}; + +struct st_sci12_ctr3_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char SDST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char SDST : 1; +#endif +}; + +union un_sci12_ctr3 +{ + unsigned char BYTE; + struct st_sci12_ctr3_bit BIT; +}; + +struct st_sci12_pcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TXDXPS : 1; + unsigned char RXDXPS : 1; + unsigned char : 2; + unsigned char SHARPS : 1; + unsigned char : 3; +#else + unsigned char : 3; + unsigned char SHARPS : 1; + unsigned char : 2; + unsigned char RXDXPS : 1; + unsigned char TXDXPS : 1; +#endif +}; + +union un_sci12_pcr +{ + unsigned char BYTE; + struct st_sci12_pcr_bit BIT; +}; + +struct st_sci12_icr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDIE : 1; + unsigned char CF0MIE : 1; + unsigned char CF1MIE : 1; + unsigned char PIBDIE : 1; + unsigned char BCDIE : 1; + unsigned char AEDIE : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDIE : 1; + unsigned char BCDIE : 1; + unsigned char PIBDIE : 1; + unsigned char CF1MIE : 1; + unsigned char CF0MIE : 1; + unsigned char BFDIE : 1; +#endif +}; + +union un_sci12_icr +{ + unsigned char BYTE; + struct st_sci12_icr_bit BIT; +}; + +struct st_sci12_str_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDF : 1; + unsigned char CF0MF : 1; + unsigned char CF1MF : 1; + unsigned char PIBDF : 1; + unsigned char BCDF : 1; + unsigned char AEDF : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDF : 1; + unsigned char BCDF : 1; + unsigned char PIBDF : 1; + unsigned char CF1MF : 1; + unsigned char CF0MF : 1; + unsigned char BFDF : 1; +#endif +}; + +union un_sci12_str +{ + unsigned char BYTE; + struct st_sci12_str_bit BIT; +}; + +struct un_sci12_stcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char BFDCL : 1; + unsigned char CF0MCL : 1; + unsigned char CF1MCL : 1; + unsigned char PIBDCL : 1; + unsigned char BCDCL : 1; + unsigned char AEDCL : 1; + unsigned char : 2; +#else + unsigned char : 2; + unsigned char AEDCL : 1; + unsigned char BCDCL : 1; + unsigned char PIBDCL : 1; + unsigned char CF1MCL : 1; + unsigned char CF0MCL : 1; + unsigned char BFDCL : 1; +#endif +}; + +union un_sci12_stcr +{ + unsigned char BYTE; + struct un_sci12_stcr_bit BIT; +}; + +struct st_sci12_cf0cr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF0CE0 : 1; + unsigned char CF0CE1 : 1; + unsigned char CF0CE2 : 1; + unsigned char CF0CE3 : 1; + unsigned char CF0CE4 : 1; + unsigned char CF0CE5 : 1; + unsigned char CF0CE6 : 1; + unsigned char CF0CE7 : 1; +#else + unsigned char CF0CE7 : 1; + unsigned char CF0CE6 : 1; + unsigned char CF0CE5 : 1; + unsigned char CF0CE4 : 1; + unsigned char CF0CE3 : 1; + unsigned char CF0CE2 : 1; + unsigned char CF0CE1 : 1; + unsigned char CF0CE0 : 1; +#endif +}; + +union un_sci12_cf0cr +{ + unsigned char BYTE; + struct st_sci12_cf0cr_bit BIT; +}; + +struct st_sci12_cf1cr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char CF1CE0 : 1; + unsigned char CF1CE1 : 1; + unsigned char CF1CE2 : 1; + unsigned char CF1CE3 : 1; + unsigned char CF1CE4 : 1; + unsigned char CF1CE5 : 1; + unsigned char CF1CE6 : 1; + unsigned char CF1CE7 : 1; +#else + unsigned char CF1CE7 : 1; + unsigned char CF1CE6 : 1; + unsigned char CF1CE5 : 1; + unsigned char CF1CE4 : 1; + unsigned char CF1CE3 : 1; + unsigned char CF1CE2 : 1; + unsigned char CF1CE1 : 1; + unsigned char CF1CE0 : 1; +#endif +}; + +union un_sci12_cf1cr +{ + unsigned char BYTE; + struct st_sci12_cf1cr_bit BIT; +}; + +struct st_sci12_tcr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TCST : 1; + unsigned char : 7; +#else + unsigned char : 7; + unsigned char TCST : 1; +#endif +}; + +union un_sci12_tcr +{ + unsigned char BYTE; + struct st_sci12_tcr_bit BIT; +}; + +struct st_sci12_tmr_bit +{ +#ifdef __RX_LITTLE_ENDIAN__ + unsigned char TOMS : 2; + unsigned char : 1; + unsigned char TWRC : 1; + unsigned char TCSS : 3; + unsigned char : 1; +#else + unsigned char : 1; + unsigned char TCSS : 3; + unsigned char TWRC : 1; + unsigned char : 1; + unsigned char TOMS : 2; +#endif +}; + +union un_sci12_tmr +{ + unsigned char BYTE; + struct st_sci12_tmr_bit BIT; +}; + +typedef struct st_bsc +{ + union un_berclr BERCLR; + char wk0[3]; + char wk1[3]; + union un_beren BEREN; + char wk2[1]; + union un_bersr1 BERSR1; + char wk3[4]; + union un_bersr2 BERSR2; + char wk4[7408]; + union un_buspri BUSPRI; + union un_cs0mod CS0MOD; + union un_cs0wcr1 CS0WCR1; + char wk5[6]; + union un_cs1mod CS1MOD; + union un_cs1wcr1 CS1WCR1; + union un_cs1wcr2 CS1WCR2; + char wk6[6]; + union un_cs2mod CS2MOD; + union un_cs2wcr1 CS2WCR1; + union un_cs2wcr2 CS2WCR2; + char wk7[6]; + union un_cs3mod CS3MOD; + union un_cs3wcr1 CS3WCR1; + union un_cs3wcr2 CS3WCR2; + char wk8[6]; + union un_cs4mod CS4MOD; + union un_cs4wcr1 CS4WCR1; + union un_cs4wcr2 CS4WCR2; + char wk9[6]; + union un_cs5mod CS5MOD; + union un_cs5wcr1 CS5WCR1; + union un_cs5wcr2 CS5WCR2; + char wk10[6]; + union un_cs6mod CS6MOD; + union un_cs6wcr1 CS6WCR1; + union un_cs6wcr2 CS6WCR2; + char wk11[6]; + union un_cs7mod CS7MOD; + union un_cs7wcr1 CS7WCR1; + union un_cs7wcr2 CS7WCR2; + char wk12[1926]; + union un_cs0cr CS0CR; + char wk13[6]; + union un_cs0rec CS0REC; + char wk14[6]; + union un_cs1cr CS1CR; + char wk15[6]; + union un_cs1rec CS1REC; + char wk16[6]; + union un_cs2cr CS2CR; + char wk17[6]; + union un_cs2rec CS2REC; + char wk18[6]; + union un_cs3cr CS3CR; + char wk19[6]; + union un_cs3rec CS3REC; + char wk20[6]; + union un_cs4cr CS4CR; + char wk21[6]; + union un_cs4rec CS4REC; + char wk22[6]; + union un_cs5cr CS5CR; + char wk23[6]; + union un_cs5rec CS5REC; + char wk24[6]; + union un_cs6cr CS6CR; + char wk25[6]; + union un_cs6rec CS6REC; + char wk26[6]; + union un_cs7cr CS7CR; + char wk27[6]; + union un_cs7rec CS7REC; + char wk28[4]; + union un_csrecen CSRECEN; + char wk29[894]; + union un_sdccr SDCCR; + union un_sdcmod SDCMOD; + union un_sdamod SDAMOD; + char wk30[13]; + union un_sdself SDSELF; + char wk31[3]; + union un_sdrfcr SDRFCR; + union un_sdrfen SDRFEN; + char wk32[9]; + union un_sdicr SDICR; + char wk33[3]; + union un_sdir SDIR; + char wk34[26]; + union un_sdar SDAR; + char wk35[3]; + union un_sdtr SDTR; + union un_sdmod SDMOD; + char wk36[6]; + union un_sdsr SDSR; + char wk37[269231]; + union un_ebmapcr EBMAPCR; +} st_bsc_t; + +typedef struct st_cac +{ + union un_cacr0 CACR0; + union un_cacr1 CACR1; + union un_cacr2 CACR2; + union un_caicr CAICR; + union un_castr CASTR; + char wk0[1]; + unsigned short CAULVR; + unsigned short CALLVR; + unsigned short CACNTBR; +} st_cac_t; + +typedef struct st_cmt +{ + union un_cmstr0 CMSTR0; + char wk0[14]; + union un_cmstr1 CMSTR1; +} st_cmt_t; + +typedef struct st_cmt0 +{ + union un_cmcr CMCR; + unsigned short CMCNT; + unsigned short CMCOR; +} st_cmt0_t; + +typedef struct st_icu +{ + union un_icu_ir256 IR[256]; + union un_icu_dtcer256 DTCER[256]; + union un_ier32 IER[32]; + char wk0[192]; + union un_swintr SWINTR; + union un_swint2r SWINT2R; + char wk1[14]; + union un_icu_fir FIR; + char wk2[14]; + union un_icu_ipr256 IPR[256]; + unsigned char DMRSR0; + char wk3[3]; + unsigned char DMRSR1; + char wk4[3]; + unsigned char DMRSR2; + char wk5[3]; + unsigned char DMRSR3; + char wk6[3]; + unsigned char DMRSR4; + char wk7[3]; + unsigned char DMRSR5; + char wk8[3]; + unsigned char DMRSR6; + char wk9[3]; + unsigned char DMRSR7; + char wk10[227]; + union un_irqcr16 IRQCR[16]; + char wk11[16]; + union un_irqflte0 IRQFLTE0; + union un_irqflte1 IRQFLTE1; + char wk12[6]; + union un_icu_irqfltc0 IRQFLTC0; + union un_icu_irqfltc1 IRQFLCT1; + char wk13[84]; + union un_icu_nmisr NMISR; + union un_icu_nmier NMIER; + union un_icu_nmiclr NMICLR; + union un_icu_nmicr NMICR; + char wk14[12]; + union un_icu_nmiflte NMIFLTE; + char wk15[3]; + union un_icu_nmifltc NMIFLTC; + char wk16[107]; + union un_icu_grpbe0 GRPBE0; + char wk17[44]; + union un_grpbl0 GRPBL0; + union un_grpbl1 GRPBL1; + union un_icu_grpbl2 GRPBL2; + char wk18[4]; + union un_icu_genbe0 GENBE0; + char wk19[44]; + union un_genbl0 GENBL0; + union un_genbl1 GENBL1; + union un_icu_genbl2 GENBL2; + char wk20[4]; + union un_icu_gcrbe0 GCRBE0; + char wk21[124]; + union un_icu_pibr0 PIBR0; + union un_icu_pibr1 PIBR1; + union un_icu_pibr2 PIBR2; + union un_icu_pibr3 PIBR3; + union un_icu_pibr4 PIBR4; + union un_icu_pibr5 PIBR5; + union un_icu_pibr6 PIBR6; + union un_icu_pibr7 PIBR7; + union un_icu_pibr8 PIBR8; + union un_icu_pibr9 PIBR9; + union un_icu_pibra PIBRA; + union un_icu_pibrb PIBRB; + char wk22[116]; + union un_icu_slibxr128 SLIBXR128; + union un_icu_slibxr129 SLIBXR129; + union un_icu_slibxr130 SLIBXR130; + union un_icu_slibxr131 SLIBXR131; + union un_icu_slibxr132 SLIBXR132; + union un_icu_slibxr133 SLIBXR133; + union un_icu_slibxr134 SLIBXR134; + union un_icu_slibxr135 SLIBXR135; + union un_icu_slibxr136 SLIBXR136; + union un_icu_slibxr137 SLIBXR137; + union un_icu_slibxr138 SLIBXR138; + union un_icu_slibxr139 SLIBXR139; + union un_icu_slibxr140 SLIBXR140; + union un_icu_slibxr141 SLIBXR141; + union un_icu_slibxr142 SLIBXR142; + union un_icu_slibxr143 SLIBXR143; + union un_icu_slibr144 SLIBR144; + union un_icu_slibr145 SLIBR145; + union un_icu_slibr146 SLIBR146; + union un_icu_slibr147 SLIBR147; + union un_icu_slibr148 SLIBR148; + union un_icu_slibr149 SLIBR149; + union un_icu_slibr150 SLIBR150; + union un_icu_slibr151 SLIBR151; + union un_icu_slibr152 SLIBR152; + union un_icu_slibr153 SLIBR153; + union un_icu_slibr154 SLIBR154; + union un_icu_slibr155 SLIBR155; + union un_icu_slibr156 SLIBR156; + union un_icu_slibr157 SLIBR157; + union un_icu_slibr158 SLIBR158; + union un_icu_slibr159 SLIBR159; + union un_icu_slibr160 SLIBR160; + union un_icu_slibr161 SLIBR161; + union un_icu_slibr162 SLIBR162; + union un_icu_slibr163 SLIBR163; + union un_icu_slibr164 SLIBR164; + union un_icu_slibr165 SLIBR165; + union un_icu_slibr166 SLIBR166; + union un_icu_slibr167 SLIBR167; + union un_icu_slibr168 SLIBR168; + union un_icu_slibr169 SLIBR169; + union un_icu_slibr170 SLIBR170; + union un_icu_slibr171 SLIBR171; + union un_icu_slibr172 SLIBR172; + union un_icu_slibr173 SLIBR173; + union un_icu_slibr174 SLIBR174; + union un_icu_slibr175 SLIBR175; + union un_icu_slibr176 SLIBR176; + union un_icu_slibr177 SLIBR177; + union un_icu_slibr178 SLIBR178; + union un_icu_slibr179 SLIBR179; + union un_icu_slibr180 SLIBR180; + union un_icu_slibr181 SLIBR181; + union un_icu_slibr182 SLIBR182; + union un_icu_slibr183 SLIBR183; + union un_icu_slibr184 SLIBR184; + union un_icu_slibr185 SLIBR185; + union un_icu_slibr186 SLIBR186; + union un_icu_slibr187 SLIBR187; + union un_icu_slibr188 SLIBR188; + union un_icu_slibr189 SLIBR189; + union un_icu_slibr190 SLIBR190; + union un_icu_slibr191 SLIBR191; + union un_icu_slibr192 SLIBR192; + union un_icu_slibr193 SLIBR193; + union un_icu_slibr194 SLIBR194; + union un_icu_slibr195 SLIBR195; + union un_icu_slibr196 SLIBR196; + union un_icu_slibr197 SLIBR197; + union un_icu_slibr198 SLIBR198; + union un_icu_slibr199 SLIBR199; + union un_icu_slibr200 SLIBR200; + union un_icu_slibr201 SLIBR201; + union un_icu_slibr202 SLIBR202; + union un_icu_slibr203 SLIBR203; + union un_icu_slibr204 SLIBR204; + union un_icu_slibr205 SLIBR205; + union un_icu_slibr206 SLIBR206; + union un_icu_slibr207 SLIBR207; + char wk23[96]; + union un_grpal0 GRPAL0; + union un_grpal1 GRPAL1; + char wk24[56]; + union un_genal0 GENAL0; + union un_genal1 GENAL1; + char wk25[136]; + union un_icu_piar0 PIAR0; + union un_icu_piar1 PIAR1; + union un_icu_piar2 PIAR2; + union un_icu_piar3 PIAR3; + union un_icu_piar4 PIAR4; + union un_icu_piar5 PIAR5; + char wk26[5]; + union un_icu_piarb PIARB; + char wk27[196]; + union un_icu_sliar208 SLIAR208; + union un_icu_sliar209 SLIAR209; + union un_icu_sliar210 SLIAR210; + union un_icu_sliar211 SLIAR211; + union un_icu_sliar212 SLIAR212; + union un_icu_sliar213 SLIAR213; + union un_icu_sliar214 SLIAR214; + union un_icu_sliar215 SLIAR215; + union un_icu_sliar216 SLIAR216; + union un_icu_sliar217 SLIAR217; + union un_icu_sliar218 SLIAR218; + union un_icu_sliar219 SLIAR219; + union un_icu_sliar220 SLIAR220; + union un_icu_sliar221 SLIAR221; + union un_icu_sliar222 SLIAR222; + union un_icu_sliar223 SLIAR223; + union un_icu_sliar224 SLIAR224; + union un_icu_sliar225 SLIAR225; + union un_icu_sliar226 SLIAR226; + union un_icu_sliar227 SLIAR227; + union un_icu_sliar228 SLIAR228; + union un_icu_sliar229 SLIAR229; + union un_icu_sliar230 SLIAR230; + union un_icu_sliar231 SLIAR231; + union un_icu_sliar232 SLIAR232; + union un_icu_sliar233 SLIAR233; + union un_icu_sliar234 SLIAR234; + union un_icu_sliar235 SLIAR235; + union un_icu_sliar236 SLIAR236; + union un_icu_sliar237 SLIAR238; + union un_icu_sliar239 SLIAR239; + union un_icu_sliar240 SLIAR240; + union un_icu_sliar241 SLIAR241; + union un_icu_sliar242 SLIAR242; + union un_icu_sliar243 SLIAR243; + union un_icu_sliar244 SLIAR244; + union un_icu_sliar245 SLIAR245; + union un_icu_sliar246 SLIAR246; + union un_icu_sliar247 SLIAR247; + union un_icu_sliar248 SLIAR248; + union un_icu_sliar249 SLIAR249; + union un_icu_sliar250 SLIAR250; + union un_icu_sliar251 SLIAR251; + union un_icu_sliar252 SLIAR252; + union un_icu_sliar253 SLIAR253; + union un_icu_sliar254 SLIAR254; + union un_icu_sliar255 SLIAR255; + union un_icu_sliprcr SLIPRCR; + union un_icu_slexdr SLEXDR; +} st_icu_t; + +typedef struct st_mpc +{ + union un_mpc_pfcse PFCSE; + char wk0[1]; + union un_mpc_pfcss0 PFCSS0; + union un_mpc_pfcss1 PFCSS1; + union un_mpc_pfa0e0 PFA0E0; + union un_mpc_pfa0e1 PFA0E1; + union un_mpc_pfbcr0 PFBCR0; + union un_mpc_pfbcr1 PFBCR1; + union un_mpc_pfbcr2 PFBCR2; + union un_mpc_pfbcr3 PFBCR3; + char wk1[4]; + union un_mpc_pfenet PFENET; + char wk2[16]; + union un_pwpr PWPR; + char wk3[32]; + union un_p00pfs P00PFS; + union un_p01pfs P01PFS; + union un_mpc_p02pfs P02PFS; + union un_mpc_p03pfs P03PFS; + char wk4[1]; + union un_mpc_p05pfs P05PFS; + char wk5[1]; + union un_mpc_p07pfs P07PFS; + union un_mpc_p10pfs P10PFS; + union un_mpc_p11pfs P11PFS; + union un_mpc_p12pfs P12PFS; + union un_mpc_p13pfs P13PFS; + union un_mpc_p14pfs P14PFS; + union un_mpc_p15pfs P15PFS; + union un_mpc_p16pfs P16PFS; + union un_mpc_p17pfs P17PFS; + union un_mpc_p20pfs P20PFS; + union un_mpc_p21pfs P21PFS; + union un_mpc_p22pfs P22PFS; + union un_mpc_p23pfs P23PFS; + union un_mpc_p24pfs P24PFS; + union un_mpc_p25pfs P25PFS; + union un_mpc_p26pfs P26PFS; + union un_mpc_p27pfs P27PFS; + union un_mpc_p30pfs P30PFS; + union un_mpc_p31pfs P31PFS; + union un_mpc_p32pfs P32PFS; + union un_mpc_p33pfs P33PFS; + union un_mpc_p34pfs P34PFS; + char wk6[3]; + union un_mpc_p40pfs P40PFS; + union un_mpc_p41pfs P41PFS; + union un_mpc_p42pfs P42PFS; + union un_mpc_p43pfs P43PFS; + union un_mpc_p44pfs P44PFS; + union un_mpc_p45pfs P45PFS; + union un_mpc_p46pfs P46PFS; + union un_mpc_p47pfs P47PFS; + union un_mpc_p50pfs P50PFS; + union un_mpc_p51pfs P51PFS; + union un_mpc_p52pfs P52PFS; + char wk7[1]; + union un_mpc_p54pfs P54PFS; + union un_mpc_p55pfs P55PFS; + union un_mpc_p56pfs P56PFS; + union un_mpc_p57pfs P57PFS; + char wk8[6]; + union un_mpc_p66pfs P66PFS; + union un_mpc_p67pfs P67PFS; + char wk9[1]; + union un_mpc_p71pfs P71PFS; + union un_mpc_p72pfs P72PFS; + union un_mpc_p73pfs P73PFS; + union un_mpc_p74pfs P74PFS; + union un_mpc_p75pfs P75PFS; + union un_mpc_p76pfs P76PFS; + union un_mpc_p77pfs P77PFS; + union un_mpc_p80pfs P80PFS; + union un_mpc_p81pfs P81PFS; + union un_mpc_p82pfs P82PFS; + union un_mpc_p83pfs P83PFS; + union un_mpc_p84pfs P84PFS; + union un_mpc_p85pfs P85PFS; + union un_mpc_p86pfs P86PFS; + union un_mpc_p87pfs P87PFS; + union un_mpc_p90pfs P90PFS; + union un_mpc_p91pfs P91PFS; + union un_mpc_p92pfs P92PFS; + union un_mpc_p93pfs P93PFS; + char wk10[4]; + union un_mpc_pa0pfs PA0PFS; + union un_mpc_pa1pfs PA1PFS; + union un_mpc_pa2pfs PA2PFS; + union un_mpc_pa3pfs PA3PFS; + union un_mpc_pa4pfs PA4PFS; + union un_mpc_pa5pfs PA5PFS; + union un_mpc_pa6pfs PA6PFS; + union un_mpc_pa7pfs PA7PFS; + union un_mpc_pb0pfs PB0PFS; + union un_mpc_pb1pfs PB1PFS; + union un_mpc_pb2pfs PB2PFS; + union un_mpc_pb3pfs PB3PFS; + union un_mpc_pb4pfs PB4PFS; + union un_mpc_pb5pfs PB5PFS; + union un_mpc_pb6pfs PB6PFS; + union un_mpc_pb7pfs PB7PFS; + union un_mpc_pc0pfs PC0PFS; + union un_mpc_pc1pfs PC1PFS; + union un_mpc_pc2pfs PC2PFS; + union un_mpc_pc3pfs PC3PFS; + union un_mpc_pc4pfs PC4PFS; + union un_mpc_pc5pfs PC5PFS; + union un_mpc_pc6pfs PC6PFS; + union un_mpc_pc7pfs PC7PFS; + union un_mpc_pd0pfs PD0PFS; + union un_mpc_pd1pfs PD1PFS; + union un_mpc_pd2pfs PD2PFS; + union un_mpc_pd3pfs PD3PFS; + union un_mpc_pd4pfs PD4PFS; + union un_mpc_pd5pfs PD5PFS; + union un_mpc_pd6pfs PD6PFS; + union un_mpc_pd7pfs PD7PFS; + union un_mpc_pe0pfs PE0PFS; + union un_mpc_pe1pfs PE1PFS; + union un_mpc_pe2pfs PE2PFS; + union un_mpc_pe3pfs PE3PFS; + union un_mpc_pe4pfs PE4PFS; + union un_mpc_pe5pfs PE5PFS; + union un_mpc_pe6pfs PE6PFS; + union un_mpc_pe7pfs PE7PFS; + union un_mpc_pf0pfs PF0PFS; + union un_mpc_pf1pfs PF1PFS; + union un_mpc_pf2pfs PF2PFS; + char wk11[2]; + union un_mpc_pf5pfs PF5PFS; + char wk12[18]; + union un_mpc_pj0pfs PJ0PFS; + union un_mpc_pj1pfs PJ1PFS; + union un_mpc_pj2pfs PJ2PFS; + union un_mpc_pj3pfs PJ3PFS; + char wk13[1]; + union un_mpc_pj5pfs PJ5PFS; +} st_mpc_t; + +typedef struct st_port0 +{ + union un_pdr PDR; + char wk0[31]; + union un_podr PODR; + char wk1[31]; + union un_pidr PIDR; + char wk2[31]; + union un_pmr PMR; + char wk3[31]; + union un_odr0 ODR0; + union un_odr1 ODR1; + char wk4[62]; + union un_pcr PCR; + char wk5[31]; + union un_dscr DSCR; + char wk6[71]; + union un_dscr2 DSCR2; +} st_port0_t; + +typedef struct st_port1 +{ + union un_port1_pdr PDR; + char wk0[31]; + union un_port1_podr PODR; + char wk1[31]; + union un_port1_pidr PIDR; + char wk2[31]; + union un_port1_pmr PMR; + char wk3[32]; + union un_port1_odr0 ODR0; + union un_port1_odr1 ODR1; + char wk4[61]; + union un_port1_pcr PCR; + char wk5[31]; + union un_port1_dscr DSCR; + char wk6[71]; + union un_port1_dscr2 DSCR2; +} st_port1_t; + +typedef struct st_port2 +{ + union un_port2_pdr PDR; + char wk0[31]; + union un_port2_podr PODR; + char wk1[31]; + union un_port2_pidr PIDR; + char wk2[31]; + union un_port2_pmr PMR; + char wk3[33]; + union un_port2_odr0 ODR0; + union un_port2_odr1 ODR1; + char wk4[60]; + union un_port2_pcr PCR; + char wk5[31]; + union un_port2_dscr DSCR; + char wk6[71]; + union un_port2_dscr2 DSCR2; +} st_port2_t; + +typedef struct st_port3 +{ + union un_port3_pdr PDR; + char wk0[31]; + union un_port3_podr PODR; + char wk1[31]; + union un_port3_pidr PIDR; + char wk2[31]; + union un_port3_pmr PMR; + char wk3[34]; + union un_port3_odr0 ODR0; + union un_port3_odr1 ODR1; + char wk4[59]; + union un_port3_pcr PCR; + char wk5[103]; + union un_port3_dscr2 DSCR2; +} st_port3_t; + +typedef struct st_port5 +{ + union un_port5_pdr PDR; + char wk0[31]; + union un_port5_podr PODR; + char wk1[31]; + union un_port5_pidr PIDR; + char wk2[31]; + union un_port5_pmr PMR; + char wk3[36]; + union un_port5_odr0 ODR0; + union un_port5_odr1 ODR1; + char wk4[57]; + union un_port5_pcr PCR; + char wk5[31]; + union un_port5_dscr DSCR; + char wk6[71]; + union un_port5_dscr2 DSCR2; +} st_port5_t; + +typedef struct st_port7 +{ + union un_port7_pdr PDR; + char wk0[31]; + union un_port7_podr PODR; + char wk1[31]; + union un_port7_pidr PIDR; + char wk2[31]; + union un_port7_pmr PMR; + char wk3[38]; + union un_port7_odr0 ODR0; + union un_port7_odr1 ODR1; + char wk4[55]; + union un_port7_pcr PCR; + char wk5[31]; + union un_port7_dscr DSCR; + char wk6[71]; + union un_port7_dscr2 DSCR2; +} st_port7_t; + +typedef struct st_port8 +{ + union un_port8_pdr PDR; + char wk0[31]; + union un_port8_podr PODR; + char wk1[31]; + union un_port8_pidr PIDR; + char wk2[31]; + union un_port8_pmr PMR; + char wk3[39]; + union un_port8_odr0 ODR0; + union un_port8_odr1 ODR1; + char wk4[54]; + union un_port8_pcr PCR; + char wk5[31]; + union un_port8_dscr DSCR; + char wk6[71]; + union un_port8_dscr2 DSCR2; +} st_port8_t; + +typedef struct st_port9 +{ + union un_port9_pdr PDR; + char wk0[31]; + union un_port9_podr PODR; + char wk1[31]; + union un_port9_pidr PIDR; + char wk2[31]; + union un_port9_pmr PMR; + char wk3[40]; + union un_port9_odr0 ODR0; + union un_port9_odr1 ODR1; + char wk4[53]; + union un_port9_pcr PCR; + char wk5[31]; + union un_port9_dscr DSCR; + char wk6[71]; + union un_port9_dscr2 DSCR2; +} st_port9_t; + +typedef struct st_porta +{ + union un_porta_pdr PDR; + char wk0[31]; + union un_porta_podr PODR; + char wk1[31]; + union un_porta_pidr PIDR; + char wk2[31]; + union un_porta_pmr PMR; + char wk3[41]; + union un_porta_odr0 ODR0; + union un_porta_odr1 ODR1; + char wk4[52]; + union un_porta_pcr PCR; + char wk5[31]; + union un_porta_dscr DSCR; + char wk6[71]; + union un_porta_dscr2 DSCR2; +} st_porta_t; + +typedef struct st_portb +{ + union un_portb_pdr PDR; + char wk0[31]; + union un_portb_podr PODR; + char wk1[31]; + union un_portb_pidr PIDR; + char wk2[31]; + union un_portb_pmr PMR; + char wk3[42]; + union un_portb_odr0 ODR0; + union un_portb_odr1 ODR1; + char wk4[51]; + union un_portb_pcr PCR; + char wk5[31]; + union un_portb_dscr DSCR; + char wk6[71]; + union un_portb_dscr2 DSCR2; +} st_portb_t; + +typedef struct st_portc +{ + union un_portc_pdr PDR; + char wk0[31]; + union un_portc_podr PODR; + char wk1[31]; + union un_portc_pidr PIDR; + char wk2[31]; + union un_portc_pmr PMR; + char wk3[43]; + union un_portc_odr0 ODR0; + union un_portc_odr1 ODR1; + char wk4[50]; + union un_portc_pcr PCR; + char wk5[31]; + union un_portc_dscr DSCR; + char wk6[71]; + union un_portc_dscr2 DSCR2; +} st_portc_t; + +typedef struct st_porte +{ + union un_porte_pdr PDR; + char wk0[31]; + union un_porte_podr PODR; + char wk1[31]; + union un_porte_pidr PIDR; + char wk2[31]; + union un_porte_pmr PMR; + char wk3[45]; + union un_porte_odr0 ODR0; + union un_porte_odr1 ODR1; + char wk4[48]; + union un_porte_pcr PCR; + char wk5[31]; + union un_porte_dscr DSCR; + char wk6[71]; + union un_porte_dscr2 DSCR2; +} st_porte_t; + +typedef struct st_portf +{ + union un_portf_pdr PDR; + char wk0[31]; + union un_portf_podr PODR; + char wk1[31]; + union un_portf_pidr PIDR; + char wk2[31]; + union un_portf_pmr PMR; + char wk3[46]; + union un_portf_odr0 ODR0; + union un_portf_odr1 ODR1; + char wk4[47]; + union un_portf_pcr PCR; +} st_portf_t; + +typedef struct st_portg +{ + union un_portg_pdr PDR; + char wk0[31]; + union un_portg_podr PODR; + char wk1[31]; + union un_portg_pidr PIDR; + char wk2[31]; + union un_portg_pmr PMR; + char wk3[47]; + union un_portg_odr0 ODR0; + union un_portg_odr1 ODR1; + char wk4[46]; + union un_portg_pcr PCR; + char wk5[31]; + union un_portg_dscr DSCR; + char wk6[71]; + union un_portg_dscr2 DSCR2; +} st_portg_t; + +typedef struct st_portj +{ + union un_portj_pdr PDR; + char wk0[31]; + union un_portj_podr PODR; + char wk1[31]; + union un_portj_pidr PIDR; + char wk2[31]; + union un_portj_pmr PMR; + char wk3[49]; + union un_portj_odr0 ODR0; + union un_portj_odr1 ODR1; + char wk4[44]; + union un_portj_pcr PCR; + char wk5[31]; + union un_portj_dscr DSCR; + char wk6[71]; + union un_portj_dscr2 DSCR2; +} st_portj_t; + +typedef struct st_rtc +{ + union un_rtc_r64cnt R64CNT; + char wk0[1]; + union + { + union un_rtc_rseccnt RSECCNT; + union un_rtc_bcnt0 BCNT0; + }; + char wk1[1]; + union + { + union un_rtc_rmincnt RMINCNT; + union un_rtc_bcnt1 BCNT1; + }; + char wk2[1]; + union + { + union un_rtc_rhrcnt RHRCNT; + union un_rtc_bcnt2 BCNT2; + }; + char wk3[1]; + union + { + union un_rtc_rwkcnt RWKCNT; + union un_rtc_bcnt3 BCNT3; + }; + char wk4[1]; + union un_rtc_rdaycnt RDAYCNT; + char wk5[1]; + union un_rtc_rmoncnt RMONCNT; + char wk6[1]; + union un_rtc_ryrcnt RYRCNT; + union + { + union un_rtc_rsecar RSECAR; + union un_rtc_bcnt0ar BCNT0AR; + }; + char wk7[1]; + union + { + union un_rtc_rminar RMINAR; + union un_rtc_bcnt1ar BCNT1AR; + }; + char wk8[1]; + union + { + union un_rtc_rhrar RHRAR; + union un_rtc_bcnt2ar BCNT2AR; + }; + char wk9[1]; + union + { + union un_rtc_rwkar RWKAR; + union un_rtc_bcnt3ar BCNT3AR; + }; + char wk10[1]; + union + { + union un_rtc_rdayar RDAYAR; + union un_rtc_bcnt0aer BCNT0AER; + }; + char wk11[1]; + union + { + union un_rtc_rmonar RMONAR; + union un_rtc_bcnt1aer BCNT1AER; + }; + char wk12[1]; + union + { + union un_rtc_ryrar RYRAR; + union un_rtc_bcnt2aer BCNT2AER; + }; + union + { + union un_rtc_ryraren RYRAREN; + union un_rtc_bcnt3aer BCNT3AER; + }; + char wk13[3]; + union un_rtc_rcr1 RCR1; + char wk14[1]; + union un_rtc_rcr2 RCR2; + char wk15[1]; + union un_rcr3 RCR3; + char wk16[1]; + union un_rtc_rcr4 RCR4; + char wk17[1]; + union un_rtc_rfrh RFRH; + union un_rtc_rfrl RFRL; + union un_rtc_radj RADJ; + char wk18[17]; + union un_rtc_rfrh RTCCR0; + char wk19[1]; + union un_rtc_rtccr1 RTCCR1; + char wk20[1]; + union un_rtc_rtccr2 RTCCR2; + char wk21[13]; + union + { + union un_rtc_rseccp0 RSECCP0; + union un_rtc_bcnt0cp0 BCNT0PC0; + }; + char wk22[1]; + union + { + union un_rtc_rmincp0 RMINCP0; + union un_rtc_bcnt1cp0 BCNT1CP0; + }; + char wk23[1]; + union + { + union un_rtc_rhrcp0 RHRCP0; + union un_rtc_bcnt2cp0 BCNT2CP0; + }; + char wk24[3]; + union + { + union un_rtc_rdaycp0 RDAYCP0; + union un_rtc_bcnt3cp0 BCNT3CP0; + }; + char wk25[1]; + union un_rtc_rmoncp0 RMONCP0; + char wk26[5]; + union + { + union un_rtc_rseccp1 RSECCP1; + union un_rtc_bcnt0cp1 BCNT0CP1; + }; + char wk27[1]; + union + { + union un_rtc_rmincp1 RMINCP1; + union un_rtc_bcnt1cp1 BCNT1CP1; + }; + char wk28[1]; + union + { + union un_rtc_rhrcp1 RHRCP1; + union un_rtc_bcnt2cp1 BCNT2CP1; + }; + char wk29[3]; + union + { + union un_rtc_rdaycp1 RDAYCP1; + union un_rtc_bcnt3cp1 BCNT3CP1; + }; + char wk30[1]; + union un_rtc_rmoncp1 RMONCP1; + char wk31[5]; + union + { + union un_rtc_rseccp2 RSECCP2; + union un_rtc_bcnt0cp2 BCNT0CP2; + }; + char wk32[1]; + union + { + union un_rtc_rmincp2 RMINCP2; + union un_rtc_bcnt1cp2 BCNT1CP2; + }; + char wk33[1]; + union + { + union un_rtc_rhrcp2 RHRCP2; + union un_rtc_bcnt2cp2 BCNT2CP2; + }; + char wk34[3]; + union + { + union un_rtc_rdaycp2 RDAYCP2; + union un_rtc_bcnt3cp2 BCNT3CP2; + }; + char wk35[1]; + union un_rtc_rmoncp2 RMONCP2; +} st_rtc_t; + +typedef struct st_sci0 +{ + union un_sci0_smr SMR; + unsigned char BRR; + union un_sci0_scr SCR; + unsigned char TDR; + union un_sci0_ssr SSR; + unsigned char RDR; + union un_sci0_scmr SCMR; + union un_sci0_semr SEMR; + union un_sci0_snfr SNFR; + union un_sci0_simr1 SIMR1; + union un_sci0_simr2 SIMR2; + union un_sci0_simr3 SIMR3; + union un_sci0_sisr SISR; + union un_sci0_spmr SPMR; + union un_sci0_tdrhl TDRHL; + union un_sci0_rdrhl RDRHL; + unsigned char MDDR; +} st_sci0_t; + +typedef struct st_system +{ + union un_mdmonr MDMONR; + char wk0[4]; + union un_syscr0 SYSCR0; + union un_syscr1 SYSCR1; + char wk1[2]; + union un_sbycr SBYCR; + char wk2[2]; + union un_mstpcra MSTPCRA; + union un_mstpcrb MSTPCRB; + union un_mstpcrc MSTPCRC; + union un_mstpcrd MSTPCRD; + union un_sckcr SCKCR; + union un_sckcr2 SCKCR2; + union un_sckcr3 SCKCR3; + union un_pllcr PLLCR; + union un_pllcr2 PLLCR2; + char wk3[5]; + union un_bckcr BCKCR; + char wk4[1]; + union un_mosccr MOSCCR; + union un_sosccr SOSCCR; + union un_lococr LOCOCR; + union un_ilococr ILOCOCR; + union un_hococr HOCOCR; + union un_hococr2 HOCOCR2; + char wk5[4]; + union un_oscovfsr OSCOVFSR; + char wk6[3]; + union un_ostdcr OSTDCR; + union un_ostdsr OSTDSR; + char wk7[94]; + union un_opccr OPCCR; + union un_rstckcr RSTCKCR; + union un_moscwtcr MOSCWTCR; + union un_soscwtcr SOSCWTCR; + char wk8[28]; + union un_rstsr2 RSTSR2; + char wk9[1]; + unsigned short SWRR; + char wk10[28]; + union un_lvd1cr1 LVD1CR1; + union un_lvd1sr LVD1SR; + union un_lvd2cr1 LVD2CR1; + union un_lvd2sr LVD2SR; + char wk11[794]; + union un_prcr PRCR; + char wk12[3100]; + union un_romwt ROMWT; + char wk13[45667]; + union un_dpsbycr DPSBYCR; + char wk14[1]; + union un_dpsier0 DPSIER0; + union un_dpsier1 DPSIER1; + union un_dpsier2 DPSIER2; + union un_dpsier3 DPSIER3; + union un_dpsifr0 DPSIFR0; + union un_dpsifr1 DPSIFR1; + union un_dpsifr2 DPSIFR2; + union un_dpsifr3 DPSIFR3; + union un_dpsiegr0 DPSIEGR0; + union un_dpsiegr1 DPSIEGR1; + union un_dpsiegr2 DPSIEGR2; + union un_dpsiegr3 DPSIEGR3; + char wk15[2]; + union un_rstsr0 RSTSR0; + union un_rstsr1 RSTSR1; + char wk16[1]; + union un_mofcr MOFCR; + union un_hocopcr HOCOPCR; + char wk17[2]; + union un_lvcmpcr LVCMPCR; + union un_lvdlvlr LVDLVLR; + char wk18[1]; + union un_lvd1cr0 LVD1CR0; + union un_lvd2cr0 LVD2CR0; + char wk19[4]; + unsigned char DPSBKR[32]; +} st_system_t; + +typedef struct st_sci10 +{ + union un_sci10_smr SMR; + unsigned char BRR; + union un_sci10_scr SCR; + unsigned char TDR; + union + { + union un_sci10_ssr SSR; + union un_sci10_ssrfifo SSRFIFO; + }; + unsigned char RDR; + union un_sci10_scmr SCMR; + union un_sci10_semr SEMR; + union un_sci10_snfr SNFR; + union un_sci10_simr1 SIMR1; + union un_sci10_simr2 SIMR2; + union un_sci10_simr3 SIMR3; + union un_sci10_sisr SISR; + union un_sci10_spmr SPMR; + union + { + union un_sci10_tdrhl TDRHL; + union un_sci10_ftdr_bit_byte FTDR; + }; + union + { + union un_sci10_rdrhl_byte RDRHL; + union un_sci10_frdr_bit_byte FRDR; + }; + unsigned char MDDR; + union un_sci10_dccr DCCR; + union un_sci10_fcr FCR; + union un_sci10_fdr FDR; + union un_sci10_lsr LSR; + union un_sci10_cdr CDR; + union st_sci10_sptr SPTR; +} st_sci10_t; + +typedef struct st_sci12 +{ + union un_sci12_smr SMR; + unsigned char BRR; + union un_sci12_scr SCR; + unsigned char TDR; + union un_sci12_ssr SSR; + unsigned char RDR; + union un_sci12_scmr SCMR; + union un_sci12_semr SEMR; + union un_sci12_snfr SNFR; + union un_sci12_simr1 SIMR1; + union un_sci12_simr2 SIMR2; + union un_sci12_simr3 SIMR3; + union un_sci12_sisr SISR; + union un_sci12_spmr SPMR; + union un_sci12_tdrhl TDRHL; + union un_sci12_rdrhl RDRHL; + unsigned char MDDR; + char wk0[13]; + union un_sci12_esmer ESMER; + union un_sci12_ctr0 CTR0; + union un_sci12_ctr1 CTR1; + union un_sci12_ctr2 CTR2; + union un_sci12_ctr3 CTR3; + union un_sci12_pcr PCR; + union un_sci12_icr ICR; + union un_sci12_str STR; + union un_sci12_stcr STCR; + unsigned char CF0DR; + union un_sci12_cf0cr CF0CR; + unsigned char CF0RR; + unsigned char PCF1DR; + unsigned char SCF1DR; + union un_sci12_cf1cr CF1CR; + unsigned char CF1RR; + union un_sci12_tcr TCR; + union un_sci12_tmr TMR; + unsigned char TPRE; + unsigned char TCNT; +} st_sci12_t; + +typedef struct st_cmtw +{ + union un_cmtw_cmwstr CMWSTR; + char wk0[2]; + union un_cmtw_cmwcr CMWCR; + char wk1[2]; + union un_cmtw_cmwior CMWIOR; + char wk2[6]; + unsigned long CMWCNT; + unsigned long CMWCOR; + unsigned long CMWICR0; + unsigned long CMWICR1; + unsigned long CMWOCR0; + unsigned long CMWOCR1; +} st_cmtw_t; + +#pragma pack() + +#endif /* __ASSEMBLER__ */ +#endif + diff --git a/arch/renesas/include/rx65n/irq.h b/arch/renesas/include/rx65n/irq.h new file mode 100644 index 00000000000..8cf9d0d9d14 --- /dev/null +++ b/arch/renesas/include/rx65n/irq.h @@ -0,0 +1,1076 @@ +/**************************************************************************** + * arch/renesas/include/rx65n/irq.h + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_RENESAS_INCLUDE_RX65N_IRQ_H +#define __ARCH_RENESAS_INCLUDE_RX65N_IRQ_H + +/* SCI */ + +#define RX_RXI_IRQ_OFFSET (0) /* RxIn */ +#define RX_TXI_IRQ_OFFSET (1) /* TxIn */ +#define RX_ERI_IRQ_OFFSET (2) /* ERIn */ +#define RX_TEI_IRQ_OFFSET (3) /* TEIn */ +#define RX_SCI_NIRQS (4) + +#define RX65N_TRAP_IRQBASE (0) +#define RX65N_TRAP0_IRQ (RX65N_TRAP_IRQBASE) +#define RX65N_TRAP1_IRQ (RX65N_TRAP_IRQBASE+1) +#define RX65N_TRAP2_IRQ (RX65N_TRAP_IRQBASE+2) +#define RX65N_TRAP3_IRQ (RX65N_TRAP_IRQBASE+3) +#define RX65N_TRAP4_IRQ (RX65N_TRAP_IRQBASE+4) +#define RX65N_TRAP5_IRQ (RX65N_TRAP_IRQBASE+5) +#define RX65N_TRAP6_IRQ (RX65N_TRAP_IRQBASE+6) +#define RX65N_TRAP7_IRQ (RX65N_TRAP_IRQBASE+7) +#define RX65N_TRAP8_IRQ (RX65N_TRAP_IRQBASE+8) +#define RX65N_TRAP9_IRQ (RX65N_TRAP_IRQBASE+9) +#define RX65N_TRAP10_IRQ (RX65N_TRAP_IRQBASE+10) +#define RX65N_TRAP11_IRQ (RX65N_TRAP_IRQBASE+11) +#define RX65N_TRAP12_IRQ (RX65N_TRAP_IRQBASE+12) +#define RX65N_TRAP13_IRQ (RX65N_TRAP_IRQBASE+13) +#define RX65N_TRAP14_IRQ (RX65N_TRAP_IRQBASE+14) +#define RX65N_TRAP15_IRQ (RX65N_TRAP_IRQBASE+15) +#define RX65N_BUSERR_IRQBASE (RX65N_TRAP_IRQBASE+16) + +#if defined(CONFIG_BSC) || defined(CONFIG_RX65N_BSC) +# define RX65N_BUSERR_IRQ (RX65N_BUSERR_IRQBASE) +# define RX65N_RAMERR_IRQBASE (RX65N_BUSERR_IRQBASE + 1) +#else +# define RX65N_RAMERR_IRQBASE (RX65N_BUSERR_IRQBASE) +#endif + +#if defined(CONFIG_RAM) || defined(CONFIG_RX65N_RAM) +# define RX65N_RAMERR_IRQ (RX65N_RAMERR_IRQBASE) +# define RX65N_FIFERR_IRQBASE (RX65N_RAMERR_IRQBASE + 1) +#else +# define RX65N_FIFERR_IRQBASE (RX65N_RAMERR_IRQBASE) +#endif + +#if defined(CONFIG_FIFERR) || defined(CONFIG_RX65N_FIFERR) +# define RX65N_FIFERR_IRQ (RX65N_FIFERR_IRQBASE) +# define RX65N_FRDYI_IRQBASE (RX65N_FIFERR_IRQBASE + 1) +#else +# define RX65N_FRDYI_IRQBASE (RX65N_FIFERR_IRQBASE) +#endif + +#if defined(CONFIG_FRDYI) || defined(CONFIG_RX65N_FRDYI) +# define RX65N_FRDYI_IRQ (RX65N_FRDYI_IRQBASE) +# define RX65N_SWINT2_IRQBASE (RX65N_FRDYI_IRQBASE + 1) +#else +# define RX65N_SWINT2_IRQBASE (RX65N_FRDYI_IRQBASE) +#endif + +# define RX65N_SWINT2_IRQ (RX65N_SWINT2_IRQBASE) +# define RX65N_SWINT_IRQBASE (RX65N_SWINT2_IRQBASE + 1) + +# define RX65N_SWINT_IRQ (RX65N_SWINT_IRQBASE) +# define RX65N_CMT0_IRQBASE (RX65N_SWINT_IRQBASE+1) + +#define RX65N_CMI0_IRQ (RX65N_CMT0_IRQBASE) +#define RX65N_CMT1_IRQBASE (RX65N_CMT0_IRQBASE + 1) + +#ifdef CONFIG_RX65N_CMT1 +# define RX65N_CMI1_IRQ (RX65N_CMT1_IRQBASE) +# define RX65N_CMTW0_IRQBASE (RX65N_CMT1_IRQBASE + 1) +#else +# define RX65N_CMTW0_IRQBASE (RX65N_CMT1_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_CMTW0 +# define RX65N_CMWI0_IRQ (RX65N_CMTW0_IRQBASE) +# define RX65N_CMTW1_IRQBASE (RX65N_CMTW0_IRQBASE + 1) +#else +# define RX65N_CMTW1_IRQBASE (RX65N_CMTW0_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_CMTW1 +# define RX65N_CMWI1_IRQ (RX65N_CMTW1_IRQBASE) +# define RX65N_USB0_IRQBASE (RX65N_CMTW1_IRQBASE + 1) +#else +# define RX65N_USB0_IRQBASE (RX65N_CMTW1_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_USB0 +# define RX65N_D0FIFO0_IRQ (RX65N_USB0_IRQBASE) +# define RX65N_D1FIFO0_IRQ (RX65N_USB0_IRQBASE + 1) +# define RX65N_RSPI0_IRQBASE (RX65N_USB0_IRQBASE + 2) +#else +# define RX65N_RSPI0_IRQBASE (RX65N_USB0_IRQBASE) +#endif +#ifdef CONFIG_RX65N_RSPI0 +# define RX65N_SPRI0_IRQ (RX65N_RSPI0_IRQBASE) +# define RX65N_SPTI0_IRQ (RX65N_RSPI0_IRQBASE + 1) +# define RX65N_RSPI1_IRQBASE (RX65N_RSPI0_IRQBASE + 2) +#else +# define RX65N_RSPI1_IRQBASE (RX65N_RSPI0_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_RSPI1 +# define RX65N_SPRI1_IRQ (RX65N_RSPI1_IRQBASE) +# define RX65N_SPTI1_IRQ (RX65N_RSPI1_IRQBASE + 1) +# define RX65N_QSPI_IRQBASE (RX65N_RSPI1_IRQBASE + 2) +#else +# define RX65N_QSPI_IRQBASE (RX65N_RSPI1_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_QSPI +# define RX65N_SPRI_IRQ (RX65N_QSPI_IRQBASE) +# define RX65N_SPTI_IRQ (RX65N_QSPI_IRQBASE + 1) +# define RX65N_SDHI_IRQBASE (RX65N_QSPI_IRQBASE + 2) +#else +# define RX65N_SDHI_IRQBASE (RX65N_QSPI_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_SDHI +# define RX65N_SBFAI_IRQ (RX65N_SDHI_IRQBASE) +# define RX65N_MMCIF_IRQBASE (RX65N_SDHI_IRQBASE + 1) +#else +# define RX65N_MMCIF_IRQBASE (RX65N_SDHI_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_MMCIF +# define RX65N_MBFAI_IRQ (RX65N_MMCIF_IRQBASE) +# define RX65N_RIIC1_IRQBASE (RX65N_MMCIF_IRQBASE + 1) +#else +# define RX65N_RIIC1_IRQBASE (RX65N_MMCIF_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_RIIC1 +# define RX65N_RIIC1_RXI1_IRQ (RX65N_RIIC1_IRQBASE + RX_RXI_IRQ_OFFSET) +# define RX65N_RIIC1_TXI1_IRQ (RX65N_RIIC1_IRQBASE + RX_TXI_IRQ_OFFSET) +# define RX65N_RIIC0_IRQBASE (RX65N_RIIC1_IRQBASE + RX_SCI_NIRQS) +#else +# define RX65N_RIIC0_IRQBASE (RX65N_RIIC1_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_RIIC0 +# define RX65N_RIIC0_RXI0_IRQ (RX65N_RIIC0_IRQBASE + RX_RXI_IRQ_OFFSET) +# define RX65N_RIIC0_TXI0_IRQ (RX65N_RIIC0_IRQBASE + RX_TXI_IRQ_OFFSET) +# define RX65N_RIIC2_IRQBASE (RX65N_RIIC0_IRQBASE + RX_SCI_NIRQS) +#else +# define RX65N_RIIC2_IRQBASE (RX65N_RIIC0_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_RIIC2 +# define RX65N_RIIC2_RXI2_IRQ (RX65N_RIIC2_IRQBASE + RX_RXI_IRQ_OFFSET) +# define RX65N_RIIC2_TXI2_IRQ (RX65N_RIIC2_IRQBASE + RX_TXI_IRQ_OFFSET) +# define RX65N_SCI0_IRQBASE (RX65N_RIIC2_IRQBASE + RX_SCI_NIRQS) +#else +# define RX65N_SCI0_IRQBASE (RX65N_RIIC2_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_SCI0 +# define RX65N_RXI0_IRQ (RX65N_SCI0_IRQBASE + RX_RXI_IRQ_OFFSET) +# define RX65N_TXI0_IRQ (RX65N_SCI0_IRQBASE + RX_TXI_IRQ_OFFSET) +# define RX65N_ERI0_IRQ (RX65N_SCI0_IRQBASE + RX_ERI_IRQ_OFFSET) +# define RX65N_TEI0_IRQ (RX65N_SCI0_IRQBASE + RX_TEI_IRQ_OFFSET) +# define RX65N_SCI1_IRQBASE (RX65N_SCI0_IRQBASE + RX_SCI_NIRQS) +#else +# define RX65N_SCI1_IRQBASE (RX65N_SCI0_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_SCI1 +# define RX65N_RXI1_IRQ (RX65N_SCI1_IRQBASE + RX_RXI_IRQ_OFFSET) +# define RX65N_TXI1_IRQ (RX65N_SCI1_IRQBASE + RX_TXI_IRQ_OFFSET) +# define RX65N_ERI1_IRQ (RX65N_SCI1_IRQBASE + RX_ERI_IRQ_OFFSET) +# define RX65N_TEI1_IRQ (RX65N_SCI1_IRQBASE + RX_TEI_IRQ_OFFSET) +# define RX65N_SCI2_IRQBASE (RX65N_SCI1_IRQBASE + RX_SCI_NIRQS) +#else +# define RX65N_SCI2_IRQBASE (RX65N_SCI1_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_SCI2 +# define RX65N_RXI2_IRQ (RX65N_SCI2_IRQBASE + RX_RXI_IRQ_OFFSET) +# define RX65N_TXI2_IRQ (RX65N_SCI2_IRQBASE + RX_TXI_IRQ_OFFSET) +# define RX65N_ERI2_IRQ (RX65N_SCI2_IRQBASE + RX_ERI_IRQ_OFFSET) +# define RX65N_TEI2_IRQ (RX65N_SCI2_IRQBASE + RX_TEI_IRQ_OFFSET) +# define RX65N_ICU_IRQ_IRQBASE (RX65N_SCI2_IRQBASE + RX_SCI_NIRQS) +#else +# define RX65N_ICU_IRQ_IRQBASE (RX65N_SCI2_IRQBASE) +#endif + +#if defined(CONFIG_ICU) || defined(CONFIG_RX65N_ICU) +# define RX65N_IRQ0_IRQ (RX65N_ICU_IRQ_IRQBASE) +# define RX65N_IRQ1_IRQ (RX65N_ICU_IRQ_IRQBASE+1) +# define RX65N_IRQ2_IRQ (RX65N_ICU_IRQ_IRQBASE+2) +# define RX65N_IRQ3_IRQ (RX65N_ICU_IRQ_IRQBASE+3) +# define RX65N_IRQ4_IRQ (RX65N_ICU_IRQ_IRQBASE+4) +# define RX65N_IRQ5_IRQ (RX65N_ICU_IRQ_IRQBASE+5) +# define RX65N_IRQ6_IRQ (RX65N_ICU_IRQ_IRQBASE+6) +# define RX65N_IRQ7_IRQ (RX65N_ICU_IRQ_IRQBASE+7) +# define RX65N_IRQ8_IRQ (RX65N_ICU_IRQ_IRQBASE+8) +# define RX65N_IRQ9_IRQ (RX65N_ICU_IRQ_IRQBASE+9) +# define RX65N_IRQ10_IRQ (RX65N_ICU_IRQ_IRQBASE+10) +# define RX65N_IRQ11_IRQ (RX65N_ICU_IRQ_IRQBASE+11) +# define RX65N_IRQ12_IRQ (RX65N_ICU_IRQ_IRQBASE+12) +# define RX65N_IRQ13_IRQ (RX65N_ICU_IRQ_IRQBASE+13) +# define RX65N_IRQ14_IRQ (RX65N_ICU_IRQ_IRQBASE+14) +# define RX65N_IRQ15_IRQ (RX65N_ICU_IRQ_IRQBASE+15) +# define RX65N_SCI3_IRQBASE (RX65N_ICU_IRQ_IRQBASE+16) +#else +# define RX65N_SCI3_IRQBASE (RX65N_ICU_IRQ_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_SCI3 +# define RX65N_RXI3_IRQ (RX65N_SCI3_IRQBASE + RX_RXI_IRQ_OFFSET) +# define RX65N_TXI3_IRQ (RX65N_SCI3_IRQBASE + RX_TXI_IRQ_OFFSET) +# define RX65N_ERI3_IRQ (RX65N_SCI3_IRQBASE + RX_ERI_IRQ_OFFSET) +# define RX65N_TEI3_IRQ (RX65N_SCI3_IRQBASE + RX_TEI_IRQ_OFFSET) +# define RX65N_SCI4_IRQBASE (RX65N_SCI3_IRQBASE + RX_SCI_NIRQS) +#else +# define RX65N_SCI4_IRQBASE (RX65N_SCI3_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_SCI4 +# define RX65N_RXI4_IRQ (RX65N_SCI4_IRQBASE + RX_RXI_IRQ_OFFSET) +# define RX65N_TXI4_IRQ (RX65N_SCI4_IRQBASE + RX_TXI_IRQ_OFFSET) +# define RX65N_ERI4_IRQ (RX65N_SCI4_IRQBASE + RX_ERI_IRQ_OFFSET) +# define RX65N_TEI4_IRQ (RX65N_SCI4_IRQBASE + RX_TEI_IRQ_OFFSET) +# define RX65N_SCI5_IRQBASE (RX65N_SCI4_IRQBASE + RX_SCI_NIRQS) +#else +# define RX65N_SCI5_IRQBASE (RX65N_SCI4_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_SCI5 +# define RX65N_RXI5_IRQ (RX65N_SCI5_IRQBASE + RX_RXI_IRQ_OFFSET) +# define RX65N_TXI5_IRQ (RX65N_SCI5_IRQBASE + RX_TXI_IRQ_OFFSET) +# define RX65N_ERI5_IRQ (RX65N_SCI5_IRQBASE + RX_ERI_IRQ_OFFSET) +# define RX65N_TEI5_IRQ (RX65N_SCI5_IRQBASE + RX_TEI_IRQ_OFFSET) +# define RX65N_SCI6_IRQBASE (RX65N_SCI5_IRQBASE + RX_SCI_NIRQS) +#else +# define RX65N_SCI6_IRQBASE (RX65N_SCI5_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_SCI6 +# define RX65N_RXI6_IRQ (RX65N_SCI6_IRQBASE + RX_RXI_IRQ_OFFSET) +# define RX65N_TXI6_IRQ (RX65N_SCI6_IRQBASE + RX_TXI_IRQ_OFFSET) +# define RX65N_ERI6_IRQ (RX65N_SCI6_IRQBASE + RX_ERI_IRQ_OFFSET) +# define RX65N_TEI6_IRQ (RX65N_SCI6_IRQBASE + RX_TEI_IRQ_OFFSET) +# define RX65N_LVD1_IRQBASE (RX65N_SCI6_IRQBASE + RX_SCI_NIRQS) +#else +# define RX65N_LVD1_IRQBASE (RX65N_SCI6_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_LVD1 +# define RX65N_LVD1_IRQ (RX65N_LVD1_IRQBASE) +# define RX65N_LVD2_IRQBASE (RX65N_LVD1_IRQBASE + 1) +#else +# define RX65N_LVD2_IRQBASE (RX65N_LVD1_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_LVD2 +# define RX65N_LVD2_IRQ (RX65N_LVD2_IRQBASE) +# define RX65N_USB0_R0_IRQBASE (RX65N_LVD2_IRQBASE + 1) +#else +# define RX65N_USB0_R0_IRQBASE (RX65N_LVD2_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_USB0_R0 +# define RX65N_USBR0_IRQ (RX65N_USB0_R0_IRQBASE) +# define RX65N_RTC_IRQBASE (RX65N_USB0_R0_IRQBASE) +#else +# define RX65N_RTC_IRQBASE (RX65N_USB0_R0_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_RTC +# define RX65N_ALM_IRQ (RX65N_RTC_IRQBASE) +# define RX65N_PRD_IRQ (RX65N_RTC_IRQBASE + 1) +# define RX65N_IWDT_IRQBASE (RX65N_RTC_IRQBASE + 2) +#else +# define RX65N_IWDT_IRQBASE (RX65N_RTC_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_IWDT +# define RX65N_IWUNI_IRQ (RX65N_IWDT_IRQBASE) +# define RX65N_WDT_IRQBASE (RX65N_IWDT_IRQBASE + 1) +#else +# define RX65N_WDT_IRQBASE (RX65N_IWDT_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_WDT +# define RX65N_WUNI_IRQ (RX65N_WDT_IRQBASE) +# define RX65N_PDC_IRQBASE (RX65N_WDT_IRQBASE + 1) +#else +# define RX65N_PDC_IRQBASE (RX65N_WDT_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_PDC +# define RX65N_PCDFI_IRQ (RX65N_PDC_IRQBASE) +# define RX65N_SCI7_IRQBASE (RX65N_PDC_IRQBASE + 1) +#else +# define RX65N_SCI7_IRQBASE (RX65N_PDC_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_SCI7 +# define RX65N_RXI7_IRQ (RX65N_SCI7_IRQBASE + RX_RXI_IRQ_OFFSET) +# define RX65N_TXI7_IRQ (RX65N_SCI7_IRQBASE + RX_TXI_IRQ_OFFSET) +# define RX65N_ERI7_IRQ (RX65N_SCI7_IRQBASE + RX_ERI_IRQ_OFFSET) +# define RX65N_TEI7_IRQ (RX65N_SCI7_IRQBASE + RX_TEI_IRQ_OFFSET) +# define RX65N_SCI8_IRQBASE (RX65N_SCI7_IRQBASE + RX_SCI_NIRQS) +#else +# define RX65N_SCI8_IRQBASE (RX65N_SCI7_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_SCI8 +# define RX65N_RXI8_IRQ (RX65N_SCI8_IRQBASE + RX_RXI_IRQ_OFFSET) +# define RX65N_TXI8_IRQ (RX65N_SCI8_IRQBASE + RX_TXI_IRQ_OFFSET) +# define RX65N_ERI8_IRQ (RX65N_SCI8_IRQBASE + RX_ERI_IRQ_OFFSET) +# define RX65N_TEI8_IRQ (RX65N_SCI8_IRQBASE + RX_TEI_IRQ_OFFSET) +# define RX65N_SCI9_IRQBASE (RX65N_SCI8_IRQBASE + RX_SCI_NIRQS) +#else +# define RX65N_SCI9_IRQBASE (RX65N_SCI8_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_SCI9 +# define RX65N_RXI9_IRQ (RX65N_SCI9_IRQBASE + RX_RXI_IRQ_OFFSET) +# define RX65N_TXI9_IRQ (RX65N_SCI9_IRQBASE + RX_TXI_IRQ_OFFSET) +# define RX65N_ERI9_IRQ (RX65N_SCI9_IRQBASE + RX_ERI_IRQ_OFFSET) +# define RX65N_TEI9_IRQ (RX65N_SCI9_IRQBASE + RX_TEI_IRQ_OFFSET) +# define RX65N_SCI10_IRQBASE (RX65N_SCI9_IRQBASE + RX_SCI_NIRQS) +#else +# define RX65N_SCI10_IRQBASE (RX65N_SCI9_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_SCI10 +# define RX65N_RXI10_IRQ (RX65N_SCI10_IRQBASE + RX_RXI_IRQ_OFFSET) +# define RX65N_TXI10_IRQ (RX65N_SCI10_IRQBASE + RX_TXI_IRQ_OFFSET) +# define RX65N_ERI10_IRQ (RX65N_SCI10_IRQBASE + RX_ERI_IRQ_OFFSET) +# define RX65N_TEI10_IRQ (RX65N_SCI10_IRQBASE + RX_TEI_IRQ_OFFSET) +# define RX65N_IRQ_GROUPB_IRQBASE (RX65N_SCI10_IRQBASE + RX_SCI_NIRQS) +#else +# define RX65N_IRQ_GROUPB_IRQBASE (RX65N_SCI10_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_IRQ_GROUP +# define RX65N_GROUPBE0_IRQ (RX65N_IRQ_GROUPB_IRQBASE) +# define RX65N_GROUPBL2_IRQ (RX65N_IRQ_GROUPB_IRQBASE + 1) +# define RX65N_RSPI2_IRQBASE (RX65N_IRQ_GROUPB_IRQBASE + 2) +#else +# define RX65N_RSPI2_IRQBASE (RX65N_IRQ_GROUPB_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_RSPI2 +# define RX65N_SPRI2_IRQ (RX65N_RSPI2_IRQBASE) +# define RX65N_SPTI2_IRQ (RX65N_RSPI2_IRQBASE + 1) +# define RX65N_IRQ_GROUPBL_IRQBASE (RX65N_RSPI2_IRQBASE + 2) +#else +# define RX65N_IRQ_GROUPBL_IRQBASE (RX65N_RSPI2_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_IRQ_GROUP +# define RX65N_GROUPBL0_IRQ (RX65N_IRQ_GROUPBL_IRQBASE) +# define RX65N_GROUPBL1_IRQ (RX65N_IRQ_GROUPBL_IRQBASE + 1) +# define RX65N_GROUPAL0_IRQ (RX65N_IRQ_GROUPBL_IRQBASE + 2) +# define RX65N_GROUPAL1_IRQ (RX65N_IRQ_GROUPBL_IRQBASE + 3) +# define RX65N_ETH_IRQBASE (RX65N_IRQ_GROUPBL_IRQBASE + 4) +#else +# define RX65N_ETH_IRQBASE (RX65N_IRQ_GROUPBL_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_EMAC0 +# define RX65N_ETH_IRQ RX65N_ETH_IRQBASE +# define RX65N_SCI11_IRQBASE (RX65N_ETH_IRQBASE + 1) +#else +# define RX65N_SCI11_IRQBASE (RX65N_ETH_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_SCI11 +# define RX65N_RXI11_IRQ (RX65N_SCI11_IRQBASE + RX_RXI_IRQ_OFFSET) +# define RX65N_TXI11_IRQ (RX65N_SCI11_IRQBASE + RX_TXI_IRQ_OFFSET) +# define RX65N_ERI11_IRQ (RX65N_SCI11_IRQBASE + RX_ERI_IRQ_OFFSET) +# define RX65N_TEI11_IRQ (RX65N_SCI11_IRQBASE + RX_TEI_IRQ_OFFSET) +# define RX65N_SCI12_IRQBASE (RX65N_SCI11_IRQBASE + RX_SCI_NIRQS) +#else +# define RX65N_SCI12_IRQBASE (RX65N_SCI11_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_SCI12 +# define RX65N_RXI12_IRQ (RX65N_SCI12_IRQBASE + RX_RXI_IRQ_OFFSET) +# define RX65N_TXI12_IRQ (RX65N_SCI12_IRQBASE + RX_TXI_IRQ_OFFSET) +# define RX65N_ERI12_IRQ (RX65N_SCI12_IRQBASE + RX_ERI_IRQ_OFFSET) +# define RX65N_TEI12_IRQ (RX65N_SCI12_IRQBASE + RX_TEI_IRQ_OFFSET) +# define RX65N_DMAC_IRQBASE (RX65N_SCI12_IRQBASE + RX_SCI_NIRQS) +#else +# define RX65N_DMAC_IRQBASE (RX65N_SCI12_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_DMAC +# define RX65N_DMAC0I_IRQ (RX65N_DMAC_IRQBASE) +# define RX65N_DMAC1I_IRQ (RX65N_DMAC_IRQBASE + 1) +# define RX65N_DMAC2I_IRQ (RX65N_DMAC_IRQBASE + 2) +# define RX65N_DMAC3I_IRQ (RX65N_DMAC_IRQBASE + 3) +# define RX65N_DMAC74I_IRQ (RX65N_DMAC_IRQBASE + 4) +# define RX65N_OST_IRQBASE (RX65N_DMAC_IRQBASE + 5) +#else +# define RX65N_OST_IRQBASE (RX65N_DMAC_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_OST +# define RX65N_OSTD1_IRQ (RX65N_OST_IRQBASE) +# define RX65N_EXDMAC_IRQBASE (RX65N_OST_IRQBASE + 1) +#else +# define RX65N_EXDMAC_IRQBASE (RX65N_OST_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_EXDMAC +# define RX65N_EXDMAC0I_IRQ (RX65N_EXDMAC_IRQBASE) +# define RX65N_EXDMAC1I_IRQ (RX65N_EXDMAC_IRQBASE + 1) +# define RX65N_PERIB_IRQBASE (RX65N_EXDMAC_IRQBASE + 2) +#else +# define RX65N_PERIB_IRQBASE (RX65N_EXDMAC_IRQBASE) +#endif + +# ifdef CONFIG_RX65N_PERIB +# define RX65N_INTB128_IRQ (RX65N_PERIB_IRQBASE) +# define RX65N_INTB129_IRQ (RX65N_PERIB_IRQBASE + 1) +# define RX65N_INTB130_IRQ (RX65N_PERIB_IRQBASE + 2) +# define RX65N_INTB131_IRQ (RX65N_PERIB_IRQBASE + 3) +# define RX65N_INTB132_IRQ (RX65N_PERIB_IRQBASE + 4) +# define RX65N_INTB133_IRQ (RX65N_PERIB_IRQBASE + 5) +# define RX65N_INTB134_IRQ (RX65N_PERIB_IRQBASE + 6) +# define RX65N_INTB135_IRQ (RX65N_PERIB_IRQBASE + 7) +# define RX65N_INTB136_IRQ (RX65N_PERIB_IRQBASE + 8) +# define RX65N_INTB137_IRQ (RX65N_PERIB_IRQBASE + 9) +# define RX65N_INTB138_IRQ (RX65N_PERIB_IRQBASE + 10) +# define RX65N_INTB139_IRQ (RX65N_PERIB_IRQBASE + 11) +# define RX65N_INTB140_IRQ (RX65N_PERIB_IRQBASE + 12) +# define RX65N_INTB141_IRQ (RX65N_PERIB_IRQBASE + 13) +# define RX65N_INTB142_IRQ (RX65N_PERIB_IRQBASE + 14) +# define RX65N_INTB143_IRQ (RX65N_PERIB_IRQBASE + 15) +# define RX65N_INTB144_IRQ (RX65N_PERIB_IRQBASE + 16) +# define RX65N_INTB145_IRQ (RX65N_PERIB_IRQBASE + 17) +# define RX65N_INTB146_IRQ (RX65N_PERIB_IRQBASE + 18) +# define RX65N_INTB147_IRQ (RX65N_PERIB_IRQBASE + 19) +# define RX65N_INTB148_IRQ (RX65N_PERIB_IRQBASE + 20) +# define RX65N_INTB149_IRQ (RX65N_PERIB_IRQBASE + 21) +# define RX65N_INTB150_IRQ (RX65N_PERIB_IRQBASE + 22) +# define RX65N_INTB151_IRQ (RX65N_PERIB_IRQBASE + 23) +# define RX65N_INTB152_IRQ (RX65N_PERIB_IRQBASE + 24) +# define RX65N_INTB153_IRQ (RX65N_PERIB_IRQBASE + 25) +# define RX65N_INTB154_IRQ (RX65N_PERIB_IRQBASE + 26) +# define RX65N_INTB155_IRQ (RX65N_PERIB_IRQBASE + 27) +# define RX65N_INTB156_IRQ (RX65N_PERIB_IRQBASE + 28) +# define RX65N_INTB157_IRQ (RX65N_PERIB_IRQBASE + 29) +# define RX65N_INTB158_IRQ (RX65N_PERIB_IRQBASE + 30) +# define RX65N_INTB159_IRQ (RX65N_PERIB_IRQBASE + 31) +# define RX65N_INTB160_IRQ (RX65N_PERIB_IRQBASE + 32) +# define RX65N_INTB161_IRQ (RX65N_PERIB_IRQBASE + 33) +# define RX65N_INTB162_IRQ (RX65N_PERIB_IRQBASE + 34) +# define RX65N_INTB163_IRQ (RX65N_PERIB_IRQBASE + 35) +# define RX65N_INTB164_IRQ (RX65N_PERIB_IRQBASE + 36) +# define RX65N_INTB165_IRQ (RX65N_PERIB_IRQBASE + 37) +# define RX65N_INTB166_IRQ (RX65N_PERIB_IRQBASE + 38) +# define RX65N_INTB167_IRQ (RX65N_PERIB_IRQBASE + 39) +# define RX65N_INTB168_IRQ (RX65N_PERIB_IRQBASE + 40) +# define RX65N_INTB169_IRQ (RX65N_PERIB_IRQBASE + 41) + +/* using for CONFIG_RX65N_CMTW0 */ + +# define RX65N_INTB170_IRQ (RX65N_PERIB_IRQBASE + 42) + +/* using for CONFIG_RX65N_CMTW1 */ + +# define RX65N_INTB171_IRQ (RX65N_PERIB_IRQBASE + 43) +# define RX65N_INTB172_IRQ (RX65N_PERIB_IRQBASE + 44) +# define RX65N_INTB173_IRQ (RX65N_PERIB_IRQBASE + 45) +# define RX65N_INTB174_IRQ (RX65N_PERIB_IRQBASE + 46) +# define RX65N_INTB175_IRQ (RX65N_PERIB_IRQBASE + 47) +# define RX65N_INTB176_IRQ (RX65N_PERIB_IRQBASE + 48) +# define RX65N_INTB177_IRQ (RX65N_PERIB_IRQBASE + 49) +# define RX65N_INTB178_IRQ (RX65N_PERIB_IRQBASE + 50) +# define RX65N_INTB179_IRQ (RX65N_PERIB_IRQBASE + 51) +# define RX65N_INTB180_IRQ (RX65N_PERIB_IRQBASE + 52) +# define RX65N_INTB181_IRQ (RX65N_PERIB_IRQBASE + 53) +# define RX65N_INTB182_IRQ (RX65N_PERIB_IRQBASE + 54) +# define RX65N_INTB183_IRQ (RX65N_PERIB_IRQBASE + 55) +# define RX65N_INTB184_IRQ (RX65N_PERIB_IRQBASE + 56) +# define RX65N_INTB185_IRQ (RX65N_PERIB_IRQBASE + 57) +# define RX65N_INTB186_IRQ (RX65N_PERIB_IRQBASE + 58) +# define RX65N_INTB187_IRQ (RX65N_PERIB_IRQBASE + 59) +# define RX65N_INTB188_IRQ (RX65N_PERIB_IRQBASE + 60) +# define RX65N_INTB189_IRQ (RX65N_PERIB_IRQBASE + 61) +# define RX65N_INTB190_IRQ (RX65N_PERIB_IRQBASE + 62) +# define RX65N_INTB191_IRQ (RX65N_PERIB_IRQBASE + 63) +# define RX65N_INTB192_IRQ (RX65N_PERIB_IRQBASE + 64) +# define RX65N_INTB193_IRQ (RX65N_PERIB_IRQBASE + 65) +# define RX65N_INTB194_IRQ (RX65N_PERIB_IRQBASE + 66) +# define RX65N_INTB195_IRQ (RX65N_PERIB_IRQBASE + 67) +# define RX65N_INTB196_IRQ (RX65N_PERIB_IRQBASE + 68) +# define RX65N_INTB197_IRQ (RX65N_PERIB_IRQBASE + 69) +# define RX65N_INTB198_IRQ (RX65N_PERIB_IRQBASE + 70) +# define RX65N_INTB199_IRQ (RX65N_PERIB_IRQBASE + 71) +# define RX65N_INTB200_IRQ (RX65N_PERIB_IRQBASE + 72) +# define RX65N_INTB201_IRQ (RX65N_PERIB_IRQBASE + 73) +# define RX65N_INTB202_IRQ (RX65N_PERIB_IRQBASE + 74) +# define RX65N_INTB203_IRQ (RX65N_PERIB_IRQBASE + 75) +# define RX65N_INTB204_IRQ (RX65N_PERIB_IRQBASE + 76) +# define RX65N_INTB205_IRQ (RX65N_PERIB_IRQBASE + 77) +# define RX65N_INTB206_IRQ (RX65N_PERIB_IRQBASE + 78) +# define RX65N_INTB207_IRQ (RX65N_PERIB_IRQBASE + 79) +# define RX65N_PERIA_IRQBASE (RX65N_PERIB_IRQBASE + 80) +#else +# define RX65N_PERIA_IRQBASE (RX65N_PERIB_IRQBASE) +#endif + +#ifdef CONFIG_RX65N_PERIA +# define RX65N_INTA208_IRQ (RX65N_PERIA_IRQBASE) +# define RX65N_INTA209_IRQ (RX65N_PERIA_IRQBASE + 1) +# define RX65N_INTA210_IRQ (RX65N_PERIA_IRQBASE + 2) +# define RX65N_INTA211_IRQ (RX65N_PERIA_IRQBASE + 3) +# define RX65N_INTA212_IRQ (RX65N_PERIA_IRQBASE + 4) +# define RX65N_INTA213_IRQ (RX65N_PERIA_IRQBASE + 5) +# define RX65N_INTA214_IRQ (RX65N_PERIA_IRQBASE + 6) +# define RX65N_INTA215_IRQ (RX65N_PERIA_IRQBASE + 7) +# define RX65N_INTA216_IRQ (RX65N_PERIA_IRQBASE + 8) +# define RX65N_INTA217_IRQ (RX65N_PERIA_IRQBASE + 9) +# define RX65N_INTA218_IRQ (RX65N_PERIA_IRQBASE + 10) +# define RX65N_INTA219_IRQ (RX65N_PERIA_IRQBASE + 11) +# define RX65N_INTA220_IRQ (RX65N_PERIA_IRQBASE + 12) +# define RX65N_INTA221_IRQ (RX65N_PERIA_IRQBASE + 13) +# define RX65N_INTA222_IRQ (RX65N_PERIA_IRQBASE + 14) +# define RX65N_INTA223_IRQ (RX65N_PERIA_IRQBASE + 15) +# define RX65N_INTA224_IRQ (RX65N_PERIA_IRQBASE + 16) +# define RX65N_INTA225_IRQ (RX65N_PERIA_IRQBASE + 17) +# define RX65N_INTA226_IRQ (RX65N_PERIA_IRQBASE + 18) +# define RX65N_INTA227_IRQ (RX65N_PERIA_IRQBASE + 19) +# define RX65N_INTA228_IRQ (RX65N_PERIA_IRQBASE + 20) +# define RX65N_INTA229_IRQ (RX65N_PERIA_IRQBASE + 21) +# define RX65N_INTA230_IRQ (RX65N_PERIA_IRQBASE + 22) +# define RX65N_INTA231_IRQ (RX65N_PERIA_IRQBASE + 23) +# define RX65N_INTA232_IRQ (RX65N_PERIA_IRQBASE + 24) +# define RX65N_INTA233_IRQ (RX65N_PERIA_IRQBASE + 25) +# define RX65N_INTA234_IRQ (RX65N_PERIA_IRQBASE + 26) +# define RX65N_INTA235_IRQ (RX65N_PERIA_IRQBASE + 27) +# define RX65N_INTA236_IRQ (RX65N_PERIA_IRQBASE + 28) +# define RX65N_INTA237_IRQ (RX65N_PERIA_IRQBASE + 29) +# define RX65N_INTA238_IRQ (RX65N_PERIA_IRQBASE + 30) +# define RX65N_INTA239_IRQ (RX65N_PERIA_IRQBASE + 31) +# define RX65N_INTA240_IRQ (RX65N_PERIA_IRQBASE + 32) +# define RX65N_INTA241_IRQ (RX65N_PERIA_IRQBASE + 33) +# define RX65N_INTA242_IRQ (RX65N_PERIA_IRQBASE + 34) +# define RX65N_INTA243_IRQ (RX65N_PERIA_IRQBASE + 35) +# define RX65N_INTA244_IRQ (RX65N_PERIA_IRQBASE + 36) +# define RX65N_INTA245_IRQ (RX65N_PERIA_IRQBASE + 37) +# define RX65N_INTA246_IRQ (RX65N_PERIA_IRQBASE + 38) +# define RX65N_INTA247_IRQ (RX65N_PERIA_IRQBASE + 39) +# define RX65N_INTA248_IRQ (RX65N_PERIA_IRQBASE + 40) +# define RX65N_INTA249_IRQ (RX65N_PERIA_IRQBASE + 41) +# define RX65N_INTA250_IRQ (RX65N_PERIA_IRQBASE + 42) +# define RX65N_INTA251_IRQ (RX65N_PERIA_IRQBASE + 43) +# define RX65N_INTA252_IRQ (RX65N_PERIA_IRQBASE + 44) +# define RX65N_INTA253_IRQ (RX65N_PERIA_IRQBASE + 45) +# define RX65N_INTA254_IRQ (RX65N_PERIA_IRQBASE + 46) +# define RX65N_INTA255_IRQ (RX65N_PERIA_IRQBASE + 47) +# define NR_IRQS (RX65N_PERIA_IRQBASE + 48) +#else +# define NR_IRQS (RX65N_PERIA_IRQBASE) +#endif + +/* IRQ Stack Frame Format. The RX65N has a push down stack. The PC + * and SR are pushed by hardware at the time an IRQ is taken. + */ + +/* Saved to the stacked by up_vector */ + +/* Vector table offets **************************************************************/ + +/* Trap instruction */ + +#define RX65N_TRAP_VNDX (0) +#define RX65N_TRAP0_VNDX (RX65N_TRAP_VNDX) +#define RX65N_TRAP1_VNDX (RX65N_TRAP_VNDX + 1) +#define RX65N_TRAP2_VNDX (RX65N_TRAP_VNDX + 2) +#define RX65N_TRAP3_VNDX (RX65N_TRAP_VNDX + 3) +#define RX65N_TRAP4_VNDX (RX65N_TRAP_VNDX + 4) +#define RX65N_TRAP5_VNDX (RX65N_TRAP_VNDX + 5) +#define RX65N_TRAP6_VNDX (RX65N_TRAP_VNDX + 6) +#define RX65N_TRAP7_VNDX (RX65N_TRAP_VNDX + 7) +#define RX65N_TRAP8_VNDX (RX65N_TRAP_VNDX + 8) +#define RX65N_TRAP9_VNDX (RX65N_TRAP_VNDX + 9) +#define RX65N_TRAP10_VNDX (RX65N_TRAP_VNDX + 10) +#define RX65N_TRAP11_VNDX (RX65N_TRAP_VNDX + 11) +#define RX65N_TRAP12_VNDX (RX65N_TRAP_VNDX + 12) +#define RX65N_TRAP13_VNDX (RX65N_TRAP_VNDX + 13) +#define RX65N_TRAP14_VNDX (RX65N_TRAP_VNDX + 14) +#define RX65N_TRAP15_VNDX (RX65N_TRAP_VNDX + 15) + +/* Bus Error */ + +# define RX65N_BUSERR_VNDX (VECT_BSC_BUSERR) + +/* RAM Error */ + +#define RX65N_RAMERR_VNDX (VECT_RAM_RAMERR) + +/* FIFERR Error */ + +#define RX65N_FIFERR_VNDX (VECT_FCU_FIFERR) + +/* FRDYI */ + +#define RX65N_FRDYI_VNDX (VECT_FCU_FRDYI) + +/* ICU Interrupts */ + +#define RX65N_SWINT2_VNDX (VECT_ICU_SWINT2) +#define RX65N_SWINT_VNDX (VECT_ICU_SWINT) +#define RX65N_IRQ0_VNDX (VECT_ICU_IRQ0) +#define RX65N_IRQ1_VNDX (VECT_ICU_IRQ1) +#define RX65N_IRQ2_VNDX (VECT_ICU_IRQ2) +#define RX65N_IRQ3_VNDX (VECT_ICU_IRQ3) +#define RX65N_IRQ4_VNDX (VECT_ICU_IRQ4) +#define RX65N_IRQ5_VNDX (VECT_ICU_IRQ5) +#define RX65N_IRQ6_VNDX (VECT_ICU_IRQ6) +#define RX65N_IRQ7_VNDX (VECT_ICU_IRQ7) +#define RX65N_IRQ8_VNDX (VECT_ICU_IRQ8) +#define RX65N_IRQ9_VNDX (VECT_ICU_IRQ9) +#define RX65N_IRQ10_VNDX (VECT_ICU_IRQ10) +#define RX65N_IRQ11_VNDX (VECT_ICU_IRQ11) +#define RX65N_IRQ12_VNDX (VECT_ICU_IRQ12) +#define RX65N_IRQ13_VNDX (VECT_ICU_IRQ13) +#define RX65N_IRQ14_VNDX (VECT_ICU_IRQ14) +#define RX65N_IRQ15_VNDX (VECT_ICU_IRQ15) +#define RX65N_GROUPBE0_VNDX (VECT_ICU_GROUPBE0) +#define RX65N_GROUPBL0_VNDX (VECT_ICU_GROUPBL0) +#define RX65N_GROUPBL1_VNDX (VECT_ICU_GROUPBL1) +#define RX65N_GROUPBL2_VNDX (VECT_ICU_GROUPBL2) +#define RX65N_GROUPAL0_VNDX (VECT_ICU_GROUPAL0) +#define RX65N_GROUPAL1_VNDX (VECT_ICU_GROUPAL1) + +/* CMT Interrupts */ + +#define RX65N_CMI0_VNDX (VECT_CMT0_CMI0) +#define RX65N_CMI1_VNDX (VECT_CMT0_CMI1) +#define RX65N_CMWI0_VNDX (VECT_CMT0_CMWI0) +#define RX65N_CMWI1_VNDX (VECT_CMT0_CMWI1) + +/* USB Interrupts */ + +#define RX65N_D0FIFO0_VNDX (VECT_USB0_D0FIFO0) +#define RX65N_D1FIFO0_VNDX (VECT_USB0_D1FIFO0) +#define RX65N_USBR0_VNDX (VECT_USB0_USBR0) + +/* RSPI Interrupts */ + +#define RX65N_SPRI0_VNDX (VECT_RSPI0_SPRI0) +#define RX65N_SPTI0_VNDX (VECT_RSPI0_SPTI0) +#define RX65N_SPRI1_VNDX (VECT_RSPI1_SPRI1) +#define RX65N_SPTI1_VNDX (VECT_RSPI1_SPTI1) +#define RX65N_SPRI2_VNDX (VECT_RSPI2_SPRI2) +#define RX65N_SPTI2_VNDX (VECT_RSPI2_SPTI2) + +/* QSPI Interrupts */ + +#define RX65N_SPRI_VNDX (VECT_QSPI_SPRI) +#define RX65N_SPTI_VNDX (VECT_QSPI_SPTI) + +/* SDHI MMC Interrupts */ + +#define RX65N_SBFAI_VNDX (VECT_SDHI_SBFAI) +#define RX65N_MBFAI_VNDX (VECT_MMCIF_MBFAI) + +/* RIIC Interrupts */ + +#define RX65N_RIIC0_EEI0_VNDX (VECT_ICU_GROUPBL1) +#define RX65N_RIIC0_RXI0_VNDX (VECT_RIIC0_RXI0) +#define RX65N_RIIC0_TXI0_VNDX (VECT_RIIC0_TXI0) +#define RX65N_RIIC0_TEI0_VNDX (VECT_ICU_GROUPBL1) + +#define RX65N_RIIC1_EEI1_VNDX (VECT_ICU_GROUPBL1) +#define RX65N_RIIC1_RXI1_VNDX (VECT_RIIC1_RXI1) +#define RX65N_RIIC1_TXI1_VNDX (VECT_RIIC1_TXI1) +#define RX65N_RIIC1_TEI1_VNDX (VECT_ICU_GROUPBL1) + +#define RX65N_RIIC2_EEI2_VNDX (VECT_ICU_GROUPBL1) +#define RX65N_RIIC2_RXI2_VNDX (VECT_RIIC2_RXI2) +#define RX65N_RIIC2_TXI2_VNDX (VECT_RIIC2_TXI2) +#define RX65N_RIIC2_TEI2_VNDX (VECT_ICU_GROUPBL1) + +/* SCI Interrupts */ + +#define RX65N_ERI0_VNDX (VECT_ICU_GROUPBL0) +#define RX65N_RXI0_VNDX (VECT_SCI0_RXI0) +#define RX65N_TXI0_VNDX (VECT_SCI0_TXI0) +#define RX65N_TEI0_VNDX (VECT_ICU_GROUPBL0) + +#define RX65N_ERI1_VNDX (VECT_ICU_GROUPBL0) +#define RX65N_RXI1_VNDX (VECT_SCI1_RXI1) +#define RX65N_TXI1_VNDX (VECT_SCI1_TXI1) +#define RX65N_TEI1_VNDX (VECT_ICU_GROUPBL0) + +#define RX65N_ERI2_VNDX (VECT_ICU_GROUPBL0) +#define RX65N_RXI2_VNDX (VECT_SCI2_RXI2) +#define RX65N_TXI2_VNDX (VECT_SCI2_TXI2) +#define RX65N_TEI2_VNDX (VECT_ICU_GROUPBL0) + +#define RX65N_ERI3_VNDX (VECT_ICU_GROUPBL0) +#define RX65N_RXI3_VNDX (VECT_SCI3_RXI3) +#define RX65N_TXI3_VNDX (VECT_SCI3_TXI3) +#define RX65N_TEI3_VNDX (VECT_ICU_GROUPBL0) + +#define RX65N_ERI4_VNDX (VECT_ICU_GROUPBL0) +#define RX65N_RXI4_VNDX (VECT_SCI4_RXI4) +#define RX65N_TXI4_VNDX (VECT_SCI4_TXI4) +#define RX65N_TEI4_VNDX (VECT_ICU_GROUPBL0) + +#define RX65N_ERI5_VNDX (VECT_ICU_GROUPBL0) +#define RX65N_RXI5_VNDX (VECT_SCI5_RXI5) +#define RX65N_TXI5_VNDX (VECT_SCI5_TXI5) +#define RX65N_TEI5_VNDX (VECT_ICU_GROUPBL0) + +#define RX65N_ERI6_VNDX (VECT_ICU_GROUPBL0) +#define RX65N_RXI6_VNDX (VECT_SCI6_RXI6) +#define RX65N_TXI6_VNDX (VECT_SCI6_TXI6) +#define RX65N_TEI6_VNDX (VECT_ICU_GROUPBL0) + +#define RX65N_ERI7_VNDX (VECT_ICU_GROUPBL0) +#define RX65N_RXI7_VNDX (VECT_SCI7_RXI7) +#define RX65N_TXI7_VNDX (VECT_SCI7_TXI7) +#define RX65N_TEI7_VNDX (VECT_ICU_GROUPBL0) + +#define RX65N_ERI8_VNDX (VECT_ICU_GROUPBL1) +#define RX65N_RXI8_VNDX (VECT_SCI8_RXI8) +#define RX65N_TXI8_VNDX (VECT_SCI8_TXI8) +#define RX65N_TEI8_VNDX (VECT_ICU_GROUPBL1) + +#define RX65N_ERI9_VNDX (VECT_ICU_GROUPBL1) +#define RX65N_RXI9_VNDX (VECT_SCI9_RXI9) +#define RX65N_TXI9_VNDX (VECT_SCI9_TXI9) +#define RX65N_TEI9_VNDX (VECT_ICU_GROUPBL1) + +#define RX65N_ERI10_VNDX (VECT_ICU_GROUPAL0) +#define RX65N_RXI10_VNDX (VECT_SCI10_RXI10) +#define RX65N_TXI10_VNDX (VECT_SCI10_TXI10) +#define RX65N_TEI10_VNDX (VECT_ICU_GROUPAL0) + +#define RX65N_ERI11_VNDX (VECT_ICU_GROUPAL0) +#define RX65N_RXI11_VNDX (VECT_SCI11_RXI11) +#define RX65N_TXI11_VNDX (VECT_SCI11_TXI11) +#define RX65N_TEI11_VNDX (VECT_ICU_GROUPAL0) + +#define RX65N_ERI12_VNDX (VECT_ICU_GROUPBL0) +#define RX65N_RXI12_VNDX (VECT_SCI12_RXI12) +#define RX65N_TXI12_VNDX (VECT_SCI12_TXI12) +#define RX65N_TEI12_VNDX (VECT_ICU_GROUPBL0) + +/* LVD Interrupts */ + +#define RX65N_LVD1_VNDX (VECT_LVD1_LVD1) +#define RX65N_LVD2_VNDX (VECT_LVD2_LVD2) + +/* RTC Interrupts */ + +#define RX65N_ALM_VNDX (VECT_RTC_ALM) +#define RX65N_PRD_VNDX (VECT_RTC_PRD) + +/* WDT Interrupts */ + +#define RX65N_IWUNI_VNDX (VECT_IWDT_IWUNI) +#define RX65N_WUNI_VNDX (VECT_WDT_WUNI) + +/* PDC Interrupts */ + +#define RX65N_PCDFI_VNDX (VECT_PDC_PCDFI) + +/* DMAC Interrupts */ + +#define RX65N_DMAC0I_VNDX (VECT_DMAC_DMAC0I) +#define RX65N_DMAC1I_VNDX (VECT_DMAC_DMAC1I) +#define RX65N_DMAC2I_VNDX (VECT_DMAC_DMAC2I) +#define RX65N_DMAC3I_VNDX (VECT_DMAC_DMAC3I) +#define RX65N_DMAC74I_VNDX (VECT_DMAC_DMAC74I) + +/* OST Interrupts */ + +#define RX65N_OSTDI_VNDX (VECT_OST_OSTDI) + +/* EXDMAC Interrupts */ + +#define RX65N_EXDMAC0I_VNDX (VECT_EXDMAC_EXDMAC0I) +#define RX65N_EXDMAC1I_VNDX (VECT_EXDMAC_EXDMAC1I) + +/* PERIB Interrupts */ + +#define RX65N_INTB128_VNDX (VECT_PERIB_INTB128) +#define RX65N_INTB129_VNDX (VECT_PERIB_INTB129) +#define RX65N_INTB130_VNDX (VECT_PERIB_INTB130) +#define RX65N_INTB131_VNDX (VECT_PERIB_INTB131) +#define RX65N_INTB132_VNDX (VECT_PERIB_INTB132) +#define RX65N_INTB133_VNDX (VECT_PERIB_INTB133) +#define RX65N_INTB134_VNDX (VECT_PERIB_INTB134) +#define RX65N_INTB135_VNDX (VECT_PERIB_INTB135) +#define RX65N_INTB136_VNDX (VECT_PERIB_INTB136) +#define RX65N_INTB137_VNDX (VECT_PERIB_INTB137) +#define RX65N_INTB138_VNDX (VECT_PERIB_INTB138) +#define RX65N_INTB139_VNDX (VECT_PERIB_INTB139) +#define RX65N_INTB140_VNDX (VECT_PERIB_INTB140) +#define RX65N_INTB141_VNDX (VECT_PERIB_INTB141) +#define RX65N_INTB142_VNDX (VECT_PERIB_INTB142) +#define RX65N_INTB143_VNDX (VECT_PERIB_INTB143) +#define RX65N_INTB144_VNDX (VECT_PERIB_INTB144) +#define RX65N_INTB145_VNDX (VECT_PERIB_INTB145) +#define RX65N_INTB146_VNDX (VECT_PERIB_INTB146) +#define RX65N_INTB147_VNDX (VECT_PERIB_INTB147) +#define RX65N_INTB148_VNDX (VECT_PERIB_INTB148) +#define RX65N_INTB149_VNDX (VECT_PERIB_INTB149) +#define RX65N_INTB150_VNDX (VECT_PERIB_INTB150) +#define RX65N_INTB151_VNDX (VECT_PERIB_INTB151) +#define RX65N_INTB152_VNDX (VECT_PERIB_INTB152) +#define RX65N_INTB153_VNDX (VECT_PERIB_INTB153) +#define RX65N_INTB154_VNDX (VECT_PERIB_INTB154) +#define RX65N_INTB155_VNDX (VECT_PERIB_INTB155) +#define RX65N_INTB156_VNDX (VECT_PERIB_INTB156) +#define RX65N_INTB157_VNDX (VECT_PERIB_INTB157) +#define RX65N_INTB158_VNDX (VECT_PERIB_INTB158) +#define RX65N_INTB159_VNDX (VECT_PERIB_INTB159) +#define RX65N_INTB160_VNDX (VECT_PERIB_INTB160) +#define RX65N_INTB161_VNDX (VECT_PERIB_INTB161) +#define RX65N_INTB162_VNDX (VECT_PERIB_INTB162) +#define RX65N_INTB163_VNDX (VECT_PERIB_INTB163) +#define RX65N_INTB164_VNDX (VECT_PERIB_INTB164) +#define RX65N_INTB165_VNDX (VECT_PERIB_INTB165) +#define RX65N_INTB166_VNDX (VECT_PERIB_INTB166) +#define RX65N_INTB167_VNDX (VECT_PERIB_INTB167) +#define RX65N_INTB168_VNDX (VECT_PERIB_INTB168) +#define RX65N_INTB169_VNDX (VECT_PERIB_INTB169) +#define RX65N_INTB170_VNDX (VECT_PERIB_INTB170) +#define RX65N_INTB171_VNDX (VECT_PERIB_INTB171) +#define RX65N_INTB172_VNDX (VECT_PERIB_INTB172) +#define RX65N_INTB173_VNDX (VECT_PERIB_INTB173) +#define RX65N_INTB174_VNDX (VECT_PERIB_INTB174) +#define RX65N_INTB175_VNDX (VECT_PERIB_INTB175) +#define RX65N_INTB176_VNDX (VECT_PERIB_INTB176) +#define RX65N_INTB177_VNDX (VECT_PERIB_INTB177) +#define RX65N_INTB178_VNDX (VECT_PERIB_INTB178) +#define RX65N_INTB179_VNDX (VECT_PERIB_INTB179) +#define RX65N_INTB180_VNDX (VECT_PERIB_INTB180) +#define RX65N_INTB181_VNDX (VECT_PERIB_INTB181) +#define RX65N_INTB182_VNDX (VECT_PERIB_INTB182) +#define RX65N_INTB183_VNDX (VECT_PERIB_INTB183) +#define RX65N_INTB184_VNDX (VECT_PERIB_INTB184) +#define RX65N_INTB185_VNDX (VECT_PERIB_INTB185) +#define RX65N_INTB186_VNDX (VECT_PERIB_INTB186) +#define RX65N_INTB187_VNDX (VECT_PERIB_INTB187) +#define RX65N_INTB188_VNDX (VECT_PERIB_INTB188) +#define RX65N_INTB189_VNDX (VECT_PERIB_INTB189) +#define RX65N_INTB190_VNDX (VECT_PERIB_INTB190) +#define RX65N_INTB191_VNDX (VECT_PERIB_INTB191) +#define RX65N_INTB192_VNDX (VECT_PERIB_INTB192) +#define RX65N_INTB193_VNDX (VECT_PERIB_INTB193) +#define RX65N_INTB194_VNDX (VECT_PERIB_INTB194) +#define RX65N_INTB195_VNDX (VECT_PERIB_INTB195) +#define RX65N_INTB196_VNDX (VECT_PERIB_INTB196) +#define RX65N_INTB197_VNDX (VECT_PERIB_INTB197) +#define RX65N_INTB198_VNDX (VECT_PERIB_INTB198) +#define RX65N_INTB199_VNDX (VECT_PERIB_INTB199) +#define RX65N_INTB200_VNDX (VECT_PERIB_INTB200) +#define RX65N_INTB201_VNDX (VECT_PERIB_INTB201) +#define RX65N_INTB202_VNDX (VECT_PERIB_INTB202) +#define RX65N_INTB203_VNDX (VECT_PERIB_INTB203) +#define RX65N_INTB204_VNDX (VECT_PERIB_INTB204) +#define RX65N_INTB205_VNDX (VECT_PERIB_INTB205) +#define RX65N_INTB206_VNDX (VECT_PERIB_INTB206) +#define RX65N_INTB207_VNDX (VECT_PERIB_INTB207) + +/* PERIA Interrupts */ + +#define RX65N_INTA208_VNDX (VECT_PERIA_INTA208) +#define RX65N_INTA209_VNDX (VECT_PERIA_INTA209) +#define RX65N_INTA210_VNDX (VECT_PERIA_INTA210) +#define RX65N_INTA211_VNDX (VECT_PERIA_INTA211) +#define RX65N_INTA212_VNDX (VECT_PERIA_INTA212) +#define RX65N_INTA213_VNDX (VECT_PERIA_INTA213) +#define RX65N_INTA214_VNDX (VECT_PERIA_INTA214) +#define RX65N_INTA215_VNDX (VECT_PERIA_INTA215) +#define RX65N_INTA216_VNDX (VECT_PERIA_INTA216) +#define RX65N_INTA217_VNDX (VECT_PERIA_INTA217) +#define RX65N_INTA218_VNDX (VECT_PERIA_INTA218) +#define RX65N_INTA219_VNDX (VECT_PERIA_INTA219) +#define RX65N_INTA220_VNDX (VECT_PERIA_INTA220) +#define RX65N_INTA221_VNDX (VECT_PERIA_INTA221) +#define RX65N_INTA222_VNDX (VECT_PERIA_INTA222) +#define RX65N_INTA223_VNDX (VECT_PERIA_INTA223) +#define RX65N_INTA224_VNDX (VECT_PERIA_INTA224) +#define RX65N_INTA225_VNDX (VECT_PERIA_INTA225) +#define RX65N_INTA226_VNDX (VECT_PERIA_INTA226) +#define RX65N_INTA227_VNDX (VECT_PERIA_INTA227) +#define RX65N_INTA228_VNDX (VECT_PERIA_INTA228) +#define RX65N_INTA229_VNDX (VECT_PERIA_INTA229) +#define RX65N_INTA230_VNDX (VECT_PERIA_INTA230) +#define RX65N_INTA231_VNDX (VECT_PERIA_INTA231) +#define RX65N_INTA232_VNDX (VECT_PERIA_INTA232) +#define RX65N_INTA233_VNDX (VECT_PERIA_INTA233) +#define RX65N_INTA234_VNDX (VECT_PERIA_INTA234) +#define RX65N_INTA235_VNDX (VECT_PERIA_INTA235) +#define RX65N_INTA236_VNDX (VECT_PERIA_INTA236) +#define RX65N_INTA237_VNDX (VECT_PERIA_INTA237) +#define RX65N_INTA238_VNDX (VECT_PERIA_INTA238) +#define RX65N_INTA239_VNDX (VECT_PERIA_INTA239) +#define RX65N_INTA240_VNDX (VECT_PERIA_INTA240) +#define RX65N_INTA241_VNDX (VECT_PERIA_INTA241) +#define RX65N_INTA242_VNDX (VECT_PERIA_INTA242) +#define RX65N_INTA243_VNDX (VECT_PERIA_INTA243) +#define RX65N_INTA244_VNDX (VECT_PERIA_INTA244) +#define RX65N_INTA245_VNDX (VECT_PERIA_INTA245) +#define RX65N_INTA246_VNDX (VECT_PERIA_INTA246) +#define RX65N_INTA247_VNDX (VECT_PERIA_INTA247) +#define RX65N_INTA248_VNDX (VECT_PERIA_INTA248) +#define RX65N_INTA249_VNDX (VECT_PERIA_INTA249) +#define RX65N_INTA250_VNDX (VECT_PERIA_INTA250) +#define RX65N_INTA251_VNDX (VECT_PERIA_INTA251) +#define RX65N_INTA252_VNDX (VECT_PERIA_INTA252) +#define RX65N_INTA253_VNDX (VECT_PERIA_INTA253) +#define RX65N_INTA254_VNDX (VECT_PERIA_INTA254) +#define RX65N_INTA255_VNDX (VECT_PERIA_INTA255) + +#define RX65N_NVECTORS (256) + +/* Register information */ + +#define REG_SP ( 0) +#define REG_ACC0LO ( 1) +#define REG_ACC0HI ( 2) +#define REG_ACC0GU ( 3) +#define REG_ACC1LO ( 4) +#define REG_ACC1HI ( 5) +#define REG_ACC1GU ( 6) +#define REG_FPSW ( 7) +#define REG_R1 ( 8) +#define REG_R2 ( 9) +#define REG_R3 (10) +#define REG_R4 (11) +#define REG_R5 (12) +#define REG_R6 (13) +#define REG_R7 (14) +#define REG_R8 (15) +#define REG_R9 (16) +#define REG_R10 (17) +#define REG_R11 (18) +#define REG_R12 (19) +#define REG_R13 (20) +#define REG_R14 (21) +#define REG_R15 (22) +#define REG_PC (23) +#define REG_PSW (24) +#define XCPTCONTEXT_REGS (25) +#define XCPTCONTEXT_SIZE (4 * XCPTCONTEXT_REGS) + +#ifndef __ASSEMBLY__ +struct xcptcontext +{ + /* The following function pointer is non-zero if there are pending signals + * to be processed. + */ + + void *sigdeliver; /* Actual type is sig_deliver_t */ + + /* These are saved copies of LR and SR used during signal processing. */ + + uint32_t saved_pc; + uint32_t saved_sr; + + /* Register save area */ + + uint32_t regs[XCPTCONTEXT_REGS]; +}; + +/* Name: up_irq_save, up_irq_restore, and friends. + * + * NOTE: This function should never be called from application code and, + * as a general rule unless you really know what you are doing, this + * function should not be called directly from operation system code either: + * Typically, the wrapper functions, enter_critical_section() and + * leave_critical section(), are probably what you really want. + */ + +#define RX65N_PSW_INTERRUPT (0x00010000) + +/* Return the current interrupt enable state and disable IRQs */ + +/* Get the current value of the SR */ + +static inline irqstate_t __getsr(void) +{ + irqstate_t flags; + __asm__ __volatile__("mvfc psw, %0":"=r"(flags)); + return flags; +} + +/* Set the new value of the SR */ + +static inline void __setsr(irqstate_t psw) +{ + __asm__ __volatile__("mvtc %0, psw": :"r"(psw)); +} + +/* Disable interrupts */ + +static inline void up_irq_disable(void) +{ + __asm__ __volatile__("CLRPSW I"); +} + +/* Enable interrupts */ + +static inline void up_irq_enable(void) +{ + __asm__ __volatile__("SETPSW I"); +} + +/* Return the current interrupt enable state and disable interrupts */ + +static inline irqstate_t up_irq_save(void) +{ + irqstate_t flags = __getsr(); + up_irq_disable(); + return flags; +} + +/* Restore saved interrupt state */ + +static inline void up_irq_restore(irqstate_t flags) +{ + if (RX65N_PSW_INTERRUPT == (flags & RX65N_PSW_INTERRUPT)) + { + up_irq_enable(); + } + else + { + up_irq_disable(); + } +} + +#endif /* __ASSEMBLY__ */ + +#endif /* __ARCH_RENESAS_INCLUDE_RX65N_IRQ_H */ diff --git a/arch/renesas/include/rx65n/limits.h b/arch/renesas/include/rx65n/limits.h new file mode 100644 index 00000000000..b29405a029d --- /dev/null +++ b/arch/renesas/include/rx65n/limits.h @@ -0,0 +1,84 @@ +/**************************************************************************** + * arch/renesas/include/rx65n/limits.h + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_RENESAS_INCLUDE_RX65N_LIMITS_H +#define __ARCH_RENESAS_INCLUDE_RX65N_LIMITS_H + +=/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define CHAR_BIT 8 +#define SCHAR_MIN (-SCHAR_MAX - 1) +#define SCHAR_MAX 127 +#define UCHAR_MAX 255 + +/* These could be different on machines where char is unsigned */ + +#ifdef __CHAR_UNSIGNED__ +#define CHAR_MIN 0 +#define CHAR_MAX UCHAR_MAX +#else +#define CHAR_MIN SCHAR_MIN +#define CHAR_MAX SCHAR_MAX +#endif + +#define SHRT_MIN (-SHRT_MAX - 1) +#define SHRT_MAX 32767 +#define USHRT_MAX 65535U + +/* On SH-1, type 'int' is 32-bits */ + +#define INT_MIN (-INT_MAX - 1) +#define INT_MAX 2147483647 +#define UINT_MAX 4294967295U + +/* On SH-1, type 'long' is the same size as type 'int', 32-bits */ + +#define LONG_MIN (-LONG_MAX - 1) +#define LONG_MAX 2147483647L +#define ULONG_MAX 4294967295UL + +#define LLONG_MIN (-LLONG_MAX - 1) +#define LLONG_MAX 9223372036854775807LL +#define ULLONG_MAX 18446744073709551615ULL + +/* A pointer is 4 bytes */ + +#define PTR_MIN (-PTR_MAX - 1) +#define PTR_MAX 2147483647 +#define UPTR_MAX 4294967295U + +#endif /* __ARCH_RENESAS_INCLUDE_RX65N_LIMITS_H */ diff --git a/arch/renesas/include/rx65n/types.h b/arch/renesas/include/rx65n/types.h new file mode 100644 index 00000000000..5848183c916 --- /dev/null +++ b/arch/renesas/include/rx65n/types.h @@ -0,0 +1,96 @@ +/**************************************************************************** + * arch/renesas/include/rx65n/types.h + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/* This file should never be included directed but, rather, only indirectly\ + * through sys/types.h + */ + +#ifndef __ARCH_RENESAS_INCLUDE_RX65N_TYPES_H +#define __ARCH_RENESAS_INCLUDE_RX65N_TYPES_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/**************************************************************************** + * Type Declarations + ****************************************************************************/ + +#ifndef __ASSEMBLY__ + +/* These are the sizes of the standard integer types. NOTE that these type + * names have a leading underscore character. This file will be included + * (indirectly) by include/stdint.h and typedef'ed to the final name without + * the underscore character. This roundabout way of doings things allows + * the stdint.h to be removed from the include/ directory in the event that + * the user prefers to use the definitions provided by their toolchain header + * files + */ + +typedef signed char _int8_t; +typedef unsigned char _uint8_t; + +typedef signed short _int16_t; +typedef unsigned short _uint16_t; + +typedef signed int _int32_t; +typedef unsigned int _uint32_t; + +typedef signed long long _int64_t; +typedef unsigned long long _uint64_t; +#define __INT64_DEFINED + +/* A pointer is 4 bytes */ + +typedef signed int _intptr_t; +typedef unsigned int _uintptr_t; + +/* This is the size of the interrupt state save returned by + * up_irq_save() + */ + +typedef unsigned long irqstate_t; + +#endif /* __ASSEMBLY__ */ + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +#endif /* __ARCH_RENESAS_INCLUDE_SH1_TYPES_H */ diff --git a/arch/renesas/src/Makefile b/arch/renesas/src/Makefile index c7a9e74e73a..e6e9458814e 100644 --- a/arch/renesas/src/Makefile +++ b/arch/renesas/src/Makefile @@ -43,18 +43,18 @@ CXXFLAGS += $(EXTRADEFINES) ifeq ($(CONFIG_WINDOWS_NATIVE),y) ARCH_SRCDIR = $(TOPDIR)\arch\$(CONFIG_ARCH)\src NUTTX = $(TOPDIR)\nuttx$(EXEEXT) - CFLAGS += -I$(ARCH_SRCDIR)\chip - CFLAGS += -I$(ARCH_SRCDIR)\common - CFLAGS += -I$(ARCH_SRCDIR)\$(ARCH_SUBDIR) - CFLAGS += -I$(TOPDIR)\sched + CFLAGS += -I=$(ARCH_SRCDIR)\chip + CFLAGS += -I=$(ARCH_SRCDIR)\common + CFLAGS += -I=$(ARCH_SRCDIR)\$(ARCH_SUBDIR) + CFLAGS += -I=$(TOPDIR)\sched else ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src ifeq ($(WINTOOL),y) - NUTTX = "${shell cygpath -w $(TOPDIR)/nuttx$(EXEEXT)}" - CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/chip}" - CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/common}" - CFLAGS += -I "${shell cygpath -w $(ARCH_SRCDIR)/$(ARCH_SUBDIR)}" - CFLAGS += -I "${shell cygpath -w $(TOPDIR)/sched}" + NUTTX = ${shell cygpath -w $(TOPDIR)/nuttx$(EXEEXT)} + CFLAGS += -I ${shell cygpath -w $(ARCH_SRCDIR)/chip} + CFLAGS += -I ${shell cygpath -w $(ARCH_SRCDIR)/common} + CFLAGS += -I ${shell cygpath -w $(ARCH_SRCDIR)/$(ARCH_SUBDIR)} + CFLAGS += -I. -isystem ${shell cygpath -w $(TOPDIR)/sched} else NUTTX = $(TOPDIR)/nuttx$(EXEEXT) CFLAGS += -I$(ARCH_SRCDIR)/chip @@ -64,13 +64,13 @@ else endif endif -CFLAGS += -I$(ARCH_SRCDIR)/chip -I$(ARCH_SRCDIR)/common -I$(TOPDIR)/sched +CFLAGS += -I=$(ARCH_SRCDIR)/chip -I=$(ARCH_SRCDIR)/common -I=$(TOPDIR)/sched HEAD_OBJ = $(HEAD_ASRC:.S=$(OBJEXT)) STARTUP_OBJS ?= $(HEAD_OBJ) ASRCS = $(CHIP_ASRCS) $(CMN_ASRCS) -AOBJS = $(ASRCS:.S=$(OBJEXT)) +AOBJS = $(CHIP_ASRCS:.S=$(OBJEXT)) CSRCS = $(CHIP_CSRCS) $(CMN_CSRCS) COBJS = $(CSRCS:.c=$(OBJEXT)) @@ -138,6 +138,16 @@ board/libboard$(LIBEXT): nuttx$(EXEEXT): $(HEAD_OBJ) board/libboard$(LIBEXT) @echo "LD: nuttx" +ifeq ($(WINTOOL),y) + $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) -o ${shell cygpath -m "$(TOPDIR)"}/$@ $(HEAD_OBJ) \ + $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) "$(LIBGCC)" $(LDENDGROUP) + @echo "LD: nuttx" +ifneq ($(CONFIG_WINDOWS_NATIVE),y) + $(Q) $(NM) /cygwin64$(TOPDIR)/$@ | \ + grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ + sort > $(TOPDIR)/System.map +endif +else $(Q) $(LD) --entry=__start $(LDFLAGS) $(LIBPATHS) -o $(TOPDIR)/$@ $(HEAD_OBJ) \ $(LDSTARTGROUP) $(LDLIBS) $(EXTRA_LIBS) $(LIBGCC) $(LDENDGROUP) ifneq ($(CONFIG_WINDOWS_NATIVE),y) @@ -145,6 +155,7 @@ ifneq ($(CONFIG_WINDOWS_NATIVE),y) grep -v '\(compiled\)\|\(\$(OBJEXT)$$\)\|\( [aUw] \)\|\(\.\.ng$$\)\|\(LASH[RL]DI\)' | \ sort > $(TOPDIR)/System.map endif +endif # This is part of the top-level export target diff --git a/arch/renesas/src/rx65n/Kconfig b/arch/renesas/src/rx65n/Kconfig new file mode 100644 index 00000000000..594081ac3a4 --- /dev/null +++ b/arch/renesas/src/rx65n/Kconfig @@ -0,0 +1,532 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_RX65N +comment "RX65N Configuration Options" + +menu "RX65N Peripheral Selections" + +config RX65N_SCI2 + bool "SCI2" + default n + select SCI2_SERIALDRIVER + +config RX65N_ICU + bool "ICU" + default y + +config RX65N_CMT0 + bool "CMT0" + default y + +config RX65N_CMTW0 + bool "CMTW0" + default y + +config RX65N_CMTW1 + bool "CMTW1" + default y + +config RX65N_CMT2 + bool "CMT2" + default y + +config RX65N_CMT3 + bool "CMT3" + default y + +config RX65N_PERIB + bool "PERIB" + default y + +config RX65N_IRQ_GROUP + bool "IRQ_GROUP" + default y + +endmenu # RX65N Peripheral Selections +endif + +if ARCH_RX65N_RSK1MB +comment "RX65N on RSKRX65N-1MB Configuration Options" + +menu "RX65N Peripheral Selections" + +config RX65N_SCI2 + bool "SCI2" + default n + select SCI2_SERIALDRIVER + +config RX65N_ICU + bool "ICU" + default y + +config RX65N_CMT0 + bool "CMT0" + default y + +config RX65N_CMT2 + bool "CMT2" + default y + +config RX65N_CMT3 + bool "CMT3" + default y + +config RX65N_PERIB + bool "PERIB" + default y + +config RX65N_IRQ_GROUP + bool "IRQ_GROUP" + default y + +config RX65N_EMAC + bool + default n + select ARCH_HAVE_NETDEV_STATISTICS + ---help--- + NOTE that write-through caching is automatically selected. This is + to work around issues with the RX and TX descriptors with are 8-bytes + in size. But the D-Cache cache line size is 32-bytes. That means + that you cannot reload, clean or invalidate a descriptor without also + effecting three neighboring descriptors. Setting write through mode + eliminates the need for cleaning. If only reloading and invalidating + are done, then there is no problem. + +config RX65N_EMAC0 + bool "Ethernet MAC (GMAC)" + default n + select RX65N_EMAC + select NETDEVICES + select ARCH_HAVE_PHY + +endmenu # RX65N Peripheral Selections +endif + +if ARCH_RX65N_RSK2MB +comment "RX65N on RSKRX65N-2MB Configuration Options" + +menu "RX65N Peripheral Selections" + +config RX65N_SCI2 + bool "SCI2" + select SCI2_SERIALDRIVER + +config RX65N_SCI8 + bool "SCI8" + select SCI8_SERIALDRIVER + +config RX65N_SCI9 + bool "SCI9" + default n + select SCI9_SERIALDRIVER + +config RX65N_SCI10 + bool "SCI10" + default n + select SCI10_SERIALDRIVER + +config RX65N_SCI11 + bool "SCI11" + default n + select SCI11_SERIALDRIVER + +config RX65N_SCI12 + bool "SCI12" + default n + select SCI12_SERIALDRIVER + +config RX65N_ICU + bool "ICU" + default y + +config RX65N_CMT0 + bool "CMT0" + default y + +config RX65N_CMT2 + bool "CMT2" + default y + +config RX65N_CMT3 + bool "CMT3" + default y + +config RX65N_PERIB + bool "PERIB" + default y + +config RX65N_IRQ_GROUP + bool "IRQ_GROUP" + default y + +config RX65N_EMAC + bool + default n + select ARCH_HAVE_NETDEV_STATISTICS + ---help--- + NOTE that write-through caching is automatically selected. This is + to work around issues with the RX and TX descriptors with are 8-bytes + in size. But the D-Cache cache line size is 32-bytes. That means + that you cannot reload, clean or invalidate a descriptor without also + effecting three neighboring descriptors. Setting write through mode + eliminates the need for cleaning. If only reloading and invalidating + are done, then there is no problem. + +config RX65N_EMAC0 + bool "Ethernet MAC (GMAC)" + default n + select RX65N_EMAC + select NETDEVICES + select ARCH_HAVE_PHY + +endmenu # RX65N Peripheral Selections +endif + +if ARCH_RX65N_GRROSE +comment "RX65N on GR-ROSE Configuration Options" + +menu "RX65N Peripheral Selections" + +config RX65N_SCI0 + bool "SCI0" + default n + select SCI0_SERIALDRIVER + +config RX65N_SCI1 + bool "SCI1" + default y + select SCI1_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config RX65N_SCI2 + bool "SCI2" + default y + select SCI2_SERIALDRIVER + +config RX65N_SCI3 + bool "SCI3" + default n + select SCI3_SERIALDRIVER + +config RX65N_SCI4 + bool "SCI4" + default n + select SCI4_SERIALDRIVER + +config RX65N_SCI5 + bool "SCI5" + default y + select SCI5_SERIALDRIVER + select ARCH_HAVE_SERIAL_TERMIOS + +config RX65N_SCI6 + bool "SCI6" + default y + select SCI6_SERIALDRIVER + +config RX65N_SCI7 + bool "SCI7" + default n + select SCI7_SERIALDRIVER + +config RX65N_SCI8 + bool "SCI8" + default y + select SCI8_SERIALDRIVER + +config RX65N_SCI9 + bool "SCI9" + default n + select SCI9_SERIALDRIVER + +config RX65N_SCI10 + bool "SCI10" + default n + select SCI10_SERIALDRIVER + +config RX65N_SCI11 + bool "SCI11" + default n + select SCI11_SERIALDRIVER + +config RX65N_SCI12 + bool "SCI12" + default n + select SCI12_SERIALDRIVER + +config RX65N_ICU + bool "ICU" + default y + +config RX65N_CMT0 + bool "CMT0" + default y + +config RX65N_CMT2 + bool "CMT2" + default y + +config RX65N_CMT3 + bool "CMT3" + default y + +config RX65N_PERIB + bool "PERIB" + default y + +config RX65N_IRQ_GROUP + bool "IRQ_GROUP" + default y + +config RX65N_EMAC + bool + default n + select ARCH_HAVE_NETDEV_STATISTICS + ---help--- + NOTE that write-through caching is automatically selected. This is + to work around issues with the RX and TX descriptors with are 8-bytes + in size. But the D-Cache cache line size is 32-bytes. That means + that you cannot reload, clean or invalidate a descriptor without also + effecting three neighboring descriptors. Setting write through mode + eliminates the need for cleaning. If only reloading and invalidating + are done, then there is no problem. + +config RX65N_EMAC0 + bool "Ethernet MAC (GMAC)" + default n + select RX65N_EMAC + select NETDEVICES + select ARCH_HAVE_PHY + +endmenu # RX65N Peripheral Selections +endif + +menu "EMAC device driver options" + depends on RX65N_EMAC0 + +config RX65N_EMAC0_NRXBUFFERS + int "Number of RX buffers" + default 16 + ---help--- + EMAC buffer memory is segmented into 128 byte units (not + configurable). This setting provides the number of such 128 byte + units used for reception. This is also equal to the number of RX + descriptors that will be allocated The selected value must be an + even power of 2. + + NOTE that the defaut of 16 correspond to a total of only 2Kb of + RX buffering. That can easily exceeded on a busy network or with + large packet MTUs. You will know if this happens because you will + see the "Buffer Not Available (BNA)" receive error. + +config RX65N_EMAC0_NTXBUFFERS + int "Number of TX buffers" + default 8 + ---help--- + EMAC buffer memory is segmented into full Ethernet packets (size + CONFIG_NET_BUFSIZE bytes). This setting provides the number of such + packets that can be in flight. This is also equal to the number of TX + descriptors that will be allocated. + +config RX65N_EMAC0_PHYADDR + int "PHY address" + default 1 + ---help--- + The 5-bit address of the PHY on the board. Default: 1 + +config RX65N_EMAC0_PHYINIT + bool "Board-specific PHY Initialization" + default n + ---help--- + Some boards require specialized initialization of the PHY before it can be used. + This may include such things as configuring GPIOs, resetting the PHY, etc. If + RX65N_EMAC0_PHYINIT is defined in the configuration then the board specific logic must + provide sam_phyinitialize(); The RX65N EMAC driver will call this function + one time before it first uses the PHY. + +choice + prompt "PHY interface" + default RX65N_EMAC0_MII + +config RX65N_EMAC0_MII + bool "MII" + ---help--- + Support Ethernet MII interface (vs RMII). + +config RX65N_EMAC0_RMII + bool "RMII" + depends on !ARCH_CHIP_SAM4E + ---help--- + Support Ethernet RMII interface (vs MII). + +endchoice # PHY interface + +config RX65N_EMAC0_CLAUSE45 + bool "Clause 45 MII" + depends on RX65N_EMAC0_MII + ---help--- + MDIO was originally defined in Clause 22 of IEEE RFC802.3. In the + original specification, a single MDIO interface is able to access up + to 32 registers in 32 different PHY devices. To meet the needs the + expanding needs of 10-Gigabit Ethernet devices, Clause 45 of the + 802.3ae specification provided the following additions to MDIO: + + - Ability to access 65,536 registers in 32 different devices on + 32 different ports + - Additional OP-code and ST-code for Indirect Address register + access for 10 Gigabit Ethernet + - End-to-end fault signaling + - Multiple loopback points + - Low voltage electrical specification + + By default, Clause 22 PHYs will be supported unless this option is + selected. + +config RX65N_EMAC0_AUTONEG + bool "Use autonegotiation" + default y + ---help--- + Use PHY autonegotiation to determine speed and mode + +config RX65N_EMAC0_ETHFD + bool "Full duplex" + default n + depends on !RX65N_EMAC0_AUTONEG + ---help--- + If RX65N_EMAC0_AUTONEG is not defined, then this may be defined to select full duplex + mode. Default: half-duplex + +config RX65N_EMAC0_ETH100MBPS + bool "100 Mbps" + default n + depends on !RX65N_EMAC0_AUTONEG + ---help--- + If RX65N_EMAC0_AUTONEG is not defined, then this may be defined to select 100 MBps + speed. Default: 10 Mbps + +config RX65N_EMAC0_PHYSR + int "PHY Status Register Address (decimal)" + depends on RX65N_EMAC0_AUTONEG + ---help--- + This must be provided if RX65N_EMAC0_AUTONEG is defined. The PHY status register + address may diff from PHY to PHY. This configuration sets the address of + the PHY status register. + +config RX65N_EMAC0_PHYSR_ALTCONFIG + bool "PHY Status Alternate Bit Layout" + default n + depends on RX65N_EMAC0_AUTONEG + ---help--- + Different PHYs present speed and mode information in different ways. Some + will present separate information for speed and mode (this is the default). + Those PHYs, for example, may provide a 10/100 Mbps indication and a separate + full/half duplex indication. This options selects an alternative representation + where speed and mode information are combined. This might mean, for example, + separate bits for 10HD, 100HD, 10FD and 100FD. + +if RX65N_EMAC0_AUTONEG +if RX65N_EMAC0_PHYSR_ALTCONFIG + +config RX65N_EMAC0_PHYSR_ALTMODE + hex "PHY Mode Mask" + ---help--- + This must be provided if RX65N_EMAC0_AUTONEG is defined. This provide bit mask + for isolating the speed and full/half duplex mode bits. + +config RX65N_EMAC0_PHYSR_10HD + hex "10MBase-T Half Duplex Value" + ---help--- + This must be provided if RX65N_EMAC0_AUTONEG is defined. This is the value + under the bit mask that represents the 10Mbps, half duplex setting. + +config RX65N_EMAC0_PHYSR_100HD + hex "100Base-T Half Duplex Value" + ---help--- + This must be provided if RX65N_EMAC0_AUTONEG is defined. This is the value + under the bit mask that represents the 100Mbps, half duplex setting. + +config RX65N_EMAC0_PHYSR_10FD + hex "10Base-T Full Duplex Value" + ---help--- + This must be provided if RX65N_EMAC0_AUTONEG is defined. This is the value + under the bit mask that represents the 10Mbps, full duplex setting. + +config RX65N_EMAC0_PHYSR_100FD + hex "100Base-T Full Duplex Value" + ---help--- + This must be provided if RX65N_EMAC0_AUTONEG is defined. This is the value + under the bit mask that represents the 100Mbps, full duplex setting. + +endif # RX65N_EMAC0_PHYSR_ALTCONFIG +if !RX65N_EMAC0_PHYSR_ALTCONFIG + +config RX65N_EMAC0_PHYSR_SPEED + hex "PHY Speed Mask" + ---help--- + This must be provided if RX65N_EMAC0_AUTONEG is defined. This provides bit mask + for isolating the 10 or 100MBps speed indication. + +config RX65N_EMAC0_PHYSR_100MBPS + hex "PHY 100Mbps Speed Value" + ---help--- + This must be provided if RX65N_EMAC0_AUTONEG is defined. This provides the value + of the speed bit(s) indicating 100MBps speed. + +config RX65N_EMAC0_PHYSR_MODE + hex "PHY Mode Mask" + ---help--- + This must be provided if RX65N_EMAC0_AUTONEG is defined. This provides the + bit mask for isolating the full or half duplex mode bits. + +config RX65N_EMAC0_PHYSR_FULLDUPLEX + hex "PHY Full Duplex Mode Value" + ---help--- + This must be provided if RX65N_EMAC0_AUTONEG is defined. This provides the + value of the mode bits indicating full duplex mode. + +endif # !RX65N_EMAC0_PHYSR_ALTCONFIG +endif # RX65N_EMAC0_AUTONEG + +# These apply to both EMAC0 and EMAC1 (but are in the EMAC0 menu for now +# because there is not yet any RX65N chip that supports two Ethernet MACS + +config RX65N_EMAC0_ISETH0 + bool + default y + +config RX65N_EMAC_PREALLOCATE + bool "Preallocate buffers" + default n + ---help--- + Buffer an descriptor many may either be allocated from the memory + pool or pre-allocated to lie in .bss. This options selected pre- + allocated buffer memory. + +config RX65N_EMAC_NBC + bool "Disable Broadcast" + default n + ---help--- + Select to disable receipt of broadcast packets. + +config RX65N_EMAC_DEBUG + bool "Force EMAC0/1 DEBUG" + default n + depends on DEBUG_FEATURES && !DEBUG_NET + ---help--- + This option will force debug output from EMAC driver even without + network debug output enabled. This is not normally something + that would want to do but is convenient if you are debugging the + driver and do not want to get overloaded with other + network-related debug output. + +config RX65N_EMAC_REGDEBUG + bool "Register-Level Debug" + default y + depends on DEBUG_NET + ---help--- + Enable very low-level register access debug. Depends on CONFIG_DEBUG_NET. + +endmenu # EMAC0 device driver options diff --git a/arch/renesas/src/rx65n/Make.defs b/arch/renesas/src/rx65n/Make.defs new file mode 100644 index 00000000000..5320e09c8a1 --- /dev/null +++ b/arch/renesas/src/rx65n/Make.defs @@ -0,0 +1,54 @@ +############################################################################## +# arch/renesas/src/rx65n/Make.defs +# +# Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. +# Author: Anjana +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################## + +HEAD_ASRC = rx65n_head.S + +CMN_ASRCS = +CMN_CSRCS = up_allocateheap.c up_assert.c up_blocktask.c +CMN_CSRCS += up_createstack.c up_doirq.c up_exit.c up_idle.c up_initialize.c +CMN_CSRCS += up_interruptcontext.c up_lowputs.c up_mdelay.c up_puts.c +CMN_CSRCS += up_releasepending.c up_releasestack.c up_reprioritizertr.c +CMN_CSRCS += up_stackframe.c up_udelay.c up_unblocktask.c up_usestack.c + +CHIP_ASRCS = rx65n_vector.S +CHIP_CSRCS = rx65n_lowputc.c rx65n_serial.c rx65n_copystate.c rx65n_irq.c +CHIP_CSRCS += rx65n_schedulesigaction.c rx65n_sigdeliver.c rx65n_initialstate.c +CHIP_CSRCS += rx65n_hardware_setup.c rx65n_icu.c rx65n_port.c rx65n_sci.c +CHIP_CSRCS += rx65n_cgc.c rx65n_dumpstate.c rx65n_vector_table.c +CHIP_CSRCS += rx65n_timerisr.c + +ifeq ($(CONFIG_RX65N_EMAC),y) +CHIP_CSRCS += rx65n_eth.c rx65n_cmtw0.c +endif diff --git a/arch/renesas/src/rx65n/chip.h b/arch/renesas/src/rx65n/chip.h new file mode 100644 index 00000000000..e82f13ec83e --- /dev/null +++ b/arch/renesas/src/rx65n/chip.h @@ -0,0 +1,72 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/chip.h + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef __ARCH_RENESAS_SRC_RX65N_CHIP_H +#define __ARCH_RENESAS_SRC_RX65N_CHIP_H +#ifndef __ASSEMBLY__ + +/**************************************************************************** + * Included Files + ***************************************************************************/ + +#include + +#ifdef CONFIG_ARCH_CHIP_R5F565NEDDF +# include "rx65n_definitions.h" +#endif +#include "rx65n_definitions.h" + +/**************************************************************************** + * Pre-processor Definitions + ***************************************************************************/ + +/**************************************************************************** + * Public Types + ***************************************************************************/ + +/*************************************************************************** + * Public Data + **************************************************************************/ + +#ifndef __ASSEMBLY__ +extern uint16_t ebss; +#endif + +/************************************************************************** + * Public Functions + *************************************************************************/ + +#endif +#endif /* __ARCH_RENESAS_SRC_SH1_CHIP_H */ diff --git a/arch/renesas/src/rx65n/rx65n_cgc.c b/arch/renesas/src/rx65n/rx65n_cgc.c new file mode 100644 index 00000000000..a9cea45cc9c --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_cgc.c @@ -0,0 +1,230 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_cgc.c + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "rx65n_macrodriver.h" +#include "rx65n_cgc.h" +#include "arch/board/board.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: r_cgc_create + * + * Description: + * Clock generator Initialization + ****************************************************************************/ + +void r_cgc_create(void) +{ +#if ((24 * RX_CLK_1MHz) == RX_RESONATOR) + /* Set main clock control registers */ + + SYSTEM.MOFCR.BYTE = _00_CGC_MAINOSC_RESONATOR | + _00_CGC_MAINOSC_UNDER24M; + SYSTEM.MOSCWTCR.BYTE = _5C_CGC_MOSCWTCR_VALUE; + + /* Set main clock operation */ + + SYSTEM.MOSCCR.BIT.MOSTP = 0u; + + /* Wait for main clock oscillator wait counter overflow */ + + while (1u != SYSTEM.OSCOVFSR.BIT.MOOVF) + { + /* Do nothing */ + } + + /* Set system clock */ + + SYSTEM.SCKCR.LONG = _00000002_CGC_PCLKD_DIV_4 | _00000020_CGC_PCLKC_DIV_4 | + _00000200_CGC_PCLKB_DIV_4 | _00001000_CGC_PCLKA_DIV_2 | + _00010000_CGC_BCLK_DIV_2 | _01000000_CGC_ICLK_DIV_2 | + _20000000_CGC_FCLK_DIV_4; + + /* Set PLL circuit */ + + SYSTEM.PLLCR.WORD = _0000_CGC_PLL_FREQ_DIV_1 | + _0000_CGC_PLL_SOURCE_MAIN | + _1300_CGC_PLL_FREQ_MUL_10_0; + SYSTEM.PLLCR2.BIT.PLLEN = 0u; + + /* Wait for PLL wait counter overflow */ + + while (1u != SYSTEM.OSCOVFSR.BIT.PLOVF) + { + /* Do nothing */ + } + + /* Stop sub-clock */ + + RTC.RCR3.BIT.RTCEN = 0u; + + /* Wait for the register modification to complete */ + + while (0u != RTC.RCR3.BIT.RTCEN) + { + /* Do nothing */ + } + + /* Stop sub-clock */ + + SYSTEM.SOSCCR.BIT.SOSTP = 1u; + + /* Wait for the register modification to complete */ + + while (1u != SYSTEM.SOSCCR.BIT.SOSTP) + { + /* Do nothing */ + } + + /* Wait for sub-clock oscillation stopping */ + + while (0u != SYSTEM.OSCOVFSR.BIT.SOOVF) + { + /* Do nothing */ + } + + /* Set UCLK */ + + SYSTEM.SCKCR2.WORD = _0040_CGC_UCLK_DIV_5 | _0001_SCKCR2_BIT0; + + /* Set ROM wait cycle */ + + SYSTEM.ROMWT.BYTE = _02_CGC_ROMWT_CYCLE_2; + + /* Set SDCLK */ + + SYSTEM.SCKCR.BIT.PSTOP0 = 1U; + + /* Set clock source */ + + SYSTEM.SCKCR3.WORD = _0400_CGC_CLOCKSOURCE_PLL; + + /* Set LOCO */ + + SYSTEM.LOCOCR.BIT.LCSTP = 1U; +#elif ((12 * RX_CLK_1MHz) == RX_RESONATOR) + SYSTEM.MOFCR.BIT.MOFXIN = 0; + SYSTEM.MOFCR.BIT.MOSEL = 0; + + if (1 == SYSTEM.HOCOCR.BIT.HCSTP) + { + SYSTEM.HOCOPCR.BYTE = 0x01; + } + + else + { + while (0 == SYSTEM.OSCOVFSR.BIT.HCOVF); + } + SYSTEM.MOFCR.BIT.MODRV2 = 2; + SYSTEM.MOSCWTCR.BYTE = 0x53; + SYSTEM.MOSCCR.BYTE = 0x00; + + if (0x00 == SYSTEM.MOSCCR.BYTE) + { + __asm("nop"); + } + + while (0 == SYSTEM.OSCOVFSR.BIT.MOOVF); + if (0 == SYSTEM.RSTSR1.BIT.CWSF) + { + volatile uint8_t i; + RTC.RCR4.BIT.RCKSEL = 0; + for (i = 0; i < 4; i++) + { + __asm("nop"); + } + + if (0 != RTC.RCR4.BIT.RCKSEL) + { + __asm("nop"); + } + + RTC.RCR3.BIT.RTCEN = 0; + for (i = 0; i < 4; i++) + { + __asm("nop"); + } + + if (0 != RTC.RCR3.BIT.RTCEN) + { + __asm("nop"); + } + + SYSTEM.SOSCCR.BYTE = 0x01; + if (0x01 != SYSTEM.SOSCCR.BYTE) + { + __asm("nop"); + } + + while (0 != SYSTEM.OSCOVFSR.BIT.SOOVF); + } + else + { + SYSTEM.SOSCCR.BYTE = 0x01; + if (0x01 != SYSTEM.SOSCCR.BYTE) + { + __asm("nop"); + } + + while (0 != SYSTEM.OSCOVFSR.BIT.SOOVF); + } + + SYSTEM.PLLCR.BIT.PLIDIV = 0; + SYSTEM.PLLCR.BIT.PLLSRCSEL = 0; + SYSTEM.PLLCR.BIT.STC = (20 * 2) - 1; + SYSTEM.PLLCR2.BYTE = 0x00; + while (0 == SYSTEM.OSCOVFSR.BIT.PLOVF); + SYSTEM.ROMWT.BYTE = 0x02; + if (0x02 == SYSTEM.ROMWT.BYTE) + { + __asm("nop"); + } + + SYSTEM.SCKCR.LONG = 0x21c11222; + SYSTEM.SCKCR2.WORD = 0x0011; + SYSTEM.SCKCR3.WORD = 4u << 8; /* BSP_CFG_CLOCK_SOURCE */ + + SYSTEM.LOCOCR.BYTE = 0x01; +#else +# error "RX_RESONATOR is not defined in board.h" +#endif +} diff --git a/arch/renesas/src/rx65n/rx65n_cgc.h b/arch/renesas/src/rx65n/rx65n_cgc.h new file mode 100644 index 00000000000..56b10aeda70 --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_cgc.h @@ -0,0 +1,295 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_cgc.h + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RENESAS_SRC_RX65N_CGC_H +#define __ARCH_RENESAS_SRC_RX65N_CGC_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* System Clock Control Register (SCKCR) */ + +/* Peripheral Module Clock D (PCLKD) */ + +#define _00000000_CGC_PCLKD_DIV_1 (0x00000000ul) /* x1 */ +#define _00000001_CGC_PCLKD_DIV_2 (0x00000001ul) /* x1/2 */ +#define _00000002_CGC_PCLKD_DIV_4 (0x00000002ul) /* x1/4 */ +#define _00000003_CGC_PCLKD_DIV_8 (0x00000003ul) /* x1/8 */ +#define _00000004_CGC_PCLKD_DIV_16 (0x00000004ul) /* x1/16 */ +#define _00000005_CGC_PCLKD_DIV_32 (0x00000005ul) /* x1/32 */ +#define _00000006_CGC_PCLKD_DIV_64 (0x00000006ul) /* x1/64 */ + +/* Peripheral Module Clock C (PCLKC) */ + +#define _00000000_CGC_PCLKC_DIV_1 (0x00000000ul) /* x1 */ +#define _00000010_CGC_PCLKC_DIV_2 (0x00000010ul) /* x1/2 */ +#define _00000020_CGC_PCLKC_DIV_4 (0x00000020ul) /* x1/4 */ +#define _00000030_CGC_PCLKC_DIV_8 (0x00000030ul) /* x1/8 */ +#define _00000040_CGC_PCLKC_DIV_16 (0x00000040ul) /* x1/16 */ +#define _00000050_CGC_PCLKC_DIV_32 (0x00000050ul) /* x1/32 */ +#define _00000060_CGC_PCLKC_DIV_64 (0x00000060ul) /* x1/64 */ + +/* Peripheral Module Clock B (PCLKB) */ + +#define _00000000_CGC_PCLKB_DIV_1 (0x00000000ul) /* x1 */ +#define _00000100_CGC_PCLKB_DIV_2 (0x00000100ul) /* x1/2 */ +#define _00000200_CGC_PCLKB_DIV_4 (0x00000200ul) /* x1/4 */ +#define _00000300_CGC_PCLKB_DIV_8 (0x00000300ul) /* x1/8 */ +#define _00000400_CGC_PCLKB_DIV_16 (0x00000400ul) /* x1/16 */ +#define _00000500_CGC_PCLKB_DIV_32 (0x00000500ul) /* x1/32 */ +#define _00000600_CGC_PCLKB_DIV_64 (0x00000600ul) /* x1/64 */ + +/* Peripheral Module Clock A (PCLKA) */ + +#define _00000000_CGC_PCLKA_DIV_1 (0x00000000ul) /* x1 */ +#define _00001000_CGC_PCLKA_DIV_2 (0x00001000ul) /* x1/2 */ +#define _00002000_CGC_PCLKA_DIV_4 (0x00002000ul) /* x1/4 */ +#define _00003000_CGC_PCLKA_DIV_8 (0x00003000ul) /* x1/8 */ +#define _00004000_CGC_PCLKA_DIV_16 (0x00004000ul) /* x1/16 */ +#define _00005000_CGC_PCLKA_DIV_32 (0x00005000ul) /* x1/32 */ +#define _00006000_CGC_PCLKA_DIV_64 (0x00006000ul) /* x1/64 */ + +/* External Bus Clock (BCLK) */ + +#define _00000000_CGC_BCLK_DIV_1 (0x00000000ul) /* x1 */ +#define _00010000_CGC_BCLK_DIV_2 (0x00010000ul) /* x1/2 */ +#define _00020000_CGC_BCLK_DIV_4 (0x00020000ul) /* x1/4 */ +#define _00030000_CGC_BCLK_DIV_8 (0x00030000ul) /* x1/8 */ +#define _00040000_CGC_BCLK_DIV_16 (0x00040000ul) /* x1/16 */ +#define _00050000_CGC_BCLK_DIV_32 (0x00050000ul) /* x1/32 */ +#define _00060000_CGC_BCLK_DIV_64 (0x00060000ul) /* x1/64 */ + +/* System Clock (ICLK) */ + +#define _00000000_CGC_ICLK_DIV_1 (0x00000000ul) /* x1 */ +#define _01000000_CGC_ICLK_DIV_2 (0x01000000ul) /* x1/2 */ +#define _02000000_CGC_ICLK_DIV_4 (0x02000000ul) /* x1/4 */ +#define _03000000_CGC_ICLK_DIV_8 (0x03000000ul) /* x1/8 */ +#define _04000000_CGC_ICLK_DIV_16 (0x04000000ul) /* x1/16 */ +#define _05000000_CGC_ICLK_DIV_32 (0x05000000ul) /* x1/32 */ +#define _06000000_CGC_ICLK_DIV_64 (0x06000000ul) /* x1/64 */ + +/* System Clock (FCLK) */ + +#define _00000000_CGC_FCLK_DIV_1 (0x00000000ul) /* x1 */ +#define _10000000_CGC_FCLK_DIV_2 (0x10000000ul) /* x1/2 */ +#define _20000000_CGC_FCLK_DIV_4 (0x20000000ul) /* x1/4 */ +#define _30000000_CGC_FCLK_DIV_8 (0x30000000ul) /* x1/8 */ +#define _40000000_CGC_FCLK_DIV_16 (0x40000000ul) /* x1/16 */ +#define _50000000_CGC_FCLK_DIV_32 (0x50000000ul) /* x1/32 */ +#define _60000000_CGC_FCLK_DIV_64 (0x60000000ul) /* x1/64 */ + +/* ROM Wait Cycle Setting Register (ROMWT) */ + +/* ROM Wait Cycle Setting (ROMWT) */ + +#define _00_CGC_ROMWT_CYCLE_0 (0x00u) /* No wait */ +#define _01_CGC_ROMWT_CYCLE_1 (0x01u) /* One wait cycle */ +#define _02_CGC_ROMWT_CYCLE_2 (0x02u) /* Two wait cycles */ + +/* System Clock Control Register 2 (SCKCR2) */ + +#define _0010_CGC_UCLK_DIV_1 (0x0010u) /* x1/2 */ +#define _0020_CGC_UCLK_DIV_3 (0x0020u) /* x1/3 */ +#define _0030_CGC_UCLK_DIV_4 (0x0030u) /* x1/4 */ +#define _0040_CGC_UCLK_DIV_5 (0x0040u) /* x1/5 */ +#define _0001_SCKCR2_BIT0 (0x0001u) /* RESERVE BIT0 */ + +/* System Clock Control Register 3 (SCKCR3) */ + +#define _0000_CGC_CLOCKSOURCE_LOCO (0x0000u) /* LOCO */ +#define _0100_CGC_CLOCKSOURCE_HOCO (0x0100u) /* HOCO */ +#define _0200_CGC_CLOCKSOURCE_MAINCLK (0x0200u) /* Main clock oscillator */ +#define _0300_CGC_CLOCKSOURCE_SUBCLK (0x0300u) /* Sub-clock oscillator */ +#define _0400_CGC_CLOCKSOURCE_PLL (0x0400u) /* PLL circuit */ + +/* PLL Control Register (PLLCR) */ + +/* PLL Input Frequency Division Ratio Select (PLIDIV[1:0]) */ + +#define _0000_CGC_PLL_FREQ_DIV_1 (0x0000u) /* x1 */ +#define _0001_CGC_PLL_FREQ_DIV_2 (0x0001u) /* x1/2 */ +#define _0002_CGC_PLL_FREQ_DIV_3 (0x0002u) /* x1/3 */ + +/* PLL Clock Source Select (PLLSRCSEL) */ + +#define _0000_CGC_PLL_SOURCE_MAIN (0x0000u) /* Main clock oscillator */ +#define _0010_CGC_PLL_SOURCE_HOCO (0x0010u) /* HOCO */ + +/* Frequency Multiplication Factor Select (STC[5:0]) */ + +#define _1300_CGC_PLL_FREQ_MUL_10_0 (0x1300u) /* x10.0 */ +#define _1400_CGC_PLL_FREQ_MUL_10_5 (0x1400u) /* x10.5 */ +#define _1500_CGC_PLL_FREQ_MUL_11_0 (0x1500u) /* x11.0 */ +#define _1600_CGC_PLL_FREQ_MUL_11_5 (0x1600u) /* x11.5 */ +#define _1700_CGC_PLL_FREQ_MUL_12_0 (0x1700u) /* x12.0 */ +#define _1800_CGC_PLL_FREQ_MUL_12_5 (0x1800u) /* x12.5 */ +#define _1900_CGC_PLL_FREQ_MUL_13_0 (0x1900u) /* x13.0 */ +#define _1A00_CGC_PLL_FREQ_MUL_13_5 (0x1a00u) /* x13.5 */ +#define _1B00_CGC_PLL_FREQ_MUL_14_0 (0x1b00u) /* x14.0 */ +#define _1C00_CGC_PLL_FREQ_MUL_14_5 (0x1c00u) /* x14.5 */ +#define _1D00_CGC_PLL_FREQ_MUL_15_0 (0x1d00u) /* x15.0 */ +#define _1E00_CGC_PLL_FREQ_MUL_15_5 (0x1e00u) /* x15.5 */ +#define _1F00_CGC_PLL_FREQ_MUL_16_0 (0x1f00u) /* x16.0 */ +#define _2000_CGC_PLL_FREQ_MUL_16_5 (0x2000u) /* x16.5 */ +#define _2100_CGC_PLL_FREQ_MUL_17_0 (0x2100u) /* x17.0 */ +#define _2200_CGC_PLL_FREQ_MUL_17_5 (0x2200u) /* x17.5 */ +#define _2300_CGC_PLL_FREQ_MUL_18_0 (0x2300u) /* x18.0 */ +#define _2400_CGC_PLL_FREQ_MUL_18_5 (0x2400u) /* x18.5 */ +#define _2500_CGC_PLL_FREQ_MUL_19_0 (0x2500u) /* x19.0 */ +#define _2600_CGC_PLL_FREQ_MUL_19_5 (0x2600u) /* x19.5 */ +#define _2700_CGC_PLL_FREQ_MUL_20_0 (0x2700u) /* x20.0 */ +#define _2800_CGC_PLL_FREQ_MUL_20_5 (0x2800u) /* x20.5 */ +#define _2900_CGC_PLL_FREQ_MUL_21_0 (0x2900u) /* x21.0 */ +#define _2A00_CGC_PLL_FREQ_MUL_21_5 (0x2a00u) /* x21.5 */ +#define _2B00_CGC_PLL_FREQ_MUL_22_0 (0x2b00u) /* x22.0 */ +#define _2C00_CGC_PLL_FREQ_MUL_22_5 (0x2c00u) /* x22.5 */ +#define _2D00_CGC_PLL_FREQ_MUL_23_0 (0x2d00u) /* x23.0 */ +#define _2E00_CGC_PLL_FREQ_MUL_23_5 (0x2e00u) /* x23.5 */ +#define _2F00_CGC_PLL_FREQ_MUL_24_0 (0x2f00u) /* x24.0 */ +#define _3000_CGC_PLL_FREQ_MUL_24_5 (0x3000u) /* x24.5 */ +#define _3100_CGC_PLL_FREQ_MUL_25_0 (0x3100u) /* x25.0 */ +#define _3200_CGC_PLL_FREQ_MUL_25_5 (0x3200u) /* x25.5 */ +#define _3300_CGC_PLL_FREQ_MUL_26_0 (0x3300u) /* x26.0 */ +#define _3400_CGC_PLL_FREQ_MUL_26_5 (0x3400u) /* x26.5 */ +#define _3500_CGC_PLL_FREQ_MUL_27_0 (0x3500u) /* x27.0 */ +#define _3600_CGC_PLL_FREQ_MUL_27_5 (0x3600u) /* x27.5 */ +#define _3700_CGC_PLL_FREQ_MUL_28_0 (0x3700u) /* x28.0 */ +#define _3800_CGC_PLL_FREQ_MUL_28_5 (0x3800u) /* x28.5 */ +#define _3900_CGC_PLL_FREQ_MUL_29_0 (0x3900u) /* x29.0 */ +#define _3A00_CGC_PLL_FREQ_MUL_29_5 (0x3a00u) /* x29.5 */ +#define _3B00_CGC_PLL_FREQ_MUL_30_0 (0x3b00u) /* x30.0 */ + +/* Oscillation Stop Detection Control Register (OSTDCR) */ + +/* Oscillation Stop Detection Interrupt Enable (OSTDIE) */ + +/* The oscillation stop detection interrupt is disabled */ + +#define _00_CGC_OSC_STOP_INT_DISABLE (0x00u) + +/* The oscillation stop detection interrupt is enabled */ + +#define _01_CGC_OSC_STOP_INT_ENABLE (0x01u) + +/* Oscillation Stop Detection Function Enable (OSTDE) */ + +/* Oscillation stop detection function is disabled */ + +#define _00_CGC_OSC_STOP_DISABLE (0x00u) + +/* Oscillation stop detection function is enabled */ + +#define _80_CGC_OSC_STOP_ENABLE (0x80u) + +/* High-Speed On-Chip Oscillator Control Register 2 (HOCOCR2) */ + +/* HOCO Frequency Setting (HCFRQ[1:0]) */ + +#define _00_CGC_HOCO_CLK_16 (0x00u) /* 16 MHz */ +#define _01_CGC_HOCO_CLK_18 (0x01u) /* 18 MHz */ +#define _02_CGC_HOCO_CLK_20 (0x02u) /* 20 MHz */ + +/* Main Clock Oscillator Forced Oscillation Control Register (MOFCR) */ + +/* Main Clock Oscillator Forced Oscillation (MOFXIN) */ + +/* Oscillator is not controlled by this bit */ + +#define _00_CGC_MAINOSC_NOT_CONTROLLED (0x00u) + +/* The main clock oscillator is forcedly oscillated */ + +#define _01_CGC_MAINOSC_FORCE_OSCILLATED (0x01u) + +/* Main Oscillator Drive Capability 2 Switching (MODRV2[1:0]) */ + +#define _00_CGC_MAINOSC_UNDER24M (0x00u) /* 20.1 to 24 MHz */ +#define _10_CGC_MAINOSC_UNDER20M (0x10u) /* 16.1 to 20 MHz */ +#define _20_CGC_MAINOSC_UNDER16M (0x20u) /* 8.1 to 16 MHz */ +#define _30_CGC_MAINOSC_EQUATE8M (0x30u) /* 8 MHz */ + +/* Main Clock Oscillator Switch (MOSEL) */ + +#define _00_CGC_MAINOSC_RESONATOR (0x00u) /* Resonator */ +#define _40_CGC_MAINOSC_EXTERNAL (0x40u) /* External oscillator input */ + +/* RTC Control Register 4 (RCR4) */ + +/* Count source select (RCKSEL) */ + +#define _00_RTC_SOURCE_SELECT_SUB (0x00u) /* Select sub-clock oscillator */ +#define _01_RTC_SOURCE_SELECT_MAIN_FORCED (0x01u) /* Select main clock oscillator */ + +/* Interrupt Source Priority Register n (IPRn) */ + +/* Interrupt Priority Level Select (IPR[3:0]) */ + +#define _00_CGC_PRIORITY_LEVEL0 (0x00u) /* Level 0 (interrupt disabled) */ +#define _01_CGC_PRIORITY_LEVEL1 (0x01u) /* Level 1 */ +#define _02_CGC_PRIORITY_LEVEL2 (0x02u) /* Level 2 */ +#define _03_CGC_PRIORITY_LEVEL3 (0x03u) /* Level 3 */ +#define _04_CGC_PRIORITY_LEVEL4 (0x04u) /* Level 4 */ +#define _05_CGC_PRIORITY_LEVEL5 (0x05u) /* Level 5 */ +#define _06_CGC_PRIORITY_LEVEL6 (0x06u) /* Level 6 */ +#define _07_CGC_PRIORITY_LEVEL7 (0x07u) /* Level 7 */ +#define _08_CGC_PRIORITY_LEVEL8 (0x08u) /* Level 8 */ +#define _09_CGC_PRIORITY_LEVEL9 (0x09u) /* Level 9 */ +#define _0A_CGC_PRIORITY_LEVEL10 (0x0au) /* Level 10 */ +#define _0B_CGC_PRIORITY_LEVEL11 (0x0bu) /* Level 11 */ +#define _0C_CGC_PRIORITY_LEVEL12 (0x0cu) /* Level 12 */ +#define _0D_CGC_PRIORITY_LEVEL13 (0x0du) /* Level 13 */ +#define _0E_CGC_PRIORITY_LEVEL14 (0x0eu) /* Level 14 */ +#define _0F_CGC_PRIORITY_LEVEL15 (0x0fu) /* Level 15 (highest) */ + +/* Main clock oscillator wait time */ + +#define _5C_CGC_MOSCWTCR_VALUE (0x5cu) + +/**************************************************************************** + * Public Function Prototypes + ***************************************************************************/ + +/**************************************************************************** + * Name: r_cgc_create + * + * Description: + * Clock Initialization + ****************************************************************************/ + +void r_cgc_create(void); + +#endif diff --git a/arch/renesas/src/rx65n/rx65n_cmt.h b/arch/renesas/src/rx65n/rx65n_cmt.h new file mode 100644 index 00000000000..de7b04fa328 --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_cmt.h @@ -0,0 +1,66 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_cmt.h + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RENESAS_SRC_RX65N_CMT_H +#define __ARCH_RENESAS_SRC_RX65N_CMT_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Compare Match Timer Control Register (CMCR) */ + +/* Interrupt Source Priority Register n (IPRn) */ + +/* Interrupt Priority Level Select (IPR[3:0]) */ + +#define _00_CMT_PRIORITY_LEVEL0 (0x00U) /* Level 0 (interrupt disabled) */ +#define _01_CMT_PRIORITY_LEVEL1 (0x01U) /* Level 1 */ +#define _02_CMT_PRIORITY_LEVEL2 (0x02U) /* Level 2 */ +#define _03_CMT_PRIORITY_LEVEL3 (0x03U) /* Level 3 */ +#define _04_CMT_PRIORITY_LEVEL4 (0x04U) /* Level 4 */ +#define _05_CMT_PRIORITY_LEVEL5 (0x05U) /* Level 5 */ +#define _06_CMT_PRIORITY_LEVEL6 (0x06U) /* Level 6 */ +#define _07_CMT_PRIORITY_LEVEL7 (0x07U) /* Level 7 */ +#define _08_CMT_PRIORITY_LEVEL8 (0x08U) /* Level 8 */ +#define _09_CMT_PRIORITY_LEVEL9 (0x09U) /* Level 9 */ +#define _0A_CMT_PRIORITY_LEVEL10 (0x0aU) /* Level 10 */ +#define _0B_CMT_PRIORITY_LEVEL11 (0x0bU) /* Level 11 */ +#define _0C_CMT_PRIORITY_LEVEL12 (0x0cU) /* Level 12 */ +#define _0D_CMT_PRIORITY_LEVEL13 (0x0dU) /* Level 13 */ +#define _0E_CMT_PRIORITY_LEVEL14 (0x0eU) /* Level 14 */ +#define _0F_CMT_PRIORITY_LEVEL15 (0x0fU) /* Level 15 (highest) */ + +#endif /* __ARCH_RENESAS_SRC_RX65N_CMT_H */ diff --git a/arch/renesas/src/rx65n/rx65n_cmtw.h b/arch/renesas/src/rx65n/rx65n_cmtw.h new file mode 100644 index 00000000000..fdef2250892 --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_cmtw.h @@ -0,0 +1,259 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_cmtw.h + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Surya Prakash + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef __ARCH_RENESAS_SRC_RX65N_CMTW_H +#define __ARCH_RENESAS_SRC_RX65N_CMTW_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Timer Start Register (CMWSTR) */ + +#define _0000_CMTW_CMWSTR_COUNTER_STOP (0x0000U) /* Stop counter count */ +#define _0001_CMTW_CMWSTR_COUNTER_START (0x0001U) /* Start counter count */ + +/* Timer Control Register (CMWCR) */ + +/* Clock select (CKS[1:0]) */ + +#define _0000_CMTW_CMWCR_CLOCK_PCLK8 (0x0000U) /* PCLK/8 */ +#define _0001_CMTW_CMWCR_CLOCK_PCLK32 (0x0001U) /* PCLK/32 */ +#define _0002_CMTW_CMWCR_CLOCK_PCLK128 (0x0002U) /* PCLK/128 */ +#define _0003_CMTW_CMWCR_CLOCK_PCLK512 (0x0003U) /* PCLK/512 */ + +/* Compare Match Interrupt Enable (CMWIE) */ + +/* Disable Compare Match Interrupt */ + +#define _0000_CMTW_CMWCR_CMWIE_DISABLE (0x0000U) + +/* Enable Compare Match Interrupt */ + +#define _0008_CMTW_CMWCR_CMWIE_ENABLE (0x0008U) + +/* Input Capture 0 Interrupt Enable (IC0IE) */ + +/* Disable Input Capture 0 Interrupt */ + +#define _0000_CMTW_CMWCR_IC0IE_DISABLE (0x0000U) + +/* Enable Input Capture 0 Interrupt */ + +#define _0010_CMTW_CMWCR_IC0IE_ENABLE (0x0010U) + +/* Input Capture 1 Interrupt Enable (IC1IE) */ + +/* Disable Input Capture 1 Interrupt */ + +#define _0000_CMTW_CMWCR_IC1IE_DISABLE (0x0000U) + +/* Enable Input Capture 1 Interrupt */ + +#define _0020_CMTW_CMWCR_IC1IE_ENABLE (0x0020U) + +/* Output Compare 0 Interrupt Enable (OC0IE) */ + +/* Disable Output Compare 0 Interrupt */ + +#define _0000_CMTW_CMWCR_OC0IE_DISABLE (0x0000U) + +/* Enable Output Compare 0 Interrupt */ + +#define _0040_CMTW_CMWCR_OC0IE_ENABLE (0x0040U) + +/* Output Compare 1 Interrupt Enable (OC1IE) */ + +/* Disable Output Compare 1 Interrupt */ + +#define _0000_CMTW_CMWCR_OC1IE_DISABLE (0x0000U) + +/* Enable Output Compare 1 Interrupt */ + +#define _0080_CMTW_CMWCR_OC1IE_ENABLE (0x0080U) + +/* Timer Counter Size (CMS) */ + +#define _0000_CMTW_CMWCR_COUNTER_SIZE_32 (0x0000U) /* 32 bits */ +#define _0200_CMTW_CMWCR_COUNTER_SIZE_16 (0x0200U) /* 16 bits */ + +/* Counter Clear (CCLR[2:0]) */ + +/* CMWCNT counter cleared by CMWCOR */ + +#define _0000_CMTW_CMWCR_CCLR_ENABLE_CMWCOR (0x6000U) + +/* Clearing of CMWCNT counter disabled */ + +#define _2000_CMTW_CMWCR_CCLR_DISABLE (0x2000U) + +/* Clearing of CMWCNT counter disabled */ + +#define _4000_CMTW_CMWCR_CCLR_DISABLE (0x4000U) + +/* Clearing of CMWCNT counter disabled */ + +#define _6000_CMTW_CMWCR_CCLR_DISABLE (0x6000U) + +/* CMWCNT counter cleared by CMWICR0 */ + +#define _8000_CMTW_CMWCR_CCLR_CMWICR0_ENABLE (0x8000U) + +/* CMWCNT counter cleared by CMWICR1 */ + +#define _A000_CMTW_CMWCR_CCLR_CMWICR1_ENABLE (0xa000U) + +/* CMWCNT counter cleared by CMWOCR0 */ + +#define _C000_CMTW_CMWCR_CCLR_CMWOCR0_ENABLE (0xc000U) + +/* CMWCNT counter cleared by CMWOCR1 */ + +#define _E000_CMTW_CMWCR_CCLR_CMWOCR1_ENABLE (0xe000U) + +/* Timer I/O Control Register (CMWIOR) */ + +/* Input Compare Control 0 (IC0[1:0]) */ + +#define _0000_CMTW_CMWIOR_IC0_RISE (0x0000U) /* Rising edge */ +#define _0001_CMTW_CMWIOR_IC0_FALL (0x0001U) /* Falling edge */ +#define _0002_CMTW_CMWIOR_IC0_BOTH (0x0002U) /* Both edges */ + +/* Input Capture Control 1 (IC1[1:0]) */ + +#define _0000_CMTW_CMWIOR_IC1_RISE (0x0000U) /* Rising edge */ +#define _0004_CMTW_CMWIOR_IC1_FALL (0x0004U) /* Falling edge */ +#define _0008_CMTW_CMWIOR_IC1_BOTH (0x0008U) /* Both edges */ + +/* Input Capture Enable 0 (IC0E) */ + +/* Disable input capture of CMWICR0 */ + +#define _0000_CMTW_CMWIOR_IC0E_DISABLE (0x0000U) + +/* Enable input capture of CMWICR0 */ + +#define _0010_CMTW_CMWIOR_IC0E_ENABLE (0x0010U) + +/* Input Capture Enable 1 (IC1E) */ + +/* Disable input capture of CMWICR1 */ + +#define _0000_CMTW_CMWIOR_IC1E_DISABLE (0x0000U) + +/* Enable input capture of CMWICR1 */ + +#define _0020_CMTW_CMWIOR_IC1E_ENABLE (0x0020U) + +/* Output Compare Control 0 (OC0[1:0]) */ + +/* Retains the output value */ + +#define _0000_CMTW_CMWIOR_OC0_RETAIN (0x0000U) + +/* Initially outputs 0 */ + +#define _0100_CMTW_CMWIOR_OC0_OUTPUT0 (0x0100U) + +/* Initially outputs 1 */ + +#define _0200_CMTW_CMWIOR_OC0_OUTPUT1 (0x0200U) + +/* Output Compare Control 1 (OC1[1:0]) */ + +/* Retains the output value */ + +#define _0000_CMTW_CMWIOR_OC1_RETAIN (0x0000U) + +/* Initially outputs 0 */ + +#define _0400_CMTW_CMWIOR_OC1_OUTPUT0 (0x0400U) + +/* Initially outputs 1 */ + +#define _0800_CMTW_CMWIOR_OC1_OUTPUT1 (0x0800U) + +/* Compare Match Enable 0 (OC0E) */ + +/* Disable compare match using CMWOCR0 */ + +#define _0000_CMTW_CMWIOR_OC0E_DISABLE (0x0000U) + +/* Enable compare match using CMWOCR0 */ + +#define _1000_CMTW_CMWIOR_OC0E_ENABLE (0x1000U) + +/* Compare Match Enable 1 (OC1E) */ + +/* Disable compare match using CMWOCR1 */ + +#define _0000_CMTW_CMWIOR_OC1E_DISABLE (0x0000U) + +/* Enable compare match using CMWOCR1 */ + +#define _2000_CMTW_CMWIOR_OC1E_ENABLE (0x2000U) + +/* Compare Match Enable (CMWE) */ + +/* Disable compare match using CMWCOR */ + +#define _0000_CMTW_CMWIOR_CMWE_DISABLE (0x0000U) + +/* Enable compare match using CMWCOR */ + +#define _8000_CMTW_CMWIOR_CMWE_ENABLE (0x8000U) + +/* Interrupt Source Priority Register n (IPRn) */ + +/* Interrupt Priority Level Select (IPR[3:0]) */ + +#define _00_CMTW_PRIORITY_LEVEL0 (0x00U) /* Level 0 (interrupt disabled) */ +#define _01_CMTW_PRIORITY_LEVEL1 (0x01U) /* Level 1 */ +#define _02_CMTW_PRIORITY_LEVEL2 (0x02U) /* Level 2 */ +#define _03_CMTW_PRIORITY_LEVEL3 (0x03U) /* Level 3 */ +#define _04_CMTW_PRIORITY_LEVEL4 (0x04U) /* Level 4 */ +#define _05_CMTW_PRIORITY_LEVEL5 (0x05U) /* Level 5 */ +#define _06_CMTW_PRIORITY_LEVEL6 (0x06U) /* Level 6 */ +#define _07_CMTW_PRIORITY_LEVEL7 (0x07U) /* Level 7 */ +#define _08_CMTW_PRIORITY_LEVEL8 (0x08U) /* Level 8 */ +#define _09_CMTW_PRIORITY_LEVEL9 (0x09U) /* Level 9 */ +#define _0A_CMTW_PRIORITY_LEVEL10 (0x0aU) /* Level 10 */ +#define _0B_CMTW_PRIORITY_LEVEL11 (0x0bU) /* Level 11 */ +#define _0C_CMTW_PRIORITY_LEVEL12 (0x0cU) /* Level 12 */ +#define _0D_CMTW_PRIORITY_LEVEL13 (0x0dU) /* Level 13 */ +#define _0E_CMTW_PRIORITY_LEVEL14 (0x0eU) /* Level 14 */ +#define _0F_CMTW_PRIORITY_LEVEL15 (0x0fU) /* Level 15 (highest) */ + +#endif /* __ARCH_RENESAS_SRC_RX65N_CMTW_H */ diff --git a/arch/renesas/src/rx65n/rx65n_cmtw0.c b/arch/renesas/src/rx65n/rx65n_cmtw0.c new file mode 100644 index 00000000000..1ed3f1a0fff --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_cmtw0.c @@ -0,0 +1,229 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_cmtw0.c + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author:Surya Prakash + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include +#include +#include +#include +#include +#include + +#include "rx65n_cmtw0.h" +#include "rx65n/iodefine.h" +#include "rx65n/irq.h" +#include "rx65n_definitions.h" +#include +#include "rx65n_eth.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rx65n_cmtw0_create + * + * Description: + * CMTW0 Timer Initialization + ****************************************************************************/ + +void rx65n_cmtw0_create(uint32_t txpoll_time, uint32_t txtimeout_time) +{ + /* Disable OC0I0 interrupt */ + + IEN(PERIB, INTB170) = 0U; + + /* Disable OC1I0 interrupt */ + + IEN(PERIB, INTB171) = 0U; + + /* Cancel CMTW stop state in LPC */ + + MSTP(CMTW0) = 0U; + + /* Stop CMTW0 count */ + + CMTW0.CMWSTR.BIT.STR = 0U; + + /* Set timer I/O control register */ + + CMTW0.CMWIOR.WORD = _1000_CMTW_CMWIOR_OC0E_ENABLE | + _0000_CMTW_CMWIOR_OC0_RETAIN | + _2000_CMTW_CMWIOR_OC1E_ENABLE | + _0000_CMTW_CMWIOR_OC1_RETAIN | + _8000_CMTW_CMWIOR_CMWE_ENABLE; + + /* Set compare match register */ + + CMTW0.CMWCOR = _000000BB_CMTW0_CMWCOR_VALUE; + + /* Set output compare register 0 */ + + CMTW0.CMWOCR0 = txpoll_time; + + /* Set output compare register 1 */ + + CMTW0.CMWOCR1 = txtimeout_time; + + /* Set control registers */ + + CMTW0.CMWCR.WORD = _0001_CMTW_CMWCR_CLOCK_PCLK32 | + _0040_CMTW_CMWCR_OC0IE_ENABLE | + _0080_CMTW_CMWCR_OC1IE_ENABLE | + _0000_CMTW_CMWCR_COUNTER_SIZE_32 | + _0000_CMTW_CMWCR_CCLR_ENABLE_CMWCOR; + + /* Set OC0I0 interrupt and priority level */ + + ICU.SLIBR170.BYTE = 0x2bu; + IPR(PERIB, INTB170) = _0F_CMTW_PRIORITY_LEVEL15; + + /* Set OC1I0 interrupt and priority level */ + + ICU.SLIBR171.BYTE = 0x2cu; + IPR(PERIB, INTB171) = _0F_CMTW_PRIORITY_LEVEL15; + + /* Set TIC0 pin */ + + MPC.PC6PFS.BYTE = 0x1du; + PORTC.PMR.BYTE |= 0x40u; + + /* Set TIC1 pin */ + + MPC.PE6PFS.BYTE = 0x1du; + PORTE.PMR.BYTE |= 0x40u; + + /* Set TOC0 pin */ + + MPC.PC7PFS.BYTE = 0x1du; + PORTC.PMR.BYTE |= 0x80u; + + /* Set TOC1 pin */ + + MPC.PE7PFS.BYTE = 0x1du; + PORTE.PMR.BYTE |= 0x80u; + + /* Attach the IRQ for poll expiry */ + + irq_attach(RX65N_INTB170_IRQ, (xcpt_t)rx65n_poll_expiry, NULL); + + /* Attach the IRQ for tx timeout */ + + irq_attach(RX65N_INTB171_IRQ, (xcpt_t)rx65n_txtimeout_expiry, NULL); +} + +/**************************************************************************** + * Name: rx65n_cmtw0_start + * + * Description: + * CMTW0 Timer Initialization + ****************************************************************************/ + +void rx65n_cmtw0_start(uint8_t type, uint32_t timeout) +{ + /* Update OC0I0 for polling */ + + if (type == rx65n_cmtw0_txpoll) + { + CMTW0.CMWOCR0 = CMTW0.CMWCNT + timeout; + + /* Enable OC0I0 interrupt in ICU */ + + IEN(PERIB, INTB170) = 1U; + + /* Enabling OC0 */ + + CMTW0.CMWIOR.WORD |= _1000_CMTW_CMWIOR_OC0E_ENABLE; + } + + /* Update OC0I1 for timeout */ + + if (type == rx65n_cmtw0_timeout) + { + CMTW0.CMWOCR1 = CMTW0.CMWCNT + timeout; + + /* Enable OC1I0 interrupt in ICU */ + + IEN(PERIB, INTB171) = 1U; + + /* Enabling OC1 */ + + CMTW0.CMWIOR.WORD |= _2000_CMTW_CMWIOR_OC1E_ENABLE; + } + + /* Start CMTW0 count */ + + CMTW0.CMWSTR.BIT.STR = 1U; +} + +/**************************************************************************** + * Name: rx65n_cmtw0_stop + * + * Description: + * CMTW0 Timer Initialization + ****************************************************************************/ + +void rx65n_cmtw0_stop(uint8_t type) +{ + /* STOP OC0I0 fot polling */ + + if (type == rx65n_cmtw0_txpoll) + { + /* Disable OC0I0 interrupt in ICU */ + + IEN(PERIB, INTB170) = 0U; + + /* Enabling OC0 */ + + CMTW0.CMWIOR.WORD &= ~(_1000_CMTW_CMWIOR_OC0E_ENABLE); + } + + /* Stop OC0I1 fot timeout */ + + if (type == rx65n_cmtw0_timeout) + { + /* Disable OC1I0 interrupt in ICU */ + + IEN(PERIB, INTB171) = 0U; + + /* Disabling OC1 */ + + CMTW0.CMWIOR.WORD &= ~(_2000_CMTW_CMWIOR_OC1E_ENABLE); + } +} diff --git a/arch/renesas/src/rx65n/rx65n_cmtw0.h b/arch/renesas/src/rx65n/rx65n_cmtw0.h new file mode 100644 index 00000000000..344abb4607e --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_cmtw0.h @@ -0,0 +1,113 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_cmtw0.h + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Surya Prakash + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef __ARCH_RENESAS_SRC_RX65N_CMTW0_H +#define __ARCH_RENESAS_SRC_RX65N_CMTW0_H + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "rx65n_cmtw.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Compare Match Constant Register (CMWCOR) */ + +#define _000000BB_CMTW0_CMWCOR_VALUE (0xfffffffful) + +/* Output Compare Registers 0 (CMWOCR0) */ + +#define _0000000A_CMTW0_CMWOCR0_VALUE (0x0000000aul) + +/* Output Compare Registers 1 (CMWOCR1) */ + +#define _0000000A_CMTW0_CMWOCR1_VALUE (0x0000000aul) + +/**************************************************************************** + * Public Function Prototypes + ***************************************************************************/ + +/**************************************************************************** + * Name: rx65n_cmtw0_create + * + * Description: + * Initializes CMTW0 Timer + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void rx65n_cmtw0_create(uint32_t txpoll_time, uint32_t txtimeout_time); + +/**************************************************************************** + * Name: rx65n_cmtw0_start + * + * Description: + * Start CMTW0 Timer + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void rx65n_cmtw0_start(uint8_t type, uint32_t timeout); + +/**************************************************************************** + * Name: rx65n_cmtw0_stop + * + * Description: + * Stop CMTW0 Timer + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void rx65n_cmtw0_stop(uint8_t type); + +#endif /* __ARCH_RENESAS_SRC_RX65N_CMTW0_H */ diff --git a/arch/renesas/src/rx65n/rx65n_copystate.c b/arch/renesas/src/rx65n/rx65n_copystate.c new file mode 100644 index 00000000000..505474c3908 --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_copystate.c @@ -0,0 +1,62 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/up_copystate.c + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include + +#include "up_internal.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_copystate + ****************************************************************************/ + +/* A little faster than most memcpy's */ + +void up_copystate(uint32_t *dest, uint32_t *src) +{ + memcpy(dest, src, XCPTCONTEXT_SIZE); +} diff --git a/arch/renesas/src/rx65n/rx65n_definitions.h b/arch/renesas/src/rx65n/rx65n_definitions.h new file mode 100644 index 00000000000..8fbf4313228 --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_definitions.h @@ -0,0 +1,504 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_definitions.h + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * Surya + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef __ARCH_RENESAS_SRC_RX65N_RX65N_DEFINITIONS_H +#define __ARCH_RENESAS_SRC_RX65N_RX65N_DEFINITIONS_H + +/**************************************************************************** + * Included Files + ***************************************************************************/ + +#include +#include "rx65n/iodefine.h" +#include "arch/board/board.h" + +/**************************************************************************** + * Pre-processor Definitions + ***************************************************************************/ + +/* Memory-mapped register addresses ****************************************/ + +#define RX65N_SCI0_BASE (uint32_t)&SCI0 +#define RX65N_SCI1_BASE (uint32_t)&SCI1 +#define RX65N_SCI2_BASE (uint32_t)&SCI2 +#define RX65N_SCI3_BASE (uint32_t)&SCI3 +#define RX65N_SCI4_BASE (uint32_t)&SCI4 +#define RX65N_SCI5_BASE (uint32_t)&SCI5 +#define RX65N_SCI6_BASE (uint32_t)&SCI6 +#define RX65N_SCI7_BASE (uint32_t)&SCI7 +#define RX65N_SCI8_BASE (uint32_t)&SCI8 +#define RX65N_SCI9_BASE (uint32_t)&SCI9 +#define RX65N_SCI10_BASE (uint32_t)&SCI10 +#define RX65N_SCI11_BASE (uint32_t)&SCI11 +#define RX65N_SCI12_BASE (uint32_t)&SCI12 + +/* Serial Communications interface (SCI) */ + +#define RX_SCISMR_CKSMASK (0x03) /* Bit 0-1: Internal clock source */ +#define RX_SCISMR_DIV1 (0x00) /* System clock (phi) */ +#define RX_SCISMR_DIV4 (0x01) /* phi/4 */ +#define RX_SCISMR_DIV16 (0x02) /* phi/16 */ +#define RX_SCISMR_DIV64 (0x03) /* phi/64 */ +#define RX_SCISMR_MP (0x04) /* Bit 2: Multiprocessor select */ +#define RX_SCISMR_STOP (0x08) /* Bit 3: 0:One stop bit, 1:Two stop bits */ +#define RX_SCISMR_OE (0x10) /* Bit 4: 0:Even parity, 1:Odd parity */ +#define RX_SCISMR_PE (0x20) /* Bit 5: Parity enable */ +#define RX_SCISMR_CHR (0x40) /* Bit 6: 0:8-bit data, 1:7-bit data */ +#define RX_SCISMR_CA (0x80) /* Bit 7: 0:Asynchronous, 1:clocked synchronous */ +#define RX_SCISCR_CKEMASK (0x03) /* Bit 0-1: Internal clock source */ + +/* Asynchronous mode: */ + +/* Internal clock, SCK pin used for input pin */ + +#define RX_SCISCR_AISIN (0x00) + +/* Internal clock, SCK pin used for clock output */ + +#define RX_SCISCR_AISOUT (0x01) + +/* External clock, SCK pin used for clock input */ + +#define RX_SCISCR_AXSIN1 (0x02) + +/* External clock, SCK pin used for clock input */ + +#define RX_SCISCR_AXSIN2 (0x03) + +/* Synchronous mode: */ + +/* Internal clock, SCK pin used for clock output */ + +#define RX_SCISCR_SISOUT2 (0x01) + +/* External clock, SCK pin used for clock input */ + +#define RX_SCISCR_SXSIN1 (0x02) + +/* External clock, SCK pin used for clock input */ + +#define RX_SCISCR_SXSIN2 (0x03) + +/* Bit 2: 1=Transmit end interrupt enable */ + +#define RX_SCISCR_TEIE (0x04) + +/* Bit 3: 1=Multiprocessor interrupt enable */ + +#define RX_SCISCR_MPIE (0x08) +#define RX_SCISCR_RE (0x10) /* Bit 4: 1=Receiver enable */ +#define RX_SCISCR_TE (0x20) /* Bit 5: 1=Transmitter enable */ + +/* Bit 6: 1=Recieve-data-full interrupt enable */ + +#define RX_SCISCR_RIE (0x40) + +/* Bit 7: 1=Transmit-data-empty interrupt enable */ + +#define RX_SCISCR_TIE (0x80) +#define RX_SCISCR_ALLINTS (0xcc) + +/* Bit 0: Multi-processor Bit in Transmit data */ + +#define RX_SCISSR_MPBT (0x01) + +/* Bit 1: Multi-processor Bit in receive data */ + +#define RX_SCISSR_MPB (0x02) +#define RX_SCISSR_TEND (0x04) /* Bit 2: End of transmission */ +#define RX_SCISSR_PER (0x08) /* Bit 3: Receive parity error */ +#define RX_SCISSR_FER (0x10) /* Bit 4: Receive framing error */ +#define RX_SCISSR_ORER (0x20) /* Bit 5: Receive overrun error */ + +/* Bit 6: RDR contains valid received data */ + +#define RX_SCISSR_RDRF (0x40) + +/* Bit 7: TDR does not contain valid transmit data */ + +#define RX_SCISSR_TDRE (0x80) +#define RX65N_CMT_CMSTR0_ADDR (0x00088000) /* 8-bits wide */ +#define RX65N_CMT0_CMCNT_ADDR (0x00088004) +#define RX65N_CMT0_CMCOR_ADDR (0x00088006) +#define RX65N_CMT0_CMCR_ADDR (0x00088002) + +/* CMTW0 used for Ethernet TX polling and TX timeout */ + +#define RX65N_CMTW0_CMWSTR_ADDR (0x00094200) +#define RX65N_CMTW0_CMWCR_ADDR (0x00094204) +#define RX65N_CMTW0_CMWIOR_ADDR (0x00094208) +#define RX65N_CMTW0_CMWCNT_ADDR (0x00094210) +#define RX65N_CMTW0_CMWCOR_ADDR (0x00094214) +#define RX65N_CMTW0_CMWICR0_ADDR (0x00094218) +#define RX65N_CMTW0_CMWICR1_ADDR (0x0009421c) +#define RX65N_CMTW0_CMWOCR0_ADDR (0x00094220) +#define RX65N_CMTW0_CMWOCR1_ADDR (0x00094224) +#define RX65N_CMTW0_TICKFREQ (1) /* 1Hz tick frequency */ +#define RX65N_CMTW0_DIV_VALUE (32) +#define RX65N_CMTW0_COUNT_VALUE_FOR_TXPOLL ((RX_PCLKB / RX65N_CMTW0_DIV_VALUE)/(RX65N_CMTW0_TICKFREQ)) +#define RX65N_CMTW0_COUNT_VALUE_FOR_TXTIMEOUT (((RX_PCLKB / RX65N_CMTW0_DIV_VALUE)/(RX65N_CMTW0_TICKFREQ))*60) +#define rx65n_cmtw0_txpoll 1 +#define rx65n_cmtw0_timeout 2 + +#define RX65N_MSTPCRA_ADDR (0x00080010) +#define RX65N_CMT0_TICKFREQ (100) /* 100Hz tick frequency */ +#define RX65N_CMT_DIV32 (0x0001) +#define RX65N_CMT0_DIV_VALUE (32) +#define RX65N_CMT0_COUNT_VALUE ((RX_PCLKB / RX65N_CMT0_DIV_VALUE)/(RX65N_CMT0_TICKFREQ)) +#define RX65N_CMT_CMCR_INIT (RX65N_CMT_DIV32 |\ + RX65N_CMT_CMCR_CMIE_ENABLE |\ + RX65N_CMT_CMCR_DEFAULT) +#define RX65N_CMTW_DIV32 (0x0001) +#define RX65N_CMTW_CMWCR_INIT (RX65N_CMTW_DIV32 |\ + RX65N_CMTW_CMWCR_CMWIE_ENABLE |\ + RX65N_CMTW_CMWCR_DEFAULT) +#define RX65N_CMTW_CMWCR_DEFAULT (0x0000) +#define RX65N_CMTW_CMWCR_CMWIE_ENABLE (0x0008) + +#define RX65N_CMT_CMCR_DEFAULT (0x0080) +#define RX65N_CMT_CMCR_CMIE_ENABLE (0x0040) +#define RX65N_CMT_MSTPCRA_STOP (0x00008000) /*Release unit0(CMT0 and CMT1) from module stop state*/ +#define RX65N_CMT_UNIT1_MSTPCRA_STOP (0x00004000) /*Release unit1(CMT2 and CMT3) from module stop state*/ +#define RX65N_CMTW_UNIT1_MSTPCRA_STOP (0x00000001) /*Release CMTW unit1 from module stop state*/ +#define RX65N_CMTW_UNIT0_MSTPCRA_STOP (0x00000002) /*Release CMTW unit0 from module stop state*/ +#define RX65N_CMTCMSTR0_STR0 (0x0001) /* Bit 0: TCNT0 is counting */ +#define RX65N_CMTCMSTR0_STR1 (0x0002) /* Bit 1: TCNT1 is counting */ +#define RX65N_CMTCMSTR1_STR2 (0x0001) /* Bit 0: TCNT0 is counting */ +#define RX65N_CMTCMSTR1_STR3 (0x0002) /* Bit 1: TCNT1 is counting */ +#define RX65N_PRCR_ADDR (0x000803fe) +#define RX65N_PRCR_VALUE (0xa50b) +#define RX65N_GRPBE0_ADDR (0x00087600) +#define RX65N_GRPBL0_ADDR (0x00087630) +#define RX65N_GRPBL1_ADDR (0x00087634) +#define RX65N_GRPBL2_ADDR (0x00087638) +#define RX65N_GRPAL0_ADDR (0x00087830) +#define RX65N_GRPAL1_ADDR (0x00087834) +#define RX65N_GENBE0_ADDR (0x00087640) +#define RX65N_GENBL0_ADDR (0x00087670) +#define RX65N_GENBL1_ADDR (0x00087674) +#define RX65N_GENBL2_ADDR (0x00087678) +#define RX65N_GENAL0_ADDR (0x00087870) +#define RX65N_GENAL1_ADDR (0x00087874) +#define RX65N_GRPBL0_TEI0_MASK (1U << 0) /* (0x00000001) */ +#define RX65N_GRPBL0_ERI0_MASK (1U << 1) /* (0x00000002) */ +#define RX65N_GRPBL0_TEI1_MASK (1U << 2) /* (0x00000004) */ +#define RX65N_GRPBL0_ERI1_MASK (1U << 3) /* (0x00000008) */ +#define RX65N_GRPBL0_TEI2_MASK (1U << 4) /* (0x00000010) */ +#define RX65N_GRPBL0_ERI2_MASK (1U << 5) /* (0x00000020) */ +#define RX65N_GRPBL0_TEI3_MASK (1U << 6) /* (0x00000040) */ +#define RX65N_GRPBL0_ERI3_MASK (1U << 7) /* (0x00000080) */ +#define RX65N_GRPBL0_TEI4_MASK (1U << 8) /* (0x00000100) */ +#define RX65N_GRPBL0_ERI4_MASK (1U << 9) /* (0x00000200) */ +#define RX65N_GRPBL0_TEI5_MASK (1U << 10) /* (0x00000400) */ +#define RX65N_GRPBL0_ERI5_MASK (1U << 11) /* (0x00000800) */ +#define RX65N_GRPBL0_TEI6_MASK (1U << 12) /* (0x00001000) */ +#define RX65N_GRPBL0_ERI6_MASK (1U << 13) /* (0x00002000) */ +#define RX65N_GRPBL0_TEI7_MASK (1U << 14) /* (0x00004000) */ +#define RX65N_GRPBL0_ERI7_MASK (1U << 15) /* (0x00008000) */ +#define RX65N_GRPBL1_TEI8_MASK (1U << 24) +#define RX65N_GRPBL1_ERI8_MASK (1U << 25) +#define RX65N_GRPBL1_TEI9_MASK (1U << 26) +#define RX65N_GRPBL1_ERI9_MASK (1U << 27) +#define RX65N_GRPAL0_TEI10_MASK (1U << 8) +#define RX65N_GRPAL0_ERI10_MASK (1U << 9) +#define RX65N_GRPAL0_TEI11_MASK (1U << 12) +#define RX65N_GRPAL0_ERI11_MASK (1U << 13) +#define RX65N_GRPBL0_TEI12_MASK (1U << 16) +#define RX65N_GRPBL0_ERI12_MASK (1U << 17) + +/* Start Ethernet and EDMAC Interface */ + +/* ETHERC and EDMAC base Addresses */ + +#define RX65N_EDMAC0_BASE (0x000c0000) /* EDMAC base address */ +#define RX65N_ETHERC0_BASE (0x000c0100) /* Ethernet MAC base address */ + +/* Ethernet Addresses */ + +/* Register Offsets */ + +/* MAC Registers */ + +#define RX65N_ETH_ECMR_OFFSET (0x0000) /* ETHERC Mode register */ +#define RX65N_ETH_RFLR_OFFSET (0x0008) /* Receive Frame Maximum Length Register */ +#define RX65N_ETH_ECSR_OFFSET (0x0010) /* ETHERC Status Register */ +#define RX65N_ETH_ECSIPR_OFFSET (0x0018) /* ETHERC Interrupt Enable Register */ +#define RX65N_ETH_PIR_OFFSET (0x0020) /* PHY Interface Register */ +#define RX65N_ETH_PSR_OFFSET (0x0028) /* PHY Status Register */ +#define RX65N_ETH_RDMLR_OFFSET (0x0040) /* Random Number Generation Counter Limit Setting Register */ +#define RX65N_ETH_IPGR_OFFSET (0x0050) /* Interpacket Gap Register */ +#define RX65N_ETH_APR_OFFSET (0x0054) /* Automatic PAUSE Frame Register */ +#define RX65N_ETH_MPR_OFFSET (0x0058) /* Manual PAUSE Frame Register */ +#define RX65N_ETH_RFCF_OFFSET (0x0060) /* Received PAUSE Frame Counter */ +#define RX65N_ETH_TPAUSER_OFFSET (0x0064) /* PAUSE Frame Retransmit Count Setting Register */ +#define RX65N_ETH_TPAUSECR_OFFSET (0x0068) /* PAUSE Frame Retransmit Counter */ +#define RX65N_ETH_BCFRR_OFFSET (0x006c) /* Broadcast Frame Receive Count Setting Register */ +#define RX65N_ETH_MAHR_OFFSET (0x00c0) /* MAC Address Upper Bit Register */ +#define RX65N_ETH_MALR_OFFSET (0x00c8) /* MAC Address Lower Bit Register */ +#define RX65N_ETH_TROCR_OFFSET (0x00d0) /* Transmit Retry Over Counter Register */ +#define RX65N_ETH_CDCR_OFFSET (0x00d4) /* Late Collision Detect Counter Register */ +#define RX65N_ETH_LCCR_OFFSET (0x00d8) /* Lost Carrier Counter Register */ +#define RX65N_ETH_CNDCR_OFFSET (0x00dc) /* Carrier Not Detect Counter Register */ +#define RX65N_ETH_CEFCR_OFFSET (0x00e4) /* CRC Error Frame Receive Counter Register */ +#define RX65N_ETH_FRECR_OFFSET (0x00e8) /* Frame Receive Error Counter Register */ +#define RX65N_ETH_TSFRCR_OFFSET (0x00ec) /* Too-Short Frame Receive Counter Register */ +#define RX65N_ETH_TLFRCR_OFFSET (0x00f0) /* Too-Long Frame Receive Counter Register */ +#define RX65N_ETH_RFCR_OFFSET (0x00f4) /* Received Alignment Error Frame Counter Register */ +#define RX65N_ETH_MAFCR_OFFSET (0x00f8) /* Multicast Address Frame Receive Counter Register */ + +/* DMA Registers */ + +#define RX65N_ETHD_EDMR_OFFSET (0x0000) /* EDMAC Mode Register */ +#define RX65N_ETHD_EDTRR_OFFSET (0x0008) /* EDMAC Transmit Request Register */ +#define RX65N_ETHD_EDRRR_OFFSET (0x0010) /* EDMAC Receive Request Register */ +#define RX65N_ETHD_TDLAR_OFFSET (0x0018) /* Transmit Descriptor List Start Address Register */ +#define RX65N_ETHD_RDLAR_OFFSET (0x0020) /* Receive Descriptor List Start Address Register */ +#define RX65N_ETHD_EESR_OFFSET (0x0028) /* ETHERC/EDMAC Status Register */ +#define RX65N_ETHD_EESIPR_OFFSET (0x0030) /* ETHERC/EDMAC Status Interrupt Enable Register */ +#define RX65N_ETHD_TRSCER_OFFSET (0x0038) /* ETHERC/EDMAC Transmit/Receive Status Copy Enable Register */ +#define RX65N_ETHD_RMFCR_OFFSET (0x0040) /* Missed-Frame Counter Register */ +#define RX65N_ETHD_TFTR_OFFSET (0x0048) /* Transmit FIFO Threshold Register */ +#define RX65N_ETHD_FDR_OFFSET (0x0050) /* FIFO Depth Register */ +#define RX65N_ETHD_RMCR_OFFSET (0x0058) /* Receive Method Control Register */ +#define RX65N_ETHD_TFUCR_OFFSET (0x0064) /* Transmit FIFO Underflow Counter */ +#define RX65N_ETHD_RFOCR_OFFSET (0x0068) /* Receive FIFO Overflow Counter */ +#define RX65N_ETHD_IOSR_OFFSET (0x006c) /* Independent Output Signal Setting Register */ +#define RX65N_ETHD_FCFTR_OFFSET (0x0070) /* Flow Control Start FIFO Threshold Setting Register */ +#define RX65N_ETHD_RPADIR_OFFSET (0x0078) /* Receive Data Padding Insert Register */ +#define RX65N_ETHD_TRIMD_OFFSET (0x007c) /* Transmit Interrupt Setting Register */ +#define RX65N_ETHD_RBWAR_OFFSET (0x00c8) /* Receive Buffer Write Address Register */ +#define RX65N_ETHD_RDFAR_OFFSET (0x00cc) /* Receive Descriptor Fetch Address Register */ +#define RX65N_ETHD_TBRAR_OFFSET (0x00d4) /* Transmit Buffer Read Address Register */ +#define RX65N_ETHD_TDFAR_OFFSET (0x00d8) /* Transmit Descriptor Fetch Address Register */ + +/* Register Base Addresses */ + +/* MAC Registers */ + +#define RX65N_ETH_ECMR (RX65N_ETHERC0_BASE+RX65N_ETH_ECMR_OFFSET) +#define RX65N_ETH_RFLR (RX65N_ETHERC0_BASE+RX65N_ETH_RFLR_OFFSET) +#define RX65N_ETH_ECSR (RX65N_ETHERC0_BASE+RX65N_ETH_ECSR_OFFSET) +#define RX65N_ETH_ECSIPR (RX65N_ETHERC0_BASE+RX65N_ETH_ECSIPR_OFFSET) +#define RX65N_ETH_PIR (RX65N_ETHERC0_BASE+RX65N_ETH_PIR_OFFSET) +#define RX65N_ETH_PSR (RX65N_ETHERC0_BASE+RX65N_ETH_PSR_OFFSET) +#define RX65N_ETH_RDMLR (RX65N_ETHERC0_BASE+RX65N_ETH_RDMLR_OFFSET) +#define RX65N_ETH_IPGR (RX65N_ETHERC0_BASE+RX65N_ETH_IPGR_OFFSET) +#define RX65N_ETH_APR (RX65N_ETHERC0_BASE+RX65N_ETH_APR_OFFSET) +#define RX65N_ETH_MPR (RX65N_ETHERC0_BASE+RX65N_ETH_MPR_OFFSET) +#define RX65N_ETH_RFCF (RX65N_ETHERC0_BASE+RX65N_ETH_RFCF_OFFSET) +#define RX65N_ETH_TPAUSER (RX65N_ETHERC0_BASE+RX65N_ETH_TPAUSER_OFFSET) +#define RX65N_ETH_TPAUSECR (RX65N_ETHERC0_BASE+RX65N_ETH_TPAUSECR_OFFSET) +#define RX65N_ETH_BCFRR (RX65N_ETHERC0_BASE+RX65N_ETH_BCFRR_OFFSET) +#define RX65N_ETH_MAHR (RX65N_ETHERC0_BASE+RX65N_ETH_MAHR_OFFSET) +#define RX65N_ETH_MALR (RX65N_ETHERC0_BASE+RX65N_ETH_MALR_OFFSET) +#define RX65N_ETH_TROCR (RX65N_ETHERC0_BASE+RX65N_ETH_TROCR_OFFSET) +#define RX65N_ETH_CDCR (RX65N_ETHERC0_BASE+RX65N_ETH_CDCR_OFFSET) +#define RX65N_ETH_LCCR (RX65N_ETHERC0_BASE+RX65N_ETH_LCCR_OFFSET) +#define RX65N_ETH_CNDCR (RX65N_ETHERC0_BASE+RX65N_ETH_CNDCR_OFFSET) +#define RX65N_ETH_CEFCR (RX65N_ETHERC0_BASE+RX65N_ETH_CEFCR_OFFSET) +#define RX65N_ETH_FRECR (RX65N_ETHERC0_BASE+RX65N_ETH_FRECR_OFFSET) +#define RX65N_ETH_TSFRCR (RX65N_ETHERC0_BASE+RX65N_ETH_TSFRCR_OFFSET) +#define RX65N_ETH_TLFRCR (RX65N_ETHERC0_BASE+RX65N_ETH_TLFRCR_OFFSET) +#define RX65N_ETH_RFCR (RX65N_ETHERC0_BASE+RX65N_ETH_RFCR_OFFSET) +#define RX65N_ETH_MAFCR (RX65N_ETHERC0_BASE+RX65N_ETH_MAFCR_OFFSET) + +/* DMA Registers */ + +#define RX65N_ETHD_EDMR (RX65N_EDMAC0_BASE+RX65N_ETHD_EDMR_OFFSET) +#define RX65N_ETHD_EDTRR (RX65N_EDMAC0_BASE+RX65N_ETHD_EDTRR_OFFSET) +#define RX65N_ETHD_EDRRR (RX65N_EDMAC0_BASE+RX65N_ETHD_EDRRR_OFFSET) +#define RX65N_ETHD_TDLAR (RX65N_EDMAC0_BASE+RX65N_ETHD_TDLAR_OFFSET) +#define RX65N_ETHD_RDLAR (RX65N_EDMAC0_BASE+RX65N_ETHD_RDLAR_OFFSET) +#define RX65N_ETHD_EESR (RX65N_EDMAC0_BASE+RX65N_ETHD_EESR_OFFSET) +#define RX65N_ETHD_EESIPR (RX65N_EDMAC0_BASE+RX65N_ETHD_EESIPR_OFFSET) +#define RX65N_ETHD_TRSCER (RX65N_EDMAC0_BASE+RX65N_ETHD_TRSCER_OFFSET) +#define RX65N_ETHD_RMFCR (RX65N_EDMAC0_BASE+RX65N_ETHD_RMFCR_OFFSET) +#define RX65N_ETHD_TFTR (RX65N_EDMAC0_BASE+RX65N_ETHD_TFTR_OFFSET) +#define RX65N_ETHD_FDR (RX65N_EDMAC0_BASE+RX65N_ETHD_FDR_OFFSET) +#define RX65N_ETHD_RMCR (RX65N_EDMAC0_BASE+RX65N_ETHD_RMCR_OFFSET) +#define RX65N_ETHD_TFUCR (RX65N_EDMAC0_BASE+RX65N_ETHD_TFUCR_OFFSET) +#define RX65N_ETHD_RFOCR (RX65N_EDMAC0_BASE+RX65N_ETHD_RFOCR_OFFSET) +#define RX65N_ETHD_IOSR (RX65N_EDMAC0_BASE+RX65N_ETHD_IOSR_OFFSET) +#define RX65N_ETHD_FCFTR (RX65N_EDMAC0_BASE+RX65N_ETHD_FCFTR_OFFSET) +#define RX65N_ETHD_RPADIR (RX65N_EDMAC0_BASE+RX65N_ETHD_RPADIR_OFFSET) +#define RX65N_ETHD_TRIMD (RX65N_EDMAC0_BASE+RX65N_ETHD_TRIMD_OFFSET) +#define RX65N_ETHD_RBWAR (RX65N_EDMAC0_BASE+RX65N_ETHD_RBWAR_OFFSET) +#define RX65N_ETHD_RDFAR (RX65N_EDMAC0_BASE+RX65N_ETHD_RDFAR_OFFSET) +#define RX65N_ETHD_TBRAR (RX65N_EDMAC0_BASE+RX65N_ETHD_TBRAR_OFFSET) +#define RX65N_ETHD_TDFAR (RX65N_EDMAC0_BASE+RX65N_ETHD_TDFAR_OFFSET) + +/* MPC (Multifunction pin controller) Registers for Ethernet */ + +#define RX65N_MPC_PFENET (0x0008c10e) +#define RX65N_MPC_PWPR (0x0008c11f) + +/* (Module control Registers) for Ethernet */ + +#define RX65N_MSTP_CRB (0x00080014) + +/* Register Bit-Field Definitions */ + +/* MAC Registers */ + +#define ETH_ECSR_LCHNG (1 << 2) /* Bit 2: Link Signal Change Flag */ + +/* Bit 2: LINK Signal Change Interrupt enable/disable */ + +#define ETH_ECSIPR_LCHNGIP (1 << 2) +#define ETH_ECMR_CLR (0x00000000) + +/* Clear all ETHERC status BFR, PSRTO, LCHNG, MPD, ICD */ + +#define ETH_ECSR_CLR (0x00000037) +#define ETH_ECMR_RE (1 << 6) /* Transmit function is enabled */ +#define ETH_ECMR_TE (1 << 5) /* Receive function is enabled */ +#define ETH_ECMR_DM (1 << 1) /* Duplex Mode */ +#define ETH_ECMR_RTM (1 << 2) /* Bit Rate */ + +/* Bit 4:0:Interpacket Gap 96 bit time (initial value) */ + +#define ETH_IPGR_IPG_INITIAL (0x00000014) + +/* Receive Frame Maximum Length */ + +#define ETH_RFLR_RFL (1518) + +/* EDMA Registers */ + +/* Bit 22: ETHERC status interrupt request is enable/disabled. */ + +#define ETHD_EDMR_SWR (1 << 0) + +/* Bit 6: Big Endian Mode/Little Endian Mode */ + +#define ETHD_EDMR_DE (1 << 6) + +/* Clear all EDMAC status bits */ + +#define ETHD_EESR_EDMAC (0x47ff0f9f) + +/* Frame transfer Complete status Flag check */ + +#define ETHD_EESR_TC (1 << 21) + +/* ETHERC/EDMAC Status Register Source Flag */ + +#define ETHD_EESR_ECI (1 << 22) +#define ETHD_EESR_FR (1 << 18) /* Frame Receive Flag */ + +/* Frame Receive Interrupt Request Enable */ + +#define ETHD_EESIPR_FRIP (1 << 18) + +/* Frame Transfer Complete Interrupt Request Enable */ + +#define ETHD_EESIPR_TCIP (1 << 21) + +/* ETHERC/EDMAC Status Register Source Interrupt Request Enable */ + +#define ETHD_EESIPR_ECIIP (1 << 22) + +/* ETHERC/EDMAC Write-Back Complete Interrupt Request Enable */ + +#define ETHD_EESIPR_TWBIP (1 << 30) + +/* Bit 0:10: Transmit FIFO Threshold */ + +#define ETHD_TFTR_TFT (0x00000000) + +/* Bit: 20: Transmit Descriptor Empty Flag */ + +#define ETHD_EESR_TDE (1<20) + +/* Ether PSR register */ + +#define ETH_PSR_LMON (1) + +/* End Ethernet and EDMAC Interface */ + +/* General Values LED: */ + +#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) || defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB) +# define LED_ON (0) +# define LED_OFF (1) +#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE) +# define LED_ON (1) +# define LED_OFF (0) +#else +# error "No Selection for PORT definition in rx65n_port.c" +#endif + +/* Bit Set Values */ + +#define SET_BIT_HIGH (1) +#define SET_BIT_LOW (0) +#define SET_BYTE_HIGH (0xff) +#define SET_BYTE_LOW (0x00) + +/**************************************************************************** + * Public Types + ***************************************************************************/ + +/**************************************************************************** + * Public Data + ***************************************************************************/ + +#ifndef __ASSEMBLER__ +/* Serial Communications interface (SCI) */ + +enum E_RX_SCI +{ + RX_SCI_SMR_OFFSET = 0, + RX_SCI_BRR_OFFSET, + RX_SCI_SCR_OFFSET, + RX_SCI_TDR_OFFSET, + RX_SCI_SSR_OFFSET, + RX_SCI_RDR_OFFSET, + RX_SCI_SCMR_OFFSET, + RX_SCI_SEMR_OFFSET, + RX_SCI_SNFR_OFFSET, + RX_SCI_SIMR1_OFFSET, + RX_SCI_SIMR2_OFFSET, + RX_SCI_SIMR3_OFFSET, + RX_SCI_SISR_OFFSET, + RX_SCI_SPMR_OFFSET, + RX_SCI_THRHL_OFFSET, + RX_SCI_RDRHL_OFFSET, + RX_SCI_MDDR_OFFSET +}; +#endif /* __ASSEMBLER__ */ + +#endif /* __ARCH_RENESAS_SRC_RX65N_RX65N_DEFINITIONS_H */ diff --git a/arch/renesas/src/rx65n/rx65n_dumpstate.c b/arch/renesas/src/rx65n/rx65n_dumpstate.c new file mode 100644 index 00000000000..20c4556c86a --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_dumpstate.c @@ -0,0 +1,243 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_dumpstate.c + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include +#include + +#include "up_arch.h" +#include "up_internal.h" +#include "sched/sched.h" +#include "chip.h" +#include "rx65n/irq.h" + +#ifdef CONFIG_ARCH_STACKDUMP + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +static uint32_t s_last_regs[XCPTCONTEXT_REGS]; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rx65n_getsp + ****************************************************************************/ + +static inline uint16_t rx65n_getsp(void) +{ + uint16_t sp; + + __asm__ __volatile__("\tmvfc usp, %0\n\t": "=r" (sp):: "memory"); /* check */ + + return sp; +} + +/**************************************************************************** + * Name: rx65n_getusersp + ****************************************************************************/ + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 +static inline uint16_t rx65n_getusersp(void) +{ + uint8_t *ptr = (uint8_t *) g_current_regs; + return (uint16_t)ptr[REG_SP] << 8 | ptr[REG_SP + 1]; /* check */ +} +#endif + +/**************************************************************************** + * Name: rx65n_stackdump + ****************************************************************************/ + +static void rx65n_stackdump(uint16_t sp, uint16_t stack_base) +{ + uint16_t stack; + + for (stack = sp & ~7; stack < stack_base; stack += 8) /* check */ + + { + uint8_t *ptr = (uint8_t *)&stack; + _alert("%04x: %02x %02x %02x %02x %02x %02x %02x %02x\n", + stack, ptr[0], ptr[1], ptr[2], ptr[3], + ptr[4], ptr[5], ptr[6], ptr[7]); + } +} + +/**************************************************************************** + * Name: rx65n_registerdump + ****************************************************************************/ + +static inline void rx65n_registerdump(void) +{ + uint8_t *ptr = (uint8_t *) g_current_regs; + uint32_t regs[XCPTCONTEXT_SIZE]; + + /* Are user registers available from interrupt processing? */ + + if (ptr == NULL) + { + /* No.. capture user registers by hand */ + + up_saveusercontext((uint32_t *)s_last_regs); + *regs = *s_last_regs; + } + + /* Dump the interrupt registers */ + + _alert("PC: %08x PSW=%08x\n", + ptr[REG_PC], ptr[REG_PSW]); + + _alert("FPSW: %08x ACC0LO: %08x ACC0HI: %08x ACC0GU: %08x" + "ACC1LO: %08x ACC1HI: %08x ACC1GU: %0.8x\n", + ptr[REG_FPSW], ptr[REG_ACC0LO], ptr[REG_ACC0HI], + ptr[REG_ACC0GU], ptr[REG_ACC1LO], + ptr[REG_ACC1HI], ptr[REG_ACC1GU]); + + _alert("R%d:%08x %08x %08x %08x %08x %08x %08x\n", 0, + ptr[REG_R1], ptr[REG_R2], ptr[REG_R3], + ptr[REG_R4], ptr[REG_R5], ptr[REG_R6], ptr[REG_R7]); + + _alert("R%d: %08x %08x %08x %08x %08x %08x %08x %08x\n", 8, + ptr[REG_R8], ptr[REG_R9], ptr[REG_R10], ptr[REG_R11], + ptr[REG_R12], ptr[REG_R13], ptr[REG_R14], ptr[REG_R15]); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_dumpstate + ****************************************************************************/ + +void up_dumpstate(void) +{ + struct tcb_s *rtcb = running_task(); + uint32_t sp = rx65n_getsp(); + uint32_t ustackbase; + uint32_t ustacksize; +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + uint32_t istackbase; + uint32_t istacksize; +#endif + + /* Dump the registers (if available) */ + + rx65n_registerdump(); + + /* Get the limits on the user stack memory */ + + if (rtcb->pid == 0) /* Check for CPU0 IDLE thread */ + { + ustackbase = g_idle_topstack - 1; + ustacksize = CONFIG_IDLETHREAD_STACKSIZE; + } + else + { + ustackbase = (uint32_t)rtcb->adj_stack_ptr; + ustacksize = (uint16_t)rtcb->adj_stack_size; + } + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + istackbase = ebss; /* check how to declare ebss, as of now declared in chip.h */ + + istacksize = CONFIG_ARCH_INTERRUPTSTACK; + + /* Show interrupt stack info */ + + _alert("sp: %04x\n", sp); + _alert("IRQ stack:\n"); + _alert(" base: %04x\n", istackbase); + _alert(" size: %04x\n", istacksize); + + /* Does the current stack pointer lie within the interrupt + * stack? + */ + + if (sp <= istackbase && sp > istackbase - istacksize) + { + /* Yes.. dump the interrupt stack */ + + rx65n_stackdump(sp, istackbase); + + /* Extract the user stack pointer from the register area */ + + sp = rx65n_getusersp(); + _alert("sp: %04x\n", sp); + } + else if (g_current_regs) + { + _alert("ERROR: Stack pointer is not within the interrupt stack\n"); + rx65n_stackdump(istackbase - istacksize, istackbase); + } + + /* Show user stack info */ + + _alert("User stack:\n"); + _alert(" base: %04x\n", ustackbase); + _alert(" size: %04x\n", ustacksize); +#else + _alert("sp: %04x\n", sp); + _alert("stack base: %04x\n", ustackbase); + _alert("stack size: %04x\n", ustacksize); +#endif + + /* Dump the user stack if the stack pointer lies within the allocated user + * stack memory. + */ + + if (sp > ustackbase || sp <= ustackbase - ustacksize) + { + _alert("ERROR: Stack pointer is not within allocated stack\n"); + rx65n_stackdump(ustackbase - ustacksize, ustackbase); + } + else + { + rx65n_stackdump(sp, ustackbase); + } +} + +#endif /* CONFIG_ARCH_STACKDUMP */ diff --git a/arch/renesas/src/rx65n/rx65n_eth.c b/arch/renesas/src/rx65n/rx65n_eth.c new file mode 100644 index 00000000000..6ccec8acfd9 --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_eth.c @@ -0,0 +1,4423 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_eth.c + * 10/100 Base-T Ethernet driver for the RX65N family + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Surya + * + * This logic derives from the NuttX Ethernet Skeleton driver, STM32 ethernet + * driver and + * RX65N-rsk2mb baremetal code + * This code has a BSD compatible license that requires this copyright notice: + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the names NuttX nor Atmel nor the names of its contributors + * may be used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#if defined(CONFIG_NET) && defined(CONFIG_RX65N_EMAC) + +#include +#include +#include +#include +#include +#include +#include + +#include + +#include +#include +#include +#include +#include +#include +#include +#include + +#if defined(CONFIG_ARCH_PHY_INTERRUPT) +# include +#endif + +#if defined(CONFIG_NET_PKT) +# include +#endif + +#include "up_internal.h" + +#include "chip.h" +#include "up_arch.h" +#include "rx65n_definitions.h" +#include "rx65n_eth.h" +#include "rx65n_cmt.h" +#include "rx65n_cmtw.h" +#include "rx65n_cmtw0.h" + +#include + +#if RX65N_NETHERNET > 0 + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#if RX65N_NETHERNET > 1 +# error "Logic to support multiple Ethernet interfaces is incomplete" +#endif + +#define RX65N_EMAC0_DEVNAME "eth0" + +/* Work queue support is required. */ + +#if !defined (CONFIG_SCHED_WORKQUEUE) +# error Work queue support is required +#endif + +/* The low priority work queue is preferred. If it is not enabled, LPWORK + * will be the same as HPWORK. + * + * NOTE: However, the network should NEVER run on the high priority work + * queue! That queue is intended only to service short back end interrupt + * processing that never suspends. Suspending the high priority work queue + * may bring the system to its knees! + */ + +#define ETHWORK LPWORK + +#ifndef CONFIG_RX65N_EMAC0_PHYADDR +# error "CONFIG_RX65N_EMAC0_PHYADDR must be defined in the NuttX configuration" +#endif + +#if !defined(CONFIG_RX65N_EMAC0_MII) && !defined(CONFIG_RX65N_EMAC0_RMII) +# warning "Neither CONFIG_RX65N_EMAC0_MII nor CONFIG_RX65N_EMAC0_RMII defined" +#endif + +#if defined(CONFIG_RX65N_EMAC0_MII) && defined(CONFIG_RX65N_EMAC0_RMII) +# error "Both CONFIG_RX65N_EMAC0_MII and CONFIG_RX65N_EMAC0_RMII defined" +#endif + +#ifdef CONFIG_RX65N_EMAC0_AUTONEG +# ifndef CONFIG_RX65N_EMAC0_PHYSR +# error "CONFIG_RX65N_EMAC0_PHYSR must be defined in the NuttX configuration" +# endif +# ifdef CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG +# ifndef CONFIG_RX65N_EMAC0_PHYSR_ALTMODE +# error "CONFIG_RX65N_EMAC0_PHYSR_ALTMODE must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_RX65N_EMAC0_PHYSR_10HD +# error "CONFIG_RX65N_EMAC0_PHYSR_10HD must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_RX65N_EMAC0_PHYSR_100HD +# error "CONFIG_RX65N_EMAC0_PHYSR_100HD must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_RX65N_EMAC0_PHYSR_10FD +# error "CONFIG_RX65N_EMAC0_PHYSR_10FD must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_RX65N_EMAC0_PHYSR_100FD +# error "CONFIG_RX65N_EMAC0_PHYSR_100FD must be defined in the NuttX configuration" +# endif +# else +# ifndef CONFIG_RX65N_EMAC0_PHYSR_SPEED +# error "CONFIG_RX65N_EMAC0_PHYSR_SPEED must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_RX65N_EMAC0_PHYSR_100MBPS +# error "CONFIG_RX65N_EMAC0_PHYSR_100MBPS must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_RX65N_EMAC0_PHYSR_MODE +# error "CONFIG_RX65N_EMAC0_PHYSR_MODE must be defined in the NuttX configuration" +# endif +# ifndef CONFIG_RX65N_EMAC0_PHYSR_FULLDUPLEX +# error "CONFIG_RX65N_EMAC0_PHYSR_FULLDUPLEX must be defined in the NuttX configuration" +# endif +# endif +#endif + +/* This driver does not use enhanced descriptors. Enhanced descriptors must + * be used, however, if time stamping and/or IPv4 checksum offload is + * supported. + */ +#undef CONFIG_RX65N_ETH_ENHANCEDDESC +#undef CONFIG_RX65N_ETH_HWCHECKSUM + +/* Add 4 to the configured buffer size to account for the 2 byte checksum + * memory needed at the end of the maximum size packet. Buffer sizes must + * be an even multiple of 4, 8, 16 or 32bytes (depending on buswidth). We + * will use the 32-byte alignment in all cases. + */ + +#define OPTIMAL_ETH_BUFSIZE ((CONFIG_NET_ETH_PKTSIZE + 4 + 31) & ~31) + +#ifndef CONFIG_RX65N_ETH_BUFSIZE +# define CONFIG_RX65N_ETH_BUFSIZE OPTIMAL_ETH_BUFSIZE +#endif + +#if (CONFIG_RX65N_ETH_BUFSIZE & 31) != 0 +# error "CONFIG_RX65N_ETH_BUFSIZE must be aligned" +#endif + +#if CONFIG_RX65N_ETH_BUFSIZE != OPTIMAL_ETH_BUFSIZE +# warning "You using an incomplete/untested configuration" +#endif + +#ifndef CONFIG_RX65N_ETH_NRXDESC +# define CONFIG_RX65N_ETH_NRXDESC 16 +#endif +#ifndef CONFIG_RX65N_ETH_NTXDESC +# define CONFIG_RX65N_ETH_NTXDESC 12 +#endif + +/* We need at least one more free buffer than transmit buffers */ + +#define RX65N_ETH_NFREEBUFFERS (CONFIG_RX65N_ETH_NTXDESC+1) + +/* Extremely detailed register debug that you would normally never want + * enabled. + */ + +#ifndef CONFIG_DEBUG_NET +# undef CONFIG_RX65N_EMAC_REGDEBUG +#endif + +/* Helpers */ + +/* This is a helper pointer for accessing the contents of the Ethernet + * header + */ + +#define BUF ((struct eth_hdr_s *)priv->dev.d_buf) + +/* PHY return definitions */ + +#define R_PHY_OK (0) +#define R_PHY_ERROR (-1) + +#define ETHER_FLAG_OFF (0) + +/* PHY Mode Selection */ + +#define PHY_MII_SET_MODE (0) +#define PHY_RMII_SET_MODE (1) + +/* Pause frame disable/enable */ + +#define PAUSE_FRAME_DISABLE (0) +#define PAUSE_FRAME_ENABLE (1) + +/* Media Independent Interface */ + +#define PHY_MII_ST (1) +#define PHY_MII_READ (2) +#define PHY_MII_WRITE (1) + +/* Define the access timing of MII/RMII register */ + +#define ETHER_CFG_PHY_MII_WAIT (8) /* Plese define the value of 1 or more */ + +/* Define the waiting time for reset completion of PHY-LSI */ + +#define ETHER_CFG_PHY_DELAY_RESET (0x00020000L) +#define ETHER_PHY_STATUS_CHECK_DELAY (20000) + +/* Group AL1 interrupt priority level. + * This definition is not used when EINT interrupt + * is assigned to Peripheral + * interrupt. + */ + +#define ETHER_CFG_AL1_INT_PRIORTY (15) + +/* Use LINKSTA signal for detect link status changes + * 0 = unused (use PHY-LSI status register) + * 1 = use (use LINKSTA signal) + */ + +/* This setting is reflected in all channels */ + +#define ETHER_CFG_USE_LINKSTA (1) +#if defined(CONFIG_ARCH_RX65N_RSK2MB) + +#define ETHER_LINKUP (0) +#define ETHER_LINKDOWN (1) + +#elif defined(CONFIG_ARCH_RX65N_GRROSE) + +#define ETHER_LINKUP (1) +#define ETHER_LINKDOWN (0) + +#endif + +/* Standard PHY Registers */ + +#define PHY_REG_CONTROL (0) +#define PHY_REG_STATUS (1) +#define PHY_REG_IDENTIFIER1 (2) +#define PHY_REG_IDENTIFIER2 (3) +#define PHY_REG_AN_ADVERTISEMENT (4) +#define PHY_REG_AN_LINK_PARTNER (5) +#define PHY_REG_AN_EXPANSION (6) + +#if defined(CONFIG_ARCH_RX65N_RSK2MB) +#define PHY_STS_REG 0x10 +#define PHY_STS_REG_LINK (1 << 0) +#elif defined(CONFIG_ARCH_RX65N_GRROSE) +#define PHY_STS_REG 0x1f +#define PHY_STS_REG_AUTO_NEG (1 << 12) +#endif + +/* If we want to debug PHY register. Need to define these two macro + * #define PHY_READ_WRITE_TEST + * #define PHY_REG_DEBUGGING + */ + +#if defined(PHY_READ_WRITE_TEST) +#if defined(CONFIG_ARCH_RX65N_RSK2MB) + #define PHY_REG_IDENTIFIER1_DEF_VAL 0x2000 + #define PHY_REG_IDENTIFIER2_DEF_VAL 0x5ce1 +#elif defined(CONFIG_ARCH_RX65N_GRROSE) + #define PHY_REG_IDENTIFIER1_DEF_VAL 0x0007 + #define PHY_REG_IDENTIFIER2_DEF_VAL 0xc0f0 /* The The default value of LSB 4bit will vary dependent on the silicon revision number */ +#endif + #define PHY_REG_MII_INT_CONTROL 0x11 +#endif + +/* Phy Interrupt register */ + +#define PHY_REG_MICR (17) +#define PHY_REG_MISR (18) +#define PHY_MICR_TINT (1<<2) +#define PHY_MICR_INTEN (1<<1) +#define PHY_MICR_INT_OE (1<<0) +#define PHY_MISR_LINK_LQ_INT_EN (1<<7) +#define PHY_MISR_LINK_ED_INT_EN (1<<6) +#define PHY_MISR_LINK_INT_EN (1<<5) + +/* Basic Mode Control Register Bit Definitions */ + +#define PHY_CONTROL_RESET (1 << 15) +#define PHY_CONTROL_LOOPBACK (1 << 14) +#define PHY_CONTROL_100_MBPS (1 << 13) +#define PHY_CONTROL_AN_ENABLE (1 << 12) +#define PHY_CONTROL_POWER_DOWN (1 << 11) +#define PHY_CONTROL_ISOLATE (1 << 10) +#define PHY_CONTROL_AN_RESTART (1 << 9) +#define PHY_CONTROL_FULL_DUPLEX (1 << 8) +#define PHY_CONTROL_COLLISION (1 << 7) +#define PHY_VALID_LINK (1 << 2) +#define PHY_AUTO_NEG_DONE (1 << 5) + +/* Auto Negotiation Advertisement Bit Definitions */ + +#define PHY_AN_ADVERTISEMENT_NEXT_PAGE (1 << 15) +#define PHY_AN_ADVERTISEMENT_RM_FAULT (1 << 13) +#define PHY_AN_ADVERTISEMENT_ASM_DIR (1 << 11) +#define PHY_AN_ADVERTISEMENT_PAUSE (1 << 10) +#define PHY_AN_ADVERTISEMENT_100_T4 (1 << 9) +#define PHY_AN_ADVERTISEMENT_100F (1 << 8) +#define PHY_AN_ADVERTISEMENT_100H (1 << 7) +#define PHY_AN_ADVERTISEMENT_10F (1 << 6) +#define PHY_AN_ADVERTISEMENT_10H (1 << 5) +#define PHY_AN_ADVERTISEMENT_SELECTOR (1 << 0) + +/* Bit definitions of status member of DescriptorS */ + +#define TACT (0x80000000) +#define TDLE (0x40000000) +#define RACT (0x80000000) +#define RDLE (0x40000000) +#define TFP1 (0x20000000) +#define RFP1 (0x20000000) +#define TFP0 (0x10000000) +#define RFP0 (0x10000000) +#define TFE (0x08000000) +#define RFE (0x08000000) + +#define RFS9_RFOVER (0x00000200) +#define RFS8_RAD (0x00000100) +#define RFS7_RMAF (0x00000080) +#define RFS4_RRF (0x00000010) +#define RFS3_RTLF (0x00000008) +#define RFS2_RTSF (0x00000004) +#define RFS1_PRE (0x00000002) +#define RFS0_CERF (0x00000001) + +#define TWBI (0x04000000) +#define TFS8_TAD (0x00000100) +#define TFS3_CND (0x00000008) +#define TFS2_DLC (0x00000004) +#define TFS1_CD (0x00000002) +#define TFS0_TRO (0x00000001) + +/**************************************************************************** + * Public Types + ****************************************************************************/ + +/* Ethernet TX DMA Descriptor */ + +struct eth_txdesc_s +{ + /* Normal DMA descriptor words */ + + volatile uint32_t tdes0; /* Indicates transfer frame setting and the status after transmission */ + volatile uint32_t tdes1; /* Used to set the valid byte length of the transmit buffer */ + volatile uint32_t tdes2; /* Used to set the start address of transmit buffer */ + volatile uint32_t tdes3; /* next descriptor address pointer */ +}; + +/* Ethernet RX DMA Descriptor */ + +struct eth_rxdesc_s +{ + volatile uint32_t rdes0; /* Indicates receive frame status */ + + /* Indicates receive buffer length when reception is completed, + * the receive frame length is return back + */ + + volatile uint32_t rdes1; + volatile uint32_t rdes2; /* Indicates the start address of the receive buffer */ + volatile uint32_t rdes3; /* next descriptor address pointer */ +}; + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +/* The rx65n_ethmac_s encapsulates all state information for a single hardware + * interface + */ + +struct rx65n_ethmac_s +{ + /* Descriptor allocations */ + + struct eth_rxdesc_s rxtable[CONFIG_RX65N_ETH_NRXDESC]; + struct eth_txdesc_s txtable[CONFIG_RX65N_ETH_NTXDESC]; + + /* Buffer allocations */ + + uint8_t rxbuffer[CONFIG_RX65N_ETH_NRXDESC*CONFIG_RX65N_ETH_BUFSIZE]; + uint8_t alloc[RX65N_ETH_NFREEBUFFERS*CONFIG_RX65N_ETH_BUFSIZE]; + uint8_t ifup : 1; /* true:ifup false:ifdown */ + uint8_t mbps100 : 1; /* 100MBps operation (vs 10 MBps) */ + uint8_t fduplex : 1; /* Full (vs. half) duplex */ + struct work_s irqwork; /* For deferring interrupt work to the work queue */ + struct work_s pollwork; /* For deferring poll work to the work queue */ + + /* This holds the information visible to the NuttX network */ + + struct net_driver_s dev; /* Interface understood by the network */ + + /* Used to track transmit and receive descriptors */ + + struct eth_txdesc_s *txhead; /* Next available TX descriptor */ + struct eth_rxdesc_s *rxhead; /* Next available RX descriptor */ + + struct eth_txdesc_s *txtail; /* First "in_flight" TX descriptor */ + struct eth_rxdesc_s *rxcurr; /* First RX descriptor of the segment */ + uint16_t segments; /* RX segment count */ + uint16_t inflight; /* Number of TX transfers "in_flight" */ + sq_queue_t freeb; /* The free buffer list */ + + uint32_t prevlinkstatus; /* Previous link status to ignore multiple link change interrupt (specific to GR-Rose) */ +}; + +/**************************************************************************** + * Private Data + ****************************************************************************/ +#define NX_ALIGN32 __attribute__((aligned(32))) /* DMA descriptor buffer alignment to 32 bytes */ +NX_ALIGN32 static struct rx65n_ethmac_s g_rx65nethmac[RX65N_NETHERNET]; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/* Register operations */ + +#if defined(CONFIG_RX65N_EMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +static uint32_t rx65n_getreg(uint32_t addr); +static void rx65n_putreg(uint32_t val, uint32_t addr); +static void rx65n_checksetup(void); +#else +# define rx65n_getreg(addr) getreg32(addr) +# define rx65n_putreg(val,addr) putreg32(val,addr) +# define rx65n_checksetup() +#endif + +/* Debug */ + +/* Extra, in-depth debug output that is only available if + * CONFIG_NETDEV_PHY_DEBUG us defined. + */ + +#ifdef CONFIG_NETDEV_PHY_DEBUG +# define phyerr _err +# define phywarn _warn +# define phyinfo _info +#else +# define phyerr(x...) +# define phywarn(x...) +# define phyinfo(x...) +#endif + +/* Free buffer management */ + +static void rx65n_initbuffer(FAR struct rx65n_ethmac_s *priv); +static inline uint8_t *rx65n_allocbuffer(FAR struct rx65n_ethmac_s *priv); +static inline void rx65n_freebuffer(FAR struct rx65n_ethmac_s *priv, + uint8_t *buffer); +static inline bool rx65n_isfreebuffer(FAR struct rx65n_ethmac_s *priv); + +/* Common TX logic */ + +static int rx65n_transmit(FAR struct rx65n_ethmac_s *priv); +static int rx65n_txpoll(struct net_driver_s *dev); +static void rx65n_dopoll(FAR struct rx65n_ethmac_s *priv); + +/* Interrupt handling */ + +static void rx65n_enableint(FAR struct rx65n_ethmac_s *priv, + uint32_t ierbit); +static void rx65n_disableint(FAR struct rx65n_ethmac_s *priv, + uint32_t ierbit); + +static void rx65n_freesegment(FAR struct rx65n_ethmac_s *priv, + FAR struct eth_rxdesc_s *rxfirst, int segments); +static int rx65n_recvframe(FAR struct rx65n_ethmac_s *priv); +static void rx65n_receive(FAR struct rx65n_ethmac_s *priv); +static void rx65n_freeframe(FAR struct rx65n_ethmac_s *priv); +static void rx65n_txdone(FAR struct rx65n_ethmac_s *priv); + +static void rx65n_interrupt_work(FAR void *arg); +static int rx65n_interrupt(int irq, FAR void *context, FAR void *arg); + +/* Timer expirations */ + +static void rx65n_txtimeout_work(FAR void *arg); + +static void rx65n_poll_work(FAR void *arg); + +/* NuttX callback functions */ + +static int rx65n_ifup(struct net_driver_s *dev); +static int rx65n_ifdown(struct net_driver_s *dev); + +static void rx65n_txavail_work(FAR void *arg); +static int rx65n_txavail(struct net_driver_s *dev); + +#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6) +static int rx65n_addmac(struct net_driver_s *dev, FAR const uint8_t *mac); +#endif +#ifdef CONFIG_NET_MCASTGROUP +static int rx65n_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac); +#endif +#ifdef CONFIG_NETDEV_IOCTL +static int rx65n_ioctl(struct net_driver_s *dev, int cmd, + unsigned long arg); +#endif + +/* Descriptor Initialization */ + +static void rx65n_txdescinit(FAR struct rx65n_ethmac_s *priv); +static void rx65n_rxdescinit(FAR struct rx65n_ethmac_s *priv); + +/* PHY Initialization */ + +#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) +static void rx65n_phyintenable(bool enable); +#endif +#if defined(CONFIG_ARCH_PHY_INTERRUPT) +int arch_phy_irq(FAR const char *intf, xcpt_t handler, void *arg, + phy_enable_t *enable); +#endif +static int rx65n_phyinit(FAR struct rx65n_ethmac_s *priv); + +/* MAC/DMA Initialization */ + +static int rx65n_ethreset(FAR struct rx65n_ethmac_s *priv); +static int rx65n_macconfig(FAR struct rx65n_ethmac_s *priv); +static void rx65n_macaddress(FAR struct rx65n_ethmac_s *priv); +#ifdef CONFIG_NET_ICMPv6 +static void rx65n_ipv6multicast(FAR struct rx65n_ethmac_s *priv); +#endif +static int rx65n_ethconfig(FAR struct rx65n_ethmac_s *priv); + +static void rx65n_phy_preamble (void); +static void rx65n_phy_trans_zto0 (void); +static void rx65n_phy_trans_1to0 (void); +static void rx65n_phy_reg_set(uint8_t phydevaddr, uint16_t reg_addr, + int32_t option); +static void rx65n_phy_reg_write (uint16_t data); +static void rx65n_phy_mii_write1 (void); +static void rx65n_phy_mii_write0 (void); + +void rx65n_ether_enable_icu(void); +void rx65n_power_on_control (void); +void rx65n_ether_set_phy_mode(uint8_t mode); +void rx65n_ether_interrupt_init(void); + +static int rx65n_phywrite (uint8_t phydevaddr, uint16_t reg_addr, + uint16_t data); +static uint16_t rx65n_phyread (uint8_t phydevaddr, uint16_t reg_addr, + uint16_t *value); + +#if defined(PHY_READ_WRITE_TEST) +static int rx65n_phy_read_write_test(); +#endif +#if defined(PHY_REG_DEBUGGING) +static void rx65n_phy_reg_dump(); +#endif +void up_enable_irq(int irq); +void up_disable_irq(int irq); + +#if defined(CONFIG_ARCH_PHY_INTERRUPT) +struct phylinknotification_t +{ + xcpt_t phandler; + void *penable; + struct phy_notify_s *pclient; +}; + +struct phylinknotification_t phylinknotification; +phylinknotification_t phylinknotification = +{ + NULL, NULL, NULL +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rx65n_getreg + * + * Description: + * This function may to used to intercept an monitor all register accesses. + * Clearly this is nothing you would want to do unless you are debugging + * this driver. + * + * Input Parameters: + * addr - The register address to read + * + * Returned Value: + * The value read from the register + * + ****************************************************************************/ + +#ifdef CONFIG_RX65N_EMAC_REGDEBUG +static uint32_t rx65n_getreg(uint32_t addr) +{ + static uint32_t prevaddr = 0; + static uint32_t preval = 0; + static uint32_t count = 0; + + /* Read the value from the register */ + + uint32_t val = getreg32(addr); + + /* Is this the same value that we read from the same register last time? + * Are we polling the register? If so, suppress some of the output. + */ + + if (addr == prevaddr && val == preval) + { + if (count == 0xffffffff || ++count > 3) + { + if (count == 4) + { + ninfo("...\n"); + } + + return val; + } + } + + /* No this is a new address or value */ + + else + { + /* Did we print "..." for the previous value? */ + + if (count > 3) + { + /* Yes.. then show how many times the value repeated */ + + ninfo("[repeats %d more times]\n", count - 3); + } + + /* Save the new address, value, and count */ + + prevaddr = addr; + preval = val; + count = 1; + } + + /* Show the register value read */ + + ninfo("%08x->%08x\n", addr, val); + return val; +} +#endif + +/**************************************************************************** + * Name: rx65n_putreg + * + * Description: + * This function may to used to intercept an monitor all register accesses. + * Clearly this is nothing you would want to do unless you are debugging + * this driver. + * + * Input Parameters: + * val - The value to write to the register + * addr - The register address to read + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_RX65N_EMAC_REGDEBUG) && defined(CONFIG_DEBUG_FEATURES) +static void rx65n_putreg(uint32_t val, uint32_t addr) +{ + /* Show the register value being written */ + + ninfo("%08x<-%08x\n", addr, val); + + /* Write the value */ + + putreg32(val, addr); +} +#endif + +/**************************************************************************** + * Name: rx65n_checksetup + * + * Description: + * Show the state of critical configuration registers. + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_RX65N_EMAC_REGDEBUG +static void rx65n_checksetup(void) +{ +} +#endif + +/**************************************************************************** + * Function: rx65n_initbuffer + * + * Description: + * Initialize the free buffer list. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called during early driver initialization before Ethernet interrupts + * are enabled. + * + ****************************************************************************/ + +static void rx65n_initbuffer(FAR struct rx65n_ethmac_s *priv) +{ + uint8_t *buffer; + int i; + + /* Initialize the head of the free buffer list */ + + sq_init(&priv->freeb); + + /* Add all of the pre-allocated buffers to the free buffer list */ + + for (i = 0, buffer = priv->alloc; + i < RX65N_ETH_NFREEBUFFERS; + i++, buffer += CONFIG_RX65N_ETH_BUFSIZE) + { + sq_addlast((FAR sq_entry_t *)buffer, &priv->freeb); + } +} + +/**************************************************************************** + * Function: rx65n_allocbuffer + * + * Description: + * Allocate one buffer from the free buffer list. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * Pointer to the allocated buffer on success; NULL on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static inline uint8_t *rx65n_allocbuffer(FAR struct rx65n_ethmac_s *priv) +{ + /* Allocate a buffer by returning the head of the free buffer list */ + + return (uint8_t *)sq_remfirst(&priv->freeb); +} + +/**************************************************************************** + * Function: rx65n_freebuffer + * + * Description: + * Return a buffer to the free buffer list. + * + * Input Parameters: + * priv - Reference to the driver state structure + * buffer - A pointer to the buffer to be freed + * + * Returned Value: + * None + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static inline void rx65n_freebuffer(FAR struct rx65n_ethmac_s *priv, + uint8_t *buffer) +{ + /* Free the buffer by adding it to the end of the free buffer list */ + + sq_addlast((FAR sq_entry_t *)buffer, &priv->freeb); +} + +/**************************************************************************** + * Function: rx65n_isfreebuffer + * + * Description: + * Return TRUE if the free buffer list is not empty. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * True if there are one or more buffers in the free buffer list; + * false if the free buffer list is empty + * + * Assumptions: + * None. + * + ****************************************************************************/ + +static inline bool rx65n_isfreebuffer(FAR struct rx65n_ethmac_s *priv) +{ + /* Return TRUE if the free buffer list is not empty */ + + return !sq_empty(&priv->freeb); +} + +/**************************************************************************** + * Function: rx65n_transmit + * + * Description: + * Start hardware transmission. Called either from the txdone interrupt + * handling or from watchdog based polling. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ + +static int rx65n_transmit(FAR struct rx65n_ethmac_s *priv) +{ + struct eth_txdesc_s *txdesc; + struct eth_txdesc_s *txfirst; + + /* The internal (optimal) network buffer size may be configured to be larger + * than the Ethernet buffer size. + */ + +#if OPTIMAL_ETH_BUFSIZE > CONFIG_RX65N_ETH_BUFSIZE + uint8_t *buffer; + int bufcount; + int lastsize; + int i; +#endif + + /* Verify that the hardware is ready to send another packet. If we get + * here, then we are committed to sending a packet; Higher level logic + * must have assured that there is no transmission in progress. + */ + + txdesc = priv->txhead; + txfirst = txdesc; + + ninfo("d_len: %d d_buf: %p txhead: %p tdes0: %08x\n", + priv->dev.d_len, priv->dev.d_buf, txdesc, txdesc->tdes0); + + DEBUGASSERT(txdesc && (txdesc->tdes0 & TACT) == 0); + + /* Is the size to be sent greater than the size of the Ethernet buffer? */ + + DEBUGASSERT(priv->dev.d_len > 0 && priv->dev.d_buf != NULL); + + /* Increment statistics */ + +#if defined(CONFIG_NETDEV_STATISTICS) + (priv->dev.d_statistics.tx_packets)++; +#endif + +#if OPTIMAL_ETH_BUFSIZE > CONFIG_RX65N_ETH_BUFSIZE + if (priv->dev.d_len > CONFIG_RX65N_ETH_BUFSIZE) + { + /* Yes... how many buffers will be need to send the packet? */ + + bufcount = (priv->dev.d_len + + (CONFIG_RX65N_ETH_BUFSIZE - 1)) / CONFIG_RX65N_ETH_BUFSIZE; + lastsize = priv->dev.d_len - (bufcount - 1) * CONFIG_RX65N_ETH_BUFSIZE; + + ninfo("bufcount: %d lastsize: %d\n", bufcount, lastsize); + + /* Set the first segment bit in the first TX descriptor */ + + txdesc->tdes0 |= TFP1; + + /* Set up all but the last TX descriptor */ + + buffer = priv->dev.d_buf; + + for (i = 0; i < bufcount; i++) + { + /* This could be a normal event but the design does not handle it */ + + DEBUGASSERT((txdesc->tdes0 & TACT) == 0); + + /* Set the Buffer1 address pointer */ + + txdesc->tdes2 = (uint32_t)buffer; + + /* Set the buffer size in all TX descriptors */ + + if (i == (bufcount - 1)) + { + /* This is the last segment. Set the last segment bit in the + * last TX descriptor and ask for an interrupt when this + * segment transfer completes. + */ + + txdesc->tdes0 |= (TFP0 | TWBI); + + /* This segement is, most likely, of fractional buffersize */ + + txdesc->tdes1 = (lastsize << 16); + buffer += lastsize; + } + else + { + /* This is not the last segment. We don't want an interrupt + * when this segment transfer completes. + */ + + txdesc->tdes0 &= ~TWBI; + + /* The size of the transfer is the whole buffer */ + + txdesc->tdes1 = (CONFIG_RX65N_ETH_BUFSIZE << 16); + buffer += CONFIG_RX65N_ETH_BUFSIZE; + } + + /* Give the descriptor to DMA */ + + txdesc->tdes0 |= TACT; + rx65n_putreg(1, RX65N_ETHD_EDTRR); + + txdesc = (struct eth_txdesc_s *)txdesc->tdes3; + } + } + else +#endif + { + /* The single descriptor is both the first and last segment. And we do + * want an interrupt when the transfer completes. + */ + + txdesc->tdes0 |= (TFP0 | TFP1 | TWBI); + + /* Set frame size */ + + DEBUGASSERT(priv->dev.d_len <= CONFIG_NET_ETH_PKTSIZE); + txdesc->tdes1 = ((priv->dev.d_len) << 16); + + /* Set the Buffer1 address pointer */ + + txdesc->tdes2 = (uint32_t)priv->dev.d_buf; + + /* Set OWN bit of the TX descriptor tdes0. This gives the buffer to + * Ethernet DMA + */ + + txdesc->tdes0 |= TACT; + rx65n_putreg(1, RX65N_ETHD_EDTRR); + + /* Point to the next available TX descriptor */ + + txdesc = (struct eth_txdesc_s *)txdesc->tdes3; + } + + /* Remember where we left off in the TX descriptor chain */ + + priv->txhead = txdesc; + + /* Detach the buffer from priv->dev structure. That buffer is now + * "in-flight". + */ + + priv->dev.d_buf = NULL; + priv->dev.d_len = 0; + + /* If there is no other TX buffer, in flight, then remember the location + * of the TX descriptor. This is the location to check for TX done events. + */ + + if (!priv->txtail) + { + DEBUGASSERT(priv->inflight == 0); + priv->txtail = txfirst; + } + + /* Increment the number of TX transfer in-flight */ + + priv->inflight++; + + ninfo("txhead: %p txtail: %p inflight: %d\n", + priv->txhead, priv->txtail, priv->inflight); + + /* If all TX descriptors are in-flight, then we + * have to disable receive interrupts + * too. This is because receive events + * can trigger more un-stoppable transmit + * events. + */ + + if (priv->inflight >= CONFIG_RX65N_ETH_NTXDESC) + { + rx65n_disableint(priv, ETHD_EESIPR_FRIP); + } + + /* Enable TX interrupts */ + + rx65n_enableint(priv, ETHD_EESIPR_TCIP); + + /* Setup the TX timeout (perhaps restarting the timer) */ + + rx65n_cmtw0_start(rx65n_cmtw0_timeout, + RX65N_CMTW0_COUNT_VALUE_FOR_TXTIMEOUT); + return OK; +} + +/**************************************************************************** + * Function: rx65n_txpoll + * + * Description: + * The transmitter is available, check if the network + * has any outgoing packets ready + * to send. This is a callback from devif_poll(). + * devif_poll() may be called: + * + * 1. When the preceding TX packet send is complete, + * 2. When the preceding TX packet send timesout and the interface is reset + * 3. During normal TX polling + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * OK on success; a negated errno on failure + * + * Assumptions: + * May or may not be called from an interrupt handler. In either case, + * global interrupts are disabled, either explicitly or indirectly through + * interrupt handling logic. + * + ****************************************************************************/ +static int rx65n_txpoll(struct net_driver_s *dev) +{ + FAR struct rx65n_ethmac_s *priv = (FAR struct rx65n_ethmac_s *)dev-> + d_private; + + DEBUGASSERT(priv->dev.d_buf != NULL); + + /* If the polling resulted in data that should be sent out on the network, + * the field d_len is set to a value > 0. + */ + + if (priv->dev.d_len > 0) + { + /* Look up the destination MAC address and add it to the Ethernet + * header. + */ + +#ifdef CONFIG_NET_IPv4 +#ifdef CONFIG_NET_IPv6 + if (IFF_IS_IPv4(priv->dev.d_flags)) +#endif + { + arp_out(&priv->dev); + } +#endif /* CONFIG_NET_IPv4 */ + +#ifdef CONFIG_NET_IPv6 +#ifdef CONFIG_NET_IPv4 + else +#endif + { + neighbor_out(&priv->dev); + } +#endif /* CONFIG_NET_IPv6 */ + + if (!devif_loopback(&priv->dev)) + { + /* Send the packet */ + + rx65n_transmit(priv); + DEBUGASSERT(dev->d_len == 0 && dev->d_buf == NULL); + + /* Check if the next TX descriptor is owned by the + * Ethernet DMA or CPU. + * We cannot perform the TX poll if we are unable to accept + * another packet fo transmission. + * In a race condition, TACT may be cleared + * BUT still not available + * because rx65n_freeframe() has not yet run. + * If rx65n_freeframe() has run, + * the buffer1 pointer (tdes2) will be nullified + * (and inflight should + * be CONFIG_RX65N_ETH_NTXDESC). + */ + + if ((priv->txhead->tdes0 & TACT) != 0 || + priv->txhead->tdes2 != 0) + { + /* We have to terminate the poll if we have no more descriptors + * available for another transfer. + */ + + return -EBUSY; + } + + /* We have the descriptor, we can continue the poll. Allocate a new + * buffer for the poll. + */ + + dev->d_buf = rx65n_allocbuffer(priv); + + /* We can't continue the poll if we have no buffers */ + + if (dev->d_buf == NULL) + { + /* Terminate the poll. */ + + return -ENOMEM; + } + } + } + + /* If zero is returned, the polling will continue until all connections have + * been examined. + */ + + return 0; +} + +/**************************************************************************** + * Function: rx65n_dopoll + * + * Description: + * The function is called in order to perform an out-of-sequence TX poll. + * This is done: + * + * 1. After completion of a transmission (rx65n_txdone), + * 2. When new TX data is available (rx65n_txavail_process), and + * 3. After a TX timeout to restart the sending process + * (rx65n_txtimeout_process). + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by interrupt handling logic. + * + ****************************************************************************/ +static void rx65n_dopoll(FAR struct rx65n_ethmac_s *priv) +{ + FAR struct net_driver_s *dev = &priv->dev; + + /* Check if the next TX descriptor is owned by the Ethernet DMA or + * CPU. We cannot perform the TX poll if we are unable to accept + * another packet for transmission. + * + * In a race condition, TACT may be cleared BUT still not available + * because rx65n_freeframe() has not yet run. If rx65n_freeframe() has run, + * the buffer1 pointer (tdes2) will be nullified (and inflight should be < + * CONFIG_RX65N_ETH_NTXDESC). + */ + + if ((priv->txhead->tdes0 & TACT) == 0 && + priv->txhead->tdes2 == 0) + { + /* If we have the descriptor, then poll the network for new XMIT data. + * Allocate a buffer for the poll. + */ + + DEBUGASSERT(dev->d_len == 0 && dev->d_buf == NULL); + dev->d_buf = rx65n_allocbuffer(priv); + + /* We can't poll if we have no buffers */ + + if (dev->d_buf) + { + (void)devif_poll(dev, rx65n_txpoll); + + /* We will, most likely end up with a buffer to be freed. But it + * might not be the same one that we allocated above. + */ + + if (dev->d_buf) + { + DEBUGASSERT(dev->d_len == 0); + rx65n_freebuffer(priv, dev->d_buf); + dev->d_buf = NULL; + } + } + } +} + +/**************************************************************************** + * Function: rx65n_enableint + * + * Description: + * Enable interrupt + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + ****************************************************************************/ +static void rx65n_enableint(FAR struct rx65n_ethmac_s *priv, uint32_t ierbit) +{ + uint32_t regval; + + /* ETHERC/EDMAC enabling Status Interrupt */ + + regval = rx65n_getreg(RX65N_ETHD_EESIPR); + regval |= (ierbit); /* enabling ETHD_EESIPR_FRIP or ETHD_EESIPR_TCIP */ + + rx65n_putreg(regval, RX65N_ETHD_EESIPR); +} + +/**************************************************************************** + * Function: rx65n_disableint + * + * Description: + * Disable a normal interrupt. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + ****************************************************************************/ + +static void rx65n_disableint(FAR struct rx65n_ethmac_s *priv, uint32_t ierbit) +{ + uint32_t regval; + + /* ETHERC status interrupt request is disabled */ + + regval = rx65n_getreg(RX65N_ETHD_EESIPR); + regval &= (~(ierbit)); /* setting ETHD_EESIPR_FRIP or ETHD_EESIPR_TCIP */ + + rx65n_putreg(regval, RX65N_ETHD_EESIPR); +} + +/**************************************************************************** + * Function: rx65n_freesegment + * + * Description: + * The function is called when a frame is received using the DMA receive + * interrupt. It scans the RX descriptors to the received frame. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by interrupt handling logic. + * + ****************************************************************************/ + +static void rx65n_freesegment(FAR struct rx65n_ethmac_s *priv, + FAR struct eth_rxdesc_s *rxfirst, int segments) +{ + struct eth_rxdesc_s *rxdesc; + int i; + + ninfo("rxfirst: %p segments: %d\n", rxfirst, segments); + + /* Set RACT bit in RX descriptors. This gives the buffers back to EDMA */ + + rxdesc = rxfirst; + for (i = 0; i < segments; i++) + { + /* Check last descriptor */ + + if (rxdesc->rdes0 & RDLE) + { + rxdesc->rdes0 |= RACT; + } + else + { + rxdesc->rdes0 = RACT; + } + rxdesc = (struct eth_rxdesc_s *)rxdesc->rdes3; + } + + /* Resume transmission if stopped */ + + if (!(rx65n_getreg(RX65N_ETHD_EDRRR))) + { + rx65n_putreg(0x00000001, RX65N_ETHD_EDRRR); + } + + /* Reset the segment managment logic */ + + priv->rxcurr = NULL; + priv->segments = 0; +} + +/**************************************************************************** + * Function: rx65n_recvframe + * + * Description: + * The function is called when a frame is received using the DMA receive + * interrupt. It scans the RX descriptors of the received frame. + * + * NOTE: This function will silently discard any packets containing errors. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * OK if a packet was successfully returned; -EAGAIN if there are no + * further packets available + * + * Assumptions: + * Global interrupts are disabled by interrupt handling logic. + * + ****************************************************************************/ + +static int rx65n_recvframe(FAR struct rx65n_ethmac_s *priv) +{ + struct eth_rxdesc_s *rxdesc; + struct eth_rxdesc_s *rxcurr; + uint8_t *buffer; + int i; + + ninfo("rxhead: %p rxcurr: %p segments: %d\n", + priv->rxhead, priv->rxcurr, priv->segments); + + /* Check if there are free buffers. We cannot receive new frames in this + * design unless there is at least one free buffer. + */ + + if (!rx65n_isfreebuffer(priv)) + { + nerr("ERROR: No free buffers\n"); + return -ENOMEM; + } + + /* Scan descriptors owned by the CPU. Scan until: + * + * 1) We find a descriptor still owned by the DMA, + * 2) We have examined all of the RX descriptors, or + * 3) All of the TX descriptors are in flight. + * + * This last case is obscure. It is due to that fact that each packet + * that we receive can generate an unstoppable transmisson. So we have + * to stop receiving when we can not longer transmit. In this case, the + * transmit logic should also have disabled further RX interrupts. + */ + + rxdesc = priv->rxhead; + for (i = 0; + (rxdesc->rdes0 & RACT) == 0 && + i < CONFIG_RX65N_ETH_NRXDESC && + priv->inflight < CONFIG_RX65N_ETH_NTXDESC; + i++) + { + /* Check if this is the first segment in the frame */ + + if ((rxdesc->rdes0 & RFP1) != 0 && + (rxdesc->rdes0 & RFP0) == 0) + { + priv->rxcurr = rxdesc; + priv->segments = 1; + } + + /* Check if this is an intermediate segment in the frame */ + + else if (((rxdesc->rdes0 & RFP0) == 0) && + ((rxdesc->rdes0 & RFP1) == 0)) + { + priv->segments++; + } + + /* Otherwise, it is the last segment in the frame */ + + else + { + priv->segments++; + + /* Check if there is only one segment in the frame */ + + if (priv->segments == 1) + { + rxcurr = rxdesc; + } + else + { + rxcurr = priv->rxcurr; + } + + ninfo("rxhead: %p rxcurr: %p segments: %d\n", + priv->rxhead, priv->rxcurr, priv->segments); + + /* Check if any errors are reported in the frame */ + + if ((rxdesc->rdes0 & RFE) == 0) + { + struct net_driver_s *dev = &priv->dev; + + /* Get the Frame Length of the received packet: substruct 4 + * bytes of the CRC + */ + dev->d_len = ((rxdesc->rdes1 & 0x0000ffff)); + + /* Get a buffer from the free list. We don't even check if + * this is successful because we already assure the free + * list is not empty above. + */ + + buffer = rx65n_allocbuffer(priv); + + /* Take the buffer from the RX descriptor of the first free + * segment, put it into the network device structure, + * then replace the buffer in the RX descriptor with the + * newly allocated buffer. + */ + + DEBUGASSERT(dev->d_buf == NULL); + dev->d_buf = (uint8_t *)rxcurr->rdes2; + rxcurr->rdes2 = (uint32_t)buffer; + + /* Increment statistics */ + +#if defined(CONFIG_NETDEV_STATISTICS) + (priv->dev.d_statistics.rx_packets)++; +#endif + + /* Return success, remebering where we should re-start scanning + * and resetting the segment scanning logic + */ + + priv->rxhead = (struct eth_rxdesc_s *)rxdesc->rdes3; + rx65n_freesegment(priv, rxcurr, priv->segments); + + ninfo("rxhead: %p d_buf: %p d_len: %d\n", + priv->rxhead, dev->d_buf, dev->d_len); + + return OK; + } + else + { + /* Increment statistics */ + +#if defined(CONFIG_NETDEV_STATISTICS) + (priv->dev.d_statistics.rx_errors)++; +#endif + + /* Drop the frame that contains the errors, reset the segment + * scanning logic, and continue scanning with the next frame. + */ + + nerr("ERROR: Dropped, RX descriptor errors: %08x\n", + rxdesc->rdes0); + rx65n_freesegment(priv, rxcurr, priv->segments); + } + } + + /* Try the next descriptor */ + + rxdesc = (struct eth_rxdesc_s *)rxdesc->rdes3; + } + + /* We get here after all of the descriptors have been scanned or + * when rxdesc points + * to the first descriptor owned by the DMA. + * Remember where we left off. + */ + + priv->rxhead = rxdesc; + + ninfo("rxhead: %p rxcurr: %p segments: %d\n", + priv->rxhead, priv->rxcurr, priv->segments); + + return -EAGAIN; +} + +/**************************************************************************** + * Function: rx65n_receive + * + * Description: + * An interrupt was received indicating the availability of a new RX packet + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by interrupt handling logic. + * + ****************************************************************************/ + +static void rx65n_receive(FAR struct rx65n_ethmac_s *priv) +{ + struct net_driver_s *dev = &priv->dev; + + /* Loop while while rx65n_recvframe() successfully retrieves valid + * Ethernet frames. + */ + + while (rx65n_recvframe(priv) == OK) + { +#ifdef CONFIG_NET_PKT + + /* When packet sockets are enabled, feed the frame into the packet tap */ + + pkt_input(&priv->dev); +#endif + + /* Check if the packet is a valid size for the network + * buffer configuration (this should not happen) + */ + + if (dev->d_len > CONFIG_NET_ETH_PKTSIZE) + { + nerr("ERROR: Dropped, Too big: %d\n", dev->d_len); + + /* Free dropped packet buffer */ + + if (dev->d_buf) + { + rx65n_freebuffer(priv, dev->d_buf); + dev->d_buf = NULL; + dev->d_len = 0; + } + + continue; + } + + /* We only accept IP packets of the configured type and ARP packets */ + +#ifdef CONFIG_NET_IPv4 + if (BUF->type == HTONS(ETHTYPE_IP)) + { + ninfo("IPv4 frame\n"); + + /* Handle ARP on input then give the IPv4 packet to the network + * layer + */ + + /* Increment statistics */ + +#if defined(CONFIG_NETDEV_STATISTICS) + (priv->dev.d_statistics.rx_ipv4)++; +#endif + + arp_ipin(&priv->dev); + ipv4_input(&priv->dev); + + /* If the above function invocation resulted in data + * that should be + * sent out on the network, the field d_len will set + * to a value > 0. + */ + + if (priv->dev.d_len > 0) + { + /* Update the Ethernet header with the correct MAC address */ + +#ifdef CONFIG_NET_IPv6 + if (IFF_IS_IPv4(priv->dev.d_flags)) +#endif + { + arp_out(&priv->dev); + } +#ifdef CONFIG_NET_IPv6 + else + { + neighbor_out(&priv->dev); + } +#endif + + /* And send the packet */ + + rx65n_transmit(priv); + } + } + else +#endif +#ifdef CONFIG_NET_IPv6 + if (BUF->type == HTONS(ETHTYPE_IP6)) + { + ninfo("Iv6 frame\n"); + + /* Give the IPv6 packet to the network layer */ + + ipv6_input(&priv->dev); + + /* If the above function invocation resulted in data + * that should be sent out on the network, the field + * d_len will set to a value > 0. + */ + + if (priv->dev.d_len > 0) + { + /* Update the Ethernet header with the correct MAC address */ + +#ifdef CONFIG_NET_IPv4 + if (IFF_IS_IPv4(priv->dev.d_flags)) + { + arp_out(&priv->dev); + } + else +#endif +#ifdef CONFIG_NET_IPv6 + { + neighbor_out(&priv->dev); + } +#endif + + /* And send the packet */ + + rx65n_transmit(priv); + } + } + else +#endif +#ifdef CONFIG_NET_ARP + if (BUF->type == htons(ETHTYPE_ARP)) + { + ninfo("ARP frame\n"); + + /* Increment statistics */ + +#if defined(CONFIG_NETDEV_STATISTICS) + (priv->dev.d_statistics.rx_arp)++; +#endif + + /* Handle ARP packet */ + + arp_arpin(&priv->dev); + + /* If the above function invocation resulted in data + * that should be sent out on the network, the field + * d_len will set to a value > 0. + */ + + if (priv->dev.d_len > 0) + { + rx65n_transmit(priv); + } + } + else +#endif + { + nerr("ERROR: Dropped, Unknown type: %04x\n", BUF->type); +#if defined(CONFIG_NETDEV_STATISTICS) + (priv->dev.d_statistics.rx_dropped)++; +#endif + } + + /* We are finished with the RX buffer. NOTE: If the buffer is + * re-used for transmission, the dev->d_buf field will have been + * nullified. + */ + + if (dev->d_buf) + { + /* Free the receive packet buffer */ + + rx65n_freebuffer(priv, dev->d_buf); + dev->d_buf = NULL; + dev->d_len = 0; + } + } +} + +/**************************************************************************** + * Function: rx65n_freeframe + * + * Description: + * Scans the TX descriptors and frees the buffers of completed TX transfers. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None. + * + * Assumptions: + * Global interrupts are disabled by interrupt handling logic. + * + ****************************************************************************/ + +static void rx65n_freeframe(FAR struct rx65n_ethmac_s *priv) +{ + struct eth_txdesc_s *txdesc; + int i; + + ninfo("txhead: %p txtail: %p inflight: %d\n", + priv->txhead, priv->txtail, priv->inflight); + + /* Scan for "in-flight" descriptors owned by the CPU */ + + txdesc = priv->txtail; + if (txdesc) + { + DEBUGASSERT(priv->inflight > 0); + + for (i = 0; (txdesc->tdes0 & TACT) == 0; i++) + { + /* There should be a buffer assigned to all in-flight + * TX descriptors. + */ + + ninfo("txtail: %p tdes0: %08x tdes2: %08x tdes3: %08x\n", + txdesc, txdesc->tdes0, txdesc->tdes2, txdesc->tdes3); + + DEBUGASSERT(txdesc->tdes2 != 0); + + /* Check if this is the first segment of a TX frame. */ + + if ((txdesc->tdes0 & TFP1) != 0) + { + /* Yes.. Free the buffer */ + + rx65n_freebuffer(priv, (uint8_t *)txdesc->tdes2); + } + + /* In any event, make sure that TDES2 is nullified. */ + + txdesc->tdes2 = 0; + + /* Check if this is the last segement of a TX frame */ + + if ((txdesc->tdes0 & TFP0) != 0) + { + /* Yes.. Decrement the number of frames "in-flight". */ + + priv->inflight--; + + /* If all of the TX descriptors were in-flight, + * then RX interrupts may have been disabled... we + * can re-enable them now. + */ + + /* Need to check this and update the arguments of the + * rx65n_enableint function + */ + + rx65n_enableint(priv, ETHD_EESIPR_FRIP); + + /* If there are no more frames in-flight, then bail. */ + + if (priv->inflight <= 0) + { + priv->txtail = NULL; + priv->inflight = 0; + return; + } + } + + /* Try the next descriptor in the TX chain */ + + txdesc = (struct eth_txdesc_s *)txdesc->tdes3; + } + + /* We get here if (1) there are still frames "in-flight". Remember + * where we left off. + */ + + priv->txtail = txdesc; + + ninfo("txhead: %p txtail: %p inflight: %d\n", + priv->txhead, priv->txtail, priv->inflight); + } +} + +/**************************************************************************** + * Function: rx65n_txdone + * + * Description: + * An interrupt was received indicating that the last TX packet + * transfer(s) are complete. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * + ****************************************************************************/ +static void rx65n_txdone(FAR struct rx65n_ethmac_s *priv) +{ + DEBUGASSERT(priv->txtail != NULL); + + /* Scan the TX descriptor change, returning buffers to free list */ + + rx65n_freeframe(priv); + + /* If no further xmits are pending, then cancel the TX timeout */ + + if (priv->inflight <= 0) + { + /* Cancel the TX timeout */ + + rx65n_cmtw0_stop(rx65n_cmtw0_timeout); + + /* And disable further TX interrupts. */ + + rx65n_disableint(priv, ETHD_EESIPR_TCIP); + } + + /* Then poll the network for new XMIT data */ + + rx65n_dopoll(priv); +} + +/**************************************************************************** + * Function: rx65n_interrupt_work + * + * Description: + * Perform interrupt related work from the worker thread + * + * Input Parameters: + * arg - The argument passed when work_queue() was called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * Ethernet interrupts are disabled + * + ****************************************************************************/ +static void rx65n_interrupt_work(FAR void *arg) +{ + FAR struct rx65n_ethmac_s *priv = (FAR struct rx65n_ethmac_s *)arg; + uint32_t edmasr; + uint32_t regval; + + uint32_t ethsr; +#if defined(CONFIG_ARCH_PHY_INTERRUPT) + uint16_t phyreg; + int phyreg_read_status; +#endif + DEBUGASSERT(priv); + + /* Process pending Ethernet interrupts */ + + net_lock(); + + /* Check and clear the Link Signal Change Flag */ + + ethsr = rx65n_getreg(RX65N_ETH_ECSR); + ethsr &= rx65n_getreg(RX65N_ETH_ECSIPR); + if ((ethsr & ETH_ECSR_LCHNG) != 0) + { + regval = rx65n_getreg(RX65N_ETH_ECSR); + regval |= ((ETH_ECSR_LCHNG)); /* Write 1 to clear flag */ + rx65n_putreg(regval, RX65N_ETH_ECSR); + +#if defined(CONFIG_ARCH_PHY_INTERRUPT) +#if defined(CONFIG_ARCH_BOARD_RX65N_GRROSE) + phyreg_read_status = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_REG_STATUS, &phyreg); + regval = (uint32_t)(phyreg & 0x04) >> 2; +#elif defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB) + phyreg_read_status = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_STS_REG, &phyreg); + regval = (uint32_t)(phyreg & 0x01); +#endif + if (regval != priv->prevlinkstatus) /* Check link status by 0th bit */ + { + /* Link UP or DOWN status */ + + if (phylinknotification.phandler != NULL) + { + phylinknotification.phandler(NULL, (FAR void *)NULL, + (FAR void *)phylinknotification.pclient); + priv->prevlinkstatus = regval; + } + } +#endif + } + + /* Get the interrupt status bits (ETHERC/EDMAC interrupt status check ) */ + + edmasr = rx65n_getreg(RX65N_ETHD_EESR); + + /* Mask only enabled interrupts. This depends on the + * fact that the interrupt + * related bits (0-16) correspond in these two registers. + */ + + edmasr &= rx65n_getreg(RX65N_ETHD_EESIPR); + + /* Yes.. Check if we received an incoming packet, + * if so, call + * rx65n_receive() + */ + + if ((edmasr & ETHD_EESR_FR) != 0) + { + /* Clear the pending receive interrupt */ + + rx65n_putreg(ETHD_EESR_FR, RX65N_ETHD_EESR); + + /* Handle the received package */ + + rx65n_receive(priv); + } + + /* Check if a packet transmission just completed. + * If so, call rx65n_txdone(). This may disable further + * TX interrupts if there are no pending transmissions. + */ + + if ((edmasr & ETHD_EESR_TC) != 0) + { + /* Clear the pending transmit interrupt */ + + rx65n_putreg(ETHD_EESR_TC, RX65N_ETHD_EESR); + + /* Increment statistics */ + +#if defined(CONFIG_NETDEV_STATISTICS) + (priv->dev.d_statistics.tx_done)++; +#endif + + /* Check if there are pending transmissions */ + + rx65n_txdone(priv); + } + + net_unlock(); + + /* Re-enable Ethernet interrupts */ + + up_enable_irq(RX65N_ETH_IRQ); +} + +/**************************************************************************** + * Function: rx65n_interrupt + * + * Description: + * Hardware interrupt handler + * + * Input Parameters: + * irq - Number of the IRQ that generated the interrupt + * context - Interrupt register state save info (architecture-specific) + * + * Returned Value: + * OK on success + * + * Assumptions: + * + ****************************************************************************/ + +static int rx65n_interrupt(int irq, FAR void *context, FAR void *arg) +{ + FAR struct rx65n_ethmac_s *priv = &g_rx65nethmac[0]; + uint32_t edmasr; + + /* Get the interrupt status bits (ETHERC/EDMAC interrupt status check ) */ + + edmasr = rx65n_getreg(RX65N_ETHD_EESR); + if (edmasr != 0) + { + /* Disable further Ethernet interrupts. Because Ethernet interrupts + * are also disabled if the TX timeout event occurs, there can be no + * race condition here. + */ + + up_disable_irq(RX65N_ETH_IRQ); + + /* Check if a packet transmission just completed. */ + + if ((edmasr & ETHD_EESR_TC) != 0) + { + /* If a TX transfer just completed, then cancel the TX timeout so + * there will be no race condition between any subsequent timeout + * expiration and the deferred interrupt processing. + */ + + rx65n_cmtw0_stop(rx65n_cmtw0_timeout); + } + + /* Schedule to perform the interrupt processing on the worker thread. */ + + work_queue(ETHWORK, &priv->irqwork, rx65n_interrupt_work, priv, 0); + } + + return OK; +} + +/**************************************************************************** + * Function: rx65n_txtimeout_work + * + * Description: + * Perform TX timeout related work from the worker thread + * + * Input Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * Ethernet interrupts are disabled + * + ****************************************************************************/ + +static void rx65n_txtimeout_work(FAR void *arg) +{ + FAR struct rx65n_ethmac_s *priv = (FAR struct rx65n_ethmac_s *)arg; + + /* Reset the hardware.Just take the interface down, then back up again. */ + + net_lock(); + + /* Increment statistics */ + +#if defined(CONFIG_NETDEV_STATISTICS) + (priv->dev.d_statistics.tx_errors)++; + (priv->dev.d_statistics.tx_timeouts)++; +#endif + + (void)rx65n_ifdown(&priv->dev); + (void)rx65n_ifup(&priv->dev); + + /* Then poll for new XMIT data */ + + rx65n_dopoll(priv); + net_unlock(); +} + +/**************************************************************************** + * Function: rx65n_txtimeout_expiry + * + * Description: + * Our TX watchdog timed out. Called from the timer interrupt handler. + * The last TX never completed. Reset the hardware and start again. + * + * Input Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * + ****************************************************************************/ + +void rx65n_txtimeout_expiry(int argc, uint32_t arg, ...) +{ + FAR struct rx65n_ethmac_s *priv = (FAR struct rx65n_ethmac_s *)arg; + nerr("ERROR: Timeout!\n"); + + /* Disable further Ethernet interrupts. This will prevent some race + * conditions with interrupt work. There is still a potential race + * condition with interrupt work that is already queued and in progress. + * + * Interrupts will be re-enabled when rx65n_ifup() is called. + */ + + up_disable_irq(RX65N_ETH_IRQ); + + /* Schedule to perform the TX timeout processing on the worker thread, + * perhaps canceling any pending IRQ processing. + */ + + work_queue(ETHWORK, &priv->irqwork, rx65n_txtimeout_work, priv, 0); +} + +/**************************************************************************** + * Function: rx65n_poll_work + * + * Description: + * Perform periodic polling from the worker thread + * + * Input Parameters: + * arg - The argument passed when work_queue() as called. + * + * Returned Value: + * OK on success + * + * Assumptions: + * Ethernet interrupts are disabled + * + ****************************************************************************/ + +static void rx65n_poll_work(FAR void *arg) +{ + FAR struct rx65n_ethmac_s *priv = (FAR struct rx65n_ethmac_s *)arg; + FAR struct net_driver_s *dev = &priv->dev; + + /* Check if the next TX descriptor is owned by the Ethernet DMA or CPU. We + * cannot perform the timer poll if we are unable to accept another packet + * for transmission. Hmmm.. might be bug here. Does this mean if there is + * a transmit in progress, we will miss TCP time state updates? + * + * In a race condition, TACT may be cleared BUT still not available + * because rx65n_freeframe() has not yet run. If rx65n_freeframe() has run, + * the buffer1 pointer (tdes2) will be nullified (and inflight should be < + * CONFIG_RX65N_ETH_NTXDESC). + */ + + net_lock(); + if ((priv->txhead->tdes0 & TACT) == 0 && + priv->txhead->tdes2 == 0) + { + /* If we have the descriptor, then perform the timer poll. Allocate a + * buffer for the poll. + */ + + DEBUGASSERT(dev->d_len == 0 && dev->d_buf == NULL); + dev->d_buf = rx65n_allocbuffer(priv); + + /* We can't poll if we have no buffers */ + + if (dev->d_buf) + { + /* Update TCP timing states and poll the network for new XMIT data. + */ + + (void)devif_timer(dev, rx65n_txpoll); + + /* We will, most likely end up with a buffer to be freed. But it + * might not be the same one that we allocated above. + */ + + if (dev->d_buf) + { + DEBUGASSERT(dev->d_len == 0); + rx65n_freebuffer(priv, dev->d_buf); + dev->d_buf = NULL; + } + } + } + + /* Setup the poll timer again */ + + rx65n_cmtw0_start(rx65n_cmtw0_txpoll, RX65N_CMTW0_COUNT_VALUE_FOR_TXPOLL); + + net_unlock(); +} + +/**************************************************************************** + * Function: rx65n_poll_expiry + * + * Description: + * Periodic timer handler. Called from the timer interrupt handler. + * + * Input Parameters: + * argc - The number of available arguments + * arg - The first argument + * + * Returned Value: + * None + * + * Assumptions: + * Global interrupts are disabled by the watchdog logic. + * + ****************************************************************************/ + +void rx65n_poll_expiry(int argc, uint32_t arg, ...) +{ + FAR struct rx65n_ethmac_s *priv = (FAR struct rx65n_ethmac_s *)arg; + rx65n_cmtw0_stop(rx65n_cmtw0_txpoll); + if (work_available(&priv->pollwork)) + { + /* Schedule to perform the interrupt processing + * on the worker thread. + */ + + work_queue(ETHWORK, &priv->pollwork, rx65n_poll_work, priv, 0); + } + else + { + rx65n_cmtw0_start(rx65n_cmtw0_txpoll, + RX65N_CMTW0_COUNT_VALUE_FOR_TXPOLL); + } +} + +/**************************************************************************** + * Function: rx65n_ifup + * + * Description: + * NuttX Callback: Bring up the Ethernet interface when an IP address is + * provided + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * Zero is returned on success; a negated errno value is returned on any + * failure. + * + * Assumptions: + * + ****************************************************************************/ + +static int rx65n_ifup(struct net_driver_s *dev) +{ + FAR struct rx65n_ethmac_s *priv = (FAR struct rx65n_ethmac_s *)dev-> + d_private; + int ret; + +#ifdef CONFIG_NET_IPv4 + ninfo("Bringing up: %d.%d.%d.%d\n", + dev->d_ipaddr & 0xff, (dev->d_ipaddr >> 8) & 0xff, + (dev->d_ipaddr >> 16) & 0xff, dev->d_ipaddr >> 24); +#endif +#ifdef CONFIG_NET_IPv6 + ninfo("Bringing up: %04x:%04x:%04x:%04x:%04x:%04x:%04x:%04x\n", + dev->d_ipv6addr[0], dev->d_ipv6addr[1], dev->d_ipv6addr[2], + dev->d_ipv6addr[3], dev->d_ipv6addr[4], dev->d_ipv6addr[5], + dev->d_ipv6addr[6], dev->d_ipv6addr[7]); +#endif + + /* Configure the Ethernet interface for DMA operation. */ + + ret = rx65n_ethconfig(priv); + if (ret < 0) + { + return ret; + } + + /* Set and activate a timer process */ + + rx65n_cmtw0_start(rx65n_cmtw0_txpoll, RX65N_CMTW0_COUNT_VALUE_FOR_TXPOLL); + priv->ifup = true; + + /* Enable the Ethernet interrupt */ + + up_enable_irq(RX65N_ETH_IRQ); + + rx65n_checksetup(); + return OK; +} + +/**************************************************************************** + * Function: rx65n_ifdown + * + * Description: + * NuttX Callback: Stop the interface. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * Returns zero on success; a negated errno value is returned on any + * failure. + * + * Assumptions: + * + ****************************************************************************/ + +static int rx65n_ifdown(struct net_driver_s *dev) +{ + FAR struct rx65n_ethmac_s *priv = (FAR struct rx65n_ethmac_s *)dev-> + d_private; + irqstate_t flags; + int ret = OK; + ninfo("Taking the network down\n"); + flags = enter_critical_section(); + + /* Disable the Ethernet interrupt */ + + up_disable_irq(RX65N_ETH_IRQ); + + /* Cancel the TX poll timer and TX timeout timers */ + + rx65n_cmtw0_stop(rx65n_cmtw0_txpoll); + rx65n_cmtw0_stop(rx65n_cmtw0_timeout); + + /* Put the EMAC in its reset, non-operational state. + * This should be a known configuration that will guarantee + * the rx65n_ifup() alwayssuccessfully brings the interface back up. + */ + + ret = rx65n_ethreset(priv); + if (ret < 0) + { + nerr("ERROR: rx65n_ethreset failed (timeout), " + "still assuming it's going down.\n"); + } + + /* Mark the device "down" */ + + priv->ifup = false; + leave_critical_section(flags); + return ret; +} + +/**************************************************************************** + * Function: rx65n_txavail_work + * + * Description: + * Perform an out-of-cycle poll on the worker thread. + * + * Input Parameters: + * arg - Reference to the NuttX driver state structure (cast to void*) + * + * Returned Value: + * None + * + * Assumptions: + * Called on the higher priority worker thread. + * + ****************************************************************************/ + +static void rx65n_txavail_work(FAR void *arg) +{ + FAR struct rx65n_ethmac_s *priv = (FAR struct rx65n_ethmac_s *)arg; + + ninfo("ifup: %d\n", priv->ifup); + + /* Ignore the notification if the interface is not yet up */ + + net_lock(); + if (priv->ifup) + { + /* Poll the network for new XMIT data */ + + rx65n_dopoll(priv); + } + + net_unlock(); +} + +/**************************************************************************** + * Function: rx65n_txavail + * + * Description: + * Driver callback invoked when new TX data is available. This is a + * stimulus perform an out-of-cycle poll and, thereby, reduce the TX + * latency. + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * Called in normal user mode + * + ****************************************************************************/ + +static int rx65n_txavail(struct net_driver_s *dev) +{ + FAR struct rx65n_ethmac_s *priv = (FAR struct rx65n_ethmac_s *)dev-> + d_private; + + /* Is our single work structure available? + * It may not be if there are + * pending interrupt actions and we will have to ignore the Tx + * availability action. + */ + + if (work_available(&priv->pollwork)) + { + /* Schedule to serialize the poll on the worker thread. */ + + work_queue(ETHWORK, &priv->pollwork, rx65n_txavail_work, priv, 0); + } + + return OK; +} + +/**************************************************************************** + * Function: rx65n_calcethcrc + * + * Description: + * Function to calculate the CRC used by RX65N to check an ethernet frame + * + * Input Parameters: + * data - the data to be checked + * length - length of the data + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6) +/* Currently Not supportted, Need to update this code when support added */ + +static uint32_t rx65n_calcethcrc(const uint8_t *data, size_t length) +{ + uint32_t crc = 0xffffffff; + + /* Currently not implemented */ + + return ~crc; +} +#endif + +/**************************************************************************** + * Function: rx65n_addmac + * + * Description: + * NuttX Callback: Add the specified MAC address to the hardware multicast + * address filtering + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be added + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ +#if defined(CONFIG_NET_MCASTGROUP) || defined(CONFIG_NET_ICMPv6) +/* Currently Not supported, Need to update this code when support added */ + +static int rx65n_addmac(struct net_driver_s *dev, FAR const uint8_t *mac) +{ + /* Currnently not implemented */ + + return OK; +} +#endif /* CONFIG_NET_MCASTGROUP || CONFIG_NET_ICMPv6 */ + +/**************************************************************************** + * Function: rx65n_rmmac + * + * Description: + * NuttX Callback: Remove the specified MAC address from the + * hardware multicast + * address filtering + * + * Input Parameters: + * dev - Reference to the NuttX driver state structure + * mac - The MAC address to be removed + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +/* Currently Not supportted, Need to update this code when support added */ + +#ifdef CONFIG_NET_MCASTGROUP +static int rx65n_rmmac(struct net_driver_s *dev, FAR const uint8_t *mac) +{ + /* Currnently not implemented */ + + return OK; +} +#endif + +/**************************************************************************** + * Function: rx65n_txdescinit + * + * Description: + * Initializes the DMA TX descriptors in chain mode. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void rx65n_txdescinit(FAR struct rx65n_ethmac_s *priv) +{ + struct eth_txdesc_s *txdesc; + int i; + + /* priv->txhead will point to the first, available TX descriptor in + * the chain. + * Set the priv->txhead pointer to the first descriptor in the table. + */ + + priv->txhead = priv->txtable; + + /* priv->txtail will point to the first segment + * of the oldest pending "in-flight" TX transfer. + * NULL means that there are no active TX transfers. + */ + + priv->txtail = NULL; + priv->inflight = 0; + + /* Initialize each TX descriptor */ + + for (i = 0; i < CONFIG_RX65N_ETH_NTXDESC; i++) + { + txdesc = &priv->txtable[i]; + + /* Set Second Address Chained bit */ + + txdesc->tdes0 = 0x00000000; /* All bits are cleared initially */ + + /* Clear Buffer1 address pointer + * (buffers will be assigned as they are used) + */ + + txdesc->tdes1 = (uint32_t)(1 << 16); + txdesc->tdes2 = 0; + + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ + + if (i < (CONFIG_RX65N_ETH_NTXDESC - 1)) + { + /* Set next descriptor address register with + * next descriptor base address + */ + + txdesc->tdes3 = (uint32_t)&priv->txtable[i + 1]; + } + else + { + /* For last descriptor, set next descriptor + * address register equal to the first descriptor base address + */ + + txdesc->tdes0 = TDLE; /* When this bit is 1, it indicates that this descriptor is the last descriptor of the descriptor list. */ + + txdesc->tdes3 = (uint32_t)priv->txtable; + } + } + + /* Set Transmit Desciptor List Address Register */ + + rx65n_putreg((uint32_t)priv->txtable, RX65N_ETHD_TDLAR); +} + +/**************************************************************************** + * Function: rx65n_rxdescinit + * + * Description: + * Initializes the DMA RX descriptors in chain mode. + * + * Input Parameters: + * priv - Reference to the driver state structure + * + * Returned Value: + * None + * + * Assumptions: + * + ****************************************************************************/ + +static void rx65n_rxdescinit(FAR struct rx65n_ethmac_s *priv) +{ + struct eth_rxdesc_s *rxdesc; + int i; + + /* priv->rxhead will point to the first, + * RX descriptor in the chain. + * This will be where we receive the first incomplete frame. + */ + + priv->rxhead = priv->rxtable; + + /* If we accumulate the frame in segments, priv->rxcurr points to the + * RX descriptor of the first segment in the current TX frame. + */ + + priv->rxcurr = NULL; + priv->segments = 0; + + /* Initialize each RX descriptor */ + + for (i = 0; i < CONFIG_RX65N_ETH_NRXDESC; i++) + { + rxdesc = &priv->rxtable[i]; + + /* Set Own bit of the RX descriptor rdes0 */ + + rxdesc->rdes0 = RACT; /* Indicates that Descriptor is valid */ + + /* Set Buffer1 size RX desc receive interrupt */ + + rxdesc->rdes1 = (uint32_t)(CONFIG_RX65N_ETH_BUFSIZE << 16); + + /* Set Buffer1 address pointer */ + + rxdesc->rdes2 = (uint32_t)&priv->rxbuffer[i*CONFIG_RX65N_ETH_BUFSIZE]; + + /* Initialize the next descriptor with the Next Descriptor Polling Enable */ + + if (i < (CONFIG_RX65N_ETH_NRXDESC - 1)) + { + /* Set next descriptor address register with next descriptor base + * address + */ + + rxdesc->rdes3 = (uint32_t)&priv->rxtable[i + 1]; + } + else + { + /* For last descriptor, set next descriptor address register equal + * to the first descriptor base address + */ + + rxdesc->rdes0 |= RDLE; /* Indicates that Descriptor is last descriptor valid */ + + rxdesc->rdes3 = (uint32_t)priv->rxtable; + } + } + + /* Set Receive Descriptor List Address Register */ + + rx65n_putreg((uint32_t)priv->rxtable, RX65N_ETHD_RDLAR); +} + +/**************************************************************************** + * Function: rx65n_ioctl + * + * Description: + * Executes the SIOCxMIIxxx command and responds using the request struct + * that must be provided as its 2nd parameter. + * + * When called with SIOCGMIIPHY it will get the PHY address for the device + * and write it to the req->phy_id field of the request struct. + * + * When called with SIOCGMIIREG it will read a register of the PHY that is + * specified using the req->reg_no struct field and then write its output + * to the req->val_out field. + * + * When called with SIOCSMIIREG it will write to a register of the PHY that + * is specified using the req->reg_no struct field and use req->val_in as + * its input. + * + * Input Parameters: + * dev - Ethernet device structure + * cmd - SIOCxMIIxxx command code + * arg - Request structure also used to return values + * + * Returned Value: Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +#ifdef CONFIG_NETDEV_IOCTL +static int rx65n_ioctl(struct net_driver_s *dev, int cmd, unsigned long arg) +{ +#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) + FAR struct rx65n_ethmac_s *priv = + (FAR struct rx65n_ethmac_s *)dev->d_private; +#endif + int ret; + + switch (cmd) + { +#ifdef CONFIG_NETDEV_PHY_IOCTL +#ifdef CONFIG_ARCH_PHY_INTERRUPT + case SIOCMIINOTIFY: /* Set up for PHY event notifications */ + { + struct mii_ioctl_notify_s *req = + (struct mii_ioctl_notify_s *)((uintptr_t)arg); + + ret = phy_notify_subscribe(dev->d_ifname, req->pid, &req->event); + if (ret == OK) + { + /* Enable PHY link up/down interrupts */ + + rx65n_phyintenable(true); + } + } + break; +#endif + + case SIOCGMIIPHY: /* Get MII PHY address */ + { + struct mii_ioctl_data_s *req = + (struct mii_ioctl_data_s *)((uintptr_t)arg); + req->phy_id = CONFIG_RX65N_EMAC0_PHYADDR; + ret = OK; + } + break; + + case SIOCGMIIREG: /* Get register from MII PHY */ + { + struct mii_ioctl_data_s *req = + (struct mii_ioctl_data_s *)((uintptr_t)arg); + ret = rx65n_phyread(req->phy_id, req->reg_num, &req->val_out); + } + break; + + case SIOCSMIIREG: /* Set register in MII PHY */ + { + struct mii_ioctl_data_s *req = + (struct mii_ioctl_data_s *)((uintptr_t)arg); + ret = rx65n_phywrite(req->phy_id, req->reg_num, req->val_in); + } + break; +#endif /* CONFIG_NETDEV_PHY_IOCTL */ + + default: + ret = -ENOTTY; + break; + } + return ret; +} +#endif /* CONFIG_NETDEV_IOCTL */ + +/**************************************************************************** + * Function: rx65n_phyintenable + * + * Description: + * Enable link up/down PHY interrupts. The interrupt protocol is like this: + * + * - Interrupt status is cleared when the interrupt is enabled. + * - Interrupt occurs. Interrupt is disabled (at the processor level) when + * is received. + * - Interrupt status is cleared when the interrupt is re-enabled. + * + * Input Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * None + * + ****************************************************************************/ + +#if defined(CONFIG_NETDEV_PHY_IOCTL) && defined(CONFIG_ARCH_PHY_INTERRUPT) +static void rx65n_phyintenable(bool enable) +{ + uint32_t regval; + regval = rx65n_getreg(RX65N_ETH_ECSR); + regval |= ((ETH_ECSR_LCHNG)); /* Write 1 to clear flag */ + rx65n_putreg(regval, RX65N_ETH_ECSR); + + if (enable) + { + } + else + { + } +} +#endif + +/**************************************************************************** + * Name: arch_phy_irq + * + * Description: + * This function may be called to register an interrupt handler that will + * be called when a PHY interrupt occurs. This function both attaches + * the interrupt handler and enables the interrupt if 'handler' is non- + * NULL. If handler is NULL, then the interrupt is detached and disabled + * instead. + * + * The PHY interrupt is always disabled upon return. The caller must + * call back through the enable function point to control the state of + * the interrupt. + * + * This interrupt may or may not be available on a given platform depending + * on how the network hardware architecture is implemented. In a typical + * case, the PHY interrupt is provided to board-level logic as a GPIO + * interrupt (in which case this is a board-specific interface and really + * should be called board_phy_irq()); In other cases, the PHY interrupt + * may be cause by the chip's MAC logic (in which case arch_phy_irq()) is + * an appropriate name. Other other boards, there may be no PHY interrupts + * available at all. If client attachable PHY interrupts are available + * from the board or from the chip, then CONFIG_ARCH_PHY_INTERRUPT should + * be defined to indicate that fact. + * + * Typical usage: + * a. OS service logic (not application logic*) attaches to the PHY + * PHY interrupt and enables the PHY interrupt. + * b. When the PHY interrupt occurs: (1) the interrupt should be + * disabled and () work should be scheduled on the worker thread (or + * perhaps a dedicated application thread). + * c. That worker thread should use the SIOCGMIIPHY, SIOCGMIIREG, + * and SIOCSMIIREG ioctl calls** to communicate with the PHY, + * determine what network event took place (Link Up/Down?), and + * take the appropriate actions. + * d. It should then interact the PHY to clear any pending + * interrupts, then re-enable the PHY interrupt. + * + * * This is an OS internal interface and should not be used from + * application space. Rather applications should use the SIOCMIISIG + * ioctl to receive a signal when a PHY event occurs. + * ** This interrupt is really of no use if the Ethernet MAC driver + * does not support these ioctl calls. + * + * Input Parameters: + * intf - Identifies the network interface. For example "eth0". Only + * useful on platforms that support multiple Ethernet interfaces + * and, hence, multiple PHYs and PHY interrupts. + * handler - The client interrupt handler to be invoked when the PHY + * asserts an interrupt. Must reside in OS space, but can + * signal tasks in user space. A value of NULL can be passed + * in order to detach and disable the PHY interrupt. + * arg - The argument that will accompany the interrupt + * enable - A function pointer that be unsed to enable or disable the + * PHY interrupt. + * + * Returned Value: + * Zero (OK) returned on success; a negated errno value is returned on + * failure. + * + ****************************************************************************/ + +#if defined(CONFIG_ARCH_PHY_INTERRUPT) +int arch_phy_irq(FAR const char *intf, xcpt_t handler, void *arg, + phy_enable_t *enable) +{ + /* Using ET0_LINKSTA for PHY interrupt line which is connected to ETHERC. + * Interrupt will generate on common line EINT0 which is + * used for all other interrupt as well. + */ + + irqstate_t flags; + phy_enable_t enabler; + int irq; + + DEBUGASSERT(intf); + + ninfo("%s: handler=%p\n", intf, handler); + phyinfo("EMAC0: devname=%s\n", RX65N_EMAC0_DEVNAME); + + if (strcmp(intf, RX65N_EMAC0_DEVNAME) == 0) + { + phyinfo("Select EMAC0\n"); + } + else + { + nerr("ERROR: Unsupported interface: %s\n", intf); + return -ENODEV; + } + + flags = enter_critical_section(); + rx65n_phyintenable(false); + + /* Configure the interrupt */ + + if (handler) + { + phylinknotification.phandler = handler; + phylinknotification.penable = enable; + phylinknotification.pclient = arg; + enabler = rx65n_phyintenable; + } + else + { + phylinknotification.phandler = NULL; + phylinknotification.penable = NULL; + phylinknotification.pclient = NULL; + enabler = NULL; + } + + /* Return the enabling function pointer */ + + if (enable) + { + *enable = enabler; + } + + /* Return the old handler (so that it can be restored) */ + + leave_critical_section(flags); + return OK; +} +#endif + +/**************************************************************************** + * Function Name: phy_start_autonegotiate + * Description : Starts auto-negotiate + * Arguments : pause - + * Using state of pause frames + * Return Value : none + ***************************************************************************/ + +void phy_start_autonegotiate (uint8_t pause) +{ + volatile uint16_t regval = 0; + + /* Set local ability */ + + /* When pause frame is not used */ + + if (ETHER_FLAG_OFF == pause) + { + regval = ((((PHY_AN_ADVERTISEMENT_100F | + PHY_AN_ADVERTISEMENT_100H) | + PHY_AN_ADVERTISEMENT_10F) | + PHY_AN_ADVERTISEMENT_10H) | + PHY_AN_ADVERTISEMENT_SELECTOR); + } + + /* When pause frame is used */ + + else + { + regval = ((((((PHY_AN_ADVERTISEMENT_ASM_DIR | + PHY_AN_ADVERTISEMENT_PAUSE) | + PHY_AN_ADVERTISEMENT_100F) | + PHY_AN_ADVERTISEMENT_100H) | + PHY_AN_ADVERTISEMENT_10F) | + PHY_AN_ADVERTISEMENT_10H) | + PHY_AN_ADVERTISEMENT_SELECTOR); + } + + /* Configure what the PHY and the Ethernet controller on this board supports */ + + rx65n_phywrite(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_REG_AN_ADVERTISEMENT, regval); + rx65n_phywrite(CONFIG_RX65N_EMAC0_PHYADDR, PHY_REG_CONTROL, + (PHY_CONTROL_AN_ENABLE | PHY_CONTROL_AN_RESTART)); +} + +/**************************************************************************** + * Function Name: rx65n_power_on_control + * Description : Powers on the channel if the ETHEC channel + * used and the PHY access channel are different, or if the + * PHY access channel is powered off. + * Arguments : none + * Return Value : none + ***************************************************************************/ + +void rx65n_power_on_control(void) +{ + uint8_t regval = 0; + + /* Enable writing to registers related to operating modes, LPC, CGC and + * software reset + */ + + SYSTEM.PRCR.WORD = 0xa50bu; + + /* Enable writing to MSTP registers. */ + + regval = getreg8(RX65N_MPC_PWPR); + regval &= (~(1 << 7)); /* Clearing the PWPR register B0WI bit */ + putreg8(regval, RX65N_MPC_PWPR); + regval = getreg8(RX65N_MPC_PWPR); + regval |= (1 << 6); /* Enabling the PWPR registers PFSWE bit */ + putreg8(regval, RX65N_MPC_PWPR); + + /* Enable selected ETHERC/EDMAC Channel. */ + + regval = rx65n_getreg(RX65N_MSTP_CRB); + regval &= (~(1 << 15)); /* Clearing the MSTPB bit in MSTPCRB to release from module stop state */ + rx65n_putreg(regval, RX65N_MSTP_CRB); + + /* Disable writing to MSTP registers. */ + + regval = getreg8(RX65N_MPC_PWPR); + regval &= (~(1 << 7)); /* Clearing the PWPR register B0WI bit */ + putreg8(regval, RX65N_MPC_PWPR); + regval = getreg8(RX65N_MPC_PWPR); + regval &= (~(1 << 6)); /* Clear the PWPR registers PFSWE bit */ + putreg8(regval, RX65N_MPC_PWPR); + regval = getreg8(RX65N_MPC_PWPR); + regval |= (1 << 7); /* Enable the PWPR register B0WI bit */ + putreg8(regval, RX65N_MPC_PWPR); + + /* Enable protection */ + + SYSTEM.PRCR.WORD = 0xa500u; +} + +/**************************************************************************** + * Function Name: rx65n_ether_set_phy_mode + * Description : Set port connect for Mode selection + * Arguments : mode - + * phy mode + * Return Value : none + ***************************************************************************/ + +void rx65n_ether_set_phy_mode(uint8_t mode) +{ + if (PHY_MII_SET_MODE == mode) + { + /* MII */ + + /* PFENET -> PHYMODE0 is Enabled Ethernet Channel0 to use MII Mode; */ + + putreg8(0x10, RX65N_MPC_PFENET); + } + else if (PHY_RMII_SET_MODE == mode) + { + /* RMII */ + + /* PFENET -> PHYMODE0 is Enabled Ethernet Channel0 to use MII Mode; */ + + putreg8(0x00, RX65N_MPC_PFENET); + } + else + { + /* By Default MII will be selected */ + + /* PFENET -> PHYMODE0 is Enabled Ethernet Channel0 to use MII Mode; */ + + putreg8(0x10, RX65N_MPC_PFENET); + } +} + +/**************************************************************************** + * Function Name: phy_reg_read + * Description : Reads PHY register through MII interface + * Arguments : pdata - + * pointer to store the data read + * Return Value : none + ***************************************************************************/ + +static void phy_reg_read (uint16_t *pdata) +{ + int32_t databitcnt = 0; + int32_t j; + uint16_t reg_data; + + /* The processing of DATA (data) about reading of the frame format + * of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" of + * "IEEE 802.3-2008_section2". + */ + + reg_data = 0; + databitcnt = 16; /* Number of bit to read */ + + while (databitcnt > 0) /* reading 1 bit per loop */ + { + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) + { + /* Reset All Flags of PIR */ + + rx65n_putreg(0x00000000, RX65N_ETH_PIR); + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) + { + /* Setting MDC of PIR */ + + rx65n_putreg(0x00000001, RX65N_ETH_PIR); + } + + reg_data <<= 1; + + /* MDI read */ + + reg_data |= (uint16_t) (((rx65n_getreg(RX65N_ETH_PIR)) & 0x00000008) >> 3); + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) + { + /* Setting MDC of PIR */ + + rx65n_putreg(0x00000001, RX65N_ETH_PIR); + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) + { + rx65n_putreg(0x00000000, RX65N_ETH_PIR); /* Reset All Flags of PIR */ + } + + databitcnt--; + } + + (*pdata) = reg_data; +} + +/**************************************************************************** + * Function Name: rx65n_phyread + * Description : Reads a PHY register + * Arguments : phydevaddr - + * Phy address + * reg_addr - + * address of the PHY register + * Return Value : read value + ***************************************************************************/ + +static uint16_t rx65n_phyread (uint8_t phydevaddr, uint16_t reg_addr, + uint16_t *value) +{ + uint16_t data; + + /* The value is read from the PHY register by the frame format + * of MII Management Interface provided + * for by Table 22-12 of 22.2.4.5 of + * IEEE 802.3-2008_section2. + */ + + rx65n_phy_preamble(); + rx65n_phy_reg_set(phydevaddr, reg_addr, PHY_MII_READ); + rx65n_phy_trans_zto0(); + phy_reg_read(&data); + rx65n_phy_trans_zto0(); + *value = data; + return OK; +} + +/**************************************************************************** + * Function Name: rx65n_ether_enable_icu + * Description : + * Arguments : + * Return Value : none + ****************************************************************************/ + +void rx65n_ether_enable_icu(void) +{ + uint32_t ipl; + + /* Enabling EDMAC0 interrupt request using AL1 group interrupt */ + + ICU.GENAL1.BIT.EN4 = 1; + + /* Priority to this interrupt should be value 2 */ + + ipl = ETHER_CFG_AL1_INT_PRIORTY; + + /* Disable group interrupts */ + + IEN(ICU, GROUPAL1) = 0; + + /* Clear interrupt flag */ + + IR(ICU, GROUPAL1) = 0; + + /* Set priority level */ + + IPR(ICU, GROUPAL1) = (uint8_t) + (ipl > IPR(ICU, GROUPAL1) ? ipl : IPR(ICU, GROUPAL1)); + + /* Enable group BL0 interrupt */ + + IEN(ICU, GROUPAL1) = 1; +} + +/*************************************************************************** + * Function Name: rx65n_phy_trans_zto0 + * Description : Performs bus release so that PHY can drive data + * : for read operation + * Arguments : ether_channel - + * Ethernet channel number + * Return Value : none + ***************************************************************************/ + +static void rx65n_phy_trans_zto0 () +{ + int32_t j; + + /* The processing of TA (turnaround) about reading of the frame format of + * MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". + */ + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) + { + /* Resetting All flags of PIR */ + + rx65n_putreg(0x00000000, RX65N_ETH_PIR); + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) + { + rx65n_putreg(0x00000001, RX65N_ETH_PIR); /* Setting MDC of PIR */ + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) + { + rx65n_putreg(0x00000001, RX65N_ETH_PIR); /* Setting MDC of PIR */ + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) + { + /* Resetting All flags of PIR */ + + rx65n_putreg(0x00000000, RX65N_ETH_PIR); + } +} + +/**************************************************************************** + * Function Name: rx65n_phy_trans_1to0 + * Description : Switches data bus so MII interface can drive data + * : for write operation + * Arguments : ether_channel - + * Ethernet channel number + * Return Value : none + ***************************************************************************/ + +static void rx65n_phy_trans_1to0 () +{ + /* The processing of TA (turnaround) about writing of the frame format + * of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". + */ + + rx65n_phy_mii_write1(); + rx65n_phy_mii_write0(); +} + +/**************************************************************************** + * Function Name: rx65n_phy_reg_set + * Description : Sets a PHY device to read or write mode + * Arguments : phydevaddr - + * Phy address + * reg_addr - + * address of the PHY register + * option - + * mode + * Return Value : none + ***************************************************************************/ + +static void rx65n_phy_reg_set (uint8_t phydevaddr, uint16_t reg_addr, + int32_t option) +{ + int32_t bitcnt = 0; + uint16_t data; + + /* The processing of ST (start of frame), + * OP (operation code), PHYAD (PHY Address), and + * REGAD (Register Address) about the frame format of + * MII Management Interface which is + * provided by "Table 22-12" of + * "22.2.4.5" of "IEEE 802.3-2008_section2". + */ + + data = 0; + data = (PHY_MII_ST << 14); /* ST code */ + if (PHY_MII_READ == option) + { + data |= (PHY_MII_READ << 12); /* OP code(RD) */ + } + else + { + data |= (PHY_MII_WRITE << 12); /* OP code(WR) */ + } + + data |= (uint16_t) (phydevaddr << 7); /* PHY Address configured 0x1e in decimal 30 */ + data |= (reg_addr << 2); + bitcnt = 14; /* These number of bits to send for ST, OP, PHYAD and REGAD */ + while (bitcnt > 0) + { + if (0 == (data & 0x8000)) + { + rx65n_phy_mii_write0(); + } + else + { + rx65n_phy_mii_write1(); + } + + data <<= 1; + bitcnt--; + } +} + +/**************************************************************************** + * Function Name: rx65n_phy_reg_write + * Description : Writes to PHY register through MII interface + * Arguments : data - + * value to write + * Return Value : none + ***************************************************************************/ + +static void rx65n_phy_reg_write (uint16_t data) +{ + int32_t databitcnt = 0; + + /* The processing of DATA (data) about writing of the frame format + * of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" + * of "IEEE 802.3-2008_section2". + */ + + databitcnt = 16; /* Number of bit to write */ + while (databitcnt > 0) /* writing 1 bit per loop */ + { + if (0 == (data & 0x8000)) + { + rx65n_phy_mii_write0(); + } + else + { + rx65n_phy_mii_write1(); + } + + databitcnt--; + data <<= 1; + } +} + +/**************************************************************************** + * Function Name: rx65n_phy_mii_write1 + * Description : Outputs 1 to the MII interface + * Arguments : none + * Return Value : none + ***************************************************************************/ + +static void rx65n_phy_mii_write1 () +{ + int32_t j; + + /* The processing of one bit about frame format + * of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" + * of "IEEE 802.3-2008_section2". + * The data that 1 is output. + */ + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) + { + /* Setting MDO and MMD and by default MDI */ + + rx65n_putreg(0x00000006, RX65N_ETH_PIR); + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) + { + /* Setting MDO, MMD and MDC and by default MDI */ + + rx65n_putreg(0x00000007, RX65N_ETH_PIR); + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) + { + /* Setting MDO, MMD and MDC and by default MDI */ + + rx65n_putreg(0x00000007, RX65N_ETH_PIR); + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) + { + /* Setting MDO and MMD and by default MDI */ + + rx65n_putreg(0x00000006, RX65N_ETH_PIR); + } +} + +/**************************************************************************** + * Function Name: rx65n_phy_mii_write0 + * Description : Outputs 0 to the MII interface + * Arguments : none + * Return Value : none + ***************************************************************************/ + +static void rx65n_phy_mii_write0(void) +{ + int32_t j; + + /* The processing of one bit about frame format + * of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" of "IEEE 802.3-2008_section2". + * The data that 0 is output. + */ + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) + { + /* Setting MMD and by default MDI */ + + rx65n_putreg(0x00000002, RX65N_ETH_PIR); + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) + { + /* Setting MDC and MMD and by default MDI */ + + rx65n_putreg(0x00000003, RX65N_ETH_PIR); + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) + { + /* Setting MDC and MMD and by default MDI */ + + rx65n_putreg(0x00000003, RX65N_ETH_PIR); + } + + for (j = ETHER_CFG_PHY_MII_WAIT; j > 0; j--) + { + /* Setting MMD and by default MDI */ + + rx65n_putreg(0x00000002, RX65N_ETH_PIR); + } +} + +/**************************************************************************** + * Function Name: rx65n_phy_preamble + * Description : As preliminary preparation for access + * to the PHY module register, + * "1" is output via the MII management interface. + * Arguments : none + * Return Value : none + ***************************************************************************/ + +static void rx65n_phy_preamble(void) +{ + int16_t preamble_bits = 0; + + /* The processing of PRE (preamble) about the frame format + * of MII Management Interface which is + * provided by "Table 22-12" of "22.2.4.5" + * of "IEEE 802.3-2008_section2". + */ + + /* Send 32 consecutive 1’s as per 34.3.4.1 + * MII/RMII Management Frame Format + */ + + preamble_bits = 32; + while (preamble_bits > 0) + { + rx65n_phy_mii_write1(); + preamble_bits--; + } +} + +/**************************************************************************** + * Function Name: rx65n_phywrite + * Description : Writes to a PHY register + * Arguments : phydevaddr - + * Phy device address + * reg_addr - + * address of the PHY register + * data - + * value + * Return Value : none + ***************************************************************************/ + +static int rx65n_phywrite (uint8_t phydevaddr, uint16_t reg_addr, + uint16_t data) +{ + /* The value is read from the PHY register by the frame format + * of MII Management Interface provided + * for by Table 22-12 of 22.2.4.5 of IEEE 802.3-2008_section2. + */ + + rx65n_phy_preamble(); + rx65n_phy_reg_set(phydevaddr, reg_addr, PHY_MII_WRITE); + rx65n_phy_trans_1to0(); + rx65n_phy_reg_write(data); + rx65n_phy_trans_zto0(); + return OK; +} + +/**************************************************************************** + * Function Name: rx65n_ether_interrupt_init + * Description : Writes to a ETHERC/EDMAC register + * Arguments : none + * Return Value : none + ***************************************************************************/ + +void rx65n_ether_interrupt_init(void) +{ + uint32_t regval; + + /* Start interrupt control unit for ethernet interrupt */ + + rx65n_ether_enable_icu(); + + /* Clear all ETHERC status BFR, PSRTO, LCHNG, MPD, ICD */ + + rx65n_putreg(ETH_ECSR_CLR, RX65N_ETH_ECSR); + + /* Clear all EDMAC status bits */ + + rx65n_putreg(ETHD_EESR_EDMAC, RX65N_ETHD_EESR); + + /* Notification of ET0_LINKSTA signal change interrupt is disabled. */ + + regval = rx65n_getreg(RX65N_ETH_ECSIPR); + regval &= (~(ETH_ECSIPR_LCHNGIP)); + rx65n_putreg(regval, RX65N_ETH_ECSIPR); + + /* ETHERC status interrupt request is disabled */ + + regval = rx65n_getreg(RX65N_ETHD_EESIPR); + regval &= (~(ETHD_EESIPR_ECIIP)); + rx65n_putreg(regval, RX65N_ETHD_EESIPR); +} + +/**************************************************************************** + * Function: rx65n_phy_reg_dump + * + * Description: + * Test PHY all register read and dump + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +#if defined(PHY_REG_DEBUGGING) +static void rx65n_phy_reg_dump(void) +{ + int reg_offset; + int ret; + uint16_t reg; + + /* Info: BMCR(Basic mode control register) offset 0x0; + * BMSR(Basic mode control register) offset 0x1 + * PHSTS(Phy status register) offset 0x10 + */ + + for (reg_offset = 0; reg_offset < 32; reg_offset++) + { + reg = 0; + ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR, reg_offset, ®); + + /* Read data from reg variable while debugging */ + + if (ret < 0) + { + nerr("ERROR: Failed to read register: %d\n", reg_offset); + } + } +} +#endif + +/**************************************************************************** + * Function: rx65n_phy_read_write_test + * + * Description: + * Test PHY read write operation + * + * Input Parameters: + * None + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +#if defined(PHY_READ_WRITE_TEST) +static int rx65n_phy_read_write_test(void) +{ + int ret; + uint16_t reg; + reg = 0; + ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR, PHY_REG_IDENTIFIER1, ®); + if (reg != PHY_REG_IDENTIFIER1_DEF_VAL) + { + nerr("ERROR: Failed to read PHY IDENTIFIER1 register\n"); + return R_PHY_ERROR; + } + + ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR, PHY_REG_IDENTIFIER2, ®); +#if defined(CONFIG_ARCH_RX65N_GRROSE) + + /* The default value of LSB 4 bit will vary + * dependent on the silicon revision number. + */ + + reg = reg & 0xfff0; +#endif + if (reg != PHY_REG_IDENTIFIER2_DEF_VAL) + { + nerr("ERROR: Failed to read PHY IDENTIFIER2 register\n"); + nerr("ERROR: Failed to read PHY IDENTIFIER2 register\n"); + return R_PHY_ERROR; + } + +#if defined(CONFIG_ARCH_RX65N_RSK2MB) + ret = rx65n_phywrite(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_REG_MII_INT_CONTROL, 0x0000); + ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_REG_MII_INT_CONTROL, ®); + if (reg != 0x0000) + { + nerr("ERROR: Failed to write to PHY_REG_MII_INT_CONTROL n"); + return R_PHY_ERROR; + } + + ret = rx65n_phywrite(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_REG_MII_INT_CONTROL, 0x0001); + ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_REG_MII_INT_CONTROL, ®); + if (reg != 0x0001) + { + nerr("ERROR: Failed to write to PHY_REG_MII_INT_CONTROL n"); + return R_PHY_ERROR; + } + + ret = rx65n_phywrite(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_REG_MII_INT_CONTROL, 0x0002); + ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_REG_MII_INT_CONTROL, ®); + if (reg != 0x0002) + { + nerr("ERROR: Failed to write to PHY_REG_MII_INT_CONTROL n"); + return R_PHY_ERROR; + } + + ret = rx65n_phywrite(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_REG_MII_INT_CONTROL, 0x0003); + ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_REG_MII_INT_CONTROL, ®); + if (reg != 0x0003) + { + nerr("ERROR: Failed to write to PHY_REG_MII_INT_CONTROL n"); + return R_PHY_ERROR; + } + + ret = rx65n_phywrite(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_REG_MII_INT_CONTROL, 0x0004); + ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_REG_MII_INT_CONTROL, ®); + if (reg != 0x0004) + { + nerr("ERROR: Failed to write to PHY_REG_MII_INT_CONTROL n"); + return R_PHY_ERROR; + } + + ret = rx65n_phywrite(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_REG_MII_INT_CONTROL, 0x0005); + ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_REG_MII_INT_CONTROL, ®); + if (reg != 0x0005) + { + nerr("ERROR: Failed to write to PHY_REG_MII_INT_CONTROL n"); + return R_PHY_ERROR; + } + + ret = rx65n_phywrite(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_REG_MII_INT_CONTROL, 0x0006); + ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_REG_MII_INT_CONTROL, ®); + if (reg != 0x0006) + { + nerr("ERROR: Failed to write to PHY_REG_MII_INT_CONTROL n"); + return R_PHY_ERROR; + } + + ret = rx65n_phywrite(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_REG_MII_INT_CONTROL, 0x0007); + ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_REG_MII_INT_CONTROL, ®); + if (reg != 0x0007) + { + nerr("ERROR: Failed to write to PHY_REG_MII_INT_CONTROL n"); + return R_PHY_ERROR; + } +#endif + + return R_PHY_OK; +} +#endif + +/**************************************************************************** + * Function: rx65n_phyinit + * + * Description: + * Configure the PHY and determine the link speed/duplex. + * + * Input Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +static int rx65n_phyinit(FAR struct rx65n_ethmac_s *priv) +{ + uint32_t count; + uint16_t reg; + int ret; + count = 0; + +#ifdef CONFIG_RX65N_EMAC0_AUTONEG + /* Software Reset the PHY */ + + ret = rx65n_phywrite(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_REG_CONTROL, PHY_CONTROL_RESET); + + /* Reset completion waiting */ + + do + { + ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR, + PHY_REG_CONTROL, ®); + count++; + } + while ((reg & PHY_CONTROL_RESET) && (count < ETHER_CFG_PHY_DELAY_RESET)); + + if (count > ETHER_CFG_PHY_DELAY_RESET) + { + ret = -ETIMEDOUT; + goto error_with_reset_timeout; + } + + priv->mbps100 = 0; + priv->fduplex = 0; + + /* Initialize the PHY Auto negotiation with frame pause disable */ + + phy_start_autonegotiate (PAUSE_FRAME_DISABLE); + + /* Interrupt initialization */ + + rx65n_ether_interrupt_init(); + + /* To check the Link status in PHY registers read Auto-negotiation + * Advertisement register + */ + + ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR, PHY_REG_STATUS, ®); + + count = 0; + do + { + /* Reading PHY status register after negotiation */ + + ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR, PHY_REG_STATUS, ®); + count++; + } + while ((!((reg & (PHY_VALID_LINK | PHY_AUTO_NEG_DONE)) + || (count > ETHER_PHY_STATUS_CHECK_DELAY)))); + + if (count > ETHER_PHY_STATUS_CHECK_DELAY) + { + ret = -ETIMEDOUT; + goto error_with_auto_neg_timeout; + } + +#ifdef CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG + ret = rx65n_phyread(CONFIG_RX65N_EMAC0_PHYADDR, PHY_STS_REG, ®); + switch (reg & CONFIG_RX65N_EMAC0_PHYSR_ALTMODE) + { + default: + case CONFIG_RX65N_EMAC0_PHYSR_10HD: + priv->fduplex = 0; + priv->mbps100 = 0; + break; + + case CONFIG_RX65N_EMAC0_PHYSR_100HD: + priv->fduplex = 0; + priv->mbps100 = 1; + break; + + case CONFIG_RX65N_EMAC0_PHYSR_10FD: + priv->fduplex = 1; + priv->mbps100 = 0; + break; + + case CONFIG_RX65N_EMAC0_PHYSR_100FD: + priv->fduplex = 1; + priv->mbps100 = 1; + break; + } +#endif +#endif + error_with_reset_timeout: + error_with_auto_neg_timeout: + return ret; +} + +/**************************************************************************** + * Function: rx65n_ethreset + * + * Description: + * Reset the Ethernet block. + * + * Input Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * Zero on success, or a negated errno value on any failure. + * + * Assumptions: + * + ****************************************************************************/ + +static int rx65n_ethreset(FAR struct rx65n_ethmac_s *priv) +{ + uint32_t regval; + uint32_t retries; + + /* Notification of ET0_LINKSTA signal change interrupt is disabled. */ + + regval = rx65n_getreg(RX65N_ETH_ECSIPR); + regval &= (~(ETH_ECSIPR_LCHNGIP)); + rx65n_putreg(regval, RX65N_ETH_ECSIPR); + + regval = rx65n_getreg(RX65N_ETHD_EESIPR); + regval &= (~(ETHD_EESIPR_ECIIP)); + rx65n_putreg(regval, RX65N_ETHD_EESIPR); + + /* Disable TE and RE in ECMR Register */ + + /* rx65n_putreg(ETH_ECMR_CLR, RX65N_ETH_ECMR); */ + + regval = rx65n_getreg(RX65N_ETH_ECMR); + regval &= (~(ETH_ECMR_TE | ETH_ECMR_RE)); + rx65n_putreg(regval, RX65N_ETH_ECMR); + + /* Perform a software reset by setting the SWR bit in the EDMR register. + * When 1 is written, the EDMAC and ETHERC are reset + */ + + /* Registers TDLAR, RDLAR, RMFCR TFUCR and RFOCR are not reset */ + + regval = rx65n_getreg(RX65N_ETHD_EDMR); + regval |= ETHD_EDMR_SWR; + rx65n_putreg(regval, RX65N_ETHD_EDMR); + + /* Wait for software reset to complete. The SR bit is cleared automatically + * after the reset operation has completed in all of the core clock + * domains. + */ + + retries = 10; + while (((rx65n_getreg(RX65N_ETHD_EDMR) & ETHD_EDMR_SWR) != 0) && + retries > 0) + { + retries --; + up_mdelay(10); + } + + if (retries == 0) + { + return -ETIMEDOUT; + } + + /* Notification of ET0_LINKSTA signal change interrupt is disabled. */ + + regval = rx65n_getreg(RX65N_ETH_ECSIPR); + regval |= (ETH_ECSIPR_LCHNGIP); + rx65n_putreg(regval, RX65N_ETH_ECSIPR); + + regval = rx65n_getreg(RX65N_ETHD_EESIPR); + regval |= (ETHD_EESIPR_ECIIP); + rx65n_putreg(regval, RX65N_ETHD_EESIPR); + + return 0; +} + +/**************************************************************************** + * Function: rx65n_macconfig + * + * Description: + * Configure the Ethernet MAC for DMA operation. + * Software reset has to be executed, and ETHERC and EDMAC are configured. + * Input Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +static int rx65n_macconfig(FAR struct rx65n_ethmac_s *priv) +{ + uint32_t regval; + uint32_t retries; + + /* Perform a software reset by setting the SWR bit in the EDMR register. + * When 1 is written, the EDMAC and ETHERC are reset + */ + + /* Registers TDLAR, RDLAR, RMFCR TFUCR and RFOCR are not reset */ + + regval = rx65n_getreg(RX65N_ETHD_EDMR); + regval |= ETHD_EDMR_SWR; + rx65n_putreg(regval, RX65N_ETHD_EDMR); + + retries = 10; + while (((rx65n_getreg(RX65N_ETHD_EDMR) & ETHD_EDMR_SWR) != 0) && + retries > 0) + { + retries --; + up_mdelay(10); + } + + /* Notification of ET0_LINKSTA signal change interrupt is disabled. */ + + regval = rx65n_getreg(RX65N_ETH_ECSIPR); + regval |= (ETH_ECSIPR_LCHNGIP); + rx65n_putreg(regval, RX65N_ETH_ECSIPR); + + regval = rx65n_getreg(RX65N_ETHD_EESIPR); + regval |= (ETHD_EESIPR_ECIIP); + rx65n_putreg(regval, RX65N_ETHD_EESIPR); + + rx65n_macaddress(priv); + return OK; +} + +/**************************************************************************** + * Function: rx65n_macaddress + * + * Description: + * Configure the selected MAC address. + * + * Input Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +static void rx65n_macaddress(FAR struct rx65n_ethmac_s *priv) +{ + FAR struct net_driver_s *dev = &priv->dev; + uint32_t regval; + regval = 0; + + ninfo("%s MAC: %02x:%02x:%02x:%02x:%02x:%02x\n", + dev->d_ifname, + dev->d_mac.ether.ether_addr_octet[0], + dev->d_mac.ether.ether_addr_octet[1], + dev->d_mac.ether.ether_addr_octet[2], + dev->d_mac.ether.ether_addr_octet[3], + dev->d_mac.ether.ether_addr_octet[4], + dev->d_mac.ether.ether_addr_octet[5]); + + /* Set the MAC address high register */ + + regval = (((((uint32_t) dev->d_mac.ether.ether_addr_octet[0] << 24) | + ((uint32_t) dev->d_mac.ether.ether_addr_octet[1] << 16)) + | ((uint32_t) dev->d_mac.ether.ether_addr_octet[2] << 8)) | + (uint32_t) dev->d_mac.ether.ether_addr_octet[3]); + rx65n_putreg(regval, RX65N_ETH_MAHR); + + /* Set the MAC address low register */ + + regval = 0; + regval = (((uint32_t) dev->d_mac.ether.ether_addr_octet[4] << 8) | + (uint32_t)dev->d_mac.ether.ether_addr_octet[5]); + rx65n_putreg(regval, RX65N_ETH_MALR); +} + +/**************************************************************************** + * Function: rx65n_ipv6multicast + * + * Description: + * Configure the IPv6 multicast MAC address. + * + * Input Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +/* Currently Not supportted, Need to update this code when support added */ + +#ifdef CONFIG_NET_ICMPv6 +static void rx65n_ipv6multicast(FAR struct rx65n_ethmac_s *priv) +{ + /* Currnently not implemented */ +} +#endif /* CONFIG_NET_ICMPv6 */ + +/**************************************************************************** + * Function: rx65n_ethconfig + * + * Description: + * Configure the Ethernet interface for operation. + * + * Input Parameters: + * priv - A reference to the private driver state structure + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * + ****************************************************************************/ + +static int rx65n_ethconfig(FAR struct rx65n_ethmac_s *priv) +{ + int ret; + uint32_t regval; + + /* Reset the Ethernet block */ + + ninfo("Reset the Ethernet block\n"); + ret = rx65n_ethreset(priv); + if (ret < 0) + { + nerr("ERROR: Reset of Ethernet block failed\n"); + return ret; + } + + /* Initialize the PHY selection Set port connect + * Currently we are using MII + */ + +#if defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB) || \ + defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) + rx65n_ether_set_phy_mode(PHY_MII_SET_MODE); +#else + rx65n_ether_set_phy_mode(PHY_RMII_SET_MODE); +#endif + + /* ETHERC/EDMAC Power on */ + + rx65n_power_on_control(); + + /* Test PHY read write */ + +#if defined(PHY_READ_WRITE_TEST) + ret = rx65n_phy_read_write_test(); + if (ret < 0) + { + nerr("ERROR: PHY read write failed\n"); + return ret; + } +#endif + + /* Initialize the PHY */ + + ninfo("Initialize the PHY\n"); + ret = rx65n_phyinit(priv); + if (ret < 0) + { + return ret; + } + + /* Initialize the MAC and Ethernet DMA */ + + ninfo("Initialize the MAC and DMA\n"); + ret = rx65n_macconfig(priv); + if (ret < 0) + { + return ret; + } + +#ifndef CONFIG_ENDIAN_BIG + + /* Set little endian mode */ + + regval = rx65n_getreg(RX65N_ETHD_EDMR); + regval |= ETHD_EDMR_DE; + rx65n_putreg(regval, RX65N_ETHD_EDMR); +#endif + + /* Initialize the free buffer list */ + + rx65n_initbuffer(priv); + + /* Initialize TX Descriptors list: Chain Mode */ + + rx65n_txdescinit(priv); + + /* Initialize RX Descriptors list: Chain Mode */ + + rx65n_rxdescinit(priv); + + /* Clear all ETHERC status BFR, PSRTO, LCHNG, MPD, ICD */ + + rx65n_putreg(ETH_ECSR_CLR, RX65N_ETH_ECSR); + + /* Clear all EDMAC status bits */ + + rx65n_putreg(ETHD_EESR_EDMAC, RX65N_ETHD_EESR); + + /* Interrupt configuration */ + + /* Notification of ET0_LINKSTA signal change interrupt */ + + regval = rx65n_getreg(RX65N_ETH_ECSR); + regval |= ((ETH_ECSR_LCHNG)); /* Write 1 to clear flag */ + rx65n_putreg(regval, RX65N_ETH_ECSR); + regval = rx65n_getreg(RX65N_ETH_ECSIPR); + regval |= ((ETH_ECSIPR_LCHNGIP)); + rx65n_putreg(regval, RX65N_ETH_ECSIPR); + + /* ETHERC/EDMAC enabling Status Interrupt */ + + regval = rx65n_getreg(RX65N_ETHD_EESIPR); + regval |= ((ETHD_EESIPR_ECIIP)); + rx65n_putreg(regval, RX65N_ETHD_EESIPR); + + /* Ethernet length 1514bytes + CRC and */ + + rx65n_putreg(ETH_RFLR_RFL, RX65N_ETH_RFLR); + + /* Intergap is 96-bit time */ + + rx65n_putreg(ETH_IPGR_IPG_INITIAL, RX65N_ETH_IPGR); + + /* Continuous reception number of Broadcast frame */ + + rx65n_putreg(0x00000000, RX65N_ETH_BCFRR); + +#ifdef CONFIG_NET_MCASTGROUP + + /* Reflect the EESR.RMAF bit status in the RD0.RFS bit + * in the receive descriptor + */ + + rx65n_putreg(0x00000000, RX65N_ETHD_TRSCER); +#else + + /* Don't reflect the EESR.RMAF bit status in the RD0.RFS + * bit in the receive descriptor + */ + + rx65n_putreg(0x00000080, RX65N_ETHD_TRSCER); +#endif + + /* Threshold of Tx_FIFO */ + + rx65n_putreg(ETHD_TFTR_TFT, RX65N_ETHD_TFTR); /* Store and forward mode */ + + /* transmit fifo is 1968 bytes & receive fifo is 2048 bytes */ + + rx65n_putreg(0x00000707, RX65N_ETHD_FDR); + + /* Configure receiving method */ + + /* b0 RNR - Receive Request Bit Reset - Continuous reception + * of multiple frames is possible. + * b31:b1 Reserved set to 0 + */ + + rx65n_putreg(0x00000001, RX65N_ETHD_RMCR); + + /* Transmit Interrupt Setting */ + + rx65n_putreg(0x00000011, RX65N_ETHD_TRIMD); + + /* ETHERC/EDMAC enabling Interrupt */ + + regval = rx65n_getreg(RX65N_ETHD_EESIPR); + regval |= ((ETHD_EESIPR_TCIP) | (ETHD_EESIPR_FRIP) | (ETHD_EESIPR_ECIIP)); + rx65n_putreg(regval, RX65N_ETHD_EESIPR); + + regval = rx65n_getreg(RX65N_ETH_ECSIPR); + regval |= ((ETH_ECSIPR_LCHNGIP)); + rx65n_putreg(regval, RX65N_ETH_ECSIPR); + + /* Enabling TE and RE and set DM mode */ + + regval = rx65n_getreg(RX65N_ETH_ECMR); + regval |= ETH_ECMR_RE; + regval |= ETH_ECMR_TE; + if (priv->fduplex) + { + regval |= ETH_ECMR_DM; + } + else + { + regval &= (~ETH_ECMR_DM); + } + + if (priv->mbps100) + { + regval |= ETH_ECMR_RTM; + } + else + { + regval &= (~ETH_ECMR_RTM); + } + + rx65n_putreg(regval, RX65N_ETH_ECMR); + + /* Start DMA reception */ + + rx65n_putreg(0x00000001, RX65N_ETHD_EDRRR); + + /* Phy debugging */ + +#if defined(PHY_REG_DEBUGGING) + rx65n_phy_reg_dump(); +#endif + + return ret; +} + +/**************************************************************************** + * Function: rx65n_ethinitialize + * + * Description: + * Initialize the EMAC driver. + * + * Input Parameters: + * intf - If multiple EMAC peripherals are supported, this identifies the + * the EMAC peripheral being initialized. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * Called very early in the initialization sequence. + * + ****************************************************************************/ + +int rx65n_ethinitialize(int intf) +{ + struct rx65n_ethmac_s *priv; + int ret; + uint32_t reg32; + + /* Initialize hardware mac address */ + +#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) + uint8_t mac[6]; + mac[0] = 0x74; + mac[1] = 0x90; + mac[2] = 0x50; + mac[3] = 0x00; + mac[4] = 0x9c; + mac[5] = 0x91; +#elif defined (CONFIG_ARCH_BOARD_RX65N_RSK2MB) + uint8_t mac[6]; + mac[0] = 0x74; + mac[1] = 0x90; + mac[2] = 0x50; + mac[3] = 0x00; + mac[4] = 0x9c; + mac[5] = 0x94; +#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE) + uint8_t mac[6]; + mac[0] = 0x74; + mac[1] = 0x90; + mac[2] = 0x50; + mac[3] = 0x00; + mac[4] = 0x9c; + mac[5] = 0x97; +#else + uint8_t mac[6]; + mac[0] = 0x00; + mac[1] = 0x00; + mac[2] = 0x00; + mac[3] = 0x00; + mac[4] = 0x00; + mac[5] = 0x00; +#endif + + ninfo("intf: %d\n", intf); + + /* Get the interface structure associated with this interface number. */ + + DEBUGASSERT(intf < RX65N_NETHERNET); + + priv = &g_rx65nethmac[intf]; + + /* Initialize the driver structure */ + + memset(priv, 0, sizeof(struct rx65n_ethmac_s)); + + /* I/F up (new IP address) callback */ + + priv->dev.d_ifup = rx65n_ifup; + + /* I/F down callback */ + + priv->dev.d_ifdown = rx65n_ifdown; + priv->dev.d_txavail = rx65n_txavail; /* New TX data callback */ +#ifdef CONFIG_NET_MCASTGROUP + priv->dev.d_addmac = rx65n_addmac; /* Add multicast MAC address */ + priv->dev.d_rmmac = rx65n_rmmac; /* Remove multicast MAC address */ +#endif +#ifdef CONFIG_NETDEV_IOCTL + priv->dev.d_ioctl = rx65n_ioctl; /* Support PHY ioctl() calls */ +#endif + + /* Used to recover private state from dev */ + + priv->dev.d_private = (void *)g_rx65nethmac; + + /* hw mac address */ + + priv->dev.d_mac.ether.ether_addr_octet[0] = mac[0]; + priv->dev.d_mac.ether.ether_addr_octet[1] = mac[1]; + priv->dev.d_mac.ether.ether_addr_octet[2] = mac[2]; + priv->dev.d_mac.ether.ether_addr_octet[3] = mac[3]; + priv->dev.d_mac.ether.ether_addr_octet[4] = mac[4]; + priv->dev.d_mac.ether.ether_addr_octet[5] = mac[5]; + + /* Enable write to System registers */ + + putreg16(RX65N_PRCR_VALUE, RX65N_PRCR_ADDR); + + /* Start CMT module */ + + reg32 = getreg32(RX65N_MSTPCRA_ADDR); + + /* Release CMTW unit1 from module stop state(for CMTW1) */ + + reg32 &= (~RX65N_CMTW_UNIT1_MSTPCRA_STOP); + + /* Release CMTW unit1 from module stop state(for CMTW0) */ + + reg32 &= (~RX65N_CMTW_UNIT0_MSTPCRA_STOP); + putreg32(reg32, RX65N_MSTPCRA_ADDR); + + /* Create timer for timing polling for and timing of transmissions */ + + rx65n_cmtw0_create(RX65N_CMTW0_COUNT_VALUE_FOR_TXPOLL , + RX65N_CMTW0_COUNT_VALUE_FOR_TXTIMEOUT); + + /* Attach the IRQ to the driver */ + + if (irq_attach(RX65N_ETH_IRQ, rx65n_interrupt, NULL)) + { + /* We could not attach the ISR to the interrupt */ + + return -EAGAIN; + } + + /* Put the interface in the down state. */ + + ret = rx65n_ifdown(&priv->dev); + if (ret < 0) + { + nerr("ERROR: Initialization of Ethernet block failed: %d\n", ret); + return ret; + } + + /* Register the device with the OS so that socket IOCTLs can be performed */ + + (void)netdev_register(&priv->dev, NET_LL_ETHERNET); + return OK; +} + +/**************************************************************************** + * Function: up_netinitialize + * + * Description: + * This is the "standard" network initialization logic called from the + * low-level initialization logic in up_initialize.c. If RX65N_NETHERNET + * greater than one, then board specific logic will have to supply a + * version of up_netinitialize() that calls rx65n_ethinitialize() with + * the appropriate interface number. + * + * Input Parameters: + * None. + * + * Returned Value: + * None. + * + * Assumptions: + * + ****************************************************************************/ + +#if defined (CONFIG_NET) && !defined(CONFIG_NETDEV_LATEINIT) +void up_netinitialize(void) +{ + int ret; + +#if defined(CONFIG_RX65N_EMAC0) + + /* Initialize the EMAC0 driver */ + + ret = rx65n_ethinitialize(EMAC0_INTF); + if (ret < 0) + { + nerr("ERROR: up_emac_initialize(EMAC0) failed: %d\n", ret); + } +#endif +} +#endif +#endif /* RX65N_NETHERNET > 0 */ +#endif /* CONFIG_NET && CONFIG_RX65N_EMAC */ diff --git a/arch/renesas/src/rx65n/rx65n_eth.h b/arch/renesas/src/rx65n/rx65n_eth.h new file mode 100644 index 00000000000..1084523138e --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_eth.h @@ -0,0 +1,138 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_eth.h + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef __ARCH_RENESAS_SRC_RX65N_RX65N_ETH_H +#define __ARCH_RENESAS_SRC_RX65N_RX65N_ETH_H + +/**************************************************************************** + * Included Files + ***************************************************************************/ + +#include +#include "chip.h" + +/**************************************************************************** + * Pre-processor Definitions + ***************************************************************************/ + +/* Understood PHY types */ + +/* Definitions for use with rx65n_phy_boardinitialize */ + +#define RX65N_NETHERNET 1 + +#define EMAC0_INTF 0 + +/**************************************************************************** + * Public Functions + ***************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ***************************************************************************/ + +/**************************************************************************** + * Function: rx65n_ethinitialize + * + * Description: + * Initialize the EMAC driver. + * + * Input Parameters: + * intf - If multiple EMAC peripherals are supported, this identifies the + * the EMAC peripheral being initialized. + * + * Returned Value: + * OK on success; Negated errno on failure. + * + * Assumptions: + * Called very early in the initialization sequence. + * + ****************************************************************************/ + +#ifdef CONFIG_RX65N_EMAC0 +int rx65n_ethinitialize(int intf); + +/**************************************************************************** + * Function: rx65n_poll_expiry + * + * Description: + * Poll Expiry timer + * + * Input Parameters: + * argc - Input argument + * arg - Input argument + * + * Returned Value: + * None + * + ****************************************************************************/ + +void rx65n_poll_expiry(int argc, uint32_t arg, ...); + +/**************************************************************************** + * Function: rx65n_txtimeout_expiry + * + * Description: + * txtimeout timer + * + * Input Parameters: + * argc - Input argument + * arg - Input argument + * + * Returned Value: + * None + * + ****************************************************************************/ + +void rx65n_txtimeout_expiry(int argc, uint32_t arg, ...); +#endif + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_RENESAS_SRC_RX65N_RX65N_ETH_H */ diff --git a/arch/renesas/src/rx65n/rx65n_hardware_setup.c b/arch/renesas/src/rx65n/rx65n_hardware_setup.c new file mode 100644 index 00000000000..3c5929f24f1 --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_hardware_setup.c @@ -0,0 +1,118 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_hardware_setup.c + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * Surya + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "rx65n_macrodriver.h" +#include "rx65n_cgc.h" +#include "rx65n_icu.h" +#include "rx65n_port.h" +#include "rx65n_sci.h" +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" +#include "rx65n_definitions.h" + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +void r_ether_port_configuration(void); +void r_ether_pheriperal_enable(void); + +/**************************************************************************** + * Name: r_system_init + * + * Description: + * Initialization of hardware + ****************************************************************************/ + +void r_system_init(void) +{ + /* Enable writing to registers related to operating modes,LPC, CGC + * and software reset + */ + + SYSTEM.PRCR.WORD = 0xa50b; + + /* Enable writing to MPC pin function control registers */ + + MPC.PWPR.BIT.B0WI = 0; + MPC.PWPR.BIT.PFSWE = 1; + + /* Set peripheral settings */ + + r_cgc_create(); + r_icu_create(); + r_port_create(); + +#ifdef CONFIG_RX65N_EMAC0 + r_ether_port_configuration(); + r_ether_pheriperal_enable(); +#endif + + /* Disable writing to MPC pin function control registers */ + + MPC.PWPR.BIT.PFSWE = 0; + MPC.PWPR.BIT.B0WI = 1; + + /* Enable protection */ + + SYSTEM.PRCR.WORD = 0xa500; + + r_config_icu_software_start(); + r_config_icu_software2_start(); +} + +/**************************************************************************** + * Name: hardware_setup + * + * Description: + * Initialization of hardware + ****************************************************************************/ + +int hardware_setup(void) +{ + r_system_init(); + + return (1U); +} diff --git a/arch/renesas/src/rx65n/rx65n_head.S b/arch/renesas/src/rx65n/rx65n_head.S new file mode 100644 index 00000000000..22e9d1b7f2c --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_head.S @@ -0,0 +1,187 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_head.S + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#include /* NuttX configuration settings */ +#include /* Board-specific settings */ +#include /* IRQ definitons */ +#include "chip.h" /* Chip-specific settings */ +#include "up_internal.h" +#include "up_arch.h" + +/***************************************************************************** + * Pre-processor Definitions + *****************************************************************************/ + +/***************************************************************************** + * External references + *****************************************************************************/ + +/* Called functions */ + + .globl _up_lowsetup /* Early initialization of UART */ +#ifdef USE_EARLYSERIALINIT + .globl _up_earlyconsoleinit /* Early initialization of console driver */ +#endif +#ifdef CONFIG_ARCH_LEDS + .globl _board_autoled_initialize /* Boot LED setup */ +#endif +#ifdef CONFIG_DEBUG_FEATURES + .globl _up_lowputc /* Low-level debug output */ +#endif + .globl _nx_start /* NuttX entry point */ + +/* Variables set up by the linker script */ + + .globl _hardware_setup /* external Sub-routine to initialise Hardware */ + .globl _up_lowsetup + .globl _data + .globl _mdata + .globl _ebss + .globl _bss + .globl _edata + .globl _ustack + .globl _istack + .globl _g_exp_vector_table + .type _g_exp_vector_table, object + +/***************************************************************************** + * Macros + *****************************************************************************/ + +/***************************************************************************** + * Name: showprogress + * + * Description: + * Print a character on the UART to show boot status. This macro will + * modify r0, r1, r2 and r14 + * + *****************************************************************************/ + + .macro showprogress, code +#ifdef CONFIG_DEBUG_FEATURES + mov.l #_up_lowputc, r13 /* Address of up_earlyconsoleinit */ + mov #\code, r1 + jsr r13 /* Call it */ +#endif + .endm + +/**************************************************************************** + * Code + ***************************************************************************/ + + .section .text + +/**************************************************************************** + * Name: __start + * + * Description: + * After reset, program execution starts here. + * + ***************************************************************************/ + + .text + .align 16 + .globl __start + .type __start, #function + +__start: + mvtc #_ustack, USP /* initialise user stack pointer */ + mvtc #_istack, ISP /* initialise interrupt stack pointer */ +#ifdef __RXv2__ + mvtc #_except_vectors, extb /* setup exception vector (extb) */ +#endif + mvtc #__int_vector_table, intb /* setup interrupt vector (intb) */ + mvtc #100h, fpsw /* setup FPSW */ + +/* load data section from ROM to RAM */ + + mov #_mdata, r2 /* src ROM address of data section in R2 */ + mov #_data, r1 /* dest start RAM address of data section in R1 */ + mov #_edata, r3 /* end RAM address of data section in R3 */ + sub r1, r3 /* size of data section in R3 (R3=R3-R1) */ + smovf /* block copy R3 bytes from R2 to R1 */ + +/* bss initialisation : zero out bss */ + + mov #00h, r2 /* load R2 reg with zero */ + mov #_ebss, r3 /* store the end address of bss in R3 */ + mov #_bss, r1 /* store the start address of bss in R1 */ + sub r1, r3 /* size of bss section in R3 (R3=R3-R1) */ + sstr.b + +/* call the hardware initialiser */ + + bsr.a _hardware_setup + nop + mvtc #30000h, psw /* Set Ubit & Ibit for PSW */ + mov.l #_up_lowsetup, r15 + jsr r15 /* Call up_lowsetup */ + nop +#ifdef USE_EARLYSERIALINIT + mov.l #_up_earlyconsoleinit, r14 + jsr r14 /* Call up_earlyconsoleinit */ + nop +#endif + bsr.a _nx_start + nop +_exit: + nop +_loop_here: + bra _loop_here + nop + +/**************************************************************************** + * Data + ***************************************************************************/ + + .section .data + .data + .align 4 + + .global _g_idle_topstack + .type _g_idle_topstack, @object + +_g_idle_topstack: + .long _ebss + CONFIG_ARCH_INTERRUPTSTACK + CONFIG_IDLETHREAD_STACKSIZE + .size _g_idle_topstack, . - _g_idle_topstack + .end + +/**************************************************************************** + * EOF + ***************************************************************************/ diff --git a/arch/renesas/src/rx65n/rx65n_icu.c b/arch/renesas/src/rx65n/rx65n_icu.c new file mode 100644 index 00000000000..fe7fd7e252d --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_icu.c @@ -0,0 +1,312 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_icu.c + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "rx65n_macrodriver.h" +#include "rx65n_icu.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: r_icu_create + * + * Description: + * ICU Initialization + ****************************************************************************/ + +void r_icu_create(void) +{ + /* Disable IRQ interrupts */ + + ICU.IER[0x08].BYTE = _00_ICU_IRQ0_DISABLE | _00_ICU_IRQ1_DISABLE | + _00_ICU_IRQ2_DISABLE | _00_ICU_IRQ3_DISABLE | + _00_ICU_IRQ4_DISABLE | _00_ICU_IRQ5_DISABLE | + _00_ICU_IRQ6_DISABLE | _00_ICU_IRQ7_DISABLE ; + ICU.IER[0x09].BYTE = _00_ICU_IRQ8_DISABLE | _00_ICU_IRQ9_DISABLE | + _00_ICU_IRQ10_DISABLE | _00_ICU_IRQ11_DISABLE | + _00_ICU_IRQ12_DISABLE | _00_ICU_IRQ13_DISABLE | + _00_ICU_IRQ14_DISABLE | _00_ICU_IRQ15_DISABLE ; + + /* Disable group interrupts */ + + IEN(ICU, GROUPBL0) = 0u; + + /* Set IRQ settings */ + + ICU.IRQCR[8].BYTE = _04_ICU_IRQ_EDGE_FALLING; + ICU.IRQCR[9].BYTE = _04_ICU_IRQ_EDGE_FALLING; + + /* Set IRQ8 priority level */ + + IPR(ICU, IRQ8) = _0F_ICU_PRIORITY_LEVEL15; + + /* Set IRQ9 priority level */ + + IPR(ICU, IRQ9) = _0F_ICU_PRIORITY_LEVEL15; + + /* Set Group BL0 priority level */ + + IPR(ICU, GROUPBL0) = _0F_ICU_PRIORITY_LEVEL15; + + /* Enable group BL0 interrupt */ + + IEN(ICU, GROUPBL0) = 1U; + + /* Disable software interrupt */ + + IEN(ICU, SWINT) = 0U; + IEN(ICU, SWINT2) = 0U; + + /* Set SWINT priority level */ + + IPR(ICU, SWINT) = _0F_ICU_PRIORITY_LEVEL15; + + /* Set SWINT2 priority level */ + + IPR(ICU, SWINT2) = _0F_ICU_PRIORITY_LEVEL15; + + /* Set IRQ8 pin */ + + MPC.P00PFS.BYTE = 0x40u; + PORT0.PDR.BYTE &= 0xfeu; + PORT0.PMR.BYTE &= 0xfeu; + + /* Set IRQ9 pin */ + + MPC.P01PFS.BYTE = 0x40u; + PORT0.PDR.BYTE &= 0xfdu; + PORT0.PMR.BYTE &= 0xfdu; +} + +/**************************************************************************** + * Name: r_icu_irq8_start + * + * Description: + * Enable IRQ8 Interrupt + ****************************************************************************/ + +void r_icu_irq8_start(void) +{ + /* Enable IRQ8 interrupt */ + + IEN(ICU, IRQ8) = 1u; +} + +/**************************************************************************** + * Name: r_icu_irq8_stop + * + * Description: + *Initialize IRQ9 Interrupt + ****************************************************************************/ + +void r_icu_irq8_stop(void) +{ + /* Disable IRQ8 interrupt */ + + IEN(ICU, IRQ8) = 0u; +} + +/**************************************************************************** + * Name: r_icu_irq9_start + * + * Description: + * Enable IRQ9 Interrupt + ****************************************************************************/ + +void r_icu_irq9_start(void) +{ + /* Enable IRQ9 interrupt */ + + IEN(ICU, IRQ9) = 1u; +} + +/**************************************************************************** + * Name: r_icu_irq9_stop + * + * Description: + * Disable IRQ9 Interrupt + ****************************************************************************/ + +void r_icu_irq9_stop(void) +{ + /* Disable IRQ9 interrupt */ + + IEN(ICU, IRQ9) = 0u; +} + +/**************************************************************************** + * Name: r_config_icu_software_start + * + * Description: + * Enable S/W Interrupt + ****************************************************************************/ + +void r_config_icu_software_start(void) +{ + /* Enable software interrupt */ + + IEN(ICU, SWINT) = 1u; +} + +/**************************************************************************** + * Name: r_config_icu_softwareinterrupt_generate + * + * Description: + * Generate S/W Interrupt + ****************************************************************************/ + +void r_config_icu_softwareinterrupt_generate(void) +{ + /* Generate software interrupt */ + + ICU.SWINTR.BIT.SWINT = 1u; +} + +/**************************************************************************** + * Name: r_config_icu_software_stop + * + * Description: + * Disable S/W Interrupt + ****************************************************************************/ + +void r_config_icu_software_stop(void) +{ + /* Disable software interrupt */ + + IEN(ICU, SWINT) = 0u; +} + +/**************************************************************************** + * Name: r_config_icu_software2_start + * + * Description: + * Enable S/W Interrupt 2 + ****************************************************************************/ + +void r_config_icu_software2_start(void) +{ + /* Enable software interrupt 2 */ + + IEN(ICU, SWINT2) = 1u; +} + +/**************************************************************************** + * Name: r_config_icu_softwareinterrupt2_generate + * + * Description: + * Generate software interrupt 2 + ****************************************************************************/ + +void r_config_icu_softwareinterrupt2_generate(void) +{ + /* Generate software interrupt 2 */ + + ICU.SWINT2R.BIT.SWINT2 = 1u; +} + +/**************************************************************************** + * Name: r_config_icu_softwareinterrupt2_stop + * + * Description: + * Disable software interrupt 2 + ****************************************************************************/ + +void r_config_icu_software2_stop(void) +{ + /* Disable software interrupt 2 */ + + IEN(ICU, SWINT2) = 0u; +} + +/**************************************************************************** + * Name: r_icu_irqisfallingedge + * + * Description: + * Detect if falling edge interrupt is triggered + ****************************************************************************/ + +uint8_t r_icu_irqisfallingedge (const uint8_t irq_no) +{ + uint8_t falling_edge_trig = 0x0; + if (ICU.IRQCR[irq_no].BYTE & _04_ICU_IRQ_EDGE_FALLING) + { + falling_edge_trig = 1; + } + + return (falling_edge_trig); +} + +/**************************************************************************** + * Name: r_icu_irqsetfallingedge + * + * Description: + * Sets or unsets falling edge triggered + ****************************************************************************/ + +void r_icu_irqsetfallingedge (const uint8_t irq_no, const uint8_t set_f_edge) +{ + if (1 == set_f_edge) + { + ICU.IRQCR[irq_no].BYTE |= _04_ICU_IRQ_EDGE_FALLING; + } + else + { + ICU.IRQCR[irq_no].BYTE &= (uint8_t) ~_04_ICU_IRQ_EDGE_FALLING; + } +} + +/**************************************************************************** + * Name: r_icu_irqsetrisingedge + * + * Description: + * Sets or unsets rising edge triggered + ****************************************************************************/ + +void r_icu_irqsetrisingedge (const uint8_t irq_no, const uint8_t set_r_edge) +{ + if (1 == set_r_edge) + { + ICU.IRQCR[irq_no].BYTE |= _08_ICU_IRQ_EDGE_RISING; + } + else + { + ICU.IRQCR[irq_no].BYTE &= (uint8_t) ~_08_ICU_IRQ_EDGE_RISING; + } +} diff --git a/arch/renesas/src/rx65n/rx65n_icu.h b/arch/renesas/src/rx65n/rx65n_icu.h new file mode 100644 index 00000000000..65a6650087b --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_icu.h @@ -0,0 +1,481 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_icu.h + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. Gregory Nutt. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef __ARCH_RENESAS_SRC_RX65N_RX65N_ICU_H +#define __ARCH_RENESAS_SRC_RX65N_RX65N_ICU_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Interrupt Request Enable Register 08 (IER08) */ + +/* Interrupt Request Enable/Disable(IENn) */ + +#define _00_ICU_IRQ0_DISABLE (0x00u) +#define _01_ICU_IRQ0_ENABLE (0x01u) +#define _00_ICU_IRQ1_DISABLE (0x00u) +#define _02_ICU_IRQ1_ENABLE (0x02u) +#define _00_ICU_IRQ2_DISABLE (0x00u) +#define _04_ICU_IRQ2_ENABLE (0x04u) +#define _00_ICU_IRQ3_DISABLE (0x00u) +#define _08_ICU_IRQ3_ENABLE (0x08u) +#define _00_ICU_IRQ4_DISABLE (0x00u) +#define _10_ICU_IRQ4_ENABLE (0x10u) +#define _00_ICU_IRQ5_DISABLE (0x00u) +#define _20_ICU_IRQ5_ENABLE (0x20u) +#define _00_ICU_IRQ6_DISABLE (0x00u) +#define _40_ICU_IRQ6_ENABLE (0x40u) +#define _00_ICU_IRQ7_DISABLE (0x00u) +#define _80_ICU_IRQ7_ENABLE (0x80u) + +/* Interrupt Request Enable Register 09 (IER09) */ + +/* Interrupt Request Enable/Disable(IENn) */ + +#define _00_ICU_IRQ8_DISABLE (0x00u) +#define _01_ICU_IRQ8_ENABLE (0x01u) +#define _00_ICU_IRQ9_DISABLE (0x00u) +#define _02_ICU_IRQ9_ENABLE (0x02u) +#define _00_ICU_IRQ10_DISABLE (0x00u) +#define _04_ICU_IRQ10_ENABLE (0x04u) +#define _00_ICU_IRQ11_DISABLE (0x00u) +#define _08_ICU_IRQ11_ENABLE (0x08u) +#define _00_ICU_IRQ12_DISABLE (0x00u) +#define _10_ICU_IRQ12_ENABLE (0x10u) +#define _00_ICU_IRQ13_DISABLE (0x00u) +#define _20_ICU_IRQ13_ENABLE (0x20u) +#define _00_ICU_IRQ14_DISABLE (0x00u) +#define _40_ICU_IRQ14_ENABLE (0x40u) +#define _00_ICU_IRQ15_DISABLE (0x00u) +#define _80_ICU_IRQ15_ENABLE (0x80u) + +/* Interrupt Source Priority Register n (IPRn) */ + +/* Interrupt Priority Level Select (IPR[3:0]) */ + +#define _00_ICU_PRIORITY_LEVEL0 (0x00u) +#define _01_ICU_PRIORITY_LEVEL1 (0x01u) +#define _02_ICU_PRIORITY_LEVEL2 (0x02u) +#define _03_ICU_PRIORITY_LEVEL3 (0x03u) +#define _04_ICU_PRIORITY_LEVEL4 (0x04u) +#define _05_ICU_PRIORITY_LEVEL5 (0x05u) +#define _06_ICU_PRIORITY_LEVEL6 (0x06u) +#define _07_ICU_PRIORITY_LEVEL7 (0x07u) +#define _08_ICU_PRIORITY_LEVEL8 (0x08u) +#define _09_ICU_PRIORITY_LEVEL9 (0x09u) +#define _0A_ICU_PRIORITY_LEVEL10 (0x0au) +#define _0B_ICU_PRIORITY_LEVEL11 (0x0bu) +#define _0C_ICU_PRIORITY_LEVEL12 (0x0cu) +#define _0D_ICU_PRIORITY_LEVEL13 (0x0du) +#define _0E_ICU_PRIORITY_LEVEL14 (0x0eu) +#define _0F_ICU_PRIORITY_LEVEL15 (0x0fu) + +/* Fast Interrupt Set Register (FIR) */ + +/* Fast Interrupt Enable (FIEN) */ + +#define _0000_ICU_FAST_INTERRUPT_DISABLE (0x0000u) +#define _8000_ICU_FAST_INTERRUPT_ENABLE (0x8000u) + +/* IRQ Control Register i (IRQCRi) (i = 0 to 15) */ + +/* IRQ Detection Sense Select (IRQMD[1:0]) */ + +#define _00_ICU_IRQ_EDGE_LOW_LEVEL (0x00u) +#define _04_ICU_IRQ_EDGE_FALLING (0x04u) +#define _08_ICU_IRQ_EDGE_RISING (0x08u) +#define _0C_ICU_IRQ_EDGE_BOTH (0x0cu) + +/* IRQ Pin Digital Filter Enable Register 0 (IRQFLTE0) */ + +/* Digital Filter Enable (FLTEN0n) */ + +#define _00_ICU_IRQn_FILTER_DISABLE (0x00u) +#define _01_ICU_IRQ0_FILTER_ENABLE (0x01u) +#define _02_ICU_IRQ1_FILTER_ENABLE (0x02u) +#define _04_ICU_IRQ2_FILTER_ENABLE (0x04u) +#define _08_ICU_IRQ3_FILTER_ENABLE (0x08u) +#define _10_ICU_IRQ4_FILTER_ENABLE (0x10u) +#define _20_ICU_IRQ5_FILTER_ENABLE (0x20u) +#define _40_ICU_IRQ6_FILTER_ENABLE (0x40u) +#define _80_ICU_IRQ7_FILTER_ENABLE (0x80u) + +/* IRQ Pin Digital Filter Enable Register 1 (IRQFLTE1) */ + +/* Digital Filter Enable (FLTEN8~15) */ + +#define _01_ICU_IRQ8_FILTER_ENABLE (0x01u) +#define _02_ICU_IRQ9_FILTER_ENABLE (0x02u) +#define _04_ICU_IRQ10_FILTER_ENABLE (0x04u) +#define _08_ICU_IRQ11_FILTER_ENABLE (0x08u) +#define _10_ICU_IRQ12_FILTER_ENABLE (0x10u) +#define _20_ICU_IRQ13_FILTER_ENABLE (0x20u) +#define _40_ICU_IRQ14_FILTER_ENABLE (0x40u) +#define _80_ICU_IRQ15_FILTER_ENABLE (0x80u) + +/* IRQ Pin Digital Filter Setting Register 0 (IRQFLTC0) */ + +/* IRQn Digital Filter Sampling Clock (FCLKSELn) */ + +#define _0000_ICU_IRQ0_FILTER_PCLK (0x0000u) +#define _0001_ICU_IRQ0_FILTER_PCLK_8 (0x0001u) +#define _0002_ICU_IRQ0_FILTER_PCLK_32 (0x0002u) +#define _0003_ICU_IRQ0_FILTER_PCLK_64 (0x0003u) +#define _0000_ICU_IRQ1_FILTER_PCLK (0x0000u) +#define _0004_ICU_IRQ1_FILTER_PCLK_8 (0x0004u) +#define _0008_ICU_IRQ1_FILTER_PCLK_32 (0x0008u) +#define _000C_ICU_IRQ1_FILTER_PCLK_64 (0x000cu) +#define _0000_ICU_IRQ2_FILTER_PCLK (0x0000u) +#define _0010_ICU_IRQ2_FILTER_PCLK_8 (0x0010u) +#define _0020_ICU_IRQ2_FILTER_PCLK_32 (0x0020u) +#define _0030_ICU_IRQ2_FILTER_PCLK_64 (0x0030u) +#define _0000_ICU_IRQ3_FILTER_PCLK (0x0000u) +#define _0040_ICU_IRQ3_FILTER_PCLK_8 (0x0040u) +#define _0080_ICU_IRQ3_FILTER_PCLK_32 (0x0080u) +#define _00C0_ICU_IRQ3_FILTER_PCLK_64 (0x00c0u) +#define _0000_ICU_IRQ4_FILTER_PCLK (0x0000u) +#define _0100_ICU_IRQ4_FILTER_PCLK_8 (0x0100u) +#define _0200_ICU_IRQ4_FILTER_PCLK_32 (0x0200u) +#define _0300_ICU_IRQ4_FILTER_PCLK_64 (0x0300u) +#define _0000_ICU_IRQ5_FILTER_PCLK (0x0000u) +#define _0400_ICU_IRQ5_FILTER_PCLK_8 (0x0400u) +#define _0800_ICU_IRQ5_FILTER_PCLK_32 (0x0800u) +#define _0C00_ICU_IRQ5_FILTER_PCLK_64 (0x0c00u) +#define _0000_ICU_IRQ6_FILTER_PCLK (0x0000u) +#define _1000_ICU_IRQ6_FILTER_PCLK_8 (0x1000u) +#define _2000_ICU_IRQ6_FILTER_PCLK_32 (0x2000u) +#define _3000_ICU_IRQ6_FILTER_PCLK_64 (0x3000u) +#define _0000_ICU_IRQ7_FILTER_PCLK (0x0000u) +#define _4000_ICU_IRQ7_FILTER_PCLK_8 (0x4000u) +#define _8000_ICU_IRQ7_FILTER_PCLK_32 (0x8000u) +#define _C000_ICU_IRQ7_FILTER_PCLK_64 (0xc000u) + +/* IRQ Pin Digital Filter Setting Register 0 (IRQFLTC1) */ + +/* IRQn Digital Filter Sampling Clock (FCLKSEL8~15) */ + +#define _0000_ICU_IRQ8_FILTER_PCLK (0x0000u) +#define _0001_ICU_IRQ8_FILTER_PCLK_8 (0x0001u) +#define _0002_ICU_IRQ8_FILTER_PCLK_32 (0x0002u) +#define _0003_ICU_IRQ8_FILTER_PCLK_64 (0x0003u) +#define _0000_ICU_IRQ9_FILTER_PCLK (0x0000u) +#define _0004_ICU_IRQ9_FILTER_PCLK_8 (0x0004u) +#define _0008_ICU_IRQ9_FILTER_PCLK_32 (0x0008u) +#define _000C_ICU_IRQ9_FILTER_PCLK_64 (0x000cu) +#define _0000_ICU_IRQ10_FILTER_PCLK (0x0000u) +#define _0010_ICU_IRQ10_FILTER_PCLK_8 (0x0010u) +#define _0020_ICU_IRQ10_FILTER_PCLK_32 (0x0020u) +#define _0030_ICU_IRQ10_FILTER_PCLK_64 (0x0030u) +#define _0000_ICU_IRQ11_FILTER_PCLK (0x0000u) +#define _0040_ICU_IRQ11_FILTER_PCLK_8 (0x0040u) +#define _0080_ICU_IRQ11_FILTER_PCLK_32 (0x0080u) +#define _00C0_ICU_IRQ11_FILTER_PCLK_64 (0x00c0u) +#define _0000_ICU_IRQ12_FILTER_PCLK (0x0000u) +#define _0100_ICU_IRQ12_FILTER_PCLK_8 (0x0100u) +#define _0200_ICU_IRQ12_FILTER_PCLK_32 (0x0200u) +#define _0300_ICU_IRQ12_FILTER_PCLK_64 (0x0300u) +#define _0000_ICU_IRQ13_FILTER_PCLK (0x0000u) +#define _0400_ICU_IRQ13_FILTER_PCLK_8 (0x0400u) +#define _0800_ICU_IRQ13_FILTER_PCLK_32 (0x0800u) +#define _0C00_ICU_IRQ13_FILTER_PCLK_64 (0x0c00u) +#define _0000_ICU_IRQ14_FILTER_PCLK (0x0000u) +#define _1000_ICU_IRQ14_FILTER_PCLK_8 (0x1000u) +#define _2000_ICU_IRQ14_FILTER_PCLK_32 (0x2000u) +#define _3000_ICU_IRQ14_FILTER_PCLK_64 (0x3000u) +#define _0000_ICU_IRQ15_FILTER_PCLK (0x0000u) +#define _4000_ICU_IRQ15_FILTER_PCLK_8 (0x4000u) +#define _8000_ICU_IRQ15_FILTER_PCLK_32 (0x8000u) +#define _C000_ICU_IRQ15_FILTER_PCLK_64 (0xc000u) + +/* NMI Pin Interrupt Control Register (NMICR) */ + +/* NMI Detection Set (NMIMD) */ + +#define _00_ICU_NMI_EDGE_FALLING (0x00u) +#define _08_ICU_NMI_EDGE_RISING (0x08u) + +/* NMI Pin Digital Filter Setting Register (NMIFLTC) */ + +/* NMI Digital Filter Sampling Clock (NFCLKSEL[1:0]) */ + +#define _00_ICU_NMI_FILTER_PCLK (0x00u) +#define _01_ICU_NMI_FILTER_PCLK_8 (0x01u) +#define _02_ICU_NMI_FILTER_PCLK_32 (0x02u) +#define _03_ICU_NMI_FILTER_PCLK_64 (0x03u) + +/* EXDMAC Activation Peripheral Interrupt Select Register (SELEXDR) */ + +/* EXDMAC0 Activation Peripheral Interrupt Select (SELEXD0) */ + +#define _00_ICU_EXDMAC0_SLIBR144 (0x00u) +#define _01_ICU_EXDMAC0_SLIAR208 (0x01u) + +/* EXDMAC1 Activation Peripheral Interrupt Select (SELEXD1) */ + +#define _00_ICU_EXDMAC1_SLIBR145 (0x00u) +#define _02_ICU_EXDMAC1_SLIAR209 (0x02u) + +/**************************************************************************** + * Public Function Prototypes + ***************************************************************************/ + +/**************************************************************************** + * Name: r_icu_create + * + * Description: + * Initializes ICU + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_icu_create(void); + +/**************************************************************************** + * Name: r_icu_irq8_start + * + * Description: + * Enables IRQ8 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_icu_irq8_start(void); + +/**************************************************************************** + * Name: r_icu_irq8_stop + * + * Description: + * Disables IRQ8 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_icu_irq8_stop(void); + +/**************************************************************************** + * Name: r_icu_irq9_start + * + * Description: + * Enables IRQ9 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_icu_irq9_start(void); + +/**************************************************************************** + * Name: r_icu_irq9_stop + * + * Description: + * Disables IRQ9 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_icu_irq9_stop(void); + +/**************************************************************************** + * Name: r_config_icu_software_start + * + * Description: + * Enable Software Interrupt + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_config_icu_software_start(void); + +/**************************************************************************** + * Name: r_config_icu_softwareinterrupt_generate + * + * Description: + * Generate software interrupt + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_config_icu_softwareinterrupt_generate(void); + +/**************************************************************************** + * Name: r_config_icu_software_stop + * + * Description: + * Disable S/W Interrupt + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_config_icu_software_stop(void); + +/**************************************************************************** + * Name: r_config_icu_software2_start + * + * Description: + * Enable S/W Interrupt2 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_config_icu_software2_start(void); + +/**************************************************************************** + * Name: r_config_icu_softwareinterrupt2_generate + * + * Description: + * Generate software interrupt 2 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_config_icu_softwareinterrupt2_generate(void); + +/**************************************************************************** + * Name: r_config_icu_software2_stop + * + * Description: + * Disable software interrupt 2 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_config_icu_software2_stop(void); + +/**************************************************************************** + * Name: r_icu_irqisfallingedge + * + * Description: + * Detect if falling edge interrupt is triggered + * + * Input Parameters: + * irqno - irq number + * + * Returned Value: + * 1 is returned on success + * + ****************************************************************************/ + +uint8_t r_icu_irqisfallingedge(const uint8_t irq_no); + +/**************************************************************************** + * Name: r_icu_irqsetfallingedge + * + * Description: + * Sets or unsets falling edge triggered + * + * Input Parameters: + * irqno - irq number + * set_f_edge - value that has to be set for falling edge + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_icu_irqsetfallingedge(const uint8_t irq_no, const uint8_t set_f_edge); + +/**************************************************************************** + * Name: r_icu_irqsetfallingedge + * + * Description: + * Sets or unsets falling edge triggered + * + * Input Parameters: + * irqno - irq number + * set_r_edge - value that has to be set for rising edge + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_icu_irqsetrisingedge(const uint8_t irq_no, const uint8_t set_r_edge); + +#endif /* __ARCH_RENESAS_SRC_RX65N_RX65N_ICU_H *. diff --git a/arch/renesas/src/rx65n/rx65n_initialstate.c b/arch/renesas/src/rx65n/rx65n_initialstate.c new file mode 100644 index 00000000000..ce105df454c --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_initialstate.c @@ -0,0 +1,93 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_initialstate.c + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include "chip/chip.h" +#include "up_internal.h" +#include "up_arch.h" +#include "rx65n/irq.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define up_getsr() __getsr() + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_initial_state + * + * Description: + * A new thread is being started and a new TCB + * has been created. This function is called to initialize + * the processor specific portions of the new TCB. + * + * This function must setup the intial architecture registers + * and/or stack so that execution will begin at tcb->start + * on the next context switch. + * + ****************************************************************************/ + +void up_initial_state(struct tcb_s *tcb) +{ + struct xcptcontext *xcp = &tcb->xcp; + + /* Initialize the initial exception register context structure */ + + memset(xcp, 0, sizeof(struct xcptcontext)); + + xcp->regs[REG_SP] = (uint32_t)tcb->adj_stack_ptr; + xcp->regs[REG_PC] = (uint32_t)tcb->start; + + /* Enable or disable interrupts, based on user configuration */ + +#ifdef CONFIG_SUPPRESS_INTERRUPTS + xcp->regs[REG_PSW] = up_getsr() & ~0x00010000; +#else + xcp->regs[REG_PSW] = up_getsr() | 0x00010000; +#endif +} diff --git a/arch/renesas/src/rx65n/rx65n_irq.c b/arch/renesas/src/rx65n/rx65n_irq.c new file mode 100644 index 00000000000..9fac5bcb66c --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_irq.c @@ -0,0 +1,760 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_irq.c + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * Surya + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include "rx65n/iodefine.h" + +#include "up_internal.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +/* This holds a references to the current interrupt level register storage + * structure. If is non-NULL only during interrupt processing. + */ + +/* Actually a pointer to the beginning of a uint8_t array */ + +volatile uint32_t *g_current_regs; + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_irqinitialize + ****************************************************************************/ + +void up_irqinitialize(void) +{ + /* Currents_regs is non-NULL only while processing an interrupt */ + + g_current_regs = NULL; + + /* Enable interrupts */ + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + up_irq_enable(); +#endif +} + +/**************************************************************************** + * Name: up_disable_irq + * + * Description: + * On many architectures, there are three levels of interrupt enabling: (1) + * at the global level, (2) at the level of the interrupt controller, + * and (3) at the device level. In order to receive interrupts, they + * must be enabled at all three levels. + * + * This function implements disabling of the device specified by 'irq' + * at the interrupt controller level if supported by the architecture + * (up_irq_save() supports the global level, the device level is hardware + * specific). + * + ****************************************************************************/ + +void up_disable_irq(int irq) +{ + if (irq == RX65N_CMI0_IRQ) + { + ICU.IER[3].BIT.IEN4 = 0; + } + +#ifdef CONFIG_RX65N_SCI0 + if (irq == RX65N_RXI0_IRQ) + { + ICU.IER[7].BIT.IEN2 = 0; + } + + if (irq == RX65N_TXI0_IRQ) + { + ICU.IER[7].BIT.IEN3 = 0; + } + + if (irq == RX65N_ERI0_IRQ) + { + ICU.GRPBL0.BIT.IS1 = 0; + ICU.GENBL0.BIT.EN1 = 0; + } + + if (irq == RX65N_TEI0_IRQ) + { + ICU.GRPBL0.BIT.IS0 = 0; + ICU.GENBL0.BIT.EN0 = 0; + } +#endif + +#ifdef CONFIG_RX65N_SCI1 + if (irq == RX65N_RXI1_IRQ) + { + ICU.IER[7].BIT.IEN4 = 0; + } + + if (irq == RX65N_TXI1_IRQ) + { + ICU.IER[7].BIT.IEN5 = 0; + } + + if (irq == RX65N_ERI1_IRQ) + { + ICU.GRPBL0.BIT.IS3 = 0; + ICU.GENBL0.BIT.EN3 = 0; + } + + if (irq == RX65N_TEI1_IRQ) + { + ICU.GRPBL0.BIT.IS2 = 0; + ICU.GENBL0.BIT.EN2 = 0; + } +#endif + +#ifdef CONFIG_RX65N_SCI2 + if (irq == RX65N_RXI2_IRQ) + { + ICU.IER[7].BIT.IEN6 = 0; + } + + if (irq == RX65N_TXI2_IRQ) + { + ICU.IER[7].BIT.IEN7 = 0; + } + + if (irq == RX65N_ERI2_IRQ) + { + ICU.GRPBL0.BIT.IS5 = 0; + ICU.GENBL0.BIT.EN5 = 0; + } + + if (irq == RX65N_TEI2_IRQ) + { + ICU.GRPBL0.BIT.IS4 = 0; + ICU.GENBL0.BIT.EN4 = 0; + } +#endif +#ifdef CONFIG_RX65N_SCI3 + if (irq == RX65N_RXI3_IRQ) + { + ICU.IER[10].BIT.IEN0 = 0; + } + + if (irq == RX65N_TXI3_IRQ) + { + ICU.IER[10].BIT.IEN1 = 0; + } + + if (irq == RX65N_ERI3_IRQ) + { + ICU.GRPBL0.BIT.IS7 = 0; + ICU.GENBL0.BIT.EN7 = 0; + } + + if (irq == RX65N_TEI3_IRQ) + { + ICU.GRPBL0.BIT.IS6 = 0; + ICU.GENBL0.BIT.EN6 = 0; + } +#endif + +#ifdef CONFIG_RX65N_SCI4 + if (irq == RX65N_RXI4_IRQ) + { + ICU.IER[10].BIT.IEN2 = 0; + } + + if (irq == RX65N_TXI4_IRQ) + { + ICU.IER[10].BIT.IEN3 = 0; + } + + if (irq == RX65N_ERI4_IRQ) + { + ICU.GRPBL0.BIT.IS9 = 0; + ICU.GENBL0.BIT.EN9 = 0; + } + + if (irq == RX65N_TEI4_IRQ) + { + ICU.GRPBL0.BIT.IS8 = 0; + ICU.GENBL0.BIT.EN8 = 0; + } +#endif + +#ifdef CONFIG_RX65N_SCI5 + if (irq == RX65N_RXI5_IRQ) + { + ICU.IER[10].BIT.IEN4 = 0; + } + + if (irq == RX65N_TXI5_IRQ) + { + ICU.IER[10].BIT.IEN5 = 0; + } + + if (irq == RX65N_ERI5_IRQ) + { + ICU.GRPBL0.BIT.IS11 = 0; + ICU.GENBL0.BIT.EN11 = 0; + } + + if (irq == RX65N_TEI5_IRQ) + { + ICU.GRPBL0.BIT.IS10 = 0; + ICU.GENBL0.BIT.EN10 = 0; + } +#endif +#ifdef CONFIG_RX65N_SCI6 + if (irq == RX65N_RXI6_IRQ) + { + ICU.IER[10].BIT.IEN6 = 0; + } + + if (irq == RX65N_TXI6_IRQ) + { + ICU.IER[10].BIT.IEN7 = 0; + } + + if (irq == RX65N_ERI6_IRQ) + { + ICU.GRPBL0.BIT.IS13 = 0; + ICU.GENBL0.BIT.EN13 = 0; + } + + if (irq == RX65N_TEI6_IRQ) + { + ICU.GRPBL0.BIT.IS12 = 0; + ICU.GENBL0.BIT.EN12 = 0; + } +#endif + +#ifdef CONFIG_RX65N_SCI7 + if (irq == RX65N_RXI7_IRQ) + { + ICU.IER[12].BIT.IEN2 = 0; + } + + if (irq == RX65N_TXI7_IRQ) + { + ICU.IER[12].BIT.IEN3 = 0; + } + + if (irq == RX65N_ERI7_IRQ) + { + ICU.GRPBL0.BIT.IS15 = 0; + ICU.GENBL0.BIT.EN15 = 0; + } + + if (irq == RX65N_TEI7_IRQ) + { + ICU.GRPBL0.BIT.IS14 = 0; + ICU.GENBL0.BIT.EN14 = 0; + } +#endif + +#ifdef CONFIG_RX65N_SCI8 + if (irq == RX65N_RXI8_IRQ) + { + ICU.IER[12].BIT.IEN4 = 0; + } + + if (irq == RX65N_TXI8_IRQ) + { + ICU.IER[12].BIT.IEN5 = 0; + } + + if (irq == RX65N_ERI8_IRQ) + { + ICU.GRPBL1.BIT.IS25 = 0; + ICU.GENBL1.BIT.EN25 = 0; + } + + if (irq == RX65N_TEI8_IRQ) + { + ICU.GRPBL1.BIT.IS24 = 0; + ICU.GENBL1.BIT.EN24 = 0; + } +#endif + +#ifdef CONFIG_RX65N_SCI9 + if (irq == RX65N_RXI9_IRQ) + { + ICU.IER[12].BIT.IEN6 = 0; + } + + if (irq == RX65N_TXI9_IRQ) + { + ICU.IER[12].BIT.IEN7 = 0; + } + + if (irq == RX65N_ERI9_IRQ) + { + ICU.GRPBL1.BIT.IS27 = 0; + ICU.GENBL1.BIT.EN27 = 0; + } + + if (irq == RX65N_TEI9_IRQ) + { + ICU.GRPBL1.BIT.IS26 = 0; + ICU.GENBL1.BIT.EN26 = 0; + } +#endif + +#ifdef CONFIG_RX65N_SCI10 + if (irq == RX65N_RXI10_IRQ) + { + ICU.IER[10].BIT.IEN0 = 0; + } + + if (irq == RX65N_TXI10_IRQ) + { + ICU.IER[10].BIT.IEN1 = 0; + } + + if (irq == RX65N_ERI10_IRQ) + { + ICU.GRPAL0.BIT.IS9 = 0; + ICU.GENAL0.BIT.EN9 = 0; + } + + if (irq == RX65N_TEI10_IRQ) + { + ICU.GRPAL0.BIT.IS8 = 0; + ICU.GENAL0.BIT.EN8 = 0; + } +#endif + +#ifdef CONFIG_RX65N_SCI11 + if (irq == RX65N_RXI11_IRQ) + { + ICU.IER[14].BIT.IEN2 = 0; + } + + if (irq == RX65N_TXI11_IRQ) + { + ICU.IER[14].BIT.IEN3 = 0; + } + + if (irq == RX65N_ERI11_IRQ) + { + ICU.GRPAL0.BIT.IS13 = 0; + ICU.GENAL0.BIT.EN13 = 0; + } + + if (irq == RX65N_TEI11_IRQ) + { + ICU.GRPAL0.BIT.IS12 = 0; + ICU.GENAL0.BIT.EN12 = 0; + } +#endif + +#ifdef CONFIG_RX65N_SCI12 + if (irq == RX65N_RXI12_IRQ) + { + ICU.IER[14].BIT.IEN4 = 0; + } + + if (irq == RX65N_TXI12_IRQ) + { + ICU.IER[14].BIT.IEN5 = 0; + } + + if (irq == RX65N_ERI12_IRQ) + { + ICU.GRPBL0.BIT.IS17 = 0; + ICU.GENBL0.BIT.EN17 = 0; + } + + if (irq == RX65N_TEI12_IRQ) + { + ICU.GRPBL0.BIT.IS16 = 0; + ICU.GENBL0.BIT.EN16 = 0; + } +#endif + +#ifdef CONFIG_RX65N_EMAC + if (irq == RX65N_ETH_IRQ) + { + ICU.GRPAL1.BIT.IS4 = 0; + ICU.GENAL1.BIT.EN4 = 0; + } +#endif +} + +/**************************************************************************** + * Name: up_enable_irq + * + * Description: + * This function implements enabling of the device specified by 'irq' + * at the interrupt controller level if supported by the architecture + * (up_irq_save() supports the global level, the device level is hardware + * specific). + * + ****************************************************************************/ + +void up_enable_irq(int irq) +{ + if (irq == RX65N_CMI0_IRQ) + { + ICU.IER[3].BIT.IEN4 = 1; + } + + #ifdef CONFIG_RX65N_SCI0 + if (irq == RX65N_RXI0_IRQ) + { + ICU.IER[7].BIT.IEN2 = 1; + } + + if (irq == RX65N_TXI0_IRQ) + { + ICU.IER[7].BIT.IEN3 = 1; + } + + if (irq == RX65N_ERI0_IRQ) + { + ICU.GRPBL0.BIT.IS1 = 1; + ICU.GENBL0.BIT.EN1 = 1; + } + + if (irq == RX65N_TEI0_IRQ) + { + ICU.GRPBL0.BIT.IS0 = 1; + ICU.GENBL0.BIT.EN0 = 1; + } +#endif + +#ifdef CONFIG_RX65N_SCI1 + if (irq == RX65N_RXI1_IRQ) + { + ICU.IER[7].BIT.IEN4 = 1; + } + + if (irq == RX65N_TXI1_IRQ) + { + ICU.IER[7].BIT.IEN5 = 1; + } + + if (irq == RX65N_ERI1_IRQ) + { + ICU.GRPBL0.BIT.IS3 = 1; + ICU.GENBL0.BIT.EN3 = 1; + } + + if (irq == RX65N_TEI1_IRQ) + { + ICU.GRPBL0.BIT.IS2 = 1; + ICU.GENBL0.BIT.EN2 = 1; + } +#endif + +#ifdef CONFIG_RX65N_SCI2 + if (irq == RX65N_RXI2_IRQ) + { + ICU.IER[7].BIT.IEN6 = 1; + } + + if (irq == RX65N_TXI2_IRQ) + { + ICU.IER[7].BIT.IEN7 = 1; + } + + if (irq == RX65N_ERI2_IRQ) + { + ICU.GRPBL0.BIT.IS5 = 1; + ICU.GENBL0.BIT.EN5 = 1; + } + + if (irq == RX65N_TEI2_IRQ) + { + ICU.GRPBL0.BIT.IS4 = 1; + ICU.GENBL0.BIT.EN4 = 1; + } +#endif +#ifdef CONFIG_RX65N_SCI3 + if (irq == RX65N_RXI3_IRQ) + { + ICU.IER[10].BIT.IEN0 = 1; + } + + if (irq == RX65N_TXI3_IRQ) + { + ICU.IER[10].BIT.IEN1 = 1; + } + + if (irq == RX65N_ERI3_IRQ) + { + ICU.GRPBL0.BIT.IS7 = 1; + ICU.GENBL0.BIT.EN7 = 1; + } + + if (irq == RX65N_TEI3_IRQ) + { + ICU.GRPBL0.BIT.IS6 = 1; + ICU.GENBL0.BIT.EN6 = 1; + } +#endif + +#ifdef CONFIG_RX65N_SCI4 + if (irq == RX65N_RXI4_IRQ) + { + ICU.IER[10].BIT.IEN2 = 1; + } + + if (irq == RX65N_TXI4_IRQ) + { + ICU.IER[10].BIT.IEN3 = 1; + } + + if (irq == RX65N_ERI4_IRQ) + { + ICU.GRPBL0.BIT.IS9 = 1; + ICU.GENBL0.BIT.EN9 = 1; + } + + if (irq == RX65N_TEI4_IRQ) + { + ICU.GRPBL0.BIT.IS8 = 1; + ICU.GENBL0.BIT.EN8 = 1; + } +#endif + +#ifdef CONFIG_RX65N_SCI5 + if (irq == RX65N_RXI5_IRQ) + { + ICU.IER[10].BIT.IEN4 = 1; + } + + if (irq == RX65N_TXI5_IRQ) + { + ICU.IER[10].BIT.IEN5 = 1; + } + + if (irq == RX65N_ERI5_IRQ) + { + ICU.GRPBL0.BIT.IS11 = 1; + ICU.GENBL0.BIT.EN11 = 1; + } + + if (irq == RX65N_TEI5_IRQ) + { + ICU.GRPBL0.BIT.IS10 = 1; + ICU.GENBL0.BIT.EN10 = 1; + } +#endif +#ifdef CONFIG_RX65N_SCI6 + if (irq == RX65N_RXI6_IRQ) + { + ICU.IER[10].BIT.IEN6 = 1; + } + + if (irq == RX65N_TXI6_IRQ) + { + ICU.IER[10].BIT.IEN7 = 1; + } + + if (irq == RX65N_ERI6_IRQ) + { + ICU.GRPBL0.BIT.IS13 = 1; + ICU.GENBL0.BIT.EN13 = 1; + } + + if (irq == RX65N_TEI6_IRQ) + { + ICU.GRPBL0.BIT.IS12 = 1; + ICU.GENBL0.BIT.EN12 = 1; + } +#endif + +#ifdef CONFIG_RX65N_SCI7 + if (irq == RX65N_RXI7_IRQ) + { + ICU.IER[12].BIT.IEN2 = 1; + } + + if (irq == RX65N_TXI7_IRQ) + { + ICU.IER[12].BIT.IEN3 = 1; + } + + if (irq == RX65N_ERI7_IRQ) + { + ICU.GRPBL0.BIT.IS15 = 1; + ICU.GENBL0.BIT.EN15 = 1; + } + + if (irq == RX65N_TEI7_IRQ) + { + ICU.GRPBL0.BIT.IS14 = 1; + ICU.GENBL0.BIT.EN14 = 1; + } +#endif + +#ifdef CONFIG_RX65N_SCI8 + if (irq == RX65N_RXI8_IRQ) + { + ICU.IER[12].BIT.IEN4 = 1; + } + + if (irq == RX65N_TXI8_IRQ) + { + ICU.IER[12].BIT.IEN5 = 1; + } + + if (irq == RX65N_ERI8_IRQ) + { + ICU.GRPBL1.BIT.IS25 = 1; + ICU.GENBL1.BIT.EN25 = 1; + } + + if (irq == RX65N_TEI8_IRQ) + { + ICU.GRPBL1.BIT.IS24 = 1; + ICU.GENBL1.BIT.EN24 = 1; + } +#endif + +#ifdef CONFIG_RX65N_SCI9 + if (irq == RX65N_RXI9_IRQ) + { + ICU.IER[12].BIT.IEN6 = 1; + } + + if (irq == RX65N_TXI9_IRQ) + { + ICU.IER[12].BIT.IEN7 = 1; + } + + if (irq == RX65N_ERI9_IRQ) + { + ICU.GRPBL1.BIT.IS27 = 1; + ICU.GENBL1.BIT.EN27 = 1; + } + + if (irq == RX65N_TEI9_IRQ) + { + ICU.GRPBL1.BIT.IS26 = 1; + ICU.GENBL1.BIT.EN26 = 1; + } +#endif + +#ifdef CONFIG_RX65N_SCI10 + if (irq == RX65N_RXI10_IRQ) + { + ICU.IER[10].BIT.IEN0 = 1; + } + + if (irq == RX65N_TXI10_IRQ) + { + ICU.IER[10].BIT.IEN1 = 1; + } + + if (irq == RX65N_ERI10_IRQ) + { + ICU.GRPAL0.BIT.IS9 = 1; + ICU.GENAL0.BIT.EN9 = 1; + } + + if (irq == RX65N_TEI10_IRQ) + { + ICU.GRPAL0.BIT.IS8 = 1; + ICU.GENAL0.BIT.EN8 = 1; + } +#endif + +#ifdef CONFIG_RX65N_SCI11 + if (irq == RX65N_RXI11_IRQ) + { + ICU.IER[14].BIT.IEN2 = 1; + } + + if (irq == RX65N_TXI11_IRQ) + { + ICU.IER[14].BIT.IEN3 = 1; + } + + if (irq == RX65N_ERI11_IRQ) + { + ICU.GRPAL0.BIT.IS13 = 1; + ICU.GENAL0.BIT.EN13 = 1; + } + + if (irq == RX65N_TEI11_IRQ) + { + ICU.GRPAL0.BIT.IS12 = 1; + ICU.GENAL0.BIT.EN12 = 1; + } +#endif + +#ifdef CONFIG_RX65N_SCI12 + if (irq == RX65N_RXI12_IRQ) + { + ICU.IER[14].BIT.IEN4 = 1; + } + + if (irq == RX65N_TXI12_IRQ) + { + ICU.IER[14].BIT.IEN5 = 1; + } + + if (irq == RX65N_ERI12_IRQ) + { + ICU.GRPBL0.BIT.IS17 = 1; + ICU.GENBL0.BIT.EN17 = 1; + } + + if (irq == RX65N_TEI12_IRQ) + { + ICU.GRPBL0.BIT.IS16 = 1; + ICU.GENBL0.BIT.EN16 = 1; + } +#endif + +#ifdef CONFIG_RX65N_EMAC + if (irq == RX65N_ETH_IRQ) + { + ICU.GRPAL1.BIT.IS4 = 1; + ICU.GENAL1.BIT.EN4 = 1; + } +#endif +} diff --git a/arch/renesas/src/rx65n/rx65n_lowputc.c b/arch/renesas/src/rx65n/rx65n_lowputc.c new file mode 100644 index 00000000000..47f9aed79c5 --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_lowputc.c @@ -0,0 +1,265 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_lowputc.c + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include + +#include "chip.h" +#include "up_internal.h" +#include "up_arch.h" +#include "rx65n_definitions.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Configuration **********************************************************/ + +/* Is there a serial console? */ + +#if defined(CONFIG_SCI0_SERIAL_CONSOLE) && defined(CONFIG_RX65N_SCI0) +# define HAVE_CONSOLE 1 +# undef CONFIG_SCI1_SERIAL_CONSOLE +#elif defined(CONFIG_SCI2_SERIAL_CONSOLE) && defined(CONFIG_RX65N_SCI2) +# define HAVE_CONSOLE 1 +# undef CONFIG_SCI0_SERIAL_CONSOLE +#else +# if defined(CONFIG_SCI0_SERIAL_CONSOLE) || defined(CONFIG_SCI2_SERIAL_CONSOLE) +# error "Serial console selected, but corresponding SCI not enabled" +# endif +# undef HAVE_CONSOLE +#endif + +/* Select UART parameters for the selected console */ + +#if defined(CONFIG_SCI0_SERIAL_CONSOLE) +# define RX_SCI_BASE RX65N_SCI0_BASE +# define RX_SCI_BAUD CONFIG_SCI0_BAUD +# define RX_SCI_BITS CONFIG_SCI0_BITS +# define RX_SCI_PARITY CONFIG_SCI0_PARITY +# define RX_SCI_2STOP CONFIG_SCI0_2STOP +#elif defined(CONFIG_SCI1_SERIAL_CONSOLE) +# define RX_SCI_BASE RX65N_SCI1_BASE +# define RX_SCI_BAUD CONFIG_SCI1_BAUD +# define RX_SCI_BITS CONFIG_SCI1_BITS +# define RX_SCI_PARITY CONFIG_SCI1_PARITY +# define RX_SCI_2STOP CONFIG_SCI1_2STOP +#elif defined(CONFIG_SCI2_SERIAL_CONSOLE) +# define RX_SCI_BASE RX65N_SCI2_BASE +# define RX_SCI_BAUD CONFIG_SCI2_BAUD +# define RX_SCI_BITS CONFIG_SCI2_BITS +# define RX_SCI_PARITY CONFIG_SCI2_PARITY +# define RX_SCI_2STOP CONFIG_SCI2_2STOP +#elif defined(CONFIG_SCI3_SERIAL_CONSOLE) +# define RX_SCI_BASE RX65N_SCI3_BASE +# define RX_SCI_BAUD CONFIG_SCI3_BAUD +# define RX_SCI_BITS CONFIG_SCI3_BITS +# define RX_SCI_PARITY CONFIG_SCI3_PARITY +# define RX_SCI_2STOP CONFIG_SCI3_2STOP +#elif defined(CONFIG_SCI4_SERIAL_CONSOLE) +# define RX_SCI_BASE RX65N_SCI4_BASE +# define RX_SCI_BAUD CONFIG_SCI4_BAUD +# define RX_SCI_BITS CONFIG_SCI4_BITS +# define RX_SCI_PARITY CONFIG_SCI4_PARITY +# define RX_SCI_2STOP CONFIG_SCI4_2STOP +#elif defined(CONFIG_SCI5_SERIAL_CONSOLE) +# define RX_SCI_BASE RX65N_SCI5_BASE +# define RX_SCI_BAUD CONFIG_SCI5_BAUD +# define RX_SCI_BITS CONFIG_SCI5_BITS +# define RX_SCI_PARITY CONFIG_SCI5_PARITY +# define RX_SCI_2STOP CONFIG_SCI5_2STOP +#elif defined(CONFIG_SCI6_SERIAL_CONSOLE) +# define RX_SCI_BASE RX65N_SCI6_BASE +# define RX_SCI_BAUD CONFIG_SCI6_BAUD +# define RX_SCI_BITS CONFIG_SCI6_BITS +# define RX_SCI_PARITY CONFIG_SCI6_PARITY +# define RX_SCI_2STOP CONFIG_SCI6_2STOP +#elif defined(CONFIG_SCI7_SERIAL_CONSOLE) +# define RX_SCI_BASE RX65N_SCI7_BASE +# define RX_SCI_BAUD CONFIG_SCI7_BAUD +# define RX_SCI_BITS CONFIG_SCI7_BITS +# define RX_SCI_PARITY CONFIG_SCI7_PARITY +# define RX_SCI_2STOP CONFIG_SCI7_2STOP +#elif defined(CONFIG_SCI8_SERIAL_CONSOLE) +# define RX_SCI_BASE RX65N_SCI8_BASE +# define RX_SCI_BAUD CONFIG_SCI8_BAUD +# define RX_SCI_BITS CONFIG_SCI8_BITS +# define RX_SCI_PARITY CONFIG_SCI8_PARITY +# define RX_SCI_2STOP CONFIG_SCI8_2STOP +#else +# error "No CONFIG_SCIn_SERIAL_CONSOLE Setting" +#endif + +/* Get mode setting */ + +#if RX_SCI_BITS == 7 +# define RX_SMR_MODE RX_SCISMR_CHR +#elif RX_SCI_BITS == 8 +# define RX_SMR_MODE (0) +#else +# define RX_SMR_MODE (0) +#endif + +#if RX_SCI_PARITY == 0 +# define RX_SMR_PARITY (0) +#elif RX_SCI_PARITY == 1 +# define RX_SMR_PARITY (RX_SCISMR_PE|RX_SCISMR_OE) +#elif RX_SCI_PARITY == 2 +# define RX_SMR_PARITY RX_SCISMR_PE +#else +# define RX_SMR_PARITY (0) +#endif + +#if RX_SCI_2STOP != 0 +# define RX_SMR_STOP RX_SCISMR_STOP +#else +# define RX_SMR_STOP (0) +#endif + +/* The full SMR setting also includes internal clocking with no divisor, + * aysnchronous operation and multiprocessor disabled: + */ + +#define RX_SMR_VALUE (RX_SMR_MODE|RX_SMR_PARITY|RX_SMR_STOP) + +/* Clocking ***************************************************************/ + +#define RX_DIVISOR (8 * RX_SCI_BAUD) +#define RX_BRR ((RX_PCLKB / RX_DIVISOR) - 1) + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_txready + * + * Description: + * Return TRUE of the Transmit Data Register is empty + * + ****************************************************************************/ + +#ifdef HAVE_CONSOLE +static inline int up_txready(void) +{ + /* Check the TDRE bit in the SSR. 1=TDR is empty */ + + return ((getreg8(RX_SCI_BASE + RX_SCI_SSR_OFFSET) & RX_SCISSR_TDRE) != 0); +} +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_lowputc + * + * Description: + * Output one byte on the serial console + * + ****************************************************************************/ + +void up_lowputc(char ch) +{ +#ifdef HAVE_CONSOLE + uint8_t ssr; + + /* Wait until the TDR is avaible */ + + while (!up_txready()); + + /* Write the data to the TDR */ + + putreg8(ch, RX_SCI_BASE + RX_SCI_TDR_OFFSET); + + /* Clear the TDRE bit in the SSR */ + + ssr = getreg8(RX_SCI_BASE + RX_SCI_SSR_OFFSET); + ssr &= ~RX_SCISSR_TDRE; + putreg8(ssr, RX_SCI_BASE + RX_SCI_SSR_OFFSET); +#endif +} + +/**************************************************************************** + * Name: up_lowsetup + * + * Description: + * This performs basic initialization of the UART used for the serial + * console. Its purpose is to get the console output availabe as soon + * as possible. + * + ****************************************************************************/ + +void up_lowsetup(void) +{ +#if defined(HAVE_CONSOLE) && !defined(CONFIG_SUPPRESS_SCI_CONFIG) + uint8_t scr; + + /* Disable the transmitter and receiver */ + + scr = getreg8(RX_SCI_BASE + RX_SCI_SCR_OFFSET); + scr &= ~(RX_SCISCR_TE | RX_SCISCR_RE); + putreg8(scr, RX_SCI_BASE + RX_SCI_SCR_OFFSET); + + /* Set communication to be asynchronous with the configured number of data + * bits, parity, and stop bits. Use the internal clock (undivided) + */ + + putreg8(RX_SMR_VALUE, RX_SCI_BASE + RX_SCI_SMR_OFFSET); + + /* Set the baud based on the configured console baud and configured + * system clock. + */ + + putreg8(RX_BRR, RX_SCI_BASE + RX_SCI_BRR_OFFSET); + + /* Select the internal clock source as input */ + + scr &= ~RX_SCISCR_CKEMASK; + putreg8(scr, RX_SCI_BASE + RX_SCI_SCR_OFFSET); + + /* Then enable the transmitter and reciever */ + + scr |= (RX_SCISCR_TE | RX_SCISCR_RE); + putreg8(scr, RX_SCI_BASE + RX_SCI_SCR_OFFSET); +#endif +} diff --git a/arch/renesas/src/rx65n/rx65n_macrodriver.h b/arch/renesas/src/rx65n/rx65n_macrodriver.h new file mode 100644 index 00000000000..27fc7146a8d --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_macrodriver.h @@ -0,0 +1,100 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_macrodriver.h + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +#ifndef __ARCH_RENESAS_SRC_RX65N_STATUS_H +#define __ARCH_RENESAS_SRC_RX65N_STATUS_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#include "rx65n/iodefine.h" + +#ifndef TRUE +#define TRUE (1) +#else +#if (1 != TRUE) +#error "TRUE is not defined by 1." +#endif +#endif + +#ifndef FALSE +#define FALSE (0) +#else +#if (0 != FALSE) +#error "FALSE is not defined by 0." +#endif +#endif + +#ifndef __TYPEDEF__ + +/* Status list definition */ + +#define MD_STATUSBASE (0x00U) +#define MD_OK (MD_STATUSBASE + 0x00U) /* register setting OK */ +#define MD_SPT (MD_STATUSBASE + 0x01U) /* IIC stop */ +#define MD_NACK (MD_STATUSBASE + 0x02U) /* IIC no ACK */ +#define MD_BUSY1 (MD_STATUSBASE + 0x03U) /* busy 1 */ +#define MD_BUSY2 (MD_STATUSBASE + 0x04U) /* busy 2 */ + +/* Error list definition */ + +#define MD_ERRORBASE (0x80U) +#define MD_ERROR (MD_ERRORBASE + 0x00U) /* error */ + +/* error argument input error */ + +#define MD_ARGERROR (MD_ERRORBASE + 0x01U) +#define MD_ERROR1 (MD_ERRORBASE + 0x02U) /* error 1 */ +#define MD_ERROR2 (MD_ERRORBASE + 0x03U) /* error 2 */ +#define MD_ERROR3 (MD_ERRORBASE + 0x04U) /* error 3 */ +#define MD_ERROR4 (MD_ERRORBASE + 0x05U) /* error 4 */ +#define MD_ERROR5 (MD_ERRORBASE + 0x06U) /* error 5 */ + +#define nop() asm("nop;") +#define brk() asm("brk;") +#define wait() asm("wait;") +#endif + +#ifndef __TYPEDEF__ +#ifndef _STDINT_H + typedef unsigned char uint8_t; + typedef unsigned short uint16_t; +#endif + typedef unsigned short MD_STATUS; +#define __TYPEDEF__ +#endif + +#endif /* __ARCH_RENESAS_SRC_RX65N_STATUS_H */ diff --git a/arch/renesas/src/rx65n/rx65n_port.c b/arch/renesas/src/rx65n/rx65n_port.c new file mode 100644 index 00000000000..97dfdd23ad5 --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_port.c @@ -0,0 +1,358 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_port.c + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * Surya + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "rx65n_macrodriver.h" +#include "rx65n_port.h" +#include "arch/board/board.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: r_port_create + * + * Description: + * Port Initialization + ****************************************************************************/ + +void r_port_create(void) +{ +#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) + + /* LED_PORTINIT(0); */ + + PORT0.PODR.BYTE = _04_PM2_OUTPUT_1 | _08_PM3_OUTPUT_1 | _20_PM5_OUTPUT_1; + PORT5.PODR.BYTE = _40_PM6_OUTPUT_1; + PORT7.PODR.BYTE = _08_PM3_OUTPUT_1; + PORT9.PODR.BYTE = _08_PM3_OUTPUT_1; + PORTJ.PODR.BYTE = _20_PM5_OUTPUT_1; + PORT0.DSCR.BYTE = _00_PM2_HIDRV_OFF; + PORT0.DSCR2.BYTE = _00_PM2_HISPEED_OFF; + PORT5.DSCR.BYTE = _20_PM5_HIDRV_ON | _00_PM6_HIDRV_OFF; + PORT5.DSCR2.BYTE = _00_PM5_HISPEED_OFF | _00_PM6_HISPEED_OFF; + PORT7.DSCR2.BYTE = _00_PM3_HISPEED_OFF; + PORT9.DSCR.BYTE = _00_PM3_HIDRV_OFF; + PORT9.DSCR2.BYTE = _00_PM3_HISPEED_OFF; + PORT0.PMR.BYTE = 0x00u; + PORT0.PDR.BYTE = _04_PM2_MODE_OUTPUT | _08_PM3_MODE_OUTPUT | + _20_PM5_MODE_OUTPUT | _50_PDR0_DEFAULT; + PORT5.PMR.BYTE = 0x00u; + PORT5.PDR.BYTE = _20_PM5_MODE_OUTPUT | _40_PM6_MODE_OUTPUT | + _80_PDR5_DEFAULT; + PORT7.PMR.BYTE = 0x00u; + PORT7.PDR.BYTE = _08_PM3_MODE_OUTPUT; + PORT9.PMR.BYTE = 0x00u; + PORT9.PDR.BYTE = _08_PM3_MODE_OUTPUT | _F0_PDR9_DEFAULT; + PORTJ.PMR.BYTE = 0x00u; + PORTJ.PDR.BYTE = _20_PM5_MODE_OUTPUT | _D7_PDRJ_DEFAULT; +#elif defined (CONFIG_ARCH_BOARD_RX65N_RSK2MB) + + /* LED_PORTINIT(0); */ + + PORT0.PODR.BYTE = _04_PM2_OUTPUT_1 | _08_PM3_OUTPUT_1 | _20_PM5_OUTPUT_1; + PORT5.PODR.BYTE = _40_PM6_OUTPUT_1; + PORT7.PODR.BYTE = _08_PM3_OUTPUT_1; + PORT9.PODR.BYTE = _08_PM3_OUTPUT_1; + PORTJ.PODR.BYTE = _20_PM5_OUTPUT_1; + PORT0.DSCR.BYTE = _00_PM2_HIDRV_OFF; + PORT0.DSCR2.BYTE = _00_PM2_HISPEED_OFF; + PORT5.DSCR.BYTE = _20_PM5_HIDRV_ON | _00_PM6_HIDRV_OFF; + PORT5.DSCR2.BYTE = _00_PM5_HISPEED_OFF | _00_PM6_HISPEED_OFF; + PORT7.DSCR2.BYTE = _00_PM3_HISPEED_OFF; + PORT9.DSCR.BYTE = _00_PM3_HIDRV_OFF; + PORT9.DSCR2.BYTE = _00_PM3_HISPEED_OFF; + PORT0.PMR.BYTE = 0x00u; + PORT0.PDR.BYTE = _04_PM2_MODE_OUTPUT | _08_PM3_MODE_OUTPUT | + _20_PM5_MODE_OUTPUT | _50_PDR0_DEFAULT; + PORT5.PMR.BYTE = 0x00u; + PORT5.PDR.BYTE = _20_PM5_MODE_OUTPUT | _40_PM6_MODE_OUTPUT | + _80_PDR5_DEFAULT; + PORT7.PMR.BYTE = 0x00u; + PORT7.PDR.BYTE = _08_PM3_MODE_OUTPUT; + PORT9.PMR.BYTE = 0x00u; + PORT9.PDR.BYTE = _08_PM3_MODE_OUTPUT | _F0_PDR9_DEFAULT; + PORTJ.PMR.BYTE = 0x00u; + PORTJ.PDR.BYTE = _20_PM5_MODE_OUTPUT | _D7_PDRJ_DEFAULT; +#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE) + LED_PORTINIT(0); + + /* SCI0(UART) direction */ + + PORT2.PODR.BIT.B2 = 0; PORT2.PMR.BIT.B2 = 0; PORT2.PDR.BIT.B2 = 1; + + /* SCI2(UART) direction */ + + PORT1.PODR.BIT.B4 = 0; PORT1.PMR.BIT.B4 = 0; PORT1.PDR.BIT.B4 = 1; + + /* SCI5(UART) direction */ + + PORTC.PODR.BIT.B4 = 0; PORTC.PMR.BIT.B4 = 0; PORTC.PDR.BIT.B4 = 1; + + /* SCI6(UART) direction */ + + PORT3.PODR.BIT.B4 = 0; PORT3.PMR.BIT.B4 = 0; PORT3.PDR.BIT.B4 = 1; + + /* SCI8(RS485) direction */ + + PORTC.PODR.BIT.B5 = 0; PORTC.PMR.BIT.B5 = 0; PORTC.PDR.BIT.B5 = 1; +#else +# error "No Selection for PORT definition in rx65n_port.c" +#endif +} +#ifdef CONFIG_RX65N_EMAC0 +void r_ether_port_configuration(void) +{ + /* Port configuration */ + + /* Enable LEDs. */ + + /* Start with LEDs OFF */ + + PORT7.PODR.BIT.B3 = 1; + PORTG.PODR.BIT.B7 = 1; + PORTG.PODR.BIT.B6 = 1; + PORTG.PODR.BIT.B5 = 1; + + /* SET LED pins as outputs */ + + PORT7.PDR.BIT.B3 = 1; + PORTG.PDR.BIT.B7 = 1; + PORTG.PDR.BIT.B6 = 1; + PORTG.PDR.BIT.B5 = 1; + + /* Enable Switches */ + + /* Set pins as Inputs */ + + PORT0.PDR.BIT.B3 = 0; + PORT0.PDR.BIT.B5 = 0; + PORT0.PDR.BIT.B7 = 0; + + /* Set port mode registers for switches. */ + + PORT0.PMR.BIT.B3 = 0; + PORT0.PMR.BIT.B5 = 0; + PORT0.PMR.BIT.B7 = 0; +} + +void r_ether_pheriperal_enable(void) +{ +#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) + + /* TODO */ + +#elif defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB) + + /* Set ET0_TX_CLK pin */ + + MPC.PC4PFS.BYTE = 0x11u; + PORTC.PMR.BIT.B4 = 1u; + + /* Set ET0_RX_CLK pin */ + + MPC.P76PFS.BYTE = 0x11u; + PORT7.PMR.BIT.B6 = 1u; + + /* Set ET0_TX_EN pin */ + + MPC.P80PFS.BYTE = 0x11u; + PORT8.PMR.BIT.BT0 = 1u; + + /* Set ET0_ETXD3 pin */ + + MPC.PC6PFS.BYTE = 0x11u; + PORTC.PMR.BIT.B6 = 1u; + + /* Set ET0_ETXD2 pin */ + + MPC.PC5PFS.BYTE = 0x11u; + PORTC.PMR.BIT.B5 = 1u; + + /* Set ET0_ETXD1 pin */ + + MPC.P82PFS.BYTE = 0x11u; + PORT8.PMR.BIT.B2 = 1u; + + /* Set ET0_ETXD0 pin */ + + MPC.P81PFS.BYTE = 0x11u; + PORT8.PMR.BIT.B1 = 1u; + + /* Set ET0_TX_ER pin */ + + MPC.PC3PFS.BYTE = 0x11u; + PORTC.PMR.BIT.B3 = 1u; + + /* Set ET0_RX_DV pin */ + + MPC.PC2PFS.BYTE = 0x11u; + PORTC.PMR.BIT.B2 = 1u; + + /* Set ET0_ERXD3 pin */ + + MPC.PC0PFS.BYTE = 0x11u; + PORTC.PMR.BIT.BT0 = 1u; + + /* Set ET0_ERXD2 pin */ + + MPC.PC1PFS.BYTE = 0x11u; + PORTC.PMR.BIT.B1 = 1u; + + /* Set ET0_ERXD1 pin */ + + MPC.P74PFS.BYTE = 0x11u; + PORT7.PMR.BIT.B4 = 1u; + + /* Set ET0_ERXD0 pin */ + + MPC.P75PFS.BYTE = 0x11u; + PORT7.PMR.BIT.B5 = 1u; + + /* Set ET0_RX_ER pin */ + + MPC.P77PFS.BYTE = 0x11u; + PORT7.PMR.BIT.B7 = 1u; + + /* Set ET0_CRS pin */ + + MPC.P83PFS.BYTE = 0x11u; + PORT8.PMR.BIT.B3 = 1u; + + /* Set ET0_COL pin */ + + MPC.PC7PFS.BYTE = 0x11u; + PORTC.PMR.BIT.B7 = 1u; + + /* Set ET0_MDC pin */ + + MPC.P72PFS.BYTE = 0x11u; + PORT7.PMR.BIT.B2 = 1u; + + /* Set ET0_MDIO pin */ + + MPC.P71PFS.BYTE = 0x11u; + PORT7.PMR.BIT.B1 = 1u; + + /* Set ET0_LINKSTA pin */ + + MPC.P54PFS.BYTE = 0x11u; + PORT5.PMR.BIT.B4 = 1u; + + /* Set ET0_LINKSTA pin */ + + MPC.P34PFS.BYTE = 0x11u; + PORT3.PMR.BIT.B4 = 1u; + +#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE) + + /* Set ET0_MDC(PA4_ET_MDC) pin */ + + MPC.PA4PFS.BYTE = 0x11u; + PORTA.PMR.BIT.B4 = 1u; + + /* Set ET0_MDIO(PA3_ET_MDIO) pin */ + + MPC.PA3PFS.BYTE = 0x11u; + PORTA.PMR.BIT.B3 = 1u; + + /* Set REF50CK0 (PB2_ET_CLK) pin */ + + MPC.PB2PFS.BYTE = 0x12u; + PORTB.PMR.BIT.B2 = 1u; + + /* Set RMII0_CRS_DV(PB7_ET_CRS) pin */ + + MPC.PB7PFS.BYTE = 0x12u; + PORTB.PMR.BIT.B7 = 1u; + + /* Set RMII0_RXD0(PB1_ET_RXD0) pin */ + + MPC.PB1PFS.BYTE = 0x12u; + PORTB.PMR.BIT.B1 = 1u; + + /* Set RMII0_RXD1(PB0_ET_RXD1) pin */ + + MPC.PB0PFS.BYTE = 0x12u; + PORTB.PMR.BIT.BT0 = 1u; + + /* Set RMII0_RX_ER(PB3_ET_RXER) pin */ + + MPC.PB3PFS.BYTE = 0x12u; + PORTB.PMR.BIT.B3 = 1u; + + /* Set RMII0_ETXD0(PB5_ET_TXD0) pin */ + + MPC.PB5PFS.BYTE = 0x12u; + PORTB.PMR.BIT.B5 = 1u; + + /* Set RMII0_ETXD1(PB6_ET_TXD1) pin */ + + MPC.PB6PFS.BYTE = 0x12u; + PORTB.PMR.BIT.B6 = 1u; + + /* Set RMII0_TXD_EN(PB4_ET_TXEN) pin */ + + MPC.PB4PFS.BYTE = 0x12u; + PORTB.PMR.BIT.B4 = 1u; + + /* Set RXD2 pin */ + + MPC.P52PFS.BYTE = 0x0au; + PORT5.PMR.BIT.B2 = 1u; + + /* Set TXD2 pin */ + + PORT5.PODR.BYTE |= 0x01u; + MPC.P50PFS.BYTE = 0x0au; + PORT5.PDR.BYTE |= 0x01u; + + /* Set ET0_LINKSTA(PA5_ET_LINK) pin */ + + MPC.PA5PFS.BYTE = 0x11u; + PORTA.PMR.BIT.B5 = 1u; + + /* Set ETHER reset(PA6_ET_RST) pin */ + + MPC.PA6PFS.BYTE = 0x12u; + PORTA.PMR.BIT.B6 = 1u; +#endif +} +#endif diff --git a/arch/renesas/src/rx65n/rx65n_port.h b/arch/renesas/src/rx65n/rx65n_port.h new file mode 100644 index 00000000000..9b5b63708b0 --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_port.h @@ -0,0 +1,338 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_port.h + * + * Copyright (C) 2009 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef __ARCH_RENESAS_SRC_RX65N_PORT_H +#define __ARCH_RENESAS_SRC_RX65N_PORT_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Port Direction Register (PDR) */ + +/* Pmn Direction Control (B7 - B0) */ + +#define _00_PM0_MODE_NOT_USED (0x00u) /* PM0 not used */ +#define _00_PM0_MODE_INPUT (0x00u) /* PM0 as input */ +#define _01_PM0_MODE_OUTPUT (0x01u) /* PM0 as output */ +#define _00_PM1_MODE_NOT_USED (0x00u) /* PM1 not used */ +#define _00_PM1_MODE_INPUT (0x00u) /* PM1 as input */ +#define _02_PM1_MODE_OUTPUT (0x02u) /* PM1 as output */ +#define _00_PM2_MODE_NOT_USED (0x00u) /* PM2 not used */ +#define _00_PM2_MODE_INPUT (0x00u) /* PM2 as input */ +#define _04_PM2_MODE_OUTPUT (0x04u) /* PM2 as output */ +#define _00_PM3_MODE_NOT_USED (0x00u) /* PM3 not used */ +#define _00_PM3_MODE_INPUT (0x00u) /* PM3 as input */ +#define _08_PM3_MODE_OUTPUT (0x08u) /* PM3 as output */ +#define _00_PM4_MODE_NOT_USED (0x00u) /* PM4 not used */ +#define _00_PM4_MODE_INPUT (0x00u) /* PM4 as input */ +#define _10_PM4_MODE_OUTPUT (0x10u) /* PM4 as output */ +#define _00_PM5_MODE_NOT_USED (0x00u) /* PM5 not used */ +#define _00_PM5_MODE_INPUT (0x00u) /* PM5 as input */ +#define _20_PM5_MODE_OUTPUT (0x20u) /* PM5 as output */ +#define _00_PM6_MODE_NOT_USED (0x00u) /* PM6 not used */ +#define _00_PM6_MODE_INPUT (0x00u) /* PM6 as input */ +#define _40_PM6_MODE_OUTPUT (0x40u) /* PM6 as output */ +#define _00_PM7_MODE_NOT_USED (0x00u) /* PM7 not used */ +#define _00_PM7_MODE_INPUT (0x00u) /* PM7 as input */ +#define _80_PM7_MODE_OUTPUT (0x80u) /* PM7 as output */ +#define _50_PDR0_DEFAULT (0x50u) /* PDR0 default value */ +#define _03_PDR1_DEFAULT (0x03u) /* PDR1 default value */ +#define _80_PDR5_DEFAULT (0x80u) /* PDR5 default value */ +#define _30_PDR8_DEFAULT (0x30u) /* PDR8 default value */ +#define _F0_PDR9_DEFAULT (0xf0u) /* PDR9 default value */ +#define _DF_PDRF_DEFAULT (0xdfu) /* PDRF default value */ +#define _D7_PDRJ_DEFAULT (0xd7u) /* PDRJ default value */ + +/* Port Output Data Register (PODR) */ + +/* Pmn Output Data Store (B7 - B0) */ + +#define _00_PM0_OUTPUT_0 (0x00u) /* output low at B0 */ +#define _01_PM0_OUTPUT_1 (0x01u) /* output high at B0 */ +#define _00_PM1_OUTPUT_0 (0x00u) /* output low at B1 */ +#define _02_PM1_OUTPUT_1 (0x02u) /* output high at B1 */ +#define _00_PM2_OUTPUT_0 (0x00u) /* output low at B2 */ +#define _04_PM2_OUTPUT_1 (0x04u) /* output high at B2 */ +#define _00_PM3_OUTPUT_0 (0x00u) /* output low at B3 */ +#define _08_PM3_OUTPUT_1 (0x08u) /* output high at B3 */ +#define _00_PM4_OUTPUT_0 (0x00u) /* output low at B4 */ +#define _10_PM4_OUTPUT_1 (0x10u) /* output high at B4 */ +#define _00_PM5_OUTPUT_0 (0x00u) /* output low at B5 */ +#define _20_PM5_OUTPUT_1 (0x20u) /* output high at B5 */ +#define _00_PM6_OUTPUT_0 (0x00u) /* output low at B6 */ +#define _40_PM6_OUTPUT_1 (0x40u) /* output high at B6 */ +#define _00_PM7_OUTPUT_0 (0x00u) /* output low at B7 */ +#define _80_PM7_OUTPUT_1 (0x80u) /* output high at B7 */ + +/* Open Drain Control Register 0 (ODR0) */ + +/* Pmn Output Type Select (Pm0 to Pm3) */ + +#define _00_PM0_CMOS_OUTPUT (0x00u) /* CMOS output */ +#define _01_PM0_NCH_OPEN_DRAIN (0x01u) /* NMOS open-drain output */ +#define _00_PM1_CMOS_OUTPUT (0x00u) /* CMOS output */ +#define _04_PM1_NCH_OPEN_DRAIN (0x04u) /* NMOS open-drain output */ +#define _08_PM1_PCH_OPEN_DRAIN (0x08u) /* PMOS open-drain output,for PE1 only */ +#define _00_PM2_CMOS_OUTPUT (0x00u) /* CMOS output */ +#define _10_PM2_NCH_OPEN_DRAIN (0x10u) /* NMOS open-drain output */ +#define _00_PM3_CMOS_OUTPUT (0x00u) /* CMOS output */ +#define _40_PM3_NCH_OPEN_DRAIN (0x40u) /* NMOS open-drain output */ + +/* Open Drain Control Register 1 (ODR1) */ + +/* Pmn Output Type Select (Pm4 to Pm7) */ + +#define _00_PM4_CMOS_OUTPUT (0x00u) /* CMOS output */ +#define _01_PM4_NCH_OPEN_DRAIN (0x01u) /* NMOS open-drain output */ +#define _00_PM5_CMOS_OUTPUT (0x00u) /* CMOS output */ +#define _04_PM5_NCH_OPEN_DRAIN (0x04u) /* NMOS open-drain output */ +#define _00_PM6_CMOS_OUTPUT (0x00u) /* CMOS output */ +#define _10_PM6_NCH_OPEN_DRAIN (0x10u) /* NMOS open-drain output */ +#define _00_PM7_CMOS_OUTPUT (0x00u) /* CMOS output */ +#define _40_PM7_NCH_OPEN_DRAIN (0x40u) /* NMOS open-drain output */ + +/* Pull-Up Control Register (PCR) */ + +/* Pmn Input Pull-Up Resistor Control (B7 - B0) */ + +/* PM0 pull-up resistor not connected */ + +#define _00_PM0_PULLUP_OFF (0x00u) + +/* PM0 pull-up resistor connected */ + +#define _01_PM0_PULLUP_ON (0x01u) + +/* PM1 pull-up resistor not connected */ + +#define _00_PM1_PULLUP_OFF (0x00u) + +/* PM1 pull-up resistor connected */ + +#define _02_PM1_PULLUP_ON (0x02u) + +/* PM2 Pull-up resistor not connected */ + +#define _00_PM2_PULLUP_OFF (0x00u) + +/* PM2 pull-up resistor connected */ + +#define _04_PM2_PULLUP_ON (0x04u) + +/* PM3 pull-up resistor not connected */ + +#define _00_PM3_PULLUP_OFF (0x00u) + +/* PM3 pull-up resistor connected */ + +#define _08_PM3_PULLUP_ON (0x08u) + +/* PM4 pull-up resistor not connected */ + +#define _00_PM4_PULLUP_OFF (0x00u) + +/* PM4 pull-up resistor connected */ + +#define _10_PM4_PULLUP_ON (0x10u) + +/* PM5 pull-up resistor not connected */ + +#define _00_PM5_PULLUP_OFF (0x00u) + +/* PM5 pull-up resistor connected */ + +#define _20_PM5_PULLUP_ON (0x20u) + +/* PM6 pull-up resistor not connected */ + +#define _00_PM6_PULLUP_OFF (0x00u) + +/* PM6 pull-up resistor connected */ + +#define _40_PM6_PULLUP_ON (0x40u) + +/* PM7 pull-up resistor not connected */ + +#define _00_PM7_PULLUP_OFF (0x00u) + +/* Pm7 pull-up resistor connected */ + +#define _80_PM7_PULLUP_ON (0x80u) + +/* Drive Capacity Control Register (DSCR) */ + +/* Pmn Drive Capacity Control (B7 - B0) */ + +#define _00_PM0_HIDRV_OFF (0x00u) /* PM0 Normal drive output */ +#define _01_PM0_HIDRV_ON (0x01u) /* PM0 High-drive output */ +#define _00_PM1_HIDRV_OFF (0x00u) /* PM1 Normal drive output */ +#define _02_PM1_HIDRV_ON (0x02u) /* PM1 High-drive output */ +#define _00_PM2_HIDRV_OFF (0x00u) /* PM2 Normal drive output */ +#define _04_PM2_HIDRV_ON (0x04u) /* PM2 High-drive output */ +#define _00_PM3_HIDRV_OFF (0x00u) /* PM3 Normal drive output */ +#define _08_PM3_HIDRV_ON (0x08u) /* PM3 High-drive output */ +#define _00_PM4_HIDRV_OFF (0x00u) /* PM4 Normal drive output */ +#define _10_PM4_HIDRV_ON (0x10u) /* PM4 High-drive output */ +#define _00_PM5_HIDRV_OFF (0x00u) /* PM5 Normal drive output */ +#define _20_PM5_HIDRV_ON (0x20u) /* PM5 High-drive output */ +#define _00_PM6_HIDRV_OFF (0x00u) /* PM6 Normal drive output */ +#define _40_PM6_HIDRV_ON (0x40u) /* PM6 High-drive output */ +#define _00_PM7_HIDRV_OFF (0x00u) /* PM7 Normal drive output */ +#define _80_PM7_HIDRV_ON (0x80u) /* PM7 High-drive output */ + +/* Drive Capacity Control Register 2 (DSCR2) */ + +/* Pmn Drive Capacity Control (B7 - B0) */ + +/* PM0 Normal drive/high-drive output */ + +#define _00_PM0_HISPEED_OFF (0x00u) + +/* PM0 High-speed interface high-drive output */ + +#define _01_PM0_HISPEED_ON (0x01u) + +/* PM1 Normal drive/high-drive output */ + +#define _00_PM1_HISPEED_OFF (0x00u) + +/* PM1 High-speed interface high-drive output */ + +#define _02_PM1_HISPEED_ON (0x02u) + +/* PM2 Normal drive/high-drive output */ + +#define _00_PM2_HISPEED_OFF (0x00u) + +/* PM2 High-speed interface high-drive output */ + +#define _04_PM2_HISPEED_ON (0x04u) + +/* PM3 Normal drive/high-drive output */ + +#define _00_PM3_HISPEED_OFF (0x00u) + +/* PM3 High-speed interface high-drive output */ + +#define _08_PM3_HISPEED_ON (0x08u) + +/* PM4 Normal drive/high-drive output */ + +#define _00_PM4_HISPEED_OFF (0x00u) + +/* PM4 High-speed interface high-drive output */ + +#define _10_PM4_HISPEED_ON (0x10u) + +/* PM5 Normal drive/high-drive output */ + +#define _00_PM5_HISPEED_OFF (0x00u) + +/* PM5 High-speed interface high-drive output */ + +#define _20_PM5_HISPEED_ON (0x20u) + +/* PM6 Normal drive/high-drive output */ + +#define _00_PM6_HISPEED_OFF (0x00u) + +/* PM6 High-speed interface high-drive output */ + +#define _40_PM6_HISPEED_ON (0x40u) + +/* PM7 Normal drive/high-drive output */ + +#define _00_PM7_HISPEED_OFF (0x00u) + +/* PM7 High-speed interface high-drive output */ + +#define _80_PM7_HISPEED_ON (0x80u) + +/**************************************************************************** + * Public Function Prototypes + ***************************************************************************/ + +/**************************************************************************** + * Name: r_port_create + * + * Description: + * Initializes Ports of rx65n + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_port_create(void); + +/**************************************************************************** + * Name: r_ether_port_configuration + * + * Description: + * Initializes Ethernet Ports of rx65n + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +#ifdef CONFIG_RX65N_EMAC0 +void r_ether_port_configuration(void); + +/**************************************************************************** + * Name: r_ether_pheriperal_enable + * + * Description: + * Ethernet Pheriperal enabling + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_ether_pheriperal_enable(void); +#endif + +#endif /* __ARCH_RENESAS_SRC_RX65N_PORT_H */ diff --git a/arch/renesas/src/rx65n/rx65n_schedulesigaction.c b/arch/renesas/src/rx65n/rx65n_schedulesigaction.c new file mode 100644 index 00000000000..0675aa9d19d --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_schedulesigaction.c @@ -0,0 +1,180 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_schedulesigaction.c + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include + +#include "sched/sched.h" +#include "up_internal.h" +#include "up_arch.h" + +/**************************************************************************** + * Public Funictions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_schedule_sigaction + * + * Description: + * This function is called by the OS when one or more + * signal handling actions have been queued for execution. + * The architecture specific code must configure things so + * that the 'igdeliver' callback is executed on the thread + * specified by 'tcb' as soon as possible. + * + * This function may be called from interrupt handling logic. + * + * This operation should not cause the task to be unblocked + * nor should it cause any immediate execution of sigdeliver. + * Typically, a few cases need to be considered: + * + * (1) This function may be called from an interrupt handler + * During interrupt processing, all xcptcontext structures + * should be valid for all tasks. That structure should + * be modified to invoke sigdeliver() either on return + * from (this) interrupt or on some subsequent context + * switch to the recipient task. + * (2) If not in an interrupt handler and the tcb is NOT + * the currently executing task, then again just modify + * the saved xcptcontext structure for the recipient + * task so it will invoke sigdeliver when that task is + * later resumed. + * (3) If not in an interrupt handler and the tcb IS the + * currently executing task -- just call the signal + * handler now. + * + ****************************************************************************/ + +void up_schedule_sigaction(struct tcb_s *tcb, sig_deliver_t sigdeliver) +{ + irqstate_t flags; + + sinfo("tcb=0x%p sigdeliver=0x%p\n", tcb, sigdeliver); + + /* Make sure that interrupts are disabled */ + + flags = enter_critical_section(); + + /* Refuse to handle nested signal actions */ + + if (!tcb->xcp.sigdeliver) + { + /* First, handle some special cases when the signal is + * being delivered to the currently executing task. + */ + + sinfo("rtcb=0x%p g_current_regs=0x%p\n", this_task(), g_current_regs); + + if (tcb == this_task()) + { + /* CASE 1: We are not in an interrupt handler and + * a task is signalling itself for some reason. + */ + + if (!g_current_regs) + { + /* In this case just deliver the signal now. */ + + sigdeliver(tcb); + } + + /* CASE 2: We are in an interrupt handler AND the + * interrupted task is the same as the one that + * must receive the signal, then we will have to modify + * the return state as well as the state in the TCB. + */ + + else + { + /* Save the return PC and SR and one scratch register + * These will be restored by the signal trampoline after + * the signals have been delivered. + */ + + tcb->xcp.sigdeliver = sigdeliver; + tcb->xcp.saved_pc = g_current_regs[REG_PC]; + + /* Then set up to vector to the trampoline with interrupts + * disabled + */ + + g_current_regs[REG_PC] = (uint32_t)up_sigdeliver; + + /* And make sure that the saved context in the TCB + * is the same as the interrupt return context. + */ + + up_copystate(tcb->xcp.regs, (uint32_t *)&g_current_regs); + } + } + + /* Otherwise, we are (1) signaling a task is not running + * from an interrupt handler or (2) we are not in an + * interrupt handler and the running task is signalling + * some non-running task. + */ + + else + { + /* Save the return PC and SR and one scratch register + * These will be restored by the signal trampoline after + * the signals have been delivered. + */ + + tcb->xcp.sigdeliver = sigdeliver; + tcb->xcp.saved_pc = tcb->xcp.regs[REG_PC]; + tcb->xcp.saved_sr = tcb->xcp.regs[REG_PSW]; + + /* Then set up to vector to the trampoline with interrupts + * disabled + */ + + tcb->xcp.regs[REG_PC] = (uint32_t)up_sigdeliver; + tcb->xcp.regs[REG_PSW] |= 0x00030000; + } + } + + leave_critical_section(flags); +} diff --git a/arch/renesas/src/rx65n/rx65n_sci.c b/arch/renesas/src/rx65n/rx65n_sci.c new file mode 100644 index 00000000000..5a92dc86ba6 --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_sci.c @@ -0,0 +1,2460 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_sci.c + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include +#include "sys/types.h" +#include "rx65n_macrodriver.h" +#include "rx65n_sci.h" +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" +#include "rx65n_definitions.h" + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI0 +/* SCI0 transmit buffer address */ + +volatile uint8_t *gp_sci0_tx_address; + +/* SCI0 receive buffer address */ + +volatile uint8_t *gp_sci0_rx_address; + +/* SCI0 transmit data number */ + +volatile uint16_t g_sci0_tx_count; + +/* SCI0 receive data number */ + +volatile uint16_t g_sci0_rx_count; + +/* SCI0 receive data length */ + +volatile uint16_t g_sci0_rx_length; +#endif + +#ifdef CONFIG_RX65N_SCI1 +/* SCI1 transmit buffer address */ + +volatile uint8_t *gp_sci1_tx_address; + +/* SCI1 receive buffer address */ + +volatile uint8_t *gp_sci1_rx_address; + +/* SCI1 transmit data number */ + +volatile uint16_t g_sci1_tx_count; + +/* SCI1 receive data number */ + +volatile uint16_t g_sci1_rx_count; + +/* SCI1 receive data length */ + +volatile uint16_t g_sci1_rx_length; +#endif + +#ifdef CONFIG_RX65N_SCI2 +/* SCI2 transmit buffer address */ + +volatile uint8_t *gp_sci2_tx_address; + +/* SCI2 receive buffer address */ + +volatile uint8_t *gp_sci2_rx_address; + +/* SCI2 transmit data number */ + +volatile uint16_t g_sci2_tx_count; + +/* SCI2 receive data number */ + +volatile uint16_t g_sci2_rx_count; + +/* SCI2 receive data length */ + +volatile uint16_t g_sci2_rx_length; +#endif + +#ifdef CONFIG_RX65N_SCI3 +/* SCI3 transmit buffer address */ + +volatile uint8_t *gp_sci3_tx_address; + +/* SCI3 receive buffer address */ + +volatile uint8_t *gp_sci3_rx_address; + +/* SCI3 transmit data number */ + +volatile uint16_t g_sci3_tx_count; + +/* SCI3 receive data number */ + +volatile uint16_t g_sci3_rx_count; + +/* SCI3 receive data length */ + +volatile uint16_t g_sci3_rx_length; +#endif + +#ifdef CONFIG_RX65N_SCI4 +/* SCI4 transmit buffer address */ + +volatile uint8_t *gp_sci4_tx_address; + +/* SCI4 receive buffer address */ + +volatile uint8_t *gp_sci4_rx_address; + +/* SCI4 transmit data number */ + +volatile uint16_t g_sci4_tx_count; + +/* SCI4 receive data number */ + +volatile uint16_t g_sci4_rx_count; + +/* SCI4 receive data length */ + +volatile uint16_t g_sci4_rx_length; +#endif + +#ifdef CONFIG_RX65N_SCI5 +/* SCI5 transmit buffer address */ + +volatile uint8_t *gp_sci5_tx_address; + +/* SCI5 receive buffer address */ + +volatile uint8_t *gp_sci5_rx_address; + +/* SCI5 transmit data number */ + +volatile uint16_t g_sci5_tx_count; + +/* SCI5 receive data number */ + +volatile uint16_t g_sci5_rx_count; + +/* SCI5 receive data length */ + +volatile uint16_t g_sci5_rx_length; +#endif + +#ifdef CONFIG_RX65N_SCI6 + +/* SCI6 transmit buffer address */ + +volatile uint8_t *gp_sci6_tx_address; + +/* SCI6 receive buffer address */ + +volatile uint8_t *gp_sci6_rx_address; + +/* SCI6 transmit data number */ + +volatile uint16_t g_sci6_tx_count; + +/* SCI6 receive data number */ + +volatile uint16_t g_sci6_rx_count; + +/* SCI6 receive data length */ + +volatile uint16_t g_sci6_rx_length; +#endif + +#ifdef CONFIG_RX65N_SCI7 + +/* SCI7 transmit buffer address */ + +volatile uint8_t *gp_sci7_tx_address; + +/* SCI7 receive buffer address */ + +volatile uint8_t *gp_sci7_rx_address; + +/* SCI7 transmit data number */ + +volatile uint16_t g_sci7_tx_count; + +/* SCI7 receive data number */ + +volatile uint16_t g_sci7_rx_count; + +/* SCI7 receive data length */ + +volatile uint16_t g_sci7_rx_length; +#endif + +#ifdef CONFIG_RX65N_SCI8 +/* SCI8 transmit buffer address */ + +volatile uint8_t *gp_sci8_tx_address; + +/* SCI8 receive buffer address */ + +volatile uint8_t *gp_sci8_rx_address; + +/* SCI8 transmit data number */ + +volatile uint16_t g_sci8_tx_count; + +/* SCI8 receive data number */ + +volatile uint16_t g_sci8_rx_count; + +/* SCI8 receive data length */ + +volatile uint16_t g_sci8_rx_length; +#endif + +#ifdef CONFIG_RX65N_SCI9 +/* SCI9 transmit buffer address */ + +volatile uint8_t *gp_sci9_tx_address; + +/* SCI9 receive buffer address */ + +volatile uint8_t *gp_sci9_rx_address; + +/* SCI9 transmit data number */ + +volatile uint16_t g_sci9_tx_count; + +/* SCI9 receive data number */ + +volatile uint16_t g_sci9_rx_count; + +/* SCI9 receive data length */ + +volatile uint16_t g_sci9_rx_length; +#endif + +#ifdef CONFIG_RX65N_SCI10 +/* SCI10 transmit buffer address */ + +volatile uint8_t *gp_sci10_tx_address; + +/* SCI10 receive buffer address */ + +volatile uint8_t *gp_sci10_rx_address; + +/* SCI10 transmit data number */ + +volatile uint16_t g_sci10_tx_count; + +/* SCI10 receive data number */ + +volatile uint16_t g_sci10_rx_count; + +/* SCI10 receive data length */ + +volatile uint16_t g_sci10_rx_length; +#endif + +#ifdef CONFIG_RX65N_SCI11 +/* SCI11 transmit buffer address */ + +volatile uint8_t *gp_sci11_tx_address; + +/* SCI11 receive buffer address */ + +volatile uint8_t *gp_sci11_rx_address; + +/* SCI11 transmit data number */ + +volatile uint16_t g_sci11_tx_count; + +/* SCI11 receive data number */ + +volatile uint16_t g_sci11_rx_count; + +/* SCI11 receive data length */ + +volatile uint16_t g_sci11_rx_length; +#endif + +#ifdef CONFIG_RX65N_SCI12 +/* SCI12 transmit buffer address */ + +volatile uint8_t *gp_sci12_tx_address; + +/* SCI12 receive buffer address */ + +volatile uint8_t *gp_sci12_rx_address; + +/* SCI12 transmit data number */ + +volatile uint16_t g_sci12_tx_count; + +/* SCI12 receive data number */ + +volatile uint16_t g_sci12_rx_count; + +/* SCI12 receive data length */ + +volatile uint16_t g_sci12_rx_length; +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: rx_mpc_enable + * + * Description: + * Enable writing to registers + ****************************************************************************/ + +static inline void rx_mpc_enable(void) +{ +/* Enable writing to registers related to operating modes, + * LPC, CGC and software reset + */ + + SYSTEM.PRCR.WORD = 0xa50bu; + + /* Enable writing to MPC pin function control registers */ + + MPC.PWPR.BIT.B0WI = 0u; + MPC.PWPR.BIT.PFSWE = 1u; +} + +/**************************************************************************** + * Name: rx_mpc_disable + * + * Description: + * Disable writing to registers + ****************************************************************************/ + +static inline void rx_mpc_disable(void) +{ + /* Disable writing to MPC pin function control registers */ + + MPC.PWPR.BIT.PFSWE = 0u; + MPC.PWPR.BIT.B0WI = 1u; + + /* Enable protection */ + + SYSTEM.PRCR.WORD = 0xa500u; +} + +=/**************************************************************************** + * Name: sci0_init_port + * + * Description: + * SCI0 Initialization + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI0 +static inline void sci0_init_port(void) +{ +#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE + /* Set RXD0 pin (P21) */ + + MPC.P21PFS.BYTE = 0x0au; + PORT2.PMR.BIT.B1 = 1u; + + /* Set TXD0 pin (P20) */ + + PORT2.PODR.BIT.BT0 = 1u; + MPC.P20PFS.BYTE = 0x0au; + PORT2.PDR.BIT.BT0 = 1u; + PORT2.PMR.BIT.BT0 = 1u; +#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */ +} +#endif + +/**************************************************************************** + * Name: sci1_init_port + * + * Description: + * SCI1 Initialization + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI1 +static inline void sci1_init_port(void) +{ +#ifdef CONFIG_ARCH_BOARD_RX65N_RSK2MB + /* Set RXD1 pin (PF2) */ + + MPC.PF2PFS.BYTE = 0x0au; + PORTF.PMR.BIT.B2 = 1u; + + /* Set TXD1 pin (PF1) */ + + PORTF.PODR.BIT.B1 = 1u; + MPC.PF1PFS.BYTE = 0x0au; + PORTF.PDR.BIT.B1 = 1u; + PORTF.PMR.BIT.B1 = 1u; + +#endif /* CONFIG_ARCH_BOARD_RX65N_RSK2MB */ + +#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE + /* Set RXD1 pin (P30) */ + + MPC.P30PFS.BYTE = 0x0au; + PORT3.PMR.BIT.BT0 = 1u; + + /* Set TXD1 pin (P26) */ + + PORT2.PODR.BIT.B6 = 1u; + MPC.P26PFS.BYTE = 0x0au; + PORT2.PDR.BIT.B6 = 1u; + PORT2.PMR.BIT.B6 = 1u; +#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */ +} +#endif + +/**************************************************************************** + * Name: sci2_init_port + * + * Description: + * SCI2 Initialization + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI2 +static inline void sci2_init_port(void) +{ +#ifdef CONFIG_ARCH_BOARD_RX65N_RSK1MB + /* Set RXD2 pin (P52) */ + + MPC.P52PFS.BYTE = 0x0au; + PORT5.PMR.BIT.B2 = 1u; + + /* Set TXD2 pin (P50) */ + + PORT5.PODR.BIT.BT0 = 1u; + MPC.P50PFS.BYTE = 0x0au; + PORT5.PDR.BIT.BT0 = 1u; + PORT5.PMR.BIT.BT0 = 1u; +#endif /* CONFIG_ARCH_BOARD_RX65N_RSK1MB */ + +#ifdef CONFIG_ARCH_BOARD_RX65N_RSK2MB + /* Set RXD2 pin (P52) */ + + MPC.P52PFS.BYTE = 0x0au; + PORT5.PMR.BIT.B2 = 1u; + + /* Set TXD2 pin (P50) */ + + PORT5.PODR.BIT.BT0 = 1u; + MPC.P50PFS.BYTE = 0x0au; + PORT5.PDR.BIT.BT0 = 1u; + PORT5.PMR.BIT.BT0 = 1u; +#endif /* CONFIG_ARCH_BOARD_RX65N_RSK2MB */ + +#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE + /* Set RXD2 pin (P12) */ + + MPC.P12PFS.BYTE = 0x0au; + PORT1.PMR.BIT.B2 = 1u; + + /* Set TXD2 pin (P13) */ + + PORT1.PODR.BIT.B3 = 1u; + MPC.P13PFS.BYTE = 0x0au; + PORT1.PDR.BIT.B3 = 1u; + PORT1.PMR.BIT.B3 = 1u; +#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */ +} +#endif + +/**************************************************************************** + * Name: sci3_init_port + * + * Description: + * SCI3 Initialization + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI3 +static inline void sci3_init_port(void) +{ + /* Set RXD3 pin (PXX) + * MPC.PXXPFS.BYTE = 0x0au; + * PORTX.PMR.BIT.BX = 1u; + * Set TXD3 pin (PXX) + * PORTX.PODR.BIT.BX = 1u; + * MPC.PXXPFS.BYTE = 0x0au; + * PORTX.PDR.BIT.BX = 1u; + * PORTX.PMR.BIT.BX = 1u; + */ + +#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE + /* Set RXD2 pin (P25) */ + + MPC.P25PFS.BYTE = 0x0au; + PORT2.PMR.BIT.B5 = 1u; + + /* Set TXD2 pin (P23) */ + + PORT2.PODR.BIT.B3 = 1u; + MPC.P23PFS.BYTE = 0x0au; + PORT2.PDR.BIT.B3 = 1u; + PORT2.PMR.BIT.B3 = 1u; +#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */ +} +#endif + +/**************************************************************************** + * Name: sci4_init_port + * + * Description: + * SCI4 Initialization + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI4 +static inline void sci4_init_port(void) +{ + /* Set RXD4 pin (PXX) + * MPC.PXXPFS.BYTE = 0x0au; + * PORTX.PMR.BIT.BX = 1u; + * Set TXD4 pin (PXX) + * PORTX.PODR.BIT.BX = 1u; + * MPC.PXXPFS.BYTE = 0x0au; + * PORTX.PDR.BIT.BX = 1u; + * PORTX.PMR.BIT.BX = 1u; + */ +} +#endif + +/**************************************************************************** + * Name: sci5_init_port + * + * Description: + * SCI5 Initialization + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI5 +static inline void sci5_init_port(void) +{ +#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE + + /* Set RXD3 pin (PC2) */ + + MPC.PC2PFS.BYTE = 0x0au; + PORTC.PMR.BIT.B2 = 1u; + + /* Set TXD3 pin (PC3) */ + + PORTC.PODR.BIT.B3 = 1u; + MPC.PC3PFS.BYTE = 0x0au; + PORTC.PDR.BIT.B3 = 1u; + PORTC.PMR.BIT.B3 = 1u; +#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */ +} +#endif + +/**************************************************************************** + * Name: sci6_init_port + * + * Description: + * SCI6 Initialization + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI6 +static inline void sci6_init_port(void) +{ +#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE + + /* Set RXD6 pin (P33) */ + + MPC.P33PFS.BYTE = 0x0au; + PORT3.PMR.BIT.B3 = 1u; + + /* Set TXD6 pin (P32) */ + + PORT3.PODR.BIT.B2 = 1u; + MPC.P32PFS.BYTE = 0x0au; + PORT3.PDR.BIT.B2 = 1u; + PORT3.PMR.BIT.B2 = 1u; +#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */ +} +#endif + +/**************************************************************************** + * Name: sci7_init_port + * + * Description: + * SCI7 Initialization + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI7 +static inline void sci7_init_port(void) +{ + /* Set RXD7 pin (PXX) + * MPC.PXXPFS.BYTE = 0x0au; + * PORTX.PMR.BIT.BX = 1u; + * Set TXD7 pin (PXX) + * PORTX.PODR.BIT.BX = 1u; + * MPC.PXXPFS.BYTE = 0x0au; + * PORTX.PDR.BIT.BX = 1u; + * PORTX.PMR.BIT.BX = 1u; + */ +} +#endif + +/**************************************************************************** + * Name: sci8_init_port + * + * Description: + * SCI8 Initialization + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI8 +static inline void sci8_init_port(void) +{ +#ifdef CONFIG_ARCH_BOARD_RX65N_RSK2MB + /* Set RXD8 pin (PJ1) */ + + MPC.PJ1PFS.BYTE = 0x0au; + PORTJ.PMR.BIT.B1 = 1u; + + /* Set TXD8 pin (PJ2) */ + + PORTJ.PODR.BIT.B2 = 1u; + MPC.PJ2PFS.BYTE = 0x0au; + PORTJ.PDR.BIT.B2 = 1u; + PORTJ.PMR.BIT.B2 = 1u; +#endif /* CONFIG_ARCH_BOARD_RX65N_RSK2MB */ + +#ifdef CONFIG_ARCH_BOARD_RX65N_GRROSE + /* Set RXD8 pin (PC6) */ + + MPC.PC6PFS.BYTE = 0x0au; + PORTC.PMR.BIT.B6 = 1u; + + /* Set TXD8 pin (PC7) */ + + PORTC.PODR.BIT.B7 = 1u; + MPC.PC7PFS.BYTE = 0x0au; + PORTC.PDR.BIT.B7 = 1u; + PORTC.PMR.BIT.B7 = 1u; +#endif /* CONFIG_ARCH_BOARD_RX65N_GRROSE */ +} +#endif + +/**************************************************************************** + * Name: sci9_init_port + * + * Description: + * SCI9 Initialization + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI9 +static inline void sci9_init_port(void) +{ + /* Set RXD9 pin (PXX) + * MPC.PXXPFS.BYTE = 0x0au; + * PORTX.PMR.BIT.BX = 1u; + * Set TXD9 pin (PXX) + * PORTX.PODR.BIT.BX = 1u; + * MPC.PXXPFS.BYTE = 0x0au; + * PORTX.PDR.BIT.BX = 1u; + * PORTX.PMR.BIT.BX = 1u; + */ +} +#endif + +/**************************************************************************** + * Name: sci10_init_port + * + * Description: + * SCI10 Initialization + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI10 +static inline void sci10_init_port(void) +{ + /* Set RXD10 pin (PXX) + * MPC.PXXPFS.BYTE = 0x0au; + * PORTX.PMR.BIT.BX = 1u; + * Set TXD10 pin (PXX) + * PORTX.PODR.BIT.BX = 1u; + * MPC.PXXPFS.BYTE = 0x0au; + * PORTX.PDR.BIT.BX = 1u; + * PORTX.PMR.BIT.BX = 1u; + */ +} +#endif + +/**************************************************************************** + * Name: sci11_init_port + * + * Description: + * SCI11 Initialization + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI11 +static inline void sci11_init_port(void) +{ + /* Set RXD11 pin (PXX) + * MPC.PXXPFS.BYTE = 0x0au; + * PORTX.PMR.BIT.BX = 1u; + * Set TXD11 pin (PXX) + * PORTX.PODR.BIT.BX = 1u; + * MPC.PXXPFS.BYTE = 0x0au; + * PORTX.PDR.BIT.BX = 1u; + * PORTX.PMR.BIT.BX = 1u; + */ +} +#endif + +/**************************************************************************** + * Name: sci12_init_port + * + * Description: + * SCI12 Initialization + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI12 +static inline void sci12_init_port(void) +{ +#ifdef CONFIG_ARCH_BOARD_RX65N_RSK2MB + + /* Set RXD12 pin */ + + MPC.PE2PFS.BYTE = 0x0cu; + PORTE.PMR.BYTE |= 0x04u; + + /* Set TXD12 pin */ + + PORTE.PODR.BYTE |= 0x02u; + MPC.PE1PFS.BYTE = 0x0cu; + PORTE.PDR.BYTE |= 0x02u; +#endif + + /* Set RXD12 pin (PXX) + * MPC.PXXPFS.BYTE = 0x0au; + * PORTX.PMR.BIT.BX = 1u; + * Set TXD12 pin (PXX) + * PORTX.PODR.BIT.BX = 1u; + * MPC.PXXPFS.BYTE = 0x0au; + * PORTX.PDR.BIT.BX = 1u; + * PORTX.PMR.BIT.BX = 1u; + */ +} +#endif + +/**************************************************************************** + * Name: r_sci0_create + * + * Description: + * SCI0 Initialization + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI0 +void r_sci0_create(void) +{ + rx_mpc_enable(); + MSTP(SCI0) = 0u; /* Cancel SCI0 module stop state */ + IPR(SCI0, RXI0) = 15; /* Set interrupt priority */ + IPR(SCI0, TXI0) = 15; /* Set interrupt priority */ + SCI0.SCR.BYTE = 0u; /* Clear the control register */ + + /* Set clock enable */ + + SCI0.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED; + SCI0.SIMR1.BIT.IICM = 0u; /* Clear SIMR1.IICM bit */ + SCI0.SPMR.BIT.CKPH = 0u; /* Clear SPMR.CKPH bit */ + SCI0.SPMR.BIT.CKPOL = 0u; /* Clear SPMR.CKPOL bit */ + + /* Set control registers */ + + SCI0.SPMR.BYTE = _00_SCI_RTS; + SCI0.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | + _00_SCI_PARITY_DISABLE | _00_SCI_DATA_LENGTH_8 | + _00_SCI_MULTI_PROCESSOR_DISABLE | + _00_SCI_ASYNCHRONOUS_OR_I2C_MODE; + SCI0.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_LSB_FIRST | + _10_SCI_DATA_LENGTH_8_OR_7 | _62_SCI_SCMR_DEFAULT; + + SCI0.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | + _20_SCI_NOISE_FILTER_ENABLE | _10_SCI_8_BASE_CLOCK | + _40_SCI_BAUDRATE_DOUBLE | + _04_SCI_BIT_MODULATION_ENABLE; + SCI0.SNFR.BYTE = _00_SCI_ASYNC_DIV_1; + + /* Set SCI0 pin */ + + sci0_init_port(); + rx_mpc_disable(); +} + +/**************************************************************************** + * Name: r_sci0_start + * + * Description: + * Starts SCI0 + ****************************************************************************/ + +void r_sci0_start(void) +{ + IR(SCI0, TXI0) = 0u; /* Clear interrupt flag */ + IR(SCI0, RXI0) = 0u; /* Clear interrupt flag */ + IEN(SCI0, TXI0) = 1u; /* Enable SCI interrupt */ + IEN(SCI0, RXI0) = 1u; /* Enable SCI interrupt */ + ICU.GENBL0.BIT.EN0 = 1u; + ICU.GENBL0.BIT.EN1 = 1u; +} + +/**************************************************************************** + * Name: r_sci0_stop + * + * Description: + * Stops SCI0 + ****************************************************************************/ + +void r_sci0_stop(void) +{ + SCI0.SCR.BIT.TE = 0u; /* Disable serial transmit */ + SCI0.SCR.BIT.RE = 0u; /* Disable serial receive */ + SCI0.SCR.BIT.TIE = 0u; /* disable TXI interrupt */ + SCI0.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */ + IEN(SCI0, TXI0) = 0u; + ICU.GENBL0.BIT.EN0 = 0u; + IR(SCI0, TXI0) = 0u; + IEN(SCI0, RXI0) = 0u; + ICU.GENBL0.BIT.EN1 = 0u; + IR(SCI0, RXI0) = 0u; +} + +/**************************************************************************** + * Name: r_sci0_serial_receive + * + * Description: + * Receives SCI0 + ****************************************************************************/ + +MD_STATUS r_sci0_serial_receive(uint8_t * const rx_buf, uint16_t rx_num) +{ + if (1u > rx_num) + { + return MD_ARGERROR; + } + + g_sci0_rx_count = 0u; + g_sci0_rx_length = rx_num; + gp_sci0_rx_address = rx_buf; + SCI0.SCR.BIT.RIE = 1u; + SCI0.SCR.BIT.RE = 1u; + return OK; +} + +/**************************************************************************** + * Name: r_sci0_serial_send + * + * Description: + * Transmits SCI0 data + ****************************************************************************/ + +MD_STATUS r_sci0_serial_send(uint8_t * const tx_buf, uint16_t tx_num) +{ + if (1u > tx_num) + { + return MD_ARGERROR; + } + + gp_sci0_tx_address = tx_buf; + g_sci0_tx_count = tx_num; + + /* Set TXD0 pin */ + + SCI0.SCR.BIT.TIE = 1u; + SCI0.SCR.BIT.TE = 1u; + return OK; +} +#endif + +/**************************************************************************** + * Name: r_sci1_create + * + * Description: + * Initializes SCI1 data + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI1 +void r_sci1_create(void) +{ + rx_mpc_enable(); + MSTP(SCI1) = 0u; /* Cancel SCI1 module stop state */ + IPR(SCI1, RXI1) = 15; /* Set interrupt priority */ + IPR(SCI1, TXI1) = 15; /* Set interrupt priority */ + SCI1.SCR.BYTE = 0u; /* Clear the control register */ + + /* Set clock enable */ + + SCI1.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED; + SCI1.SIMR1.BIT.IICM = 0u; /* Clear SIMR1.IICM bit */ + SCI1.SPMR.BIT.CKPH = 0u; /* Clear SPMR.CKPH bit */ + SCI1.SPMR.BIT.CKPOL = 0u; /* Clear SPMR.CKPOL bit */ + + /* Set control registers */ + + SCI1.SPMR.BYTE = _00_SCI_RTS; + SCI1.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | + _00_SCI_PARITY_DISABLE | _00_SCI_DATA_LENGTH_8 | + _00_SCI_MULTI_PROCESSOR_DISABLE | + _00_SCI_ASYNCHRONOUS_OR_I2C_MODE; + SCI1.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_LSB_FIRST | + _10_SCI_DATA_LENGTH_8_OR_7 | _62_SCI_SCMR_DEFAULT; + SCI1.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | + _20_SCI_NOISE_FILTER_ENABLE | + _10_SCI_8_BASE_CLOCK | _40_SCI_BAUDRATE_DOUBLE | + _04_SCI_BIT_MODULATION_ENABLE; + SCI1.SNFR.BYTE = _00_SCI_ASYNC_DIV_1; + + /* Set SCI1 pin */ + + sci1_init_port(); + rx_mpc_disable(); +} + +/**************************************************************************** + * Name: r_sci1_start + * + * Description: + * Starts SCI1 + ****************************************************************************/ + +void r_sci1_start(void) +{ + IR(SCI1, TXI1) = 0u; /* Clear interrupt flag */ + IR(SCI1, RXI1) = 0u; /* Clear interrupt flag */ + IEN(SCI1, TXI1) = 1u; /* Enable SCI interrupt */ + IEN(SCI1, RXI1) = 1u; /* Enable SCI interrupt */ + ICU.GENBL0.BIT.EN2 = 1u; + ICU.GENBL0.BIT.EN3 = 1u; +} + +/**************************************************************************** + * Name: r_sci1_stop + * + * Description: + * Stops SCI1 + ****************************************************************************/ + +void r_sci1_stop(void) +{ + SCI1.SCR.BIT.TE = 0u; /* Disable serial transmit */ + SCI1.SCR.BIT.RE = 0u; /* Disable serial receive */ + SCI1.SCR.BIT.TIE = 0u; /* disable TXI interrupt */ + SCI1.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */ + IEN(SCI1, TXI1) = 0u; + ICU.GENBL0.BIT.EN2 = 0u; + IR(SCI1, TXI1) = 0u; + IEN(SCI1, RXI1) = 0u; + ICU.GENBL0.BIT.EN3 = 0u; + IR(SCI1, RXI1) = 0u; +} + +/**************************************************************************** + * Name: r_sci1_serial_receive + * + * Description: + * Receives SCI1 data + ****************************************************************************/ + +MD_STATUS r_sci1_serial_receive(uint8_t * const rx_buf, uint16_t rx_num) +{ + if (1u > rx_num) + { + return MD_ARGERROR; + } + + g_sci1_rx_count = 0u; + g_sci1_rx_length = rx_num; + gp_sci1_rx_address = rx_buf; + SCI1.SCR.BIT.RIE = 1u; + SCI1.SCR.BIT.RE = 1u; + return OK; +} + +/**************************************************************************** + * Name: r_sci1_serial_send + * + * Description: + * Transmit SCI1 data + ****************************************************************************/ + +MD_STATUS r_sci1_serial_send(uint8_t * const tx_buf, uint16_t tx_num) +{ + if (1u > tx_num) + { + return MD_ARGERROR; + } + + gp_sci1_tx_address = tx_buf; + g_sci1_tx_count = tx_num; + + /* Set TXD1 pin */ + + SCI1.SCR.BIT.TIE = 1u; + SCI1.SCR.BIT.TE = 1u; + return OK; +} +#endif + +/**************************************************************************** + * Name: r_sci2_create + * + * Description: + * Initialize SCI2 + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI2 +void r_sci2_create(void) +{ + rx_mpc_enable(); + MSTP(SCI2) = 0u; /* Cancel SCI2 module stop state */ + IPR(SCI2, RXI2) = 15; /* Set interrupt priority */ + IPR(SCI2, TXI2) = 15; /* Set interrupt priority */ + SCI2.SCR.BYTE = 0u; /* Clear the control register */ + + /* Set clock enable */ + + SCI2.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED; + SCI2.SIMR1.BIT.IICM = 0u; /* Clear SIMR1.IICM bit */ + SCI2.SPMR.BIT.CKPH = 0u; /* Clear SPMR.CKPH bit */ + SCI2.SPMR.BIT.CKPOL = 0u; /* Clear SPMR.CKPOL bit */ + + /* Set control registers */ + + SCI2.SPMR.BYTE = _00_SCI_RTS; + SCI2.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | + _00_SCI_PARITY_DISABLE | _00_SCI_DATA_LENGTH_8 | + _00_SCI_MULTI_PROCESSOR_DISABLE | + _00_SCI_ASYNCHRONOUS_OR_I2C_MODE; + SCI2.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_LSB_FIRST | + _10_SCI_DATA_LENGTH_8_OR_7 | _62_SCI_SCMR_DEFAULT; + SCI2.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | + _20_SCI_NOISE_FILTER_ENABLE | _10_SCI_8_BASE_CLOCK | + _40_SCI_BAUDRATE_DOUBLE | _04_SCI_BIT_MODULATION_ENABLE; + SCI2.SNFR.BYTE = _00_SCI_ASYNC_DIV_1; + + /* Set SCI2 pin */ + + sci2_init_port(); + rx_mpc_disable(); +} + +/**************************************************************************** + * Name: r_sci2_start + * + * Description: + * Start SCI2 + ****************************************************************************/ + +void r_sci2_start(void) +{ + IR(SCI2, TXI2) = 0u; /* Clear interrupt flag */ + IR(SCI2, RXI2) = 0u; /* Clear interrupt flag */ + IEN(SCI2, TXI2) = 1u; /* Enable SCI interrupt */ + IEN(SCI2, RXI2) = 1u; /* Enable SCI interrupt */ + ICU.GENBL0.BIT.EN4 = 1u; + ICU.GENBL0.BIT.EN5 = 1u; +} + +/**************************************************************************** + * Name: r_sci2_stop + * + * Description: + * Stops SCI2 + ****************************************************************************/ + +void r_sci2_stop(void) +{ + SCI2.SCR.BIT.TE = 0u; /* Disable serial transmit */ + SCI2.SCR.BIT.RE = 0u; /* Disable serial receive */ + SCI2.SCR.BIT.TIE = 0u; /* disable TXI interrupt */ + SCI2.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */ + IEN(SCI2, TXI2) = 0u; + ICU.GENBL0.BIT.EN4 = 0u; + IR(SCI2, TXI2) = 0u; + IEN(SCI2, RXI2) = 0u; + ICU.GENBL0.BIT.EN5 = 0u; + IR(SCI2, RXI2) = 0u; +} + +/**************************************************************************** + * Name: r_sci2_serial_receive + * + * Description: + * Receives SCI2 data + ****************************************************************************/ + +MD_STATUS r_sci2_serial_receive(uint8_t * const rx_buf, uint16_t rx_num) +{ + if (1u > rx_num) + { + return MD_ARGERROR; + } + + g_sci2_rx_count = 0u; + g_sci2_rx_length = rx_num; + gp_sci2_rx_address = rx_buf; + SCI2.SCR.BIT.RIE = 1u; + SCI2.SCR.BIT.RE = 1u; + return OK; +} + +/**************************************************************************** + * Name: r_sci2_serial_send + * + * Description: + * Send SCI2 data + ****************************************************************************/ + +MD_STATUS r_sci2_serial_send(uint8_t * const tx_buf, uint16_t tx_num) +{ + if (1u > tx_num) + { + return MD_ARGERROR; + } + + gp_sci2_tx_address = tx_buf; + g_sci2_tx_count = tx_num; + + /* Set TXD2 pin */ + + SCI2.SCR.BIT.TIE = 1u; + SCI2.SCR.BIT.TE = 1u; + return OK; +} +#endif + +/**************************************************************************** + * Name: r_sci3_create + * + * Description: + * Initializes SCI3 + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI3 +void r_sci3_create(void) +{ + rx_mpc_enable(); + MSTP(SCI3) = 0u; /* Cancel SCI3 module stop state */ + IPR(SCI3, RXI3) = 15; /* Set interrupt priority */ + IPR(SCI3, TXI3) = 15; /* Set interrupt priority */ + SCI3.SCR.BYTE = 0u; /* Clear the control register */ + + /* Set clock enable */ + + SCI3.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED; + SCI3.SIMR1.BIT.IICM = 0u; /* Clear SIMR1.IICM bit */ + SCI3.SPMR.BIT.CKPH = 0u; /* Clear SPMR.CKPH bit */ + SCI3.SPMR.BIT.CKPOL = 0u; /* Clear SPMR.CKPOL bit */ + + /* Set control registers */ + + SCI3.SPMR.BYTE = _00_SCI_RTS; + SCI3.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | + _00_SCI_PARITY_DISABLE | _00_SCI_DATA_LENGTH_8 | + _00_SCI_MULTI_PROCESSOR_DISABLE | + _00_SCI_ASYNCHRONOUS_OR_I2C_MODE; + SCI3.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_LSB_FIRST | + _10_SCI_DATA_LENGTH_8_OR_7 | _62_SCI_SCMR_DEFAULT; + SCI3.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | + _20_SCI_NOISE_FILTER_ENABLE | + _10_SCI_8_BASE_CLOCK | _40_SCI_BAUDRATE_DOUBLE | + _04_SCI_BIT_MODULATION_ENABLE; + SCI3.SNFR.BYTE = _00_SCI_ASYNC_DIV_1; + + /* Set SCI3 pin */ + + sci3_init_port(); + rx_mpc_disable(); +} + +/**************************************************************************** + * Name: r_sci3_create + * + * Description: + * Initializes SCI3 + ****************************************************************************/ + +void r_sci3_start(void) +{ + IR(SCI3, TXI3) = 0u; /* Clear interrupt flag */ + IR(SCI3, RXI3) = 0u; /* Clear interrupt flag */ + IEN(SCI3, TXI3) = 1u; /* Enable SCI interrupt */ + IEN(SCI3, RXI3) = 1u; /* Enable SCI interrupt */ + ICU.GENBL0.BIT.EN6 = 0u; + ICU.GENBL0.BIT.EN7 = 1u; +} + +/**************************************************************************** + * Name: r_sci3_stop + * + * Description: + * Stops SCI3 + ****************************************************************************/ + +void r_sci3_stop(void) +{ + SCI3.SCR.BIT.TE = 0u; /* Disable serial transmit */ + SCI3.SCR.BIT.RE = 0u; /* Disable serial receive */ + SCI3.SCR.BIT.TIE = 0u; /* disable TXI interrupt */ + SCI3.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */ + IEN(SCI3, TXI3) = 0u; + ICU.GENBL0.BIT.EN6 = 0u; + IR(SCI3, TXI3) = 0u; + IEN(SCI3, RXI3) = 0u; + ICU.GENBL0.BIT.EN7 = 0u; + IR(SCI3, RXI3) = 0u; +} + +/**************************************************************************** + * Name: r_sci3_serial_receive + * + * Description: + * Receives SCI3 data + ****************************************************************************/ + +MD_STATUS r_sci3_serial_receive(uint8_t * const rx_buf, uint16_t rx_num) +{ + if (1u > rx_num) + { + return MD_ARGERROR; + } + + g_sci3_rx_count = 0u; + g_sci3_rx_length = rx_num; + gp_sci3_rx_address = rx_buf; + SCI3.SCR.BIT.RIE = 1u; + SCI3.SCR.BIT.RE = 1u; + return OK; +} + +/**************************************************************************** + * Name: r_sci3_serial_send + * + * Description: + * Send SCI3 data + ****************************************************************************/ + +MD_STATUS r_sci3_serial_send(uint8_t * const tx_buf, uint16_t tx_num) +{ + if (1u > tx_num) + { + return MD_ARGERROR; + } + + gp_sci3_tx_address = tx_buf; + g_sci3_tx_count = tx_num; + + /* Set TXD3 pin */ + + SCI3.SCR.BIT.TIE = 1u; + SCI3.SCR.BIT.TE = 1u; + return OK; +} +#endif + +/**************************************************************************** + * Name: r_sci4_create + * + * Description: + * Initialize SCI4 data + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI4 +void r_sci4_create(void) +{ + rx_mpc_enable(); + MSTP(SCI4) = 0u; /* Cancel SCI4 module stop state */ + IPR(SCI4, RXI4) = 15; /* Set interrupt priority */ + IPR(SCI4, TXI4) = 15; /* Set interrupt priority */ + SCI4.SCR.BYTE = 0u; /* Clear the control register */ + + /* Set clock enable */ + + SCI4.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED; + SCI4.SIMR1.BIT.IICM = 0u; /* Clear SIMR1.IICM bit */ + SCI4.SPMR.BIT.CKPH = 0u; /* Clear SPMR.CKPH bit */ + SCI4.SPMR.BIT.CKPOL = 0u; /* Clear SPMR.CKPOL bit */ + + /* Set control registers */ + + SCI4.SPMR.BYTE = _00_SCI_RTS; + SCI4.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | + _00_SCI_PARITY_DISABLE | _00_SCI_DATA_LENGTH_8 | + _00_SCI_MULTI_PROCESSOR_DISABLE | + _00_SCI_ASYNCHRONOUS_OR_I2C_MODE; + SCI4.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_LSB_FIRST | + _10_SCI_DATA_LENGTH_8_OR_7 | + _62_SCI_SCMR_DEFAULT; + SCI4.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | + _20_SCI_NOISE_FILTER_ENABLE | + _10_SCI_8_BASE_CLOCK | _40_SCI_BAUDRATE_DOUBLE | + _04_SCI_BIT_MODULATION_ENABLE; + SCI4.SNFR.BYTE = _00_SCI_ASYNC_DIV_1; + + /* Set SCI4 pin */ + + sci4_init_port(); + rx_mpc_disable(); +} + +/**************************************************************************** + * Name: r_sci4_start + * + * Description: + * Start SCI4 + ****************************************************************************/ + +void r_sci4_start(void) +{ + rx_mpc_enable(); + IR(SCI4, TXI4) = 0u; /* Clear interrupt flag */ + IR(SCI4, RXI4) = 0u; /* Clear interrupt flag */ + IEN(SCI4, TXI4) = 1u; /* Enable SCI interrupt */ + IEN(SCI4, RXI4) = 1u; /* Enable SCI interrupt */ + ICU.GENBL0.BIT.EN8 = 0u; + ICU.GENBL0.BIT.EN9 = 1u; +} + +/**************************************************************************** + * Name: r_sci4_stop + * + * Description: + * Stop SCI4 + ****************************************************************************/ + +void r_sci4_stop(void) +{ + SCI4.SCR.BIT.TE = 0u; /* Disable serial transmit */ + SCI4.SCR.BIT.RE = 0u; /* Disable serial receive */ + SCI4.SCR.BIT.TIE = 0u; /* disable TXI interrupt */ + SCI4.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */ + IEN(SCI4, TXI4) = 0u; + ICU.GENBL0.BIT.EN8 = 0u; + IR(SCI4, TXI4) = 0u; + IEN(SCI4, RXI4) = 0u; + ICU.GENBL0.BIT.EN9 = 0u; + IR(SCI4, RXI4) = 0u; +} + +/**************************************************************************** + * Name: r_sci4_serial_receive + * + * Description: + * Receive SCI4 data + ****************************************************************************/ + +MD_STATUS r_sci4_serial_receive(uint8_t * const rx_buf, uint16_t rx_num) +{ + if (1u > rx_num) + { + return MD_ARGERROR; + } + + g_sci4_rx_count = 0u; + g_sci4_rx_length = rx_num; + gp_sci4_rx_address = rx_buf; + SCI4.SCR.BIT.RIE = 1u; + SCI4.SCR.BIT.RE = 1u; + return OK; +} + +/**************************************************************************** + * Name: r_sci4_serial_send + * + * Description: + * Send SCI4 data + ****************************************************************************/ + +MD_STATUS r_sci4_serial_send(uint8_t * const tx_buf, uint16_t tx_num) +{ + if (1u > tx_num) + { + return MD_ARGERROR; + } + + gp_sci4_tx_address = tx_buf; + g_sci4_tx_count = tx_num; + + /* Set TXD4 pin */ + + SCI4.SCR.BIT.TIE = 1u; + SCI4.SCR.BIT.TE = 1u; + return OK; +} +#endif + +/**************************************************************************** + * Name: r_sci5_create + * + * Description: + * SCI5 Initialization + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI5 +void r_sci5_create(void) +{ + rx_mpc_enable(); + MSTP(SCI5) = 0u; /* Cancel SCI0 module stop state */ + IPR(SCI5, RXI5) = 15; /* Set interrupt priority */ + IPR(SCI5, TXI5) = 15; /* Set interrupt priority */ + SCI5.SCR.BYTE = 0u; /* Clear the control register */ + + /* Set clock enable */ + + SCI5.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED; + SCI5.SIMR1.BIT.IICM = 0u; /* Clear SIMR1.IICM bit */ + SCI5.SPMR.BIT.CKPH = 0u; /* Clear SPMR.CKPH bit */ + SCI5.SPMR.BIT.CKPOL = 0u; /* Clear SPMR.CKPOL bit */ + + /* Set control registers */ + + SCI5.SPMR.BYTE = _00_SCI_RTS; + SCI5.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | + _00_SCI_PARITY_DISABLE | _00_SCI_DATA_LENGTH_8 | + _00_SCI_MULTI_PROCESSOR_DISABLE | + _00_SCI_ASYNCHRONOUS_OR_I2C_MODE; + SCI5.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_LSB_FIRST | + _10_SCI_DATA_LENGTH_8_OR_7 | _62_SCI_SCMR_DEFAULT; + SCI5.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | + _20_SCI_NOISE_FILTER_ENABLE | _10_SCI_8_BASE_CLOCK | + _40_SCI_BAUDRATE_DOUBLE | + _04_SCI_BIT_MODULATION_ENABLE; + SCI5.SNFR.BYTE = _00_SCI_ASYNC_DIV_1; + + /* Set SCI5 pin */ + + sci5_init_port(); + rx_mpc_disable(); +} + +/**************************************************************************** + * Name: r_sci5_start + * + * Description: + * Start SCI5 + ****************************************************************************/ + +void r_sci5_start(void) +{ + IR(SCI5, TXI5) = 0u; /* Clear interrupt flag */ + IR(SCI5, RXI5) = 0u; /* Clear interrupt flag */ + IEN(SCI5, TXI5) = 1u; /* Enable SCI interrupt */ + IEN(SCI5, RXI5) = 1u; /* Enable SCI interrupt */ + ICU.GENBL0.BIT.EN10 = 0u; + ICU.GENBL0.BIT.EN11 = 1u; +} + +/**************************************************************************** + * Name: r_sci5_stop + * + * Description: + * Stop SCI5 + ****************************************************************************/ + +void r_sci5_stop(void) +{ + SCI5.SCR.BIT.TE = 0u; /* Disable serial transmit */ + SCI5.SCR.BIT.RE = 0u; /* Disable serial receive */ + SCI5.SCR.BIT.TIE = 0u; /* disable TXI interrupt */ + SCI5.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */ + IEN(SCI5, TXI5) = 0u; + ICU.GENBL0.BIT.EN10 = 0u; + IR(SCI5, TXI5) = 0u; + IEN(SCI5, RXI5) = 0u; + ICU.GENBL0.BIT.EN11 = 0u; + IR(SCI5, RXI5) = 0u; +} + +/**************************************************************************** + * Name: r_sci5_serial_receive + * + * Description: + * Receive SCI5 + ****************************************************************************/ + +MD_STATUS r_sci5_serial_receive(uint8_t * const rx_buf, uint16_t rx_num) +{ + if (1u > rx_num) + { + return MD_ARGERROR; + } + + g_sci5_rx_count = 0u; + g_sci5_rx_length = rx_num; + gp_sci5_rx_address = rx_buf; + SCI5.SCR.BIT.RIE = 1u; + SCI5.SCR.BIT.RE = 1u; + return OK; +} +/**************************************************************************** + * Name: r_sci5_serial_send + * + * Description: + * Transmit SCI5 data + ****************************************************************************/ + +MD_STATUS r_sci5_serial_send(uint8_t * const tx_buf, uint16_t tx_num) +{ + if (1u > tx_num) + { + return MD_ARGERROR; + } + + gp_sci5_tx_address = tx_buf; + g_sci5_tx_count = tx_num; + + /* Set TXD5 pin */ + + SCI5.SCR.BIT.TIE = 1u; + SCI5.SCR.BIT.TE = 1u; + return OK; +} +#endif + +/**************************************************************************** + * Name: r_sci6_create + * + * Description: + * Initialization of SCI6 + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI6 +void r_sci6_create(void) +{ + rx_mpc_enable(); + MSTP(SCI6) = 0u; /* Cancel SCI0 module stop state */ + IPR(SCI6, RXI6) = 15; /* Set interrupt priority */ + IPR(SCI6, TXI6) = 15; /* Set interrupt priority */ + SCI6.SCR.BYTE = 0u; /* Clear the control register */ + + /* Set clock enable */ + + SCI6.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED; + SCI6.SIMR1.BIT.IICM = 0u; /* Clear SIMR1.IICM bit */ + SCI6.SPMR.BIT.CKPH = 0u; /* Clear SPMR.CKPH bit */ + SCI6.SPMR.BIT.CKPOL = 0u; /* Clear SPMR.CKPOL bit */ + + /* Set control registers */ + + SCI6.SPMR.BYTE = _00_SCI_RTS; + SCI6.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | + _00_SCI_PARITY_DISABLE | _00_SCI_DATA_LENGTH_8 | + _00_SCI_MULTI_PROCESSOR_DISABLE | + _00_SCI_ASYNCHRONOUS_OR_I2C_MODE; + SCI6.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_LSB_FIRST | + _10_SCI_DATA_LENGTH_8_OR_7 | _62_SCI_SCMR_DEFAULT; + SCI6.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | + _20_SCI_NOISE_FILTER_ENABLE | + _10_SCI_8_BASE_CLOCK | _40_SCI_BAUDRATE_DOUBLE | + _04_SCI_BIT_MODULATION_ENABLE; + SCI6.SNFR.BYTE = _00_SCI_ASYNC_DIV_1; + + /* Set SCI6 pin */ + + sci6_init_port(); + rx_mpc_disable(); +} + +/**************************************************************************** + * Name: r_sci6_start + * + * Description: + * Start SCI6 + ****************************************************************************/ + +void r_sci6_start(void) +{ + IR(SCI6, TXI6) = 0u; /* Clear interrupt flag */ + IR(SCI6, RXI6) = 0u; /* Clear interrupt flag */ + IEN(SCI6, TXI6) = 1u; /* Enable SCI interrupt */ + IEN(SCI6, RXI6) = 1u; /* Enable SCI interrupt */ + ICU.GENBL0.BIT.EN12 = 0u; + ICU.GENBL0.BIT.EN13 = 1u; +} + +/**************************************************************************** + * Name: r_sci6_stop + * + * Description: + * Stop SCI6 + ****************************************************************************/ + +void r_sci6_stop(void) +{ + SCI6.SCR.BIT.TE = 0u; /* Disable serial transmit */ + SCI6.SCR.BIT.RE = 0u; /* Disable serial receive */ + SCI6.SCR.BIT.TIE = 0u; /* disable TXI interrupt */ + SCI6.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */ + IEN(SCI6, TXI6) = 0u; + ICU.GENBL0.BIT.EN12 = 0u; + IR(SCI6, TXI6) = 0u; + IEN(SCI6, RXI6) = 0u; + ICU.GENBL0.BIT.EN13 = 0u; + IR(SCI6, RXI6) = 0u; +} + +/**************************************************************************** + * Name: r_sci6_serial_receive + * + * Description: + * Stop SCI6 + ****************************************************************************/ + +MD_STATUS r_sci6_serial_receive(uint8_t * const rx_buf, uint16_t rx_num) +{ + if (1u > rx_num) + { + return MD_ARGERROR; + } + + g_sci6_rx_count = 0u; + g_sci6_rx_length = rx_num; + gp_sci6_rx_address = rx_buf; + SCI6.SCR.BIT.RIE = 1u; + SCI6.SCR.BIT.RE = 1u; + return OK; +} + +/**************************************************************************** + * Name: r_sci6_serial_send + * + * Description: + * Stop SCI6 + ****************************************************************************/ + +MD_STATUS r_sci6_serial_send(uint8_t * const tx_buf, uint16_t tx_num) +{ + if (1u > tx_num) + { + return MD_ARGERROR; + } + + gp_sci6_tx_address = tx_buf; + g_sci6_tx_count = tx_num; + + /* Set TXD0 pin */ + + SCI6.SCR.BIT.TIE = 1u; + SCI6.SCR.BIT.TE = 1u; + return OK; +} +#endif + +/**************************************************************************** + * Name: r_sci7_create + * + * Description: + * SCI7 + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI7 +void r_sci7_create(void) +{ + rx_mpc_enable(); + MSTP(SCI7) = 0u; /* Cancel SCI7 module stop state */ + IPR(SCI7, RXI7) = 15; /* Set interrupt priority */ + IPR(SCI7, TXI7) = 15; /* Set interrupt priority */ + SCI7.SCR.BYTE = 0u; /* Clear the control register */ + + /* Set clock enable */ + + SCI7.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED; + SCI7.SIMR1.BIT.IICM = 0u; /* Clear SIMR1.IICM bit */ + SCI7.SPMR.BIT.CKPH = 0u; /* Clear SPMR.CKPH bit */ + SCI7.SPMR.BIT.CKPOL = 0u; /* Clear SPMR.CKPOL bit */ + + /* Set control registers */ + + SCI7.SPMR.BYTE = _00_SCI_RTS; + SCI7.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | + _00_SCI_PARITY_DISABLE | _00_SCI_DATA_LENGTH_8 | + _00_SCI_MULTI_PROCESSOR_DISABLE | + _00_SCI_ASYNCHRONOUS_OR_I2C_MODE; + SCI7.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_LSB_FIRST | + _10_SCI_DATA_LENGTH_8_OR_7 | _62_SCI_SCMR_DEFAULT; + + SCI7.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | + _20_SCI_NOISE_FILTER_ENABLE | + _10_SCI_8_BASE_CLOCK | _40_SCI_BAUDRATE_DOUBLE | + _04_SCI_BIT_MODULATION_ENABLE; + SCI7.SNFR.BYTE = _00_SCI_ASYNC_DIV_1; + + /* Set SCI7 pin */ + + sci7_init_port(); + rx_mpc_disable(); +} + +/**************************************************************************** + * Name: r_sci7_start + * + * Description: + * SCI7 Start + ****************************************************************************/ + +void r_sci7_start(void) +{ + IR(SCI7, TXI7) = 0u; /* Clear interrupt flag */ + IR(SCI7, RXI7) = 0u; /* Clear interrupt flag */ + IEN(SCI7, TXI7) = 1u; /* Enable SCI interrupt */ + IEN(SCI7, RXI7) = 1u; /* Enable SCI interrupt */ + ICU.GENBL0.BIT.EN14 = 0u; + ICU.GENBL0.BIT.EN15 = 1u; +} + +/**************************************************************************** + * Name: r_sci7_stop + * + * Description: + * SCI7 Stop + ****************************************************************************/ + +void r_sci7_stop(void) +{ + SCI7.SCR.BIT.TE = 0u; /* Disable serial transmit */ + SCI7.SCR.BIT.RE = 0u; /* Disable serial receive */ + SCI7.SCR.BIT.TIE = 0u; /* disable TXI interrupt */ + SCI7.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */ + IEN(SCI7, TXI7) = 0u; + IR(SCI7, TXI7) = 0u; + IEN(SCI7, RXI7) = 0u; + IR(SCI7, RXI7) = 0u; + ICU.GENBL0.BIT.EN14 = 0u; + ICU.GENBL0.BIT.EN15 = 0u; +} + +/**************************************************************************** + * Name: r_sci7_serial_receive + * + * Description: + * Receive SCI7 data + ****************************************************************************/ + +MD_STATUS r_sci7_serial_receive(uint8_t * const rx_buf, uint16_t rx_num) +{ + if (1u > rx_num) + { + return MD_ARGERROR; + } + + g_sci7_rx_count = 0u; + g_sci7_rx_length = rx_num; + gp_sci7_rx_address = rx_buf; + SCI7.SCR.BIT.RIE = 1u; + SCI7.SCR.BIT.RE = 1u; + return OK; +} + +/**************************************************************************** + * Name: r_sci7_serial_send + * + * Description: + * Send SCI7 data + ****************************************************************************/ + +MD_STATUS r_sci7_serial_send(uint8_t * const tx_buf, uint16_t tx_num) +{ + if (1u > tx_num) + { + return MD_ARGERROR; + } + + gp_sci7_tx_address = tx_buf; + g_sci7_tx_count = tx_num; + + /* Set TXD0 pin */ + + SCI7.SCR.BIT.TIE = 1u; + SCI7.SCR.BIT.TE = 1u; + return OK; +} +#endif + +/**************************************************************************** + * Name: r_sci8_create + * + * Description: + * SCI8 + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI8 +void r_sci8_create(void) +{ + rx_mpc_enable(); + MSTP(SCI8) = 0u; /* Cancel SCI8 module stop state */ + IPR(SCI8, RXI8) = 15; /* Set interrupt priority */ + IPR(SCI8, TXI8) = 15; /* Set interrupt priority */ + SCI8.SCR.BYTE = 0u; /* Clear the control register */ + + /* Set clock enable */ + + SCI8.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED; + SCI8.SIMR1.BIT.IICM = 0u; /* Clear SIMR1.IICM bit */ + SCI8.SPMR.BIT.CKPH = 0u; /* Clear SPMR.CKPH bit */ + SCI8.SPMR.BIT.CKPOL = 0u; /* Clear SPMR.CKPOL bit */ + + /* Set control registers */ + + SCI8.SPMR.BYTE = _00_SCI_RTS; + SCI8.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | + _00_SCI_PARITY_DISABLE | _00_SCI_DATA_LENGTH_8 | + _00_SCI_MULTI_PROCESSOR_DISABLE | + _00_SCI_ASYNCHRONOUS_OR_I2C_MODE; + SCI8.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_LSB_FIRST | + _10_SCI_DATA_LENGTH_8_OR_7 | _62_SCI_SCMR_DEFAULT; + + SCI8.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | + _20_SCI_NOISE_FILTER_ENABLE | + _10_SCI_8_BASE_CLOCK | _40_SCI_BAUDRATE_DOUBLE | + _04_SCI_BIT_MODULATION_ENABLE; + SCI8.SNFR.BYTE = _00_SCI_ASYNC_DIV_1; + + /* Set SCI8 pin */ + + sci8_init_port(); + rx_mpc_disable(); +} + +/**************************************************************************** + * Name: r_sci8_start + * + * Description: + * SCI8 Start + ****************************************************************************/ + +void r_sci8_start(void) +{ + IR(SCI8, TXI8) = 0u; /* Clear interrupt flag */ + IR(SCI8, RXI8) = 0u; /* Clear interrupt flag */ + IEN(SCI8, TXI8) = 1u; /* Enable SCI interrupt */ + IEN(SCI8, RXI8) = 1u; /* Enable SCI interrupt */ + ICU.GENBL1.BIT.EN24 = 0u; + ICU.GENBL1.BIT.EN25 = 1u; +} + +/**************************************************************************** + * Name: r_sci8_stop + * + * Description: + * SCI8 Stop + ****************************************************************************/ + +void r_sci8_stop(void) +{ + SCI8.SCR.BIT.TE = 0u; /* Disable serial transmit */ + SCI8.SCR.BIT.RE = 0u; /* Disable serial receive */ + SCI8.SCR.BIT.TIE = 0u; /* disable TXI interrupt */ + SCI8.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */ + IEN(SCI8, TXI8) = 0u; + IR(SCI8, TXI8) = 0u; + IEN(SCI8, RXI8) = 0u; + IR(SCI8, RXI8) = 0u; + ICU.GENBL1.BIT.EN24 = 0u; + ICU.GENBL1.BIT.EN25 = 0u; +} + +/**************************************************************************** + * Name: r_sci8_serial_receive + * + * Description: + * Receive SCI8 data + ****************************************************************************/ + +MD_STATUS r_sci8_serial_receive(uint8_t * const rx_buf, uint16_t rx_num) +{ + if (1u > rx_num) + { + return MD_ARGERROR; + } + + g_sci8_rx_count = 0u; + g_sci8_rx_length = rx_num; + gp_sci8_rx_address = rx_buf; + SCI8.SCR.BIT.RIE = 1u; + SCI8.SCR.BIT.RE = 1u; + return OK; +} + +/**************************************************************************** + * Name: r_sci8_serial_send + * + * Description: + * Send SCI8 data + ****************************************************************************/ + +MD_STATUS r_sci8_serial_send(uint8_t * const tx_buf, uint16_t tx_num) +{ + if (1u > tx_num) + { + return MD_ARGERROR; + } + + gp_sci8_tx_address = tx_buf; + g_sci8_tx_count = tx_num; + + /* Set TXD0 pin */ + + SCI8.SCR.BIT.TIE = 1u; + SCI8.SCR.BIT.TE = 1u; + return OK; +} +#endif + +/**************************************************************************** + * Name: r_sci9_create + * + * Description: + * SCI9 + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI9 +void r_sci9_create(void) +{ + rx_mpc_enable(); + MSTP(SCI9) = 0u; /* Cancel SCI9 module stop state */ + IPR(SCI9, RXI9) = 15; /* Set interrupt priority */ + IPR(SCI9, TXI9) = 15; /* Set interrupt priority */ + SCI9.SCR.BYTE = 0u; /* Clear the control register */ + + /* Set clock enable */ + + SCI9.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED; + SCI9.SIMR1.BIT.IICM = 0u; /* Clear SIMR1.IICM bit */ + SCI9.SPMR.BIT.CKPH = 0u; /* Clear SPMR.CKPH bit */ + SCI9.SPMR.BIT.CKPOL = 0u; /* Clear SPMR.CKPOL bit */ + + /* Set control registers */ + + SCI9.SPMR.BYTE = _00_SCI_RTS; + SCI9.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | + _00_SCI_PARITY_DISABLE | _00_SCI_DATA_LENGTH_8 | + _00_SCI_MULTI_PROCESSOR_DISABLE | + _00_SCI_ASYNCHRONOUS_OR_I2C_MODE; + SCI9.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_LSB_FIRST | + _10_SCI_DATA_LENGTH_8_OR_7 | _62_SCI_SCMR_DEFAULT; + + SCI9.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | + _20_SCI_NOISE_FILTER_ENABLE | + _10_SCI_8_BASE_CLOCK | _40_SCI_BAUDRATE_DOUBLE | + _04_SCI_BIT_MODULATION_ENABLE; + SCI9.SNFR.BYTE = _00_SCI_ASYNC_DIV_1; + + /* Set SCI9 pin */ + + sci9_init_port(); + rx_mpc_disable(); +} + +/**************************************************************************** + * Name: r_sci9_start + * + * Description: + * SCI9 Start + ****************************************************************************/ + +void r_sci9_start(void) +{ + IR(SCI9, TXI9) = 0u; /* Clear interrupt flag */ + IR(SCI9, RXI9) = 0u; /* Clear interrupt flag */ + IEN(SCI9, TXI9) = 1u; /* Enable SCI interrupt */ + IEN(SCI9, RXI9) = 1u; /* Enable SCI interrupt */ + ICU.GENBL1.BIT.EN26 = 0u; + ICU.GENBL1.BIT.EN27 = 1u; +} + +/**************************************************************************** + * Name: r_sci9_stop + * + * Description: + * SCI9 Stop + ****************************************************************************/ + +void r_sci9_stop(void) +{ + SCI9.SCR.BIT.TE = 0u; /* Disable serial transmit */ + SCI9.SCR.BIT.RE = 0u; /* Disable serial receive */ + SCI9.SCR.BIT.TIE = 0u; /* disable TXI interrupt */ + SCI9.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */ + IEN(SCI9, TXI9) = 0u; + IR(SCI9, TXI9) = 0u; + IEN(SCI9, RXI9) = 0u; + IR(SCI9, RXI9) = 0u; + ICU.GENBL1.BIT.EN26 = 0u; + ICU.GENBL1.BIT.EN27 = 0u; +} + +/**************************************************************************** + * Name: r_sci9_serial_receive + * + * Description: + * Receive SCI9 data + ****************************************************************************/ + +MD_STATUS r_sci9_serial_receive(uint8_t * const rx_buf, uint16_t rx_num) +{ + if (1u > rx_num) + { + return MD_ARGERROR; + } + + g_sci9_rx_count = 0u; + g_sci9_rx_length = rx_num; + gp_sci9_rx_address = rx_buf; + SCI9.SCR.BIT.RIE = 1u; + SCI9.SCR.BIT.RE = 1u; + return OK; +} + +/**************************************************************************** + * Name: r_sci9_serial_send + * + * Description: + * Send SCI9 data + ****************************************************************************/ + +MD_STATUS r_sci9_serial_send(uint8_t * const tx_buf, uint16_t tx_num) +{ + if (1u > tx_num) + { + return MD_ARGERROR; + } + + gp_sci9_tx_address = tx_buf; + g_sci9_tx_count = tx_num; + + /* Set TXD0 pin */ + + SCI9.SCR.BIT.TIE = 1u; + SCI9.SCR.BIT.TE = 1u; + return OK; +} +#endif + +/**************************************************************************** + * Name: r_sci10_create + * + * Description: + * SCI10 Initialization + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI10 +void r_sci10_create(void) +{ + rx_mpc_enable(); + MSTP(SCI10) = 0u; /* Cancel SCI10 module stop state */ + IPR(SCI10, RXI10) = 15; /* Set interrupt priority */ + IPR(SCI10, TXI10) = 15; /* Set interrupt priority */ + SCI10.SCR.BYTE = 0u; /* Clear the control register */ + + /* Set clock enable */ + + SCI10.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED; + SCI10.SIMR1.BIT.IICM = 0u; /* Clear SIMR1.IICM bit */ + SCI10.SPMR.BIT.CKPH = 0u; /* Clear SPMR.CKPH bit */ + SCI10.SPMR.BIT.CKPOL = 0u; /* Clear SPMR.CKPOL bit */ + + /* Set control registers */ + + SCI10.SPMR.BYTE = _00_SCI_RTS; + SCI10.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | + _00_SCI_PARITY_DISABLE | _00_SCI_DATA_LENGTH_8 | + _00_SCI_MULTI_PROCESSOR_DISABLE | + _00_SCI_ASYNCHRONOUS_OR_I2C_MODE; + SCI10.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_LSB_FIRST | + _10_SCI_DATA_LENGTH_8_OR_7 | _62_SCI_SCMR_DEFAULT; + + SCI10.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | + _20_SCI_NOISE_FILTER_ENABLE | _10_SCI_8_BASE_CLOCK | + _40_SCI_BAUDRATE_DOUBLE | + _04_SCI_BIT_MODULATION_ENABLE; + SCI10.SNFR.BYTE = _00_SCI_ASYNC_DIV_1; + + /* Set SCI10 pin */ + + sci10_init_port(); + rx_mpc_disable(); +} + +/**************************************************************************** + * Name: r_sci10_start + * + * Description: + * Starts SCI10 + ****************************************************************************/ + +void r_sci10_start(void) +{ + IR(SCI10, TXI10) = 0u; /* Clear interrupt flag */ + IR(SCI10, RXI10) = 0u; /* Clear interrupt flag */ + IEN(SCI10, TXI10) = 1u; /* Enable SCI interrupt */ + IEN(SCI10, RXI10) = 1u; /* Enable SCI interrupt */ + ICU.GENAL0.BIT.EN8 = 1u; + ICU.GENAL0.BIT.EN9 = 1u; +} + +/**************************************************************************** + * Name: r_sci10_stop + * + * Description: + * Stops SCI10 + ****************************************************************************/ + +void r_sci10_stop(void) +{ + SCI10.SCR.BIT.TE = 0u; /* Disable serial transmit */ + SCI10.SCR.BIT.RE = 0u; /* Disable serial receive */ + SCI10.SCR.BIT.TIE = 0u; /* disable TXI interrupt */ + SCI10.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */ + IEN(SCI10, TXI10) = 0u; + ICU.GENAL0.BIT.EN8 = 0u; + IR(SCI10, TXI10) = 0u; + IEN(SCI10, RXI10) = 0u; + ICU.GENAL0.BIT.EN9 = 0u; + IR(SCI10, RXI10) = 0u; +} + +/**************************************************************************** + * Name: r_sci10_serial_receive + * + * Description: + * Receives SCI10 + ****************************************************************************/ + +MD_STATUS r_sci10_serial_receive(uint8_t * const rx_buf, uint16_t rx_num) +{ + if (1u > rx_num) + { + return MD_ARGERROR; + } + + g_sci10_rx_count = 0u; + g_sci10_rx_length = rx_num; + gp_sci10_rx_address = rx_buf; + SCI10.SCR.BIT.RIE = 1u; + SCI10.SCR.BIT.RE = 1u; + return OK; +} +/**************************************************************************** + * Name: r_sci10_serial_send + * + * Description: + * Transmits SCI10 data + ****************************************************************************/ + +MD_STATUS r_sci10_serial_send(uint8_t * const tx_buf, uint16_t tx_num) +{ + if (1u > tx_num) + { + return MD_ARGERROR; + } + + gp_sci10_tx_address = tx_buf; + g_sci10_tx_count = tx_num; + + /* Set TXD0 pin */ + + SCI10.SCR.BIT.TIE = 1u; + SCI10.SCR.BIT.TE = 1u; + return OK; +} +#endif + +/**************************************************************************** + * Name: r_sci11_create + * + * Description: + * Initializes SCI11 data + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI11 +void r_sci11_create(void) +{ + rx_mpc_enable(); + MSTP(SCI11) = 0u; /* Cancel SCI11 module stop state */ + IPR(SCI11, RXI11) = 15; /* Set interrupt priority */ + IPR(SCI11, TXI11) = 15; /* Set interrupt priority */ + SCI11.SCR.BYTE = 0u; /* Clear the control register */ + + /* Set clock enable */ + + SCI11.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED; + SCI11.SIMR1.BIT.IICM = 0u; /* Clear SIMR1.IICM bit */ + SCI11.SPMR.BIT.CKPH = 0u; /* Clear SPMR.CKPH bit */ + SCI11.SPMR.BIT.CKPOL = 0u; /* Clear SPMR.CKPOL bit */ + + /* Set control registers */ + + SCI11.SPMR.BYTE = _00_SCI_RTS; + SCI11.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | + _00_SCI_PARITY_DISABLE | _00_SCI_DATA_LENGTH_8 | + _00_SCI_MULTI_PROCESSOR_DISABLE | + _00_SCI_ASYNCHRONOUS_OR_I2C_MODE; + SCI11.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_LSB_FIRST | + _10_SCI_DATA_LENGTH_8_OR_7 | _62_SCI_SCMR_DEFAULT; + SCI11.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | + _20_SCI_NOISE_FILTER_ENABLE | + _10_SCI_8_BASE_CLOCK | _40_SCI_BAUDRATE_DOUBLE | + _04_SCI_BIT_MODULATION_ENABLE; + SCI11.SNFR.BYTE = _00_SCI_ASYNC_DIV_1; + + /* Set SCI11 pin */ + + sci11_init_port(); + rx_mpc_disable(); +} + +/**************************************************************************** + * Name: r_sci11_start + * + * Description: + * Starts SCI11 + ****************************************************************************/ + +void r_sci11_start(void) +{ + IR(SCI11, TXI11) = 0u; /* Clear interrupt flag */ + IR(SCI11, RXI11) = 0u; /* Clear interrupt flag */ + IEN(SCI11, TXI11) = 1u; /* Enable SCI interrupt */ + IEN(SCI11, RXI11) = 1u; /* Enable SCI interrupt */ + ICU.GENAL0.BIT.EN12 = 1u; + ICU.GENAL0.BIT.EN13 = 1u; +} + +/**************************************************************************** + * Name: r_sci11_stop + * + * Description: + * Stops SCI11 + ****************************************************************************/ + +void r_sci11_stop(void) +{ + SCI11.SCR.BIT.TE = 0u; /* Disable serial transmit */ + SCI11.SCR.BIT.RE = 0u; /* Disable serial receive */ + SCI11.SCR.BIT.TIE = 0u; /* disable TXI interrupt */ + SCI11.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */ + IEN(SCI11, TXI11) = 0u; + ICU.GENAL0.BIT.EN12 = 0u; + IR(SCI11, TXI11) = 0u; + IEN(SCI11, RXI11) = 0u; + ICU.GENAL0.BIT.EN13 = 0u; + IR(SCI11, RXI11) = 0u; +} + +/**************************************************************************** + * Name: r_sci11_serial_receive + * + * Description: + * Receives SCI11 data + ****************************************************************************/ + +MD_STATUS r_sci11_serial_receive(uint8_t * const rx_buf, uint16_t rx_num) +{ + if (1u > rx_num) + { + return MD_ARGERROR; + } + + g_sci11_rx_count = 0u; + g_sci11_rx_length = rx_num; + gp_sci11_rx_address = rx_buf; + SCI11.SCR.BIT.RIE = 1u; + SCI11.SCR.BIT.RE = 1u; + return OK; +} + +/**************************************************************************** + * Name: r_sci11_serial_send + * + * Description: + * Transmit SCI11 data + ****************************************************************************/ + +MD_STATUS r_sci11_serial_send(uint8_t * const tx_buf, uint16_t tx_num) +{ + if (1u > tx_num) + { + return MD_ARGERROR; + } + + gp_sci11_tx_address = tx_buf; + g_sci11_tx_count = tx_num; + + /* Set TXD1 pin */ + + SCI11.SCR.BIT.TIE = 1u; + SCI11.SCR.BIT.TE = 1u; + return OK; +} +#endif + +/**************************************************************************** + * Name: r_sci12_create + * + * Description: + * Initialize SCI12 + ****************************************************************************/ + +#ifdef CONFIG_RX65N_SCI12 +void r_sci12_create(void) +{ + rx_mpc_enable(); + MSTP(SCI12) = 0u; /* Cancel SCI12 module stop state */ + IPR(SCI12, RXI12) = 15; /* Set interrupt priority */ + IPR(SCI12, TXI12) = 15; /* Set interrupt priority */ + SCI12.SCR.BYTE = 0u; /* Clear the control register */ + + /* Set clock enable */ + + SCI12.SCR.BYTE = _00_SCI_INTERNAL_SCK_UNUSED; + SCI12.SIMR1.BIT.IICM = 0u; /* Clear SIMR1.IICM bit */ + SCI12.SPMR.BIT.CKPH = 0u; /* Clear SPMR.CKPH bit */ + SCI12.SPMR.BIT.CKPOL = 0u; /* Clear SPMR.CKPOL bit */ + + /* Set control registers */ + + SCI12.SPMR.BYTE = _00_SCI_RTS; + SCI12.SMR.BYTE = _00_SCI_CLOCK_PCLK | _00_SCI_STOP_1 | + _00_SCI_PARITY_DISABLE | _00_SCI_DATA_LENGTH_8 | + _00_SCI_MULTI_PROCESSOR_DISABLE | + _00_SCI_ASYNCHRONOUS_OR_I2C_MODE; + SCI12.SCMR.BYTE = _00_SCI_SERIAL_MODE | _00_SCI_DATA_LSB_FIRST | + _10_SCI_DATA_LENGTH_8_OR_7 | _62_SCI_SCMR_DEFAULT; + SCI12.SEMR.BYTE = _80_SCI_FALLING_EDGE_START_BIT | + _20_SCI_NOISE_FILTER_ENABLE | _10_SCI_8_BASE_CLOCK | + _40_SCI_BAUDRATE_DOUBLE | _04_SCI_BIT_MODULATION_ENABLE; + SCI12.SNFR.BYTE = _00_SCI_ASYNC_DIV_1; + + /* Set SCI12 pin */ + + sci12_init_port(); + rx_mpc_disable(); +} + +/**************************************************************************** + * Name: r_sci12_start + * + * Description: + * Start SCI12 + ****************************************************************************/ + +void r_sci12_start(void) +{ + IR(SCI12, TXI12) = 0u; /* Clear interrupt flag */ + IR(SCI12, RXI12) = 0u; /* Clear interrupt flag */ + IEN(SCI12, TXI12) = 1u; /* Enable SCI interrupt */ + IEN(SCI12, RXI12) = 1u; /* Enable SCI interrupt */ + ICU.GENBL0.BIT.EN16 = 1u; + ICU.GENBL0.BIT.EN17 = 1u; +} + +/**************************************************************************** + * Name: r_sci12_stop + * + * Description: + * Stops SCI12 + ****************************************************************************/ + +void r_sci12_stop(void) +{ + SCI12.SCR.BIT.TE = 0u; /* Disable serial transmit */ + SCI12.SCR.BIT.RE = 0u; /* Disable serial receive */ + SCI12.SCR.BIT.TIE = 0u; /* disable TXI interrupt */ + SCI12.SCR.BIT.RIE = 0u; /* disable RXI and ERI interrupt */ + IEN(SCI12, TXI12) = 0u; + ICU.GENBL0.BIT.EN16 = 0u; + IR(SCI12, TXI12) = 0u; + IEN(SCI12, RXI12) = 0u; + ICU.GENBL0.BIT.EN17 = 0u; + IR(SCI12, RXI12) = 0u; +} + +/**************************************************************************** + * Name: r_sci12_serial_receive + * + * Description: + * Receives SCI12 data + ****************************************************************************/ + +MD_STATUS r_sci12_serial_receive(uint8_t * const rx_buf, uint16_t rx_num) +{ + if (1u > rx_num) + { + return MD_ARGERROR; + } + + g_sci12_rx_count = 0u; + g_sci12_rx_length = rx_num; + gp_sci12_rx_address = rx_buf; + SCI12.SCR.BIT.RIE = 1u; + SCI12.SCR.BIT.RE = 1u; + return OK; +} + +/**************************************************************************** + * Name: r_sci12_serial_send + * + * Description: + * Send SCI12 data + ****************************************************************************/ + +MD_STATUS r_sci12_serial_send(uint8_t * const tx_buf, uint16_t tx_num) +{ + if (1u > tx_num) + { + return MD_ARGERROR; + } + + gp_sci12_tx_address = tx_buf; + g_sci12_tx_count = tx_num; + + /* Set TXD2 pin */ + + SCI12.SCR.BIT.TIE = 1u; + SCI12.SCR.BIT.TE = 1u; + return OK; +} +#endif diff --git a/arch/renesas/src/rx65n/rx65n_sci.h b/arch/renesas/src/rx65n/rx65n_sci.h new file mode 100644 index 00000000000..751bc6da97c --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_sci.h @@ -0,0 +1,1398 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_sci.h + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_RENESAS_SRC_RX65N_SCI_H +#define __ARCH_RENESAS_SRC_RX65N_SCI_H + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Transmit FIFO Data Register (FTDR) */ + +/* Transmit Multi-Processor */ + +#define _FC00_SCI_DATA_TRANSMIT (0xfc00u) /* Data transmission cycles */ +#define _FE00_SCI_ID_TRANSMIT (0xfe00u) /* ID transmission cycles */ + +/* Serial Mode Register (SMR) */ + +/* Clock Select (CKS) */ + +#define _00_SCI_CLOCK_PCLK (0x00u) /* PCLK */ +#define _01_SCI_CLOCK_PCLK_4 (0x01u) /* PCLK/4 */ +#define _02_SCI_CLOCK_PCLK_16 (0x02u) /* PCLK/16 */ +#define _03_SCI_CLOCK_PCLK_64 (0x03u) /* PCLK/64 */ + +/* Multi-Processor Mode (MP) */ + +/* Disable multiprocessor mode */ + +#define _00_SCI_MULTI_PROCESSOR_DISABLE (0x00u) + +/* Enable multiprocessor mode */ + +#define _04_SCI_MULTI_PROCESSOR_ENABLE (0x04u) + +/* Stop Bit Length (STOP) */ + +#define _00_SCI_STOP_1 (0x00u) /* 1 stop bit length */ +#define _08_SCI_STOP_2 (0x08u) /* 2 stop bits length */ + +/* Parity Mode (PM) */ + +#define _00_SCI_PARITY_EVEN (0x00u) /* Parity even */ +#define _10_SCI_PARITY_ODD (0x10u) /* Parity odd */ + +/* Parity Enable (PE) */ + +#define _00_SCI_PARITY_DISABLE (0x00u) /* Parity disable */ +#define _20_SCI_PARITY_ENABLE (0x20u) /* Parity enable */ + +/* Character Length (CHR) */ + +#define _00_SCI_DATA_LENGTH_8 (0x00u) /* Data length 8 bits */ +#define _40_SCI_DATA_LENGTH_7 (0x40u) /* Data length 7 bits */ + +/* Communications Mode (CM) */ + +/* Asynchronous or simple I2C mode */ + +#define _00_SCI_ASYNCHRONOUS_OR_I2C_MODE (0x00u) + +/* Clock synchronous or simple SPI mode */ + +#define _80_SCI_CLOCK_SYNCHRONOUS_OR_SPI_MODE (0x80u) + +/* Base Clock Pulse (BCP) */ + +#define _00_SCI_32_93_CLOCK_CYCLES (0x00u) /* 32 or 93 clock cycles */ +#define _04_SCI_64_128_CLOCK_CYCLES (0x04u) /* 64 or 128 clock cycles */ +#define _08_SCI_186_372_CLOCK_CYCLES (0x08u) /* 186 or 372 clock cycles */ +#define _0C_SCI_256_512_CLOCK_CYCLES (0x0cu) /* 256 or 512 clock cycles */ + +/* Block Transfer Mode (BLK) */ + +#define _00_SCI_BLK_TRANSFER_DISABLE (0x00u) /* Block transfer disable */ +#define _40_SCI_BLK_TRANSFER_ENABLE (0x40u) /* Block transfer enable */ + +/* GSM Mode (GSM) */ + +#define _00_SCI_GSM_DISABLE (0x00u) /* Normal mode operation */ +#define _80_SCI_GSM_ENABLE (0x80u) /* GSM mode operation */ + +/* Serial Control Register (SCR) */ + +/* Clock Enable (CKE) */ + +/* Internal clock selected, SCK pin unused */ + +#define _00_SCI_INTERNAL_SCK_UNUSED (0x00u) + +/* Internal clock selected, SCK pin output low */ + +#define _00_SCI_INTERNAL_SCK_FIXED_LOW (0x00u) + +/* Internal clock selected, SCK pin as clock output */ + +#define _01_SCI_INTERNAL_SCK_OUTPUT (0x01u) + +/* Internal clock selected, SCK pin output high */ + +#define _02_SCI_INTERNAL_SCK_FIXED_HIGH (0x02u) + +/* External clock selected */ + +#define _02_SCI_EXTERNAL (0x02u) + +/* External or TMR clock selected */ + +#define _02_SCI_EXTERNAL_TMR (0x02u) + +/* Transmit End Interrupt Enable (TEIE) */ + +/* TEI interrupt request disable */ + +#define _00_SCI_TEI_INTERRUPT_DISABLE (0x00u) + +/* TEI interrupt request enable */ + +#define _04_SCI_TEI_INTERRUPT_ENABLE (0x04u) + +/* Multi-Processor Interrupt Enable (MPIE) */ + +#define _00_SCI_MP_INTERRUPT_NORMAL (0x00u) /* Normal reception */ + +/* Multi-processor ID reception */ + +#define _08_SCI_MP_INTERRUPT_SPECIAL (0x08u) + +/* Receive Enable (RE) */ + +#define _00_SCI_RECEIVE_DISABLE (0x00u) /* Disable receive mode */ +#define _10_SCI_RECEIVE_ENABLE (0x10u) /* Enable receive mode */ + +/* Transmit Enable (TE) */ + +#define _00_SCI_TRANSMIT_DISABLE (0x00u) /* Disable transmit mode */ +#define _20_SCI_TRANSMIT_ENABLE (0x20u) /* Enable transmit mode */ + +/* Receive Interrupt Enable (RIE) */ + +#define _00_SCI_RXI_ERI_DISABLE (0x00u) + +/* Disable RXI and ERI interrupt requests */ + +#define _40_SCI_RXI_ERI_ENABLE (0x40u) + +/* Enable RXI and ERI interrupt requests */ + +/* Transmit Interrupt Enable (TIE) */ + +#define _00_SCI_TXI_DISABLE (0x00u) /* Disable TXI interrupt requests */ +#define _80_SCI_TXI_ENABLE (0x80u) /* Enable TXI interrupt requests */ + +/* Smart Card Mode Register (SCMR) */ + +/* Smart Card Interface Mode Select (SMIF) */ + +#define _00_SCI_SERIAL_MODE (0x00u) + +/* Serial communications interface mode */ + +#define _01_SCI_SMART_CARD_MODE (0x01u) + +/* Smart card interface mode */ + +/* Transmitted / Received Data Invert (SINV) */ + +#define _00_SCI_DATA_INVERT_NONE (0x00u) /* Data is not inverted */ +#define _04_SCI_DATA_INVERTED (0x04u) /* Data is inverted */ + +/* Transmitted / Received Data Transfer Direction (SDIR) */ + +#define _00_SCI_DATA_LSB_FIRST (0x00u) /* Transfer data LSB first */ +#define _08_SCI_DATA_MSB_FIRST (0x08u) /* Transfer data MSB first */ + +/* Character Length 1 (CHR1) */ + +#define _00_SCI_DATA_LENGTH_9 (0x00u) + +/* Transmit/receive in 9-bit data length */ + +#define _10_SCI_DATA_LENGTH_8_OR_7 (0x10u) + +/* Transmit/receive in 8-bit or 7-bit data length */ + +/* Base Clock Pulse 2 (BCP2) */ + +/* 93, 128, 186, or 512 clock cycles */ + +#define _00_SCI_93_128_186_512_CLK (0x00u) + +/* 32, 64, 256, or 372 clock cycles */ + +#define _80_SCI_32_64_256_372_CLK (0x80u) + +/* SCMR default value */ + +#define _62_SCI_SCMR_DEFAULT (0x62u) /* Write default value of SCMR */ + +/* Serial Extended Mode Register (SEMR) */ + +/* Asynchronous Mode Clock Source Select (ACS0) */ + +#define _00_SCI_ASYNC_SOURCE_EXTERNAL (0x00u) /* External clock input */ + +/* Logical AND of two clock cycles output from TMR */ + +#define _01_SCI_ASYNC_SOURCE_TMR (0x01u) + +/* Bit Modulation Enable (BRME) */ + +/* Bit rate modulation function is disabled */ + +#define _00_SCI_BIT_MODULATION_DISABLE (0x00u) +#define _04_SCI_BIT_MODULATION_ENABLE (0x04u) + +/* Bit rate modulation function is enabled */ + +/* Asynchronous Mode Base Clock Select (ABCS) */ + +/* Selects 16 base clock cycles for 1 bit period */ + +#define _00_SCI_16_BASE_CLOCK (0x00u) + +/* Selects 8 base clock cycles for 1 bit period */ + +#define _10_SCI_8_BASE_CLOCK (0x10u) + +/* Digital Noise Filter Function Enable (NFEN) */ + +#define _00_SCI_NOISE_FILTER_DISABLE (0x00u) /* Noise filter is disabled */ +#define _20_SCI_NOISE_FILTER_ENABLE (0x20u) /* Noise filter is enabled */ + +/* Baud Rate Generator Double-Speed Mode Select (BGDM) */ + +/* Baud rate generator outputs normal frequency */ + +#define _00_SCI_BAUDRATE_SINGLE (0x00u) + +/* Baud rate generator doubles output frequency */ + +#define _40_SCI_BAUDRATE_DOUBLE (0x40u) + +/* Asynchronous Start Bit Edge Detections Select (RXDESEL) */ + +/* Low level on RXDn pin selected as start bit */ + +#define _00_SCI_LOW_LEVEL_START_BIT (0x00u) + +/* Falling edge on RXDn pin selected as start bit */ + +#define _80_SCI_FALLING_EDGE_START_BIT (0x80u) + +/* Noise Filter Setting Register (SNFR) */ + +/* Noise Filter Clock Select (NFCS) */ + +#define _00_SCI_ASYNC_DIV_1 (0x00u) /* Clock signal divided by 1 */ +#define _01_SCI_IIC_DIV_1 (0x01u) /* Clock signal divided by 1 */ +#define _02_SCI_IIC_DIV_2 (0x02u) /* Clock signal divided by 2 */ +#define _03_SCI_IIC_DIV_4 (0x03u) /* Clock signal divided by 4 */ +#define _04_SCI_IIC_DIV_8 (0x04u) /* Clock signal divided by 8 */ + +/* I2C Mode Register 1 (SIMR1) */ + +/* Simple IIC Mode Select (IICM) */ + +/* Serial or smart card mode */ + +#define _00_SCI_SERIAL_SMART_CARD_MODE (0x00u) +#define _01_SCI_IIC_MODE (0x01u) /* Simple IIC mode */ + +/* SSDA Output Delay Select (IICDL) */ + +#define _00_SCI_NONE (0x00u) /* No output delay */ +#define _08_SCI_0_TO_1_CYCLE (0x08u) /* 0 to 1 cycle */ +#define _10_SCI_1_TO_2_CYCLE (0x10u) /* 1 to 2 cycles */ +#define _18_SCI_2_TO_3_CYCLE (0x18u) /* 2 to 3 cycles */ +#define _20_SCI_3_TO_4_CYCLE (0x20u) /* 3 to 4 cycles */ +#define _28_SCI_4_TO_5_CYCLE (0x28u) /* 4 to 5 cycles */ +#define _30_SCI_5_TO_6_CYCLE (0x30u) /* 5 to 6 cycles */ +#define _38_SCI_6_TO_7_CYCLE (0x38u) /* 6 to 7 cycles */ +#define _40_SCI_7_TO_8_CYCLE (0x40u) /* 7 to 8 cycles */ +#define _48_SCI_8_TO_9_CYCLE (0x48u) /* 8 to 9 cycles */ +#define _50_SCI_9_TO_10_CYCLE (0x50u) /* 9 to 10 cycles */ +#define _58_SCI_10_TO_11_CYCLE (0x58u) /* 10 to 11 cycles */ +#define _60_SCI_11_TO_12_CYCLE (0x60u) /* 11 to 12 cycles */ +#define _68_SCI_12_TO_13_CYCLE (0x68u) /* 12 to 13 cycles */ +#define _70_SCI_13_TO_14_CYCLE (0x70u) /* 13 to 14 cycles */ +#define _78_SCI_14_TO_15_CYCLE (0x78u) /* 14 to 15 cycles */ +#define _80_SCI_15_TO_16_CYCLE (0x80u) /* 15 to 16 cycles */ +#define _88_SCI_16_TO_17_CYCLE (0x88u) /* 16 to 17 cycles */ +#define _90_SCI_17_TO_18_CYCLE (0x90u) /* 17 to 18 cycles */ +#define _98_SCI_18_TO_19_CYCLE (0x98u) /* 18 to 19 cycles */ +#define _A0_SCI_19_TO_20_CYCLE (0xa0u) /* 19 to 20 cycles */ +#define _A8_SCI_20_TO_21_CYCLE (0xa8u) /* 20 to 21 cycles */ +#define _B0_SCI_21_TO_22_CYCLE (0xb0u) /* 21 to 22 cycles */ +#define _B8_SCI_22_TO_23_CYCLE (0xb8u) /* 22 to 23 cycles */ +#define _C0_SCI_23_TO_24_CYCLE (0xc0u) /* 23 to 24 cycles */ +#define _C8_SCI_24_TO_25_CYCLE (0xc8u) /* 24 to 25 cycles */ +#define _D0_SCI_25_TO_26_CYCLE (0xd0u) /* 25 to 26 cycles */ +#define _D8_SCI_26_TO_27_CYCLE (0xd8u) /* 26 to 27 cycles */ +#define _E0_SCI_27_TO_28_CYCLE (0xe0u) /* 27 to 28 cycles */ +#define _E8_SCI_28_TO_29_CYCLE (0xe8u) /* 28 to 29 cycles */ +#define _F0_SCI_29_TO_30_CYCLE (0xf0u) /* 29 to 30 cycles */ +#define _F8_SCI_30_TO_31_CYCLE (0xf8u) /* 30 to 31 cycles */ + +/* I2C Mode Register 2 (SIMR2) */ + +/* IIC Interrupt Mode Select (IICINTM) */ + +#define _00_SCI_ACK_NACK_INTERRUPTS (0x00u) /* Use ACK/NACK interrupts */ + +/* Use reception/transmission interrupts */ + +#define _01_SCI_RX_TX_INTERRUPTS (0x01u) + +/* Clock Synchronization (IICCSC) */ + +/* No synchronization with the clock signal */ + +#define _00_SCI_NO_SYNCHRONIZATION (0x00u) + +/* Synchronization with the clock signal */ + +#define _02_SCI_SYNCHRONIZATION (0x02u) + +/* ACK Transmission Data (IICACKT) */ + +#define _00_SCI_ACK_TRANSMISSION (0x00u) /* ACK transmission */ + +/* NACK transmission and reception of ACK/NACK */ + +#define _20_SCI_NACK_TRANSMISSION (0x20u) + +/* I2C Mode Register 3 (SIMR3) */ + +/* Start Condition Generation (IICSTAREQ) */ + +/* Start condition is not generated */ + +#define _00_SCI_START_CONDITION_OFF (0x00u) + +/* Start condition is generated */ + +#define _01_SCI_START_CONDITION_ON (0x01u) + +/* Restart Condition Generation (IICRSTAREQ) */ + +/* Restart condition is not generated */ + +#define _00_SCI_RESTART_CONDITION_OFF (0x00u) + +/* Restart condition is generated */ + +#define _02_SCI_RESTART_CONDITION_ON (0x02u) + +/* Stop Condition Generation (IICSTPREQ) */ + +/* Stop condition is not generated */ + +#define _00_SCI_STOP_CONDITION_OFF (0x00u) + +/* Stop condition is generated */ + +#define _04_SCI_STOP_CONDITION_ON (0x04u) + +/* Issuing of Start, Restart, or Stop Condition Completed Flag (IICSTIF) */ + +/* No requests to generate conditions/conditions generated */ + +#define _00_SCI_CONDITION_GENERATED (0x00u) + +/* All request generation has been completed */ + +#define _08_SCI_GENERATION_COMPLETED (0x08u) + +/* SSDA Output Select (IICSDAS) */ + +/* SSDA output is serial data output */ + +#define _00_SCI_SSDA_DATA_OUTPUT (0x00u) + +/* SSDA output generates start, restart or stop condition */ + +#define _10_SCI_SSDA_START_RESTART_STOP_CONDITION (0x10u) + +/* SSDA output low level */ + +#define _20_SCI_SSDA_LOW_LEVEL (0x20u) + +/* SSDA output high impedance */ + +#define _30_SCI_SSDA_HIGH_IMPEDANCE (0x30u) + +/* SSCL Output Select (IICSCLS) */ + +/* SSCL output is serial clock output */ + +#define _00_SCI_SSCL_CLOCK_OUTPUT (0x00u) + +/* SSCL output generates start, restart or stop condition */ + +#define _40_SCI_SSCL_START_RESTART_STOP_CONDITION (0x40u) + +/* SSCL output low level */ + +#define _80_SCI_SSCL_LOW_LEVEL (0x80u) + +/* SSCL output high impedance */ + +#define _C0_SCI_SSCL_HIGH_IMPEDANCE (0xc0u) + +/* SPI Mode Register (SPMR) */ + +/* SS Pin Function Enable (SSE) */ + +#define _00_SCI_SS_PIN_DISABLE (0x00u) /* SS pin function disabled */ +#define _01_SCI_SS_PIN_ENABLE (0x01u) /* SS pin function enabled */ + +/* CTS Enable (CTSE) */ + +#define _00_SCI_RTS (0x00u) /* RTS function is enabled */ +#define _02_SCI_CTS (0x02u) /* CTS function is enabled */ + +/* Master Slave Select (MSS) */ + +#define _00_SCI_SPI_MASTER (0x00u) /* Master mode */ +#define _04_SCI_SPI_SLAVE (0x04u) /* Slave mode */ + +/* Mode Fault Flag (MFF) */ + +#define _00_SCI_NO_MODE_FAULT (0x00u) /* No mode fault */ +#define _10_SCI_MODE_FAULT (0x10u) /* Mode fault */ + +/* Clock Polarity Select (CKPOL) */ + +/* Clock polarity is not inverted */ + +#define _00_SCI_CLOCK_NOT_INVERTED (0x00u) + +/* Clock polarity is inverted */ + +#define _40_SCI_CLOCK_INVERTED (0x40u) + +/* Clock Phase Select (CKPH) */ + +#define _00_SCI_CLOCK_NOT_DELAYED (0x00u) /* Clock is not delayed */ +#define _80_SCI_CLOCK_DELAYED (0x80u) /* Clock is delayed */ + +/* FIFO Control Register (FCR) */ + +/* FIFO Mode Select (FM) */ + +#define _0000_SCI_NON_FIFO_MODE (0x0000u) /* Non-FIFO mode */ +#define _0001_SCI_FIFO_MODE (0x0001u) /* FIFO mode */ + +/* Receive FIFO Reset (RFRST) */ + +/* Select receive data full interrupt (RXI) */ + +#define _0000_SCI_RX_FIFO_RESET_DISABLE (0x0000u) +#define _0002_SCI_RX_FIFO_RESET_ENABLE (0x0002u) /* FIFO mode */ + +/* Transmit FIFO Reset (TFRST) */ + +/* Select receive data full interrupt (RXI) */ + +#define _0000_SCI_TX_FIFO_RESET_DISABLE (0x0000u) +#define _0004_SCI_TX_FIFO_RESET_ENABLE (0x0004u) /* FIFO mode */ + +/* Receive Data Ready Interrupt Select (DRES) */ + +/* Select receive data full interrupt (RXI) */ + +#define _0000_SCI_RXI_SELECT (0x0000u) +#define _0008_SCI_ERI_SELECT (0x0008u) /* Select error interrupt (RXI) */ + +/* Transmit FIFO Threshold Setting (TTRG) */ + +/* Transmit FIFO threshold value is 0 */ + +#define _0000_SCI_TX_TRIGGER_NUM_0 (0x0000u) + +/* Transmit FIFO threshold value is 1 */ + +#define _0010_SCI_TX_TRIGGER_NUM_1 (0x0010u) + +/* Transmit FIFO threshold value is 2 */ + +#define _0020_SCI_TX_TRIGGER_NUM_2 (0x0020u) + +/* Transmit FIFO threshold value is 3 */ + +#define _0030_SCI_TX_TRIGGER_NUM_3 (0x0030u) + +/* Transmit FIFO threshold value is 4 */ + +#define _0040_SCI_TX_TRIGGER_NUM_4 (0x0040u) + +/* Transmit FIFO threshold value is 5 */ + +#define _0050_SCI_TX_TRIGGER_NUM_5 (0x0050u) + +/* Transmit FIFO threshold value is 6 */ + +#define _0060_SCI_TX_TRIGGER_NUM_6 (0x0060u) + +/* Transmit FIFO threshold value is 7 */ + +#define _0070_SCI_TX_TRIGGER_NUM_7 (0x0070u) + +/* Transmit FIFO threshold value is 8 */ + +#define _0080_SCI_TX_TRIGGER_NUM_8 (0x0080u) + +/* Transmit FIFO threshold value is 9 */ + +#define _0090_SCI_TX_TRIGGER_NUM_9 (0x0090u) + +/* Transmit FIFO threshold value is 10 */ + +#define _00A0_SCI_TX_TRIGGER_NUM_10 (0x00a0u) + +/* Transmit FIFO threshold value is 11 */ + +#define _00B0_SCI_TX_TRIGGER_NUM_11 (0x00b0u) + +/* Transmit FIFO threshold value is 12 */ + +#define _00C0_SCI_TX_TRIGGER_NUM_12 (0x00c0u) + +/* Transmit FIFO threshold value is 13 */ + +#define _00D0_SCI_TX_TRIGGER_NUM_13 (0x00d0u) + +/* Transmit FIFO threshold value is 14 */ + +#define _00E0_SCI_TX_TRIGGER_NUM_14 (0x00e0u) +#define _00F0_SCI_TX_TRIGGER_NUM_15 (0x00f0u) + +/* Transmit FIFO threshold value is 15 */ + +/* Receive FIFO Threshold Setting (RTRG) */ + +/* Receive FIFO threshold value is 1 */ + +#define _0100_SCI_RX_TRIGGER_NUM_1 (0x0100u) + +/* Receive FIFO threshold value is 2 */ + +#define _0200_SCI_RX_TRIGGER_NUM_2 (0x0200u) + +/* Receive FIFO threshold value is 3 */ + +#define _0300_SCI_RX_TRIGGER_NUM_3 (0x0300u) + +/* Receive FIFO threshold value is 4 */ + +#define _0400_SCI_RX_TRIGGER_NUM_4 (0x0400u) + +/* Receive FIFO threshold value is 5 */ + +#define _0500_SCI_RX_TRIGGER_NUM_5 (0x0500u) + +/* Receive FIFO threshold value is 6 */ + +#define _0600_SCI_RX_TRIGGER_NUM_6 (0x0600u) + +/* Receive FIFO threshold value is 7 */ + +#define _0700_SCI_RX_TRIGGER_NUM_7 (0x0700u) + +/* Receive FIFO threshold value is 8 */ + +#define _0800_SCI_RX_TRIGGER_NUM_8 (0x0800u) + +/* Receive FIFO threshold value is 9 */ + +#define _0900_SCI_RX_TRIGGER_NUM_9 (0x0900u) + +/* Receive FIFO threshold value is 10 */ + +#define _0A00_SCI_RX_TRIGGER_NUM_10 (0x0a00u) + +/* Receive FIFO threshold value is 11 */ + +#define _0B00_SCI_RX_TRIGGER_NUM_11 (0x0b00u) + +/* Receive FIFO threshold value is 12 */ + +#define _0C00_SCI_RX_TRIGGER_NUM_12 (0x0c00u) + +/* Receive FIFO threshold value is 13 */ + +#define _0D00_SCI_RX_TRIGGER_NUM_13 (0x0d00u) + +/* Receive FIFO threshold value is 14 */ + +#define _0E00_SCI_RX_TRIGGER_NUM_14 (0x0e00u) + +/* Receive FIFO threshold value is 15 */ + +#define _0F00_SCI_RX_TRIGGER_NUM_15 (0x0f00u) + +/* RTS# Output Threshold Setting (RSTRG) */ + +/* Receive FIFO threshold value is 1 */ + +#define _1000_SCI_RTS_TRIGGER_NUM_1 (0x1000u) + +/* Receive FIFO threshold value is 2 */ + +#define _2000_SCI_RTS_TRIGGER_NUM_2 (0x2000u) + +/* Receive FIFO threshold value is 3 */ + +#define _3000_SCI_RTS_TRIGGER_NUM_3 (0x3000u) + +/* Receive FIFO threshold value is 4 */ + +#define _4000_SCI_RTS_TRIGGER_NUM_4 (0x4000u) + +/* Receive FIFO threshold value is 5 */ + +#define _5000_SCI_RTS_TRIGGER_NUM_5 (0x5000u) + +/* Receive FIFO threshold value is 6 */ + +#define _6000_SCI_RTS_TRIGGER_NUM_6 (0x6000u) + +/* Receive FIFO threshold value is 7 */ + +#define _7000_SCI_RTS_TRIGGER_NUM_7 (0x7000u) + +/* Receive FIFO threshold value is 8 */ + +#define _8000_SCI_RTS_TRIGGER_NUM_8 (0x8000u) + +/* Receive FIFO threshold value is 9 */ + +#define _9000_SCI_RTS_TRIGGER_NUM_9 (0x9000u) + +/* Receive FIFO threshold value is 10 */ + +#define _A000_SCI_RTS_TRIGGER_NUM_10 (0xa000u) + +/* Receive FIFO threshold value is 11 */ + +#define _B000_SCI_RTS_TRIGGER_NUM_11 (0xb000u) + +/* Receive FIFO threshold value is 12 */ + +#define _C000_SCI_RTS_TRIGGER_NUM_12 (0xc000u) + +/* Receive FIFO threshold value is 13 */ + +#define _D000_SCI_RTS_TRIGGER_NUM_13 (0xd000u) + +/* Receive FIFO threshold value is 14 */ + +#define _E000_SCI_RTS_TRIGGER_NUM_14 (0xe000u) + +/* Receive FIFO threshold value is 15 */ + +#define _F000_SCI_RTS_TRIGGER_NUM_15 (0xf000u) + +/* Data Comparison Control Register (DCCR) */ + +/* ID Frame Select (IDSEL) */ + +#define _00_SCI_ALL_DATA_COMPARED (0x00u) + +/* All data is to be compared */ + +#define _40_SCI_ID_FRAME_COMPARED (0x40u) + +/* Only data in ID frames is compared */ + +/* Data Match Detection Enable (DCME) */ + +/* Data match detection is disabled */ + +#define _00_SCI_DATA_MATCH_DISABLE (0x00u) + +/* Data match detection is enabled */ + +#define _80_SCI_DATA_MATCH_ENABLE (0x80u) + +/* Interrupt Source Priority Register n (IPRn) */ + +/* Interrupt Priority Level Select (IPR[3:0]) */ + +#define _00_SCI_PRIORITY_LEVEL0 (0x00u) /* Level 0 (interrupt disabled) */ +#define _01_SCI_PRIORITY_LEVEL1 (0x01u) /* Level 1 */ +#define _02_SCI_PRIORITY_LEVEL2 (0x02u) /* Level 2 */ +#define _03_SCI_PRIORITY_LEVEL3 (0x03u) /* Level 3 */ +#define _04_SCI_PRIORITY_LEVEL4 (0x04u) /* Level 4 */ +#define _05_SCI_PRIORITY_LEVEL5 (0x05u) /* Level 5 */ +#define _06_SCI_PRIORITY_LEVEL6 (0x06u) /* Level 6 */ +#define _07_SCI_PRIORITY_LEVEL7 (0x07u) /* Level 7 */ +#define _08_SCI_PRIORITY_LEVEL8 (0x08u) /* Level 8 */ +#define _09_SCI_PRIORITY_LEVEL9 (0x09u) /* Level 9 */ +#define _0A_SCI_PRIORITY_LEVEL10 (0x0au) /* Level 10 */ +#define _0B_SCI_PRIORITY_LEVEL11 (0x0bu) /* Level 11 */ +#define _0C_SCI_PRIORITY_LEVEL12 (0x0cu) /* Level 12 */ +#define _0D_SCI_PRIORITY_LEVEL13 (0x0du) /* Level 13 */ +#define _0E_SCI_PRIORITY_LEVEL14 (0x0eu) /* Level 14 */ +#define _0F_SCI_PRIORITY_LEVEL15 (0x0fu) /* Level 15 (highest) */ + +/* Transfer Status Control Value */ + +/* Simple IIC Transmit Receive Flag */ + +#define _80_SCI_IIC_TRANSMISSION (0x80u) /* Simple IIC Transmission State */ +#define _00_SCI_IIC_RECEPTION (0x00u) /* Simple IIC Reception State */ + +/* Simple IIC Start Stop Flag */ + +#define _80_SCI_IIC_START_CYCLE (0x80u) /* Simple IIC Start Cycle */ +#define _00_SCI_IIC_STOP_CYCLE (0x00u) /* Simple IIC Stop Cycle */ + +/* Multiprocessor Asynchronous Communication Flag */ + +/* Multiprocessor Asynchronous ID Transmission Cycle */ + +#define _80_SCI_ID_TRANSMISSION_CYCLE (0x80u) + +/* Multiprocessor Asynchronous Data Transmission Cycle */ + +#define _00_SCI_DATA_TRANSMISSION_CYCLE (0x00u) + +/* FIFO Buffer Maximum Size */ + +#define _10_SCI_FIFO_MAX_SIZE (0x10u) /* Size of 16-stage FIFO buffer */ + +/**************************************************************************** + * Public Function Prototypes + ***************************************************************************/ + +/**************************************************************************** + * Name: r_sci0_create + * + * Description: + * Initializes SCI0 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci0_create(void); + +/**************************************************************************** + * Name: r_sci0_start + * + * Description: + * Starts SCI0 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci0_start(void); + +/**************************************************************************** + * Name: r_sci0_stop + * + * Description: + * Stops SCI0 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci0_stop(void); + +/**************************************************************************** + * Name: r_sci1_create + * + * Description: + * Initializes SCI1 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci1_create(void); + +/**************************************************************************** + * Name: r_sci1_start + * + * Description: + * Starts SCI1 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci1_start(void); + +/**************************************************************************** + * Name: r_sci1_stop + * + * Description: + * Stops SCI1 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci1_stop(void); + +/**************************************************************************** + * Name: r_sci2_create + * + * Description: + * Initializes SCI2 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci2_create(void); + +/**************************************************************************** + * Name: r_sci2_start + * + * Description: + * Starts SCI2 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci2_start(void); + +/**************************************************************************** + * Name: r_sci2_stop + * + * Description: + * Stops SCI2 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci2_stop(void); + +/**************************************************************************** + * Name: r_sci3_create + * + * Description: + * Initializes SCI3 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci3_create(void); + +/**************************************************************************** + * Name: r_sci3_start + * + * Description: + * Starts SCI3 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci3_start(void); + +/**************************************************************************** + * Name: r_sci3_stop + * + * Description: + * Stops SCI3 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci3_stop(void); + +/**************************************************************************** + * Name: r_sci4_create + * + * Description: + * Creates SCI3 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci4_create(void); + +/**************************************************************************** + * Name: r_sci4_start + * + * Description: + * Starts SCI4 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci4_start(void); + +/**************************************************************************** + * Name: r_sci4_stop + * + * Description: + * Stops SCI4 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci4_stop(void); + +/**************************************************************************** + * Name: r_sci5_create + * + * Description: + * Initialization of SCI5 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci5_create(void); + +/**************************************************************************** + * Name: r_sci5_start + * + * Description: + * Starts SCI5 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci5_start(void); + +/**************************************************************************** + * Name: r_sci5_stop + * + * Description: + * Stops SCI5 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci5_stop(void); + +/**************************************************************************** + * Name: r_sci6_create + * + * Description: + * Initialization of SCI6 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci6_create(void); + +/**************************************************************************** + * Name: r_sci6_start + * + * Description: + * Starts SCI6 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci6_start(void); + +/**************************************************************************** + * Name: r_sci6_stop + * + * Description: + * Stops SCI6 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci6_stop(void); + +/**************************************************************************** + * Name: r_sci7_create + * + * Description: + * Initialization of SCI7 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci7_create(void); + +/**************************************************************************** + * Name: r_sci7_start + * + * Description: + * Starts SCI7 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci7_start(void); + +/**************************************************************************** + * Name: r_sci7_stop + * + * Description: + * Stops SCI7 + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci7_stop(void); + +/**************************************************************************** + * Name: r_sci8_create + * + * Description: + * SCI8 Initialization + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci8_create(void); + +/**************************************************************************** + * Name: r_sci8_start + * + * Description: + * SCI8 Start + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci8_start(void); + +/**************************************************************************** + * Name: r_sci8_stop + * + * Description: + * SCI8 Stop + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci8_stop(void); + +/**************************************************************************** + * Name: r_sci9_create + * + * Description: + * SCI9 Initialization + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci9_create(void); + +/**************************************************************************** + * Name: r_sci9_start + * + * Description: + * SCI9 Start + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci9_start(void); + +/**************************************************************************** + * Name: r_sci9_stop + * + * Description: + * SCI9 Stop + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci9_stop(void); + +/**************************************************************************** + * Name: r_sci10_create + * + * Description: + * SCI10 Initialization + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci10_create(void); + +/**************************************************************************** + * Name: r_sci10_start + * + * Description: + * SCI10 Start + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci10_start(void); + +/**************************************************************************** + * Name: r_sci10_stop + * + * Description: + * SCI10 Stop + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci10_stop(void); + +/**************************************************************************** + * Name: r_sci11_create + * + * Description: + * SCI8 Initialization + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci11_create(void); + +/**************************************************************************** + * Name: r_sci11_start + * + * Description: + * SCI11 Start + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci11_start(void); + +/**************************************************************************** + * Name: r_sci11_stop + * + * Description: + * SCI11 Stop + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci11_stop(void); + +/**************************************************************************** + * Name: r_sci12_create + * + * Description: + * SCI12 Initialization + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci12_create(void); + +/**************************************************************************** + * Name: r_sci12_start + * + * Description: + * SCI12 Start + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci12_start(void); + +/**************************************************************************** + * Name: r_sci12_stop + * + * Description: + * SCI12 Stop + * + * Input Parameters: + * None + * + * Returned Value: + * None + * + ****************************************************************************/ + +void r_sci12_stop(void); + +#endif /* __ARCH_RENESAS_SRC_RX65N_SCI_H */ diff --git a/arch/renesas/src/rx65n/rx65n_serial.c b/arch/renesas/src/rx65n/rx65n_serial.c new file mode 100644 index 00000000000..8b575080635 --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_serial.c @@ -0,0 +1,1706 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_serial.c + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include +#include "rx65n_macrodriver.h" +#include "rx65n/iodefine.h" +#include "chip.h" +#include "up_arch.h" +#include "up_internal.h" +#include "rx65n_definitions.h" +#include "rx65n_sci.h" +#include "rx65n/irq.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* Some sanity checks *******************************************************/ + +#ifdef USE_SERIALDRIVER + +/* Which SCI with be tty0/console and which tty1? */ + +#ifdef CONFIG_RX65N_SCI0 +# define TTYS0_DEV g_sci0port /* SCI0 is tty0 */ +#else +# undef TTYS0_DEV /* No tty0 */ +#endif +#ifdef CONFIG_RX65N_SCI1 +# define TTYS1_DEV g_sci1port /* SCI1 is tty1 */ +#else +# undef TTYS1_DEV /* No tty1 */ +#endif +#ifdef CONFIG_RX65N_SCI2 +# define TTYS2_DEV g_sci2port /* SCI2 is tty2 */ +#else +# undef TTYS2_DEV /* No tty2 */ +#endif +#ifdef CONFIG_RX65N_SCI3 +# define TTYS3_DEV g_sci3port /* SCI3 is tty3 */ +#else +# undef TTYS3_DEV /* No tty3 */ +#endif +#ifdef CONFIG_RX65N_SCI4 +# define TTYS4_DEV g_sci4port /* SCI4 is tty4 */ +#else +# undef TTYS4_DEV /* No tty4 */ +#endif +#ifdef CONFIG_RX65N_SCI5 +# define TTYS5_DEV g_sci5port /* SCI5 is tty5 */ +#else +# undef TTYS5_DEV /* No tty5 */ +#endif +#ifdef CONFIG_RX65N_SCI6 +# define TTYS6_DEV g_sci6port /* SCI6 is tty6 */ +#else +# undef TTYS6_DEV /* No tty6 */ +#endif +#ifdef CONFIG_RX65N_SCI7 +# define TTYS7_DEV g_sci7port /* SCI7 is tty7 */ +#else +# undef TTYS7_DEV /* No tty7 */ +#endif +#ifdef CONFIG_RX65N_SCI8 +# define TTYS8_DEV g_sci8port /* SCI8 is tty8 */ +#else +# undef TTYS8_DEV /* No tty8 */ +#endif +#ifdef CONFIG_RX65N_SCI9 +# define TTYS9_DEV g_sci9port /* SCI9 is tty9 */ +#else +# undef TTYS9_DEV /* No tty9 */ +#endif +#ifdef CONFIG_RX65N_SCI10 +# define TTYS10_DEV g_sci10port /* SCI10 is tty10 */ +#else +# undef TTYS10_DEV /* No tty10 */ +#endif +#ifdef CONFIG_RX65N_SCI11 +# define TTYS11_DEV g_sci11port /* SCI11 is tty11 */ +#else +# undef TTYS11_DEV /* No tty11 */ +#endif +#ifdef CONFIG_RX65N_SCI12 +# define TTYS12_DEV g_sci12port /* SCI12 is tty12 */ +#else +# undef TTYS12_DEV /* No tty12 */ +#endif + +#if defined(CONFIG_SCI0_SERIAL_CONSOLE) && defined(CONFIG_RX65N_SCI0) +# define HAVE_CONSOLE +# define CONSOLE_DEV g_sci0port /* SCI0 is console */ +#elif defined(CONFIG_SCI1_SERIAL_CONSOLE) && defined(CONFIG_RX65N_SCI1) +# define HAVE_CONSOLE +# define CONSOLE_DEV g_sci1port /* SCI1 is console */ +# ifdef TTYS0_DEV +# undef TTYS1_DEV +# define TTYS1_DEV g_sci0port +# undef TTYS0_DEV +# endif /* TTYS0_DEV */ + +# define TTYS0_DEV CONSOLE_DEV + +#elif defined(CONFIG_SCI2_SERIAL_CONSOLE) && defined(CONFIG_RX65N_SCI2) +# define HAVE_CONSOLE +# define CONSOLE_DEV g_sci2port /* SCI2 is console */ +# ifdef TTYS0_DEV +# undef TTYS2_DEV +# define TTYS2_DEV g_sci0port +# undef TTYS0_DEV +# endif /* TTYS0_DEV */ + +# define TTYS0_DEV CONSOLE_DEV +#elif defined(CONFIG_SCI3_SERIAL_CONSOLE) && defined(CONFIG_RX65N_SCI3) +# define HAVE_CONSOLE +# define CONSOLE_DEV g_sci3port /* SCI3 is console */ +# ifdef TTYS0_DEV +# undef TTYS3_DEV +# define TTYS3_DEV g_sci0port +# undef TTYS0_DEV +# endif /* TTYS0_DEV */ + +# define TTYS0_DEV CONSOLE_DEV +#elif defined(CONFIG_SCI4_SERIAL_CONSOLE) && defined(CONFIG_RX65N_SCI4) +# define HAVE_CONSOLE +# define CONSOLE_DEV g_sci4port /* SCI4 is console */ +# ifdef TTYS0_DEV +# undef TTYS4_DEV +# define TTYS4_DEV g_sci0port +# undef TTYS0_DEV +# endif /* TTYS0_DEV */ + +# define TTYS0_DEV CONSOLE_DEV +#elif defined(CONFIG_SCI5_SERIAL_CONSOLE) && defined(CONFIG_RX65N_SCI5) +# define HAVE_CONSOLE +# define CONSOLE_DEV g_sci5port /* SCI5 is console */ +# ifdef TTYS0_DEV +# undef TTYS5_DEV +# define TTYS5_DEV g_sci0port +# undef TTYS0_DEV +# endif /* TTYS0_DEV */ + +# define TTYS0_DEV CONSOLE_DEV +#elif defined(CONFIG_SCI6_SERIAL_CONSOLE) && defined(CONFIG_RX65N_SCI6) +# define HAVE_CONSOLE +# define CONSOLE_DEV g_sci6port /* SCI6 is console */ +# ifdef TTYS0_DEV +# undef TTYS6_DEV +# define TTYS6_DEV g_sci0port +# undef TTYS0_DEV +# endif /* TTYS0_DEV */ + +# define TTYS0_DEV CONSOLE_DEV +#elif defined(CONFIG_SCI7_SERIAL_CONSOLE) && defined(CONFIG_RX65N_SCI7) +# define HAVE_CONSOLE +# define CONSOLE_DEV g_sci7port /* SCI7 is console */ +# ifdef TTYS0_DEV +# undef TTYS7_DEV +# define TTYS7_DEV g_sci0port +# undef TTYS0_DEV +# endif /* TTYS0_DEV */ + +# define TTYS0_DEV CONSOLE_DEV +#elif defined(CONFIG_SCI8_SERIAL_CONSOLE) && defined(CONFIG_RX65N_SCI8) +# define HAVE_CONSOLE +# define CONSOLE_DEV g_sci8port /* SCI8 is console */ +# ifdef TTYS0_DEV +# undef TTYS8_DEV +# define TTYS8_DEV g_sci0port +# undef TTYS0_DEV +# endif /* TTYS0_DEV */ + +# define TTYS0_DEV CONSOLE_DEV +#elif defined(CONFIG_SCI9_SERIAL_CONSOLE) && defined(CONFIG_RX65N_SCI9) +# define HAVE_CONSOLE +# define CONSOLE_DEV g_sci9port /* SCI9 is console */ +# ifdef TTYS0_DEV +# undef TTYS9_DEV +# define TTYS9_DEV g_sci0port +# undef TTYS0_DEV +# endif /* TTYS0_DEV */ + +# define TTYS0_DEV CONSOLE_DEV +#elif defined(CONFIG_SCI10_SERIAL_CONSOLE) && defined(CONFIG_RX65N_SCI10) +# define HAVE_CONSOLE +# define CONSOLE_DEV g_sci10port /* SCI10 is console */ +# ifdef TTYS0_DEV +# undef TTYS10_DEV +# define TTYS10_DEV g_sci0port +# undef TTYS0_DEV +# endif /* TTYS0_DEV */ + +# define TTYS0_DEV CONSOLE_DEV +#elif defined(CONFIG_SCI11_SERIAL_CONSOLE) && defined(CONFIG_RX65N_SCI11) +# define HAVE_CONSOLE +# define CONSOLE_DEV g_sci11port /* SCI11 is console */ +# ifdef TTYS0_DEV +# undef TTYS11_DEV +# define TTYS11_DEV g_sci0port +# undef TTYS0_DEV +# endif /* TTYS0_DEV */ + +# define TTYS0_DEV CONSOLE_DEV +#elif defined(CONFIG_SCI12_SERIAL_CONSOLE) && defined(CONFIG_RX65N_SCI12) +# define HAVE_CONSOLE +# define CONSOLE_DEV g_sci12port /* SCI12 is console */ +# ifdef TTYS0_DEV +# undef TTYS12_DEV +# define TTYS12_DEV g_sci0port +# undef TTYS0_DEV +# endif /* TTYS0_DEV */ + +# define TTYS0_DEV CONSOLE_DEV +#else +# undef HAVE_CONSOLE +# undef CONSOLE_DEV /* No console */ +#endif + +/**************************************************************************** + * Private Types + ****************************************************************************/ + +struct up_dev_s +{ + uint32_t scibase; /* Base address of SCI registers */ + uint32_t baud; /* Configured baud */ + volatile uint8_t scr; /* Saved SCR value */ + volatile uint8_t ssr; /* Saved SR value */ + uint8_t xmitirq; /* Base IRQ associated with xmit IRQ */ + uint8_t recvirq; /* Base IRQ associated with receive IRQ */ + uint8_t eriirq; + uint8_t teiirq; + uint32_t grpibase; + uint32_t erimask; + uint32_t teimask; + uint8_t parity; /* 0=none, 1=odd, 2=even */ + uint8_t bits; /* Number of bits (7 or 8) */ + bool stopbits2; /* true: Configure with 2 stop bits instead of 1 */ +}; + +/**************************************************************************** + * Private Function Prototypes + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev); +static void up_shutdown(struct uart_dev_s *dev); +static int up_attach(struct uart_dev_s *dev); +static void up_detach(struct uart_dev_s *dev); +static int up_xmtinterrupt(int irq, void *context, FAR void *arg); +static int up_rcvinterrupt(int irq, void *context, FAR void *arg); +static int up_eriinterrupt(int irq, void *context, FAR void *arg); +static int up_teiinterrupt(int irq, void *context, FAR void *arg); +static int up_receive(struct uart_dev_s *dev, uint32_t *status); +static void up_rxint(struct uart_dev_s *dev, bool enable); +static bool up_rxavailable(struct uart_dev_s *dev); +static void up_send(struct uart_dev_s *dev, int ch); +static void up_txint(struct uart_dev_s *dev, bool enable); +static bool up_txready(struct uart_dev_s *dev); + +/**************************************************************************** + * Public Function Prototypes + ****************************************************************************/ + +void up_enable_irq(int irq); +void up_disable_irq(int irq); + +/**************************************************************************** + * Private Data + ****************************************************************************/ + +/* I/O buffers */ + +#ifdef CONFIG_RX65N_SCI0 + static char g_sci0rxbuffer[CONFIG_SCI0_RXBUFSIZE]; + static char g_sci0txbuffer[CONFIG_SCI0_TXBUFSIZE]; +#endif +#ifdef CONFIG_RX65N_SCI1 + static char g_sci1rxbuffer[CONFIG_SCI1_RXBUFSIZE]; + static char g_sci1txbuffer[CONFIG_SCI1_TXBUFSIZE]; +#endif +#ifdef CONFIG_RX65N_SCI2 + static char g_sci2rxbuffer[CONFIG_SCI2_RXBUFSIZE]; + static char g_sci2txbuffer[CONFIG_SCI2_TXBUFSIZE]; +#endif +#ifdef CONFIG_RX65N_SCI3 + static char g_sci3rxbuffer[CONFIG_SCI3_RXBUFSIZE]; + static char g_sci3txbuffer[CONFIG_SCI3_TXBUFSIZE]; +#endif +#ifdef CONFIG_RX65N_SCI4 + static char g_sci4rxbuffer[CONFIG_SCI4_RXBUFSIZE]; + static char g_sci4txbuffer[CONFIG_SCI4_TXBUFSIZE]; +#endif +#ifdef CONFIG_RX65N_SCI5 + static char g_sci5rxbuffer[CONFIG_SCI5_RXBUFSIZE]; + static char g_sci5txbuffer[CONFIG_SCI5_TXBUFSIZE]; +#endif +#ifdef CONFIG_RX65N_SCI6 + static char g_sci6rxbuffer[CONFIG_SCI6_RXBUFSIZE]; + static char g_sci6txbuffer[CONFIG_SCI6_TXBUFSIZE]; +#endif +#ifdef CONFIG_RX65N_SCI7 + static char g_sci7rxbuffer[CONFIG_SCI7_RXBUFSIZE]; + static char g_sci7txbuffer[CONFIG_SCI7_TXBUFSIZE]; +#endif +#ifdef CONFIG_RX65N_SCI8 + static char g_sci8rxbuffer[CONFIG_SCI8_RXBUFSIZE]; + static char g_sci8txbuffer[CONFIG_SCI8_TXBUFSIZE]; +#endif +#ifdef CONFIG_RX65N_SCI9 + static char g_sci9rxbuffer[CONFIG_SCI9_RXBUFSIZE]; + static char g_sci9txbuffer[CONFIG_SCI9_TXBUFSIZE]; +#endif +#ifdef CONFIG_RX65N_SCI10 + static char g_sci10rxbuffer[CONFIG_SCI10_RXBUFSIZE]; + static char g_sci10txbuffer[CONFIG_SCI10_TXBUFSIZE]; +#endif +#ifdef CONFIG_RX65N_SCI11 + static char g_sci11rxbuffer[CONFIG_SCI11_RXBUFSIZE]; + static char g_sci11txbuffer[CONFIG_SCI11_TXBUFSIZE]; +#endif +#ifdef CONFIG_RX65N_SCI12 + static char g_sci12rxbuffer[CONFIG_SCI12_RXBUFSIZE]; + static char g_sci12txbuffer[CONFIG_SCI12_TXBUFSIZE]; +#endif + +struct uart_ops_s g_sci_ops = +{ + .setup = up_setup, + .shutdown = up_shutdown, + .attach = up_attach, + .detach = up_detach, + .receive = up_receive, + .rxint = up_rxint, + .rxavailable = up_rxavailable, +#ifdef CONFIG_SERIAL_IFLOWCONTROL + .rxflowcontrol = NULL, +#endif + .send = up_send, + .txint = up_txint, + .txready = up_txready, + .txempty = up_txready, +}; + +#ifdef CONFIG_RX65N_SCI0 +static struct up_dev_s g_sci0priv = +{ + .scibase = RX65N_SCI0_BASE, + .baud = CONFIG_SCI0_BAUD, + .recvirq = RX65N_RXI0_IRQ, + .xmitirq = RX65N_TXI0_IRQ, + .eriirq = RX65N_ERI0_IRQ, + .teiirq = RX65N_TEI0_IRQ, + .grpibase = RX65N_GRPBL0_ADDR, + .erimask = RX65N_GRPBL0_ERI0_MASK, + .teimask = RX65N_GRPBL0_TEI0_MASK, + .parity = CONFIG_SCI0_PARITY, + .bits = CONFIG_SCI0_BITS, + .stopbits2 = CONFIG_SCI0_2STOP, +}; + +static uart_dev_t g_sci0port = +{ + .recv = + { + .size = CONFIG_SCI0_RXBUFSIZE, + .buffer = g_sci0rxbuffer, + }, + .xmit = + { + .size = CONFIG_SCI0_TXBUFSIZE, + .buffer = g_sci0txbuffer, + }, + .ops = &g_sci_ops, + .priv = &g_sci0priv, +}; +#endif + +#ifdef CONFIG_RX65N_SCI1 +static struct up_dev_s g_sci1priv = +{ + .scibase = RX65N_SCI1_BASE, + .baud = CONFIG_SCI1_BAUD, + .recvirq = RX65N_RXI1_IRQ, + .xmitirq = RX65N_TXI1_IRQ, + .eriirq = RX65N_ERI1_IRQ, + .teiirq = RX65N_TEI1_IRQ, + .grpibase = RX65N_GRPBL0_ADDR, + .erimask = RX65N_GRPBL0_ERI1_MASK, + .teimask = RX65N_GRPBL0_TEI1_MASK, + .parity = CONFIG_SCI1_PARITY, + .bits = CONFIG_SCI1_BITS, + .stopbits2 = CONFIG_SCI1_2STOP, +}; + +static uart_dev_t g_sci1port = +{ + .recv = + { + .size = CONFIG_SCI1_RXBUFSIZE, + .buffer = g_sci1rxbuffer, + }, + .xmit = + { + .size = CONFIG_SCI1_TXBUFSIZE, + .buffer = g_sci1txbuffer, + }, + .ops = &g_sci_ops, + .priv = &g_sci1priv, +}; +#endif + +#ifdef CONFIG_RX65N_SCI2 +static struct up_dev_s g_sci2priv = +{ + .scibase = RX65N_SCI2_BASE, + .baud = CONFIG_SCI2_BAUD, + .recvirq = RX65N_RXI2_IRQ, + .xmitirq = RX65N_TXI2_IRQ, + .eriirq = RX65N_ERI2_IRQ, + .teiirq = RX65N_TEI2_IRQ, + .grpibase = RX65N_GRPBL0_ADDR, + .erimask = RX65N_GRPBL0_ERI2_MASK, + .teimask = RX65N_GRPBL0_TEI2_MASK, + .parity = CONFIG_SCI2_PARITY, + .bits = CONFIG_SCI2_BITS, + .stopbits2 = CONFIG_SCI2_2STOP, +}; + +static uart_dev_t g_sci2port = +{ + .recv = + { + .size = CONFIG_SCI2_RXBUFSIZE, + .buffer = g_sci2rxbuffer, + }, + .xmit = + { + .size = CONFIG_SCI2_TXBUFSIZE, + .buffer = g_sci2txbuffer, + }, + .ops = &g_sci_ops, + .priv = &g_sci2priv, +}; +#endif + +#ifdef CONFIG_RX65N_SCI3 +static struct up_dev_s g_sci3priv = +{ + .scibase = RX65N_SCI3_BASE, + .baud = CONFIG_SCI3_BAUD, + .recvirq = RX65N_RXI3_IRQ, + .xmitirq = RX65N_TXI3_IRQ, + .eriirq = RX65N_ERI3_IRQ, + .teiirq = RX65N_TEI3_IRQ, + .grpibase = RX65N_GRPBL0_ADDR, + .erimask = RX65N_GRPBL0_ERI3_MASK, + .teimask = RX65N_GRPBL0_TEI3_MASK, + .parity = CONFIG_SCI3_PARITY, + .bits = CONFIG_SCI3_BITS, + .stopbits2 = CONFIG_SCI3_2STOP, +}; + +static uart_dev_t g_sci3port = +{ + .recv = + { + .size = CONFIG_SCI3_RXBUFSIZE, + .buffer = g_sci3rxbuffer, + }, + .xmit = + { + .size = CONFIG_SCI3_TXBUFSIZE, + .buffer = g_sci3txbuffer, + }, + .ops = &g_sci_ops, + .priv = &g_sci3priv, +}; +#endif + +#ifdef CONFIG_RX65N_SCI4 +static struct up_dev_s g_sci4priv = +{ + .scibase = RX65N_SCI4_BASE, + .baud = CONFIG_SCI4_BAUD, + .recvirq = RX65N_RXI4_IRQ, + .xmitirq = RX65N_TXI4_IRQ, + .eriirq = RX65N_ERI4_IRQ, + .teiirq = RX65N_TEI4_IRQ, + .grpibase = RX65N_GRPBL0_ADDR, + .erimask = RX65N_GRPBL0_ERI4_MASK, + .teimask = RX65N_GRPBL0_TEI4_MASK, + .parity = CONFIG_SCI4_PARITY, + .bits = CONFIG_SCI4_BITS, + .stopbits2 = CONFIG_SCI4_2STOP, +}; + +static uart_dev_t g_sci4port = +{ + .recv = + { + .size = CONFIG_SCI4_RXBUFSIZE, + .buffer = g_sci4rxbuffer, + }, + .xmit = + { + .size = CONFIG_SCI4_TXBUFSIZE, + .buffer = g_sci4txbuffer, + }, + .ops = &g_sci_ops, + .priv = &g_sci4priv, +}; +#endif + +#ifdef CONFIG_RX65N_SCI5 +static struct up_dev_s g_sci5priv = +{ + .scibase = RX65N_SCI5_BASE, + .baud = CONFIG_SCI5_BAUD, + .recvirq = RX65N_RXI5_IRQ, + .xmitirq = RX65N_TXI5_IRQ, + .eriirq = RX65N_ERI5_IRQ, + .teiirq = RX65N_TEI5_IRQ, + .grpibase = RX65N_GRPBL0_ADDR, + .erimask = RX65N_GRPBL0_ERI5_MASK, + .teimask = RX65N_GRPBL0_TEI5_MASK, + .parity = CONFIG_SCI5_PARITY, + .bits = CONFIG_SCI5_BITS, + .stopbits2 = CONFIG_SCI5_2STOP, +}; + +static uart_dev_t g_sci5port = +{ + .recv = + { + .size = CONFIG_SCI5_RXBUFSIZE, + .buffer = g_sci5rxbuffer, + }, + .xmit = + { + .size = CONFIG_SCI5_TXBUFSIZE, + .buffer = g_sci5txbuffer, + }, + .ops = &g_sci_ops, + .priv = &g_sci5priv, +}; +#endif + +#ifdef CONFIG_RX65N_SCI6 +static struct up_dev_s g_sci6priv = +{ + .scibase = RX65N_SCI6_BASE, + .baud = CONFIG_SCI6_BAUD, + .recvirq = RX65N_RXI6_IRQ, + .xmitirq = RX65N_TXI6_IRQ, + .eriirq = RX65N_ERI6_IRQ, + .teiirq = RX65N_TEI6_IRQ, + .grpibase = RX65N_GRPBL0_ADDR, + .erimask = RX65N_GRPBL0_ERI6_MASK, + .teimask = RX65N_GRPBL0_TEI6_MASK, + .parity = CONFIG_SCI6_PARITY, + .bits = CONFIG_SCI6_BITS, + .stopbits2 = CONFIG_SCI6_2STOP, +}; + +static uart_dev_t g_sci6port = +{ + .recv = + { + .size = CONFIG_SCI6_RXBUFSIZE, + .buffer = g_sci6rxbuffer, + }, + .xmit = + { + .size = CONFIG_SCI6_TXBUFSIZE, + .buffer = g_sci6txbuffer, + }, + .ops = &g_sci_ops, + .priv = &g_sci6priv, +}; +#endif + +#ifdef CONFIG_RX65N_SCI7 +static struct up_dev_s g_sci7priv = +{ + .scibase = RX65N_SCI7_BASE, + .baud = CONFIG_SCI7_BAUD, + .recvirq = RX65N_RXI7_IRQ, + .xmitirq = RX65N_TXI7_IRQ, + .eriirq = RX65N_ERI7_IRQ, + .teiirq = RX65N_TEI7_IRQ, + .grpibase = RX65N_GRPBL0_ADDR, + .erimask = RX65N_GRPBL0_ERI7_MASK, + .teimask = RX65N_GRPBL0_TEI7_MASK, + .parity = CONFIG_SCI7_PARITY, + .bits = CONFIG_SCI7_BITS, + .stopbits2 = CONFIG_SCI7_2STOP, +}; + +static uart_dev_t g_sci7port = +{ + .recv = + { + .size = CONFIG_SCI7_RXBUFSIZE, + .buffer = g_sci7rxbuffer, + }, + .xmit = + { + .size = CONFIG_SCI7_TXBUFSIZE, + .buffer = g_sci7txbuffer, + }, + .ops = &g_sci_ops, + .priv = &g_sci7priv, +}; +#endif + +#ifdef CONFIG_RX65N_SCI8 +static struct up_dev_s g_sci8priv = +{ + .scibase = RX65N_SCI8_BASE, + .baud = CONFIG_SCI8_BAUD, + .recvirq = RX65N_RXI8_IRQ, + .xmitirq = RX65N_TXI8_IRQ, + .eriirq = RX65N_ERI8_IRQ, + .teiirq = RX65N_TEI8_IRQ, + .grpibase = RX65N_GRPBL6_ADDR, + .erimask = RX65N_GRPBL1_ERI8_MASK, + .teimask = RX65N_GRPBL1_TEI8_MASK, + .parity = CONFIG_SCI8_PARITY, + .bits = CONFIG_SCI8_BITS, + .stopbits2 = CONFIG_SCI8_2STOP, +}; + +static uart_dev_t g_sci8port = +{ + .recv = + { + .size = CONFIG_SCI8_RXBUFSIZE, + .buffer = g_sci8rxbuffer, + }, + .xmit = + { + .size = CONFIG_SCI8_TXBUFSIZE, + .buffer = g_sci8txbuffer, + }, + .ops = &g_sci_ops, + .priv = &g_sci8priv, +}; +#endif + +#ifdef CONFIG_RX65N_SCI9 +static struct up_dev_s g_sci9priv = +{ + .scibase = RX65N_SCI9_BASE, + .baud = CONFIG_SCI9_BAUD, + .recvirq = RX65N_RXI9_IRQ, + .xmitirq = RX65N_TXI9_IRQ, + .eriirq = RX65N_ERI9_IRQ, + .teiirq = RX65N_TEI9_IRQ, + .grpibase = RX65N_GRPBL1_ADDR, + .erimask = RX65N_GRPBL1_ERI9_MASK, + .teimask = RX65N_GRPBL1_TEI9_MASK, + .parity = CONFIG_SCI9_PARITY, + .bits = CONFIG_SCI9_BITS, + .stopbits2 = CONFIG_SCI9_2STOP, +}; + +static uart_dev_t g_sci9port = +{ + .recv = + { + .size = CONFIG_SCI9_RXBUFSIZE, + .buffer = g_sci9rxbuffer, + }, + .xmit = + { + .size = CONFIG_SCI9_TXBUFSIZE, + .buffer = g_sci9txbuffer, + }, + .ops = &g_sci_ops, + .priv = &g_sci9priv, +}; +#endif + +#ifdef CONFIG_RX65N_SCI10 +static struct up_dev_s g_sci10priv = +{ + .scibase = RX65N_SCI10_BASE, + .baud = CONFIG_SCI10_BAUD, + .recvirq = RX65N_RXI10_IRQ, + .xmitirq = RX65N_TXI10_IRQ, + .eriirq = RX65N_ERI10_IRQ, + .teiirq = RX65N_TEI10_IRQ, + .grpibase = RX65N_GRPAL0_ADDR, + .erimask = RX65N_GRPAL0_ERI10_MASK, + .teimask = RX65N_GRPAL0_TEI10_MASK, + .parity = CONFIG_SCI10_PARITY, + .bits = CONFIG_SCI10_BITS, + .stopbits2 = CONFIG_SCI10_2STOP, +}; + +static uart_dev_t g_sci10port = +{ + .recv = + { + .size = CONFIG_SCI10_RXBUFSIZE, + .buffer = g_sci10rxbuffer, + }, + .xmit = + { + .size = CONFIG_SCI10_TXBUFSIZE, + .buffer = g_sci10txbuffer, + }, + .ops = &g_sci_ops, + .priv = &g_sci10priv, +}; +#endif + +#ifdef CONFIG_RX65N_SCI11 +static struct up_dev_s g_sci11priv = +{ + .scibase = RX65N_SCI11_BASE, + .baud = CONFIG_SCI11_BAUD, + .recvirq = RX65N_RXI11_IRQ, + .xmitirq = RX65N_TXI11_IRQ, + .eriirq = RX65N_ERI11_IRQ, + .teiirq = RX65N_TEI11_IRQ, + .grpibase = RX65N_GRPAL0_ADDR, + .erimask = RX65N_GRPAL0_ERI11_MASK, + .teimask = RX65N_GRPAL0_TEI11_MASK, + .parity = CONFIG_SCI11_PARITY, + .bits = CONFIG_SCI11_BITS, + .stopbits2 = CONFIG_SCI11_2STOP, +}; + +static uart_dev_t g_sci11port = +{ + .recv = + { + .size = CONFIG_SCI11_RXBUFSIZE, + .buffer = g_sci11rxbuffer, + }, + .xmit = + { + .size = CONFIG_SCI11_TXBUFSIZE, + .buffer = g_sci11txbuffer, + }, + .ops = &g_sci_ops, + .priv = &g_sci11priv, +}; +#endif + +#ifdef CONFIG_RX65N_SCI12 +static struct up_dev_s g_sci12priv = +{ + .scibase = RX65N_SCI12_BASE, + .baud = CONFIG_SCI12_BAUD, + .recvirq = RX65N_RXI12_IRQ, + .xmitirq = RX65N_TXI12_IRQ, + .eriirq = RX65N_ERI12_IRQ, + .teiirq = RX65N_TEI12_IRQ, + .grpibase = RX65N_GRPBL0_ADDR, + .erimask = RX65N_GRPBL0_ERI12_MASK, + .teimask = RX65N_GRPBL0_TEI12_MASK, + .parity = CONFIG_SCI12_PARITY, + .bits = CONFIG_SCI12_BITS, + .stopbits2 = CONFIG_SCI12_2STOP, +}; + +static uart_dev_t g_sci12port = +{ + .recv = + { + .size = CONFIG_SCI12_RXBUFSIZE, + .buffer = g_sci12rxbuffer, + }, + .xmit = + { + .size = CONFIG_SCI12_TXBUFSIZE, + .buffer = g_sci12txbuffer, + }, + .ops = &g_sci_ops, + .priv = &g_sci12priv, +}; +#endif + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_serialin + ****************************************************************************/ + +static inline uint8_t up_serialin(struct up_dev_s *priv, int offset) +{ + return getreg8(priv->scibase + offset); +} + +/**************************************************************************** + * Name: up_serialout + ****************************************************************************/ + +static inline +void up_serialout(struct up_dev_s *priv, int offset, uint8_t value) +{ + putreg8(value, priv->scibase + offset); +} + +/**************************************************************************** + * Name: up_disablesciint + ****************************************************************************/ + +static inline void up_disablesciint(struct up_dev_s *priv, uint8_t *scr) +{ + if (scr) + { + *scr = priv->scr; + } + + /* The disable all interrupts */ + + priv->scr &= ~RX_SCISCR_ALLINTS; + up_serialout(priv, RX_SCI_SCR_OFFSET, priv->scr); +} + +/**************************************************************************** + * Name: up_restoresciint + ****************************************************************************/ + +static inline void up_restoresciint(struct up_dev_s *priv, uint8_t scr) +{ + /* Set the interrupt bits in the scr value */ + + priv->scr &= ~RX_SCISCR_ALLINTS; + priv->scr |= (scr & RX_SCISCR_ALLINTS); + up_serialout(priv, RX_SCI_SCR_OFFSET, priv->scr); +} + +/**************************************************************************** + * Name: up_waittxready + ****************************************************************************/ + +#ifdef HAVE_CONSOLE +static inline void up_waittxready(struct up_dev_s *priv) +{ + int tmp; + + /* Limit how long we will wait for the TDR empty condition */ + + for (tmp = 1000 ; tmp > 0 ; tmp--) + { + /* Check if the TDR is empty. The TDR becomes empty when: (1) the + * the chip is reset or enters standby mode, (2) the TE bit in the SCR + * is cleared, or (3) the current TDR contents are loaded in the TSR so + * that new data can be written in the TDR. + */ + + if (0 != (up_serialin(priv, RX_SCI_SSR_OFFSET) & RX_SCISSR_TDRE)) + { + /* The TDR is empty... return */ + + break; + } + } +} +#endif + +/**************************************************************************** + * Name: up_setbrr + * + * Description: + * Calculate the correct value for the BRR given the configured frequency + * and the desired BAUD settings. + * + ****************************************************************************/ + +static inline void up_setbrr(struct up_dev_s *priv, unsigned int baud) +{ + uint32_t t_baud; + uint32_t t_brr1; + uint32_t brrdiv; + uint32_t t_pclk_divbrr; + float f_mddr; + uint8_t semr; + uint8_t mddr; + uint8_t brr; + + semr = up_serialin(priv, RX_SCI_SEMR_OFFSET); + brrdiv = 32U; + if (0U != (0x10 & semr)) + { + brrdiv /= 2U; + } + + if (0U != (0x40 & semr)) + { + brrdiv /= 2U; + } + + if ((RX65N_SCI10_BASE == priv->scibase) + || (RX65N_SCI11_BASE == priv->scibase)) + { + t_pclk_divbrr = RX_PCLKA / brrdiv; + } + else + { + t_pclk_divbrr = RX_PCLKB / brrdiv; + } + + t_brr1 = t_pclk_divbrr / baud; + t_baud = t_pclk_divbrr / t_brr1; + while (t_baud < baud) + { + t_brr1--; + t_baud = RX_PCLKB / brrdiv / t_brr1; + } + + brr = t_brr1 - 1; + f_mddr = ((float)baud * 256.0f) / (float)t_baud + 0.5f; + mddr = ((256.0f <= f_mddr) || (0.0f > f_mddr)) ? 0 : (uint8_t)f_mddr; + if (0 < mddr) + { + /* BRME(0x04) = 1; */ + + semr |= 0x04; + } + else + { + /* BRME(0x04) = 0; */ + + semr &= 0xf1; + mddr = 255U; + } + + /* RXDE(0x80) = NFEN(0x20) = 1; */ + + semr |= 0xa0; + + up_serialout(priv, RX_SCI_SEMR_OFFSET, semr); + up_serialout(priv, RX_SCI_BRR_OFFSET, brr); + up_serialout(priv, RX_SCI_MDDR_OFFSET, mddr); +} + +/**************************************************************************** + * Name: up_setup + * + * Description: + * Configure the SCI baud, bits, parity, fifos, etc. This + * method is called the first time that the serial port is + * opened. + * + ****************************************************************************/ + +static int up_setup(struct uart_dev_s *dev) +{ +#ifndef CONFIG_SUPPRESS_SCI_CONFIG + struct up_dev_s *priv; + uint8_t smr; + + priv = (struct up_dev_s *)dev->priv; + + /* Disable the transmitter and receiver */ + + priv->scr = up_serialin(priv, RX_SCI_SCR_OFFSET); + priv->scr &= ~(RX_SCISCR_TE | RX_SCISCR_RE); + priv->scr &= ~RX_SCISCR_CKEMASK; + up_serialout(priv, RX_SCI_SCR_OFFSET, priv->scr); + + /* Set communication to be asynchronous with the configured number of data + * bits, parity, and stop bits. Use the internal clock (undivided) + */ + + smr = 0; + if (7 == priv->bits) + { + smr |= RX_SCISMR_CHR; + } + + if (1 == priv->parity) + { + smr |= (RX_SCISMR_PE | RX_SCISMR_OE); + } + else if(2 == priv->parity) + { + smr |= RX_SCISMR_PE; + } + + if (priv->stopbits2) + { + smr |= RX_SCISMR_STOP; + } + + up_serialout(priv, RX_SCI_SMR_OFFSET, smr); + + /* Set the baud based on the configured console baud and configured + * system clock. + */ + + up_setbrr(priv, priv->baud); + + /* Then enable the transmitter and reciever */ + + priv->scr |= (RX_SCISCR_TE | RX_SCISCR_RE); + up_serialout(priv, RX_SCI_SCR_OFFSET, priv->scr); +#endif + return OK; +} + +/**************************************************************************** + * Name: up_shutdown + * + * Description: + * Disable the SCI. This method is called when the serial port is closed + * + ****************************************************************************/ + +static void up_shutdown(struct uart_dev_s *dev) +{ + struct up_dev_s *priv; + + priv = (struct up_dev_s *)dev->priv; + up_disablesciint(priv, NULL); + priv->scr = up_serialin(priv, RX_SCI_SCR_OFFSET); + priv->scr &= ~(RX_SCISCR_TE | RX_SCISCR_RE); + up_serialout(priv, RX_SCI_SCR_OFFSET, priv->scr); +} + +/**************************************************************************** + * Name: up_attach + * + * Description: + * Configure the SCI to operation in interrupt driven mode. This method is + * called when the serial port is opened. Normally, this is just after the + * the setup() method is called, however, the serial console may operate in + * a non-interrupt driven mode during the boot phase. + * + * RX and TX interrupts are not enabled when by the attach method + * (unless the + * hardware supports multiple levels of interrupt enabling). + * The RX and TX + * interrupts are not enabled until the txint() and rxint() + * methods are called. + * + ****************************************************************************/ + +static int up_attach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv; + int ret; + priv = (struct up_dev_s *)dev->priv; + + /* Attach the RDR full IRQ (RXI) that is enabled by the RIE SCR bit */ + + ret = irq_attach(priv->recvirq, up_rcvinterrupt, dev); + if (OK != ret) + { + return ret; + } + + /* Attach the TDR empty IRQ (TXI) enabled by the TIE SCR bit */ + + ret = irq_attach(priv->xmitirq, up_xmtinterrupt, dev); + if (OK != ret) + { + return ret; + } + + /* Attach the ERI IRQ */ + + ret = irq_attach(priv->eriirq, up_eriinterrupt, dev); + if (OK != ret) + { + return ret; + } + + /* Attach the TEI IRQ */ + + ret = irq_attach(priv->teiirq, up_teiinterrupt, dev); + if (OK == ret) + { +#ifdef CONFIG_ARCH_IRQPRIO + /* All SCI0 interrupts share the same prioritization */ + + up_prioritize_irq(priv->recvirq, 7); /* Set SCI priority midway */ + up_prioritize_irq(priv->xmitirq, 7); +#endif + + /* Return OK on success */ + + return OK; + } + + (void)irq_detach(priv->recvirq); + (void)irq_detach(priv->xmitirq); + (void)irq_detach(priv->eriirq); + return ret; +} + +/**************************************************************************** + * Name: up_detach + * + * Description: + * Detach SCI interrupts. This method is called when the serial port is + * closed normally just before the shutdown method is called. + * The exception is + * the serial console which is never shutdown. + * + ****************************************************************************/ + +static void up_detach(struct uart_dev_s *dev) +{ + struct up_dev_s *priv; + priv = (struct up_dev_s *)dev->priv; + + /* Disable all SCI interrupts */ + + up_disablesciint(priv, NULL); + + /* Detach the SCI interrupts */ + + up_disable_irq(priv->recvirq); + up_disable_irq(priv->xmitirq); + (void)irq_detach(priv->recvirq); + (void)irq_detach(priv->xmitirq); +} + +static int up_eriinterrupt(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev; + struct up_dev_s *priv; + uint32_t grpreg; + dev = (struct uart_dev_s *)arg; + DEBUGASSERT((NULL != dev) && (NULL != priv)); + priv = (struct up_dev_s *)dev->priv; + grpreg = getreg32(priv->grpibase); + if (grpreg | priv->erimask) + { + /* Get the current SCI status */ + + priv->ssr = up_serialin(priv, RX_SCI_SSR_OFFSET); + + /* Clear all read related events (probably already done in up_receive)) */ + + priv->ssr &= ~(RX_SCISSR_ORER | RX_SCISSR_FER | RX_SCISSR_PER); + up_serialout(priv, RX_SCI_SSR_OFFSET, priv->ssr); + } + + return OK; +} + +static int up_teiinterrupt(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev; + struct up_dev_s *priv; + uint32_t grpreg; + + dev = (struct uart_dev_s *)arg; + DEBUGASSERT((NULL != dev) && (NULL != priv)); + priv = (struct up_dev_s *)dev->priv; + grpreg = getreg32(priv->grpibase); + if (grpreg | priv->teimask) + { + /* Get the current SCI status */ + + priv->ssr = up_serialin(priv, RX_SCI_SSR_OFFSET); + + /* Clear all read related events (probably already done in up_receive)) */ + + priv->ssr &= ~(RX_SCISSR_TEND); + up_serialout(priv, RX_SCI_SSR_OFFSET, priv->ssr); + } + + return OK; +} + +static int up_rcvinterrupt(int irq, void *context, void *arg) +{ + struct uart_dev_s *dev; + dev = (struct uart_dev_s *)arg; + DEBUGASSERT((NULL != dev)); + + /* Handle receive-related events with RIE is enabled. RIE is enabled at + * times that driver is open EXCEPT when the driver is actively copying + * data from the circular buffer. In that case, the read events must + * pend until RIE is set + */ + + uart_recvchars(dev); + return OK; +} + +/**************************************************************************** + * Name: up_xmtinterrupt + * + * Description: + * This is the SCI interrupt handler. It will be invoked + * when an interrupt received on the 'irq' It should call + * uart_transmitchars or uart_receivechar to perform the + * appropriate data transfers. The interrupt handling logic\ + * must be able to map the 'irq' number into the approprite + * up_dev_s structure in order to call these functions. + * + ****************************************************************************/ + +static int up_xmtinterrupt(int irq, void *context, FAR void *arg) +{ + struct uart_dev_s *dev; + dev = (struct uart_dev_s *)arg; + DEBUGASSERT((NULL != dev)); + + /* Handle outgoing, transmit bytes (TDRE: Transmit Data Register Empty) + * when TIE is enabled. TIE is only enabled when the driver is waiting with + * buffered data. Since TDRE is usually true, + */ + + uart_xmitchars(dev); + return OK; +} + +/**************************************************************************** + * Name: up_receive + * + * Description: + * Called (usually) from the interrupt level to receive one + * character from the SCI. Error bits associated with the + * receipt are provided in the return 'status'. + * + ****************************************************************************/ + +static int up_receive(struct uart_dev_s *dev, unsigned int *status) +{ + struct up_dev_s *priv; + uint8_t rdr; + uint8_t ssr; + priv = (struct up_dev_s *)dev->priv; + + /* Read the character from the RDR port */ + + rdr = up_serialin(priv, RX_SCI_RDR_OFFSET); + + /* Clear all read related status in real ssr (so that when when rxavailable + * is called again, it will return false. + */ + + ssr = up_serialin(priv, RX_SCI_SSR_OFFSET); + ssr &= ~(RX_SCISSR_RDRF | RX_SCISSR_ORER | + RX_SCISSR_FER | RX_SCISSR_PER) ; + up_serialout(priv, RX_SCI_SSR_OFFSET, ssr); + + /* For status, return the SSR at the time that the interrupt was received */ + + *status = (uint32_t)priv->ssr << 8 | rdr; + + /* Return the received character */ + + return (int)rdr; +} + +/**************************************************************************** + * Name: up_rxint + * + * Description: + * Call to enable or disable RX interrupts + * + ****************************************************************************/ + +static void up_rxint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv; + irqstate_t flags; + priv = (struct up_dev_s *)dev->priv; + + /* Disable interrupts to prevent asynchronous accesses */ + + flags = enter_critical_section(); + + /* Are we enabling or disabling? */ + + if (enable) + { + /* Enable the RDR full interrupt */ + + priv->scr |= RX_SCISCR_RIE; +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + up_enable_irq(priv->recvirq); +#endif + } + else + { + /* Disable the RDR full interrupt */ + + priv->scr &= ~RX_SCISCR_RIE; + up_disable_irq(priv->recvirq); + } + + /* Write the modified SCR value to hardware */ + + up_serialout(priv, RX_SCI_SCR_OFFSET, priv->scr); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_rxavailable + * + * Description: + * Return true if the RDR is not empty + * + ****************************************************************************/ + +static bool up_rxavailable(struct uart_dev_s *dev) +{ + struct up_dev_s *priv; + + /* Return true if the RDR full bit is set in the SSR */ + + priv = (struct up_dev_s *)dev->priv; + return (0 != (up_serialin(priv, RX_SCI_SSR_OFFSET) & RX_SCISSR_RDRF)); +} + +/**************************************************************************** + * Name: up_send + * + * Description: + * This method will send one byte on the SCI + * + ****************************************************************************/ + +static void up_send(struct uart_dev_s *dev, int ch) +{ + struct up_dev_s *priv; + uint8_t ssr; + priv = (struct up_dev_s *)dev->priv; + + /* Write the data to the TDR */ + + up_serialout(priv, RX_SCI_TDR_OFFSET, (uint8_t)ch); + + /* Clear the TDRE bit in the SSR */ + + ssr = up_serialin(priv, RX_SCI_SSR_OFFSET); + ssr &= ~(RX_SCISSR_TDRE | RX_SCISSR_TEND | RX_SCISSR_MPBT); + up_serialout(priv, RX_SCI_SSR_OFFSET, ssr); +} + +/**************************************************************************** + * Name: up_txint + * + * Description: + * Call to enable or disable TX interrupts + * + ****************************************************************************/ + +static void up_txint(struct uart_dev_s *dev, bool enable) +{ + struct up_dev_s *priv; + irqstate_t flags; + priv = (struct up_dev_s *)dev->priv; + + /* Disable interrupts to prevent asynchronous accesses */ + + flags = enter_critical_section(); + + /* Are we enabling or disabling? */ + + if (enable) + { + /* Enable the TDR empty interrupt */ + +#ifndef CONFIG_SUPPRESS_SERIAL_INTS + up_enable_irq(priv->xmitirq); +#endif + + priv->scr |= RX_SCISCR_TIE; + + /* If the TDR is already empty, then don't wait for the interrupt */ + + if (up_txready(dev)) + { + /* Tx data register empty ... process outgoing bytes. Note: + * this could call up_txint to be called recursively. However, + * in this event, priv->scr should hold the correct value upon + * return from uuart_xmitchars(). + */ + uart_xmitchars(dev); + } + } + else + { + /* Disable the TDR empty interrupt */ + + up_disable_irq(priv->xmitirq); + } + + /* Write the modified SCR value to hardware */ + + up_serialout(priv, RX_SCI_SCR_OFFSET, priv->scr); + leave_critical_section(flags); +} + +/**************************************************************************** + * Name: up_txready + * + * Description: + * Return true if the TDR is empty + * + ****************************************************************************/ + +static bool up_txready(struct uart_dev_s *dev) +{ + struct up_dev_s *priv; + priv = (struct up_dev_s *)dev->priv; + return (0 != (up_serialin(priv, RX_SCI_SSR_OFFSET) & RX_SCISSR_TDRE)); +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_earlyconsoleinit + * + * Description: + * Performs the low level SCI initialization early in + * debug so that the serial console will be available + * during bootup. This must be called before up_consoleinit. + * + ****************************************************************************/ + +void up_earlyconsoleinit(void) +{ + /* NOTE: All GPIO configuration for the SCIs was performed in + * up_lowsetup + */ + + /* Disable all SCIs */ + +#ifdef TTYS0_DEV + up_disablesciint(TTYS0_DEV.priv, NULL); +#endif +#ifdef TTYS1_DEV + up_disablesciint(TTYS1_DEV.priv, NULL); +#endif +#ifdef TTYS2_DEV + up_disablesciint(TTYS2_DEV.priv, NULL); +#endif +#ifdef TTYS3_DEV + up_disablesciint(TTYS3_DEV.priv, NULL); +#endif +#ifdef TTYS4_DEV + up_disablesciint(TTYS4_DEV.priv, NULL); +#endif +#ifdef TTYS5_DEV + up_disablesciint(TTYS5_DEV.priv, NULL); +#endif +#ifdef TTYS6_DEV + up_disablesciint(TTYS6_DEV.priv, NULL); +#endif +#ifdef TTYS7_DEV + up_disablesciint(TTYS7_DEV.priv, NULL); +#endif +#ifdef TTYS8_DEV + up_disablesciint(TTYS8_DEV.priv, NULL); +#endif +#ifdef TTYS9_DEV + up_disablesciint(TTYS9_DEV.priv, NULL); +#endif +#ifdef TTYS10_DEV + up_disablesciint(TTYS10_DEV.priv, NULL); +#endif +#ifdef TTYS11_DEV + up_disablesciint(TTYS11_DEV.priv, NULL); +#endif +#ifdef TTYS12_DEV + up_disablesciint(TTYS12_DEV.priv, NULL); +#endif + + /* Configuration whichever one is the console */ + +#ifdef HAVE_CONSOLE + CONSOLE_DEV.isconsole = true; + up_setup(&CONSOLE_DEV); +#endif +} + +/**************************************************************************** + * Name: up_serialinit + * + * Description: + * Register serial console and serial ports. This assumes + * that up_earlyconsoleinit was called previously. + * + ****************************************************************************/ + +void up_serialinit(void) +{ + /* Register all SCIs */ + +#ifdef CONFIG_RX65N_SCI0 + r_sci0_create(); + r_sci0_start(); +#endif +#ifdef CONFIG_RX65N_SCI1 + r_sci1_create(); + r_sci1_start(); +#endif +#ifdef CONFIG_RX65N_SCI2 + r_sci2_create(); + r_sci2_start(); +#endif +#ifdef CONFIG_RX65N_SCI3 + r_sci3_create(); + r_sci3_start(); +#endif +#ifdef CONFIG_RX65N_SCI4 + r_sci4_create(); + r_sci4_start(); +#endif +#ifdef CONFIG_RX65N_SCI5 + r_sci5_create(); + r_sci5_start(); +#endif +#ifdef CONFIG_RX65N_SCI6 + r_sci6_create(); + r_sci6_start(); +#endif +#ifdef CONFIG_RX65N_SCI7 + r_sci7_create(); + r_sci7_start(); +#endif +#ifdef CONFIG_RX65N_SCI8 + r_sci8_create(); + r_sci8_start(); +#endif +#ifdef CONFIG_RX65N_SCI9 + r_sci9_create(); + r_sci9_start(); +#endif +#ifdef CONFIG_RX65N_SCI10 + r_sci10_create(); + r_sci10_start(); +#endif +#ifdef CONFIG_RX65N_SCI11 + r_sci11_create(); + r_sci11_start(); +#endif +#ifdef CONFIG_RX65N_SCI12 + r_sci12_create(); + r_sci12_start(); +#endif + +#ifdef TTYS1_DEV + (void)uart_register("/dev/ttyS1", &TTYS1_DEV); +#endif +#ifdef TTYS2_DEV + (void)uart_register("/dev/ttyS2", &TTYS2_DEV); +#endif +#ifdef TTYS3_DEV + (void)uart_register("/dev/ttyS3", &TTYS3_DEV); +#endif +#ifdef TTYS4_DEV + (void)uart_register("/dev/ttyS4", &TTYS4_DEV); +#endif +#ifdef TTYS5_DEV + (void)uart_register("/dev/ttyS5", &TTYS5_DEV); +#endif +#ifdef TTYS6_DEV + (void)uart_register("/dev/ttyS6", &TTYS6_DEV); +#endif +#ifdef TTYS7_DEV + (void)uart_register("/dev/ttyS7", &TTYS7_DEV); +#endif +#ifdef TTYS8_DEV + (void)uart_register("/dev/ttyS8", &TTYS8_DEV); +#endif +#ifdef TTYS9_DEV + (void)uart_register("/dev/ttyS9", &TTYS9_DEV); +#endif +#ifdef TTYS10_DEV + (void)uart_register("/dev/ttyS10", &TTYS10_DEV); +#endif +#ifdef TTYS11_DEV + (void)uart_register("/dev/ttyS11", &TTYS11_DEV); +#endif +#ifdef TTYS12_DEV + (void)uart_register("/dev/ttyS12", &TTYS12_DEV); +#endif + + /* Register the console */ + +#ifdef HAVE_CONSOLE + up_setup(&CONSOLE_DEV); + (void)uart_register("/dev/console", &CONSOLE_DEV); +#endif +} + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_CONSOLE + struct up_dev_s *priv; + uint8_t scr; + priv = (struct up_dev_s *)CONSOLE_DEV.priv; + up_disablesciint(priv, &scr); + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_waittxready(priv); + up_serialout(priv, RX_SCI_TDR_OFFSET, '\r'); + } + + up_waittxready(priv); + up_serialout(priv, RX_SCI_TDR_OFFSET, (uint8_t)ch); + up_waittxready(priv); + up_restoresciint(priv, scr); +#endif + return ch; +} +#else /* USE_SERIALDRIVER */ + +/**************************************************************************** + * Name: up_putc + * + * Description: + * Provide priority, low-level access to support OS debug writes + * + ****************************************************************************/ + +int up_putc(int ch) +{ +#ifdef HAVE_CONSOLE + + /* Check for LF */ + + if (ch == '\n') + { + /* Add CR */ + + up_lowputc('\r'); + } + + up_lowputc(ch); +#endif + return ch; +} + +#endif /* USE_SERIALDRIVER */ diff --git a/arch/renesas/src/rx65n/rx65n_sigdeliver.c b/arch/renesas/src/rx65n/rx65n_sigdeliver.c new file mode 100644 index 00000000000..9aca8188d28 --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_sigdeliver.c @@ -0,0 +1,131 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_sigdeliver.c + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include + +#include +#include +#include + +#include "sched/sched.h" +#include "up_internal.h" +#include "up_arch.h" + +=/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: up_sigdeliver + * + * Description: + * This is the a signal handling trampoline. When a signal action was + * posted. The task context was mucked with and forced to branch to this + * location with interrupts disabled. + * + ****************************************************************************/ + +void up_sigdeliver(void) +{ +#ifndef CONFIG_DISABLE_SIGNALS + struct tcb_s *rtcb = this_task(); + uint32_t regs[XCPTCONTEXT_REGS]; + sig_deliver_t sigdeliver; + + /* Save the errno. This must be preserved throughout the signal handling + * so that the user code final gets the correct errno value (probably + * EINTR). + */ + + int saved_errno = rtcb->pterrno; + + board_autoled_on(LED_SIGNAL); + + sinfo("rtcb=%p sigdeliver=%p sigpendactionq.head=%p\n", + rtcb, rtcb->xcp.sigdeliver, rtcb->sigpendactionq.head); + DEBUGASSERT(rtcb->xcp.sigdeliver != NULL); + + /* Save the real return state on the stack. */ + + up_copystate(regs, rtcb->xcp.regs); + regs[REG_PC] = rtcb->xcp.saved_pc; + regs[REG_PSW] = rtcb->xcp.saved_sr; + + /* Get a local copy of the sigdeliver function pointer. We do this so + * that we can nullify the sigdeliver function pointer in the TCB and + * accept more signal deliveries while processing the current pending + * signals. + */ + + sigdeliver = rtcb->xcp.sigdeliver; + rtcb->xcp.sigdeliver = NULL; + +#ifndef CONFIG_SUPPRESS_INTERRUPTS + /* Then make sure that interrupts are enabled. Signal handlers must always + * run with interrupts enabled. + */ + + up_irq_enable(); +#endif + + /* Deliver the signals */ + + sigdeliver(rtcb); + + /* Output any debug messages BEFORE restoring errno (because they may + * alter errno), then disable interrupts again and restore the original + * errno that is needed by the user logic (it is probably EINTR). + */ + + sinfo("Resuming\n"); + (void)up_irq_save(); + rtcb->pterrno = saved_errno; + + /* Then restore the correct state for this thread of + * execution. + */ + + board_autoled_off(LED_SIGNAL); + up_fullcontextrestore(regs); +#endif +} diff --git a/arch/renesas/src/rx65n/rx65n_timerisr.c b/arch/renesas/src/rx65n/rx65n_timerisr.c new file mode 100644 index 00000000000..54ccac9ea4c --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_timerisr.c @@ -0,0 +1,170 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_timerisr.c + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include + +#include +#include +#include +#include +#include +#include +#include "rx65n/irq.h" +#include "clock/clock.h" +#include "up_internal.h" +#include "up_arch.h" +#include "rx65n/iodefine.h" +#include "chip.h" +#include "rx65n_cmt.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +/* The desired timer interrupt frequency is provided by the definition + * CLK_TCK (see include/time.h). CLK_TCK defines the desired number of + * system clock ticks per second. That value is a user configurable setting + * that defaults to 100 (100 ticks per second = 10 MS interval). + * + * ITU1 operates in periodic timer mode. TCNT counts up until it matches + * the value of GRA0, then an interrupt is generated. Two values must be + * computed: + * + * (1) The divider that determines the rate at which TCNT increments, and + * (2) The value of GRA0 that cause the interrupt to occur. + * + * These must be selected so that the frequency of interrupt generation is + * CLK_TCK. Ideally, we would like to use the full range of GRA0 for better + * timing acuracy: + */ + +/* The ideal divider would be one that generates exactly 65535 ticks in + * 1/CLK_TCK seconds. For example, if RX_CLOCK is 10MHz and CLK_TCK is + * 100, then the ideal divider must be less greater than or equal to: + * + * (10,000,000 / CLK_TCK) / 65535 = 1.525 + * + * The actual selected divider would then have to be 2, resulting in a + * counting rate of 5,000,0000 and a GRA0 setting of 50,000. + */ + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: rx65n_timerisr + * + * Description: + * The timer ISR will perform a variety of services for various portions + * of the systems. + * + ****************************************************************************/ + +static int rx65n_timerisr(int irq, uint32_t *regs, void *arg) +{ + /* Process timer interrupt */ + + nxsched_process_timer(); + + return 0; +} + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Function: renesas_timer_initialize + * + * Description: + * This function is called during start-up to initialize + * the timer interrupt. + * + ****************************************************************************/ + +void renesas_timer_initialize(void) +{ + uint16_t reg16; + uint32_t reg32; + + /* Enable write to System registers */ + + putreg16(RX65N_PRCR_VALUE, RX65N_PRCR_ADDR); + + /* Start CMT module */ + + reg32 = getreg32(RX65N_MSTPCRA_ADDR); + reg32 &= (~RX65N_CMT_MSTPCRA_STOP); + putreg32(reg32, RX65N_MSTPCRA_ADDR); + + /* Disable CMT interrupt */ + + putreg16(RX65N_CMT_CMCR_DEFAULT, RX65N_CMT0_CMCR_ADDR); + IEN(CMT0, CMI0) = 0; + + /* Set CMI0 priority level */ + + IPR(CMT0, CMI0) = _0F_CMT_PRIORITY_LEVEL15; + + /* Set Counter to 0 initially */ + + putreg16(0, RX65N_CMT0_CMCNT_ADDR); + + /* Set the CMCOR match value. The interrupt will be generated when TNCT + * increments to this value + */ + + putreg16(RX65N_CMT0_COUNT_VALUE, RX65N_CMT0_CMCOR_ADDR); + + /* Attach the IMIA0 IRQ */ + + irq_attach(RX65N_CMI0_IRQ, (xcpt_t)rx65n_timerisr, NULL); + + /* Set control registers */ + + putreg16(RX65N_CMT_CMCR_INIT, RX65N_CMT0_CMCR_ADDR); + IEN(CMT0, CMI0) = 1; + + /* Start the timer */ + + reg16 = getreg16(RX65N_CMT_CMSTR0_ADDR); + reg16 |= RX65N_CMTCMSTR0_STR0; /* Enable TCNT0 */ + putreg16(reg16, RX65N_CMT_CMSTR0_ADDR); /* TCNT0 is counting */ +} diff --git a/arch/renesas/src/rx65n/rx65n_vector.S b/arch/renesas/src/rx65n/rx65n_vector.S new file mode 100644 index 00000000000..32a6ff8c8cf --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_vector.S @@ -0,0 +1,1418 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_vector.S + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * Surya + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ***************************************************************************/ + +#include /* NuttX configuration settings */ +#include /* Board-specific settings */ +#include /* IRQ definitons */ +#include "up_internal.h" +#include "rx65n/iodefine.h" +#include "rx65n_definitions.h" + +/**************************************************************************** + * Pre-processor Definitions + ***************************************************************************/ + +/**************************************************************************** + * External references + ***************************************************************************/ + + .section .text + .globl _up_doirq /* C interrupt processing logic */ + + .section .bss + .globl _up_num_irq +_up_num_irq: + .long 0 + .size _up_num_irq, . - _up_num_irq + +/**************************************************************************** + * Text + ***************************************************************************/ + .section .text + .text + +/**************************************************************************** + * Macros + ***************************************************************************/ + +/**************************************************************************** + * Macro: trampoline + * + * Description: + * Enter on exception with: + * + * SP -> PC + * PSW + * + * Branch to up_vector with: + * + ***************************************************************************/ + + .macro trampoline, irq, label + .globl \label +\label: + PUSH.L R15 + MOV.L #_up_num_irq, R15 + MOV.W #\irq, [R15] + POP R15 + BRA.A _up_vector /* Jump to the common vector handling logic */ + NOP + .endm + +/**************************************************************************** + * Macro: PUSHREGS + * + * Description: + * push registers to stacks + * registers : R15, R14, ..., R1, FPSW, + * ACC1GU, ACC1HI, ACC1LO, ACC0GU, ACC0HI, ACC0LO, USP + ***************************************************************************/ + + .macro PUSHREGS + PUSHM R1 - R15 + PUSHC FPSW + MVFACGU #0, A1, R15 + PUSH.L R15 + MVFACHI #0, A1, R15 + PUSH.L R15 + MVFACLO #0, A1, R15 + PUSH.L R15 + MVFACGU #0, A0, R15 + PUSH.L R15 + MVFACHI #0, A0, R15 + PUSH.L R15 + MVFACLO #0, A0, R15 + PUSH.L R15 + PUSHC USP + .endm + +/**************************************************************************** + * Macro: POPREGS + * + * Description: + * ppop registers from stacks + * registers : USP, ACC0LO, ACC0,HI, ACC0GU, ACC1LO, ACC1,HI, ACC1GU, + * FPSW, R1, R2, ..., R15 + ***************************************************************************/ + + .macro POPREGS + POPC USP + POP R15 + MVTACLO R15, A0 + POP R15 + MVTACHI R15, A0 + POP R15 + MVTACGU R15, A0 + POP R15 + MVTACLO R15, A1 + POP R15 + MVTACHI R15, A1 + POP R15 + MVTACGU R15, A1 + POPC FPSW + POPM R1 - R15 + .endm + +/**************************************************************************** + * Macro: MULTI_SWITCHING + * + * Description: + * interrupt group branch for groupa and groupb + ***************************************************************************/ + + .macro multi_switching, is_adrs, en_adrs, bit_number, irq_number + PUSH.L R1 + MOV.L #\is_adrs, R1 + MOV.L [R1], R1 + BTST #\bit_number, R1 + POP R1 + BZ .L\@ + NOP + PUSH.L R1 + MOV.L #\en_adrs, R1 + MOV.L [R1], R1 + BTST #\bit_number, R1 + POP R1 + BZ .L\@ + NOP + PUSH.L R1 + PUSH.L R2 + MOV.L #\irq_number, R1 + MOV.L #_up_num_irq, R2 + MOV.W R1, [R2] + POP R2 + POP R1 + PUSHC PSW /* for RTE of the end of _up_vector */ + BSR.A _up_vector /* Jump to the common vector handling logic */ +.L\@: + NOP + .endm + +/**************************************************************************** + * Name: _up_vector + * R1 = ISP because PC jump from each interrupt handler to _up_vector + ***************************************************************************/ + + .global _up_vector + .type _up_vector, #function + +_up_vector: + SETPSW I /* Re-enable interrupts. */ + PUSHREGS +#ifdef RX65N_INTERRUPT_IPL + + /* Ensure the interrupt mask is set to the syscall priority while the kernel + * structures are being accessed. + */ + + SETPSW I /* Enable Inerrupt */ + MVTIPL RX65N_INTERRUPT_IPL /* configMAX_SYSCALL_INTERRUPT_PRIORITY */ +#endif + MOV.L #_up_num_irq, R2 + MOV.W [R2], R1 + MVFC ISP, R2 /* stack pointer as 2nd args of _up_doirq */ + BSR.A _up_doirq /* remaining R1 register as 1st args of _up_doirq */ + NOP + MVFC ISP, R2 + CMP R2, R1 + BEQ .lint_contextswitch + NOP + MOV.L R1, R2 + MVFC ISP, R1 + MOV.L #(XCPTCONTEXT_SIZE), R3 /* R3 = Number of bytes to transfer */ + SMOVF /* while(R3 > 0) {*R1++ = *R2++; R3--; } */ + NOP +.lint_contextswitch: +#ifdef RX65N_INTERRUPT_IPL + + /* Reset the interrupt mask as no more data structure access is required. */ + + CLRPSW I /* Disable Inerrupt */ + MVTIPL #15 /* configKERNEL_INTERRUPT_PRIORITY */ +#endif + POPREGS + RTE + NOP + NOP + .size _up_vector, . - _up_vector + +/**************************************************************************** + * Name: int up_saveusercontext(uint32_t *regs) + * + * Description: + * Save the context of the calling function at the point of the return from + * the + * call. This basically a setjmp. + * + * Input Parameters: + * R1 = Address of register save array + * + * Returned Value: + * R1 = 0 on normal call; 1 on context switch + ***************************************************************************/ + + .globl _up_saveusercontext + .type _up_saveusercontext, #function + +_up_saveusercontext: + INT #VECT_ICU_SWINT /* #RX65N_SWINT_VNDX */ + NOP + NOP + RTS + NOP + NOP + .size _up_saveusercontext, . - _up_saveusercontext + +_uprx65_swint_handler: + PUSHREGS + + /* Then copy the stack content to the register context + * array pointed to by r1 + */ + + MVFC ISP, R2 /* stack pointer as source context info */ + MOV.L #XCPTCONTEXT_SIZE, R3 /* R3 = Number of bytes to transfer */ + SMOVF /* while(R3 > 0) {*R1++ = *R2++; R3--; } */ + NOP + SUB #XCPTCONTEXT_SIZE, R1 + ADD #(REG_R1 * 4), R1 + MOV.L #1, R2 + MOV.L R2, [R1] /* Return 1 on context switch */ + + /* Then restore R2, R3 and ISP */ + + MVFC ISP, R1 + MOV.L (REG_R2 * 4)[R1], R2 + MOV.L (REG_R3 * 4)[R1], R3 + ADD #(XCPTCONTEXT_SIZE - 8), R1 + MVTC R1, ISP + + /* Then return zero to indicate a normal function call return */ + + MOV #0, R1 /* And return zero */ + RTE + NOP + NOP + .size _uprx65_swint_handler, . - _uprx65_swint_handler + +/**************************************************************************** + * Name: void up_fullcontextrestore(uint32_t *regs) + * + * Description: + * Restore the context of the using the provided register save array. + * + * Input Parameters: + * R1 = Address of register save array + * + * Returned Value: + * None + ***************************************************************************/ + + .global _up_fullcontextrestore + .type _up_fullcontextrestore, #function + +_up_fullcontextrestore: + INT #VECT_ICU_SWINT2 /* #RX65N_SWINT2_VNDX */ + NOP + NOP + RTS + NOP + NOP + .size _up_fullcontextrestore, . - _up_fullcontextrestore + +_uprx65_swint2_handler: + MOV.L R1, R2 + +/* Then copy the stack content from the register context array pointed */ + + MVFC ISP, R1 /* stack pointer as destination context info */ + ADD # - (XCPTCONTEXT_SIZE - 8), R1 + MVTC R1, ISP /* ISP = address of base of new context info */ + MOV.L #(XCPTCONTEXT_SIZE), R3 /* R3 = Number of bytes to transfer */ + SMOVF /* while(R3 > 0) {*R1++ = *R2++; R3--;} */ + POPREGS + RTE + NOP + NOP + .size _uprx65_swint2_handler, . - _uprx65_swint2_handler + +/**************************************************************************** + * Name: _uprx65_*_handler + * + * Description: + * Trampoline entry points for each, individual IRQ + * + * R1 : Points to a the register save structure + * + ***************************************************************************/ + +_uprx65n_start_handler: + trampoline NR_IRQS, _uprx65_invalid_handler + +#ifdef CONFIG_BSC + trampoline RX65N_BUSERR_IRQ, _uprx65_buserr_handler +#endif +#ifdef CONFIG_RAM + trampoline RX65N_RAMERR_IRQ, _uprx65_ramerr_handler +#endif +#ifdef CONFIG_FCU + trampoline RX65N_FIFERR_IRQ, _uprx65_fiferr_handler +#endif +#ifdef CONFIG_FRDYI + trampoline RX65N_FRDYI_IRQ, _uprx65_frdyi_handler +#endif + trampoline RX65N_CMI0_IRQ, _uprx65_cmi0_handler +#ifdef CONFIG_RX65N_CMT1 + trampoline RX65N_CMI1_IRQ, _uprx65_cmi1_handler +#endif +#ifdef CONFIG_RX65N_CMTW0 + trampoline RX65N_CMWI0_IRQ, _uprx65_cmwi0_handler +#endif +#ifdef CONFIG_RX65N_CMTW1 + trampoline RX65N_CMWI0_IRQ, _uprx65_cmwi1_handler +#endif +#ifdef CONFIG_RX65N_USB0 + trampoline RX65N_D0FIFO0_IRQ, _uprx65_d0fifo0_handler + trampoline RX65N_D1FIFO0_IRQ, _uprx65_d1fifo0_handler +#endif +#ifdef CONFIG_RX65N_RSPI0 + trampoline RX65N_SPRI0_IRQ, _uprx65_spri0_handler + trampoline RX65N_SPTI0_IRQ, _uprx65_spti0_handler +#endif +#ifdef CONFIG_RX65N_RSPI1 + trampoline RX65N_SPRI1_IRQ, _uprx65_spri1_handler + trampoline RX65N_SPTI1_IRQ, _uprx65_spti1_handler +#endif +#ifdef CONFIG_RX65N_QSPI + trampoline RX65N_SPRI_IRQ, _uprx65_spri_handler + trampoline RX65N_SPTI_IRQ, _uprx65_spti_handler +#endif +#ifdef CONFIG_RX65N_SDHI + trampoline RX65N_SBFAI_IRQ, _uprx65_sbfai_handler +#endif +#ifdef CONFIG_RX65N_MMCIF + trampoline RX65N_MBFAI_IRQ, _uprx65_mbfai_handler +#endif +#ifdef CONFIG_RX65N_RIIC1 + trampoline RX65N_RIIC1_RXI1_IRQ, _uprx65_rxii1_handler + trampoline RX65N_RIIC1_TXI1_IRQ, _uprx65_txii1_handler +#endif +#ifdef CONFIG_RX65N_RIIC0 + trampoline RX65N_RIIC0_RXI0_IRQ, _uprx65_rxii0_handler + trampoline RX65N_RIIC0_TXI0_IRQ, _uprx65_txii0_handler +#endif +#ifdef CONFIG_RX65N_RIIC2 + trampoline RX65N_RIIC2_RXI2_IRQ, _uprx65_rxii2_handler + trampoline RX65N_RIIC2_TXI2_IRQ, _uprx65_txii2_handler +#endif +#ifdef CONFIG_RX65N_SCI0 + trampoline RX65N_RXI0_IRQ, _uprx65_rxi0_handler + trampoline RX65N_TXI0_IRQ, _uprx65_txi0_handler +#endif +#ifdef CONFIG_RX65N_SCI1 + trampoline RX65N_RXI1_IRQ, _uprx65_rxi1_handler + trampoline RX65N_TXI1_IRQ, _uprx65_txi1_handler +#endif +#ifdef CONFIG_RX65N_SCI2 + trampoline RX65N_RXI2_IRQ, _uprx65_rxi2_handler + trampoline RX65N_TXI2_IRQ, _uprx65_txi2_handler +#endif +#if defined(CONFIG_ICU) || defined(CONFIG_RX65N_ICU) + trampoline RX65N_IRQ0_IRQ, _uprx65_irq0_handler + trampoline RX65N_IRQ1_IRQ, _uprx65_irq1_handler + trampoline RX65N_IRQ2_IRQ, _uprx65_irq2_handler + trampoline RX65N_IRQ3_IRQ, _uprx65_irq3_handler + trampoline RX65N_IRQ4_IRQ, _uprx65_irq4_handler + trampoline RX65N_IRQ5_IRQ, _uprx65_irq5_handler + trampoline RX65N_IRQ6_IRQ, _uprx65_irq6_handler + trampoline RX65N_IRQ7_IRQ, _uprx65_irq7_handler + trampoline RX65N_IRQ8_IRQ, _uprx65_irq8_handler + trampoline RX65N_IRQ9_IRQ, _uprx65_irq9_handler + trampoline RX65N_IRQ10_IRQ, _uprx65_irq10_handler + trampoline RX65N_IRQ11_IRQ, _uprx65_irq11_handler + trampoline RX65N_IRQ12_IRQ, _uprx65_irq12_handler + trampoline RX65N_IRQ13_IRQ, _uprx65_irq13_handler + trampoline RX65N_IRQ14_IRQ, _uprx65_irq14_handler + trampoline RX65N_IRQ15_IRQ, _uprx65_irq15_handler +#endif +#ifdef CONFIG_RX65N_SCI3 + trampoline RX65N_RXI3_IRQ, _uprx65_rxi3_handler + trampoline RX65N_TXI3_IRQ, _uprx65_txi3_handler +#endif +#ifdef CONFIG_RX65N_SCI4 + trampoline RX65N_RXI4_IRQ, _uprx65_rxi4_handler + trampoline RX65N_TXI4_IRQ, _uprx65_txi4_handler +#endif +#ifdef CONFIG_RX65N_SCI5 + trampoline RX65N_RXI5_IRQ, _uprx65_rxi5_handler + trampoline RX65N_TXI5_IRQ, _uprx65_txi5_handler +#endif +#ifdef CONFIG_RX65N_SCI6 + trampoline RX65N_RXI6_IRQ, _uprx65_rxi6_handler + trampoline RX65N_TXI6_IRQ, _uprx65_txi6_handler +#endif +#ifdef CONFIG_RX65N_LVD1 + trampoline RX65N_LVD1_IRQ, _uprx65_lvd1_handler +#endif +#ifdef CONFIG_RX65N_LVD2 + trampoline RX65N_LVD2_IRQ, _uprx65_lvd2_handler +#endif +#ifdef CONFIG_RX65N_USB0_R0 + trampoline RX65N_USBR0_IRQ, _uprx65_usbr0_handler +#endif +#ifdef CONFIG_RX65N_RTC + trampoline RX65N_ALM_IRQ, _uprx65_alm_handler + trampoline RX65N_PRD_IRQ, _uprx65_prd_handler +#endif +#ifdef CONFIG_RX65N_IWDT + trampoline RX65N_IWUNI_IRQ, _uprx65_iwuni_handler +#endif +#ifdef CONFIG_RX65N_WDT + trampoline RX65N_WUNI_IRQ, _uprx65_wuni_handler +#endif +#ifdef CONFIG_RX65N_PDC + trampoline RX65N_PCDFI_IRQ, _uprx65_pcdfi_handler +#endif +#ifdef CONFIG_RX65N_SCI7 + trampoline RX65N_RXI7_IRQ, _uprx65_rxi7_handler + trampoline RX65N_TXI7_IRQ, _uprx65_txi7_handler +#endif +#ifdef CONFIG_RX65N_SCI8 + trampoline RX65N_RXI8_IRQ, _uprx65_rxi8_handler + trampoline RX65N_TXI8_IRQ, _uprx65_txi8_handler +#endif +#ifdef CONFIG_RX65N_SCI9 + trampoline RX65N_RXI9_IRQ, _uprx65_rxi9_handler + trampoline RX65N_TXI9_IRQ, _uprx65_txi9_handler +#endif +#ifdef CONFIG_RX65N_SCI10 + trampoline RX65N_RXI10_IRQ, _uprx65_rxi10_handler + trampoline RX65N_TXI10_IRQ, _uprx65_txi10_handler +#endif +#if defined(CONFIG_RX65N_IRQ_GROUP) +_uprx65_groupbe0_handler: + +/* TODO: Please write the others with + * definition RX65N_XXX_IRQ in irq.h as IRQ number + */ + + RTE + NOP +_uprx65_groupbl2_handler: + +/* TODO: Please write the others with + * definition RX65N_XXX_IRQ in irq.h as IRQ number + */ + + RTE + NOP +#endif +#ifdef CONFIG_RX65N_RSPI2 + trampoline RX65N_SPRI2_IRQ, _uprx65_spri2_handler + trampoline RX65N_SPTI2_IRQ, _uprx65_spti2_handler +#endif +#if defined(CONFIG_RX65N_IRQ_GROUP) +_uprx65_groupbl0_handler: +#ifdef CONFIG_RX65N_SCI0 + multi_switching RX65N_GRPBL0_ADDR, RX65N_GENBL0_ADDR, 0, RX65N_TEI0_IRQ + multi_switching RX65N_GRPBL0_ADDR, RX65N_GENBL0_ADDR, 1, RX65N_ERI0_IRQ +#endif +#ifdef CONFIG_RX65N_SCI1 + multi_switching RX65N_GRPBL0_ADDR, RX65N_GENBL0_ADDR, 2, RX65N_TEI1_IRQ + multi_switching RX65N_GRPBL0_ADDR, RX65N_GENBL0_ADDR, 3, RX65N_ERI1_IRQ +#endif +#ifdef CONFIG_RX65N_SCI2 + multi_switching RX65N_GRPBL0_ADDR, RX65N_GENBL0_ADDR, 4, RX65N_TEI2_IRQ + multi_switching RX65N_GRPBL0_ADDR, RX65N_GENBL0_ADDR, 5, RX65N_ERI2_IRQ +#endif +#ifdef CONFIG_RX65N_SCI3 + multi_switching RX65N_GRPBL0_ADDR, RX65N_GENBL0_ADDR, 6, RX65N_TEI3_IRQ + multi_switching RX65N_GRPBL0_ADDR, RX65N_GENBL0_ADDR, 7, RX65N_ERI3_IRQ +#endif +#ifdef CONFIG_RX65N_SCI4 + multi_switching RX65N_GRPBL0_ADDR, RX65N_GENBL0_ADDR, 8, RX65N_TEI4_IRQ + multi_switching RX65N_GRPBL0_ADDR, RX65N_GENBL0_ADDR, 9, RX65N_ERI4_IRQ +#endif +#ifdef CONFIG_RX65N_SCI5 + multi_switching RX65N_GRPBL0_ADDR, RX65N_GENBL0_ADDR, 10, RX65N_TEI5_IRQ + multi_switching RX65N_GRPBL0_ADDR, RX65N_GENBL0_ADDR, 11, RX65N_ERI5_IRQ +#endif +#ifdef CONFIG_RX65N_SCI6 + multi_switching RX65N_GRPBL0_ADDR, RX65N_GENBL0_ADDR, 12, RX65N_TEI6_IRQ + multi_switching RX65N_GRPBL0_ADDR, RX65N_GENBL0_ADDR, 13, RX65N_ERI6_IRQ +#endif +#ifdef CONFIG_RX65N_SCI7 + multi_switching RX65N_GRPBL0_ADDR, RX65N_GENBL0_ADDR, 14, RX65N_TEI7_IRQ + multi_switching RX65N_GRPBL0_ADDR, RX65N_GENBL0_ADDR, 15, RX65N_ERI7_IRQ +#endif +#ifdef CONFIG_RX65N_SCI12 + multi_switching RX65N_GRPBL0_ADDR, RX65N_GENBL0_ADDR, 16, RX65N_TEI12_IRQ + multi_switching RX65N_GRPBL0_ADDR, RX65N_GENBL0_ADDR, 17, RX65N_ERI12_IRQ +#endif + +/* TODO: Please write the others with + * definition RX65N_XXX_IRQ in irq.h as IRQ number + */ + + RTE + NOP +_uprx65_groupbl1_handler: +#ifdef CONFIG_RX65N_SCI8 + multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 24, RX65N_TEI8_IRQ + multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 25, RX65N_ERI8_IRQ +#endif /* CONFIG_RX65N_SCI8 */ + +#ifdef CONFIG_RX65N_SCI9 + multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 26, RX65N_TEI9_IRQ + multi_switching RX65N_GRPBL1_ADDR, RX65N_GENBL1_ADDR, 27, RX65N_ERI9_IRQ +#endif /* CONFIG_RX65N_SCI9 */ + +/* TODO: Please write the others with + * definition RX65N_XXX_IRQ in irq.h as IRQ number + */ + + RTE + NOP +_uprx65_groupal0_handler: +#ifdef CONFIG_RX65N_SCI10 + multi_switching RX65N_GRPAL0_ADDR, RX65N_GENAL0_ADDR, 8, RX65N_TEI10_IRQ + multi_switching RX65N_GRPAL0_ADDR, RX65N_GENAL0_ADDR, 9, RX65N_ERI10_IRQ +#endif /* CONFIG_RX65N_SCI10 */ + +#ifdef CONFIG_RX65N_SCI11 + multi_switching RX65N_GRPAL0_ADDR, RX65N_GENAL0_ADDR, 12, RX65N_TEI11_IRQ + multi_switching RX65N_GRPAL0_ADDR, RX65N_GENAL0_ADDR, 13, RX65N_ERI11_IRQ +#endif /* CONFIG_RX65N_SCI11 */ + +/* TODO: Please write the others with + * definition RX65N_XXX_IRQ in irq.h as IRQ number + */ + + RTE + NOP +_uprx65_groupal1_handler: +#ifdef CONFIG_RX65N_EMAC0 + multi_switching RX65N_GRPAL1_ADDR, RX65N_GENAL1_ADDR, 4, RX65N_ETH_IRQ +#endif /* CONFIG_RX65N_EMAC0 */ + +/* TODO: Please write the others with definition RX65N_XXX_IRQ in + * irq.h as IRQ number */ + + RTE + NOP +#endif /* CONFIG_RX65N_IRQ_GROUP */ + +#ifdef CONFIG_RX65N_SCI11 + trampoline RX65N_RXI11_IRQ, _uprx65_rxi11_handler + trampoline RX65N_TXI11_IRQ, _uprx65_txi11_handler +#endif +#ifdef CONFIG_RX65N_SCI12 + trampoline RX65N_RXI12_IRQ, _uprx65_rxi12_handler + trampoline RX65N_TXI12_IRQ, _uprx65_txi12_handler +#endif +#ifdef CONFIG_RX65N_DMAC + trampoline RX65N_DMAC0I_IRQ, _uprx65_dmac0i_handler + trampoline RX65N_DMAC1I_IRQ, _uprx65_dmac1i_handler + trampoline RX65N_DMAC2I_IRQ, _uprx65_dmac2i_handler + trampoline RX65N_DMAC3I_IRQ, _uprx65_dmac3i_handler + trampoline RX65N_DMAC74I_IRQ, _uprx65_dmac74i_handler +#endif +#ifdef CONFIG_RX65N_OST + trampoline RX65N_OSTD1_IRQ, _uprx65_ostdi_handler +#endif +#ifdef CONFIG_RX65N_EXDMAC + trampoline RX65N_EXDMAC0I_IRQ, _uprx65_exdmac0i_handler + trampoline RX65N_EXDMAC1I_IRQ, _uprx65_exdmac1i_handler +#endif + +#ifdef CONFIG_RX65N_PERIB + trampoline RX65N_INTB128_IRQ, _uprx65_intb128_handler + trampoline RX65N_INTB129_IRQ, _uprx65_intb129_handler + trampoline RX65N_INTB130_IRQ, _uprx65_intb130_handler + trampoline RX65N_INTB131_IRQ, _uprx65_intb131_handler + trampoline RX65N_INTB132_IRQ, _uprx65_intb132_handler + trampoline RX65N_INTB133_IRQ, _uprx65_intb133_handler + trampoline RX65N_INTB134_IRQ, _uprx65_intb134_handler + trampoline RX65N_INTB135_IRQ, _uprx65_intb135_handler + trampoline RX65N_INTB136_IRQ, _uprx65_intb136_handler + trampoline RX65N_INTB137_IRQ, _uprx65_intb137_handler + trampoline RX65N_INTB138_IRQ, _uprx65_intb138_handler + trampoline RX65N_INTB139_IRQ, _uprx65_intb139_handler + trampoline RX65N_INTB140_IRQ, _uprx65_intb140_handler + trampoline RX65N_INTB141_IRQ, _uprx65_intb141_handler + trampoline RX65N_INTB142_IRQ, _uprx65_intb142_handler + trampoline RX65N_INTB143_IRQ, _uprx65_intb143_handler + trampoline RX65N_INTB144_IRQ, _uprx65_intb144_handler + trampoline RX65N_INTB145_IRQ, _uprx65_intb145_handler + trampoline RX65N_INTB146_IRQ, _uprx65_intb146_handler + trampoline RX65N_INTB147_IRQ, _uprx65_intb147_handler + trampoline RX65N_INTB148_IRQ, _uprx65_intb148_handler + trampoline RX65N_INTB149_IRQ, _uprx65_intb149_handler + trampoline RX65N_INTB150_IRQ, _uprx65_intb150_handler + trampoline RX65N_INTB151_IRQ, _uprx65_intb151_handler + trampoline RX65N_INTB152_IRQ, _uprx65_intb152_handler + trampoline RX65N_INTB153_IRQ, _uprx65_intb153_handler + trampoline RX65N_INTB154_IRQ, _uprx65_intb154_handler + trampoline RX65N_INTB155_IRQ, _uprx65_intb155_handler + trampoline RX65N_INTB156_IRQ, _uprx65_intb156_handler + trampoline RX65N_INTB157_IRQ, _uprx65_intb157_handler + trampoline RX65N_INTB158_IRQ, _uprx65_intb158_handler + trampoline RX65N_INTB159_IRQ, _uprx65_intb159_handler + trampoline RX65N_INTB160_IRQ, _uprx65_intb160_handler + trampoline RX65N_INTB161_IRQ, _uprx65_intb161_handler + trampoline RX65N_INTB162_IRQ, _uprx65_intb162_handler + trampoline RX65N_INTB163_IRQ, _uprx65_intb163_handler + trampoline RX65N_INTB164_IRQ, _uprx65_intb164_handler + trampoline RX65N_INTB165_IRQ, _uprx65_intb165_handler + trampoline RX65N_INTB166_IRQ, _uprx65_intb166_handler + trampoline RX65N_INTB167_IRQ, _uprx65_intb167_handler + trampoline RX65N_INTB168_IRQ, _uprx65_intb168_handler + trampoline RX65N_INTB169_IRQ, _uprx65_intb169_handler + trampoline RX65N_INTB170_IRQ, _uprx65_intb170_handler + trampoline RX65N_INTB171_IRQ, _uprx65_intb171_handler + trampoline RX65N_INTB172_IRQ, _uprx65_intb172_handler + trampoline RX65N_INTB173_IRQ, _uprx65_intb173_handler + trampoline RX65N_INTB174_IRQ, _uprx65_intb174_handler + trampoline RX65N_INTB175_IRQ, _uprx65_intb175_handler + trampoline RX65N_INTB176_IRQ, _uprx65_intb176_handler + trampoline RX65N_INTB177_IRQ, _uprx65_intb177_handler + trampoline RX65N_INTB178_IRQ, _uprx65_intb178_handler + trampoline RX65N_INTB179_IRQ, _uprx65_intb179_handler + trampoline RX65N_INTB180_IRQ, _uprx65_intb180_handler + trampoline RX65N_INTB181_IRQ, _uprx65_intb181_handler + trampoline RX65N_INTB182_IRQ, _uprx65_intb182_handler + trampoline RX65N_INTB183_IRQ, _uprx65_intb183_handler + trampoline RX65N_INTB184_IRQ, _uprx65_intb184_handler + trampoline RX65N_INTB185_IRQ, _uprx65_intb185_handler + trampoline RX65N_INTB186_IRQ, _uprx65_intb186_handler + trampoline RX65N_INTB187_IRQ, _uprx65_intb187_handler + trampoline RX65N_INTB188_IRQ, _uprx65_intb188_handler + trampoline RX65N_INTB189_IRQ, _uprx65_intb189_handler + trampoline RX65N_INTB190_IRQ, _uprx65_intb190_handler + trampoline RX65N_INTB191_IRQ, _uprx65_intb191_handler + trampoline RX65N_INTB192_IRQ, _uprx65_intb192_handler + trampoline RX65N_INTB193_IRQ, _uprx65_intb193_handler + trampoline RX65N_INTB194_IRQ, _uprx65_intb194_handler + trampoline RX65N_INTB195_IRQ, _uprx65_intb195_handler + trampoline RX65N_INTB196_IRQ, _uprx65_intb196_handler + trampoline RX65N_INTB197_IRQ, _uprx65_intb197_handler + trampoline RX65N_INTB198_IRQ, _uprx65_intb198_handler + trampoline RX65N_INTB199_IRQ, _uprx65_intb199_handler + trampoline RX65N_INTB200_IRQ, _uprx65_intb200_handler + trampoline RX65N_INTB201_IRQ, _uprx65_intb201_handler + trampoline RX65N_INTB202_IRQ, _uprx65_intb202_handler + trampoline RX65N_INTB203_IRQ, _uprx65_intb203_handler + trampoline RX65N_INTB204_IRQ, _uprx65_intb204_handler + trampoline RX65N_INTB205_IRQ, _uprx65_intb205_handler + trampoline RX65N_INTB206_IRQ, _uprx65_intb206_handler + trampoline RX65N_INTB207_IRQ, _uprx65_intb207_handler +#endif +#ifdef CONFIG_RX65N_PERIA + trampoline RX65N_INTA208_IRQ, _uprx65_inta208_handler + trampoline RX65N_INTA209_IRQ, _uprx65_inta209_handler + trampoline RX65N_INTA210_IRQ, _uprx65_inta210_handler + trampoline RX65N_INTA211_IRQ, _uprx65_inta211_handler + trampoline RX65N_INTA212_IRQ, _uprx65_inta212_handler + trampoline RX65N_INTA213_IRQ, _uprx65_inta213_handler + trampoline RX65N_INTA214_IRQ, _uprx65_inta214_handler + trampoline RX65N_INTA215_IRQ, _uprx65_inta215_handler + trampoline RX65N_INTA216_IRQ, _uprx65_inta216_handler + trampoline RX65N_INTA217_IRQ, _uprx65_inta217_handler + trampoline RX65N_INTA218_IRQ, _uprx65_inta218_handler + trampoline RX65N_INTA219_IRQ, _uprx65_inta219_handler + trampoline RX65N_INTA220_IRQ, _uprx65_inta220_handler + trampoline RX65N_INTA221_IRQ, _uprx65_inta221_handler + trampoline RX65N_INTA222_IRQ, _uprx65_inta222_handler + trampoline RX65N_INTA223_IRQ, _uprx65_inta223_handler + trampoline RX65N_INTA224_IRQ, _uprx65_inta224_handler + trampoline RX65N_INTA225_IRQ, _uprx65_inta225_handler + trampoline RX65N_INTA226_IRQ, _uprx65_inta226_handler + trampoline RX65N_INTA227_IRQ, _uprx65_inta227_handler + trampoline RX65N_INTA228_IRQ, _uprx65_inta228_handler + trampoline RX65N_INTA229_IRQ, _uprx65_inta229_handler + trampoline RX65N_INTA230_IRQ, _uprx65_inta230_handler + trampoline RX65N_INTA231_IRQ, _uprx65_inta231_handler + trampoline RX65N_INTA232_IRQ, _uprx65_inta232_handler + trampoline RX65N_INTA233_IRQ, _uprx65_inta233_handler + trampoline RX65N_INTA234_IRQ, _uprx65_inta234_handler + trampoline RX65N_INTA235_IRQ, _uprx65_inta235_handler + trampoline RX65N_INTA236_IRQ, _uprx65_inta236_handler + trampoline RX65N_INTA237_IRQ, _uprx65_inta237_handler + trampoline RX65N_INTA238_IRQ, _uprx65_inta238_handler + trampoline RX65N_INTA239_IRQ, _uprx65_inta239_handler + trampoline RX65N_INTA240_IRQ, _uprx65_inta240_handler + trampoline RX65N_INTA241_IRQ, _uprx65_inta241_handler + trampoline RX65N_INTA242_IRQ, _uprx65_inta242_handler + trampoline RX65N_INTA243_IRQ, _uprx65_inta243_handler + trampoline RX65N_INTA244_IRQ, _uprx65_inta244_handler + trampoline RX65N_INTA245_IRQ, _uprx65_inta245_handler + trampoline RX65N_INTA246_IRQ, _uprx65_inta246_handler + trampoline RX65N_INTA247_IRQ, _uprx65_inta247_handler + trampoline RX65N_INTA248_IRQ, _uprx65_inta248_handler + trampoline RX65N_INTA249_IRQ, _uprx65_inta249_handler + trampoline RX65N_INTA250_IRQ, _uprx65_inta250_handler + trampoline RX65N_INTA251_IRQ, _uprx65_inta251_handler + trampoline RX65N_INTA252_IRQ, _uprx65_inta252_handler + trampoline RX65N_INTA253_IRQ, _uprx65_inta253_handler + trampoline RX65N_INTA254_IRQ, _uprx65_inta254_handler + trampoline RX65N_INTA255_IRQ, _uprx65_inta255_handler +#endif + +/**************************************************************************** + * Data + ***************************************************************************/ + +/**************************************************************************** + * Name: g_intstackalloc/g_intstackbase + * + * Description: + * Should not happen + * + ***************************************************************************/ + + .bss + .align 2 + +#if CONFIG_ARCH_INTERRUPTSTACK > 3 + .bss + .align 2 + .global _g_intstackalloc + .type _g_intstackalloc, object + .global _g_intstackbase + .type _g_intstackbase, object +_g_intstackalloc: + .skip ((CONFIG_ARCH_INTERRUPTSTACK & ~3) - 4) +_g_intstackbase: + .skip 2 + .size _g_intstackbase, 4 + .size _g_intstackalloc, (CONFIG_ARCH_INTERRUPTSTACK & ~3) +#endif + +/**************************************************************************** + * Interrupt Vectors + ***************************************************************************/ + + .section .rvectors + +/**************************************************************************** + * Name: __int_vector_table + * + * Description: + * Interrupt vector table + ***************************************************************************/ + + .global __int_vector_table + .type __int_vector_table, % object + +__int_vector_table: + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#ifdef CONFIG_BSC + .long _uprx65_buserr_handler +#else + .long _uprx65_invalid_handler +#endif + .long _uprx65_invalid_handler +#ifdef CONFIG_RAM + .long _uprx65_ramerr_handler +#else + .long _uprx65_invalid_handler +#endif + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#ifdef CONFIG_FCU + .long _uprx65_fiferr_handler +#else + .long _uprx65_invalid_handler +#endif + .long _uprx65_invalid_handler +#ifdef CONFIG_FRDYI + .long _uprx65_frdyi_handler +#else + .long _uprx65_invalid_handler +#endif + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_swint2_handler + .long _uprx65_swint_handler + .long _uprx65_cmi0_handler +#ifdef CONFIG_RX65N_CMT1 + .long _uprx65_cmi1_handler +#else + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_CMTW0 + .long _uprx65_cmwi0_handler +#else + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_CMTW1 + .long _uprx65_cmwi1_handler +#else + .long _uprx65_invalid_handler +#endif + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#ifdef CONFIG_RX65N_USB0 + .long _uprx65_d0fifo0_handler + .long _uprx65_d1fifo0_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#ifdef CONFIG_RX65N_RSPI0 + .long _uprx65_spri0_handler + .long _uprx65_spti0_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_RSPI1 + .long _uprx65_spri1_handler + .long _uprx65_spti1_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_QSPI + .long _uprx65_spri_handler + .long _uprx65_spti_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_SDHI + .long _uprx65_sbfai_handler +#else + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_MMCIF + .long _uprx65_mbfai_handler +#else + .long _uprx65_invalid_handler +#endif + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#ifdef CONFIG_RX65N_RIIC1 + .long _uprx65_rxii1_handler + .long _uprx65_txii1_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_RIIC0 + .long _uprx65_rxii0_handler + .long _uprx65_txii0_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_RIIC2 + .long _uprx65_rxii2_handler + .long _uprx65_txii2_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#ifdef CONFIG_RX65N_SCI0 + .long _uprx65_rxi0_handler + .long _uprx65_txi0_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_SCI1 + .long _uprx65_rxi1_handler + .long _uprx65_txi1_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_SCI2 + .long _uprx65_rxi2_handler + .long _uprx65_txi2_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#if defined(CONFIG_ICU) || defined(CONFIG_RX65N_ICU) + .long _uprx65_irq0_handler + .long _uprx65_irq1_handler + .long _uprx65_irq2_handler + .long _uprx65_irq3_handler + .long _uprx65_irq4_handler + .long _uprx65_irq5_handler + .long _uprx65_irq6_handler + .long _uprx65_irq7_handler + .long _uprx65_irq8_handler + .long _uprx65_irq9_handler + .long _uprx65_irq10_handler + .long _uprx65_irq11_handler + .long _uprx65_irq12_handler + .long _uprx65_irq13_handler + .long _uprx65_irq14_handler + .long _uprx65_irq15_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_SCI3 + .long _uprx65_rxi3_handler + .long _uprx65_txi3_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_SCI4 + .long _uprx65_rxi4_handler + .long _uprx65_txi4_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_SCI5 + .long _uprx65_rxi5_handler + .long _uprx65_txi5_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_SCI6 + .long _uprx65_rxi6_handler + .long _uprx65_txi6_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_LVD1 + .long _uprx65_lvd1_handler +#else + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_LVD2 + .long _uprx65_lvd2_handler +#else + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_USB0_R0 + .long _uprx65_usbr0_handler +#else + .long _uprx65_invalid_handler +#endif + .long _uprx65_invalid_handler +#ifdef CONFIG_RX65N_RTC + .long _uprx65_alm_handler + .long _uprx65_prd_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif + .long _uprx65_invalid_handler +#ifdef CONFIG_RX65N_IWDT + .long _uprx65_iwuni_handler +#else + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_WDT + .long _uprx65_wuni_handler +#else + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_PDC + .long _uprx65_pcdfi_handler +#else + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_SCI7 + .long _uprx65_rxi7_handler + .long _uprx65_txi7_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_SCI8 + .long _uprx65_rxi8_handler + .long _uprx65_txi8_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_SCI9 + .long _uprx65_rxi9_handler + .long _uprx65_txi9_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_SCI10 + .long _uprx65_rxi10_handler + .long _uprx65_txi10_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#if defined(CONFIG_RX65N_IRQ_GROUP) + .long _uprx65_groupbe0_handler + .long _uprx65_groupbl2_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_RSPI2 + .long _uprx65_spri2_handler + .long _uprx65_spti2_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#if defined(CONFIG_RX65N_IRQ_GROUP) + .long _uprx65_groupbl0_handler + .long _uprx65_groupbl1_handler + .long _uprx65_groupal0_handler + .long _uprx65_groupal1_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_SCI11 + .long _uprx65_rxi11_handler + .long _uprx65_txi11_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_SCI12 + .long _uprx65_rxi12_handler + .long _uprx65_txi12_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#ifdef CONFIG_RX65N_DMAC + .long _uprx65_dmac0i_handler + .long _uprx65_dmac1i_handler + .long _uprx65_dmac2i_handler + .long _uprx65_dmac3i_handler + .long _uprx65_dmac74i_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_OST + .long _uprx65_ostdi_handler +#else + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_EXDMAC + .long _uprx65_exdmac0i_handler + .long _uprx65_exdmac1i_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif + +#ifdef CONFIG_RX65N_PERIB + .long _uprx65_intb128_handler + .long _uprx65_intb129_handler + .long _uprx65_intb130_handler + .long _uprx65_intb131_handler + .long _uprx65_intb132_handler + .long _uprx65_intb133_handler + .long _uprx65_intb134_handler + .long _uprx65_intb135_handler + .long _uprx65_intb136_handler + .long _uprx65_intb137_handler + .long _uprx65_intb138_handler + .long _uprx65_intb139_handler + .long _uprx65_intb140_handler + .long _uprx65_intb141_handler + .long _uprx65_intb142_handler + .long _uprx65_intb143_handler + .long _uprx65_intb144_handler + .long _uprx65_intb145_handler + .long _uprx65_intb146_handler + .long _uprx65_intb147_handler + .long _uprx65_intb148_handler + .long _uprx65_intb149_handler + .long _uprx65_intb150_handler + .long _uprx65_intb151_handler + .long _uprx65_intb152_handler + .long _uprx65_intb153_handler + .long _uprx65_intb154_handler + .long _uprx65_intb155_handler + .long _uprx65_intb156_handler + .long _uprx65_intb157_handler + .long _uprx65_intb158_handler + .long _uprx65_intb159_handler + .long _uprx65_intb160_handler + .long _uprx65_intb161_handler + .long _uprx65_intb162_handler + .long _uprx65_intb163_handler + .long _uprx65_intb164_handler + .long _uprx65_intb165_handler + .long _uprx65_intb166_handler + .long _uprx65_intb167_handler + .long _uprx65_intb168_handler + .long _uprx65_intb169_handler + .long _uprx65_intb170_handler + .long _uprx65_intb171_handler + .long _uprx65_intb172_handler + .long _uprx65_intb173_handler + .long _uprx65_intb174_handler + .long _uprx65_intb175_handler + .long _uprx65_intb176_handler + .long _uprx65_intb177_handler + .long _uprx65_intb178_handler + .long _uprx65_intb179_handler + .long _uprx65_intb180_handler + .long _uprx65_intb181_handler + .long _uprx65_intb182_handler + .long _uprx65_intb183_handler + .long _uprx65_intb184_handler + .long _uprx65_intb185_handler + .long _uprx65_intb186_handler + .long _uprx65_intb187_handler + .long _uprx65_intb188_handler + .long _uprx65_intb189_handler + .long _uprx65_intb190_handler + .long _uprx65_intb191_handler + .long _uprx65_intb192_handler + .long _uprx65_intb193_handler + .long _uprx65_intb194_handler + .long _uprx65_intb195_handler + .long _uprx65_intb196_handler + .long _uprx65_intb197_handler + .long _uprx65_intb198_handler + .long _uprx65_intb199_handler + .long _uprx65_intb200_handler + .long _uprx65_intb201_handler + .long _uprx65_intb202_handler + .long _uprx65_intb203_handler + .long _uprx65_intb204_handler + .long _uprx65_intb205_handler + .long _uprx65_intb206_handler + .long _uprx65_intb207_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif +#ifdef CONFIG_RX65N_PERIA + .long _uprx65_inta208_handler + .long _uprx65_inta209_handler + .long _uprx65_inta210_handler + .long _uprx65_inta211_handler + .long _uprx65_inta212_handler + .long _uprx65_inta213_handler + .long _uprx65_inta214_handler + .long _uprx65_inta215_handler + .long _uprx65_inta216_handler + .long _uprx65_inta217_handler + .long _uprx65_inta218_handler + .long _uprx65_inta219_handler + .long _uprx65_inta220_handler + .long _uprx65_inta221_handler + .long _uprx65_inta222_handler + .long _uprx65_inta223_handler + .long _uprx65_inta224_handler + .long _uprx65_inta225_handler + .long _uprx65_inta226_handler + .long _uprx65_inta227_handler + .long _uprx65_inta228_handler + .long _uprx65_inta229_handler + .long _uprx65_inta230_handler + .long _uprx65_inta231_handler + .long _uprx65_inta232_handler + .long _uprx65_inta233_handler + .long _uprx65_inta234_handler + .long _uprx65_inta235_handler + .long _uprx65_inta236_handler + .long _uprx65_inta237_handler + .long _uprx65_inta238_handler + .long _uprx65_inta239_handler + .long _uprx65_inta240_handler + .long _uprx65_inta241_handler + .long _uprx65_inta242_handler + .long _uprx65_inta243_handler + .long _uprx65_inta244_handler + .long _uprx65_inta245_handler + .long _uprx65_inta246_handler + .long _uprx65_inta247_handler + .long _uprx65_inta248_handler + .long _uprx65_inta249_handler + .long _uprx65_inta250_handler + .long _uprx65_inta251_handler + .long _uprx65_inta252_handler + .long _uprx65_inta253_handler + .long _uprx65_inta254_handler + .long _uprx65_inta255_handler +#else + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler + .long _uprx65_invalid_handler +#endif + .size __int_vector_table, . - __int_vector_table + .end + +/**************************************************************************** + * EOF + ***************************************************************************/ diff --git a/arch/renesas/src/rx65n/rx65n_vector_table.c b/arch/renesas/src/rx65n/rx65n_vector_table.c new file mode 100644 index 00000000000..e820bbd0b01 --- /dev/null +++ b/arch/renesas/src/rx65n/rx65n_vector_table.c @@ -0,0 +1,248 @@ +/**************************************************************************** + * arch/renesas/src/rx65n/rx65n_vector_table.c + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + +#include "rx65n_macrodriver.h" +#include "chip.h" +#include "stdint.h" + +/**************************************************************************** + * Pre-processor Definitions + ****************************************************************************/ + +#define OFS_REG __attribute__ ((section (".ofs1"))) /* 0xfe7f5d00 */ +#define OFS_TMINF __attribute__ ((section (".ofs2"))) /* 0xfe7f5d10 */ +#define OFS_SPCC __attribute__ ((section (".ofs3"))) /* 0xfe7f5d40 */ +#define OFS_TMEF __attribute__ ((section (".ofs4"))) /* 0xfe7f5d48 */ +#define OFS_OSIS __attribute__ ((section (".ofs5"))) /* 0xfe7f5d50 */ +#define OFS_FAW __attribute__ ((section (".ofs6"))) /* 0xfe7f5d64 */ +#define OFS_ROMCODE __attribute__ ((section (".ofs7"))) /* 0xfe7f5d70 */ + +/* SPCC register */ + +const unsigned long __spccreg OFS_SPCC = 0xffffffff; + +/* TMEF register */ + +const unsigned long __tmefreg OFS_TMEF = 0xffffffff; + +/* OSIS register (ID codes) */ + +const unsigned long __osisreg[4] OFS_OSIS = +{ + 0xffffffff, + 0xffffffff, + 0xffffffff, + 0xffffffff +}; + +/* TMINF register */ + +const unsigned long __tminfreg OFS_TMINF = 0xffffffff; + +/* FAW register */ + +const unsigned long __fawreg OFS_FAW = 0xffffffff; + +/* ROMCODE register */ + +const unsigned long __romcodereg OFS_ROMCODE = 0xffffffff; + +/* MDE register (Single Chip Mode) */ + +#ifdef __RX_BIG_ENDIAN__ +const unsigned long __mdereg OFS_REG = 0xfffffff8; /* big */ +#else +const unsigned long __mdereg OFS_REG = 0xffffffff; /* little */ +#endif + +const unsigned long __ofs0reg OFS_REG = 0xffffffff; /* OFS0 register */ +const unsigned long __ofs1reg OFS_REG = 0xffffffff; /* OFS1 register */ + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: r_undefined_exception + * + * Description: + * Handler for undefined exception + ****************************************************************************/ + +void r_undefined_exception(void) +{ +#ifdef __USE_DEBUG_NOP_FOR_BREAKPOINTS + __asm("nop"); +#endif +} + +/**************************************************************************** + * Name: r_reserved_exception + * + * Description: + * Handler for reserved exception + ****************************************************************************/ + +void r_reserved_exception(void) +{ +#ifdef __USE_DEBUG_NOP_FOR_BREAKPOINTS + __asm("nop"); +#endif +} + +/**************************************************************************** + * Name: r_nmi_exception + * + * Description: + * Handler for nmi exception + ****************************************************************************/ + +void r_nmi_exception(void) +{ +#ifdef __USE_DEBUG_NOP_FOR_BREAKPOINTS + __asm("nop"); +#endif +} + +/**************************************************************************** + * Name: r_brk_exception + * + * Description: + * Handler for brk exception + ****************************************************************************/ + +void r_brk_exception(void) +{ +#ifdef __USE_DEBUG_NOP_FOR_BREAKPOINTS + __asm("nop"); +#endif +} + +/**************************************************************************** + * Name: r_privileged_exception + * + * Description: + * Handler for privileged exception + ****************************************************************************/ + +void r_privileged_exception(void) +{ +#ifdef __USE_DEBUG_NOP_FOR_BREAKPOINTS + __asm("nop"); +#endif +} + +/**************************************************************************** + * Name: r_access_exception + * + * Description: + * Handler for access exception + ****************************************************************************/ + +void r_access_exception(void) +{ +#ifdef __USE_DEBUG_NOP_FOR_BREAKPOINTS + __asm("nop"); +#endif +} +/**************************************************************************** + * Name: r_floatingpoint_exception + * + * Description: + * Handler for floating point exception + ****************************************************************************/ + +void r_floatingpoint_exception(void) +{ +#ifdef __USE_DEBUG_NOP_FOR_BREAKPOINTS + __asm("nop"); +#endif +} + +#define EXVECT_SECT __attribute__ ((section (".exvectors"))) + +const void *except_vectors[] EXVECT_SECT = +{ + r_reserved_exception, /* 0xffffff80 Reserved */ + r_reserved_exception, /* 0xffffff84 Reserved */ + r_reserved_exception, /* 0xffffff88 Reserved */ + r_reserved_exception, /* 0xffffff8c Reserved */ + r_reserved_exception, /* 0xffffff90 Reserved */ + r_reserved_exception, /* 0xffffff94 Reserved */ + r_reserved_exception, /* 0xffffff98 Reserved */ + r_reserved_exception, /* 0xffffff9c Reserved */ + r_reserved_exception, /* 0xffffffa0 Reserved */ + r_reserved_exception, /* 0xffffffa4 Reserved */ + r_reserved_exception, /* 0xffffffa8 Reserved */ + r_reserved_exception, /* 0xffffffac Reserved */ + r_reserved_exception, /* 0xffffffb0 Reserved */ + r_reserved_exception, /* 0xffffffb4 Reserved */ + r_reserved_exception, /* 0xffffffb8 Reserved */ + r_reserved_exception, /* 0xffffffbc Reserved */ + r_reserved_exception, /* 0xffffffc0 Reserved */ + r_reserved_exception, /* 0xffffffc4 Reserved */ + r_reserved_exception, /* 0xffffffc8 Reserved */ + r_reserved_exception, /* 0xffffffcc Reserved */ + r_privileged_exception, /* 0xffffffd0 Exception */ + r_access_exception, /* 0xffffffd4 Exception */ + r_reserved_exception, /* 0xffffffd8 Reserved */ + r_undefined_exception, /* 0xffffffdc Exception */ + r_reserved_exception, /* 0xffffffe0 Reserved */ + r_floatingpoint_exception, /* 0xffffffe4 Exception */ + r_undefined_exception, /* 0xffffffe8 Reserved */ + r_undefined_exception, /* 0xffffffec Reserved */ + r_undefined_exception, /* 0xfffffff0 Reserved */ + r_undefined_exception, /* 0xfffffff4 Reserved */ + r_nmi_exception /* 0xfffffff8 NMI */ +}; + +#define FVECT_SECT __attribute__ ((section (".fvectors"))) +extern void _start(void); /* defined in rx65n_head.S */ +const void *hardware_vectors[] FVECT_SECT = +{ + /* 0xfffffffc RESET */ + + _start /* Power On Reset PC */ +}; + +#define RVECT_SECT __attribute__ ((section (".rvectors"))) +const void *relocatable_vectors[256] RVECT_SECT = +{ + 0 +}; diff --git a/boards/Kconfig b/boards/Kconfig index ece2fe7c07c..473fbf1f6cc 100644 --- a/boards/Kconfig +++ b/boards/Kconfig @@ -1159,6 +1159,41 @@ config ARCH_BOARD_QEMU_I486 Port of NuttX to QEMU in i486 mode. This port will also run on real i486 hardwared (Google the Bifferboard). +config ARCH_BOARD_RX65N + bool "RX65N renesas board" + depends on ARCH_CHIP_R5F565NEDDFC + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + ---help--- + This is a port of the renesas RX65N on the Renesas RX65N board. + STATUS: Work has just began on this port. + +config ARCH_BOARD_RX65N_RSK1MB + bool "RX65N on RSKRX65N-1MB renesas board" + depends on ARCH_CHIP_R5F565NEDDFC + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + ---help--- + This is a port of the renesas RX65N on the Renesas RX65N board. + STATUS: Work has just began on this port. + +config ARCH_BOARD_RX65N_RSK2MB + bool "RX65N on RSKRX65N-2MB renesas board" + depends on ARCH_CHIP_R5F565NEHDFC + select ARCH_HAVE_LEDS + select ARCH_HAVE_BUTTONS + ---help--- + This is a port of the renesas RX65N on the Renesas RX65N board. + STATUS: Work has just began on this port. + +config ARCH_BOARD_RX65N_GRROSE + bool "RX65N on GR-ROSE renesas board" + depends on ARCH_CHIP_R5F565NEHDFP + select ARCH_HAVE_LEDS + ---help--- + This is a port of the renesas RX65N on the Renesas RX65N board. + STATUS: Work has just began on this port. + config ARCH_BOARD_S32K118EVB bool "NXP S32K118EVB" depends on ARCH_CHIP_S32K118 @@ -2022,6 +2057,10 @@ config ARCH_BOARD default "pic32mx7mmb" if ARCH_BOARD_PIC32MX7MMB default "pic32mz-starterkit" if ARCH_BOARD_PIC32MZ_STARTERKIT default "qemu-i486" if ARCH_BOARD_QEMU_I486 + default "rx65n" if ARCH_BOARD_RX65N + default "rx65n" if ARCH_BOARD_RX65N_RSK1MB + default "rx65n" if ARCH_BOARD_RX65N_RSK2MB + default "rx65n" if ARCH_BOARD_RX65N_GRROSE default "s32k118evb" if ARCH_BOARD_S32K118EVB default "s32k146evb" if ARCH_BOARD_S32K146EVB default "s32k148evb" if ARCH_BOARD_S32K148EVB @@ -2647,6 +2686,18 @@ endif if ARCH_BOARD_QEMU_I486 source "boards/x86/qemu/qemu-i486/Kconfig" endif +if ARCH_BOARD_RX65N +source "boards/renesas/rx65n/rx65n/Kconfig" +endif +if ARCH_BOARD_RX65N_RSK1MB +source "boards/renesas/rx65n/rx65n-rsk1mb/Kconfig" +endif +if ARCH_BOARD_RX65N_RSK2MB +source "boards/renesas/rx65n/rx65n-rsk2mb/Kconfig" +endif +if ARCH_BOARD_RX65N_GRROSE +source "boards/renesas/rx65n/rx65n-grrose/Kconfig" +endif if ARCH_BOARD_ESP32CORE source "boards/xtensa/esp32/esp32-core/Kconfig" endif diff --git a/boards/renesas/rx65n/drivers/Kconfig b/boards/renesas/rx65n/drivers/Kconfig new file mode 100644 index 00000000000..f72f3c094ce --- /dev/null +++ b/boards/renesas/rx65n/drivers/Kconfig @@ -0,0 +1,4 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# diff --git a/boards/renesas/rx65n/rx65n-grrose/Kconfig b/boards/renesas/rx65n/rx65n-grrose/Kconfig new file mode 100644 index 00000000000..c8345d4dc41 --- /dev/null +++ b/boards/renesas/rx65n/rx65n-grrose/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_RX65N_GRROSE +endif diff --git a/boards/renesas/rx65n/rx65n-grrose/README.txt b/boards/renesas/rx65n/rx65n-grrose/README.txt new file mode 100644 index 00000000000..5fd3d811113 --- /dev/null +++ b/boards/renesas/rx65n/rx65n-grrose/README.txt @@ -0,0 +1,254 @@ +README +====== + +This README file discusses the port of NuttX to “GR-ROSE” board produced by Gadget Renesas.This board features the RX65N (R5F565NEHDFP 100pin QFP) + +Contents +======== + + - Board Features + - Status/Open Issues + - Serial Console + - LEDs + - Networking + - Debugging + +Board Features +============== +- Micro controller - RX65N (R5F565NEHDFP 100pin QFP) RXv2 core [34 CoreMark/mA] +- ROM/RAM - 2MB/640KB +- Operating Frequency - 120MHz(12MHz 10 Multiplication) +- RTC Clock - 32.768kHz +- Sensors - Temperature(inside MCU) +- ROS I/F - Ethernet, USB(rosserial) +- Serial Servo I/F - TTL x 4, RS-485 x 1 +- Analog I/F - ADC(12bit) x 6, DAC x 1 +- Wireless - IEEE 802.11b/g/n +- PMOD I/F - 1 (I2C, SPI, UART) +- External power supply - USB VBUS or 4.5V～18V +- Supply to external - 3.3V, 5V + +See the RX65N GRROSE website for further information about this board: + + - http://gadget.renesas.com/en/product/rose.html + +Status/Open Issues +================== +Ethernet +--------- +1.Observed instability in Link Management, due to difference in hardware design.(No Seperate Interrupt line for PHY) +2.Currently tested only ping and udpblaster application. +3. Executed long run ping and udpblaster stress test for 12 hrs. Code is able to execute for 12hrs without any breakage. + +Serial Console +============== +RX65N GRROSE supports 12 serial ports (SCI0 - SCI12), however only 5 ports can be tested(SCI0, SCI1, SCI2, +SCI5 & SCI6). + +Please find the pin configurations for SCI0, SCI1, SCI2, SCI5 & SCI6 + +SCI0 Pin Configuration : + +----------- +RX65N GRROSE + Function +----------- + P21 RXD0 + P20 TXD0 +------------ + +SCI1 Pin Configuration : + +----------- +RX65N GRROSE + Function +----------- + P30 RXD1 + P26 TXD1 +------------ + +SCI2 Pin Configuration : + +----------- +RX65N GRROSE + Function +----------- + P12 RXD2 + P13 TXD2 +------------ + +SCI3 Pin Configuration : + +----------- +RX65N GRROSE + Function (connected to WiFi module) +----------- + P25 RXD3 + P23 TXD3 +------------ + +SCI5 Pin Configuration : + +----------- +RX65N GRROSE + Function +----------- + PC2 RXD5 + PC3 TXD5 +------------ + +SCI6 Pin Configuration : + +----------- +RX65N GRROSE + Function +----------- + P33 RXD6 + P32 TXD6 +------------ + +SCI8 Pin Configuration : + +----------- +RX65N GRROSE + Function (Half duplication mode with RS485 driver) +----------- + PC6 RXD8 + PC7 TXD8 + PC5 Direction (L=TX, H=RX) + +Serial Connection Configuration +-------------------------- +1. GRROSE board needs to be connected to PC terminal, using USB to Serial Chip. +2. Connect TX of USB to serial chip to RX of SCIX(0,1,2,5,6) +3. Connect RX of USB to serial chip to TX of SCIX(0,1,2,5,6) +4. Connect GND to GND pin. +5. Configure Teraterm to 115200 baud. + +LEDs +==== + + The RX65N GRROSE board has 2 LED's, 1 Power LED(LED3) and 2 User LED's(LED1, LED2),which are enabled through software. + + If enabled the LED is simply turned on when the board boots + successfully, and is blinking on panic / assertion failed. + +Networking +========== + +Ethernet Connections +----------- + + ------ --------- + RX65N + GRROSE Ethernet + Pin Function + ------ --------- + PA4 ET0_MDC + PA3 ET0_MDIO + PB2 REF50CK0 + PB7 RMII0_CRS_DV + PB1 RMII0_RXD0 + PB0 RMII0_RXD1 + PB3 RMII0_RX_ER + PB5 RMII0_ETXD0 + PB6 RMII0_ETXD1 + PB4 RMII0_TXD_EN + PA5 ET0_LINKSTA + PA6_ET_RST ETHER reset + ------ --------- +NuttX Configurations +--------------- +The following configurations, need to be enabled for network. + +CONFIG_RX65N_EMAC=y : Enable the EMAC Peripheral for RX65N +CONFIG_RX65N_EMAC0=y : Enable the EMAC Peripheral for RX65N +CONFIG_RX65N_EMAC0_PHYSR=30 : Address of PHY status register on LAN8720A +CONFIG_RX65N_EMAC0_PHYSR_100FD=0x18 : Needed for LAN8720A +CONFIG_RX65N_EMAC0_PHYSR_100HD=0x08 : " " " " " " +CONFIG_RX65N_EMAC0_PHYSR_10FD=0x14 : " " " " " " +CONFIG_RX65N_EMAC0_PHYSR_10HD=0x04 : " " " " " " +CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG=y : " " " " " " +CONFIG_RX65N_EMAC0_PHYSR_ALTMODE=0x1c : " " " " " " +CONFIG_RX65N_EMAC0_RMII=y +CONFIG_RX65N_EMAC0_PHYADDR=0 : LAN8720A PHY is at address 1 + +CONFIG_SCHED_WORKQUEUE=y : Work queue support is needed +CONFIG_SCHED_HPWORK=y : High Priority Work queue support +CONFIG_SCHED_LPWORK=y : Low Priority Work queue support + +Using the network with NSH +-------------------------- +The IP address is configured using DHCP, using the below mentioned configurations : + +The IP address is configured using DHCP, using the below mentioned configurations : + +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_DHCPD=y +CONFIG_NSH_DHCPC=y +CONFIG_NETINIT_DHCPC=y + +nsh> ifconfig + eth0 HWaddr 00:e0:de:ad:be:ef at UP + IPaddr:10.75.24.53 DRaddr:10.75.24.1 Mask:255.255.254.0 + +You can use ping to test for connectivity to the host (Careful, +Window firewalls usually block ping-related ICMP traffic). On the +target side, you can: + + nsh> ping 10.75.24.250 + PING 10.75.24.250 56 bytes of data + 56 bytes from 10.75.24.250: icmp_seq=1 time=0 ms + 56 bytes from 10.75.24.250: icmp_seq=2 time=0 ms + 56 bytes from 10.75.24.250: icmp_seq=3 time=0 ms + 56 bytes from 10.75.24.250: icmp_seq=4 time=0 ms + 56 bytes from 10.75.24.250: icmp_seq=5 time=0 ms + 56 bytes from 10.75.24.250: icmp_seq=6 time=0 ms + 56 bytes from 10.75.24.250: icmp_seq=7 time=0 ms + 56 bytes from 10.75.24.250: icmp_seq=8 time=0 ms + 56 bytes from 10.75.24.250: icmp_seq=9 time=0 ms + 56 bytes from 10.75.24.250: icmp_seq=10 time=0 ms + 10 packets transmitted, 10 received, 0% packet loss, time 10100 ms + +On the host side, you should also be able to ping the RX65N-GRROSE: + + $ ping 10.75.24.53 + +Configure UDP blaster application as mentioned below : + +CONFIG_EXAMPLES_UDPBLASTER_HOSTIP=0x0a4b1801 (10.75.24.1) ------> Gateway IP +CONFIG_EXAMPLES_UDPBLASTER_NETMASK=0xfffffe00 (255.255.254.0) --------> Netmask +CONFIG_EXAMPLES_UDPBLASTER_TARGETIP=0x0a4b189b (10.75.24.155) ---------> Target IP +Debugging +========== + +1. NuttX needs to be compiled in Cygwin. + +The following Configuration needs to be set, in order to do source level debugging. + +CONFIG_DEBUG_SYMBOLS = y (Set this option, using menuconfig only, DO NOT Enable this as default configuration). + +2. Download & Install Renesas e2studio IDE. +3. Load the project(NuttX built on Cygwin) as Makefile project with existing code +4. Right click on the project, and select Debug Configurations. +5. The binary(NuttX) needs to be loaded using E1/E2 Emulator. +6. Select the Device name as R5F565NE and Emulator as E1/E2(whichever is being used) +7. Select Connection type as FINE. +8. Load and run the binary. + +Flashing NuttX +=============== +Alternativly, NuttX binary can be flashed using Renesas flash programmer tool without using e2 studio/Cygwin + +Below are the steps mentioned to flash NuttX binary using Renesas flash programmer tool(RFP). + +1.In order to flash using Renesas flash programmer tool, nuttx.mot file should be generated. +2. Add the following lines in tools/Makefile.unix file : +ifeq ($(CONFIG_MOTOROLA_SREC),y) + @echo "CP: $(NUTTXNAME).mot" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) $(BIN) -O srec -I elf32-rx-be-ns $(NUTTXNAME).mot +endif +3. Add CONFIG_MOTOROLA_SREC=y in defconfig file or choose make menucofig->Build Setup-> Binary Output Format-> + Select Motorola SREC format. +4. Download Renesas flash programmer tool from https://www.renesas.com/in/en/products/software-tools/tools/programmer/renesas-flash-programmer-programming-gui.html#downloads +5. Refer to the user manual document, for steps to flash NuttX binary using RFP tool. \ No newline at end of file diff --git a/boards/renesas/rx65n/rx65n-grrose/configs/netnsh/defconfig b/boards/renesas/rx65n/rx65n-grrose/configs/netnsh/defconfig new file mode 100644 index 00000000000..b6435728d56 --- /dev/null +++ b/boards/renesas/rx65n/rx65n-grrose/configs/netnsh/defconfig @@ -0,0 +1,106 @@ +CONFIG_ARCH_BOARD_RX65N_GRROSE=y +CONFIG_ARCH_BOARD="rx65n-grrose" +CONFIG_ARCH_CHIP_R5F565NEHDFP=y +CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH="renesas" +CONFIG_ARCH_CHIP="rx65n" +CONFIG_BOARD_LOOPSPERMSEC=15001 +CONFIG_MOTOROLA_SREC=y +CONFIG_ENDIAN_LITTLE=y +CONFIG_SYSTEM_NSH=y +CONFIG_MAX_TASKS=8 +CONFIG_DEBUG_FEATURES=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_LAN8720A=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDEV_STATISTICS=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ARP_SEND=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCPBACKLOG=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_RAM_SIZE=655360 +CONFIG_RAM_START=0x00000000 +CONFIG_RAW_BINARY=y +CONFIG_RX65N_SCI0=y +CONFIG_RX65N_SCI1=y +CONFIG_RX65N_SCI2=y +CONFIG_RX65N_SCI5=y +CONFIG_RX65N_SCI6=y +CONFIG_RX65N_SCI8=y +CONFIG_SCI0_SERIALDRIVER=y +CONFIG_SCI0_BAUD=115200 +CONFIG_SCI1_SERIAL_CONSOLE=y +CONFIG_SCI1_SERIALDRIVER=y +CONFIG_SCI1_BAUD=115200 +CONFIG_SCI2_SERIALDRIVER=y +CONFIG_SCI2_BAUD=115200 +CONFIG_SCI5_SERIALDRIVER=y +CONFIG_SCI5_BAUD=921600 +CONFIG_SCI6_SERIALDRIVER=y +CONFIG_SCI6_BAUD=115200 +CONFIG_SCI8_SERIALDRIVER=y +CONFIG_SCI8_BAUD=115200 +CONFIG_RX65N_EMAC=y +CONFIG_RX65N_EMAC0=y +CONFIG_RX65N_EMAC0_PHYSR=30 +CONFIG_RX65N_EMAC0_PHYSR_100FD=0x18 +CONFIG_RX65N_EMAC0_PHYSR_100HD=0x08 +CONFIG_RX65N_EMAC0_PHYSR_10FD=0x14 +CONFIG_RX65N_EMAC0_PHYSR_10HD=0x04 +CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG=y +CONFIG_RX65N_EMAC0_PHYSR_ALTMODE=0x1c +CONFIG_RX65N_EMAC0_RMII=y +CONFIG_RX65N_EMAC0_PHYADDR=0 +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SYSTEM_PING=y +CONFIG_ICU=y +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_USERMAIN_STACKSIZE=1024 +CONFIG_IDLETHREAD_STACKSIZE=1024 +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_NET_ETH_PKTSIZE = 590 +CONFIG_RX65N_CMTW0=y +CONFIG_RX65N_PERIB=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_DHCPD=y +CONFIG_NSH_DHCPC=y +CONFIG_NETINIT_DHCPC=y +CONFIG_SYSTEM_NSH_PRIORITY=50 +CONFIG_EXAMPLES_SERIALBLASTER=y +CONFIG_EXAMPLES_SERIALBLASTER_STACKSIZE=2048 +CONFIG_EXAMPLES_SERIALBLASTER_PRIORITY=50 +CONFIG_EXAMPLES_SERIALBLASTER_DEVPATH="/dev/ttyS2" +CONFIG_EXAMPLES_SERIALRX=y +CONFIG_EXAMPLES_SERIALRX_STACKSIZE=2048 +CONFIG_EXAMPLES_SERIALRX_PRIORITY=75 +CONFIG_EXAMPLES_SERIALRX_BUFSIZE=11520 +CONFIG_EXAMPLES_SERIALRX_DEVPATH="/dev/ttyS0" +CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y \ No newline at end of file diff --git a/boards/renesas/rx65n/rx65n-grrose/configs/nsh/defconfig b/boards/renesas/rx65n/rx65n-grrose/configs/nsh/defconfig new file mode 100644 index 00000000000..1f454897509 --- /dev/null +++ b/boards/renesas/rx65n/rx65n-grrose/configs/nsh/defconfig @@ -0,0 +1,54 @@ +CONFIG_ARCH_BOARD_RX65N_GRROSE=y +CONFIG_ARCH_BOARD="rx65n-grrose" +CONFIG_ARCH_CHIP_R5F565NEHDFP=y +CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH="renesas" +CONFIG_ARCH_CHIP="rx65n" +CONFIG_BOARD_LOOPSPERMSEC=15001 +CONFIG_MOTOROLA_SREC=y +CONFIG_ENDIAN_LITTLE=y +CONFIG_SYSTEM_NSH=y +CONFIG_MAX_TASKS=8 +CONFIG_DEBUG_FEATURES=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_BUILTIN=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_RAM_SIZE=655360 +CONFIG_RAM_START=0x00000000 +CONFIG_RAW_BINARY=y +CONFIG_RX65N_SCI0=y +CONFIG_RX65N_SCI1=y +CONFIG_RX65N_SCI2=y +CONFIG_RX65N_SCI5=y +CONFIG_RX65N_SCI6=y +CONFIG_RX65N_SCI8=y +CONFIG_SCI0_SERIALDRIVER=y +CONFIG_SCI0_BAUD=115200 +CONFIG_SCI1_SERIAL_CONSOLE=y +CONFIG_SCI1_SERIALDRIVER=y +CONFIG_SCI1_BAUD=115200 +CONFIG_SCI2_SERIALDRIVER=y +CONFIG_SCI2_BAUD=115200 +CONFIG_SCI5_SERIALDRIVER=y +CONFIG_SCI5_BAUD=115200 +CONFIG_SCI6_SERIALDRIVER=y +CONFIG_SCI6_BAUD=115200 +CONFIG_SCI8_SERIALDRIVER=y +CONFIG_SCI8_BAUD=115200 +CONFIG_SDCLONE_DISABLE=y +CONFIG_ICU=y +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_USERMAIN_STACKSIZE=1024 +CONFIG_IDLETHREAD_STACKSIZE=1024 + diff --git a/boards/renesas/rx65n/rx65n-grrose/include/board.h b/boards/renesas/rx65n/rx65n-grrose/include/board.h new file mode 100644 index 00000000000..10dbd3b4cd0 --- /dev/null +++ b/boards/renesas/rx65n/rx65n-grrose/include/board.h @@ -0,0 +1,150 @@ +/*************************************************************************** + * configs/rx65n/include/board.h + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _CONFIGS_RX65N_BOARD_H +#define _CONFIGS_RX65N_BOARD_H + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ***************************************************************************/ + +/* Clocking ****************************************************************/ + +#define RX_CLK_1MHz (1000UL * 1000UL) +#define RX_FCLK ( 60 * RX_CLK_1MHz) +#define RX_ICLK (120 * RX_CLK_1MHz) +#define RX_PCLKA (120 * RX_CLK_1MHz) +#define RX_PCLKB ( 60 * RX_CLK_1MHz) +#define RX_PCLKC ( 60 * RX_CLK_1MHz) +#define RX_PCLKD ( 60 * RX_CLK_1MHz) +#define RX_BCK (120 * RX_CLK_1MHz) + +#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) || defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB) +#define RX_RESONATOR ( 24 * RX_CLK_1MHz) +#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE) +#define RX_RESONATOR ( 12 * RX_CLK_1MHz) +#elif defined(CONFIG_ARCH_BOARD_RX65N) +#define RX_RESONATOR ( 24 * RX_CLK_1MHz) +#else +#error "Please definition RX_RESONATOR in board.h" +#endif + +/* LED definitions */ + +#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) +#define LED0 (PORT0.PODR.BIT.B3) +#define LED1 (PORT0.PODR.BIT.B5) +#define LED_PORTINIT(X) { LED0 = LED1 = (X); \ + PORT0.ODR0.BIT.B6 = PORT0.ODR1.BIT.B2 = 0; \ + PORT0.DSCR.BIT.B3 = PORT0.DSCR.BIT.B5 = 1; \ + PORT0.PMR.BIT.B3 = PORT0.PMR.BIT.B5 = 0; \ + PORT0.PDR.BIT.B3 = PORT0.PDR.BIT.B5 = 1; \ +} +#elif defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB) +#define LED0 (PORT7.PODR.BIT.B3) +#define LED1 (PORTG.PODR.BIT.B7) +#define LED_PORTINIT(X) { LED0 = LED1 = (X); \ + PORT7.ODR0.BIT.B6 = PORTG.ODR1.BIT.B6 = 0; \ + PORT7.DSCR.BIT.B3 = PORTG.DSCR.BIT.B7 = 1; \ + PORT7.DSCR2.BIT.B3 = PORTG.DSCR2.BIT.B7 = 0; \ + PORT7.PMR.BIT.B3 = PORTG.PMR.BIT.B7 = 0; \ + PORT7.PDR.BIT.B3 = PORTG.PDR.BIT.B7 = 1; \ +} +#elif defined(CONFIG_ARCH_BOARD_RX65N) +#define LED0 (PORT0.PODR.BIT.B3) +#define LED1 (PORT0.PODR.BIT.B5) +#define LED_PORTINIT(X) { LED0 = LED1 = (X); \ + PORT0.ODR0.BIT.B6 = PORT0.ODR1.BIT.B2 = 0; \ + PORT0.DSCR.BIT.B3 = PORT0.DSCR.BIT.B5 = 1; \ + PORT0.PMR.BIT.B3 = PORT0.PMR.BIT.B5 = 0; \ + PORT0.PDR.BIT.B3 = PORT0.PDR.BIT.B5 = 1; \ +} +#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE) +#define LED0 (PORTA.PODR.BIT.BT0) +#define LED1 (PORTA.PODR.BIT.B1) +#define LED_PORTINIT(X) { LED0 = LED1 = (X); \ + PORTA.ODR0.BIT.BT0 = PORTA.ODR0.BIT.B2 = 0; \ + PORTA.DSCR.BIT.BT0 = PORTA.DSCR.BIT.B1 = 1; \ + PORTA.DSCR2.BIT.BT0 = PORTA.DSCR2.BIT.B1 = 0; \ + PORTA.PMR.BIT.BT0 = PORTA.PMR.BIT.B1 = 0; \ + PORTA.PDR.BIT.BT0 = PORTA.PDR.BIT.B1 = 1; \ +} +#else +#errror "LEDs are not defined." +#endif + +#define LED_STARTED 1 /* ON OFF NC NC */ +#define LED_HEAPALLOCATE 0 /* NC NC NC NC */ +#define LED_IRQSENABLED 0 /* NC NC NC NC */ +#define LED_STACKCREATED 2 /* ON ON NC NC */ +#define LED_INIRQ 0 /* NC NC NC NC */ +#define LED_SIGNAL 0 /* NC NC NC NC */ +#define LED_ASSERTION 0 /* NC NC NC NC */ +#define LED_PANIC 3 /* OFF ON NC NC (flashing 2Hz) */ + +/* Button definitions *******************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* _CONFIGS_RX65N_BOARD_H */ diff --git a/boards/renesas/rx65n/rx65n-grrose/scripts/Make.defs b/boards/renesas/rx65n/rx65n-grrose/scripts/Make.defs new file mode 100644 index 00000000000..03c2dbef26a --- /dev/null +++ b/boards/renesas/rx65n/rx65n-grrose/scripts/Make.defs @@ -0,0 +1,119 @@ +############################################################################## +# configs/rx65n-grrose/scripts/Make.defs +# +# Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. +# Author: Anjana +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################## + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += -Os -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ifeq ($(CONFIG_HOST_WINDOWS),y) +WINTOOL=y +DIRLINK = $(TOPDIR)/tools/copydir.sh +DIRUNLINK = $(TOPDIR)/tools/unlink.sh +MKDEP = $(TOPDIR)/tools/mkwindeps.sh +ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -I. -isystem "${shell cygpath -w $(TOPDIR)/arch/$(CONFIG_ARCH)/include}" +ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" +ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/linker_script.ld}" +ARCHPICFLAGS = -fpic +ARCHCFLAGS = -std=c99 -fno-builtin --sysroot=/cygwin64 +#ARCHCPUFLAGS = -fdata-sections -g2 -mlittle-endian-data +ARCHCPUFLAGS = -mcpu=rx64m +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +else +MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) +ARCHINCLUDES = -I. -isystem $(TOPDIR)/include +ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx +ARCHSCRIPT = -T$(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/linker_script.ld +ARCHPICFLAGS = -fpic +ARCHCFLAGS = -std=c99 -fno-builtin +#ARCHCPUFLAGS = -fdata-sections -g2 -mlittle-endian-data +ARCHCPUFLAGS = -mcpu=rx64m +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +endif + +CROSSDEV = rx-elf- +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +STRIP = $(CROSSDEV)strip --strip-unneeded +AR = $(CROSSDEV)ar rcs +AS = $(CROSSDEV)as +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ + $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) $(ARCHWARNINGSXX) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ +#AFLAGS = -Wa --mcpu=rxv2 -I$(TOPDIR)/include -I$(TOPDIR)/arch/renesas/src/common -I$(TOPDIR)/arch/renesas/src/rx65n -D__ASSEMBLY__ +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +LDMODULEFLAGS = -r -e module_initialize +ifeq ($(WINTOOL),y) + LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}" +else + LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + +CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs + +ASMEXT = .asm +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +#MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/boards/renesas/rx65n/rx65n-grrose/scripts/linker_script.ld b/boards/renesas/rx65n/rx65n-grrose/scripts/linker_script.ld new file mode 100644 index 00000000000..3bdf1f16654 --- /dev/null +++ b/boards/renesas/rx65n/rx65n-grrose/scripts/linker_script.ld @@ -0,0 +1,176 @@ +MEMORY +{ +/* RSK-RX65N-1MB */ +/* + RAM : ORIGIN = 0x0, LENGTH = 262144 + ROM : ORIGIN = 0xFFF00000, LENGTH = 1048576 + OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256 +*/ +/* RSK-RX65N-2MB | GR-ROSE */ + RAM : ORIGIN = 0x0, LENGTH = 262144 + RAMHI : ORIGIN = 0x800000, LENGTH = 393216 + ROM : ORIGIN = 0xFFE00000, LENGTH = 2097152 + OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256 +} +SECTIONS +{ + .exvectors 0xFFFFFF80: AT(0xFFFFFF80) + { + _exvectors_start = .; + KEEP(*(.exvectors)) + _exvectors_end = .; + } > ROM + .fvectors 0xFFFFFFFC: AT(0xFFFFFFFC) + { + KEEP(*(.fvectors)) + } > ROM +/* RSK-RX65N-1MB */ + + .text 0xFFF00000: AT(0xFFF00000) + +/* RSK-RX65N-2MB | GR-ROSE */ + /*.text 0xFFE00000: AT(0xFFE00000) */ + { + *(.text) + . = ALIGN(4); + *(.text.*) + . = ALIGN(4); + *(P) + etext = .; + } > ROM + .rvectors : + { + _rvectors_start = .; + KEEP(*(.rvectors)) + _rvectors_end = .; + } > ROM + /*.exvectors : + { + _exvectors_start = .; + KEEP(*(.exvectors)) + _exvectors_end = .; + } > ROM */ + .init : + { + KEEP(*(.init)) + __preinit_array_start = .; + KEEP(*(.preinit_array)) + __preinit_array_end = .; + __init_array_start = (. + 3) & ~ 3; + KEEP(*(.init_array)) + KEEP(*(SORT(.init_array.*))) + __init_array_end = .; + __fini_array_start = .; + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + __fini_array_end = .; + } > ROM + .fini : + { + KEEP(*(.fini)) + } > ROM + .got : + { + *(.got) + *(.got.plt) + } > ROM + .rodata : + { + *(.rodata) + *(.rodata.*) + *(C_1) + *(C_2) + *(C) + _erodata = .; + } > ROM + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > ROM + .eh_frame : + { + *(.eh_frame) + } > ROM + .jcr : + { + *(.jcr) + } > ROM + .tors : + { + __CTOR_LIST__ = .; + . = ALIGN(2); + ___ctors = .; + *(.ctors) + ___ctors_end = .; + __CTOR_END__ = .; + __DTOR_LIST__ = .; + ___dtors = .; + *(.dtors) + ___dtors_end = .; + __DTOR_END__ = .; + . = ALIGN(2); + _mdata = .; + } > ROM + .ustack 0x400: AT(0x200) + { + _ustack = .; + } > RAM + .istack 0x200: AT(0x200) + { + _istack = .; + } > RAM + .data 0x404: AT(_mdata) + { + _data = .; + *(.data) + *(.data.*) + *(D) + *(D_1) + *(D_2) + _edata = .; + } > RAM + .gcc_exc : + { + *(.gcc_exc) + } > RAM + .bss : + { + _bss = .; + *(.bss) + *(.bss.**) + *(COMMON) + *(B) + *(B_1) + *(B_2) + _ebss = .; + _end = .; + } >RAM + .ofs1 0xFE7F5D40: AT(0xFE7F5D00) + { + KEEP(*(.ofs1)) + } > OFS + .ofs2 0xFE7F5D48: AT(0xFE7F5D10) + { + KEEP(*(.ofs2)) + } > OFS + .ofs3 0xFE7F5D50: AT(0xFE7F5D40) + { + KEEP(*(.ofs3)) + } > OFS + .ofs4 0xFE7F5D10: AT(0xFE7F5D48) + { + KEEP(*(.ofs4)) + } > OFS + .ofs5 0xFE7F5D10: AT(0xFE7F5D50) + { + KEEP(*(.ofs5)) + } > OFS + .ofs6 0xFE7F5D10: AT(0xFE7F5D64) + { + KEEP(*(.ofs6)) + } > OFS + .ofs7 0xFE7F5D10: AT(0xFE7F5D70) + { + KEEP(*(.ofs7)) + } > OFS +} diff --git a/boards/renesas/rx65n/rx65n-grrose/src/Makefile b/boards/renesas/rx65n/rx65n-grrose/src/Makefile new file mode 100644 index 00000000000..17a7873b45a --- /dev/null +++ b/boards/renesas/rx65n/rx65n-grrose/src/Makefile @@ -0,0 +1,82 @@ +############################################################################ +# configs/rx65n-grrose/src/Makefile +# +# Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. +# Author: Anjana +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src +CFLAGS += -I=$(ARCH_SRCDIR)/chip -I=$(ARCH_SRCDIR)/common -I=$(TOPDIR)/sched +CFLAGS += -I=$(ARCH_SRCDIR)/chip + +ASRCS = +AOBJS = $(ASRCS:.asm=$(OBJEXT)) +CSRCS = rx65n_main.c +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +CFLAGS += -I=$(TOPDIR)/arch/$(CONFIG_ARCH)/src +CFLAGS += -I=$(TOPDIR)/arch/$(CONFIG_ARCH)/include + +all: libboard$(LIBEXT) + +$(AOBJS): %$(OBJEXT): %$(ASMEXT) + $(call ASSEMBLE, $<, $@) + +$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +libboard$(LIBEXT): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) + +.depend: Makefile $(SRCS) + $(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) touch $@ + +depend: .depend + +clean: + $(call DELFILE, libboard$(LIBEXT)) + $(call CLEAN) + +distclean: clean + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +ifneq ($(BOARD_CONTEXT),y) +context: +endif + +-include Make.dep diff --git a/boards/renesas/rx65n/rx65n-grrose/src/rx65n_main.c b/boards/renesas/rx65n/rx65n-grrose/src/rx65n_main.c new file mode 100644 index 00000000000..15ddd485821 --- /dev/null +++ b/boards/renesas/rx65n/rx65n-grrose/src/rx65n_main.c @@ -0,0 +1,126 @@ +/**************************************************************************** + * configs/rx65n-grrose/src/rx65n.main.c + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + *Included files + ***************************************************************************/ + +#include "rx65n_macrodriver.h" +#include "arch/board/board.h" +#include "rx65n_definitions.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled1_on + * + * Description: + * Turns on LED 0 + * + ****************************************************************************/ + +void board_autoled1_on(int led) +{ + LED0 = LED_ON; +} + +/**************************************************************************** + * Name: board_autoled2_on + * + * Description: + * Turns on LED 1 + * + ****************************************************************************/ + +void board_autoled2_on(int led) +{ + LED1 = LED_ON; +} + +/**************************************************************************** + * Name: board_autoled_on + * + * Description: + * Turns on LED 0 & LED 1 + * + ****************************************************************************/ + +void board_autoled_on(int led) +{ + LED0 = LED_ON; + LED1 = LED_ON; +} + +/**************************************************************************** + * Name: board_autoled1_off + * + * Description: + * Turns off LED 0 + * + ****************************************************************************/ + +void board_autoled1_off(int led) +{ + LED0 = LED_OFF; +} + +/**************************************************************************** + * Name: board_autoled2_off + * + * Description: + * Turns off LED 1 + * + ****************************************************************************/ + +void board_autoled2_off(int led) +{ + LED1 = LED_OFF; +} + +/**************************************************************************** + * Name: board_autoled_off + * + * Description: + * Turns off LED 0 & LED 1 + * + ****************************************************************************/ + +void board_autoled_off(int led) +{ + LED0 = LED_OFF; + LED1 = LED_OFF; +} diff --git a/boards/renesas/rx65n/rx65n-rsk1mb/Kconfig b/boards/renesas/rx65n/rx65n-rsk1mb/Kconfig new file mode 100644 index 00000000000..671fbedf7c8 --- /dev/null +++ b/boards/renesas/rx65n/rx65n-rsk1mb/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_RX65N_RSK1MB +endif diff --git a/boards/renesas/rx65n/rx65n-rsk1mb/configs/netnsh/defconfig b/boards/renesas/rx65n/rx65n-rsk1mb/configs/netnsh/defconfig new file mode 100644 index 00000000000..3f2b552effa --- /dev/null +++ b/boards/renesas/rx65n/rx65n-rsk1mb/configs/netnsh/defconfig @@ -0,0 +1,102 @@ +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH_BOARD_RX65N=y +#CONFIG_ARCH_BOARD_RX65N_RSK1MB=y +CONFIG_ARCH_BOARD="rx65n" +CONFIG_ARCH_CHIP_R5F565NEDDFC=y +CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH="renesas" +#CONFIG_BOARD_LOOPSPERMSEC=572 +#CONFIG_DISABLE_MOUNTPOINT=y +#CONFIG_DISABLE_MQUEUE=y +#CONFIG_DISABLE_POLL=y +#CONFIG_DISABLE_POSIX_TIMERS=y +#CONFIG_DISABLE_PTHREAD=y +#CONFIG_DISABLE_SIGNALS=y +CONFIG_MOTOROLA_SREC=y +CONFIG_ENDIAN_LITTLE=y +CONFIG_SYSTEM_NSH=y +CONFIG_MAX_TASKS=8 +CONFIG_DEBUG_FEATURES=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_KSZ8081=y +CONFIG_NET=y +#CONFIG_NETDEV_LATEINIT=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDEV_STATISTICS=y +#CONFIG_NETUTILS_TELNETD=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ARP_SEND=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCPBACKLOG=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +#CONFIG_NSH_CONSOLE_LOGIN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_RAM_SIZE=655360 +CONFIG_RAM_START=0x00000000 +CONFIG_RAW_BINARY=y + +#CONFIG_SCI0_SERIALDRIVER=y +#CONFIG_SCI0_SERIAL_CONSOLE=y +#CONFIG_RX65N_SCI0=y +#CONFIG_SCI1_SERIALDRIVER=y +#CONFIG_SCI1_SERIAL_CONSOLE=y +#CONFIG_RX65N_SCI1=y +CONFIG_SCI2_SERIALDRIVER=y +CONFIG_SCI2_SERIAL_CONSOLE=y +CONFIG_RX65N_SCI2=y +#CONFIG_SCI8_SERIALDRIVER=y +#CONFIG_SCI8_SERIAL_CONSOLE=y +#CONFIG_RX65N_SCI8=y + +CONFIG_RX65N_EMAC=y +CONFIG_RX65N_EMAC0=y +CONFIG_RX65N_EMAC0_PHYSR=30 +CONFIG_RX65N_EMAC0_PHYSR_100FD=0x6 +CONFIG_RX65N_EMAC0_PHYSR_100HD=0x2 +CONFIG_RX65N_EMAC0_PHYSR_10FD=0x5 +CONFIG_RX65N_EMAC0_PHYSR_10HD=0x1 +CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG=y +CONFIG_RX65N_EMAC0_PHYSR_ALTMODE=0x7 +CONFIG_RX65N_EMAC0_MII=y +CONFIG_RX65N_EMAC0_PHYADDR=30 + +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y + +CONFIG_SDCLONE_DISABLE=y +CONFIG_SYSTEM_PING=y +CONFIG_ICU=y +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_USERMAIN_STACKSIZE=1024 + +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_NET_ETH_PKTSIZE = 1518 +CONFIG_RX65N_CMT2=y +CONFIG_RX65N_CMT3=y +CONFIG_RX65N_PERIB=y + +#CONFIG_NET_IPv6=y +#CONFIG_NET_ICMPv6=y +#CONFIG_NET_MCASTGROUP=y diff --git a/boards/renesas/rx65n/rx65n-rsk1mb/configs/nsh/defconfig b/boards/renesas/rx65n/rx65n-rsk1mb/configs/nsh/defconfig new file mode 100644 index 00000000000..1ba8ca67bfa --- /dev/null +++ b/boards/renesas/rx65n/rx65n-rsk1mb/configs/nsh/defconfig @@ -0,0 +1,55 @@ +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH_BOARD_RX65N=y +#CONFIG_ARCH_BOARD_RX65N_RSK1MB=y +CONFIG_ARCH_BOARD="rx65n" +CONFIG_ARCH_CHIP_R5F565NEDDFC=y +CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH="renesas" +#CONFIG_BOARD_LOOPSPERMSEC=572 +#CONFIG_DISABLE_MOUNTPOINT=y +#CONFIG_DISABLE_MQUEUE=y +#CONFIG_DISABLE_POLL=y +#CONFIG_DISABLE_POSIX_TIMERS=y +#CONFIG_DISABLE_PTHREAD=y +#CONFIG_DISABLE_SIGNALS=y +CONFIG_MOTOROLA_SREC=y +CONFIG_ENDIAN_LITTLE=y +CONFIG_SYSTEM_NSH=y +CONFIG_MAX_TASKS=8 +CONFIG_DEBUG_FEATURES=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_BUILTIN=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +#CONFIG_NSH_CONSOLE_LOGIN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_RAM_SIZE=262144 +CONFIG_RAM_START=0x00000000 +CONFIG_RAW_BINARY=y +#CONFIG_SCI0_SERIALDRIVER=y +#CONFIG_SCI0_SERIAL_CONSOLE=y +#CONFIG_RX65N_SCI0=y +#CONFIG_SCI1_SERIALDRIVER=y +#CONFIG_SCI1_SERIAL_CONSOLE=y +#CONFIG_RX65N_SCI1=y +CONFIG_SCI2_SERIALDRIVER=y +CONFIG_SCI2_SERIAL_CONSOLE=y +CONFIG_RX65N_SCI2=y +#CONFIG_SCI8_SERIALDRIVER=y +#CONFIG_SCI8_SERIAL_CONSOLE=y +#CONFIG_RX65N_SCI8=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_ICU=y +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_USERMAIN_STACKSIZE=1024 + diff --git a/boards/renesas/rx65n/rx65n-rsk1mb/include/board.h b/boards/renesas/rx65n/rx65n-rsk1mb/include/board.h new file mode 100644 index 00000000000..8f50d46bf51 --- /dev/null +++ b/boards/renesas/rx65n/rx65n-rsk1mb/include/board.h @@ -0,0 +1,150 @@ +/*************************************************************************** + * configs/rx65n/include/board.h + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _CONFIGS_RX65N_BOARD_H +#define _CONFIGS_RX65N_BOARD_H + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ***************************************************************************/ + +/* Clocking */ + +#define RX_CLK_1MHz (1000UL * 1000UL) +#define RX_FCLK ( 60 * RX_CLK_1MHz) +#define RX_ICLK (120 * RX_CLK_1MHz) +#define RX_PCLKA (120 * RX_CLK_1MHz) +#define RX_PCLKB ( 60 * RX_CLK_1MHz) +#define RX_PCLKC ( 60 * RX_CLK_1MHz) +#define RX_PCLKD ( 60 * RX_CLK_1MHz) +#define RX_BCK (120 * RX_CLK_1MHz) + +#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) || defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB) +#define RX_RESONATOR ( 24 * RX_CLK_1MHz) +#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE) +#define RX_RESONATOR ( 12 * RX_CLK_1MHz) +#elif defined(CONFIG_ARCH_BOARD_RX65N) +#define RX_RESONATOR ( 24 * RX_CLK_1MHz) +#else +#error "Please definition RX_RESONATOR in board.h" +#endif + +/* LED definitions */ + +#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) +#define LED0 (PORT0.PODR.BIT.B3) +#define LED1 (PORT0.PODR.BIT.B5) +#define LED_PORTINIT(X) { LED0 = LED1 = (X); \ + PORT0.ODR0.BIT.B6 = PORT0.ODR1.BIT.B2 = 0; \ + PORT0.DSCR.BIT.B3 = PORT0.DSCR.BIT.B5 = 1; \ + PORT0.PMR.BIT.B3 = PORT0.PMR.BIT.B5 = 0; \ + PORT0.PDR.BIT.B3 = PORT0.PDR.BIT.B5 = 1; \ +} +#elif defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB) +#define LED0 (PORT7.PODR.BIT.B3) +#define LED1 (PORTG.PODR.BIT.B7) +#define LED_PORTINIT(X) { LED0 = LED1 = (X); \ + PORT7.ODR0.BIT.B6 = PORTG.ODR1.BIT.B6 = 0; \ + PORT7.DSCR.BIT.B3 = PORTG.DSCR.BIT.B7 = 1; \ + PORT7.DSCR2.BIT.B3 = PORTG.DSCR2.BIT.B7 = 0; \ + PORT7.PMR.BIT.B3 = PORTG.PMR.BIT.B7 = 0; \ + PORT7.PDR.BIT.B3 = PORTG.PDR.BIT.B7 = 1; \ +} +#elif defined(CONFIG_ARCH_BOARD_RX65N) +#define LED0 (PORT0.PODR.BIT.B3) +#define LED1 (PORT0.PODR.BIT.B5) +#define LED_PORTINIT(X) { LED0 = LED1 = (X); \ + PORT0.ODR0.BIT.B6 = PORT0.ODR1.BIT.B2 = 0; \ + PORT0.DSCR.BIT.B3 = PORT0.DSCR.BIT.B5 = 1; \ + PORT0.PMR.BIT.B3 = PORT0.PMR.BIT.B5 = 0; \ + PORT0.PDR.BIT.B3 = PORT0.PDR.BIT.B5 = 1; \ +} +#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE) +#define LED0 (PORTA.PODR.BIT.BT0) +#define LED1 (PORTA.PODR.BIT.B1) +#define LED_PORTINIT(X) { LED0 = LED1 = (X); \ + PORTA.ODR0.BIT.BT0 = PORTA.ODR0.BIT.B2 = 0; \ + PORTA.DSCR.BIT.BT0 = PORTA.DSCR.BIT.B1 = 1; \ + PORTA.DSCR2.BIT.BT0 = PORTA.DSCR2.BIT.B1 = 0; \ + PORTA.PMR.BIT.BT0 = PORTA.PMR.BIT.B1 = 0; \ + PORTA.PDR.BIT.BT0 = PORTA.PDR.BIT.B1 = 1; \ +} +#else +#errror "LEDs are not defined." +#endif + +#define LED_STARTED 1 /* ON OFF NC NC */ +#define LED_HEAPALLOCATE 0 /* NC NC NC NC */ +#define LED_IRQSENABLED 0 /* NC NC NC NC */ +#define LED_STACKCREATED 2 /* ON ON NC NC */ +#define LED_INIRQ 0 /* NC NC NC NC */ +#define LED_SIGNAL 0 /* NC NC NC NC */ +#define LED_ASSERTION 0 /* NC NC NC NC */ +#define LED_PANIC 3 /* OFF ON NC NC (flashing 2Hz) */ + +/* Button definitions */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* _CONFIGS_RX65N_BOARD_H */ diff --git a/boards/renesas/rx65n/rx65n-rsk1mb/scripts/Make.defs b/boards/renesas/rx65n/rx65n-rsk1mb/scripts/Make.defs new file mode 100644 index 00000000000..114f4ddbace --- /dev/null +++ b/boards/renesas/rx65n/rx65n-rsk1mb/scripts/Make.defs @@ -0,0 +1,123 @@ +############################################################################## +# configs/rx65n-rsk1mb/scripts/Make.defs +# +# Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. +# Author: Anjana +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################## + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + + + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += -Os -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ifeq ($(CONFIG_HOST_WINDOWS),y) +WINTOOL=y +DIRLINK = $(TOPDIR)/tools/copydir.sh +DIRUNLINK = $(TOPDIR)/tools/unlink.sh +MKDEP = $(TOPDIR)/tools/mkwindeps.sh +ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -I. -isystem "${shell cygpath -w $(TOPDIR)/arch/$(CONFIG_ARCH)/include}" +ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" +ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/linker_script.ld}" +ARCHPICFLAGS = -fpic +ARCHCFLAGS = -std=c99 -fno-builtin --sysroot=/cygwin64 +#ARCHCPUFLAGS = -fdata-sections -g2 -mlittle-endian-data +ARCHCPUFLAGS = -mcpu=rx64m +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +else +MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) +ARCHINCLUDES = -I. -isystem $(TOPDIR)/include +ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx +ARCHSCRIPT = -T$(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/linker_script.ld +ARCHPICFLAGS = -fpic +ARCHCFLAGS = -std=c99 -fno-builtin +#ARCHCPUFLAGS = -fdata-sections -g2 -mlittle-endian-data +ARCHCPUFLAGS = -mcpu=rx64m +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +endif + + +CROSSDEV = rx-elf- +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +STRIP = $(CROSSDEV)strip --strip-unneeded +AR = $(CROSSDEV)ar rcs +AS = $(CROSSDEV)as +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ + $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) $(ARCHWARNINGSXX) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ +#AFLAGS = -Wa --mcpu=rxv2 -I$(TOPDIR)/include -I$(TOPDIR)/arch/renesas/src/common -I$(TOPDIR)/arch/renesas/src/rx65n -D__ASSEMBLY__ +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +LDMODULEFLAGS = -r -e module_initialize +ifeq ($(WINTOOL),y) + LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}" +else + LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + +CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs + +ASMEXT = .asm +OBJEXT = .o +LIBEXT = .a +EXEEXT = + + +#MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/boards/renesas/rx65n/rx65n-rsk1mb/scripts/linker_script.ld b/boards/renesas/rx65n/rx65n-rsk1mb/scripts/linker_script.ld new file mode 100644 index 00000000000..f6da94050e9 --- /dev/null +++ b/boards/renesas/rx65n/rx65n-rsk1mb/scripts/linker_script.ld @@ -0,0 +1,167 @@ +MEMORY +{ +/* RSK-RX65N-1MB */ + RAM : ORIGIN = 0x0, LENGTH = 262144 + ROM : ORIGIN = 0xFFF00000, LENGTH = 1048576 + OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256 +/* RSK-RX65N-2MB | GR-ROSE */ +/* + RAM : ORIGIN = 0x0, LENGTH = 655360 + ROM : ORIGIN = 0xFFE00000, LENGTH = 2097152 + OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256 +*/ +} +SECTIONS +{ + .exvectors 0xFFFFFF80: AT(0xFFFFFF80) + { + KEEP(*(.exvectors)) + } > ROM + .fvectors 0xFFFFFFFC: AT(0xFFFFFFFC) + { + KEEP(*(.fvectors)) + } > ROM +/* RSK-RX65N-1MB */ + .text 0xFFF00000: AT(0xFFF00000) +/* RSK-RX65N-2MB | GR-ROSE */ +/* + .text 0xFFE00000: AT(0xFFE00000) +*/ + { + *(.text) + . = ALIGN(4); + *(.text.*) + . = ALIGN(4); + *(P) + etext = .; + } > ROM + .rvectors : + { + _rvectors_start = .; + KEEP(*(.rvectors)) + _rvectors_end = .; + } > ROM + .init : + { + KEEP(*(.init)) + __preinit_array_start = .; + KEEP(*(.preinit_array)) + __preinit_array_end = .; + __init_array_start = (. + 3) & ~ 3; + KEEP(*(.init_array)) + KEEP(*(SORT(.init_array.*))) + __init_array_end = .; + __fini_array_start = .; + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + __fini_array_end = .; + } > ROM + .fini : + { + KEEP(*(.fini)) + } > ROM + .got : + { + *(.got) + *(.got.plt) + } > ROM + .rodata : + { + *(.rodata) + *(.rodata.*) + *(C_1) + *(C_2) + *(C) + _erodata = .; + } > ROM + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > ROM + .eh_frame : + { + *(.eh_frame) + } > ROM + .jcr : + { + *(.jcr) + } > ROM + .tors : + { + __CTOR_LIST__ = .; + . = ALIGN(2); + ___ctors = .; + *(.ctors) + ___ctors_end = .; + __CTOR_END__ = .; + __DTOR_LIST__ = .; + ___dtors = .; + *(.dtors) + ___dtors_end = .; + __DTOR_END__ = .; + . = ALIGN(2); + _mdata = .; + } > ROM + .ustack 0x400: AT(0x200) + { + _ustack = .; + } > RAM + .istack 0x200: AT(0x200) + { + _istack = .; + } > RAM + .data 0x404: AT(_mdata) + { + _data = .; + *(.data) + *(.data.*) + *(D) + *(D_1) + *(D_2) + _edata = .; + } > RAM + .gcc_exc : + { + *(.gcc_exc) + } > RAM + .bss : + { + _bss = .; + *(.bss) + *(.bss.**) + *(COMMON) + *(B) + *(B_1) + *(B_2) + _ebss = .; + _end = .; + } > RAM + .ofs1 0xFE7F5D40: AT(0xFE7F5D00) + { + KEEP(*(.ofs1)) + } > OFS + .ofs2 0xFE7F5D48: AT(0xFE7F5D10) + { + KEEP(*(.ofs2)) + } > OFS + .ofs3 0xFE7F5D50: AT(0xFE7F5D40) + { + KEEP(*(.ofs3)) + } > OFS + .ofs4 0xFE7F5D10: AT(0xFE7F5D48) + { + KEEP(*(.ofs4)) + } > OFS + .ofs5 0xFE7F5D10: AT(0xFE7F5D50) + { + KEEP(*(.ofs5)) + } > OFS + .ofs6 0xFE7F5D10: AT(0xFE7F5D64) + { + KEEP(*(.ofs6)) + } > OFS + .ofs7 0xFE7F5D10: AT(0xFE7F5D70) + { + KEEP(*(.ofs7)) + } > OFS +} diff --git a/boards/renesas/rx65n/rx65n-rsk1mb/src/Makefile b/boards/renesas/rx65n/rx65n-rsk1mb/src/Makefile new file mode 100644 index 00000000000..56b145d294d --- /dev/null +++ b/boards/renesas/rx65n/rx65n-rsk1mb/src/Makefile @@ -0,0 +1,81 @@ +############################################################################ +# configs/rx65n/src/Makefile +# +# Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. +# Author: Anjana +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src +CFLAGS += -I=$(ARCH_SRCDIR)/chip -I=$(ARCH_SRCDIR)/common -I=$(TOPDIR)/sched +CFLAGS += -I=$(ARCH_SRCDIR)/chip + +ASRCS = +AOBJS = $(ASRCS:.asm=$(OBJEXT)) +CSRCS = rx65n_main.c +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +CFLAGS += -I=$(TOPDIR)/arch/$(CONFIG_ARCH)/src + +all: libboard$(LIBEXT) + +$(AOBJS): %$(OBJEXT): %$(ASMEXT) + $(call ASSEMBLE, $<, $@) + +$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +libboard$(LIBEXT): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) + +.depend: Makefile $(SRCS) + $(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) touch $@ + +depend: .depend + +clean: + $(call DELFILE, libboard$(LIBEXT)) + $(call CLEAN) + +distclean: clean + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +ifneq ($(BOARD_CONTEXT),y) +context: +endif + +-include Make.dep diff --git a/boards/renesas/rx65n/rx65n-rsk1mb/src/rx65n_main.c b/boards/renesas/rx65n/rx65n-rsk1mb/src/rx65n_main.c new file mode 100644 index 00000000000..15ddd485821 --- /dev/null +++ b/boards/renesas/rx65n/rx65n-rsk1mb/src/rx65n_main.c @@ -0,0 +1,126 @@ +/**************************************************************************** + * configs/rx65n-grrose/src/rx65n.main.c + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + *Included files + ***************************************************************************/ + +#include "rx65n_macrodriver.h" +#include "arch/board/board.h" +#include "rx65n_definitions.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled1_on + * + * Description: + * Turns on LED 0 + * + ****************************************************************************/ + +void board_autoled1_on(int led) +{ + LED0 = LED_ON; +} + +/**************************************************************************** + * Name: board_autoled2_on + * + * Description: + * Turns on LED 1 + * + ****************************************************************************/ + +void board_autoled2_on(int led) +{ + LED1 = LED_ON; +} + +/**************************************************************************** + * Name: board_autoled_on + * + * Description: + * Turns on LED 0 & LED 1 + * + ****************************************************************************/ + +void board_autoled_on(int led) +{ + LED0 = LED_ON; + LED1 = LED_ON; +} + +/**************************************************************************** + * Name: board_autoled1_off + * + * Description: + * Turns off LED 0 + * + ****************************************************************************/ + +void board_autoled1_off(int led) +{ + LED0 = LED_OFF; +} + +/**************************************************************************** + * Name: board_autoled2_off + * + * Description: + * Turns off LED 1 + * + ****************************************************************************/ + +void board_autoled2_off(int led) +{ + LED1 = LED_OFF; +} + +/**************************************************************************** + * Name: board_autoled_off + * + * Description: + * Turns off LED 0 & LED 1 + * + ****************************************************************************/ + +void board_autoled_off(int led) +{ + LED0 = LED_OFF; + LED1 = LED_OFF; +} diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/Kconfig b/boards/renesas/rx65n/rx65n-rsk2mb/Kconfig new file mode 100644 index 00000000000..2ad80f65958 --- /dev/null +++ b/boards/renesas/rx65n/rx65n-rsk2mb/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_RX65N_RSK2MB +endif diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/README.txt b/boards/renesas/rx65n/rx65n-rsk2mb/README.txt new file mode 100644 index 00000000000..52530a704a5 --- /dev/null +++ b/boards/renesas/rx65n/rx65n-rsk2mb/README.txt @@ -0,0 +1,212 @@ +README +====== + +This README file discusses the port of NuttX to the RX65N RSK2MB board. This board features the RX65N (R5F565NEHDFC 176pin) + +Contents +======== + + - Board Features + - Status/Open Issues + - Serial Console + - LEDs + - Networking + - Debugging + +Board Features +============== +- Mounted devices: RX65N (R5F565NEDDFC: No Encrypt Function, Code Flash 2MB, Pin Count 176-pin), + or RX65N (R5F565NEHDFC: Supported Encrypt Function, Code Flash 2MB, Pin Count 176-pin) +- Mounts TFT Display. Graphic LCD controller can be evaluated +- 1 channel Ethernet can be evaluated +- RX65N builds in Trusted Secure IP. AES encryption function and robust key management can be evaluated (*) +- Mounts SD slot. If an optional Wireless LAN expansion board package for RSK (RTK0ZZZZZZP00000BR#WS) is used, + Wireless LAN can evaluated +- 1 channel USB Function and 1 channel USB Host can be evaluated +- In addition, CAN, RSPI, QSPI, etc. can be evaluated + + +See the RX65N RSK2MB website for further information about this board: + + - https://www.renesas.com/br/en/products/software-tools/boards-and-kits/starter-kits/renesas-starter-kitplus-for-rx65n-2mb.html + +Status/Open Issues +================== +Ethernet +--------- +1.Observed instability in Link Management, due to difference in hardware design.(No Seperate Interrupt line for PHY) +2.Currently tested only ping and udpblaster application. +3. Executed long run ping and udpblaster stress test for 12 hrs. Code is able to execute for 12hrs without any breakage. + +Serial Console +============== +RX65N RSK2MB supports 12 serial ports (SCI0 - SCI12), however only 1 port can be tested(SCI8, which is the serial console). Only SCI8 port can be tested which is connected to USB Serial port. + +Serial ports SCI1, SCI2, SCI9-SCI12, cannot be tested because they are multiplexed to other Rx65N controller interfaces. + +Following SCI ports are configured w.r.t RX65N pin configuration +SCI1 Pin Configuration : +----------- +RX65N RSK2MB + Function +----------- + PF2 RXD1 + PF1 TXD1 +------------ + +SCI2 Pin Configuration : +----------- +RX65N RSK2MB + Function +----------- + P52 RXD2 + P50 TXD2 +------------ +SCI8 Pin Configuration : +----------- +RX65N RSK2MB + Function +----------- + PJ1 RXD8 + PJ2 TXD8 +------------ + +Serial Connection Configuration +------------------------------- +1. RSK2MB board needs to be connected to PC, using USB cable(One end of which is connected to PC, other end +connected to USB serial port on H/W board). +2. RSK USB Serial Driver needs to be downloaded on PC side. +3. Configure Teraterm to 115200 baud. + +LEDs +==== + + The RX65N RSK2MB board has 2 Power LED's(PowerLED5 LED_G, PowerLED3 LED_G) and 4 user LED's (LED_G, LED_O, LED_R, LED_R). + + If enabled 4 User LED's are simply turned on when the board boots + successfully, and is blinking on panic / assertion failed. + +Networking +========== + +Ethernet Connections +-------------------- + + ------ --------- + RX65N + RSK2MB Ethernet + Pin Function + ------ --------- + PC4 ET0_TX_CLK + P76 ET0_RX_CLK + P80 ET0_TX_EN + PC6 ET0_ETXD3 + PC5 ET0_ETXD2 + P82 ET0_ETXD1 + P81 ET0_ETXD0 + PC3 ET0_TX_ER + PC2 ET0_RX_DV + PC0 ET0_ERXD3 + PC1 ET0_ERXD2 + P74 ET0_ERXD1 + P75 ET0_ERXD0 + P77 ET0_RX_ER + P83 ET0_CRS + PC7 ET0_COL + P72 ET0_MDC + P71 ET0_MDIO + P54 ET0_LINKSTA + ------ --------- +NuttX Configurations +-------------------- +The following configurations, need to be enabled for network. + +CONFIG_RX65N_EMAC=y : Enable the EMAC Peripheral for RX65N +CONFIG_RX65N_EMAC0=y : Enable the EMAC Peripheral for RX65N +CONFIG_RX65N_EMAC0_PHYSR=30 : Address of PHY status register +CONFIG_RX65N_EMAC0_PHYSR_100FD=0x18 : Needed for PHY CHIP +CONFIG_RX65N_EMAC0_PHYSR_100HD=0x08 : " " " " " " +CONFIG_RX65N_EMAC0_PHYSR_10FD=0x14 : " " " " " " +CONFIG_RX65N_EMAC0_PHYSR_10HD=0x04 : " " " " " " +CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG=y : " " " " " " +CONFIG_RX65N_EMAC0_PHYSR_ALTMODE=0x1c : " " " " " " +CONFIG_RX65N_EMAC0_RMII=y +CONFIG_RX65N_EMAC0_PHYADDR=0 : PHY is at address 1 + +CONFIG_SCHED_WORKQUEUE=y : Work queue support is needed +CONFIG_SCHED_HPWORK=y : High Priority Work queue support +CONFIG_SCHED_LPWORK=y : Low Priority Work queue support + +Using the network with NSH +-------------------------- +The IP address is configured using DHCP, using the below mentioned configurations : + +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_DHCPD=y +CONFIG_NSH_DHCPC=y +CONFIG_NETINIT_DHCPC=y + +nsh> ifconfig + eth0 HWaddr 00:e0:de:ad:be:ef at UP + IPaddr:10.75.24.53 DRaddr:10.75.24.1 Mask:255.255.254.0 + +You can use ping to test for connectivity to the host (Careful, +Window firewalls usually block ping-related ICMP traffic). On the +target side, you can: + + nsh> ping 10.75.24.250 + PING 10.75.24.250 56 bytes of data + 56 bytes from 10.75.24.250: icmp_seq=1 time=0 ms + 56 bytes from 10.75.24.250: icmp_seq=2 time=0 ms + 56 bytes from 10.75.24.250: icmp_seq=3 time=0 ms + 56 bytes from 10.75.24.250: icmp_seq=4 time=0 ms + 56 bytes from 10.75.24.250: icmp_seq=5 time=0 ms + 56 bytes from 10.75.24.250: icmp_seq=6 time=0 ms + 56 bytes from 10.75.24.250: icmp_seq=7 time=0 ms + 56 bytes from 10.75.24.250: icmp_seq=8 time=0 ms + 56 bytes from 10.75.24.250: icmp_seq=9 time=0 ms + 56 bytes from 10.75.24.250: icmp_seq=10 time=0 ms + 10 packets transmitted, 10 received, 0% packet loss, time 10100 ms + +On the host side, you should also be able to ping the RX65N-RSK2MB: + + $ ping 10.75.24.53 + +Configure UDP blaster application as mentioned below : + +CONFIG_EXAMPLES_UDPBLASTER_HOSTIP=0x0a4b1801 (10.75.24.1) ------> Gateway IP +CONFIG_EXAMPLES_UDPBLASTER_NETMASK=0xfffffe00 (255.255.254.0) --------> Netmask +CONFIG_EXAMPLES_UDPBLASTER_TARGETIP=0x0a4b189b (10.75.24.155) ---------> Target IP + +Debugging +========== +1. NuttX needs to be compiled in Cygwin environment on Windows. + +The following Configuration needs to be set, in order to do source level debugging. + +CONFIG_DEBUG_SYMBOLS = y (Set this option, using menuconfig only, DO NOT Enable this as default configuration). + +2. Download & Install Renesas e2studio IDE +3. Load the project(NuttX built on Cygwin) as Makefile project with existing code +4. Right click on the project, and select Debug Configurations +5. The binary(NuttX) needs to be loaded using E1/E2 Emulator +6. Select the Device name as R5F565NE and Emulator as E1/E2(whichever is being used) +7. Select Connection type as JTAG +8. Load and run the binary + +Flashing NuttX +=============== +Alternativly, NuttX binary can be flashed using Renesas flash programmer tool without using e2 studio/Cygwin + +Below are the steps mentioned to flash NuttX binary using Renesas flash programmer tool(RFP). + +1.In order to flash using Renesas flash programmer tool, nuttx.mot file should be generated. +2. Add the following lines in tools/Makefile.unix file : +ifeq ($(CONFIG_MOTOROLA_SREC),y) + @echo "CP: $(NUTTXNAME).mot" + $(Q) $(OBJCOPY) $(OBJCOPYARGS) $(BIN) -O srec -I elf32-rx-be-ns $(NUTTXNAME).mot +endif +3. Add CONFIG_MOTOROLA_SREC=y in defconfig file or choose make menucofig->Build Setup-> Binary Output Format-> + Select Motorola SREC format. +4. Download Renesas flash programmer tool from https://www.renesas.com/in/en/products/software-tools/tools/programmer/renesas-flash-programmer-programming-gui.html#downloads +5. Refer to the user manual document, for steps to flash NuttX binary using RFP tool. \ No newline at end of file diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/configs/netnsh/defconfig b/boards/renesas/rx65n/rx65n-rsk2mb/configs/netnsh/defconfig new file mode 100644 index 00000000000..e032890a260 --- /dev/null +++ b/boards/renesas/rx65n/rx65n-rsk2mb/configs/netnsh/defconfig @@ -0,0 +1,91 @@ +CONFIG_ARCH_BOARD_RX65N_RSK2MB=y +CONFIG_ARCH_BOARD="rx65n" +CONFIG_ARCH_CHIP_R5F565NEHDFC=y +CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH="renesas" +CONFIG_ARCH_CHIP="rx65n" +CONFIG_BOARD_LOOPSPERMSEC=15001 +CONFIG_MOTOROLA_SREC=y +CONFIG_ENDIAN_LITTLE=y +CONFIG_SYSTEM_NSH=y +CONFIG_MAX_TASKS=8 +CONFIG_DEBUG_FEATURES=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_BUILTIN=y +CONFIG_ETH0_PHY_DP83620=y +CONFIG_NET=y +CONFIG_NETDB_DNSCLIENT=y +CONFIG_NETDB_DNSSERVER_NOADDR=y +CONFIG_NETDEV_PHY_IOCTL=y +CONFIG_NETDEV_STATISTICS=y +CONFIG_NETUTILS_TFTPC=y +CONFIG_NETUTILS_WEBCLIENT=y +CONFIG_NET_ARP_SEND=y +CONFIG_NET_BROADCAST=y +CONFIG_NET_ICMP=y +CONFIG_NET_ICMP_SOCKET=y +CONFIG_NET_SOCKOPTS=y +CONFIG_NET_STATISTICS=y +CONFIG_NET_TCP=y +CONFIG_NET_TCPBACKLOG=y +CONFIG_NET_TCP_WRITE_BUFFERS=y +CONFIG_NET_UDP=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_RAM_SIZE=655360 +CONFIG_RAM_START=0x00000000 +CONFIG_RAW_BINARY=y +CONFIG_SCI2_SERIALDRIVER=y +CONFIG_RX65N_SCI2=y +CONFIG_SCI8_SERIALDRIVER=y +CONFIG_SCI8_SERIAL_CONSOLE=y +CONFIG_RX65N_SCI8=y +CONFIG_RX65N_EMAC=y +CONFIG_RX65N_EMAC0=y +CONFIG_RX65N_EMAC0_PHYSR=30 +CONFIG_RX65N_EMAC0_PHYSR_100FD=0x4 +CONFIG_RX65N_EMAC0_PHYSR_100HD=0x0 +CONFIG_RX65N_EMAC0_PHYSR_10FD=0x6 +CONFIG_RX65N_EMAC0_PHYSR_10HD=0x2 +CONFIG_RX65N_EMAC0_PHYSR_ALTCONFIG=y +CONFIG_RX65N_EMAC0_PHYSR_ALTMODE=0x6 +CONFIG_RX65N_EMAC0_MII=y +CONFIG_RX65N_EMAC0_PHYADDR=30 +CONFIG_SCHED_WORKQUEUE=y +CONFIG_SCHED_HPWORK=y +CONFIG_SCHED_LPWORK=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_SYSTEM_PING=y +CONFIG_ICU=y +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_USERMAIN_STACKSIZE=1024 +CONFIG_FS_PROCFS=y +CONFIG_FS_PROCFS_REGISTER=y +CONFIG_NET_ETH_PKTSIZE = 590 +CONFIG_RX65N_CMTW0=y +CONFIG_RX65N_PERIB=y +CONFIG_NETUTILS_DHCPC=y +CONFIG_NETUTILS_DHCPD=y +CONFIG_NSH_DHCPC=y +CONFIG_NETINIT_DHCPC=y +CONFIG_SYSTEM_NSH_PRIORITY=50 +CONFIG_EXAMPLES_SERIALBLASTER=y +CONFIG_EXAMPLES_SERIALBLASTER_STACKSIZE=2048 +CONFIG_EXAMPLES_SERIALBLASTER_PRIORITY=50 +CONFIG_EXAMPLES_SERIALBLASTER_DEVPATH="/dev/ttyS2" +CONFIG_EXAMPLES_SERIALRX=y +CONFIG_EXAMPLES_SERIALRX_STACKSIZE=2048 +CONFIG_EXAMPLES_SERIALRX_PRIORITY=75 +CONFIG_EXAMPLES_SERIALRX_BUFSIZE=11520 +CONFIG_EXAMPLES_SERIALRX_DEVPATH="/dev/ttyS0" +CONFIG_EXAMPLES_SERIALRX_PRINTSTR=y \ No newline at end of file diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/configs/nsh/defconfig b/boards/renesas/rx65n/rx65n-rsk2mb/configs/nsh/defconfig new file mode 100644 index 00000000000..0258e890242 --- /dev/null +++ b/boards/renesas/rx65n/rx65n-rsk2mb/configs/nsh/defconfig @@ -0,0 +1,54 @@ +# CONFIG_NSH_DISABLE_IFCONFIG is not set +# CONFIG_NSH_DISABLE_PS is not set +CONFIG_ARCH_BOARD_RX65N_RSK2MB=y +CONFIG_ARCH_BOARD="rx65n" +CONFIG_ARCH_CHIP_R5F565NEHDFC=y +CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH="renesas" +#CONFIG_BOARD_LOOPSPERMSEC=572 +#CONFIG_DISABLE_MOUNTPOINT=y +#CONFIG_DISABLE_MQUEUE=y +#CONFIG_DISABLE_POLL=y +#CONFIG_DISABLE_POSIX_TIMERS=y +#CONFIG_DISABLE_PTHREAD=y +#CONFIG_DISABLE_SIGNALS=y +CONFIG_MOTOROLA_SREC=y +CONFIG_ENDIAN_LITTLE=y +CONFIG_SYSTEM_NSH=y +CONFIG_MAX_TASKS=8 +CONFIG_DEBUG_FEATURES=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_BUILTIN=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +#CONFIG_NSH_CONSOLE_LOGIN=y +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_RAM_SIZE=655360 +CONFIG_RAM_START=0x00000000 +CONFIG_RAW_BINARY=y +#CONFIG_SCI0_SERIALDRIVER=y +#CONFIG_SCI0_SERIAL_CONSOLE=y +#CONFIG_RX65N_SCI0=y +#CONFIG_SCI1_SERIALDRIVER=y +#CONFIG_SCI1_SERIAL_CONSOLE=y +#CONFIG_RX65N_SCI1=y +CONFIG_SCI2_SERIALDRIVER=y +CONFIG_SCI2_SERIAL_CONSOLE=y +CONFIG_RX65N_SCI2=y +CONFIG_SCI8_SERIALDRIVER=y +#CONFIG_SCI8_SERIAL_CONSOLE=y +CONFIG_RX65N_SCI8=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_ICU=y +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_USERMAIN_STACKSIZE=1024 + diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/include/board.h b/boards/renesas/rx65n/rx65n-rsk2mb/include/board.h new file mode 100644 index 00000000000..cc4b0bcc964 --- /dev/null +++ b/boards/renesas/rx65n/rx65n-rsk2mb/include/board.h @@ -0,0 +1,150 @@ +/*************************************************************************** + * configs/rx65n/include/board.h + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _CONFIGS_RX65N_BOARD_H +#define _CONFIGS_RX65N_BOARD_H + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ***************************************************************************/ + +/* Clocking ****************************************************************/ + +#define RX_CLK_1MHz (1000UL * 1000UL) +#define RX_FCLK ( 60 * RX_CLK_1MHz) +#define RX_ICLK (120 * RX_CLK_1MHz) +#define RX_PCLKA (120 * RX_CLK_1MHz) +#define RX_PCLKB ( 60 * RX_CLK_1MHz) +#define RX_PCLKC ( 60 * RX_CLK_1MHz) +#define RX_PCLKD ( 60 * RX_CLK_1MHz) +#define RX_BCK (120 * RX_CLK_1MHz) + +#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) || defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB) +#define RX_RESONATOR ( 24 * RX_CLK_1MHz) +#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE) +#define RX_RESONATOR ( 12 * RX_CLK_1MHz) +#elif defined(CONFIG_ARCH_BOARD_RX65N) +#define RX_RESONATOR ( 24 * RX_CLK_1MHz) +#else +#error "Please definition RX_RESONATOR in board.h" +#endif + +/* LED definitions */ + +#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) +#define LED0 (PORT0.PODR.BIT.B3) +#define LED1 (PORT0.PODR.BIT.B5) +#define LED_PORTINIT(X) { LED0 = LED1 = (X); \ + PORT0.ODR0.BIT.B6 = PORT0.ODR1.BIT.B2 = 0; \ + PORT0.DSCR.BIT.B3 = PORT0.DSCR.BIT.B5 = 1; \ + PORT0.PMR.BIT.B3 = PORT0.PMR.BIT.B5 = 0; \ + PORT0.PDR.BIT.B3 = PORT0.PDR.BIT.B5 = 1; \ +} +#elif defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB) +#define LED0 (PORT7.PODR.BIT.B3) +#define LED1 (PORTG.PODR.BIT.B7) +#define LED_PORTINIT(X) { LED0 = LED1 = (X); \ + PORT7.ODR0.BIT.B6 = PORTG.ODR1.BIT.B6 = 0; \ + PORT7.DSCR.BIT.B3 = PORTG.DSCR.BIT.B7 = 1; \ + PORT7.DSCR2.BIT.B3 = PORTG.DSCR2.BIT.B7 = 0; \ + PORT7.PMR.BIT.B3 = PORTG.PMR.BIT.B7 = 0; \ + PORT7.PDR.BIT.B3 = PORTG.PDR.BIT.B7 = 1; \ +} +#elif defined(CONFIG_ARCH_BOARD_RX65N) +#define LED0 (PORT0.PODR.BIT.B3) +#define LED1 (PORT0.PODR.BIT.B5) +#define LED_PORTINIT(X) { LED0 = LED1 = (X); \ + PORT0.ODR0.BIT.B6 = PORT0.ODR1.BIT.B2 = 0; \ + PORT0.DSCR.BIT.B3 = PORT0.DSCR.BIT.B5 = 1; \ + PORT0.PMR.BIT.B3 = PORT0.PMR.BIT.B5 = 0; \ + PORT0.PDR.BIT.B3 = PORT0.PDR.BIT.B5 = 1; \ +} +#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE) +#define LED0 (PORTA.PODR.BIT.BT0) +#define LED1 (PORTA.PODR.BIT.B1) +#define LED_PORTINIT(X) { LED0 = LED1 = (X); \ + PORTA.ODR0.BIT.BT0 = PORTA.ODR0.BIT.B2 = 0; \ + PORTA.DSCR.BIT.BT0 = PORTA.DSCR.BIT.B1 = 1; \ + PORTA.DSCR2.BIT.BT0 = PORTA.DSCR2.BIT.B1 = 0; \ + PORTA.PMR.BIT.BT0 = PORTA.PMR.BIT.B1 = 0; \ + PORTA.PDR.BIT.BT0 = PORTA.PDR.BIT.B1 = 1; \ +} +#else +#errror "LEDs are not defined." +#endif + +#define LED_STARTED 1 /* ON OFF NC NC */ +#define LED_HEAPALLOCATE 0 /* NC NC NC NC */ +#define LED_IRQSENABLED 0 /* NC NC NC NC */ +#define LED_STACKCREATED 2 /* ON ON NC NC */ +#define LED_INIRQ 0 /* NC NC NC NC */ +#define LED_SIGNAL 0 /* NC NC NC NC */ +#define LED_ASSERTION 0 /* NC NC NC NC */ +#define LED_PANIC 3 /* OFF ON NC NC (flashing 2Hz) */ + +/* Button definitions */ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* _CONFIGS_RX65N_BOARD_H */ diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/scripts/Make.defs b/boards/renesas/rx65n/rx65n-rsk2mb/scripts/Make.defs new file mode 100644 index 00000000000..4778d4b676a --- /dev/null +++ b/boards/renesas/rx65n/rx65n-rsk2mb/scripts/Make.defs @@ -0,0 +1,123 @@ +############################################################################## +# configs/rx65n-rsk2mb/scripts/Make.defs +# +# Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. +# Author: Anjana +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################## + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + + + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += -Os -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ifeq ($(CONFIG_HOST_WINDOWS),y) +WINTOOL=y +DIRLINK = $(TOPDIR)/tools/copydir.sh +DIRUNLINK = $(TOPDIR)/tools/unlink.sh +MKDEP = $(TOPDIR)/tools/mkwindeps.sh +ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -I. -isystem "${shell cygpath -w $(TOPDIR)/arch/$(CONFIG_ARCH)/include}" +ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" +ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/linker_script.ld}" +ARCHPICFLAGS = -fpic +ARCHCFLAGS = -std=c99 -fno-builtin --sysroot=/cygwin64 +#ARCHCPUFLAGS = -fdata-sections -g2 -mlittle-endian-data +ARCHCPUFLAGS = -mcpu=rx64m +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +else +MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) +ARCHINCLUDES = -I. -isystem $(TOPDIR)/include +ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx +ARCHSCRIPT = -T$(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/linker_script.ld +ARCHPICFLAGS = -fpic +ARCHCFLAGS = -std=c99 -fno-builtin +#ARCHCPUFLAGS = -fdata-sections -g2 -mlittle-endian-data +ARCHCPUFLAGS = -mcpu=rx64m +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +endif + + +CROSSDEV = rx-elf- +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +STRIP = $(CROSSDEV)strip --strip-unneeded +AR = $(CROSSDEV)ar rcs +AS = $(CROSSDEV)as +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ + $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) $(ARCHWARNINGSXX) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ +#AFLAGS = -Wa --mcpu=rxv2 -I$(TOPDIR)/include -I$(TOPDIR)/arch/renesas/src/common -I$(TOPDIR)/arch/renesas/src/rx65n -D__ASSEMBLY__ +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +LDMODULEFLAGS = -r -e module_initialize +ifeq ($(WINTOOL),y) + LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}" +else + LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + +CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs + +ASMEXT = .asm +OBJEXT = .o +LIBEXT = .a +EXEEXT = + + +#MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = + diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/scripts/linker_script.ld b/boards/renesas/rx65n/rx65n-rsk2mb/scripts/linker_script.ld new file mode 100644 index 00000000000..e2aa9f1a0fc --- /dev/null +++ b/boards/renesas/rx65n/rx65n-rsk2mb/scripts/linker_script.ld @@ -0,0 +1,168 @@ +MEMORY +{ +/* RSK-RX65N-1MB */ +/* + RAM : ORIGIN = 0x0, LENGTH = 262144 + ROM : ORIGIN = 0xFFF00000, LENGTH = 1048576 + OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256 +*/ +/* RSK-RX65N-2MB | GR-ROSE */ + RAM : ORIGIN = 0x0, LENGTH = 262144 + RAMHI : ORIGIN = 0x800000, LENGTH = 393216 + ROM : ORIGIN = 0xFFE00000, LENGTH = 2097152 + OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256 +} +SECTIONS +{ + .exvectors 0xFFFFFF80: AT(0xFFFFFF80) + { + KEEP(*(.exvectors)) + } > ROM + .fvectors 0xFFFFFFFC: AT(0xFFFFFFFC) + { + KEEP(*(.fvectors)) + } > ROM +/* RSK-RX65N-1MB */ +/* + .text 0xFFF00000: AT(0xFFF00000) +*/ +/* RSK-RX65N-2MB | GR-ROSE */ + .text 0xFFE00000: AT(0xFFE00000) + { + *(.text) + . = ALIGN(4); + *(.text.*) + . = ALIGN(4); + *(P) + etext = .; + } > ROM + .rvectors : + { + _rvectors_start = .; + KEEP(*(.rvectors)) + _rvectors_end = .; + } > ROM + .init : + { + KEEP(*(.init)) + __preinit_array_start = .; + KEEP(*(.preinit_array)) + __preinit_array_end = .; + __init_array_start = (. + 3) & ~ 3; + KEEP(*(.init_array)) + KEEP(*(SORT(.init_array.*))) + __init_array_end = .; + __fini_array_start = .; + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + __fini_array_end = .; + } > ROM + .fini : + { + KEEP(*(.fini)) + } > ROM + .got : + { + *(.got) + *(.got.plt) + } > ROM + .rodata : + { + *(.rodata) + *(.rodata.*) + *(C_1) + *(C_2) + *(C) + _erodata = .; + } > ROM + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > ROM + .eh_frame : + { + *(.eh_frame) + } > ROM + .jcr : + { + *(.jcr) + } > ROM + .tors : + { + __CTOR_LIST__ = .; + . = ALIGN(2); + ___ctors = .; + *(.ctors) + ___ctors_end = .; + __CTOR_END__ = .; + __DTOR_LIST__ = .; + ___dtors = .; + *(.dtors) + ___dtors_end = .; + __DTOR_END__ = .; + . = ALIGN(2); + _mdata = .; + } > ROM + .ustack 0x400: AT(0x200) + { + _ustack = .; + } > RAM + .istack 0x200: AT(0x200) + { + _istack = .; + } > RAM + .data 0x404: AT(_mdata) + { + _data = .; + *(.data) + *(.data.*) + *(D) + *(D_1) + *(D_2) + _edata = .; + } > RAM + .gcc_exc : + { + *(.gcc_exc) + } > RAM + .bss : + { + _bss = .; + *(.bss) + *(.bss.**) + *(COMMON) + *(B) + *(B_1) + *(B_2) + _ebss = .; + _end = .; + } > RAM + .ofs1 0xFE7F5D40: AT(0xFE7F5D00) + { + KEEP(*(.ofs1)) + } > OFS + .ofs2 0xFE7F5D48: AT(0xFE7F5D10) + { + KEEP(*(.ofs2)) + } > OFS + .ofs3 0xFE7F5D50: AT(0xFE7F5D40) + { + KEEP(*(.ofs3)) + } > OFS + .ofs4 0xFE7F5D10: AT(0xFE7F5D48) + { + KEEP(*(.ofs4)) + } > OFS + .ofs5 0xFE7F5D10: AT(0xFE7F5D50) + { + KEEP(*(.ofs5)) + } > OFS + .ofs6 0xFE7F5D10: AT(0xFE7F5D64) + { + KEEP(*(.ofs6)) + } > OFS + .ofs7 0xFE7F5D10: AT(0xFE7F5D70) + { + KEEP(*(.ofs7)) + } > OFS +} diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/src/Makefile b/boards/renesas/rx65n/rx65n-rsk2mb/src/Makefile new file mode 100644 index 00000000000..33e29da8cc9 --- /dev/null +++ b/boards/renesas/rx65n/rx65n-rsk2mb/src/Makefile @@ -0,0 +1,81 @@ +############################################################################ +# configs/rx65n-rsk2mb/src/Makefile +# +# Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. +# Author: Anjana +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src +CFLAGS += -I=$(ARCH_SRCDIR)/chip -I=$(ARCH_SRCDIR)/common -I=$(TOPDIR)/sched +CFLAGS += -I=$(ARCH_SRCDIR)/chip + +ASRCS = +AOBJS = $(ASRCS:.asm=$(OBJEXT)) +CSRCS = rx65n_main.c +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +CFLAGS += -I=$(TOPDIR)/arch/$(CONFIG_ARCH)/src + +all: libboard$(LIBEXT) + +$(AOBJS): %$(OBJEXT): %$(ASMEXT) + $(call ASSEMBLE, $<, $@) + +$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +libboard$(LIBEXT): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) + +.depend: Makefile $(SRCS) + $(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) touch $@ + +depend: .depend + +clean: + $(call DELFILE, libboard$(LIBEXT)) + $(call CLEAN) + +distclean: clean + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +ifneq ($(BOARD_CONTEXT),y) +context: +endif + +-include Make.dep diff --git a/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_main.c b/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_main.c new file mode 100644 index 00000000000..15ddd485821 --- /dev/null +++ b/boards/renesas/rx65n/rx65n-rsk2mb/src/rx65n_main.c @@ -0,0 +1,126 @@ +/**************************************************************************** + * configs/rx65n-grrose/src/rx65n.main.c + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + *Included files + ***************************************************************************/ + +#include "rx65n_macrodriver.h" +#include "arch/board/board.h" +#include "rx65n_definitions.h" + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled1_on + * + * Description: + * Turns on LED 0 + * + ****************************************************************************/ + +void board_autoled1_on(int led) +{ + LED0 = LED_ON; +} + +/**************************************************************************** + * Name: board_autoled2_on + * + * Description: + * Turns on LED 1 + * + ****************************************************************************/ + +void board_autoled2_on(int led) +{ + LED1 = LED_ON; +} + +/**************************************************************************** + * Name: board_autoled_on + * + * Description: + * Turns on LED 0 & LED 1 + * + ****************************************************************************/ + +void board_autoled_on(int led) +{ + LED0 = LED_ON; + LED1 = LED_ON; +} + +/**************************************************************************** + * Name: board_autoled1_off + * + * Description: + * Turns off LED 0 + * + ****************************************************************************/ + +void board_autoled1_off(int led) +{ + LED0 = LED_OFF; +} + +/**************************************************************************** + * Name: board_autoled2_off + * + * Description: + * Turns off LED 1 + * + ****************************************************************************/ + +void board_autoled2_off(int led) +{ + LED1 = LED_OFF; +} + +/**************************************************************************** + * Name: board_autoled_off + * + * Description: + * Turns off LED 0 & LED 1 + * + ****************************************************************************/ + +void board_autoled_off(int led) +{ + LED0 = LED_OFF; + LED1 = LED_OFF; +} diff --git a/boards/renesas/rx65n/rx65n/Kconfig b/boards/renesas/rx65n/rx65n/Kconfig new file mode 100644 index 00000000000..1a999e4dc08 --- /dev/null +++ b/boards/renesas/rx65n/rx65n/Kconfig @@ -0,0 +1,7 @@ +# +# For a description of the syntax of this configuration file, +# see the file kconfig-language.txt in the NuttX tools repository. +# + +if ARCH_BOARD_RX65N +endif diff --git a/boards/renesas/rx65n/rx65n/configs/nsh/defconfig b/boards/renesas/rx65n/rx65n/configs/nsh/defconfig new file mode 100644 index 00000000000..78f269d5381 --- /dev/null +++ b/boards/renesas/rx65n/rx65n/configs/nsh/defconfig @@ -0,0 +1,36 @@ +CONFIG_ARCH_BOARD_RX65N=y +CONFIG_ARCH_BOARD="rx65n" +CONFIG_ARCH_CHIP_R5F565NEDDFC=y +CONFIG_ARCH_RENESAS=y +CONFIG_ARCH_STACKDUMP=y +CONFIG_ARCH="renesas" +CONFIG_MOTOROLA_SREC=y +CONFIG_ENDIAN_LITTLE=y +CONFIG_SYSTEM_NSH=y +CONFIG_MAX_TASKS=8 +CONFIG_DEBUG_FEATURES=y +CONFIG_DEBUG_SYMBOLS=y +CONFIG_ARCH_INTERRUPTSTACK=1024 +CONFIG_BUILTIN=y +CONFIG_NSH_BUILTIN_APPS=y +CONFIG_NFILE_DESCRIPTORS=8 +CONFIG_NFILE_STREAMS=8 +CONFIG_NSH_FILEIOSIZE=512 +CONFIG_NSH_LINELEN=64 +CONFIG_NSH_READLINE=y +CONFIG_NUNGET_CHARS=0 +CONFIG_PREALLOC_TIMERS=0 +CONFIG_PTHREAD_STACK_DEFAULT=1024 +CONFIG_RAM_SIZE=262144 +CONFIG_RAM_START=0x00000000 +CONFIG_RAW_BINARY=y +CONFIG_SCI2_SERIALDRIVER=y +CONFIG_SCI2_SERIAL_CONSOLE=y +CONFIG_RX65N_SCI2=y +CONFIG_SDCLONE_DISABLE=y +CONFIG_ICU=y +CONFIG_STDIO_DISABLE_BUFFERING=y +CONFIG_TASK_NAME_SIZE=0 +CONFIG_USER_ENTRYPOINT="nsh_main" +CONFIG_USERMAIN_STACKSIZE=1024 + diff --git a/boards/renesas/rx65n/rx65n/include/board.h b/boards/renesas/rx65n/rx65n/include/board.h new file mode 100644 index 00000000000..c58c41279f1 --- /dev/null +++ b/boards/renesas/rx65n/rx65n/include/board.h @@ -0,0 +1,150 @@ +/*************************************************************************** + * configs/rx65n/include/board.h + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ***************************************************************************/ + +#ifndef _CONFIGS_RX65N_BOARD_H +#define _CONFIGS_RX65N_BOARD_H + +/*************************************************************************** + * Included Files + ***************************************************************************/ + +#ifndef __ASSEMBLY__ +# include +#endif + +/**************************************************************************** + * Pre-processor Definitions + ***************************************************************************/ + +/* Clocking ****************************************************************/ + +#define RX_CLK_1MHz (1000UL * 1000UL) +#define RX_FCLK ( 60 * RX_CLK_1MHz) +#define RX_ICLK (120 * RX_CLK_1MHz) +#define RX_PCLKA (120 * RX_CLK_1MHz) +#define RX_PCLKB ( 60 * RX_CLK_1MHz) +#define RX_PCLKC ( 60 * RX_CLK_1MHz) +#define RX_PCLKD ( 60 * RX_CLK_1MHz) +#define RX_BCK (120 * RX_CLK_1MHz) + +#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) || defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB) +#define RX_RESONATOR ( 24 * RX_CLK_1MHz) +#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE) +#define RX_RESONATOR ( 12 * RX_CLK_1MHz) +#elif defined(CONFIG_ARCH_BOARD_RX65N) +#define RX_RESONATOR ( 24 * RX_CLK_1MHz) +#else +#error "Please definition RX_RESONATOR in board.h" +#endif + +/* LED definitions **********************************************************/ + +#if defined(CONFIG_ARCH_BOARD_RX65N_RSK1MB) +#define LED0 (PORT0.PODR.BIT.B3) +#define LED1 (PORT0.PODR.BIT.B5) +#define LED_PORTINIT(X) { LED0 = LED1 = (X); \ + PORT0.ODR0.BIT.B6 = PORT0.ODR1.BIT.B2 = 0; \ + PORT0.DSCR.BIT.B3 = PORT0.DSCR.BIT.B5 = 1; \ + PORT0.PMR.BIT.B3 = PORT0.PMR.BIT.B5 = 0; \ + PORT0.PDR.BIT.B3 = PORT0.PDR.BIT.B5 = 1; \ +} +#elif defined(CONFIG_ARCH_BOARD_RX65N_RSK2MB) +#define LED0 (PORT7.PODR.BIT.B3) +#define LED1 (PORTG.PODR.BIT.B7) +#define LED_PORTINIT(X) { LED0 = LED1 = (X); \ + PORT7.ODR0.BIT.B6 = PORTG.ODR1.BIT.B6 = 0; \ + PORT7.DSCR.BIT.B3 = PORTG.DSCR.BIT.B7 = 1; \ + PORT7.DSCR2.BIT.B3 = PORTG.DSCR2.BIT.B7 = 0; \ + PORT7.PMR.BIT.B3 = PORTG.PMR.BIT.B7 = 0; \ + PORT7.PDR.BIT.B3 = PORTG.PDR.BIT.B7 = 1; \ +} +#elif defined(CONFIG_ARCH_BOARD_RX65N) +#define LED0 (PORT0.PODR.BIT.B3) +#define LED1 (PORT0.PODR.BIT.B5) +#define LED_PORTINIT(X) { LED0 = LED1 = (X); \ + PORT0.ODR0.BIT.B6 = PORT0.ODR1.BIT.B2 = 0; \ + PORT0.DSCR.BIT.B3 = PORT0.DSCR.BIT.B5 = 1; \ + PORT0.PMR.BIT.B3 = PORT0.PMR.BIT.B5 = 0; \ + PORT0.PDR.BIT.B3 = PORT0.PDR.BIT.B5 = 1; \ +} +#elif defined(CONFIG_ARCH_BOARD_RX65N_GRROSE) +#define LED0 (PORTA.PODR.BIT.BT0) +#define LED1 (PORTA.PODR.BIT.B1) +#define LED_PORTINIT(X) { LED0 = LED1 = (X); \ + PORTA.ODR0.BIT.BT0 = PORTA.ODR0.BIT.B2 = 0; \ + PORTA.DSCR.BIT.BT0 = PORTA.DSCR.BIT.B1 = 1; \ + PORTA.DSCR2.BIT.BT0 = PORTA.DSCR2.BIT.B1 = 0; \ + PORTA.PMR.BIT.BT0 = PORTA.PMR.BIT.B1 = 0; \ + PORTA.PDR.BIT.BT0 = PORTA.PDR.BIT.B1 = 1; \ +} +#else +#errror "LEDs are not defined." +#endif + +#define LED_STARTED 1 /* ON OFF NC NC */ +#define LED_HEAPALLOCATE 0 /* NC NC NC NC */ +#define LED_IRQSENABLED 0 /* NC NC NC NC */ +#define LED_STACKCREATED 2 /* ON ON NC NC */ +#define LED_INIRQ 0 /* NC NC NC NC */ +#define LED_SIGNAL 0 /* NC NC NC NC */ +#define LED_ASSERTION 0 /* NC NC NC NC */ +#define LED_PANIC 3 /* OFF ON NC NC (flashing 2Hz) */ + +/* Button definitions *******************************************************/ + +/**************************************************************************** + * Public Data + ****************************************************************************/ + +#ifndef __ASSEMBLY__ +#ifdef __cplusplus +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/**************************************************************************** + * Public Functions + ****************************************************************************/ + +#undef EXTERN +#ifdef __cplusplus +} +#endif +#endif + +#endif /* _CONFIGS_RX65N_BOARD_H */ diff --git a/boards/renesas/rx65n/rx65n/scripts/Make.defs b/boards/renesas/rx65n/rx65n/scripts/Make.defs new file mode 100644 index 00000000000..78cddcd9927 --- /dev/null +++ b/boards/renesas/rx65n/rx65n/scripts/Make.defs @@ -0,0 +1,118 @@ +############################################################################## +# configs/rx65n/scripts/Make.defs +# +# Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. +# Author: Anjana +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################## + +include ${TOPDIR}/.config +include ${TOPDIR}/tools/Config.mk + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + ARCHOPTIMIZATION = -g +endif + +ifneq ($(CONFIG_DEBUG_NOOPT),y) + ARCHOPTIMIZATION += -Os -fno-strict-aliasing -fno-strength-reduce -fomit-frame-pointer +endif + +ifeq ($(CONFIG_HOST_WINDOWS),y) +WINTOOL=y +DIRLINK = $(TOPDIR)/tools/copydir.sh +DIRUNLINK = $(TOPDIR)/tools/unlink.sh +MKDEP = $(TOPDIR)/tools/mkwindeps.sh +ARCHINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -I. -isystem "${shell cygpath -w $(TOPDIR)/arch/$(CONFIG_ARCH)/include}" +ARCHXXINCLUDES = -I. -isystem "${shell cygpath -w $(TOPDIR)/include}" -isystem "${shell cygpath -w $(TOPDIR)/include/cxx}" +ARCHSCRIPT = -T "${shell cygpath -w $(TOPDIR)/boards/$(CONFIG_ARCH)/$(CONFIG_ARCH_CHIP)/$(CONFIG_ARCH_BOARD)/scripts/linker_script.ld}" +ARCHPICFLAGS = -fpic +ARCHCFLAGS = -std=c99 -fno-builtin --sysroot=/cygwin64 +#ARCHCPUFLAGS = -fdata-sections -g2 -mlittle-endian-data +ARCHCPUFLAGS = -mcpu=rx64m +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +else +MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) +ARCHINCLUDES = -I. -isystem $(TOPDIR)/include +ARCHXXINCLUDES = -I. -isystem $(TOPDIR)/include -isystem $(TOPDIR)/include/cxx +ARCHSCRIPT = -T$(TOPDIR)/configs/$(CONFIG_ARCH_BOARD)/scripts/linker_script.ld +ARCHPICFLAGS = -fpic +ARCHCFLAGS = -std=c99 -fno-builtin +#ARCHCPUFLAGS = -fdata-sections -g2 -mlittle-endian-data +ARCHCPUFLAGS = -mcpu=rx64m +ARCHWARNINGS = -Wall -Wstrict-prototypes -Wshadow -Wundef +ARCHWARNINGSXX = -Wall -Wshadow -Wundef +endif + +CROSSDEV = rx-elf- +CC = $(CROSSDEV)gcc +CXX = $(CROSSDEV)g++ +CPP = $(CROSSDEV)gcc -E +LD = $(CROSSDEV)ld +STRIP = $(CROSSDEV)strip --strip-unneeded +AR = $(CROSSDEV)ar rcs +AS = $(CROSSDEV)as +NM = $(CROSSDEV)nm +OBJCOPY = $(CROSSDEV)objcopy +OBJDUMP = $(CROSSDEV)objdump + +CFLAGS = $(ARCHCFLAGS) $(ARCHWARNINGS) $(ARCHOPTIMIZATION) \ + $(ARCHCPUFLAGS) $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) -pipe +CPPFLAGS = $(ARCHINCLUDES) $(ARCHDEFINES) $(EXTRADEFINES) $(ARCHWARNINGSXX) +AFLAGS = $(CFLAGS) -D__ASSEMBLY__ +#AFLAGS = -Wa --mcpu=rxv2 -I$(TOPDIR)/include -I$(TOPDIR)/arch/renesas/src/common -I$(TOPDIR)/arch/renesas/src/rx65n -D__ASSEMBLY__ +NXFLATLDFLAGS1 = -r -d -warn-common +NXFLATLDFLAGS2 = $(NXFLATLDFLAGS1) -T$(TOPDIR)/binfmt/libnxflat/gnu-nxflat-pcrel.ld -no-check-sections +LDNXFLATFLAGS = -e main -s 2048 + +LDMODULEFLAGS = -r -e module_initialize +ifeq ($(WINTOOL),y) + LDMODULEFLAGS += -T "${shell cygpath -w $(TOPDIR)/libs/libc/modlib/gnu-elf.ld}" +else + LDMODULEFLAGS += -T $(TOPDIR)/libs/libc/modlib/gnu-elf.ld +endif + +ifeq ($(CONFIG_DEBUG_SYMBOLS),y) + LDFLAGS += -g +endif + +CMODULEFLAGS = $(CFLAGS) -mlong-calls # --target1-abs + +ASMEXT = .asm +OBJEXT = .o +LIBEXT = .a +EXEEXT = + +#MKDEP = $(TOPDIR)/tools/mkdeps$(HOSTEXEEXT) + +HOSTCC = gcc +HOSTINCLUDES = -I. +HOSTCFLAGS = -Wall -Wstrict-prototypes -Wshadow -Wundef -g -pipe +HOSTLDFLAGS = diff --git a/boards/renesas/rx65n/rx65n/scripts/linker_script.ld b/boards/renesas/rx65n/rx65n/scripts/linker_script.ld new file mode 100644 index 00000000000..3bdf1f16654 --- /dev/null +++ b/boards/renesas/rx65n/rx65n/scripts/linker_script.ld @@ -0,0 +1,176 @@ +MEMORY +{ +/* RSK-RX65N-1MB */ +/* + RAM : ORIGIN = 0x0, LENGTH = 262144 + ROM : ORIGIN = 0xFFF00000, LENGTH = 1048576 + OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256 +*/ +/* RSK-RX65N-2MB | GR-ROSE */ + RAM : ORIGIN = 0x0, LENGTH = 262144 + RAMHI : ORIGIN = 0x800000, LENGTH = 393216 + ROM : ORIGIN = 0xFFE00000, LENGTH = 2097152 + OFS : ORIGIN = 0xFE7F5D00, LENGTH = 256 +} +SECTIONS +{ + .exvectors 0xFFFFFF80: AT(0xFFFFFF80) + { + _exvectors_start = .; + KEEP(*(.exvectors)) + _exvectors_end = .; + } > ROM + .fvectors 0xFFFFFFFC: AT(0xFFFFFFFC) + { + KEEP(*(.fvectors)) + } > ROM +/* RSK-RX65N-1MB */ + + .text 0xFFF00000: AT(0xFFF00000) + +/* RSK-RX65N-2MB | GR-ROSE */ + /*.text 0xFFE00000: AT(0xFFE00000) */ + { + *(.text) + . = ALIGN(4); + *(.text.*) + . = ALIGN(4); + *(P) + etext = .; + } > ROM + .rvectors : + { + _rvectors_start = .; + KEEP(*(.rvectors)) + _rvectors_end = .; + } > ROM + /*.exvectors : + { + _exvectors_start = .; + KEEP(*(.exvectors)) + _exvectors_end = .; + } > ROM */ + .init : + { + KEEP(*(.init)) + __preinit_array_start = .; + KEEP(*(.preinit_array)) + __preinit_array_end = .; + __init_array_start = (. + 3) & ~ 3; + KEEP(*(.init_array)) + KEEP(*(SORT(.init_array.*))) + __init_array_end = .; + __fini_array_start = .; + KEEP(*(.fini_array)) + KEEP(*(SORT(.fini_array.*))) + __fini_array_end = .; + } > ROM + .fini : + { + KEEP(*(.fini)) + } > ROM + .got : + { + *(.got) + *(.got.plt) + } > ROM + .rodata : + { + *(.rodata) + *(.rodata.*) + *(C_1) + *(C_2) + *(C) + _erodata = .; + } > ROM + .eh_frame_hdr : + { + *(.eh_frame_hdr) + } > ROM + .eh_frame : + { + *(.eh_frame) + } > ROM + .jcr : + { + *(.jcr) + } > ROM + .tors : + { + __CTOR_LIST__ = .; + . = ALIGN(2); + ___ctors = .; + *(.ctors) + ___ctors_end = .; + __CTOR_END__ = .; + __DTOR_LIST__ = .; + ___dtors = .; + *(.dtors) + ___dtors_end = .; + __DTOR_END__ = .; + . = ALIGN(2); + _mdata = .; + } > ROM + .ustack 0x400: AT(0x200) + { + _ustack = .; + } > RAM + .istack 0x200: AT(0x200) + { + _istack = .; + } > RAM + .data 0x404: AT(_mdata) + { + _data = .; + *(.data) + *(.data.*) + *(D) + *(D_1) + *(D_2) + _edata = .; + } > RAM + .gcc_exc : + { + *(.gcc_exc) + } > RAM + .bss : + { + _bss = .; + *(.bss) + *(.bss.**) + *(COMMON) + *(B) + *(B_1) + *(B_2) + _ebss = .; + _end = .; + } >RAM + .ofs1 0xFE7F5D40: AT(0xFE7F5D00) + { + KEEP(*(.ofs1)) + } > OFS + .ofs2 0xFE7F5D48: AT(0xFE7F5D10) + { + KEEP(*(.ofs2)) + } > OFS + .ofs3 0xFE7F5D50: AT(0xFE7F5D40) + { + KEEP(*(.ofs3)) + } > OFS + .ofs4 0xFE7F5D10: AT(0xFE7F5D48) + { + KEEP(*(.ofs4)) + } > OFS + .ofs5 0xFE7F5D10: AT(0xFE7F5D50) + { + KEEP(*(.ofs5)) + } > OFS + .ofs6 0xFE7F5D10: AT(0xFE7F5D64) + { + KEEP(*(.ofs6)) + } > OFS + .ofs7 0xFE7F5D10: AT(0xFE7F5D70) + { + KEEP(*(.ofs7)) + } > OFS +} diff --git a/boards/renesas/rx65n/rx65n/src/Makefile b/boards/renesas/rx65n/rx65n/src/Makefile new file mode 100644 index 00000000000..c869c881214 --- /dev/null +++ b/boards/renesas/rx65n/rx65n/src/Makefile @@ -0,0 +1,82 @@ +############################################################################ +# configs/rx65n/src/Makefile +# +# Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. +# Author: Anjana +# +# Redistribution and use in source and binary forms, with or without +# modification, are permitted provided that the following conditions +# are met: +# +# 1. Redistributions of source code must retain the above copyright +# notice, this list of conditions and the following disclaimer. +# 2. Redistributions in binary form must reproduce the above copyright +# notice, this list of conditions and the following disclaimer in +# the documentation and/or other materials provided with the +# distribution. +# 3. Neither the name NuttX nor the names of its contributors may be +# used to endorse or promote products derived from this software +# without specific prior written permission. +# +# THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS +# "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT +# LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS +# FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE +# COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, +# INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, +# BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS +# OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED +# AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT +# LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN +# ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE +# POSSIBILITY OF SUCH DAMAGE. +# +############################################################################ + +-include $(TOPDIR)/Make.defs + +ARCH_SRCDIR = $(TOPDIR)/arch/$(CONFIG_ARCH)/src +CFLAGS += -I=$(ARCH_SRCDIR)/chip -I=$(ARCH_SRCDIR)/common -I=$(TOPDIR)/sched +CFLAGS += -I=$(ARCH_SRCDIR)/chip + +ASRCS = +AOBJS = $(ASRCS:.asm=$(OBJEXT)) +CSRCS = rx65n_main.c +COBJS = $(CSRCS:.c=$(OBJEXT)) + +SRCS = $(ASRCS) $(CSRCS) +OBJS = $(AOBJS) $(COBJS) + +CFLAGS += -I=$(TOPDIR)/arch/$(CONFIG_ARCH)/src +CFLAGS += -I=$(TOPDIR)/arch/$(CONFIG_ARCH)/include + +all: libboard$(LIBEXT) + +$(AOBJS): %$(OBJEXT): %$(ASMEXT) + $(call ASSEMBLE, $<, $@) + +$(COBJS) $(LINKOBJS): %$(OBJEXT): %.c + $(call COMPILE, $<, $@) + +libboard$(LIBEXT): $(OBJS) + $(call ARCHIVE, $@, $(OBJS)) + +.depend: Makefile $(SRCS) + $(Q) $(MKDEP) $(CC) -- $(CFLAGS) -- $(SRCS) >Make.dep + $(Q) touch $@ + +depend: .depend + +clean: + $(call DELFILE, libboard$(LIBEXT)) + $(call CLEAN) + +distclean: clean + $(call DELFILE, Make.dep) + $(call DELFILE, .depend) + +ifneq ($(BOARD_CONTEXT),y) +context: +endif + +-include Make.dep diff --git a/boards/renesas/rx65n/rx65n/src/rx65n_main.c b/boards/renesas/rx65n/rx65n/src/rx65n_main.c new file mode 100644 index 00000000000..354272cdf6b --- /dev/null +++ b/boards/renesas/rx65n/rx65n/src/rx65n_main.c @@ -0,0 +1,126 @@ +/**************************************************************************** + * configs/rx65n-grrose/src/rx65n.main.c + * + * Copyright (C) 2008-2019 Gregory Nutt. All rights reserved. + * Author: Anjana + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ****************************************************************************/ + +/**************************************************************************** + *Included files + ***************************************************************************/ + +#include "rx65n_macrodriver.h" +#include "arch/board/board.h" +#include "rx65n_definitions.h" + +/**************************************************************************** + * Private Functions + ****************************************************************************/ + +/**************************************************************************** + * Name: board_autoled1_on + * + * Description: + * Turns on LED 0 + * + ****************************************************************************/ + +void board_autoled1_on(int led) +{ + LED0 = LED_ON; +} + +/**************************************************************************** + * Name: board_autoled2_on + * + * Description: + * Turns on LED 1 + * + ****************************************************************************/ + +void board_autoled2_on(int led) +{ + LED1 = LED_ON; +} + +/**************************************************************************** + * Name: board_autoled_on + * + * Description: + * Turns on LED 0 & LED 1 + * + ****************************************************************************/ + +void board_autoled_on(int led) +{ + LED0 = LED_ON; + LED1 = LED_ON; +} + +/**************************************************************************** + * Name: board_autoled1_off + * + * Description: + * Turns off LED 0 + * + ****************************************************************************/ + +void board_autoled1_off(int led) +{ + LED0 = LED_OFF; +} + +/**************************************************************************** + * Name: board_autoled2_off + * + * Description: + * Turns off LED 1 + * + ****************************************************************************/ + +void board_autoled2_off(int led) +{ + LED1 = LED_OFF; +} + +/**************************************************************************** + * Name: board_autoled_off + * + * Description: + * Turns off LED 0 & LED 1 + * + ****************************************************************************/ + +void board_autoled_off(int led) +{ + LED0 = LED_OFF; + LED1 = LED_OFF; +} diff --git a/drivers/serial/Kconfig b/drivers/serial/Kconfig index 6bc33907c1c..d566f724587 100644 --- a/drivers/serial/Kconfig +++ b/drivers/serial/Kconfig @@ -406,6 +406,61 @@ config SCI1_SERIAL_CONSOLE depends on SCI1_SERIALDRIVER select SERIAL_CONSOLE +config SCI2_SERIAL_CONSOLE + bool "SCI2" + depends on SCI2_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI3_SERIAL_CONSOLE + bool "SCI3" + depends on SCI3_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI4_SERIAL_CONSOLE + bool "SCI4" + depends on SCI4_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI5_SERIAL_CONSOLE + bool "SCI5" + depends on SCI5_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI6_SERIAL_CONSOLE + bool "SCI6" + depends on SCI6_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI7_SERIAL_CONSOLE + bool "SCI7" + depends on SCI7_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI8_SERIAL_CONSOLE + bool "SCI8" + depends on SCI8_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI9_SERIAL_CONSOLE + bool "SCI9" + depends on SCI9_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI10_SERIAL_CONSOLE + bool "SCI10" + depends on SCI10_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI11_SERIAL_CONSOLE + bool "SCI11" + depends on SCI11_SERIALDRIVER + select SERIAL_CONSOLE + +config SCI12_SERIAL_CONSOLE + bool "SCI12" + depends on SCI12_SERIALDRIVER + select SERIAL_CONSOLE + config OTHER_SERIAL_CONSOLE bool "Other serial console" select SERIAL_CONSOLE diff --git a/drivers/serial/Kconfig-sci b/drivers/serial/Kconfig-sci index 646cc995e13..1969e93a383 100644 --- a/drivers/serial/Kconfig-sci +++ b/drivers/serial/Kconfig-sci @@ -13,6 +13,61 @@ config SCI1_SERIALDRIVER default n select MCU_SERIAL +config SCI2_SERIALDRIVER + bool + default n + select MCU_SERIAL + +config SCI3_SERIALDRIVER + bool + default n + select MCU_SERIAL + +config SCI4_SERIALDRIVER + bool + default n + select MCU_SERIAL + +config SCI5_SERIALDRIVER + bool + default n + select MCU_SERIAL + +config SCI6_SERIALDRIVER + bool + default n + select MCU_SERIAL + +config SCI7_SERIALDRIVER + bool + default n + select MCU_SERIAL + +config SCI8_SERIALDRIVER + bool + default n + select MCU_SERIAL + +config SCI9_SERIALDRIVER + bool + default n + select MCU_SERIAL + +config SCI10_SERIALDRIVER + bool + default n + select MCU_SERIAL + +config SCI11_SERIALDRIVER + bool + default n + select MCU_SERIAL + +config SCI12_SERIALDRIVER + bool + default n + select MCU_SERIAL + menu "SCI0 Configuration" depends on SCI0_SERIALDRIVER @@ -100,3 +155,487 @@ config SCI1_2STOP 1=Two stop bits endmenu # SCI1 Configuration + +menu "SCI2 Configuration" + depends on SCI2_SERIALDRIVER + +config SCI2_RXBUFSIZE + int "SCI2 receive buffer size" + default 256 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. + +config SCI2_TXBUFSIZE + int "SCI2 transmit buffer size" + default 256 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. + +config SCI2_BAUD + int "SCI2 BAUD rate" + default 115200 + ---help--- + The configured BAUD of the SCI. + +config SCI2_BITS + int "SCI2 character size" + default 8 + ---help--- + The number of bits. Must be either 7 or 8. + +config SCI2_PARITY + int "Parity setting" + default 0 + range 0 2 + ---help--- + 0=no parity, 1=odd parity, 2=even parity + +config SCI2_2STOP + int "SCI2 use 2 stop bits" + default 0 + ---help--- + 1=Two stop bits + +endmenu # SCI2 Configuration + +menu "SCI3 Configuration" + depends on SCI3_SERIALDRIVER + +config SCI3_RXBUFSIZE + int "SCI3 receive buffer size" + default 256 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. + +config SCI3_TXBUFSIZE + int "SCI3 transmit buffer size" + default 256 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. + +config SCI3_BAUD + int "SCI3 BAUD rate" + default 115200 + ---help--- + The configured BAUD of the SCI. + +config SCI3_BITS + int "SCI3 character size" + default 8 + ---help--- + The number of bits. Must be either 7 or 8. + +config SCI3_PARITY + int "Parity setting" + default 0 + range 0 2 + ---help--- + 0=no parity, 1=odd parity, 2=even parity + +config SCI3_2STOP + int "SCI3 use 2 stop bits" + default 0 + ---help--- + 1=Two stop bits + +endmenu # SCI3 Configuration + +menu "SCI4 Configuration" + depends on SCI4_SERIALDRIVER + +config SCI4_RXBUFSIZE + int "SCI4 receive buffer size" + default 256 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. + +config SCI4_TXBUFSIZE + int "SCI4 transmit buffer size" + default 256 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. + +config SCI4_BAUD + int "SCI4 BAUD rate" + default 115200 + ---help--- + The configured BAUD of the SCI. + +config SCI4_BITS + int "SCI4 character size" + default 8 + ---help--- + The number of bits. Must be either 7 or 8. + +config SCI4_PARITY + int "Parity setting" + default 0 + range 0 2 + ---help--- + 0=no parity, 1=odd parity, 2=even parity + +config SCI4_2STOP + int "SCI4 use 2 stop bits" + default 0 + ---help--- + 1=Two stop bits + +endmenu # SCI4 Configuration + +menu "SCI5 Configuration" + depends on SCI5_SERIALDRIVER + +config SCI5_RXBUFSIZE + int "SCI5 receive buffer size" + default 256 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. + +config SCI5_TXBUFSIZE + int "SCI5 transmit buffer size" + default 256 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. + +config SCI5_BAUD + int "SCI5 BAUD rate" + default 115200 + ---help--- + The configured BAUD of the SCI. + +config SCI5_BITS + int "SCI5 character size" + default 8 + ---help--- + The number of bits. Must be either 7 or 8. + +config SCI5_PARITY + int "Parity setting" + default 0 + range 0 2 + ---help--- + 0=no parity, 1=odd parity, 2=even parity + +config SCI5_2STOP + int "SCI5 use 2 stop bits" + default 0 + ---help--- + 1=Two stop bits + +endmenu # SCI5 Configuration + +menu "SCI6 Configuration" + depends on SCI6_SERIALDRIVER + +config SCI6_RXBUFSIZE + int "SCI6 receive buffer size" + default 256 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. + +config SCI6_TXBUFSIZE + int "SCI6 transmit buffer size" + default 256 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. + +config SCI6_BAUD + int "SCI6 BAUD rate" + default 115200 + ---help--- + The configured BAUD of the SCI. + +config SCI6_BITS + int "SCI6 character size" + default 8 + ---help--- + The number of bits. Must be either 7 or 8. + +config SCI6_PARITY + int "Parity setting" + default 0 + range 0 2 + ---help--- + 0=no parity, 1=odd parity, 2=even parity + +config SCI6_2STOP + int "SCI6 use 2 stop bits" + default 0 + ---help--- + 1=Two stop bits + +endmenu # SCI6 Configuration + +menu "SCI7 Configuration" + depends on SCI7_SERIALDRIVER + +config SCI7_RXBUFSIZE + int "SCI7 receive buffer size" + default 256 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. + +config SCI7_TXBUFSIZE + int "SCI7 transmit buffer size" + default 256 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. + +config SCI7_BAUD + int "SCI7 BAUD rate" + default 115200 + ---help--- + The configured BAUD of the SCI. + +config SCI7_BITS + int "SCI7 character size" + default 8 + ---help--- + The number of bits. Must be either 7 or 8. + +config SCI7_PARITY + int "Parity setting" + default 0 + range 0 2 + ---help--- + 0=no parity, 1=odd parity, 2=even parity + +config SCI7_2STOP + int "SCI7 use 2 stop bits" + default 0 + ---help--- + 1=Two stop bits + +endmenu # SCI7 Configuration + +menu "SCI8 Configuration" + depends on SCI8_SERIALDRIVER + +config SCI8_RXBUFSIZE + int "SCI8 receive buffer size" + default 256 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. + +config SCI8_TXBUFSIZE + int "SCI8 transmit buffer size" + default 256 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. + +config SCI8_BAUD + int "SCI8 BAUD rate" + default 115200 + ---help--- + The configured BAUD of the SCI. + +config SCI8_BITS + int "SCI8 character size" + default 8 + ---help--- + The number of bits. Must be either 7 or 8. + +config SCI8_PARITY + int "Parity setting" + default 0 + range 0 2 + ---help--- + 0=no parity, 1=odd parity, 2=even parity + +config SCI8_2STOP + int "SCI8 use 2 stop bits" + default 0 + ---help--- + 1=Two stop bits + +endmenu # SCI8 Configuration + +menu "SCI9 Configuration" + depends on SCI9_SERIALDRIVER + +config SCI9_RXBUFSIZE + int "SCI9 receive buffer size" + default 256 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. + +config SCI9_TXBUFSIZE + int "SCI9 transmit buffer size" + default 256 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. + +config SCI9_BAUD + int "SCI9 BAUD rate" + default 115200 + ---help--- + The configured BAUD of the SCI. + +config SCI9_BITS + int "SCI9 character size" + default 8 + ---help--- + The number of bits. Must be either 7 or 8. + +config SCI9_PARITY + int "Parity setting" + default 0 + range 0 2 + ---help--- + 0=no parity, 1=odd parity, 2=even parity + +config SCI9_2STOP + int "SCI9 use 2 stop bits" + default 0 + ---help--- + 1=Two stop bits + +endmenu # SCI9 Configuration + +menu "SCI10 Configuration" + depends on SCI10_SERIALDRIVER + +config SCI10_RXBUFSIZE + int "SCI10 receive buffer size" + default 256 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. + +config SCI10_TXBUFSIZE + int "SCI10 transmit buffer size" + default 256 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. + +config SCI10_BAUD + int "SCI10 BAUD rate" + default 115200 + ---help--- + The configured BAUD of the SCI. + +config SCI10_BITS + int "SCI10 character size" + default 8 + ---help--- + The number of bits. Must be either 7 or 8. + +config SCI10_PARITY + int "Parity setting" + default 0 + range 0 2 + ---help--- + 0=no parity, 1=odd parity, 2=even parity + +config SCI10_2STOP + int "SCI10 use 2 stop bits" + default 0 + ---help--- + 1=Two stop bits + +endmenu # SCI10 Configuration + +menu "SCI11 Configuration" + depends on SCI11_SERIALDRIVER + +config SCI11_RXBUFSIZE + int "SCI11 receive buffer size" + default 256 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. + +config SCI11_TXBUFSIZE + int "SCI11 transmit buffer size" + default 256 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. + +config SCI11_BAUD + int "SCI11 BAUD rate" + default 115200 + ---help--- + The configured BAUD of the SCI. + +config SCI11_BITS + int "SCI11 character size" + default 8 + ---help--- + The number of bits. Must be either 7 or 8. + +config SCI11_PARITY + int "Parity setting" + default 0 + range 0 2 + ---help--- + 0=no parity, 1=odd parity, 2=even parity + +config SCI11_2STOP + int "SCI11 use 2 stop bits" + default 0 + ---help--- + 1=Two stop bits + +endmenu # SCI11 Configuration + +menu "SCI12 Configuration" + depends on SCI12_SERIALDRIVER + +config SCI12_RXBUFSIZE + int "SCI12 receive buffer size" + default 256 + ---help--- + Characters are buffered as they are received. This specifies + the size of the receive buffer. + +config SCI12_TXBUFSIZE + int "SCI12 transmit buffer size" + default 256 + ---help--- + Characters are buffered before being sent. This specifies + the size of the transmit buffer. + +config SCI12_BAUD + int "SCI12 BAUD rate" + default 115200 + ---help--- + The configured BAUD of the SCI. + +config SCI12_BITS + int "SCI12 character size" + default 8 + ---help--- + The number of bits. Must be either 7 or 8. + +config SCI12_PARITY + int "Parity setting" + default 0 + range 0 2 + ---help--- + 0=no parity, 1=odd parity, 2=even parity + +config SCI12_2STOP + int "SCI12 use 2 stop bits" + default 0 + ---help--- + 1=Two stop bits + +endmenu # SCI12 Configuration diff --git a/tools/configure.c b/tools/configure.c index bfdd2f5aecb..c849b5e3d0a 100644 --- a/tools/configure.c +++ b/tools/configure.c @@ -193,6 +193,7 @@ static const char *g_chipnames[] = "moxart", "nrf52", "nuc1xx", + "rx65n" "s32k1xx", "sam34", "sama5", diff --git a/tools/configure.sh b/tools/configure.sh index 80fbfdbf475..7df56f78b79 100755 --- a/tools/configure.sh +++ b/tools/configure.sh @@ -145,7 +145,7 @@ fi archs="arm avr hc mips misoc or1k renesas risc-v sim x86 xtensa z16 z80" chips="a1x am335x c5471 cxd56xx dm320 efm32 imx6 imxrt kinetis kl lc823450 lpc17xx_40xx lpc214x lpc2378 lpc31xx lpc43xx lpc54xx max326xx moxart nrf52 - nuc1xx s32k1xx sam34 sama5 samd2l2 samd5e5 samv7 stm32 stm32f0l0g0 stm32f7 stm32h7 + nuc1xx rx65n s32k1xx sam34 sama5 samd2l2 samd5e5 samv7 stm32 stm32f0l0g0 stm32f7 stm32h7 stm32l4 str71x tiva tms570 xmc4 at32uc3 at90usb atmega mcs92s12ne64 pic32mx pic32mz lm32 mor1kx m32262f8 sh7032 gap8 nr5m100 sim qemu esp32 z16f2811 ez80 z180 z8 z80" diff --git a/tools/refresh.sh b/tools/refresh.sh index 59971461855..a3dedf36080 100755 --- a/tools/refresh.sh +++ b/tools/refresh.sh @@ -121,7 +121,7 @@ ARCHLIST="arm avr hc mips misoc or1k renesas risc-v sim x86 xtensa z16 z80" ARCHLIST="arm avr hc mips misoc or1k renesas risc-v sim x86 xtensa z16 z80" CHIPLIST="a1x am335x c5471 cxd56xx dm320 efm32 imx6 imxrt kinetis kl lc823450 lpc17xx_40xx lpc214x lpc2378 lpc31xx lpc43xx lpc54xx max326xx moxart nrf52 - nuc1xx s32k1xx sam34 sama5 samd2l2 samd5e5 samv7 stm32 stm32f0l0g0 stm32f7 stm32h7 + nuc1xx rx65n s32k1xx sam34 sama5 samd2l2 samd5e5 samv7 stm32 stm32f0l0g0 stm32f7 stm32h7 stm32l4 str71x tiva tms570 xmc4 at32uc3 at90usb atmega mcs92s12ne64 pic32mx pic32mz lm32 mor1kx m32262f8 sh7032 gap8 nr5m100 sim qemu esp32 z16f2811 ez80 z180 z8 z80" diff --git a/tools/testbuild.sh b/tools/testbuild.sh index 75b7b52b6ed..f502b9c7dde 100755 --- a/tools/testbuild.sh +++ b/tools/testbuild.sh @@ -301,7 +301,7 @@ for line in $testlist; do ARCHLIST="arm avr hc mips misoc or1k renesas risc-v sim x86 xtensa z16 z80" CHIPLIST="a1x am335x c5471 cxd56xx dm320 efm32 imx6 imxrt kinetis kl lc823450 lpc17xx_40xx lpc214x lpc2378 lpc31xx lpc43xx lpc54xx max326xx moxart nrf52 - nuc1xx s32k1xx sam34 sama5 samd2l2 samd5e5 samv7 stm32 stm32f0l0g0 stm32f7 stm32h7 + nuc1xx rx65n s32k1xx sam34 sama5 samd2l2 samd5e5 samv7 stm32 stm32f0l0g0 stm32f7 stm32h7 stm32l4 str71x tiva tms570 xmc4 at32uc3 at90usb atmega mcs92s12ne64 pic32mx pic32mz lm32 mor1kx m32262f8 sh7032 gap8 nr5m100 sim qemu esp32 z16f2811 ez80 z180 z8 z80"