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arch/arm: Add NVIC_CPACR_CP_XXX(n) macro to avoid the hard code value

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Signed-off-by: Xiang Xiao <xiaoxiang@xiaomi.com>
This commit is contained in:
Xiang Xiao
2021-08-14 16:08:38 +08:00
committed by David Sidrane
parent 33666832c5
commit fad0c3b38b
24 changed files with 60 additions and 44 deletions
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arch/arm/src/armv7-m/nvic.h
+8
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@@ -632,6 +632,14 @@
#define NVIC_CSSELR_LEVEL_MASK (7 << NVIC_CSSELR_LEVEL_SHIFT)
#define NVIC_CSSELR_LEVEL_1 (0 << NVIC_CSSELR_LEVEL_SHIFT)
/* Coprocessor Access Control Register (CPACR) */
#define NVIC_CPACR_CP_SHIFT(n) (2 * (n))
#define NVIC_CPACR_CP_MASK(n) (3 << NVIC_CPACR_CP_SHIFT(n))
# define NVIC_CPACR_CP_DENY(n) (0 << NVIC_CPACR_CP_SHIFT(n))
# define NVIC_CPACR_CP_PRIV(n) (1 << NVIC_CPACR_CP_SHIFT(n))
# define NVIC_CPACR_CP_FULL(n) (3 << NVIC_CPACR_CP_SHIFT(n))
/* Debug Exception and Monitor Control Register (DEMCR) */
#define NVIC_DEMCR_VCCORERESET (1 << 0) /* Bit 0: Reset Vector Catch */
arch/arm/src/armv8-m/nvic.h
+8
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@@ -651,6 +651,14 @@
#define NVIC_CSSELR_LEVEL_MASK (7 << NVIC_CSSELR_LEVEL_SHIFT)
#define NVIC_CSSELR_LEVEL_1 (0 << NVIC_CSSELR_LEVEL_SHIFT)
/* Coprocessor Access Control Register (CPACR) */
#define NVIC_CPACR_CP_SHIFT(n) (2 * (n))
#define NVIC_CPACR_CP_MASK(n) (3 << NVIC_CPACR_CP_SHIFT(n))
# define NVIC_CPACR_CP_DENY(n) (0 << NVIC_CPACR_CP_SHIFT(n))
# define NVIC_CPACR_CP_PRIV(n) (1 << NVIC_CPACR_CP_SHIFT(n))
# define NVIC_CPACR_CP_FULL(n) (3 << NVIC_CPACR_CP_SHIFT(n))
/* Debug Exception and Monitor Control Register (DEMCR) */
#define NVIC_DEMCR_VCCORERESET (1 << 0) /* Bit 0: Reset Vector Catch */
arch/arm/src/cxd56xx/cxd56_start.c
+2 -2
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@@ -162,7 +162,7 @@ void fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
@@ -192,7 +192,7 @@ void fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
arch/arm/src/efm32/efm32_start.c
+2 -2
View File
@@ -154,7 +154,7 @@ static inline void efm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
@@ -184,7 +184,7 @@ static inline void efm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
arch/arm/src/eoss3/eoss3_start.c
+2 -2
View File
@@ -152,7 +152,7 @@ static inline void eoss3_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
@@ -182,7 +182,7 @@ static inline void eoss3_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
arch/arm/src/imxrt/imxrt_start.c
+2 -2
View File
@@ -136,7 +136,7 @@ static inline void imxrt_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
@@ -166,7 +166,7 @@ static inline void imxrt_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
arch/arm/src/kinetis/kinetis_start.c
+2 -2
View File
@@ -148,7 +148,7 @@ static inline void kinetis_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
@@ -178,7 +178,7 @@ static inline void kinetis_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
arch/arm/src/lpc17xx_40xx/lpc17_40_start.c
+2 -2
View File
@@ -137,7 +137,7 @@ static inline void lpc17_40_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
@@ -167,7 +167,7 @@ static inline void lpc17_40_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
arch/arm/src/lpc43xx/lpc43_start.c
+2 -2
View File
@@ -205,7 +205,7 @@ static inline void lpc43_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
@@ -235,7 +235,7 @@ static inline void lpc43_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
arch/arm/src/lpc54xx/lpc54_start.c
+2 -2
View File
@@ -135,7 +135,7 @@ static inline void lpc54_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
@@ -163,7 +163,7 @@ static inline void lpc54_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
arch/arm/src/max326xx/common/max326_start.c
+2 -2
View File
@@ -135,7 +135,7 @@ static inline void max326_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
@@ -163,7 +163,7 @@ static inline void max326_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
arch/arm/src/nrf52/nrf52_start.c
+2 -2
View File
@@ -122,7 +122,7 @@ static inline void nrf52_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
@@ -150,7 +150,7 @@ static inline void nrf52_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
arch/arm/src/s32k1xx/s32k1xx_start.c
+2 -2
View File
@@ -175,7 +175,7 @@ static inline void s32k1xx_fpu_config(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#else
@@ -203,7 +203,7 @@ static inline void s32k1xx_fpu_config(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
#endif
arch/arm/src/sam34/sam_start.c
+2 -2
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@@ -150,7 +150,7 @@ static inline void sam_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
@@ -180,7 +180,7 @@ static inline void sam_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
arch/arm/src/samd5e5/sam_start.c
+2 -2
View File
@@ -152,7 +152,7 @@ static inline void sam_fpu_configure(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
@@ -182,7 +182,7 @@ static inline void sam_fpu_configure(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
arch/arm/src/samv7/sam_start.c
+2 -2
View File
@@ -147,7 +147,7 @@ static inline void sam_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
@@ -177,7 +177,7 @@ static inline void sam_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
arch/arm/src/stm32/stm32_start.c
+2 -2
View File
@@ -153,7 +153,7 @@ static inline void stm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
@@ -183,7 +183,7 @@ static inline void stm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
arch/arm/src/stm32f7/stm32_start.c
+2 -2
View File
@@ -147,7 +147,7 @@ static inline void stm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
@@ -177,7 +177,7 @@ static inline void stm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
arch/arm/src/stm32h7/stm32_start.c
+2 -2
View File
@@ -162,7 +162,7 @@ static inline void stm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
@@ -192,7 +192,7 @@ static inline void stm32_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
arch/arm/src/stm32l4/stm32l4_start.c
+2 -2
View File
@@ -162,7 +162,7 @@ static inline void stm32l4_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
@@ -192,7 +192,7 @@ static inline void stm32l4_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
arch/arm/src/stm32l5/stm32l5_start.c
+2 -2
View File
@@ -165,7 +165,7 @@ static inline void stm32l5_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
@@ -195,7 +195,7 @@ static inline void stm32l5_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
arch/arm/src/tiva/cc13xx/cc13xx_start.c
+2 -2
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@@ -149,7 +149,7 @@ static inline void tiva_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
@@ -179,7 +179,7 @@ static inline void tiva_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
arch/arm/src/tiva/common/lmxx_tm4c_start.c
+2 -2
View File
@@ -140,7 +140,7 @@ static inline void tiva_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
@@ -170,7 +170,7 @@ static inline void tiva_fpuconfig(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
arch/arm/src/xmc4/xmc4_start.c
+2 -2
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@@ -171,7 +171,7 @@ static inline void xmc4_fpu_config(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}
@@ -201,7 +201,7 @@ static inline void xmc4_fpu_config(void)
/* Enable full access to CP10 and CP11 */
regval = getreg32(NVIC_CPACR);
regval |= ((3 << (2 * 10)) | (3 << (2 * 11)));
regval |= NVIC_CPACR_CP_FULL(10) | NVIC_CPACR_CP_FULL(11);
putreg32(regval, NVIC_CPACR);
}