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stm32h7: add configuration for STM32H723 chips (STM32H723ZG and STM32H723VG)

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Add definition to setup appropriate reduced SRAM sizes
CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX.
The define should make addition of other STM32H72X
and TM32H73X chips easier.

Signed-off-by: Pavel Pisa <pisa@fel.cvut.cz>
This commit is contained in:
Pavel Pisa
2025-06-09 13:22:44 +02:00
committed by Alan C. Assis
parent f2ecb8b6e9
commit fad037e4ca
6 changed files with 95 additions and 8 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/arm/include/stm32h7/chip.h
+12 -1
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@@ -55,7 +55,9 @@
* overridden with CONFIG_STM32H7_FLASH_OVERRIDE_x * overridden with CONFIG_STM32H7_FLASH_OVERRIDE_x
*/ */
#if defined (CONFIG_ARCH_CHIP_STM32H743AG) || \ #if defined (CONFIG_ARCH_CHIP_STM32H723VG) || \
defined (CONFIG_ARCH_CHIP_STM32H723ZG) || \
defined (CONFIG_ARCH_CHIP_STM32H743AG) || \
defined (CONFIG_ARCH_CHIP_STM32H743AI) || \ defined (CONFIG_ARCH_CHIP_STM32H743AI) || \
defined (CONFIG_ARCH_CHIP_STM32H743BG) || \ defined (CONFIG_ARCH_CHIP_STM32H743BG) || \
defined (CONFIG_ARCH_CHIP_STM32H743BI) || \ defined (CONFIG_ARCH_CHIP_STM32H743BI) || \
@@ -91,12 +93,21 @@
#if defined(CONFIG_STM32H7_STM32H7X0XX) || defined(CONFIG_STM32H7_STM32H7X3XX) || defined(CONFIG_STM32H7_STM32H7X5XX) #if defined(CONFIG_STM32H7_STM32H7X0XX) || defined(CONFIG_STM32H7_STM32H7X3XX) || defined(CONFIG_STM32H7_STM32H7X5XX)
/* Memory */ /* Memory */
# ifdef CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX
# define STM32H7_SRAM_SIZE (320*1024) /* 320Kb SRAM on AXI bus Matrix (D1) */
# define STM32H7_SRAM1_SIZE (16*1024) /* 16Kb SRAM1 on AHB bus Matrix (D2) */
# define STM32H7_SRAM2_SIZE (16*1024) /* 16Kb SRAM2 on AHB bus Matrix (D2) */
# define STM32H7_SRAM3_SIZE (0*1024) /* No SRAM3 on AHB bus Matrix (D2) */
# define STM32H7_SRAM123_SIZE (32*1024) /* 32Kb SRAM123 on AHB bus Matrix (D2) */
# define STM32H7_SRAM4_SIZE (16*1024) /* 16Kb SRAM4 on AHB bus Matrix (D3) */
# else /* STM32H74XXX or STM32H75XXX with full SRAM configuration */
# define STM32H7_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */ # define STM32H7_SRAM_SIZE (512*1024) /* 512Kb SRAM on AXI bus Matrix (D1) */
# define STM32H7_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */ # define STM32H7_SRAM1_SIZE (128*1024) /* 128Kb SRAM1 on AHB bus Matrix (D2) */
# define STM32H7_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */ # define STM32H7_SRAM2_SIZE (128*1024) /* 128Kb SRAM2 on AHB bus Matrix (D2) */
# define STM32H7_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */ # define STM32H7_SRAM3_SIZE (32*1024) /* 32Kb SRAM3 on AHB bus Matrix (D2) */
# define STM32H7_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */ # define STM32H7_SRAM123_SIZE (288*1024) /* 128Kb SRAM123 on AHB bus Matrix (D2) */
# define STM32H7_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */ # define STM32H7_SRAM4_SIZE (64*1024) /* 64Kb SRAM2 on AHB bus Matrix (D3) */
# endif /* STM32H72XXX or STM32H73XXX / STM32H74XXX or STM32H75XXX */
# if defined(CONFIG_ARMV7M_HAVE_DTCM) # if defined(CONFIG_ARMV7M_HAVE_DTCM)
# define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */ # define STM32H7_DTCM_SRAM_SIZE (128*1024) /* 128Kb DTCM SRAM on TCM interface */
# else # else
arch/arm/include/stm32h7/stm32h7x3xx_irq.h
+15 -2
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@@ -200,11 +200,24 @@
#define STM32_IRQ_LPUART (STM32_IRQ_FIRST + 142) /* 142: LPUART global interrupt */ #define STM32_IRQ_LPUART (STM32_IRQ_FIRST + 142) /* 142: LPUART global interrupt */
#define STM32_IRQ_WWDG1RST (STM32_IRQ_FIRST + 143) /* 143: Window Watchdog interrupt */ #define STM32_IRQ_WWDG1RST (STM32_IRQ_FIRST + 143) /* 143: Window Watchdog interrupt */
#define STM32_IRQ_CRS (STM32_IRQ_FIRST + 144) /* 144: Clock Recovery System global interrupt */ #define STM32_IRQ_CRS (STM32_IRQ_FIRST + 144) /* 144: Clock Recovery System global interrupt */
#define STM32_IRQ_RESERVED145 (STM32_IRQ_FIRST + 145) /* 145: Reserved */ #define STM32_IRQ_ECC (STM32_IRQ_FIRST + 145) /* 145: Reserved */
#define STM32_IRQ_SAI4 (STM32_IRQ_FIRST + 146) /* 146: SAI4 global interrupt */ #define STM32_IRQ_SAI4 (STM32_IRQ_FIRST + 146) /* 146: SAI4 global interrupt */
#define STM32_IRQ_RESERVED147 (STM32_IRQ_FIRST + 147) /* 147: Reserved */ #define STM32_IRQ_DTS (STM32_IRQ_FIRST + 147) /* 147: Reserved */
#define STM32_IRQ_RESERVED148 (STM32_IRQ_FIRST + 148) /* 148: Reserved */ #define STM32_IRQ_RESERVED148 (STM32_IRQ_FIRST + 148) /* 148: Reserved */
#define STM32_IRQ_WKUP (STM32_IRQ_FIRST + 149) /* 149: WKUP1 to WKUP6 pins */ #define STM32_IRQ_WKUP (STM32_IRQ_FIRST + 149) /* 149: WKUP1 to WKUP6 pins */
#define STM32_IRQ_OCTOSPI2 (STM32_IRQ_FIRST + 150) /* 150: OCTOSPI2 */
#define STM32_IRQ_RESERVED151 (STM32_IRQ_FIRST + 151) /* 151: Reserved */
#define STM32_IRQ_RESERVED152 (STM32_IRQ_FIRST + 152) /* 152: Reserved */
#define STM32_IRQ_FMAC (STM32_IRQ_FIRST + 153) /* 153: FMAC */
#define STM32_IRQ_CORDIC (STM32_IRQ_FIRST + 154) /* 154: CORDIC */
#define STM32_IRQ_UART9 (STM32_IRQ_FIRST + 155) /* 155: UART9 */
#define STM32_IRQ_USART10 (STM32_IRQ_FIRST + 156) /* 156: USART10 */
#define STM32_IRQ_I2C5_EV (STM32_IRQ_FIRST + 157) /* 157: I2C5 Event */
#define STM32_IRQ_I2C5_ER (STM32_IRQ_FIRST + 158) /* 158: I2C5 Error */
#define STM32_IRQ_FDCAN3_0 (STM32_IRQ_FIRST + 159) /* 159: FDCAN3 Interrupt 0 */
#define STM32_IRQ_FDCAN3_1 (STM32_IRQ_FIRST + 160) /* 160: FDCAN3 Interrupt 1 */
#define STM32_IRQ_TIM23 (STM32_IRQ_FIRST + 161) /* 161: TIM23 global */
#define STM32_IRQ_TIM24 (STM32_IRQ_FIRST + 162) /* 162: TIM24 global */
#define STM32_IRQ_NEXTINTS 163 #define STM32_IRQ_NEXTINTS 163
#define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS) #define NR_IRQS (STM32_IRQ_FIRST + STM32_IRQ_NEXTINTS)
arch/arm/src/stm32h7/Kconfig
+61 -1
View File
@@ -12,6 +12,32 @@ choice
default ARCH_CHIP_STM32H743ZI default ARCH_CHIP_STM32H743ZI
depends on ARCH_CHIP_STM32H7 depends on ARCH_CHIP_STM32H7
config ARCH_CHIP_STM32H723VG
bool "STM32H723VG"
select STM32H7_STM32H7X3XX
select STM32H7_STM32H72XXX_OR_STM32H73XXX
select STM32H7_FLASH_CONFIG_G
select STM32H7_IO_CONFIG_V
select STM32H7_HAVE_FDCAN1
select STM32H7_HAVE_FDCAN2
select STM32H7_HAVE_FDCAN3
---help---
STM32 H7 Cortex M7, 1024 Kb FLASH, 564K Kb SRAM,
LQFP144
config ARCH_CHIP_STM32H723ZG
bool "STM32H723ZG"
select STM32H7_STM32H7X3XX
select STM32H7_STM32H72XXX_OR_STM32H73XXX
select STM32H7_FLASH_CONFIG_G
select STM32H7_IO_CONFIG_Z
select STM32H7_HAVE_FDCAN1
select STM32H7_HAVE_FDCAN2
select STM32H7_HAVE_FDCAN3
---help---
STM32 H7 Cortex M7, 1024 Kb FLASH, 564K Kb SRAM,
LQFP144
config ARCH_CHIP_STM32H743AG config ARCH_CHIP_STM32H743AG
bool "STM32H743AG" bool "STM32H743AG"
select STM32H7_STM32H7X3XX select STM32H7_STM32H7X3XX
@@ -491,6 +517,11 @@ config STM32H7_STM32H7X7XX
select STM32H7_HAVE_SPI6 select STM32H7_HAVE_SPI6
select STM32H7_HAVE_RNG select STM32H7_HAVE_RNG
# The reduced SRAM configuration STM32H72X and STM32H73X
config STM32H7_STM32H72XXX_OR_STM32H73XXX
bool
default n
config STM32H7_FLASH_CONFIG_B config STM32H7_FLASH_CONFIG_B
bool bool
default n default n
@@ -700,6 +731,10 @@ config STM32H7_HAVE_FDCAN2
bool bool
default n default n
config STM32H7_HAVE_FDCAN3
bool
default n
config STM32H7_HAVE_RNG config STM32H7_HAVE_RNG
bool bool
default n default n
@@ -938,6 +973,11 @@ config STM32H7_FDCAN2
default n default n
select STM32H7_FDCAN select STM32H7_FDCAN
config STM32H7_FDCAN3
bool "FDCAN3"
default n
select STM32H7_FDCAN
endmenu # STM32H7 FDCAN Selection endmenu # STM32H7 FDCAN Selection
menu "STM32H7 I2C Selection" menu "STM32H7 I2C Selection"
@@ -6394,7 +6434,7 @@ endchoice # Input channel event count
endmenu # QEncoder Driver endmenu # QEncoder Driver
menu "FDCAN Driver Configuration" menu "FDCAN Driver Configuration"
depends on STM32H7_FDCAN1 || STM32H7_FDCAN2 depends on STM32H7_FDCAN1 || STM32H7_FDCAN2 || STM32H7_FDCAN3
menu "FDCAN1 Configuration" menu "FDCAN1 Configuration"
depends on STM32H7_FDCAN1 depends on STM32H7_FDCAN1
@@ -6436,6 +6476,26 @@ config FDCAN2_DATA_BITRATE
endmenu # STM32H7_FDCAN2 endmenu # STM32H7_FDCAN2
menu "FDCAN3 Configuration"
depends on STM32H7_FDCAN3
config FDCAN3_BITRATE
int "CAN bitrate"
depends on !NET_CAN_CANFD
default 1000000
config FDCAN3_ARBI_BITRATE
int "CAN FD Arbitration phase bitrate"
depends on NET_CAN_CANFD
default 1000000
config FDCAN3_DATA_BITRATE
int "CAN FD Data phase bitrate"
depends on NET_CAN_CANFD
default 4000000
endmenu # STM32H7_FDCAN3
config STM32H7_FDCAN_REGDEBUG config STM32H7_FDCAN_REGDEBUG
bool "Enable register dump debugging" bool "Enable register dump debugging"
depends on DEBUG_NET_INFO depends on DEBUG_NET_INFO
arch/arm/src/stm32h7/hardware/stm32h7x3xx_memorymap.h
+5 -1
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@@ -64,9 +64,13 @@
#define STM32_AXISRAM_BASE 0x24000000 /* 0x24000000-0x247fffff: System AXI SRAM */ #define STM32_AXISRAM_BASE 0x24000000 /* 0x24000000-0x247fffff: System AXI SRAM */
#ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7 #ifdef CONFIG_ARCH_CHIP_STM32H7_CORTEXM7
# define STM32_SRAM1_BASE 0x30000000 /* 0x30000000-0x3001ffff: System SRAM1 */ # define STM32_SRAM1_BASE 0x30000000 /* 0x30000000-0x30003fff: System SRAM1 */
# ifdef CONFIG_STM32H7_STM32H72XXX_OR_STM32H73XXX
# define STM32_SRAM2_BASE 0x30004000 /* 0x30004000-0x30007fff: System SRAM2 */
# else /* STM32H74XXX or STM32H75XXX with full SRAM configuration */
# define STM32_SRAM2_BASE 0x30020000 /* 0x30020000-0x3003ffff: System SRAM2 */ # define STM32_SRAM2_BASE 0x30020000 /* 0x30020000-0x3003ffff: System SRAM2 */
# define STM32_SRAM3_BASE 0x30040000 /* 0x30040000-0x30047fff: System SRAM3 */ # define STM32_SRAM3_BASE 0x30040000 /* 0x30040000-0x30047fff: System SRAM3 */
# endif /* STM32H72XXX or STM32H73XXX / STM32H74XXX or STM32H75XXX */
# define STM32_SRAM123_BASE 0x30000000 /* 0x30000000-0x30047fff: System SRAM123 */ # define STM32_SRAM123_BASE 0x30000000 /* 0x30000000-0x30047fff: System SRAM123 */
#else #else
arch/arm/src/stm32h7/stm32_fdcan_sock.c
+1 -2
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@@ -353,7 +353,6 @@ static const struct fdcan_config_s stm32_fdcan1_config =
#endif #endif
#ifdef CONFIG_STM32H7_FDCAN3 #ifdef CONFIG_STM32H7_FDCAN3
# error "FDCAN3 support not yet added to stm32h7x3xx header files (pinmap, irq, etc.)"
static const struct fdcan_config_s stm32_fdcan2_config = static const struct fdcan_config_s stm32_fdcan2_config =
{ {
.tx_pin = GPIO_CAN3_TX, .tx_pin = GPIO_CAN3_TX,
@@ -2499,7 +2498,7 @@ int stm32_fdcansockinitialize(int intf)
#ifdef CONFIG_STM32H7_FDCAN3 #ifdef CONFIG_STM32H7_FDCAN3
case 2: case 2:
priv = &g_fdcan2 priv = &g_fdcan2;
memset(priv, 0, sizeof(struct fdcan_driver_s)); memset(priv, 0, sizeof(struct fdcan_driver_s));
priv->base = STM32_FDCAN3_BASE; priv->base = STM32_FDCAN3_BASE;
priv->iface_idx = 2; priv->iface_idx = 2;
arch/arm/src/stm32h7/stm32_irq.c
+1 -1
View File
@@ -355,7 +355,7 @@ static int stm32_irqinfo(int irq, uintptr_t *regaddr, uint32_t *bit,
} }
else else
#else #else
# warning Missing logic # error Missing logic
#endif #endif
{ {
return ERROR; /* Invalid interrupt */ return ERROR; /* Invalid interrupt */