From fac5cc77b093bfc2cdf7f0c21636a613c5f0c757 Mon Sep 17 00:00:00 2001 From: Juha Niskanen Date: Tue, 28 May 2019 09:14:08 -0600 Subject: [PATCH] arch/arm/src/stm32l4/stm32l4xrxx_rcc.c: Use Range 1 Boost mode if SYSCLK is higher than 80 MHz --- arch/arm/src/stm32l4/hardware/stm32l4_pwr.h | 18 +++++++++++++ arch/arm/src/stm32l4/stm32l4xrxx_rcc.c | 28 +++++++-------------- 2 files changed, 27 insertions(+), 19 deletions(-) diff --git a/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h b/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h index bd0367b338b..0677c51f99d 100644 --- a/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h +++ b/arch/arm/src/stm32l4/hardware/stm32l4_pwr.h @@ -74,6 +74,9 @@ #define STM32L4_PWR_PDCRH_OFFSET 0x005C /* Power Port H pull-down control register */ #define STM32L4_PWR_PUCRI_OFFSET 0x0060 /* Power Port I pull-up control register */ #define STM32L4_PWR_PDCRI_OFFSET 0x0064 /* Power Port I pull-down control register */ +#if defined(CONFIG_STM32L4_STM32L4XR) +# define STM32L4_PWR_CR5_OFFSET 0x0080 /* Power control register 5 */ +#endif /* Register Addresses ***************************************************************/ @@ -102,6 +105,9 @@ #define STM32L4_PWR_PDCRH (STM32L4_PWR_BASE+STM32L4_PWR_PDCRH_OFFSET) #define STM32L4_PWR_PUCRI (STM32L4_PWR_BASE+STM32L4_PWR_PUCRI_OFFSET) #define STM32L4_PWR_PDCRI (STM32L4_PWR_BASE+STM32L4_PWR_PDCRI_OFFSET) +#if defined(CONFIG_STM32L4_STM32L4XR) +# define STM32L4_PWR_CR5 (STM32L4_PWR_BASE+STM32L4_PWR_CR5_OFFSET) +#endif /* Register Bitfield Definitions ****************************************************/ @@ -114,6 +120,9 @@ # define PWR_CR1_LPMS_STOP2 (2 << PWR_CR1_LPMS_SHIFT) /* 010: Stop 2 mode */ # define PWR_CR1_LPMS_STANDBY (3 << PWR_CR1_LPMS_SHIFT) /* 011: Standby mode */ # define PWR_CR1_LPMS_SHUTDOWN (4 << PWR_CR1_LPMS_SHIFT) /* 1xx: Shutdown mode */ +#if defined(CONFIG_STM32L4_STM32L4XR) +# define PWR_CR1_RRSTP (1 << 4) /* Bit 4: SRAM3 retention in Stop 2 mode */ +#endif #define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable Backup domain write protection */ #define PWR_CR1_VOS_SHIFT 9 #define PWR_CR1_VOS_MASK (3 << PWR_CR1_VOS_SHIFT) /* Bits 9-10: Voltage scaling range selection */ @@ -154,6 +163,9 @@ #define PWR_CR3_EWUP5 (1 << 4) /* Bit 4: Enable Wakeup pin WKUP5 */ #define PWR_CR3_RRS (1 << 8) /* Bit 8: SRAM2 retention in Standby mode */ #define PWR_CR3_APC (1 << 10) /* Bit 10: Apply pull-up and pull-down configuration */ +#if defined(CONFIG_STM32L4_STM32L4XR) +# define PWR_CR3_DSIPDEN (1 << 12) /* Bit 12: Enable Pull-down activation on DSI pins */ +#endif #define PWR_CR3_EIWUL (1 << 15) /* Bit 15: Enable internal wakeup line */ /* Power control register 4 */ @@ -202,4 +214,10 @@ /* Port X pull-up/down registers have one bit per port line, with a few exceptions */ +/* Power control register 5 */ + +#if defined(CONFIG_STM32L4_STM32L4XR) +# define PWR_CR5_R1MODE (1 << 8) /* Bit 8: Main regulator in Range 1 normal mode. */ +#endif + #endif /* __ARCH_ARM_SRC_STM32L4_HARDWARE_STM32L4_PWR_H */ diff --git a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c index 37f74c48d4d..01b9d213342 100644 --- a/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c +++ b/arch/arm/src/stm32l4/stm32l4xrxx_rcc.c @@ -726,21 +726,20 @@ static void stm32l4_stdclockconfig(void) if (timeout > 0) { #warning todo: regulator voltage according to clock freq -#if 0 /* Ensure Power control is enabled before modifying it. */ - regval = getreg32(STM32L4_RCC_APB1ENR); - regval |= RCC_APB1ENR_PWREN; - putreg32(regval, STM32L4_RCC_APB1ENR); + regval = getreg32(STM32L4_RCC_APB1ENR1); + regval |= RCC_APB1ENR1_PWREN; + putreg32(regval, STM32L4_RCC_APB1ENR1); - /* Select regulator voltage output Scale 1 mode to support system - * frequencies up to 168 MHz. + /* Switch to Range 1 boost mode to support system + * frequencies up to 120 MHz. Range 2 is not supported. */ - regval = getreg32(STM32L4_PWR_CR); - regval &= ~PWR_CR_VOS_MASK; - regval |= PWR_CR_VOS_SCALE_1; - putreg32(regval, STM32L4_PWR_CR); +#if STM32L4_SYSCLK_FREQUENCY > 80000000 + regval = getreg32(STM32L4_PWR_CR5); + regval &= ~PWR_CR5_R1MODE; + putreg32(regval, STM32L4_PWR_CR5); #endif /* Set the HCLK source/divider */ @@ -933,15 +932,6 @@ static void stm32l4_stdclockconfig(void) * XXX and other cases, like automatic trimming of MSI for USB use */ - /* ensure Power control is enabled since it is indirectly required - * to alter the LSE parameters. - */ - stm32l4_pwr_enableclk(true); - - /* XXX other LSE settings must be made before turning on the oscillator - * and we need to ensure it is first off before doing so. - */ - /* Turn on the LSE oscillator * XXX this will almost surely get moved since we also want to use * this for automatically trimming MSI, etc.