diff --git a/arch/arm/src/stm32h7/Make.defs b/arch/arm/src/stm32h7/Make.defs index f11e9dfc4ae..4e0a8790a3c 100644 --- a/arch/arm/src/stm32h7/Make.defs +++ b/arch/arm/src/stm32h7/Make.defs @@ -108,7 +108,7 @@ endif CHIP_ASRCS = CHIP_CSRCS = stm32_allocateheap.c stm32_exti_gpio.c stm32_gpio.c stm32_irq.c -CHIP_CSRCS += stm32_start.c +CHIP_CSRCS += stm32_start.c stm32_rcc.c ifneq ($(CONFIG_SCHED_TICKLESS),y) CHIP_CSRCS += stm32_timerisr.c diff --git a/arch/arm/src/stm32h7/chip.h b/arch/arm/src/stm32h7/chip.h index cdb52053bcf..127f5c2a661 100644 --- a/arch/arm/src/stm32h7/chip.h +++ b/arch/arm/src/stm32h7/chip.h @@ -48,6 +48,8 @@ #include #include +#include "chip/stm32_pinmap.h" +#include "chip/stm32_memorymap.h" /* If the common ARMv7-M vector handling logic is used, then it expects the * following definition in this file that provides the number of supported external diff --git a/arch/arm/src/stm32h7/chip/stm32_pwr.h b/arch/arm/src/stm32h7/chip/stm32_pwr.h new file mode 100644 index 00000000000..64d7bbe07d4 --- /dev/null +++ b/arch/arm/src/stm32h7/chip/stm32_pwr.h @@ -0,0 +1,52 @@ +/************************************************************************************ + * arch/arm/src/stm32h7/chip/stm32_pwr.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H7_CHIP_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32H7_CHIP_STM32_PWR_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include "chip.h" + +#if defined(CONFIG_STM32H7_STM32H7X3XX) +# include "chip/stm32h7x3xx_pwr.h" +#else +# error "Unsupported STM32 H7 part" +#endif + +#endif /* __ARCH_ARM_SRC_STM32H7_CHIP_STM32_PWR_H */ diff --git a/arch/arm/src/stm32h7/chip/stm32h7x3xx_flash.h b/arch/arm/src/stm32h7/chip/stm32h7x3xx_flash.h index a78caaeb613..824093b69b3 100644 --- a/arch/arm/src/stm32h7/chip/stm32h7x3xx_flash.h +++ b/arch/arm/src/stm32h7/chip/stm32h7x3xx_flash.h @@ -71,28 +71,28 @@ /* Register Addresses ***************************************************************/ -#define STM32_FLASH_ACR (STM32_FLASHIF_BASE+STM32_FLASH_ACR_OFFSET) -#define STM32_FLASH_KEYR (STM32_FLASHIF_BASE+STM32_FLASH_KEYR_OFFSET) -#define STM32_FLASH_OPTKEYR (STM32_FLASHIF_BASE+STM32_FLASH_OPTKEYR_OFFSET) -#define STM32_FLASH_CR (STM32_FLASHIF_BASE+STM32_FLASH_CR_OFFSET) -#define STM32_FLASH_SR (STM32_FLASHIF_BASE+STM32_FLASH_SR_OFFSET) -#define STM32_FLASH_CCR (STM32_FLASHIF_BASE+STM32_FLASH_CCR_OFFSET) -#define STM32_FLASH_OPTCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCR_OFFSET) -#define STM32_FLASH_OPTSRCUR (STM32_FLASHIF_BASE+STM32_FLASH_OPTSRCUR_OFFSET) -#define STM32_FLASH_OPTSRPRG (STM32_FLASHIF_BASE+STM32_FLASH_OPTSRPRG_OFFSET) -#define STM32_FLASH_OPTCCR (STM32_FLASHIF_BASE+STM32_FLASH_OPTCCR_OFFSET) -#define STM32_FLASH_PRARCUR (STM32_FLASHIF_BASE+STM32_FLASH_PRARCUR_OFFSET) -#define STM32_FLASH_PRARPRG (STM32_FLASHIF_BASE+STM32_FLASH_PRARPRG_OFFSET) -#define STM32_FLASH_SCARCUR (STM32_FLASHIF_BASE+STM32_FLASH_SCARCUR_OFFSET) -#define STM32_FLASH_SCARPRG (STM32_FLASHIF_BASE+STM32_FLASH_SCARPRG_OFFSET) -#define STM32_FLASH_WPSNCUR (STM32_FLASHIF_BASE+STM32_FLASH_WPSNCUR_OFFSET) -#define STM32_FLASH_BOOTCUR (STM32_FLASHIF_BASE+STM32_FLASH_BOOTCUR_OFFSET) -#define STM32_FLASH_BOOTPRGR (STM32_FLASHIF_BASE+STM32_FLASH_BOOTPRGR_OFFSET) -#define STM32_FLASH_CRCCR (STM32_FLASHIF_BASE+STM32_FLASH_CRCCR_OFFSET) -#define STM32_FLASH_CRCSADDR (STM32_FLASHIF_BASE+STM32_FLASH_CRCSADDR_OFFSET) -#define STM32_FLASH_CRCEADDR (STM32_FLASHIF_BASE+STM32_FLASH_CRCEADDR_OFFSET) -#define STM32_FLASH_CRCDATAR (STM32_FLASHIF_BASE+STM32_FLASH_CRCDATAR_OFFSET) -#define STM32_FLASH_ECCFAR (STM32_FLASHIF_BASE+STM32_FLASH_ECCFAR_OFFSET) +#define STM32_FLASH_ACR (STM32_FLASH_BASE+STM32_FLASH_ACR_OFFSET) +#define STM32_FLASH_KEYR (STM32_FLASH_BASE+STM32_FLASH_KEYR_OFFSET) +#define STM32_FLASH_OPTKEYR (STM32_FLASH_BASE+STM32_FLASH_OPTKEYR_OFFSET) +#define STM32_FLASH_CR (STM32_FLASH_BASE+STM32_FLASH_CR_OFFSET) +#define STM32_FLASH_SR (STM32_FLASH_BASE+STM32_FLASH_SR_OFFSET) +#define STM32_FLASH_CCR (STM32_FLASH_BASE+STM32_FLASH_CCR_OFFSET) +#define STM32_FLASH_OPTCR (STM32_FLASH_BASE+STM32_FLASH_OPTCR_OFFSET) +#define STM32_FLASH_OPTSRCUR (STM32_FLASH_BASE+STM32_FLASH_OPTSRCUR_OFFSET) +#define STM32_FLASH_OPTSRPRG (STM32_FLASH_BASE+STM32_FLASH_OPTSRPRG_OFFSET) +#define STM32_FLASH_OPTCCR (STM32_FLASH_BASE+STM32_FLASH_OPTCCR_OFFSET) +#define STM32_FLASH_PRARCUR (STM32_FLASH_BASE+STM32_FLASH_PRARCUR_OFFSET) +#define STM32_FLASH_PRARPRG (STM32_FLASH_BASE+STM32_FLASH_PRARPRG_OFFSET) +#define STM32_FLASH_SCARCUR (STM32_FLASH_BASE+STM32_FLASH_SCARCUR_OFFSET) +#define STM32_FLASH_SCARPRG (STM32_FLASH_BASE+STM32_FLASH_SCARPRG_OFFSET) +#define STM32_FLASH_WPSNCUR (STM32_FLASH_BASE+STM32_FLASH_WPSNCUR_OFFSET) +#define STM32_FLASH_BOOTCUR (STM32_FLASH_BASE+STM32_FLASH_BOOTCUR_OFFSET) +#define STM32_FLASH_BOOTPRGR (STM32_FLASH_BASE+STM32_FLASH_BOOTPRGR_OFFSET) +#define STM32_FLASH_CRCCR (STM32_FLASH_BASE+STM32_FLASH_CRCCR_OFFSET) +#define STM32_FLASH_CRCSADDR (STM32_FLASH_BASE+STM32_FLASH_CRCSADDR_OFFSET) +#define STM32_FLASH_CRCEADDR (STM32_FLASH_BASE+STM32_FLASH_CRCEADDR_OFFSET) +#define STM32_FLASH_CRCDATAR (STM32_FLASH_BASE+STM32_FLASH_CRCDATAR_OFFSET) +#define STM32_FLASH_ECCFAR (STM32_FLASH_BASE+STM32_FLASH_ECCFAR_OFFSET) /* Register Bitfield Definitions ****************************************************/ /* Flash Access Control Register (ACR) */ @@ -117,7 +117,7 @@ # define FLASH_ACR_LATENCY_14 (14 << FLASH_ACR_LATENCY_SHIFT) /* 1110: Fourteen wait states */ # define FLASH_ACR_LATENCY_15 (15 << FLASH_ACR_LATENCY_SHIFT) /* 1111: Fifteen wait states */ #define FLASH_ACR_WRHIGHFREQ_SHIFT (4) /* Bitd 4-5: Flash signal delay */ -#define FLASH_ACR_WRHIGHFREQ_MASK (4 << FLASH_ACR_WRHIGHFREQ_SHIFT) +#define FLASH_ACR_WRHIGHFREQ_MASK (3 << FLASH_ACR_WRHIGHFREQ_SHIFT) # define FLASH_ACR_WRHIGHFREQ(n) ((n) << FLASH_ACR_WRHIGHFREQ_SHIFT) /* Flash Control Register (CR) */ @@ -135,7 +135,7 @@ #define FLASH_CR_FW (1 << 6) /* Bit 6: Force write */ #define FLASH_CR_START (1 << 7) /* Bit 7: Erase start */ #define FLASH_CR_SNB_SHIFT (8) /* Bits 8-10: Sector number */ -#define FLASH_CR_SNB_MASK (0xf << FLASH_CR_SNB_SHIFT) /* Used to clear FLASH_CR_SNB bits */ +#define FLASH_CR_SNB_MASK (15 << FLASH_CR_SNB_SHIFT) /* Used to clear FLASH_CR_SNB bits */ # define FLASH_CR_SNB(n) ((uint32_t)(n & 0x7) << FLASH_CR_SNB_SHIFT)) /* Sector n, n=0..7 */ /* Bits 11-14: Reserved */ #define FLASH_CR_CRCEN (1 << 15) /* Bit 15: CRC control enable */ @@ -206,7 +206,7 @@ #define FLASH_OPTSR_BUSYV (1 << 0) /* Bit 0: Option byte change busy */ /* Bit 1: Reserved */ #define FLASH_OPTSR_BORLEV_SHIFT (2) /* Bits 2-3: Brownout level option */ -#define FLASH_OPTSR_BORLEV_MASK (1 << FLASH_OPTSR_BORLEV_SHIFT) +#define FLASH_OPTSR_BORLEV_MASK (3 << FLASH_OPTSR_BORLEV_SHIFT) # define FLASH_OPTSR_BORLEV_0 (0 << FLASH_OPTSR_BORLEV_SHIFT) # define FLASH_OPTSR_BORLEV_1 (1 << FLASH_OPTSR_BORLEV_SHIFT) # define FLASH_OPTSR_BORLEV_2 (2 << FLASH_OPTSR_BORLEV_SHIFT) @@ -221,7 +221,7 @@ #define FLASH_OPTSR_IWDGFZSTOP (1 << 17) /* Bit 17: IWDG Stop mode freeze */ #define FLASH_OPTSR_IWDGFZSTBY (1 << 18) /* Bit 18: IWDG Standby mode freeze */ #define FLASH_OPTSR_STRAMSIZE_SHIFT (19) /* Bits 19-20: ST RAM size */ -#define FLASH_OPTSR_STRAMSIZE_MASK (4 << FLASH_OPTSR_STRAMSIZE_SHIFT) +#define FLASH_OPTSR_STRAMSIZE_MASK (3 << FLASH_OPTSR_STRAMSIZE_SHIFT) # define FLASH_OPTSR_STRAMSIZE_2 (0 << FLASH_OPTSR_STRAMSIZE_SHIFT) # define FLASH_OPTSR_STRAMSIZE_4 (1 << FLASH_OPTSR_STRAMSIZE_SHIFT) # define FLASH_OPTSR_STRAMSIZE_8 (2 << FLASH_OPTSR_STRAMSIZE_SHIFT) @@ -235,7 +235,7 @@ /* Flash Option Clear Control Register (OPTCCR) */ /* Bits 0-29: Reserved */ -#define FLASH_OPTCR_OPTLOCK (1 << 30) /* Bit 30: OPTCHANGEERR reset */ +#define FLASH_OPTCCR_OPTLOCK (1 << 30) /* Bit 30: OPTCHANGEERR reset */ /* Bit 31: Reserved */ /* TODO: Flash Protection Address (PRAR) */ @@ -245,7 +245,7 @@ /* Flash Write Sector Protection (WPSN) */ #define FLASH_WPSN_WRPSN_SHIFT (0) /* Bits 0-7L Sector write protection option */ -#define FLASH_WPSN_WRPSN_MASK (0xf << FLASH_WPSN_WRPSN_SHIFT) +#define FLASH_WPSN_WRPSN_MASK (15 << FLASH_WPSN_WRPSN_SHIFT) /* Bits 8-31: Reserved */ /* Flash Register Boot Address (BOOT) */ diff --git a/arch/arm/src/stm32h7/chip/stm32h7x3xx_pinmap.h b/arch/arm/src/stm32h7/chip/stm32h7x3xx_pinmap.h index d23307c0250..1ea3b73f22f 100644 --- a/arch/arm/src/stm32h7/chip/stm32h7x3xx_pinmap.h +++ b/arch/arm/src/stm32h7/chip/stm32h7x3xx_pinmap.h @@ -234,7 +234,7 @@ #define GPIO_ETH_MII_TXD0_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN13) #define GPIO_ETH_MII_TXD1_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN13) #define GPIO_ETH_MII_TXD1_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN12) -#define GPIO_ETH_MII_TXD1_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14) +#define GPIO_ETH_MII_TXD1_3 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTG|GPIO_PIN14) #define GPIO_ETH_MII_TXD2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTC|GPIO_PIN2) #define GPIO_ETH_MII_TXD3_1 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTB|GPIO_PIN8) #define GPIO_ETH_MII_TXD3_2 (GPIO_ALT|GPIO_AF11|GPIO_SPEED_100MHz|GPIO_PUSHPULL|GPIO_PORTE|GPIO_PIN2) diff --git a/arch/arm/src/stm32h7/chip/stm32h7x3xx_pwr.h b/arch/arm/src/stm32h7/chip/stm32h7x3xx_pwr.h new file mode 100644 index 00000000000..6c3ad5092ed --- /dev/null +++ b/arch/arm/src/stm32h7/chip/stm32h7x3xx_pwr.h @@ -0,0 +1,122 @@ +/************************************************************************************ + * arch/arm/src/stm32h7/chip/stm32h7x3xx_pwr.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Mateusz Szafoni + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM327_CHIP_STM32H7X3XX_PWR_H +#define __ARCH_ARM_SRC_STM327_CHIP_STM32H7X3XX_PWR_H + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +/* Register Offsets *****************************************************************/ + +#define STM32_PWR_CR1_OFFSET 0x0000 /* Power control register 1 */ +#define STM32_PWR_CSR1_OFFSET 0x0004 /* Power control/status register 1 */ +#define STM32_PWR_CR2_OFFSET 0x0008 /* Power control register 2 */ +#define STM32_PWR_CR3_OFFSET 0x000c /* Power control register 3 */ +#define STM32_PWR_CPUCR_OFFSET 0x0010 /* Power CPU control register */ + /* 0x014: Reserved */ +#define STM32_PWR_D3CR_OFFSET 0x0018 /* Power D3 domain control register */ +#define STM32_PWR_WKUPCR_OFFSET 0x0020 /* Power wakeup clear register */ +#define STM32_PWR_WKUPFR_OFFSET 0x0024 /* Power wakeup flag register */ +#define STM32_PWR_WKUPEPR_OFFSET 0x0028 /* Power wakeup enable and polarity register*/ + /* 0x030: Reserved */ + +/* Register Addresses ***************************************************************/ + +#define STM32_PWR_CR1 (STM32_PWR_BASE+STM32_PWR_CR1_OFFSET) +#define STM32_PWR_CSR1 (STM32_PWR_BASE+STM32_PWR_CSR1_OFFSET) +#define STM32_PWR_CR2 (STM32_PWR_BASE+STM32_PWR_CR2_OFFSET) +#define STM32_PWR_CR3 (STM32_PWR_BASE+STM32_PWR_CR3_OFFSET) +#define STM32_PWR_CPUCR (STM32_PWR_BASE+STM32_PWR_CPUCR_OFFSET) +#define STM32_PWR_D3CR (STM32_PWR_BASE+STM32_PWR_D3CR_OFFSET) +#define STM32_PWR_WKUPCR (STM32_PWR_BASE+STM32_PWR_WKUPCR_OFFSET) +#define STM32_PWR_WKUPFR (STM32_PWR_BASE+STM32_PWR_WKUPFR_OFFSET) +#define STM32_PWR_WKUPEOR (STM32_PWR_BASE+STM32_PWR_WKUPEOR_OFFSET) + +/* Register Bitfield Definitions ****************************************************/ + +/* Power control register 1 (CR1) */ + +#define PWR_CR1_LPDS (1 << 0) /* Bit 0: Low-power Deepsleep with SVOS3 */ + /* Bits 1-3: Reserved */ +#define PWR_CR1_PVDE (1 << 4) /* Bit 4: Programmable voltage detector enable */ + + +#define PWR_CR1_PLS_SHIFT (5) /* Bits 5-7: Programmable voltage detector level */ +#define PWR_CR1_PLS_MASK (7 << PWR_CR1_PLS_SHIFT) +# define PWR_CR1_PLS_1V95 (0 << PWR_CR1_PLS_SHIFT) /* 000: */ +# define PWR_CR1_PLS_2V1 (1 << PWR_CR1_PLS_SHIFT) /* 001: */ +# define PWR_CR1_PLS_2V25 (2 << PWR_CR1_PLS_SHIFT) /* 010: */ +# define PWR_CR1_PLS_2V4 (3 << PWR_CR1_PLS_SHIFT) /* 011: */ +# define PWR_CR1_PLS_2V55 (4 << PWR_CR1_PLS_SHIFT) /* 100: */ +# define PWR_CR1_PLS_2V7 (5 << PWR_CR1_PLS_SHIFT) /* 101: */ +# define PWR_CR1_PLS_2V85 (6 << PWR_CR1_PLS_SHIFT) /* 110: */ +# define PWR_CR1_PLS_EXT (7 << PWR_CR1_PLS_SHIFT) /* 111: */ +#define PWR_CR1_DBP (1 << 8) /* Bit 8: Disable backup domain write protection */ +#define PWR_CR1_FLPS (1 << 9) /* Bit 9: */ + /* Bits 10-13: Reserved */ +#define PWR_CR1_SVOS_SHIFT (1 << 14) /* Bits 14-15: */ +#define PWR_CR1_SVOS_MASK (3 << PWR_CR1_SVOS_SHIFT) + /* 00: Reserved */ +# define PWR_CR1_SVOS_S5 (1 << PWR_CR1_SVOS_SHIFT) /* 01: */ +# define PWR_CR1_SVOS_S4 (2 << PWR_CR1_SVOS_SHIFT) /* 10: */ +# define PWR_CR1_SVOS_S3 (3 << PWR_CR1_SVOS_SHIFT) /* 11: */ +#define PWR_CR1_AVDEN (1 << 16) /* Bit 16: */ +#define PWR_CR1_ALS_SHIFT (17) /* Bits 17-18: Analog voltage detector level selection */ +#define PWR_CR1_ALS_MASK (3 << PWR_CR1_ALS_SHIFT) +# define PWR_CR1_ALS_1V7 (0 << PWR_CR1_ALS_SHIFT) /* 00: */ +# define PWR_CR1_ALS_2V1 (1 << PWR_CR1_ALS_SHIFT) /* 01 */ +# define PWR_CR1_ALS_2V5 (2 << PWR_CR1_ALS_SHIFT) /* 10: */ +# define PWR_CR1_ALS_2V8 (3 << PWR_CR1_ALS_SHIFT) /* 11: */ + /* Bits 19-31: Reserved */ + +/* Power control/status register 1 (CRS1) */ + +/* Power control register 2 (CR2) */ + +/* Power control register 3 (CR3) */ + +/* Power CPU control register (CPUCR) */ + +/* Power D3 domain control register (D3CR) */ + +/* Power wakeup clear register (WKUPCR) */ + +/* Power wakeup flag register (WKUPFR) */ + +/* Power wakeup enable and polarity register (WKUPEPR) */ + +#endif /* __ARCH_ARM_SRC_STM327_CHIP_STM32H7X3XX_PWR_H */ diff --git a/arch/arm/src/stm32h7/chip/stm32h7x3xx_rcc.h b/arch/arm/src/stm32h7/chip/stm32h7x3xx_rcc.h index 53e2ecca502..2d486d9439b 100644 --- a/arch/arm/src/stm32h7/chip/stm32h7x3xx_rcc.h +++ b/arch/arm/src/stm32h7/chip/stm32h7x3xx_rcc.h @@ -4,6 +4,7 @@ * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * David Sidrane + * Mateusz Szafoni * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -167,80 +168,37 @@ /* Source Control Register */ -#define RCC_CR_HSION_SHIFT (0ul) -#define RCC_CR_HSION_MASK (0x1ul << RCC_CR_HSION_SHIFT) /* 0x00000001 */ -#define RCC_CR_HSION RCC_CR_HSION_MASK /* Internal High Speed clock enable */ -#define RCC_CR_HSIKERON_SHIFT (1ul) -#define RCC_CR_HSIKERON_MASK (0x1ul << RCC_CR_HSIKERON_SHIFT) /* 0x00000002 */ -#define RCC_CR_HSIKERON RCC_CR_HSIKERON_MASK /* Internal High Speed clock enable for some IPs Kernel */ -#define RCC_CR_HSIRDY_SHIFT (2ul) -#define RCC_CR_HSIRDY_MASK (0x1ul << RCC_CR_HSIRDY_SHIFT) /* 0x00000004 */ -#define RCC_CR_HSIRDY RCC_CR_HSIRDY_MASK /* Internal High Speed clock ready flag */ -#define RCC_CR_HSIDIV_SHIFT (3ul) -#define RCC_CR_HSIDIV_MASK (0x3ul << RCC_CR_HSIDIV_SHIFT) /* 0x00000018 */ -#define RCC_CR_HSIDIV RCC_CR_HSIDIV_MASK /* Internal High Speed clock divider selection */ -#define RCC_CR_HSIDIV_1 (0x0ul << RCC_CR_HSIDIV_SHIFT) /* 0x00000000 */ -#define RCC_CR_HSIDIV_2 (0x1ul << RCC_CR_HSIDIV_SHIFT) /* 0x00000008 */ -#define RCC_CR_HSIDIV_4 (0x2ul << RCC_CR_HSIDIV_SHIFT) /* 0x00000010 */ -#define RCC_CR_HSIDIV_8 (0x3ul << RCC_CR_HSIDIV_SHIFT) /* 0x00000018 */ - -#define RCC_CR_HSIDIVF_SHIFT (5ul) -#define RCC_CR_HSIDIVF_MASK (0x1ul << RCC_CR_HSIDIVF_SHIFT) /* 0x00000020 */ -#define RCC_CR_HSIDIVF RCC_CR_HSIDIVF_MASK /* HSI Divider flag */ -#define RCC_CR_CSION_SHIFT (7ul) -#define RCC_CR_CSION_MASK (0x1ul << RCC_CR_CSION_SHIFT) /* 0x00000080 */ -#define RCC_CR_CSION RCC_CR_CSION_MASK /* The Internal RC 4MHz oscillator clock enable */ -#define RCC_CR_CSIRDY_SHIFT (8ul) -#define RCC_CR_CSIRDY_MASK (0x1ul << RCC_CR_CSIRDY_SHIFT) /* 0x00000100 */ -#define RCC_CR_CSIRDY RCC_CR_CSIRDY_MASK /* The Internal RC 4MHz oscillator clock ready */ -#define RCC_CR_CSIKERON_SHIFT (9ul) -#define RCC_CR_CSIKERON_MASK (0x1ul << RCC_CR_CSIKERON_SHIFT) /* 0x00000200 */ -#define RCC_CR_CSIKERON RCC_CR_CSIKERON_MASK /* Internal RC 4MHz oscillator clock enable for some IPs Kernel */ -#define RCC_CR_HSI48ON_SHIFT (12ul) -#define RCC_CR_HSI48ON_MASK (0x1ul << RCC_CR_HSI48ON_SHIFT) /* 0x00001000 */ -#define RCC_CR_HSI48ON RCC_CR_HSI48ON_MASK /* HSI48 clock enable clock enable */ -#define RCC_CR_HSI48RDY_SHIFT (13ul) -#define RCC_CR_HSI48RDY_MASK (0x1ul << RCC_CR_HSI48RDY_SHIFT) /* 0x00002000 */ -#define RCC_CR_HSI48RDY RCC_CR_HSI48RDY_MASK /* HSI48 clock ready */ - -#define RCC_CR_D1CKRDY_SHIFT (14ul) -#define RCC_CR_D1CKRDY_MASK (0x1ul << RCC_CR_D1CKRDY_SHIFT) /* 0x00004000 */ -#define RCC_CR_D1CKRDY RCC_CR_D1CKRDY_MASK /* D1 domain clocks ready flag */ -#define RCC_CR_D2CKRDY_SHIFT (15ul) -#define RCC_CR_D2CKRDY_MASK (0x1ul << RCC_CR_D2CKRDY_SHIFT) /* 0x00008000 */ -#define RCC_CR_D2CKRDY RCC_CR_D2CKRDY_MASK /* D2 domain clocks ready flag */ - -#define RCC_CR_HSEON_SHIFT (16ul) -#define RCC_CR_HSEON_MASK (0x1ul << RCC_CR_HSEON_SHIFT) /* 0x00010000 */ -#define RCC_CR_HSEON RCC_CR_HSEON_MASK /* External High Speed clock enable */ -#define RCC_CR_HSERDY_SHIFT (17ul) -#define RCC_CR_HSERDY_MASK (0x1ul << RCC_CR_HSERDY_SHIFT) /* 0x00020000 */ -#define RCC_CR_HSERDY RCC_CR_HSERDY_MASK /* External High Speed clock ready */ -#define RCC_CR_HSEBYP_SHIFT (18ul) -#define RCC_CR_HSEBYP_MASK (0x1ul << RCC_CR_HSEBYP_SHIFT) /* 0x00040000 */ -#define RCC_CR_HSEBYP RCC_CR_HSEBYP_MASK /* External High Speed clock Bypass */ -#define RCC_CR_CSSHSEON_SHIFT (19ul) -#define RCC_CR_CSSHSEON_MASK (0x1ul << RCC_CR_CSSHSEON_SHIFT) /* 0x00080000 */ -#define RCC_CR_CSSHSEON RCC_CR_CSSHSEON_MASK /* HSE Clock security System enable */ - -#define RCC_CR_PLL1ON_SHIFT (24ul) -#define RCC_CR_PLL1ON_MASK (0x1ul << RCC_CR_PLL1ON_SHIFT) /* 0x01000000 */ -#define RCC_CR_PLL1ON RCC_CR_PLL1ON_MASK /* System PLL1 clock enable */ -#define RCC_CR_PLL1RDY_SHIFT (25ul) -#define RCC_CR_PLL1RDY_MASK (0x1ul << RCC_CR_PLL1RDY_SHIFT) /* 0x02000000 */ -#define RCC_CR_PLL1RDY RCC_CR_PLL1RDY_MASK /* System PLL1 clock ready */ -#define RCC_CR_PLL2ON_SHIFT (26ul) -#define RCC_CR_PLL2ON_MASK (0x1ul << RCC_CR_PLL2ON_SHIFT) /* 0x04000000 */ -#define RCC_CR_PLL2ON RCC_CR_PLL2ON_MASK /* System PLL2 clock enable */ -#define RCC_CR_PLL2RDY_SHIFT (27ul) -#define RCC_CR_PLL2RDY_MASK (0x1ul << RCC_CR_PLL2RDY_SHIFT) /* 0x08000000 */ -#define RCC_CR_PLL2RDY RCC_CR_PLL2RDY_MASK /* System PLL2 clock ready */ -#define RCC_CR_PLL3ON_SHIFT (28ul) -#define RCC_CR_PLL3ON_MASK (0x1ul << RCC_CR_PLL3ON_SHIFT) /* 0x10000000 */ -#define RCC_CR_PLL3ON RCC_CR_PLL3ON_MASK /* System PLL3 clock enable */ -#define RCC_CR_PLL3RDY_SHIFT (29ul) -#define RCC_CR_PLL3RDY_MASK (0x1ul << RCC_CR_PLL3RDY_SHIFT) /* 0x20000000 */ -#define RCC_CR_PLL3RDY RCC_CR_PLL3RDY_MASK /* System PLL3 clock ready */ +#define RCC_CR_HSION (1 << 0) /* Bit 0: Internal High Speed clock enable */ +#define RCC_CR_HSIKERON (1 << 1) /* Bit 1: Internal High Speed clock enable for some IPs Kernel ?? */ +#define RCC_CR_HSIRDY (1 << 2) /* Bit 2: Internal High Speed clock ready flag */ +#define RCC_CR_HSIDIV_SHIFT (3) /* Bits 3-4: HSI clock divider */ +#define RCC_CR_HSIDIV_MASK (3 << RCC_CR_HSIDIV_SHIFT) /* 00: */ +# define RCC_CR_HSIDIV_1 (0 << RCC_CR_HSIDIV_SHIFT) /* 01: */ +# define RCC_CR_HSIDIV_2 (1 << RCC_CR_HSIDIV_SHIFT) /* 10: */ +# define RCC_CR_HSIDIV_4 (2 << RCC_CR_HSIDIV_SHIFT) /* 10: */ +# define RCC_CR_HSIDIV_8 (3 << RCC_CR_HSIDIV_SHIFT) /* 11: */ +#define RCC_CR_HSIDIVF (1 << 5) /* Bit 5: HSI Divider flag */ + /* Bit 6: Reserved */ +#define RCC_CR_CSION (1 << 7) /* Bit 7: The Internal RC 4MHz oscillator clock enable */ +#define RCC_CR_CSIRDY (1 << 8) /* Bit 8: The Internal RC 4MHz oscillator clock ready */ +#define RCC_CR_CSIKERON (1 << 9) /* Bit 9: Internal RC 4MHz oscillator clock enable for some IPs Kernel */ + /* Bits 10-11: Reserved */ +#define RCC_CR_HSI48ON (1 << 12) /* Bit 12: HSI48 clock enable clock enable */ +#define RCC_CR_HSI48RDY (1 << 13) /* Bit 13: HSI48 clock ready */ +#define RCC_CR_D1CKRDY (1 << 14) /* Bit 14: D1 domain clocks ready flag */ +#define RCC_CR_D2CKRDY (1 << 15) /* Bit 15: D2 domain clocks ready flag */ +#define RCC_CR_HSEON (1 << 16) /* Bit 16: External High Speed clock enable */ +#define RCC_CR_HSERDY (1 << 17) /* Bit 17: External High Speed clock ready */ +#define RCC_CR_HSEBYP (1 << 18) /* Bit 18: External High Speed clock Bypass */ +#define RCC_CR_CSSHSEON (1 << 19) /* Bit 19: HSE Clock security System enable */ + /* Bits 20-23: Reserved */ +#define RCC_CR_PLL1ON (1 << 24) /* Bit 24: System PLL1 clock enable */ +#define RCC_CR_PLL1RDY (1 << 25) /* Bit 25: System PLL1 clock ready */ +#define RCC_CR_PLL2ON (1 << 26) /* Bit 26: System PLL2 clock enable */ +#define RCC_CR_PLL2RDY (1 << 27) /* Bit 27: System PLL2 clock ready */ +#define RCC_CR_PLL3ON (1 << 28) /* Bit 28: System PLL3 clock enable */ +#define RCC_CR_PLL3RDY (1 << 29) /* Bit 29: System PLL3 clock ready */ + /* Bits 30-31: Reserved */ /* Internal Clock Source Calibration Register */ @@ -276,61 +234,120 @@ #define RCC_CRRCR_HSI48CAL_MASK (0x3FFul << RCC_CRRCR_HSI48CAL_SHIFT) /* 0x000003FF */ #define RCC_CRRCR_HSI48CAL RCC_CRRCR_HSI48CAL_MASK /* HSI48CAL[9:0] bits */ -/* Clock Configuration Register */ - -/* SW configuration */ - -#define RCC_CFGR_SW ((uint32_t)0x00000007) /* SW[2:0] bits (System clock Switch) */ -#define RCC_CFGR_SW_HSI ((uint32_t)0x00000000) /* HSI selection as system clock */ -#define RCC_CFGR_SW_CSI ((uint32_t)0x00000001) /* CSI selection as system clock */ -#define RCC_CFGR_SW_HSE ((uint32_t)0x00000002) /* HSE selection as system clock */ -#define RCC_CFGR_SW_PLL1 ((uint32_t)0x00000003) /* PLL1 selection as system clock */ - -/* SWS configuration */ - -#define RCC_CFGR_SWS ((uint32_t)0x00000038) /* SWS[2:0] bits (System Clock Switch Status) */ -#define RCC_CFGR_SWS_HSI ((uint32_t)0x00000000) /* HSI used as system clock */ -#define RCC_CFGR_SWS_CSI ((uint32_t)0x00000008) /* CSI used as system clock */ -#define RCC_CFGR_SWS_HSE ((uint32_t)0x00000010) /* HSE used as system clock */ -#define RCC_CFGR_SWS_PLL1 ((uint32_t)0x00000018) /* PLL1 used as system clock */ - -#define RCC_CFGR_STOPWUCK ((uint32_t)0x00000040) /* Wake Up from stop and CSS backup clock selection */ -#define RCC_CFGR_STOPKERWUCK ((uint32_t)0x00000080) /* Kernel Clock Selection after a Wake Up from STOP */ - -/* RTCPRE configuration */ - -#define RCC_CFGR_RTCPRE(x) (((uint32_t)(x)) << 8) /* HSE division factor for RTC clock (2 - 63) */ - -#define RCC_CFGR_HRTIMSEL ((uint32_t)0x00004000) -#define RCC_CFGR_TIMPRE ((uint32_t)0x00008000) - -/* MCO1 configuration */ +/* Clock Configuration Register (CFGR) */ +#define RCC_CFGR_SW_SHIFT (1) /* Bits 0-2: System clock Switch */ +#define RCC_CFGR_SW_MASK (7 << RCC_CFGR_SW_SHIFT) +# define RCC_CFGR_SW_HSI (0 << RCC_CFGR_SW_SHIFT) /* 000: HSI selection as system clock */ +# define RCC_CFGR_SW_CSI (1 << RCC_CFGR_SW_SHIFT) /* 001: CSI selection as system clock */ +# define RCC_CFGR_SW_HSE (2 << RCC_CFGR_SW_SHIFT) /* 010: HSE selection as system clock */ +# define RCC_CFGR_SW_PLL1 (3 << RCC_CFGR_SW_SHIFT) /* 011: PLL1 selection as system clock */ +#define RCC_CFGR_SWS_SHIFT (3) /* Bits 3-5: System Clock Switch Status */ +#define RCC_CFGR_SWS_MASK (7 << RCC_CFGR_SWS_SHIFT) +# define RCC_CFGR_SWS_HSI (0 << RCC_CFGR_SWS_SHIFT) /* 000: HSI used as system clock */ +# define RCC_CFGR_SWS_CSI (1 << RCC_CFGR_SWS_SHIFT) /* 001: CSI used as system clock */ +# define RCC_CFGR_SWS_HSE (2 << RCC_CFGR_SWS_SHIFT) /* 010: HSE used as system clock */ +# define RCC_CFGR_SWS_PLL1 (3 << RCC_CFGR_SWS_SHIFT) /* 011: PLL1 used as system clock */ +#define RCC_CFGR_STOPWUCK (1 << 6) /* Bit 6: Wake Up from stop and CSS backup clock selection */ +#define RCC_CFGR_STOPKERWUCK (1 << 7) /* Bit 7: Kernel Clock Selection after a Wake Up from STOP */ +#define RCC_CFGR_RTCPRE_SHIFT (8) /* Bits 8-13: HSE division factor for RTC clock */ +#define RCC_CFGR_RTCPRE_MASK (0x3f << RCC_CFGR_RTCPRE_SHIFT) +# define RCC_CFGR_RTCPRE(x) (((uint32_t)(x)) << RCC_CFGR_RTCPRE_SHIFT) +#define RCC_CFGR_HRTIMSEL (1 << 14) /* Bit 14: HRTIM TImer clock prescaler */ +#define RCC_CFGR_TIMPRE (1 << 15) /* Timers clocks prescaler */ +#define RCC_CFGR_MCO1PRE_SHIFT (18) /* Bits 18-21: MCO1 prescaler */ +#define RCC_CFGR_MCO1PRE_MASK (0xf << RCC_CFGR_MCO1PRE_SHIFT) +# define RCC_CFGR_MCO1PRE(x) (((uint32_t)(x)) << 18) #define RCC_CFGR_MCO1_SHIFT (22) /* Bits 22-24: Microcontroller Clock Output 1 */ -#define RCC_CFGR_MCO1_MASK (7ul << RCC_CFGR_MCO1_SHIFT) -#define RCC_CFGR_MCO1_HSI (0ul << RCC_CFGR_MCO1_SHIFT) /* 000: HSI clock selected */ -#define RCC_CFGR_MCO1_LSE (1ul << RCC_CFGR_MCO1_SHIFT) /* 001: LSE oscillator selected */ -#define RCC_CFGR_MCO1_HSE (2ul << RCC_CFGR_MCO1_SHIFT) /* 010: HSE oscillator clock selected */ -#define RCC_CFGR_MCO1_PLL (3ul << RCC_CFGR_MCO1_SHIFT) /* 011: PLL clock selected */ -#define RCC_CFGR_MCO1_PLL (4ul << RCC_CFGR_MCO1_SHIFT) /* 100: HSI48 clock selected */ -#define RCC_CFGR_MCO1PRE(x) (((uint32_t)(x)) << 18) /* MCO1 prescaler */ +#define RCC_CFGR_MCO1_MASK (7 << RCC_CFGR_MCO1_SHIFT) +# define RCC_CFGR_MCO1_HSI (0 << RCC_CFGR_MCO1_SHIFT) /* 000: HSI clock selected */ +# define RCC_CFGR_MCO1_LSE (1 << RCC_CFGR_MCO1_SHIFT) /* 001: LSE oscillator selected */ +# define RCC_CFGR_MCO1_HSE (2 << RCC_CFGR_MCO1_SHIFT) /* 010: HSE oscillator clock selected */ +# define RCC_CFGR_MCO1_PLL (3 << RCC_CFGR_MCO1_SHIFT) /* 011: PLL clock selected */ +# define RCC_CFGR_MCO1_HSI48 (4 << RCC_CFGR_MCO1_SHIFT) /* 100: HSI48 clock selected */ +#define RCC_CFGR_MCO2PRE_SHIFT (25) /* Bits 25-28: MCO2 prescaler */ +#define RCC_CFGR_MCO2PRE_MASK (0xf << RCC_CFGR_MCO2PRE_SHIFT) +# define RCC_CFGR_MCO2PRE(x) (((uint32_t)(x)) << RCC_CFGR_MCO2PRE_SHIFT) +#define RCC_CFGR_MCO2_SHIFT (29) /* Bits 29-31: Microcontroller Clock Output 2 */ +#define RCC_CFGR_MCO2_MASK (7 << RCC_CFGR_MCO1_SHIFT) +# define RCC_CFGR_MCO2_HSI (0 << RCC_CFGR_MCO1_SHIFT) /* 000: HSI clock selected */ +# define RCC_CFGR_MCO2_LSE (1 << RCC_CFGR_MCO1_SHIFT) /* 001: LSE oscillator selected */ +# define RCC_CFGR_MCO2_HSE (2 << RCC_CFGR_MCO1_SHIFT) /* 010: HSE oscillator clock selected */ +# define RCC_CFGR_MCO2_PLL (3 << RCC_CFGR_MCO1_SHIFT) /* 011: PLL clock selected */ +# define RCC_CFGR_MCO2_HSI48 (4 << RCC_CFGR_MCO1_SHIFT) /* 100: HSI48 clock selected */ -/* MCO2 configuration */ +/* Bit definitions for RCC_D1CFGR */ -#define RCC_CFGR_MCO2_SHIFT (29) /* Bits 29-31: Microcontroller Clock Output 2 */ -#define RCC_CFGR_MCO2_MASK (7ul << RCC_CFGR_MCO1_SHIFT) -#define RCC_CFGR_MCO2_HSI (0ul << RCC_CFGR_MCO1_SHIFT) /* 000: HSI clock selected */ -#define RCC_CFGR_MCO2_LSE (1ul << RCC_CFGR_MCO1_SHIFT) /* 001: LSE oscillator selected */ -#define RCC_CFGR_MCO2_HSE (2ul << RCC_CFGR_MCO1_SHIFT) /* 010: HSE oscillator clock selected */ -#define RCC_CFGR_MCO2_PLL (3ul << RCC_CFGR_MCO1_SHIFT) /* 011: PLL clock selected */ -#define RCC_CFGR_MCO2_PLL (4ul << RCC_CFGR_MCO1_SHIFT) /* 100: HSI48 clock selected */ -#define RCC_CFGR_MCO2PRE(x) (((uint32_t)(x)) << 25) /* MCO2 prescaler */ +#define RCC_D1CFGR_HPRE_SHIFT (0) /* Bits 0-3: D1 domain AHB prescaler */ +#define RCC_D1CFGR_HPRE_MASK (15 << RCC_D1CFGR_HPRE_SHIFT) +# define RCC_D1CFGR_HPRE_SYSCLK (0 << RCC_D1CFGR_HPRE_SHIFT) /* 0xxx: */ +# define RCC_D1CFGR_HPRE_SYSCLKd2 (8 << RCC_D1CFGR_HPRE_SHIFT) /* 1000: */ +# define RCC_D1CFGR_HPRE_SYSCLKd4 (9 << RCC_D1CFGR_HPRE_SHIFT) /* 1001: */ +# define RCC_D1CFGR_HPRE_SYSCLKd8 (10 << RCC_D1CFGR_HPRE_SHIFT) /* 1010: */ +# define RCC_D1CFGR_HPRE_SYSCLKd16 (11 << RCC_D1CFGR_HPRE_SHIFT) /* 1011: */ +# define RCC_D1CFGR_HPRE_SYSCLKd64 (12 << RCC_D1CFGR_HPRE_SHIFT) /* 1100: */ +# define RCC_D1CFGR_HPRE_SYSCLKd128 (13 << RCC_D1CFGR_HPRE_SHIFT) /* 1101: */ +# define RCC_D1CFGR_HPRE_SYSCLKd256 (14 << RCC_D1CFGR_HPRE_SHIFT) /* 1110: */ +# define RCC_D1CFGR_HPRE_SYSCLKd512 (15 << RCC_D1CFGR_HPRE_SHIFT) /* 1111: */ + +#define RCC_D1CFGR_D1PPRE_SHIFT (4) /* Bits 4-6: D1 domain APB3 prescaler */ +#define RCC_D1CFGR_D1PPRE_MASK (7 << RCC_D1CFGR_D1PPRE_SHIFT) +# define RCC_D1CFGR_D1PPRE_HCLK (0 << RCC_D1CFGR_D1PPRE_SHIFT) /* 0xx: */ +# define RCC_D1CFGR_D1PPRE_HCLKd2 (4 << RCC_D1CFGR_D1PPRE_SHIFT) /* 100: */ +# define RCC_D1CFGR_D1PPRE_HCLKd4 (5 << RCC_D1CFGR_D1PPRE_SHIFT) /* 101: */ +# define RCC_D1CFGR_D1PPRE_HCLKd8 (6 << RCC_D1CFGR_D1PPRE_SHIFT) /* 110: */ +# define RCC_D1CFGR_D1PPRE_HCLKd16 (7 << RCC_D1CFGR_D1PPRE_SHIFT) /* 111: */ + /* Bit 7: Reserved */ +#define RCC_D1CFGR_D1CPRE_SHIFT (8) /* Bits 8-11: D1 domain Core prescaler */ +#define RCC_D1CFGR_D1CPRE_MASK (15 << RCC_D1CFGR_D1CPRE_SHIFT) +# define RCC_D1CFGR_D1CPRE_SYSCLK (0 << RCC_D1CFGR_D1CPRE_SHIFT) /* 0xxx: */ +# define RCC_D1CFGR_D1CPRE_SYSCLKd2 (8 << RCC_D1CFGR_D1CPRE_SHIFT) /* 1000: */ +# define RCC_D1CFGR_D1CPRE_SYSCLKd4 (9 << RCC_D1CFGR_D1CPRE_SHIFT) /* 1001: */ +# define RCC_D1CFGR_D1CPRE_SYSCLKd8 (10 << RCC_D1CFGR_D1CPRE_SHIFT) /* 1010: */ +# define RCC_D1CFGR_D1CPRE_SYSCLKd16 (11 << RCC_D1CFGR_D1CPRE_SHIFT) /* 1011: */ +# define RCC_D1CFGR_D1CPRE_SYSCLKd64 (12 << RCC_D1CFGR_D1CPRE_SHIFT) /* 1100: */ +# define RCC_D1CFGR_D1CPRE_SYSCLKd128 (13 << RCC_D1CFGR_D1CPRE_SHIFT) /* 1101: */ +# define RCC_D1CFGR_D1CPRE_SYSCLKd256 (14 << RCC_D1CFGR_D1CPRE_SHIFT) /* 1110: */ +# define RCC_D1CFGR_D1CPRE_SYSCLKd512 (15 << RCC_D1CFGR_D1CPRE_SHIFT) /* 1111: */ + /* Bits 12-31: Reserved */ + +/* Bit definitions for RCC_D2CFGR */ + + /* Bits 0-3: Reserved */ +#define RCC_D2CFGR_D2PPRE1_SHIFT (4) /* Bits 4-6: D2 domain APB1 prescaler */ +#define RCC_D2CFGR_D2PPRE1_MASK (7 << RCC_D2CFGR_D2PPRE1_SHIFT) +#define RCC_D2CFGR_D2PPRE1_HCLK (0 << RCC_D2CFGR_D2PPRE1_SHIFT) /* 0xx: */ +#define RCC_D2CFGR_D2PPRE1_HCLKd2 (4 << RCC_D2CFGR_D2PPRE1_SHIFT) /* 100: */ +#define RCC_D2CFGR_D2PPRE1_HCLKd4 (5 << RCC_D2CFGR_D2PPRE1_SHIFT) /* 101: */ +#define RCC_D2CFGR_D2PPRE1_HCLKd8 (6 << RCC_D2CFGR_D2PPRE1_SHIFT) /* 110: */ +#define RCC_D2CFGR_D2PPRE1_HCLKd16 (7 << RCC_D2CFGR_D2PPRE1_SHIFT) /* 111: */ + /* Bit 7: Reserved */ +#define RCC_D2CFGR_D2PPRE2_SHIFT (8) /* Bits 8-10: D2 domain APB2 prescaler */ +#define RCC_D2CFGR_D2PPRE2_MASK (7 << RCC_D2CFGR_D2PPRE2_SHIFT) +#define RCC_D2CFGR_D2PPRE2_HCLK (0 << RCC_D2CFGR_D2PPRE2_SHIFT) /* 0xx: */ +#define RCC_D2CFGR_D2PPRE2_HCLKd2 (4 << RCC_D2CFGR_D2PPRE2_SHIFT) /* 100: */ +#define RCC_D2CFGR_D2PPRE2_HCLKd4 (5 << RCC_D2CFGR_D2PPRE2_SHIFT) /* 101: */ +#define RCC_D2CFGR_D2PPRE2_HCLKd8 (6 << RCC_D2CFGR_D2PPRE2_SHIFT) /* 110: */ +#define RCC_D2CFGR_D2PPRE2_HCLKd16 (7 << RCC_D2CFGR_D2PPRE2_SHIFT) /* 111: */ + /* Bits 11-31: Reserved */ + +/* Bit definitions for RCC_D3CFGR */ + + /* Bits 0-3: Reserved */ +#define RCC_D3CFGR_D3PPRE_SHIFT (4) /* Bits 4-6: D3 domain APB4 prescaler */ +#define RCC_D3CFGR_D3PPRE_MASK (7 << RCC_D3CFGR_D3PPRE_SHIFT) +#define RCC_D3CFGR_D3PPRE_HCLK (0 << RCC_D3CFGR_D3PPRE_SHIFT) /* 0xx: */ +#define RCC_D3CFGR_D3PPRE_HCLKd2 (4 << RCC_D3CFGR_D3PPRE_SHIFT) /* 100: */ +#define RCC_D3CFGR_D3PPRE_HCLKd4 (5 << RCC_D3CFGR_D3PPRE_SHIFT) /* 101: */ +#define RCC_D3CFGR_D3PPRE_HCLKd8 (6 << RCC_D3CFGR_D3PPRE_SHIFT) /* 110: */ +#define RCC_D3CFGR_D3PPRE_HCLKd16 (7 << RCC_D3CFGR_D3PPRE_SHIFT) /* 111: */ + /* Bits 7-31: Reserved */ /* Bit definitions for RCC_PLLCKSELR register */ -#define RCC_PLLCKSELR_PLLSRC_SHIFT (0ul) -#define RCC_PLLCKSELR_PLLSRC_MASK (0x3ul << RCC_PLLCKSELR_PLLSRC_SHIFT) /* 0x00000003 */ -#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_MASK +#define RCC_PLLCKSELR_PLLSRC_SHIFT (0) /* Bit 0: */ +#define RCC_PLLCKSELR_PLLSRC_MASK (0x3 << RCC_PLLCKSELR_PLLSRC_SHIFT) +#define RCC_PLLCKSELR_PLLSRC RCC_PLLCKSELR_PLLSRC_MASK #define RCC_PLLCKSELR_PLLSRC_HSI ((uint32_t)0x00000000) /* HSI source clock selected */ #define RCC_PLLCKSELR_PLLSRC_CSI ((uint32_t)0x00000001) /* CSI source clock selected */ diff --git a/arch/arm/src/stm32h7/stm32_pwr.h b/arch/arm/src/stm32h7/stm32_pwr.h new file mode 100644 index 00000000000..f6f1b31e21a --- /dev/null +++ b/arch/arm/src/stm32h7/stm32_pwr.h @@ -0,0 +1,134 @@ +/************************************************************************************ + * arch/arm/src/stm32h7/stm32_pwr.h + * + * Copyright (C) 2018 Gregory Nutt. All rights reserved. + * Authors: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32H7_STM32_PWR_H +#define __ARCH_ARM_SRC_STM32H7_STM32_PWR_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + +#include + +#include "chip.h" +#include "chip/stm32_pwr.h" + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/************************************************************************************ + * Public Functions + ************************************************************************************/ + +/************************************************************************************ + * Name: stm32_pwr_initbkp + * + * Description: + * Insures the referenced count access to the backup domain (RTC registers, + * RTC backup data registers and backup SRAM is consistent with the HW state + * without relying on a variable. + * + * NOTE: This function should only be called by SoC Start up code. + * + * Input Parameters: + * writable - set the initial state of the enable and the + * bkp_writable_counter + * + * Returned Value: + * None + * + ************************************************************************************/ + +void stm32_pwr_initbkp(bool writable); + +/************************************************************************************ + * Name: stm32_pwr_enablebkp + * + * Description: + * Enables access to the backup domain (RTC registers, RTC backup data registers + * and backup SRAM). + * + * Input Parameters: + * writable - True: enable ability to write to backup domain registers + * + * Returned Value: + * none + * + ************************************************************************************/ + +void stm32_pwr_enablebkp(bool writable); + +/************************************************************************************ + * Name: stm32_pwr_enablebreg + * + * Description: + * Enables the Backup regulator, the Backup regulator (used to maintain backup + * SRAM content in Standby and VBAT modes) is enabled. If BRE is reset, the backup + * regulator is switched off. The backup SRAM can still be used but its content will + * be lost in the Standby and VBAT modes. Once set, the application must wait that + * the Backup Regulator Ready flag (BRR) is set to indicate that the data written + * into the RAM will be maintained in the Standby and VBAT modes. + * + * Input Parameters: + * regon - state to set it to + * + * Returned Value: + * None + * + ************************************************************************************/ + +void stm32_pwr_enablebreg(bool regon); + +#undef EXTERN +#if defined(__cplusplus) +} +#endif + +#endif /* __ASSEMBLY__ */ +#endif /* __ARCH_ARM_SRC_STM32H7_STM32_PWR_H */ diff --git a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c index 9ebaf194676..7fe25dbe153 100644 --- a/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c +++ b/arch/arm/src/stm32h7/stm32h7x3xx_rcc.c @@ -4,6 +4,7 @@ * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * David Sidrane + * Mateusz Szafoni * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -38,7 +39,7 @@ * Included Files ****************************************************************************/ -// TODO: #include "stm32_pwr.h" +#include "stm32_pwr.h" /**************************************************************************** * Pre-processor Definitions @@ -380,39 +381,42 @@ static void stm32_stdclockconfig(void) if (timeout > 0) { - /* Select regulator voltage output Scale 1 mode to support system - * frequencies up to 216 MHz. - */ - - regval = getreg32(STM32_RCC_APB1ENR); - regval |= RCC_APB1ENR_PWREN; - putreg32(regval, STM32_RCC_APB1ENR); - - regval = getreg32(STM32_PWR_CR1); - regval &= ~PWR_CR1_VOS_MASK; - regval |= PWR_CR1_VOS_SCALE_1; - putreg32(regval, STM32_PWR_CR1); /* Set the HCLK source/divider */ - regval = getreg32(STM32_RCC_CFGR); - regval &= ~RCC_CFGR_HPRE_MASK; - regval |= STM32_RCC_CFGR_HPRE; - putreg32(regval, STM32_RCC_CFGR); + regval = getreg32(STM32_RCC_D1CFGR); + regval &= ~RCC_D1CFGR_HPRE_MASK; + regval |= STM32_RCC_D1CFGR_HPRE; + putreg32(regval, STM32_RCC_D1CFGR); - /* Set the PCLK2 divider */ + /* Set PCLK1 */ - regval = getreg32(STM32_RCC_CFGR); - regval &= ~RCC_CFGR_PPRE2_MASK; - regval |= STM32_RCC_CFGR_PPRE2; - putreg32(regval, STM32_RCC_CFGR); + regval = getreg32(STM32_RCC_D2CFGR); + regval &= ~RCC_D2CFGR_D2PPRE2_MASK; + regval |= STM32_RCC_D2CFGR_D2PPRE1; + putreg32(regval, STM32_RCC_D2CFGR); - /* Set the PCLK1 divider */ + /* Set PCLK2 */ + + regval = getreg32(STM32_RCC_D2CFGR); + regval &= ~RCC_D2CFGR_D2PPRE2_MASK; + regval |= STM32_RCC_D2CFGR_D2PPRE2; + putreg32(regval, STM32_RCC_D2CFGR); + + /* Set PCLK3 */ + + regval = getreg32(STM32_RCC_D1CFGR); + regval &= ~RCC_D1CFGR_D1PPRE_MASK; + regval |= STM32_RCC_D1CFGR_D1PPRE; + putreg32(regval, STM32_RCC_D1CFGR); + + /* Set PCLK4 */ + + regval = getreg32(STM32_RCC_D3CFGR); + regval &= ~RCC_D3CFGR_D3PPRE_MASK; + regval |= STM32_RCC_D3CFGR_D3PPRE; + putreg32(regval, STM32_RCC_D3CFGR); - regval = getreg32(STM32_RCC_CFGR); - regval &= ~RCC_CFGR_PPRE1_MASK; - regval |= STM32_RCC_CFGR_PPRE1; - putreg32(regval, STM32_RCC_CFGR); #ifdef CONFIG_STM32H7_RTC_HSECLOCK /* Set the RTC clock divisor */ @@ -423,42 +427,65 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_RCC_CFGR); #endif - /* Set the PLL dividers and multipliers to configure the main PLL */ + /* Configure PLL123 clock source and multipiers */ #ifdef STM32_BOARD_USEHSI - regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP | - RCC_PLLCFG_PLLSRC_HSI | STM32_PLLCFG_PLLQ); + regval = (RCC_PLLCKSELR_PLLSRC_HSI | + STM32_PLLCFG_PLL1M | + STM32_PLLCFG_PLL2M | + STM32_PLLCFG_PLL3M); #else /* if STM32_BOARD_USEHSE */ - regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP | - RCC_PLLCFG_PLLSRC_HSE | STM32_PLLCFG_PLLQ); + regval = (RCC_PLLCKSELR_PLLSRC_HSE | + STM32_PLLCFG_PLL1M | + STM32_PLLCFG_PLL2M | + STM32_PLLCFG_PLL3M); #endif - putreg32(regval, STM32_RCC_PLLCFG); + putreg32(regval, STM32_RCC_PLLCKSELR); - /* Enable the main PLL */ + /* Configure PLL1 dividers */ + + regval = (STM32_PLLCFG_PLL1N | + STM32_PLLCFG_PLL1P | + STM32_PLLCFG_PLL1Q | + STM32_PLLCFG_PLL1R); + putreg32(regval, STM32_RCC_PLL1DIVR); + + /* Configure PLL2 dividers */ + + regval = (STM32_PLLCFG_PLL2N | + STM32_PLLCFG_PLL2P | + STM32_PLLCFG_PLL2Q | + STM32_PLLCFG_PLL2R); + putreg32(regval, STM32_RCC_PLL2DIVR); + + /* Configure PLL3 dividers */ + + regval = (STM32_PLLCFG_PLL3N | + STM32_PLLCFG_PLL3P | + STM32_PLLCFG_PLL3Q | + STM32_PLLCFG_PLL3R); + putreg32(regval, STM32_RCC_PLL3DIVR); + + /* Configure PLLs */ + + regval = (STM32_PLLCFG_PLL1CFG | + STM32_PLLCFG_PLL2CFG | + STM32_PLLCFG_PLL3CFG); + putreg32(regval, STM32_RCC_PLLCFGR); + + /* Enable the PLL1 */ regval = getreg32(STM32_RCC_CR); - regval |= RCC_CR_PLLON; + regval |= RCC_CR_PLL1ON; putreg32(regval, STM32_RCC_CR); + /* TODO: Enable the PLL2 */ + + /* TODO: Enable the PLL3 */ + /* Wait until the PLL is ready */ - while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) - { - } - - /* Enable the Over-drive to extend the clock frequency to 216 Mhz */ - - regval = getreg32(STM32_PWR_CR1); - regval |= PWR_CR1_ODEN; - putreg32(regval, STM32_PWR_CR1); - while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODRDY) == 0) - { - } - - regval = getreg32(STM32_PWR_CR1); - regval |= PWR_CR1_ODSWEN; - putreg32(regval, STM32_PWR_CR1); - while ((getreg32(STM32_PWR_CSR1) & PWR_CSR1_ODSWRDY) == 0) + while ((getreg32(STM32_RCC_CR) & RCC_CR_PLL1RDY) == 0) { } @@ -478,16 +505,16 @@ static void stm32_stdclockconfig(void) putreg32(regval, STM32_FLASH_ACR); - /* Select the main PLL as system clock source */ + /* Select the PLL1 as system clock source */ regval = getreg32(STM32_RCC_CFGR); regval &= ~RCC_CFGR_SW_MASK; - regval |= RCC_CFGR_SW_PLL; + regval |= RCC_CFGR_SW_PLL1; putreg32(regval, STM32_RCC_CFGR); /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) + while ((getreg32(STM32_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL1) { } diff --git a/configs/nucleo-h743zi/include/board.h b/configs/nucleo-h743zi/include/board.h index 4e02595f273..48fe9e12dfa 100644 --- a/configs/nucleo-h743zi/include/board.h +++ b/configs/nucleo-h743zi/include/board.h @@ -4,6 +4,7 @@ * Copyright (C) 2018 Gregory Nutt. All rights reserved. * Authors: Gregory Nutt * Simon Laube + * Mateusz Szafoni * * Redistribution and use in source and binary forms, with or without * modification, are permitted provided that the following conditions @@ -112,7 +113,7 @@ #define STM32_PLLCFG_PLLSRC RCC_PLLCKSELR_PLLSRC_HSE -/* Wide PLL, 4 - 8 MHz input, enable DIVP */ +/* Wide PLL1, 4 - 8 MHz input, enable DIVP */ #define STM32_PLLCFG_PLL1CFG (RCC_PLLCFGR_PLL1VCOSEL_WIDE | \ RCC_PLLCFGR_PLL1RGE_4_8_MHZ | \ @@ -123,6 +124,24 @@ #define STM32_PLLCFG_PLL1Q RCC_PLL1DIVR_Q1(4) #define STM32_PLLCFG_PLL1R RCC_PLL1DIVR_R1(8) +/* PLL2 */ + +#define STM32_PLLCFG_PLL2CFG 0 +#define STM32_PLLCFG_PLL2M 0 +#define STM32_PLLCFG_PLL2N 0 +#define STM32_PLLCFG_PLL2P 0 +#define STM32_PLLCFG_PLL2Q 0 +#define STM32_PLLCFG_PLL2R 0 + +/* PLL3 */ + +#define STM32_PLLCFG_PLL3CFG 0 +#define STM32_PLLCFG_PLL3M 0 +#define STM32_PLLCFG_PLL3N 0 +#define STM32_PLLCFG_PLL3P 0 +#define STM32_PLLCFG_PLL3Q 0 +#define STM32_PLLCFG_PLL3R 0 + #define STM32_VCO1_FREQUENCY ((STM32_HSE_FREQUENCY / 4) * 200) #define STM32_SYSCLK_FREQUENCY (STM32_VCO1_FREQUENCY / 1) #define STM32_CPUCLK_FREQUENCY (STM32_SYSCLK_FREQUENCY / 1) @@ -140,25 +159,30 @@ /* AHB3 clock is SYSCLK (216 MHz) */ -#define STM32_RCC_CFGR_HPRE RCC_CFGR_HPRE_SYSCLKd2 /* HCLK = SYSCLK / 2 */ +#define STM32_RCC_D1CFGR_HPRE RCC_D1CFGR_HPRE_SYSCLKd2 /* HCLK = SYSCLK / 2 */ #define STM32_ACLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* ACLK in D1, HCLK3 in D1 */ #define STM32_HCLK_FREQUENCY (STM32_CPUCLK_FREQUENCY / 2) /* HCLK in D2, HCLK4 in D3 */ #define STM32_BOARD_HCLK STM32_HCLK_FREQUENCY /* same as above, to satisfy compiler */ /* APB3 clock (PCLK1) is HCLK/4 (54 MHz) */ -#define STM32_RCC_CFGR_D1PPRE RCC_CFGR_D1PPRE_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) +#define STM32_RCC_D1CFGR_D1PPRE RCC_D1CFGR_D1PPRE_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK3_FREQUENCY (STM32_HCLK_FREQUENCY/4) /* APB1 clock is HCLK/4 (54 MHz) */ -#define STM32_RCC_CFGR_D2PPRE1 RCC_CFGR_D2PPRE1_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) +#define STM32_RCC_D2CFGR_D2PPRE1 RCC_D2CFGR_D2PPRE1_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) /* APB2 clock is HCLK/4 (54 MHz) */ -#define STM32_RCC_CFGR_D2PPRE2 RCC_CFGR_D2PPRE2_HCLK /* PCLK1 = HCLK / 1 */ -#define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) +#define STM32_RCC_D2CFGR_D2PPRE2 RCC_D2CFGR_D2PPRE2_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK2_FREQUENCY (STM32_HCLK_FREQUENCY/4) + +/* APB4 clock is HCLK/4 (54 MHz) */ + +#define STM32_RCC_D3CFGR_D3PPRE RCC_D3CFGR_D3PPRE_HCLKd4 /* PCLK1 = HCLK / 4 */ +#define STM32_PCLK4_FREQUENCY (STM32_HCLK_FREQUENCY/4) /* FLASH wait states *