arch/arm64: add ARM64_DCACHE_DISABLE and ARM64_ICACHE_DISABLE config

Enable dcache and icache when ARM64_DCACHE_DISABLE and ARM64_ICACHE_DISABLE
disabled at __start.

Signed-off-by: zhangyuan21 <zhangyuan21@xiaomi.com>

arch/arm64/Kconfig

@@ -219,6 +219,14 @@ config ARM_GIC_EOIMODE
 
 endif
 
+config ARM64_DCACHE_DISABLE
+	bool "Disable DCACHE at __start"
+	default n
+
+config ARM64_ICACHE_DISABLE
+	bool "Disable ICACHE at __start"
+	default n
+
 if ARCH_CHIP_A64
 source "arch/arm64/src/a64/Kconfig"
 endif

arch/arm64/src/common/arm64_boot.c

@@ -55,6 +55,12 @@ void arm64_boot_el3_init(void)
 {
   uint64_t reg;
 
+#ifndef CONFIG_ARM64_ICACHE_DISABLE
+  reg = read_sysreg(sctlr_el3);
+  reg |= SCTLR_I_BIT;
+  write_sysreg(reg, sctlr_el3);
+#endif
+
   /* Setup vector table */
 
   write_sysreg((uint64_t)_vector_table, vbar_el3);
@@ -108,9 +114,11 @@ void arm64_boot_el2_init(void)
 {
   uint64_t reg;
 
-  reg   = read_sysreg(sctlr_el2);
+  reg = 0U;                   /* RES0 */
-  reg   |= (SCTLR_EL2_RES1 |    /* RES1 */
+  reg = (SCTLR_EL2_RES1 |     /* RES1 */
+#ifndef CONFIG_ARM64_ICACHE_DISABLE
          SCTLR_I_BIT |        /* Enable i-cache */
+#endif
          SCTLR_SA_BIT);       /* Enable SP alignment check */
   write_sysreg(reg, sctlr_el2);
 
@@ -166,9 +174,11 @@ void arm64_boot_el1_init(void)
 
   write_sysreg(reg, cpacr_el1);
 
-  reg   = read_sysreg(sctlr_el1);
+  reg = 0U;                   /* RES0 */
-  reg   |= (SCTLR_EL1_RES1 |    /* RES1 */
+  reg = (SCTLR_EL1_RES1 |     /* RES1 */
+#ifndef CONFIG_ARM64_ICACHE_DISABLE
          SCTLR_I_BIT |        /* Enable i-cache */
+#endif
          SCTLR_SA_BIT);       /* Enable SP alignment check */
   write_sysreg(reg, sctlr_el1);
 

arch/arm64/src/common/arm64_head.S

@@ -292,7 +292,7 @@ __reset_prep_c:
 #ifdef CONFIG_ARCH_HAVE_EL3
     /* Reinitialize SCTLR from scratch in EL3 */
 
-    ldr   w0, =(SCTLR_EL3_RES1 | SCTLR_I_BIT | SCTLR_SA_BIT)
+    ldr   w0, =(SCTLR_EL3_RES1 | SCTLR_SA_BIT)
     msr   sctlr_el3, x0
 #endif
 

arch/arm64/src/common/arm64_mmu.c

@@ -541,7 +541,11 @@ static void enable_mmu_el1(unsigned int flags)
   /* Enable the MMU and data cache */
 
   value = read_sysreg(sctlr_el1);
-  write_sysreg((value | SCTLR_M_BIT | SCTLR_C_BIT), sctlr_el1);
+  write_sysreg((value | SCTLR_M_BIT
+#ifndef CONFIG_ARM64_DCACHE_DISABLE
+               | SCTLR_C_BIT
+#endif
+               ), sctlr_el1);
 
   /* Ensure the MMU enable takes effect immediately */
 

arch/arm64/src/common/arm64_mpu.c

@@ -99,7 +99,11 @@ void arm64_core_mpu_enable(void)
   uint64_t val;
 
   val = read_sysreg(sctlr_el1);
-  val   |= (SCTLR_M_BIT | SCTLR_C_BIT);
+  val |= (SCTLR_M_BIT
+#ifndef CONFIG_ARM64_DCACHE_DISABLE
+          | SCTLR_C_BIT
+#endif
+         );
   write_sysreg(val, sctlr_el1);
   ARM64_DSB();
   ARM64_ISB();