diff --git a/arch/arm/src/stm32/Kconfig b/arch/arm/src/stm32/Kconfig index 11a6ca3ff92..07218af0655 100644 --- a/arch/arm/src/stm32/Kconfig +++ b/arch/arm/src/stm32/Kconfig @@ -5120,6 +5120,136 @@ config STM32_TIM14_DAC2 endchoice +config STM32_TIM1_CAP + bool "TIM1 Capture + default n + depends on STM32_HAVE_TIM1 + ---help--- + Reserve timer 1 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM1_CAP + bool "TIM1 Capture + default n + depends on STM32_HAVE_TIM1 + ---help--- + Reserve timer 1 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM2_CAP + bool "TIM2 Capture + default n + depends on STM32_HAVE_TIM2 + ---help--- + Reserve timer 2 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM3_CAP + bool "TIM3 Capture + default n + depends on STM32_HAVE_TIM3 + ---help--- + Reserve timer 3 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM4_CAP + bool "TIM4 Capture + default n + depends on STM32_HAVE_TIM4 + ---help--- + Reserve timer 4 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM5_CAP + bool "TIM5 Capture + default n + depends on STM32_HAVE_TIM5 + ---help--- + Reserve timer 5 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM8_CAP + bool "TIM8 Capture + default n + depends on STM32_HAVE_TIM8 + ---help--- + Reserve timer 8 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM9_CAP + bool "TIM9 Capture + default n + depends on STM32_HAVE_TIM9 + ---help--- + Reserve timer 9 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM10_CAP + bool "TIM10 Capture + default n + depends on STM32_HAVE_TIM10 + ---help--- + Reserve timer 10 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM11_CAP + bool "TIM11 Capture + default n + depends on STM32_HAVE_TIM11 + ---help--- + Reserve timer 11 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM12_CAP + bool "TIM12 Capture + default n + depends on STM32_HAVE_TIM12 + ---help--- + Reserve timer 12 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM13_CAP + bool "TIM13 Capture + default n + depends on STM32_HAVE_TIM13 + ---help--- + Reserve timer 13 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + +config STM32_TIM14_CAP + bool "TIM14 Capture + default n + depends on STM32_HAVE_TIM14 + ---help--- + Reserve timer 14 for use by Capture + + Timer devices may be used for different purposes. One special purpose is + to capture input. + menu "ADC Configuration" depends on STM32_ADC diff --git a/arch/arm/src/stm32/stm32_capture.c b/arch/arm/src/stm32/stm32_capture.c new file mode 100644 index 00000000000..fd85d2d3fab --- /dev/null +++ b/arch/arm/src/stm32/stm32_capture.c @@ -0,0 +1,692 @@ +/************************************************************************************ + * arm/arm/src/stm32/stm32_capture.c + * + * Copyright (C) 2015 Bouteville Pierre-Noel. All rights reserved. + * Author: Bouteville Pierre-Noel + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include +#include +#include + +#include +#include +#include +#include +#include +#include + +#include + +#include "chip.h" +#include "up_internal.h" +#include "up_arch.h" + +#include "stm32.h" +#include "stm32_gpio.h" +#include "stm32_capture.h" + +/************************************************************************************ + * Private Types + ************************************************************************************/ +/* Configuration ********************************************************************/ + +#if defined(GPIO_TIM1_CH1IN) || defined(GPIO_TIM2_CH1IN) || defined(GPIO_TIM3_CH1IN) || \ + defined(GPIO_TIM4_CH1IN) || defined(GPIO_TIM5_CH1IN) || defined(GPIO_TIM8_CH1IN) || \ + defined(GPIO_TIM9_CH1IN) || defined(GPIO_TIM10_CH1IN) || defined(GPIO_TIM11_CH1IN) || \ + defined(GPIO_TIM12_CH1IN) || defined(GPIO_TIM13_CH1IN) || defined(GPIO_TIM14_CH1IN) +# define HAVE_CH1IN 1 +#endif + +#if defined(GPIO_TIM1_CH2IN) || defined(GPIO_TIM2_CH2IN) || defined(GPIO_TIM3_CH2IN) || \ + defined(GPIO_TIM4_CH2IN) || defined(GPIO_TIM5_CH2IN) || defined(GPIO_TIM8_CH2IN) || \ + defined(GPIO_TIM9_CH2IN) || defined(GPIO_TIM12_CH2IN) +# define HAVE_CH2IN 1 +#endif + +#if defined(GPIO_TIM1_CH3IN) || defined(GPIO_TIM2_CH3IN) || defined(GPIO_TIM3_CH3IN) || \ + defined(GPIO_TIM4_CH3IN) || defined(GPIO_TIM5_CH3IN) || defined(GPIO_TIM8_CH3IN) +# define HAVE_CH3IN 1 +#endif + +#if defined(GPIO_TIM1_CH4IN) || defined(GPIO_TIM2_CH4IN) || defined(GPIO_TIM3_CH4IN) || \ + defined(GPIO_TIM4_CH4IN) || defined(GPIO_TIM5_CH4IN) || defined(GPIO_TIM8_CH4IN) +# define HAVE_CH4IN 1 +#endif + +#if defined(CONFIG_STM32_TIM1_CAP) || defined(CONFIG_STM32_TIM1_CAP) +#define HAVE_ADANCED_TIM 1 +#endif + +/* This module then only compiles if there are enabled timers that are not intended for + * some other purpose. + */ + +#if defined(CONFIG_STM32_TIM1_CAP) || defined(CONFIG_STM32_TIM2_CAP) || defined(CONFIG_STM32_TIM3_CAP) || \ + defined(CONFIG_STM32_TIM4_CAP) || defined(CONFIG_STM32_TIM5_CAP) || defined(CONFIG_STM32_TIM8_CAP) || \ + defined(CONFIG_STM32_TIM9_CAP) || defined(CONFIG_STM32_TIM10_CAP) || defined(CONFIG_STM32_TIM11_CAP) || \ + defined(CONFIG_STM32_TIM12_CAP) || defined(CONFIG_STM32_TIM13_CAP) || defined(CONFIG_STM32_TIM14_CAP) + +/************************************************************************************ + * Private Types + ************************************************************************************/ + +struct stm32_cap_channel_s +{ + uint8_t ch_id; + uint16_t ccmr; + uint32_t gpio; +} + +/* TIM Device Structure */ + +struct stm32_cap_priv_s +{ + const struct stm32_cap_ops_s *ops; + const uint32_t base; /* TIMn base address */ + const int irq; /* irq vector */ +#define HAVE_ADANCED_TIM 1 + const int irq_of; /* irq timer overflow is deferent in advanced timer */ +#endif + const stm32_cap_channel_s channels[CAP_NCHANNELS]; +}; + +/************************************************************************************ + * Private Functions + ************************************************************************************/ + +/* Get a 16-bit register value by offset */ + +static inline uint16_t stm32_getreg16(FAR struct stm32_cap_priv_s *priv, + uint8_t offset) +{ + return getreg16(priv->base + offset); +} + +/* Put a 16-bit register value by offset */ + +static inline void stm32_putreg16(FAR struct stm32_cap_priv_s *priv, uint8_t offset, + uint16_t value) +{ + putreg16(value, priv->base + offset); +} + +/* Modify a 16-bit register value by offset */ + +static inline void stm32_modifyreg16(FAR struct stm32_cap_priv_s *priv, + uint8_t offset, uint16_t clearbits, + uint16_t setbits) +{ + modifyreg16(priv->base + offset, clearbits, setbits); +} + +/* Get a 32-bit register value by offset. This applies only for the STM32 F4 + * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. + */ + +static inline uint32_t stm32_getreg32(FAR struct stm32_cap_priv_s *priv, + uint8_t offset) +{ + return getreg32(priv->base + offset); +} + +/* Put a 32-bit register value by offset. This applies only for the STM32 F4 + * 32-bit registers (CNT, ARR, CRR1-4) in the 32-bit timers TIM2-5. + */ + +static inline void stm32_putreg32(FAR struct stm32_cap_priv_s *priv, uint8_t offset, + uint32_t value) +{ + putreg32(value, priv->base + offset); +} + +/************************************************************************************ + * Basic Functions + ************************************************************************************/ + +static int stm32_cap_setclock(FAR struct stm32_cap_dev_s *dev, stm32_cap_clk_src_t clk_src, + uint32_t prescaler) +{ + struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev; + uint16_t regval = 0; + + if (prescaler == 0) + { + //disable Timer + stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET,ATIM_CR1_CEN,0); + return 0; + } + + /* We need to decrement value for '1', but only, if we are allowed to + * not to cause underflow. Check for overflow. + */ + + if (prescaler > 0) + prescaler--; + + if (prescaler > 0xffff) + prescaler = 0xffff; + + + switch(clk_src) + { + case STM32_CAP_CLK_INT: + regval = GTIM_SMCR_DISAB; + break; + + case STM32_CAP_CLK_EXT: + regval = GTIM_SMCR_EXTCLK1 + break; + + /* TODO: Add other case */ + + default: + return ERROR; + } + + stm32_modifyreg16(priv, STM32_BTIM_EGR_OFFSET, GTIM_SMCR_SMS_MASK, regval ); + + // Set Maximum + stm32_putreg32(priv, STM32_BTIM_ARR_OFFSET, period); + + // Set prescaler + stm32_putreg16(priv, STM32_BTIM_PSC_OFFSET, prescaler); + + //reset counter timer + stm32_modifyreg16(priv, STM32_BTIM_EGR_OFFSET,0,BTIM_EGR_UG); + + //enable timer + stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET,0,BTIM_CR1_CEN); + +#ifdef HAVE_ADANCED_TIM + /* Advanced registers require Main Output Enable */ + if ((priv->base == STM32_TIM1_BASE) || (priv->base == STM32_TIM8_BASE)) + { + stm32_modifyreg16(priv, STM32_ATIM_BDTR_OFFSET, 0, ATIM_BDTR_MOE); + } +#endif + + return prescaler; +} + +static int stm32_cap_setisr(FAR struct stm32_cap_dev_s *dev, xcpt_t handler); +{ + struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev; + int irq; +#ifdef HAVE_ADANCED_TIM + int irq_of; +#endif + + ASSERT(dev); + + irq = priv->irq; +#ifdef HAVE_ADANCED_TIM + irq_of = priv->irq_of; +#endif + + /* Disable interrupt when callback is removed */ + + if (!handler) + { + up_disable_irq(irq); + irq_detach(irq); +#ifdef HAVE_ADANCED_TIM + if (priv->irq_of) + { + up_disable_irq(irq_of); + irq_detach(irq_of); + } +#endif + return OK; + } + + /* Otherwise set callback and enable interrupt */ + + irq_attach(irq, handler); + up_enable_irq(irq); + +#ifdef HAVE_ADANCED_TIM + if (priv->irq_of) + { + irq_attach(priv->irq_of, handler); + up_enable_irq(priv->irq_of); + } +#endif + +#ifdef CONFIG_ARCH_IRQPRIO + /* Set the interrupt priority */ + + up_prioritize_irq(irq, NVIC_SYSH_PRIORITY_DEFAULT); + +# ifdef HAVE_ADANCED_TIM + if (priv->irq_of) + { + up_prioritize_irq(irq_of, NVIC_SYSH_PRIORITY_DEFAULT); + } +# endif + +#endif + + return OK; +} + + +static void stm32_cap_enableint(FAR struct stm32_cap_dev_s *dev, + stm32_cap_flags_t src, bool on) +{ + struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev; + uint16_t mask; + ASSERT(dev); + + if (src & STM32_TIM_FLAG_IRQ_OVERFLOW) + regval |= ATIM_DIER_UIE; + if (src & STM32_TIM_FLAG_IRQ_CAPTURE_1) + regval |= ATIM_DIER_CC1IE; + if (src & STM32_TIM_FLAG_IRQ_CAPTURE_2) + regval |= ATIM_DIER_CC1IE; + if (src & STM32_TIM_FLAG_IRQ_CAPTURE_3) + regval |= ATIM_DIER_CC1IE; + if (src & STM32_TIM_FLAG_IRQ_CAPTURE_4) + regval |= ATIM_DIER_CC1IE; + + /* Not IRQ on channel overflow */ + + if (on) + stm32_modifyreg16(priv, STM32_BTIM_DIER_OFFSET,0,mask); + else + stm32_modifyreg16(priv, STM32_BTIM_DIER_OFFSET,mask,0); + +} + +static void stm32_cap_ackflags(FAR struct stm32_cap_dev_s *dev, int src) +{ + struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev; + uint16_t mask = 0; + + if (src & STM32_TIM_FLAG_IRQ_OVERFLOW) + regval |= ATIM_SR_UIF; + + if (src & STM32_TIM_FLAG_IRQ_CAPTURE_1) + regval |= ATIM_SR_CC1IF; + if (src & STM32_TIM_FLAG_IRQ_CAPTURE_2) + regval |= ATIM_SR_CC2IF; + if (src & STM32_TIM_FLAG_IRQ_CAPTURE_3) + regval |= ATIM_SR_CC3IF; + if (src & STM32_TIM_FLAG_IRQ_CAPTURE_4) + regval |= ATIM_SR_CC4IF; + + if (src & STM32_TIM_FLAG_OF_CAPTURE_1) + regval |= ATIM_SR_CC1OF; + if (src & STM32_TIM_FLAG_OF_CAPTURE_2) + regval |= ATIM_SR_CC2OF; + if (src & STM32_TIM_FLAG_OF_CAPTURE_3) + regval |= ATIM_SR_CC3OF; + if (src & STM32_TIM_FLAG_OF_CAPTURE_4) + regval |= ATIM_SR_CC4OF; + + stm32_putreg16(priv, STM32_BTIM_SR_OFFSET, ~mask); + +} + +static stm32_cap_flags_t stm32_cap_getint(FAR struct stm32_cap_dev_s *dev) +{ + struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev; + uint16_t regval = 0; + stm32_cap_flags_t src = 0; + + regval = stm32_getreg16(priv, STM32_BTIM_SR_OFFSET); + + if (regval & ATIM_SR_UIF) + src |= STM32_TIM_FLAG_IRQ_OVERFLOW; + + if (regval & ATIM_SR_CC1IF) + src |= STM32_TIM_FLAG_IRQ_CAPTURE_1; + if (regval & ATIM_SR_CC2IF) + src |= STM32_TIM_FLAG_IRQ_CAPTURE_2; + if (regval & ATIM_SR_CC3IF) + src |= STM32_TIM_FLAG_IRQ_CAPTURE_3; + if (regval & ATIM_SR_CC4IF) + src |= STM32_TIM_FLAG_IRQ_CAPTURE_4; + + if (regval & ATIM_SR_CC1OF) + src |= STM32_TIM_FLAG_OF_CAPTURE_1; + if (regval & ATIM_SR_CC2OF) + src |= STM32_TIM_FLAG_OF_CAPTURE_2; + if (regval & ATIM_SR_CC3OF) + src |= STM32_TIM_FLAG_OF_CAPTURE_3; + if (regval & ATIM_SR_CC4OF) + src |= STM32_TIM_FLAG_OF_CAPTURE_4; + + return src; + +} + +/************************************************************************************ + * General Functions + ************************************************************************************/ + +static int stm32_cap_setchannel(FAR struct stm32_cap_dev_s *dev, uint8_t channel, + stm32_cap_ch_cfg_t edge) +{ + int i; + struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev; + uint32_t gpio = 0; + uint16_t mask; + uint16_t regval; + + ASSERT(dev); + + i = CAP_NCHANNELS; + while(i--) + { + if ( priv->channels[i].ch_id == channel ) + { + gpio = priv->channels[i].gpio; + break; + } + } + + if ( gpio == 0 ) + return ERROR; + + /* change to zero base index */ + channel--; + + + /* Set ccer */ + switch (cfg & STM32_CAP_EDGE_MASK) + { + case STM32_CAP_EDGE_DISABLED: + regval = 0; + break; + case STM32_CAP_EDGE_RISING: + regval = GTIM_CCER_CC1E; + break; + case STM32_CAP_EDGE_FALLING: + regval = GTIM_CCER_CC1E | GTIM_CCER_CC1P; + break; + case STM32_CAP_EDGE_BOTH: + regval = GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP; + break; + default: + return ERROR; + } + + mask = (GTIM_CCER_CC1E | GTIM_CCER_CC1P | GTIM_CCER_CC1NP) + mask <<= (channel << 2); + regval <<= (channel << 2); + stm32_modifyreg16(priv,mask,regval); + + /* Set ccmr */ + + ccmr_val = cfg; + + if ( (ccmr_val & GTIM_CCMR1_CC1S_MASK ) == 0 ) + return ERROR; /* configured as output */ + + if ( (ccmr_val & GTIM_CCMR1_CC1S_MASK ) == 3 ) + return ERROR; /* Not implemented */ + + /* Define its position (shift) and get register offset */ + + mask = (GTIM_CCMR1_IC1F_MASK | GTIM_CCMR1_IC1PSC_MASK | GTIM_CCMR1_CC1S_MASK) + ccmr_val &= mask + + if (channel & 1) + { + ccmr_val <<= 8; + ccmr_mask <<= 8; + } + + if (channel < 2) + stm32_modifyreg16(priv,STM32_GTIM_CCMR1_OFFSET,ccmr_mask,ccmr_val); + else + stm32_modifyreg16(priv,STM32_GTIM_CCMR2_OFFSET,ccmr_mask,ccmr_val); + + /* set GPIO */ + + if ( (cfg & STM32_CAP_EDGE_MASK) == STM32_CAP_EDGE_DISABLED) + stm32_unconfiggpio(gpio); + else + stm32_configgpio(gpio); + + return OK; +} + + +static int stm32_cap_getcapture(FAR struct stm32_cap_dev_s *dev, uint8_t channel) +{ + struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev; + ASSERT(dev); + + switch (channel) + { +#ifdef HAVE_CH1IN + case 1: + return stm32_getreg32(dev, STM32_GTIM_CCR1_OFFSET); +#endif +#ifdef HAVE_CH1IN + case 2: + return stm32_getreg32(dev, STM32_GTIM_CCR2_OFFSET); +#endif +#ifdef HAVE_CH1IN + case 3: + return stm32_getreg32(dev, STM32_GTIM_CCR3_OFFSET); +#endif +#ifdef HAVE_CH1IN + case 4: + return stm32_getreg32(dev, STM32_GTIM_CCR4_OFFSET); +#endif + } + + return ERROR; +} + + +/************************************************************************************ + * Advanced Functions + ************************************************************************************/ + +/* TODO: Advanced functions for the STM32_ATIM */ + +/************************************************************************************ + * Device Structures, Instantiation + ************************************************************************************/ + +struct stm32_cap_ops_s stm32_cap_ops = +{ + .setclock = &stm32_cap_setclock, + .setchannel = &stm32_cap_setchannel, + .getcapture = &stm32_cap_getcapture, + .setisr = &stm32_cap_setisr, + .enableint = &stm32_cap_enableint, + .ackflags = &stm32_cap_ackflags, + .getflags = &stm32_cap_getflags +}; + +#ifdef CONFIG_STM32_TIM2_CAP +const struct stm32_cap_priv_s stm32_tim2_priv = +{ + .ops = &stm32_cap_ops, + .base = STM32_TIM2_BASE, + .irg = STM32_IRQ_TIM2, +#define HAVE_ADANCED_TIM 1 + .irg_of = -1, +#endif + .gpio_clk = GPIO_TIM2_CLKIN; + .channels = { +#if defined(GPIO_TIM2_CH1IN) + .gpio = GPIO_TIM2_CH1IN; +#endif +#if defined(GPIO_TIM2_CH2IN) + .gpio = GPIO_TIM2_CH2IN; + .ccmr = ( GPIO_TIM2_CH2_ICF << ATIM_CCMR1_IC1F_SHIFT )|\ + ( GPIO_TIM2_CH2_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT ); +#endif +#if defined(GPIO_TIM2_CH3IN) + .gpio = GPIO_TIM2_CH3IN; + .ccmr = ( GPIO_TIM2_CH3_ICF << ATIM_CCMR1_IC1F_SHIFT )|\ + ( GPIO_TIM2_CH3_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT ); +#endif +#if defined(GPIO_TIM2_CH4IN) + .gpio = GPIO_TIM2_CH4IN; + .ccmr = ( GPIO_TIM2_CH4_ICF << ATIM_CCMR1_IC1F_SHIFT )|\ + ( GPIO_TIM2_CH4_ICPSC << ATIM_CCMR1_IC1PSC_SHIFT ); +#endif + } +}; +#endif + + +/************************************************************************************ + * Public Function - Initialization + ************************************************************************************/ + +FAR struct stm32_cap_dev_s *stm32_cap_init(int timer) +{ + struct stm32_cap_priv_s *priv = NULL; + + /* Get structure and enable power */ + + switch (timer) + { +#ifdef CONFIG_STM32_TIM1_CAP + case 1: + priv = &stm32_tim1_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM1EN); + break; +#endif +#ifdef CONFIG_STM32_TIM2_CAP + case 2: + priv = &stm32_tim2_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM2EN); + break; +#endif +#ifdef CONFIG_STM32_TIM3_CAP + case 3: + priv = &stm32_tim3_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM3EN); + break; +#endif +#ifdef CONFIG_STM32_TIM4_CAP + case 4: + priv = &stm32_tim4_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM4EN); + break; +#endif +#ifdef CONFIG_STM32_TIM5_CAP + case 5: + priv = &stm32_tim5_priv; + modifyreg32(STM32_RCC_APB1ENR, 0, RCC_APB1ENR_TIM5EN); + break; +#endif +/* TIM6 and TIM7 cannot be used in capture */ +#ifdef CONFIG_STM32_TIM8_CAP + case 8: + priv = &stm32_tim8_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + break; +#endif +#ifdef CONFIG_STM32_TIM9_CAP + case 9: + priv = &stm32_tim9_priv; + modifyreg32(STM32_RCC_APB2ENR, 0, RCC_APB2ENR_TIM8EN); + break; +#endif + default: + return NULL; + } + + if (priv->gpio_clk) + stm32_configgpio(priv->gpio_clk) + + // disable timer while is not configured + stm32_modifyreg16(priv, STM32_BTIM_CR1_OFFSET, ATIM_CR1_CEN, 0); + + return (struct stm32_cap_dev_s *)priv; +} + + +int stm32_cap_deinit(FAR struct stm32_cap_dev_s * dev) +{ + struct stm32_cap_priv_s *priv = (struct stm32_cap_priv_s *)dev; + ASSERT(dev); + + // disable timer while is not configured + stm32_modifyreg16(dev, STM32_BTIM_CR1_OFFSET, ATIM_CR1_CEN, 0); + + if (priv->gpio_clk) + stm32_unconfiggpio(priv->gpio_clk) + + switch (priv->base) + { +#ifdef CONFIG_STM32_TIM2_CAP + case STM32_TIM2_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM2EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM3_CAP + case STM32_TIM3_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM3EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM4_CAP + case STM32_TIM4_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM4EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM5_CAP + case STM32_TIM5_BASE: + modifyreg32(STM32_RCC_APB1ENR, RCC_APB1ENR_TIM5EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM1_CAP + case STM32_TIM1_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM1EN, 0); + break; +#endif +#ifdef CONFIG_STM32_TIM8_CAP + case STM32_TIM8_BASE: + modifyreg32(STM32_RCC_APB2ENR, RCC_APB2ENR_TIM8EN, 0); + break; +#endif + default: + return ERROR; + } + + return OK; +} + +#endif /* defined(CONFIG_STM32_TIM1 || ... || TIM8) */ diff --git a/arch/arm/src/stm32/stm32_capture.h b/arch/arm/src/stm32/stm32_capture.h new file mode 100644 index 00000000000..e3eb1f388ec --- /dev/null +++ b/arch/arm/src/stm32/stm32_capture.h @@ -0,0 +1,779 @@ +/************************************************************************************ + * arch/arm/src/stm32/stm32_capture.h + * + * Copyright (C) 2015 Bouteville Pierre-Noel. All rights reserved. + * Author: Bouteville Pierre-Noel + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_STM32_STM32_CAPTURE_H +#define __ARCH_ARM_SRC_STM32_STM32_CAPTURE_H + +/************************************************************************************ + * Included Files + ************************************************************************************/ + +#include + + +#include "chip.h" +#include +#include "chip/stm32_tim.h" + + +#ifdef CONFIG_STM32_TIM1_CHANNEL1 +# ifdef CONFIG_STM32_TIM1_CH1OUT +# define CAP_TIM1_CH1CFG GPIO_TIM1_CH1OUT +# else +# define CAP_TIM1_CH1CFG 0 +# endif +# define CAP_TIM1_CHANNEL1 1 +#else +# define CAP_TIM1_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL2 +# ifdef CONFIG_STM32_TIM1_CH2OUT +# define CAP_TIM1_CH2CFG GPIO_TIM1_CH2OUT +# else +# define CAP_TIM1_CH2CFG 0 +# endif +# define CAP_TIM1_CHANNEL2 1 +#else +# define CAP_TIM1_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL3 +# ifdef CONFIG_STM32_TIM1_CH3OUT +# define CAP_TIM1_CH3CFG GPIO_TIM1_CH3OUT +# else +# define CAP_TIM1_CH3CFG 0 +# endif +# define CAP_TIM1_CHANNEL3 1 +#else +# define CAP_TIM1_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM1_CHANNEL4 +# ifdef CONFIG_STM32_TIM1_CH4OUT +# define CAP_TIM1_CH4CFG GPIO_TIM1_CH4OUT +# else +# define CAP_TIM1_CH4CFG 0 +# endif +# define CAP_TIM1_CHANNEL4 1 +#else +# define CAP_TIM1_CHANNEL4 0 +#endif +#define CAP_TIM1_NCHANNELS (CAP_TIM1_CHANNEL1 + CAP_TIM1_CHANNEL2 + \ + CAP_TIM1_CHANNEL3 + CAP_TIM1_CHANNEL4) + +#ifdef CONFIG_STM32_TIM2_CHANNEL1 +# ifdef CONFIG_STM32_TIM2_CH1OUT +# define CAP_TIM2_CH1CFG GPIO_TIM2_CH1OUT +# else +# define CAP_TIM2_CH1CFG 0 +# endif +# define CAP_TIM2_CHANNEL1 1 +#else +# define CAP_TIM2_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL2 +# ifdef CONFIG_STM32_TIM2_CH2OUT +# define CAP_TIM2_CH2CFG GPIO_TIM2_CH2OUT +# else +# define CAP_TIM2_CH2CFG 0 +# endif +# define CAP_TIM2_CHANNEL2 1 +#else +# define CAP_TIM2_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL3 +# ifdef CONFIG_STM32_TIM2_CH3OUT +# define CAP_TIM2_CH3CFG GPIO_TIM2_CH3OUT +# else +# define CAP_TIM2_CH3CFG 0 +# endif +# define CAP_TIM2_CHANNEL3 1 +#else +# define CAP_TIM2_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM2_CHANNEL4 +# ifdef CONFIG_STM32_TIM2_CH4OUT +# define CAP_TIM2_CH4CFG GPIO_TIM2_CH4OUT +# else +# define CAP_TIM2_CH4CFG 0 +# endif +# define CAP_TIM2_CHANNEL4 1 +#else +# define CAP_TIM2_CHANNEL4 0 +#endif +#define CAP_TIM2_NCHANNELS (CAP_TIM2_CHANNEL1 + CAP_TIM2_CHANNEL2 + \ + CAP_TIM2_CHANNEL3 + CAP_TIM2_CHANNEL4) + +#ifdef CONFIG_STM32_TIM3_CHANNEL1 +# ifdef CONFIG_STM32_TIM3_CH1OUT +# define CAP_TIM3_CH1CFG GPIO_TIM3_CH1OUT +# else +# define CAP_TIM3_CH1CFG 0 +# endif +# define CAP_TIM3_CHANNEL1 1 +#else +# define CAP_TIM3_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL2 +# ifdef CONFIG_STM32_TIM3_CH2OUT +# define CAP_TIM3_CH2CFG GPIO_TIM3_CH2OUT +# else +# define CAP_TIM3_CH2CFG 0 +# endif +# define CAP_TIM3_CHANNEL2 1 +#else +# define CAP_TIM3_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL3 +# ifdef CONFIG_STM32_TIM3_CH3OUT +# define CAP_TIM3_CH3CFG GPIO_TIM3_CH3OUT +# else +# define CAP_TIM3_CH3CFG 0 +# endif +# define CAP_TIM3_CHANNEL3 1 +#else +# define CAP_TIM3_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM3_CHANNEL4 +# ifdef CONFIG_STM32_TIM3_CH4OUT +# define CAP_TIM3_CH4CFG GPIO_TIM3_CH4OUT +# else +# define CAP_TIM3_CH4CFG 0 +# endif +# define CAP_TIM3_CHANNEL4 1 +#else +# define CAP_TIM3_CHANNEL4 0 +#endif +#define CAP_TIM3_NCHANNELS (CAP_TIM3_CHANNEL1 + CAP_TIM3_CHANNEL2 + \ + CAP_TIM3_CHANNEL3 + CAP_TIM3_CHANNEL4) + +#ifdef CONFIG_STM32_TIM4_CHANNEL1 +# ifdef CONFIG_STM32_TIM4_CH1OUT +# define CAP_TIM4_CH1CFG GPIO_TIM4_CH1OUT +# else +# define CAP_TIM4_CH1CFG 0 +# endif +# define CAP_TIM4_CHANNEL1 1 +#else +# define CAP_TIM4_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM4_CHANNEL2 +# ifdef CONFIG_STM32_TIM4_CH2OUT +# define CAP_TIM4_CH2CFG GPIO_TIM4_CH2OUT +# else +# define CAP_TIM4_CH2CFG 0 +# endif +# define CAP_TIM4_CHANNEL2 1 +#else +# define CAP_TIM4_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM4_CHANNEL3 +# ifdef CONFIG_STM32_TIM4_CH3OUT +# define CAP_TIM4_CH3CFG GPIO_TIM4_CH3OUT +# else +# define CAP_TIM4_CH3CFG 0 +# endif +# define CAP_TIM4_CHANNEL3 1 +#else +# define CAP_TIM4_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM4_CHANNEL4 +# ifdef CONFIG_STM32_TIM4_CH4OUT +# define CAP_TIM4_CH4CFG GPIO_TIM4_CH4OUT +# else +# define CAP_TIM4_CH4CFG 0 +# endif +# define CAP_TIM4_CHANNEL4 1 +#else +# define CAP_TIM4_CHANNEL4 0 +#endif +#define CAP_TIM4_NCHANNELS (CAP_TIM4_CHANNEL1 + CAP_TIM4_CHANNEL2 + \ + CAP_TIM4_CHANNEL3 + CAP_TIM4_CHANNEL4) + +#ifdef CONFIG_STM32_TIM5_CHANNEL1 +# ifdef CONFIG_STM32_TIM5_CH1OUT +# define CAP_TIM5_CH1CFG GPIO_TIM5_CH1OUT +# else +# define CAP_TIM5_CH1CFG 0 +# endif +# define CAP_TIM5_CHANNEL1 1 +#else +# define CAP_TIM5_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM5_CHANNEL2 +# ifdef CONFIG_STM32_TIM5_CH2OUT +# define CAP_TIM5_CH2CFG GPIO_TIM5_CH2OUT +# else +# define CAP_TIM5_CH2CFG 0 +# endif +# define CAP_TIM5_CHANNEL2 1 +#else +# define CAP_TIM5_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM5_CHANNEL3 +# ifdef CONFIG_STM32_TIM5_CH3OUT +# define CAP_TIM5_CH3CFG GPIO_TIM5_CH3OUT +# else +# define CAP_TIM5_CH3CFG 0 +# endif +# define CAP_TIM5_CHANNEL3 1 +#else +# define CAP_TIM5_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM5_CHANNEL4 +# ifdef CONFIG_STM32_TIM5_CH4OUT +# define CAP_TIM5_CH4CFG GPIO_TIM5_CH4OUT +# else +# define CAP_TIM5_CH4CFG 0 +# endif +# define CAP_TIM5_CHANNEL4 1 +#else +# define CAP_TIM5_CHANNEL4 0 +#endif +#define CAP_TIM5_NCHANNELS (CAP_TIM5_CHANNEL1 + CAP_TIM5_CHANNEL2 + \ + CAP_TIM5_CHANNEL3 + CAP_TIM5_CHANNEL4) + +#ifdef CONFIG_STM32_TIM8_CHANNEL1 +# ifdef CONFIG_STM32_TIM8_CH1OUT +# define CAP_TIM8_CH1CFG GPIO_TIM8_CH1OUT +# else +# define CAP_TIM8_CH1CFG 0 +# endif +# define CAP_TIM8_CHANNEL1 1 +#else +# define CAP_TIM8_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL2 +# ifdef CONFIG_STM32_TIM8_CH2OUT +# define CAP_TIM8_CH2CFG GPIO_TIM8_CH2OUT +# else +# define CAP_TIM8_CH2CFG 0 +# endif +# define CAP_TIM8_CHANNEL2 1 +#else +# define CAP_TIM8_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL3 +# ifdef CONFIG_STM32_TIM8_CH3OUT +# define CAP_TIM8_CH3CFG GPIO_TIM8_CH3OUT +# else +# define CAP_TIM8_CH3CFG 0 +# endif +# define CAP_TIM8_CHANNEL3 1 +#else +# define CAP_TIM8_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM8_CHANNEL4 +# ifdef CONFIG_STM32_TIM8_CH4OUT +# define CAP_TIM8_CH4CFG GPIO_TIM8_CH4OUT +# else +# define CAP_TIM8_CH4CFG 0 +# endif +# define CAP_TIM8_CHANNEL4 1 +#else +# define CAP_TIM8_CHANNEL4 0 +#endif +#define CAP_TIM8_NCHANNELS (CAP_TIM8_CHANNEL1 + CAP_TIM8_CHANNEL2 + \ + CAP_TIM8_CHANNEL3 + CAP_TIM8_CHANNEL4) + +#ifdef CONFIG_STM32_TIM9_CHANNEL1 +# ifdef CONFIG_STM32_TIM9_CH1OUT +# define CAP_TIM9_CH1CFG GPIO_TIM9_CH1OUT +# else +# define CAP_TIM9_CH1CFG 0 +# endif +# define CAP_TIM9_CHANNEL1 1 +#else +# define CAP_TIM9_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM9_CHANNEL2 +# ifdef CONFIG_STM32_TIM9_CH2OUT +# define CAP_TIM9_CH2CFG GPIO_TIM9_CH2OUT +# else +# define CAP_TIM9_CH2CFG 0 +# endif +# define CAP_TIM9_CHANNEL2 1 +#else +# define CAP_TIM9_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM9_CHANNEL3 +# ifdef CONFIG_STM32_TIM9_CH3OUT +# define CAP_TIM9_CH3CFG GPIO_TIM9_CH3OUT +# else +# define CAP_TIM9_CH3CFG 0 +# endif +# define CAP_TIM9_CHANNEL3 1 +#else +# define CAP_TIM9_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM9_CHANNEL4 +# ifdef CONFIG_STM32_TIM9_CH4OUT +# define CAP_TIM9_CH4CFG GPIO_TIM9_CH4OUT +# else +# define CAP_TIM9_CH4CFG 0 +# endif +# define CAP_TIM9_CHANNEL4 1 +#else +# define CAP_TIM9_CHANNEL4 0 +#endif +#define CAP_TIM9_NCHANNELS (CAP_TIM9_CHANNEL1 + CAP_TIM9_CHANNEL2 + \ + CAP_TIM9_CHANNEL3 + CAP_TIM9_CHANNEL4) + +#ifdef CONFIG_STM32_TIM10_CHANNEL1 +# ifdef CONFIG_STM32_TIM10_CH1OUT +# define CAP_TIM10_CH1CFG GPIO_TIM10_CH1OUT +# else +# define CAP_TIM10_CH1CFG 0 +# endif +# define CAP_TIM10_CHANNEL1 1 +#else +# define CAP_TIM10_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM10_CHANNEL2 +# ifdef CONFIG_STM32_TIM10_CH2OUT +# define CAP_TIM10_CH2CFG GPIO_TIM10_CH2OUT +# else +# define CAP_TIM10_CH2CFG 0 +# endif +# define CAP_TIM10_CHANNEL2 1 +#else +# define CAP_TIM10_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM10_CHANNEL3 +# ifdef CONFIG_STM32_TIM10_CH3OUT +# define CAP_TIM10_CH3CFG GPIO_TIM10_CH3OUT +# else +# define CAP_TIM10_CH3CFG 0 +# endif +# define CAP_TIM10_CHANNEL3 1 +#else +# define CAP_TIM10_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM10_CHANNEL4 +# ifdef CONFIG_STM32_TIM10_CH4OUT +# define CAP_TIM10_CH4CFG GPIO_TIM10_CH4OUT +# else +# define CAP_TIM10_CH4CFG 0 +# endif +# define CAP_TIM10_CHANNEL4 1 +#else +# define CAP_TIM10_CHANNEL4 0 +#endif +#define CAP_TIM10_NCHANNELS (CAP_TIM10_CHANNEL1 + CAP_TIM10_CHANNEL2 + \ + CAP_TIM10_CHANNEL3 + CAP_TIM10_CHANNEL4) + +#ifdef CONFIG_STM32_TIM11_CHANNEL1 +# ifdef CONFIG_STM32_TIM11_CH1OUT +# define CAP_TIM11_CH1CFG GPIO_TIM11_CH1OUT +# else +# define CAP_TIM11_CH1CFG 0 +# endif +# define CAP_TIM11_CHANNEL1 1 +#else +# define CAP_TIM11_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM11_CHANNEL2 +# ifdef CONFIG_STM32_TIM11_CH2OUT +# define CAP_TIM11_CH2CFG GPIO_TIM11_CH2OUT +# else +# define CAP_TIM11_CH2CFG 0 +# endif +# define CAP_TIM11_CHANNEL2 1 +#else +# define CAP_TIM11_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM11_CHANNEL3 +# ifdef CONFIG_STM32_TIM11_CH3OUT +# define CAP_TIM11_CH3CFG GPIO_TIM11_CH3OUT +# else +# define CAP_TIM11_CH3CFG 0 +# endif +# define CAP_TIM11_CHANNEL3 1 +#else +# define CAP_TIM11_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM11_CHANNEL4 +# ifdef CONFIG_STM32_TIM11_CH4OUT +# define CAP_TIM11_CH4CFG GPIO_TIM11_CH4OUT +# else +# define CAP_TIM11_CH4CFG 0 +# endif +# define CAP_TIM11_CHANNEL4 1 +#else +# define CAP_TIM11_CHANNEL4 0 +#endif +#define CAP_TIM11_NCHANNELS (CAP_TIM11_CHANNEL1 + CAP_TIM11_CHANNEL2 + \ + CAP_TIM11_CHANNEL3 + CAP_TIM11_CHANNEL4) + +#ifdef CONFIG_STM32_TIM12_CHANNEL1 +# ifdef CONFIG_STM32_TIM12_CH1OUT +# define CAP_TIM12_CH1CFG GPIO_TIM12_CH1OUT +# else +# define CAP_TIM12_CH1CFG 0 +# endif +# define CAP_TIM12_CHANNEL1 1 +#else +# define CAP_TIM12_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM12_CHANNEL2 +# ifdef CONFIG_STM32_TIM12_CH2OUT +# define CAP_TIM12_CH2CFG GPIO_TIM12_CH2OUT +# else +# define CAP_TIM12_CH2CFG 0 +# endif +# define CAP_TIM12_CHANNEL2 1 +#else +# define CAP_TIM12_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM12_CHANNEL3 +# ifdef CONFIG_STM32_TIM12_CH3OUT +# define CAP_TIM12_CH3CFG GPIO_TIM12_CH3OUT +# else +# define CAP_TIM12_CH3CFG 0 +# endif +# define CAP_TIM12_CHANNEL3 1 +#else +# define CAP_TIM12_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM12_CHANNEL4 +# ifdef CONFIG_STM32_TIM12_CH4OUT +# define CAP_TIM12_CH4CFG GPIO_TIM12_CH4OUT +# else +# define CAP_TIM12_CH4CFG 0 +# endif +# define CAP_TIM12_CHANNEL4 1 +#else +# define CAP_TIM12_CHANNEL4 0 +#endif +#define CAP_TIM12_NCHANNELS (CAP_TIM12_CHANNEL1 + CAP_TIM12_CHANNEL2 + \ + CAP_TIM12_CHANNEL3 + CAP_TIM12_CHANNEL4) + +#ifdef CONFIG_STM32_TIM13_CHANNEL1 +# ifdef CONFIG_STM32_TIM13_CH1OUT +# define CAP_TIM13_CH1CFG GPIO_TIM13_CH1OUT +# else +# define CAP_TIM13_CH1CFG 0 +# endif +# define CAP_TIM13_CHANNEL1 1 +#else +# define CAP_TIM13_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM13_CHANNEL2 +# ifdef CONFIG_STM32_TIM13_CH2OUT +# define CAP_TIM13_CH2CFG GPIO_TIM13_CH2OUT +# else +# define CAP_TIM13_CH2CFG 0 +# endif +# define CAP_TIM13_CHANNEL2 1 +#else +# define CAP_TIM13_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM13_CHANNEL3 +# ifdef CONFIG_STM32_TIM13_CH3OUT +# define CAP_TIM13_CH3CFG GPIO_TIM13_CH3OUT +# else +# define CAP_TIM13_CH3CFG 0 +# endif +# define CAP_TIM13_CHANNEL3 1 +#else +# define CAP_TIM13_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM13_CHANNEL4 +# ifdef CONFIG_STM32_TIM13_CH4OUT +# define CAP_TIM13_CH4CFG GPIO_TIM13_CH4OUT +# else +# define CAP_TIM13_CH4CFG 0 +# endif +# define CAP_TIM13_CHANNEL4 1 +#else +# define CAP_TIM13_CHANNEL4 0 +#endif +#define CAP_TIM13_NCHANNELS (CAP_TIM13_CHANNEL1 + CAP_TIM13_CHANNEL2 + \ + CAP_TIM13_CHANNEL3 + CAP_TIM13_CHANNEL4) + +#ifdef CONFIG_STM32_TIM14_CHANNEL1 +# ifdef CONFIG_STM32_TIM14_CH1OUT +# define CAP_TIM14_CH1CFG GPIO_TIM14_CH1OUT +# else +# define CAP_TIM14_CH1CFG 0 +# endif +# define CAP_TIM14_CHANNEL1 1 +#else +# define CAP_TIM14_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM14_CHANNEL2 +# ifdef CONFIG_STM32_TIM14_CH2OUT +# define CAP_TIM14_CH2CFG GPIO_TIM14_CH2OUT +# else +# define CAP_TIM14_CH2CFG 0 +# endif +# define CAP_TIM14_CHANNEL2 1 +#else +# define CAP_TIM14_CHANNEL2 0 +#endif +#ifdef CONFIG_STM32_TIM14_CHANNEL3 +# ifdef CONFIG_STM32_TIM14_CH3OUT +# define CAP_TIM14_CH3CFG GPIO_TIM14_CH3OUT +# else +# define CAP_TIM14_CH3CFG 0 +# endif +# define CAP_TIM14_CHANNEL3 1 +#else +# define CAP_TIM14_CHANNEL3 0 +#endif +#ifdef CONFIG_STM32_TIM14_CHANNEL4 +# ifdef CONFIG_STM32_TIM14_CH4OUT +# define CAP_TIM14_CH4CFG GPIO_TIM14_CH4OUT +# else +# define CAP_TIM14_CH4CFG 0 +# endif +# define CAP_TIM14_CHANNEL4 1 +#else +# define CAP_TIM14_CHANNEL4 0 +#endif +#define CAP_TIM14_NCHANNELS (CAP_TIM14_CHANNEL1 + CAP_TIM14_CHANNEL2 + \ + CAP_TIM14_CHANNEL3 + CAP_TIM14_CHANNEL4) + +#ifdef CONFIG_STM32_TIM15_CHANNEL1 +# ifdef CONFIG_STM32_TIM15_CH1OUT +# define CAP_TIM15_CH1CFG GPIO_TIM15_CH1OUT +# else +# define CAP_TIM15_CH1CFG 0 +# endif +# define CAP_TIM15_CHANNEL1 1 +#else +# define CAP_TIM15_CHANNEL1 0 +#endif +#ifdef CONFIG_STM32_TIM15_CHANNEL2 +# ifdef CONFIG_STM32_TIM15_CH2OUT +# define CAP_TIM15_CH2CFG GPIO_TIM15_CH2OUT +# else +# define CAP_TIM15_CH2CFG 0 +# endif +# define CAP_TIM15_CHANNEL2 1 +#else +# define CAP_TIM15_CHANNEL2 0 +#endif +#define CAP_TIM15_NCHANNELS (CAP_TIM15_CHANNEL1 + CAP_TIM15_CHANNEL2) + +#ifdef CONFIG_STM32_TIM16_CHANNEL1 +# ifdef CONFIG_STM32_TIM16_CH1OUT +# define CAP_TIM16_CH1CFG GPIO_TIM16_CH1OUT +# else +# define CAP_TIM16_CH1CFG 0 +# endif +# define CAP_TIM16_CHANNEL1 1 +#else +# define CAP_TIM16_CHANNEL1 0 +#endif +#define CAP_TIM16_NCHANNELS CAP_TIM16_CHANNEL1 + +#ifdef CONFIG_STM32_TIM17_CHANNEL1 +# ifdef CONFIG_STM32_TIM17_CH1OUT +# define CAP_TIM17_CH1CFG GPIO_TIM17_CH1OUT +# else +# define CAP_TIM17_CH1CFG 0 +# endif +# define CAP_TIM17_CHANNEL1 1 +#else +# define CAP_TIM17_CHANNEL1 0 +#endif +#define CAP_TIM17_NCHANNELS CAP_TIM17_CHANNEL1 + +#define CAP_MAX(a, b) ((a) > (b) ? (a) : (b)) + +#define CAP_NCHANNELS CAP_MAX(CAP_TIM1_NCHANNELS, \ + CAP_MAX(CAP_TIM2_NCHANNELS, \ + CAP_MAX(CAP_TIM3_NCHANNELS, \ + CAP_MAX(CAP_TIM4_NCHANNELS, \ + CAP_MAX(CAP_TIM5_NCHANNELS, \ + CAP_MAX(CAP_TIM8_NCHANNELS, \ + CAP_MAX(CAP_TIM9_NCHANNELS, \ + CAP_MAX(CAP_TIM10_NCHANNELS, \ + CAP_MAX(CAP_TIM11_NCHANNELS, \ + CAP_MAX(CAP_TIM12_NCHANNELS, \ + CAP_MAX(CAP_TIM13_NCHANNELS, \ + CAP_MAX(CAP_TIM14_NCHANNELS, \ + CAP_MAX(CAP_TIM15_NCHANNELS, \ + CAP_MAX(CAP_TIM16_NCHANNELS, \ + CAP_TIM17_NCHANNELS)))))))))))))) + +#endif + +/************************************************************************************ + * Pre-processor Definitions + ************************************************************************************/ +/* Helpers **************************************************************************/ + +#define STM32_TIM_SETCLOCK(d,freq) ((d)->ops->setclock(d,freq)) +#define STM32_TIM_SETCHANNEL(d,ch,mode) ((d)->ops->setchannel(d,ch,mode)) +#define STM32_TIM_GETCAPTURE(d,ch) ((d)->ops->getcapture(d,ch)) +#define STM32_TIM_SETISR(d,hnd,s) ((d)->ops->setisr(d,hnd,s)) +#define STM32_TIM_ENABLEINT(d,s,on) ((d)->ops->enableint(d,s,on)) +#define STM32_TIM_ACKINT(d,s) ((d)->ops->ackint(d,s)) +#define STM32_TIM_GETINT(d) ((d)->ops->getint(d)) + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +#ifndef __ASSEMBLY__ + +#undef EXTERN +#if defined(__cplusplus) +#define EXTERN extern "C" +extern "C" +{ +#else +#define EXTERN extern +#endif + +/* Capture Device Structure */ + +struct stm32_cap_dev_s +{ + struct stm32_cap_ops_s *ops; +}; + +/* Capture input EDGE sources */ + +typedef enum +{ + + /* Mapped */ + STM32_CAP_MAPPED_MASK = (GTIM_CCMR1_CC1S_MASK), + STM32_CAP_MAPPED_TI1 = (1<