Mirrors_Framework/nuttx
1
0
Fork 0
mirror of https://github.com/apache/nuttx.git synced 2026-05-31 05:55:46 +08:00
Code Issues Actions 2 Packages Projects Releases Wiki Activity

arch/risc-v/src: Make code follow pattern of other architectures better. Fix some coding standard issues.

Browse Source
This commit is contained in:
Gregory Nutt
2018-06-06 07:46:50 -06:00
parent a002238898
commit f88a4c6ea8
4 changed files with 103 additions and 93 deletions
Download Patch File Download Diff File Expand all files Collapse all files
arch/risc-v/include/nr5m100/irq.h
-2
View File
@@ -64,8 +64,6 @@
* Public Function Prototypes * Public Function Prototypes
****************************************************************************/ ****************************************************************************/
void up_enable_irq(int irq);
irqstate_t up_irq_save(void); irqstate_t up_irq_save(void);
void up_irq_restore(irqstate_t irqstate); void up_irq_restore(irqstate_t irqstate);
arch/risc-v/src/nr5m100/nr5_timer.c
+2
View File
@@ -48,6 +48,8 @@
#include <errno.h> #include <errno.h>
#include <debug.h> #include <debug.h>
#include <nuttx/arch.h>
#include "chip.h" #include "chip.h"
#include "up_internal.h" #include "up_internal.h"
#include "up_arch.h" #include "up_arch.h"
arch/risc-v/src/nr5m100/nr5_timerisr.c
+1
View File
@@ -47,6 +47,7 @@
#include <stdint.h> #include <stdint.h>
#include <time.h> #include <time.h>
#include <debug.h> #include <debug.h>
#include <nuttx/arch.h> #include <nuttx/arch.h>
#include <arch/board/board.h> #include <arch/board/board.h>
arch/risc-v/src/nr5m100/nr5_uart.c
+100 -91
View File
@@ -30,14 +30,28 @@
* *
************************************************************************************/ ************************************************************************************/
/************************************************************************************
* Included Files
************************************************************************************/
#include <nuttx/config.h> #include <nuttx/config.h>
#include <nuttx/arch.h>
#include <nuttx/irq.h> #include <nuttx/irq.h>
#include <arch/irq.h> #include <arch/irq.h>
#include "nr5.h" #include "nr5.h"
/************************************************************************************
* Pre-processor Definitions
************************************************************************************/
#define MAKE_UINT32(a,b,c,d) (((a) << 24) | ((b) << 16) | ((c) << 8) | d) #define MAKE_UINT32(a,b,c,d) (((a) << 24) | ((b) << 16) | ((c) << 8) | d)
/************************************************************************************
* Private Types
************************************************************************************/
struct nr5_uart_buffer_s struct nr5_uart_buffer_s
{ {
uint16_t head; uint16_t head;
@@ -48,27 +62,27 @@ struct nr5_uart_buffer_s
struct nr5_uart_regs_s struct nr5_uart_regs_s
{ {
uint32_t* pBaud; // Data status port uint32_t* pbaud; /* Data status port */
uint32_t* pStat; // Data status port uint32_t* pstat; /* Data status port */
uint8_t* pTx; // Data TX port uint8_t* ptx; /* Data TX port */
uint8_t* pRx; // Data RX port uint8_t* prx; /* Data RX port */
uint32_t* pIntCtrl; // Interrupt enable control uint32_t* pintctrl; /* Interrupt enable control */
int rx_irq; // IRQ number int rxirq; /* IRQ number */
int tx_irq; // IRQ number int txirq; /* IRQ number */
}; };
struct nr5_uart_s struct nr5_uart_s
{ {
volatile struct nr5_uart_regs_s * regs; volatile struct nr5_uart_regs_s *regs;
struct nr5_uart_buffer_s * tx_buf; struct nr5_uart_buffer_s *txbuf;
struct nr5_uart_buffer_s * rx_buf; struct nr5_uart_buffer_s *rxbuf;
}; };
/* /************************************************************************************
============================================================================== * Private Data
Static global pointers to access the hardware ************************************************************************************/
==============================================================================
*/ /* Static global pointers to access the hardware */
#ifdef CONFIG_NR5_HAVE_UART1 #ifdef CONFIG_NR5_HAVE_UART1
static char g_uart1_rx_buf[CONFIG_NR5_UART_RX_BUF_SIZE]; static char g_uart1_rx_buf[CONFIG_NR5_UART_RX_BUF_SIZE];
@@ -76,51 +90,52 @@ static char g_uart1_tx_buf[CONFIG_NR5_UART_TX_BUF_SIZE];
static struct nr5_uart_buffer_s g_nr5_uart1_rx_buf = static struct nr5_uart_buffer_s g_nr5_uart1_rx_buf =
{ {
.head = 0, .head = 0,
.tail = 0, .tail = 0,
.size = CONFIG_NR5_UART_RX_BUF_SIZE, .size = CONFIG_NR5_UART_RX_BUF_SIZE,
.buffer = g_uart1_rx_buf, .buffer = g_uart1_rx_buf,
}; };
static struct nr5_uart_buffer_s g_nr5_uart1_tx_buf = static struct nr5_uart_buffer_s g_nr5_uart1_tx_buf =
{ {
.head = 0, .head = 0,
.tail = 0, .tail = 0,
.size = CONFIG_NR5_UART_TX_BUF_SIZE, .size = CONFIG_NR5_UART_TX_BUF_SIZE,
.buffer = g_uart1_tx_buf, .buffer = g_uart1_tx_buf,
}; };
static volatile struct nr5_uart_regs_s g_nr5_uart1_regs = static volatile struct nr5_uart_regs_s g_nr5_uart1_regs =
{ {
.pBaud = (uint32_t *) NR5_UART1_BAUD_RATE_REG, .pbaud = (uint32_t *) NR5_UART1_BAUD_RATE_REG,
.pStat = (uint32_t *) NR5_UART1_STATUS_REG, .pstat = (uint32_t *) NR5_UART1_STATUS_REG,
.pRx = (uint8_t *) NR5_UART1_RX_REG, .prx = (uint8_t *) NR5_UART1_RX_REG,
.pTx = (uint8_t *) NR5_UART1_TX_REG, .ptx = (uint8_t *) NR5_UART1_TX_REG,
.pIntCtrl = (uint32_t *) NR5_UART1_CTRL_REG, .pintctrl = (uint32_t *) NR5_UART1_CTRL_REG,
.rx_irq = NR5_IRQ_UART1_RX, .rxirq = NR5_IRQ_UART1_RX,
.tx_irq = NR5_IRQ_UART1_TX, .txirq = NR5_IRQ_UART1_TX,
}; };
static struct nr5_uart_s g_nr5_uart1 = static struct nr5_uart_s g_nr5_uart1 =
{ {
.regs = &g_nr5_uart1_regs, .regs = &g_nr5_uart1_regs,
.rx_buf = &g_nr5_uart1_rx_buf, .rxbuf = &g_nr5_uart1_rx_buf,
.tx_buf = &g_nr5_uart1_tx_buf, .txbuf = &g_nr5_uart1_tx_buf,
}; };
#endif #endif
/* /************************************************************************************
============================================================================== * Public Functions
ISR for NanoRisc5 UART RX availalbe. ************************************************************************************/
==============================================================================
*/ /* ISR for NanoRisc5 UART RX available. */
int nr5_uart_rx_isr(int irq_num, void *context) int nr5_uart_rx_isr(int irq_num, void *context)
{ {
struct nr5_uart_s *dev = NULL; struct nr5_uart_s *dev = NULL;
char rxdata; char rxdata;
#ifdef CONFIG_NR5_HAVE_UART1 #ifdef CONFIG_NR5_HAVE_UART1
if (irq_num == g_nr5_uart1_regs.rx_irq) if (irq_num == g_nr5_uart1_regs.rxirq)
{ {
dev = &g_nr5_uart1; dev = &g_nr5_uart1;
} }
@@ -132,88 +147,83 @@ int nr5_uart_rx_isr(int irq_num, void *context)
{ {
/* Read the RX byte */ /* Read the RX byte */
rxdata = *dev->regs->pRx; rxdata = *dev->regs->prx;
*dev->regs->pTx = rxdata; *dev->regs->ptx = rxdata;
dev->rx_buf->buffer[dev->rx_buf->head++] = rxdata; dev->rxbuf->buffer[dev->rxbuf->head++] = rxdata;
if (dev->rx_buf->head == dev->rx_buf->size) if (dev->rxbuf->head == dev->rxbuf->size)
dev->rx_buf->head = 0; {
dev->rxbuf->head = 0;
}
} }
return 0; return 0;
} }
/* /* Routine to initialize the HAL layer. Must be called prior to any other
============================================================================== * HAL function.
Routine to initialize the HAL layer. Must be called prior to any other */
HAL function.
==============================================================================
*/
void nr5_uart_init(int uart) void nr5_uart_init(int uart)
{ {
volatile struct nr5_uart_s *dev = NULL; volatile struct nr5_uart_s *dev = NULL;
uint32_t cmpval = MAKE_UINT32('F', 'P', 'G', 'A'); uint32_t cmpval = MAKE_UINT32('F', 'P', 'G', 'A');
switch (uart) switch (uart)
{ {
#ifdef CONFIG_NR5_HAVE_UART1 #ifdef CONFIG_NR5_HAVE_UART1
case 1: case 1:
dev = &g_nr5_uart1; dev = &g_nr5_uart1;
#endif #endif
} }
/* If a device was selected above, then initialize it. */
// If a device was selected above, then initilize it
//
if (dev != NULL) if (dev != NULL)
{ {
/* Attache the ISR and enable the IRQ with the EPIC */ /* Attach the ISR and enable the IRQ with the EPIC */
//irq_attach(dev->regs->rx_irq, &nr5_uart_rx_isr, NULL); //irq_attach(dev->regs->rxirq, &nr5_uart_rx_isr, NULL);
//up_enable_irq(dev->regs->rx_irq); //up_enable_irq(dev->regs->rxirq);
// Set the baud rate /* Set the baud rate */
if (up_getimpid() == cmpval) if (up_getimpid() == cmpval)
{ {
*dev->regs->pBaud = 0x0d; *dev->regs->pbaud = 0x0d;
} }
/* Now enable the RX IRQ in the UART peripheral */ /* Now enable the RX IRQ in the UART peripheral */
//*dev->regs->pIntCtrl = NR5_UART_CTRL_ENABLE_RX_IRQ; //*dev->regs->pintctrl = NR5_UART_CTRL_ENABLE_RX_IRQ;
} }
} }
/* /* Routine to get RX byte from console UART. */
==============================================================================
Routine to get RX byte from console UART
==============================================================================
*/
uint8_t nr5_uart_get_rx() uint8_t nr5_uart_get_rx()
{ {
uint8_t rxdata = 0; uint8_t rxdata = 0;
up_disableints(); up_disableints();
if (g_nr5_uart1.rx_buf->head != g_nr5_uart1.rx_buf->tail) if (g_nr5_uart1.rxbuf->head != g_nr5_uart1.rxbuf->tail)
{ {
struct nr5_uart_buffer_s *pBuf = g_nr5_uart1.rx_buf; struct nr5_uart_buffer_s *pBuf = g_nr5_uart1.rxbuf;
rxdata = pBuf->buffer[pBuf->tail++]; rxdata = pBuf->buffer[pBuf->tail++];
if (pBuf->tail == pBuf->size) if (pBuf->tail == pBuf->size)
pBuf->tail = 0; pBuf->tail = 0;
} }
up_enableints(); up_enableints();
return rxdata; return rxdata;
} }
/* /* Routine to test if RX byte available at console UART */
==============================================================================
Routine to test if RX byte available at console UART
==============================================================================
*/
int nr5_uart_test_rx_avail() int nr5_uart_test_rx_avail()
{ {
struct nr5_uart_buffer_s *pBuf = g_nr5_uart1.rx_buf; struct nr5_uart_buffer_s *pBuf = g_nr5_uart1.rxbuf;
int avail; int avail;
up_disableints(); up_disableints();
@@ -221,34 +231,33 @@ int nr5_uart_test_rx_avail()
up_enableints(); up_enableints();
/* If no RX data available then halt the processor until an interrupt */ /* If no RX data available then halt the processor until an interrupt */
if (!avail) if (!avail)
__asm__ volatile ("wfi"); {
__asm__ volatile ("wfi");
}
return avail; return avail;
} }
/* /* Routine to test if RX byte available at console UART. */
==============================================================================
Routine to test if RX byte available at console UART
==============================================================================
*/
int nr5_uart_test_tx_empty() int nr5_uart_test_tx_empty()
{ {
return *g_nr5_uart1.regs->pStat & NR5_UART_STATUS_TX_EMPTY; return *g_nr5_uart1.regs->pstat & NR5_UART_STATUS_TX_EMPTY;
} }
/* /* Routine to send TX byte to console UART. */
==============================================================================
Routine to send TX byte to console UART
==============================================================================
*/
void nr5_uart_put_tx(uint8_t ch) void nr5_uart_put_tx(uint8_t ch)
{ {
// Wait for TX to be empty /* Wait for TX to be empty */
while (!(*g_nr5_uart1.regs->pStat & NR5_UART_STATUS_TX_EMPTY))
while (!(*g_nr5_uart1.regs->pstat & NR5_UART_STATUS_TX_EMPTY))
; ;
// Write to TX /* Write to TX */
*g_nr5_uart1.regs->pTx = ch;
*g_nr5_uart1.regs->ptx = ch;
} }