diff --git a/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/src/lpc17_40_dac.c b/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/src/lpc17_40_dac.c index 94857076cba..5ba4b30366f 100644 --- a/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/src/lpc17_40_dac.c +++ b/boards/arm/lpc17xx_40xx/lpcxpresso-lpc1768/src/lpc17_40_dac.c @@ -57,6 +57,10 @@ #ifdef CONFIG_DAC +/**************************************************************************** + * Public Functions + ****************************************************************************/ + /**************************************************************************** * Name: dac_devinit * @@ -73,25 +77,27 @@ int dac_devinit(void) int ret; if (!initialized) - { - /* Call lpc17_40_dacinitialize() to get an instance of the dac interface */ + { + /* Call lpc17_40_dacinitialize() to get an instance of the dac + * interface + */ - dac = lpc17_40_dacinitialize(); - if (dac == NULL) - { - aerr("ERROR: Failed to get dac interface\n"); - return -ENODEV; - } + dac = lpc17_40_dacinitialize(); + if (dac == NULL) + { + aerr("ERROR: Failed to get dac interface\n"); + return -ENODEV; + } - ret = dac_register("/dev/dac0", dac); - if (ret < 0) - { - aerr("ERROR: dac_register failed: %d\n", ret); - return ret; - } + ret = dac_register("/dev/dac0", dac); + if (ret < 0) + { + aerr("ERROR: dac_register failed: %d\n", ret); + return ret; + } - initialized = true; - } + initialized = true; + } return OK; } diff --git a/boards/arm/lpc17xx_40xx/mbed/src/lpc17_40_adc.c b/boards/arm/lpc17xx_40xx/mbed/src/lpc17_40_adc.c index 05cc043acbb..c7b3e01e81c 100644 --- a/boards/arm/lpc17xx_40xx/mbed/src/lpc17_40_adc.c +++ b/boards/arm/lpc17xx_40xx/mbed/src/lpc17_40_adc.c @@ -83,7 +83,9 @@ int mbed_adc_setup(void) if (!initialized) { - /* Call lpc17_40_adcinitialize() to get an instance of the ADC interface */ + /* Call lpc17_40_adcinitialize() to get an instance of the ADC + * interface + */ adc = lpc17_40_adcinitialize(); if (adc == NULL) diff --git a/boards/arm/lpc17xx_40xx/mbed/src/lpc17_40_dac.c b/boards/arm/lpc17xx_40xx/mbed/src/lpc17_40_dac.c index 138a8e74a93..94ce55c212c 100644 --- a/boards/arm/lpc17xx_40xx/mbed/src/lpc17_40_dac.c +++ b/boards/arm/lpc17xx_40xx/mbed/src/lpc17_40_dac.c @@ -59,6 +59,10 @@ #ifdef CONFIG_DAC +/**************************************************************************** + * Public Functions + ****************************************************************************/ + /**************************************************************************** * Name: dac_devinit * @@ -75,25 +79,27 @@ int dac_devinit(void) int ret; if (!initialized) - { - /* Call lpc17_40_dacinitialize() to get an instance of the dac interface */ + { + /* Call lpc17_40_dacinitialize() to get an instance of the dac + * interface + */ - dac = lpc17_40_dacinitialize(); - if (dac == NULL) - { - aerr("ERROR: Failed to get dac interface\n"); - return -ENODEV; - } + dac = lpc17_40_dacinitialize(); + if (dac == NULL) + { + aerr("ERROR: Failed to get dac interface\n"); + return -ENODEV; + } - ret = dac_register("/dev/dac0", dac); - if (ret < 0) - { - aerr("ERROR: dac_register failed: %d\n", ret); - return ret; - } + ret = dac_register("/dev/dac0", dac); + if (ret < 0) + { + aerr("ERROR: dac_register failed: %d\n", ret); + return ret; + } - initialized = true; - } + initialized = true; + } return OK; } diff --git a/boards/arm/lpc17xx_40xx/mcb1700/src/lpc17_40_dac.c b/boards/arm/lpc17xx_40xx/mcb1700/src/lpc17_40_dac.c index c4522093e31..6beeec5a314 100644 --- a/boards/arm/lpc17xx_40xx/mcb1700/src/lpc17_40_dac.c +++ b/boards/arm/lpc17xx_40xx/mcb1700/src/lpc17_40_dac.c @@ -59,6 +59,10 @@ #ifdef CONFIG_DAC +/**************************************************************************** + * Public Functions + ****************************************************************************/ + /**************************************************************************** * Name: dac_devinit * @@ -76,25 +80,25 @@ int dac_devinit(void) if (!initialized) { - /* Call lpc17_40_dacinitialize() to get an instance - * of the dac interface - */ + /* Call lpc17_40_dacinitialize() to get an instance + * of the dac interface + */ - dac = lpc17_40_dacinitialize(); - if (dac == NULL) - { - aerr("ERROR: Failed to get dac interface\n"); - return -ENODEV; - } + dac = lpc17_40_dacinitialize(); + if (dac == NULL) + { + aerr("ERROR: Failed to get dac interface\n"); + return -ENODEV; + } - ret = dac_register("/dev/dac0", dac); - if (ret < 0) - { - aerr("ERROR: dac_register failed: %d\n", ret); - return ret; - } + ret = dac_register("/dev/dac0", dac); + if (ret < 0) + { + aerr("ERROR: dac_register failed: %d\n", ret); + return ret; + } - initialized = true; + initialized = true; } return OK; diff --git a/boards/arm/lpc17xx_40xx/u-blox-c027/include/board.h b/boards/arm/lpc17xx_40xx/u-blox-c027/include/board.h index d336d304ddf..f9719572d89 100644 --- a/boards/arm/lpc17xx_40xx/u-blox-c027/include/board.h +++ b/boards/arm/lpc17xx_40xx/u-blox-c027/include/board.h @@ -61,9 +61,11 @@ /* This is the clock setup we configure for: * - * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for source - * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multipler=20, pre-divider=1 - * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 + * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> + * Select Main oscillator for source + * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> + * PLL0 multipler=20, pre-divider=1 + * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 */ #define LPC17_40_CCLK 80000000 /* 80Mhz */ @@ -216,6 +218,7 @@ /* The u-blox C027 board has a single red LED * (there are additional LEDs on the base board not considered here). */ + /* ON OFF */ #define LED_STARTED 0 /* OFF ON (never happens) */ #define LED_HEAPALLOCATE 0 /* OFF ON (never happens) */ diff --git a/boards/arm/lpc17xx_40xx/zkit-arm-1769/include/board.h b/boards/arm/lpc17xx_40xx/zkit-arm-1769/include/board.h index 80926132818..d67f804aedc 100644 --- a/boards/arm/lpc17xx_40xx/zkit-arm-1769/include/board.h +++ b/boards/arm/lpc17xx_40xx/zkit-arm-1769/include/board.h @@ -72,9 +72,11 @@ /* This is the clock setup we configure for: * - * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> Select Main oscillator for source - * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> PLL0 multipler=20, pre-divider=1 - * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 + * SYSCLK = BOARD_OSCCLK_FREQUENCY = 12MHz -> + * Select Main oscillator for source + * PLL0CLK = (2 * 20 * SYSCLK) / 1 = 480MHz -> + * PLL0 multipler=20, pre-divider=1 + * CCLCK = 480MHz / 6 = 80MHz -> CCLK divider = 6 */ #define LPC17_40_CCLK 80000000 /* 80Mhz */ @@ -141,7 +143,8 @@ /* Ethernet configuration */ -//#define ETH_MCFG_CLKSEL_DIV ETH_MCFG_CLKSEL_DIV44 +/* #define ETH_MCFG_CLKSEL_DIV ETH_MCFG_CLKSEL_DIV44 */ + #define ETH_MCFG_CLKSEL_DIV ETH_MCFG_CLKSEL_DIV20 /* LED definitions **********************************************************/ @@ -179,6 +182,7 @@ * LED 1 is available for use by application software using lpc17_40_led * (prototyped below) */ + /* LED1 LED2 */ #define LED_INIRQ 4 /* NC ON (momentary) */ #define LED_SIGNAL 5 /* NC ON (momentary) */ @@ -346,7 +350,8 @@ extern "C" * Name: lpc17_40_led * * Description: - * Once the system has booted, these functions can be used to control LEDs 1 + * Once the system has booted, + * these functions can be used to control LEDs 1 * ****************************************************************************/ diff --git a/boards/arm/lpc17xx_40xx/zkit-arm-1769/src/lpc17_40_boot.c b/boards/arm/lpc17xx_40xx/zkit-arm-1769/src/lpc17_40_boot.c index eca40cdecbe..fa24892f4a0 100644 --- a/boards/arm/lpc17xx_40xx/zkit-arm-1769/src/lpc17_40_boot.c +++ b/boards/arm/lpc17xx_40xx/zkit-arm-1769/src/lpc17_40_boot.c @@ -70,7 +70,8 @@ * Name: lpc17_40_boardinitialize * * Description: - * All LPC17xx/LPC40xx architectures must provide the following entry point. + * All LPC17xx/LPC40xx architectures must provide the following entry + * point. * This entry point is called early in the initialization -- after all * memory has been configured and mapped but before any devices have been * initialized. diff --git a/boards/arm/lpc17xx_40xx/zkit-arm-1769/src/lpc17_40_dac.c b/boards/arm/lpc17xx_40xx/zkit-arm-1769/src/lpc17_40_dac.c index 829d513a3ec..72459c21051 100644 --- a/boards/arm/lpc17xx_40xx/zkit-arm-1769/src/lpc17_40_dac.c +++ b/boards/arm/lpc17xx_40xx/zkit-arm-1769/src/lpc17_40_dac.c @@ -58,6 +58,10 @@ #ifdef CONFIG_DAC +/**************************************************************************** + * Public Functions + ****************************************************************************/ + /**************************************************************************** * Name: dac_devinit * @@ -74,25 +78,27 @@ int dac_devinit(void) int ret; if (!initialized) - { - /* Call lpc17_40_dacinitialize() to get an instance of the dac interface */ + { + /* Call lpc17_40_dacinitialize() to get an instance of the dac + * interface + */ - dac = lpc17_40_dacinitialize(); - if (dac == NULL) - { - aerr("ERROR: Failed to get dac interface\n"); - return -ENODEV; - } + dac = lpc17_40_dacinitialize(); + if (dac == NULL) + { + aerr("ERROR: Failed to get dac interface\n"); + return -ENODEV; + } - ret = dac_register("/dev/dac0", dac); - if (ret < 0) - { - aerr("ERROR: dac_register failed: %d\n", ret); - return ret; - } + ret = dac_register("/dev/dac0", dac); + if (ret < 0) + { + aerr("ERROR: dac_register failed: %d\n", ret); + return ret; + } - initialized = true; - } + initialized = true; + } return OK; } diff --git a/boards/arm/lpc31xx/ea3152/tools/crc32.c b/boards/arm/lpc31xx/ea3152/tools/crc32.c index 507fc623fdc..57a81e8b849 100644 --- a/boards/arm/lpc31xx/ea3152/tools/crc32.c +++ b/boards/arm/lpc31xx/ea3152/tools/crc32.c @@ -7,37 +7,44 @@ * * The logic in this file was developed by Gary S. Brown: * - * COPYRIGHT (C) 1986 Gary S. Brown. You may use this program, or code or tables - * extracted from it, as desired without restriction. + * COPYRIGHT (C) 1986 Gary S. Brown. You may use this program, or code + * or tables extracted from it, as desired without restriction. * - * First, the polynomial itself and its table of feedback terms. The polynomial is: + * First, the polynomial itself and its table of feedback terms. + * The polynomial is: * - * X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0 + * X^32+X^26+X^23+X^22+X^16+X^12+X^11+X^10+X^8+X^7+X^5+X^4+X^2+X^1+X^0 * - * Note that we take it "backwards" and put the highest-order term in the lowest-order bit. - * The X^32 term is "implied"; the LSB is the X^31 term, etc. The X^0 term (usually shown - * as "+1") results in the MSB being 1 + * Note that we take it "backwards" and put the highest-order term in the + * lowest-order bit. + * The X^32 term is "implied"; the LSB is the X^31 term, etc. + * The X^0 term (usually shown as "+1") results in the MSB being 1 * - * Note that the usual hardware shift register implementation, which is what we're using - * (we're merely optimizing it by doing eight-bit chunks at a time) shifts bits into the - * lowest-order term. In our implementation, that means shifting towards the right. Why - * do we do it this way? Because the calculated CRC must be transmitted in order from - * highest-order term to lowest-order term. UARTs transmit characters in order from LSB - * to MSB. By storing the CRC this way we hand it to the UART in the order low-byte to - * high-byte; the UART sends each low-bit to hight-bit; and the result is transmission bit - * by bit from highest- to lowest-order term without requiring any bit shuffling on our - * part. Reception works similarly + * Note that the usual hardware shift register implementation, which is what + * we're using (we're merely optimizing it by doing eight-bit chunks at a + * time) shifts bits into the lowest-order term. In our implementation, that + * means shifting towards the right. Why do we do it this way? Because the + * calculated CRC must be transmitted in order from highest-order term to + * lowest-order term. UARTs transmit characters in order from LSB to MSB. + * By storing the CRC this way we hand it to the UART in the order low-byte + * to high-byte; the UART sends each low-bit to hight-bit; and the result is + * transmission bit by bit from highest- to lowest-order term without + * requiring any bit shuffling on our part. Reception works similarly * - * The feedback terms table consists of 256, 32-bit entries. Notes + * The feedback terms table consists of 256, 32-bit entries. + * Notes * - * - The table can be generated at runtime if desired; code to do so is shown later. It - * might not be obvious, but the feedback terms simply represent the results of eight - * shift/xor operations for all combinations of data and CRC register values + * - The table can be generated at runtime if desired; code to do so is shown + * later. It might not be obvious, but the feedback terms simply represent + * the results of eight shift/xor operations for all combinations of data + * and CRC register values * - * - The values must be right-shifted by eight bits by the updcrc logic; the shift must - * be u_(bring in zeroes). On some hardware you could probably optimize the shift in - * assembler by using byte-swap instructions polynomial $edb88320 - ***************************************************************************/ + * - The values must be right-shifted by eight bits by the updcrc logic; the + * shift must be u_(bring in zeroes). On some hardware you could probably + * optimize the shift in assembler by using byte-swap instructions + * polynomial $edb88320 + * + ****************************************************************************/ /**************************************************************************** * Included Files @@ -53,38 +60,70 @@ static const uint32_t crc32_tab[] = { - 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, - 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, - 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, - 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, - 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, - 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, - 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, - 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, - 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, - 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, - 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, - 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, - 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, - 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, - 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, - 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, - 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, - 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, - 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, - 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, - 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, - 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, - 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, - 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, - 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, - 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, - 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, - 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, - 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, - 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, - 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, - 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, + 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, + 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, + 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, + 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, + 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, + 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, + 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, + 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, + 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, + 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, + 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, + 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, + 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, + 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, + 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, + 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, + 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, + 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, + 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, + 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, + 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, + 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, + 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, + 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, + 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, + 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, + 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, + 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, + 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, + 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, + 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, + 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, + 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, + 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, + 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, + 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, + 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, + 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, + 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, + 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, + 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, + 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, + 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, + 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, + 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, + 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, + 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, + 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, + 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d }; /**************************************************************************** @@ -107,6 +146,7 @@ uint32_t crc32part(const uint8_t *src, size_t len, uint32_t crc32val) { crc32val = crc32_tab[(crc32val ^ src[i]) & 0xff] ^ (crc32val >> 8); } + return crc32val; } diff --git a/boards/arm/lpc31xx/olimex-lpc-h3131/tools/crc32.c b/boards/arm/lpc31xx/olimex-lpc-h3131/tools/crc32.c index f7214fc9de2..abc14551ded 100644 --- a/boards/arm/lpc31xx/olimex-lpc-h3131/tools/crc32.c +++ b/boards/arm/lpc31xx/olimex-lpc-h3131/tools/crc32.c @@ -59,38 +59,70 @@ static const uint32_t crc32_tab[] = { - 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, - 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, - 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, - 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, - 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, - 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, - 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, - 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, - 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, - 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, - 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, - 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, - 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, - 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, - 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, - 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, - 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, - 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, - 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, - 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, - 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, - 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, - 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, - 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, - 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, - 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, - 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, - 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, - 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, - 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, - 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, - 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d + 0x00000000, 0x77073096, 0xee0e612c, 0x990951ba, + 0x076dc419, 0x706af48f, 0xe963a535, 0x9e6495a3, + 0x0edb8832, 0x79dcb8a4, 0xe0d5e91e, 0x97d2d988, + 0x09b64c2b, 0x7eb17cbd, 0xe7b82d07, 0x90bf1d91, + 0x1db71064, 0x6ab020f2, 0xf3b97148, 0x84be41de, + 0x1adad47d, 0x6ddde4eb, 0xf4d4b551, 0x83d385c7, + 0x136c9856, 0x646ba8c0, 0xfd62f97a, 0x8a65c9ec, + 0x14015c4f, 0x63066cd9, 0xfa0f3d63, 0x8d080df5, + 0x3b6e20c8, 0x4c69105e, 0xd56041e4, 0xa2677172, + 0x3c03e4d1, 0x4b04d447, 0xd20d85fd, 0xa50ab56b, + 0x35b5a8fa, 0x42b2986c, 0xdbbbc9d6, 0xacbcf940, + 0x32d86ce3, 0x45df5c75, 0xdcd60dcf, 0xabd13d59, + 0x26d930ac, 0x51de003a, 0xc8d75180, 0xbfd06116, + 0x21b4f4b5, 0x56b3c423, 0xcfba9599, 0xb8bda50f, + 0x2802b89e, 0x5f058808, 0xc60cd9b2, 0xb10be924, + 0x2f6f7c87, 0x58684c11, 0xc1611dab, 0xb6662d3d, + 0x76dc4190, 0x01db7106, 0x98d220bc, 0xefd5102a, + 0x71b18589, 0x06b6b51f, 0x9fbfe4a5, 0xe8b8d433, + 0x7807c9a2, 0x0f00f934, 0x9609a88e, 0xe10e9818, + 0x7f6a0dbb, 0x086d3d2d, 0x91646c97, 0xe6635c01, + 0x6b6b51f4, 0x1c6c6162, 0x856530d8, 0xf262004e, + 0x6c0695ed, 0x1b01a57b, 0x8208f4c1, 0xf50fc457, + 0x65b0d9c6, 0x12b7e950, 0x8bbeb8ea, 0xfcb9887c, + 0x62dd1ddf, 0x15da2d49, 0x8cd37cf3, 0xfbd44c65, + 0x4db26158, 0x3ab551ce, 0xa3bc0074, 0xd4bb30e2, + 0x4adfa541, 0x3dd895d7, 0xa4d1c46d, 0xd3d6f4fb, + 0x4369e96a, 0x346ed9fc, 0xad678846, 0xda60b8d0, + 0x44042d73, 0x33031de5, 0xaa0a4c5f, 0xdd0d7cc9, + 0x5005713c, 0x270241aa, 0xbe0b1010, 0xc90c2086, + 0x5768b525, 0x206f85b3, 0xb966d409, 0xce61e49f, + 0x5edef90e, 0x29d9c998, 0xb0d09822, 0xc7d7a8b4, + 0x59b33d17, 0x2eb40d81, 0xb7bd5c3b, 0xc0ba6cad, + 0xedb88320, 0x9abfb3b6, 0x03b6e20c, 0x74b1d29a, + 0xead54739, 0x9dd277af, 0x04db2615, 0x73dc1683, + 0xe3630b12, 0x94643b84, 0x0d6d6a3e, 0x7a6a5aa8, + 0xe40ecf0b, 0x9309ff9d, 0x0a00ae27, 0x7d079eb1, + 0xf00f9344, 0x8708a3d2, 0x1e01f268, 0x6906c2fe, + 0xf762575d, 0x806567cb, 0x196c3671, 0x6e6b06e7, + 0xfed41b76, 0x89d32be0, 0x10da7a5a, 0x67dd4acc, + 0xf9b9df6f, 0x8ebeeff9, 0x17b7be43, 0x60b08ed5, + 0xd6d6a3e8, 0xa1d1937e, 0x38d8c2c4, 0x4fdff252, + 0xd1bb67f1, 0xa6bc5767, 0x3fb506dd, 0x48b2364b, + 0xd80d2bda, 0xaf0a1b4c, 0x36034af6, 0x41047a60, + 0xdf60efc3, 0xa867df55, 0x316e8eef, 0x4669be79, + 0xcb61b38c, 0xbc66831a, 0x256fd2a0, 0x5268e236, + 0xcc0c7795, 0xbb0b4703, 0x220216b9, 0x5505262f, + 0xc5ba3bbe, 0xb2bd0b28, 0x2bb45a92, 0x5cb36a04, + 0xc2d7ffa7, 0xb5d0cf31, 0x2cd99e8b, 0x5bdeae1d, + 0x9b64c2b0, 0xec63f226, 0x756aa39c, 0x026d930a, + 0x9c0906a9, 0xeb0e363f, 0x72076785, 0x05005713, + 0x95bf4a82, 0xe2b87a14, 0x7bb12bae, 0x0cb61b38, + 0x92d28e9b, 0xe5d5be0d, 0x7cdcefb7, 0x0bdbdf21, + 0x86d3d2d4, 0xf1d4e242, 0x68ddb3f8, 0x1fda836e, + 0x81be16cd, 0xf6b9265b, 0x6fb077e1, 0x18b74777, + 0x88085ae6, 0xff0f6a70, 0x66063bca, 0x11010b5c, + 0x8f659eff, 0xf862ae69, 0x616bffd3, 0x166ccf45, + 0xa00ae278, 0xd70dd2ee, 0x4e048354, 0x3903b3c2, + 0xa7672661, 0xd06016f7, 0x4969474d, 0x3e6e77db, + 0xaed16a4a, 0xd9d65adc, 0x40df0b66, 0x37d83bf0, + 0xa9bcae53, 0xdebb9ec5, 0x47b2cf7f, 0x30b5ffe9, + 0xbdbdf21c, 0xcabac28a, 0x53b39330, 0x24b4a3a6, + 0xbad03605, 0xcdd70693, 0x54de5729, 0x23d967bf, + 0xb3667a2e, 0xc4614ab8, 0x5d681b02, 0x2a6f2b94, + 0xb40bbe37, 0xc30c8ea1, 0x5a05df1b, 0x2d02ef8d }; /**************************************************************************** @@ -113,6 +145,7 @@ uint32_t crc32part(const uint8_t *src, size_t len, uint32_t crc32val) { crc32val = crc32_tab[(crc32val ^ src[i]) & 0xff] ^ (crc32val >> 8); } + return crc32val; } diff --git a/boards/arm/moxart/moxa/src/moxart_boot.c b/boards/arm/moxart/moxa/src/moxart_boot.c index 388cbe44f76..5fce87e1d00 100644 --- a/boards/arm/moxart/moxa/src/moxart_boot.c +++ b/boards/arm/moxart/moxa/src/moxart_boot.c @@ -63,10 +63,11 @@ * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. * ****************************************************************************/ diff --git a/boards/arm/sam34/sam4e-ek/src/sam_ili9325.c b/boards/arm/sam34/sam4e-ek/src/sam_ili9325.c index 7846ff39ea3..07afcd5250e 100644 --- a/boards/arm/sam34/sam4e-ek/src/sam_ili9325.c +++ b/boards/arm/sam34/sam4e-ek/src/sam_ili9325.c @@ -401,10 +401,10 @@ static const struct fb_videoinfo_s g_videoinfo = static const struct lcd_planeinfo_s g_planeinfo = { - .putrun = sam_putrun, /* Put a run into LCD memory */ - .getrun = sam_getrun, /* Get a run from LCD memory */ - .buffer = (uint8_t*)g_runbuffer, /* Run scratch buffer */ - .bpp = SAM_BPP, /* Bits-per-pixel */ + .putrun = sam_putrun, /* Put a run into LCD memory */ + .getrun = sam_getrun, /* Get a run from LCD memory */ + .buffer = (uint8_t *)g_runbuffer, /* Run scratch buffer */ + .bpp = SAM_BPP, /* Bits-per-pixel */ }; /* This is the standard, NuttX LCD driver object */ @@ -582,6 +582,7 @@ static void sam_dumprun(FAR const char *msg, FAR uint16_t *run, { syslog(LOG_DEBUG, " %04x", *run++); } + up_putc('\n'); } } @@ -607,7 +608,8 @@ static void sam_disable_backlight(void) * Name: sam_set_backlight * * Description: - * The the backlight to the level associated with the specified power value. + * The the backlight to the level associated with the specified power + * value. * ****************************************************************************/ @@ -691,11 +693,11 @@ static int sam_putrun(fb_coord_t row, fb_coord_t col, size_t npixels) { #if defined(CONFIG_SAM4EEK_LCD_RGB565) - FAR const uint16_t *src = (FAR const uint16_t*)buffer; + FAR const uint16_t *src = (FAR const uint16_t *)buffer; #elif defined(CONFIG_SAM4EEK_LCD_RGB24) - FAR const uint8_t *src = (FAR const uint8_t*)buffer; + FAR const uint8_t *src = (FAR const uint8_t *)buffer; #elif defined(CONFIG_SAM4EEK_LCD_RGB32) - FAR const uint32_t *src = (FAR const uint32_t*)buffer; + FAR const uint32_t *src = (FAR const uint32_t *)buffer; #endif /* Buffer must be provided and aligned to a 16-bit address boundary */ @@ -1133,7 +1135,8 @@ static void sam_lcd9325_initialize(void) sam_write_reg(ILI9325_GAMMA_CTRL9, ILI9325_GAMMA_CTRL9_RN1(7) | ILI9325_GAMMA_CTRL9_RN0(1)); sam_write_reg(ILI9325_GAMMA_CTRL10, - ILI9325_GAMMA_CTRL10_VRN1(0) | ILI9325_GAMMA_CTRL10_VRN0(14)); + ILI9325_GAMMA_CTRL10_VRN1(0) | + ILI9325_GAMMA_CTRL10_VRN0(14)); /* Set the Entry Mode: * diff --git a/boards/arm/sam34/sam4e-ek/src/sam_ili9341.c b/boards/arm/sam34/sam4e-ek/src/sam_ili9341.c index 3cab6fcf20d..d26a19cb87b 100644 --- a/boards/arm/sam34/sam4e-ek/src/sam_ili9341.c +++ b/boards/arm/sam34/sam4e-ek/src/sam_ili9341.c @@ -407,10 +407,10 @@ static const struct fb_videoinfo_s g_videoinfo = static const struct lcd_planeinfo_s g_planeinfo = { - .putrun = sam_putrun, /* Put a run into LCD memory */ - .getrun = sam_getrun, /* Get a run from LCD memory */ - .buffer = (uint8_t*)g_runbuffer, /* Run scratch buffer */ - .bpp = SAM_BPP, /* Bits-per-pixel */ + .putrun = sam_putrun, /* Put a run into LCD memory */ + .getrun = sam_getrun, /* Get a run from LCD memory */ + .buffer = (uint8_t *)g_runbuffer, /* Run scratch buffer */ + .bpp = SAM_BPP, /* Bits-per-pixel */ }; /* This is the standard, NuttX LCD driver object */ @@ -730,11 +730,11 @@ static int sam_putrun(fb_coord_t row, fb_coord_t col, size_t npixels) { #if defined(CONFIG_SAM4EEK_LCD_RGB565) - FAR const uint16_t *src = (FAR const uint16_t*)buffer; + FAR const uint16_t *src = (FAR const uint16_t *)buffer; #elif defined(CONFIG_SAM4EEK_LCD_RGB24) - FAR const uint8_t *src = (FAR const uint8_t*)buffer; + FAR const uint8_t *src = (FAR const uint8_t *)buffer; #elif defined(CONFIG_SAM4EEK_LCD_RGB32) - FAR const uint32_t *src = (FAR const uint32_t*)buffer; + FAR const uint32_t *src = (FAR const uint32_t *)buffer; #endif /* Buffer must be provided and aligned to a 16-bit address boundary */ @@ -788,11 +788,11 @@ static int sam_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, size_t npixels) { #if defined(CONFIG_SAM4EEK_LCD_RGB565) - FAR uint16_t *dest = (FAR uint16_t*)buffer; + FAR uint16_t *dest = (FAR uint16_t *)buffer; #elif defined(CONFIG_SAM4EEK_LCD_RGB24) - FAR uint8_t *dest = (FAR uint8_t*)buffer; + FAR uint8_t *dest = (FAR uint8_t *)buffer; #elif defined(dest) - FAR uint32_t *dest = (FAR uint32_t*)buffer; + FAR uint32_t *dest = (FAR uint32_t *)buffer; #endif /* Buffer must be provided and aligned to a 16-bit address boundary */ diff --git a/boards/arm/sam34/sam4s-xplained-pro/src/sam_autoleds.c b/boards/arm/sam34/sam4s-xplained-pro/src/sam_autoleds.c index c9f1339a9a2..03b393d7fad 100644 --- a/boards/arm/sam34/sam4s-xplained-pro/src/sam_autoleds.c +++ b/boards/arm/sam34/sam4s-xplained-pro/src/sam_autoleds.c @@ -54,8 +54,8 @@ #ifdef CONFIG_ARCH_LEDS /* If CONFIG_ARCH_LEDs is defined, then NuttX will control the LED on - * board the SAM4S Xplained Pro. The following definitions describe how NuttX - * controls the LEDs: + * board the SAM4S Xplained Pro. + * The following definitions describe how NuttX controls the LEDs: * * SYMBOL Meaning LED state * D9 D10 diff --git a/boards/arm/sama5/sama5d2-xult/src/sam_autoleds.c b/boards/arm/sama5/sama5d2-xult/src/sam_autoleds.c index 1423b11a026..aadf0fe510b 100644 --- a/boards/arm/sama5/sama5d2-xult/src/sam_autoleds.c +++ b/boards/arm/sama5/sama5d2-xult/src/sam_autoleds.c @@ -95,7 +95,7 @@ void board_autoled_on(int led) switch (led) { default: - case 0: /* LED_STARTED, LED_HEAPALLOCATE, LED_IRQSENABLED */ + case 0: /* LED_STARTED, LED_HEAPALLOCATE, LED_IRQSENABLED */ break; /* Leave Green LED off */ case 1: /* LED_STACKCREATED */ diff --git a/boards/arm/sama5/sama5d4-ek/src/sam_sdram.c b/boards/arm/sama5/sama5d4-ek/src/sam_sdram.c index 70e9cd25bdd..45338132989 100644 --- a/boards/arm/sama5/sama5d4-ek/src/sam_sdram.c +++ b/boards/arm/sama5/sama5d4-ek/src/sam_sdram.c @@ -273,9 +273,12 @@ static void sam_config_slaveddr(void) for (ddrport = 1 ; ddrport < 8 ; ddrport++) { - putreg32(0x00ffffff, SAM_MATRIX0_SSR(H64MX_DDR_SLAVE_PORT0 + ddrport)); - putreg32(0x0000000f, SAM_MATRIX0_SRTSR(H64MX_DDR_SLAVE_PORT0 + ddrport)); - putreg32(0x0000ffff, SAM_MATRIX0_SASSR(H64MX_DDR_SLAVE_PORT0 + ddrport)); + putreg32(0x00ffffff, + SAM_MATRIX0_SSR(H64MX_DDR_SLAVE_PORT0 + ddrport)); + putreg32(0x0000000f, + SAM_MATRIX0_SRTSR(H64MX_DDR_SLAVE_PORT0 + ddrport)); + putreg32(0x0000ffff, + SAM_MATRIX0_SASSR(H64MX_DDR_SLAVE_PORT0 + ddrport)); } } @@ -292,9 +295,9 @@ static void sam_config_slaveddr(void) * Per the SAMA5D3-EK User guide: * "Two DDR2/SDRAM (MT47H64M16HR) used as main system memory (256 MByte). * The board includes 2 Gbits of on-board solderedDDR2 (double data rate) - * SDRAM. The footprints can also host two DDR2 (MT47H128M16RT) from Micron® - * for a total of 512 MBytes of DDR2 memory. The memory bus is 32 bits wide - * and operates with a frequency of up to 166 MHz." + * SDRAM. The footprints can also host two DDR2 (MT47H128M16RT) from + * Micron® for a total of 512 MBytes of DDR2 memory. The memory bus is 32 + * bits wide and operates with a frequency of up to 166 MHz." * * From the Atmel Code Example: * MT47H64M16HR : 8 Meg x 16 x 8 banks @@ -377,7 +380,9 @@ void sam_sdram_config(void) MPDDRC_IO_CALIBR_EN_CALIB); putreg32(regval, SAM_MPDDRC_IO_CALIBR); - /* Step 2: Program the features of DDR2-SDRAM device into the Timing Register */ + /* Step 2: Program the features of DDR2-SDRAM device into the Timing + * Register + */ #if defined(CONFIG_SAMA5D4EK_MT47H128M16RT) diff --git a/boards/arm/samd5e5/metro-m4/scripts/nvm.c b/boards/arm/samd5e5/metro-m4/scripts/nvm.c index dfbece20a33..d3c386d227e 100644 --- a/boards/arm/samd5e5/metro-m4/scripts/nvm.c +++ b/boards/arm/samd5e5/metro-m4/scripts/nvm.c @@ -1,3 +1,27 @@ +/**************************************************************************** + * boards/arm/samd5e5/metro-m4/scripts/nvm.c + * + * Licensed to the Apache Software Foundation (ASF) under one or more + * contributor license agreements. See the NOTICE file distributed with + * this work for additional information regarding copyright ownership. The + * ASF licenses this file to you under the Apache License, Version 2.0 (the + * "License"); you may not use this file except in compliance with the + * License. You may obtain a copy of the License at + * + * http://www.apache.org/licenses/LICENSE-2.0 + * + * Unless required by applicable law or agreed to in writing, software + * distributed under the License is distributed on an "AS IS" BASIS, WITHOUT + * WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the + * License for the specific language governing permissions and limitations + * under the License. + * + ****************************************************************************/ + +/**************************************************************************** + * Included Files + ****************************************************************************/ + #include #include @@ -9,6 +33,10 @@ const uint8_t nvm[20] = 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff }; +/**************************************************************************** + * Public Functions + ****************************************************************************/ + int main(int argc, char **argv) { unsigned int csum; diff --git a/boards/arm/samv7/same70-xplained/src/sam_automount.c b/boards/arm/samv7/same70-xplained/src/sam_automount.c index e8534532783..a20c1448bba 100644 --- a/boards/arm/samv7/same70-xplained/src/sam_automount.c +++ b/boards/arm/samv7/same70-xplained/src/sam_automount.c @@ -170,7 +170,8 @@ static int sam_attach(FAR const struct automount_lower_s *lower, * ****************************************************************************/ -static void sam_enable(FAR const struct automount_lower_s *lower, bool enable) +static void sam_enable(FAR const struct automount_lower_s *lower, + bool enable) { FAR const struct sam_automount_config_s *config; FAR struct sam_automount_state_s *state; diff --git a/boards/arm/samv7/same70-xplained/src/sam_sdram.c b/boards/arm/samv7/same70-xplained/src/sam_sdram.c index 3d3453d5749..c77a4f61234 100644 --- a/boards/arm/samv7/same70-xplained/src/sam_sdram.c +++ b/boards/arm/samv7/same70-xplained/src/sam_sdram.c @@ -221,7 +221,9 @@ void sam_sdram_config(void) putreg32(SDRAMC_MDR_SDRAM, SAM_SDRAMC_MDR); - /* 4. A minimum pause of 200 usec is provided to precede any signal toggle. */ + /* 4. A minimum pause of 200 usec is provided to precede any signal + * toggle. + */ up_udelay(200); diff --git a/boards/arm/samv7/same70-xplained/src/sam_xbee.c b/boards/arm/samv7/same70-xplained/src/sam_xbee.c index bb524f42fd2..094d8941757 100644 --- a/boards/arm/samv7/same70-xplained/src/sam_xbee.c +++ b/boards/arm/samv7/same70-xplained/src/sam_xbee.c @@ -266,7 +266,8 @@ static int sam_xbee_devsetup(FAR struct sam_priv_s *priv) ret = xbee_netdev_register(xbee); if (ret < 0) { - wlerr("ERROR: Failed to register the XBee MAC network driver wpan%d: %d\n", + wlerr("ERROR: " + "Failed to register the XBee MAC network driver wpan%d: %d\n", 0, ret); return ret; } diff --git a/boards/arm/samv7/samv71-xult/src/sam_automount.c b/boards/arm/samv7/samv71-xult/src/sam_automount.c index e6b321af6d5..ef7066bd5c7 100644 --- a/boards/arm/samv7/samv71-xult/src/sam_automount.c +++ b/boards/arm/samv7/samv71-xult/src/sam_automount.c @@ -170,7 +170,8 @@ static int sam_attach(FAR const struct automount_lower_s *lower, * ****************************************************************************/ -static void sam_enable(FAR const struct automount_lower_s *lower, bool enable) +static void sam_enable(FAR const struct automount_lower_s *lower, + bool enable) { FAR const struct sam_automount_config_s *config; FAR struct sam_automount_state_s *state; diff --git a/boards/arm/samv7/samv71-xult/src/sam_sdram.c b/boards/arm/samv7/samv71-xult/src/sam_sdram.c index 55e76283f98..b43cee56110 100644 --- a/boards/arm/samv7/samv71-xult/src/sam_sdram.c +++ b/boards/arm/samv7/samv71-xult/src/sam_sdram.c @@ -221,7 +221,9 @@ void sam_sdram_config(void) putreg32(SDRAMC_MDR_SDRAM, SAM_SDRAMC_MDR); - /* 4. A minimum pause of 200 usec is provided to precede any signal toggle. */ + /* 4. A minimum pause of 200 usec is provided to precede any signal + * toggle. + */ up_udelay(200); diff --git a/boards/arm/stm32/axoloti/include/board.h b/boards/arm/stm32/axoloti/include/board.h index b90eaec7141..a977016a6a5 100644 --- a/boards/arm/stm32/axoloti/include/board.h +++ b/boards/arm/stm32/axoloti/include/board.h @@ -58,24 +58,26 @@ * configured at that system clock rate, so the core clock is 168MHz. * * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL configuration - * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) - * PLLM : 8 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled - * SDIO and RNG clock + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 168000000 Determined by PLL configuration + * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator + * output voltage : Scale1 mode Needed for high speed SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for + * USB OTG FS, + * SDIO and RNG clock : Enabled */ /* HSI - 16 MHz RC factory-trimmed @@ -129,8 +131,8 @@ /**************************************************************************** * LED Definitions - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any - * way. The following definitions are used to access individual LEDs. + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. */ /* LED index values for use with board_userled() */ @@ -148,8 +150,8 @@ /**************************************************************************** * Button Definitions - * There are two buttons on the axoloti, one of them is GPIO connected. The other - * is a reset button and is not under software control. + * There are two buttons on the axoloti, one of them is GPIO connected. The + * other is a reset button and is not under software control. */ #define BUTTON_USER 0 diff --git a/boards/arm/stm32/axoloti/src/stm32_adau1961.c b/boards/arm/stm32/axoloti/src/stm32_adau1961.c index 911cd66335b..3d3a55ca98c 100644 --- a/boards/arm/stm32/axoloti/src/stm32_adau1961.c +++ b/boards/arm/stm32/axoloti/src/stm32_adau1961.c @@ -106,14 +106,14 @@ static void adau1961_hw_reset(FAR const struct adau1961_lower_s *lower) static struct stm32_mwinfo_s g_adau1961info = { .lower = - { + { .address = ADAU1961_I2C_ADDRESS, .frequency = I2C_SPEED_FAST, /* 400 kHz */ .mclk = STM32_HSE_FREQUENCY, /* see MCO1 configuration */ .attach = adau1961_attach, .enable = adau1961_enable, .reset = adau1961_hw_reset, - } + } }; /**************************************************************************** @@ -125,8 +125,9 @@ static struct stm32_mwinfo_s g_adau1961info = * * Description: * This function is called by platform-specific, setup logic to configure - * and register the ADAU1961 device. This function will register the driver - * as /dev/audio/pcm[x] where x is determined by the minor device number. + * and register the ADAU1961 device. This function will register the + * driver as /dev/audio/pcm[x] where x is determined by the minor device + * number. * * Input Parameters: * minor - The input device minor number diff --git a/boards/arm/stm32/axoloti/src/stm32_boot.c b/boards/arm/stm32/axoloti/src/stm32_boot.c index 9dbc67d32ea..1a0fc4fcdf2 100644 --- a/boards/arm/stm32/axoloti/src/stm32_boot.c +++ b/boards/arm/stm32/axoloti/src/stm32_boot.c @@ -97,10 +97,11 @@ void stm32_boardinitialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. * ****************************************************************************/ diff --git a/boards/arm/stm32/axoloti/src/stm32_extmem.c b/boards/arm/stm32/axoloti/src/stm32_extmem.c index 08b885dd696..108c6774148 100644 --- a/boards/arm/stm32/axoloti/src/stm32_extmem.c +++ b/boards/arm/stm32/axoloti/src/stm32_extmem.c @@ -247,7 +247,8 @@ int stm32_sdram_initialize(void) /* Step 4: * Wait during the prescribed delay period. Typical delay is around 100 - * μs (refer to the SDRAM datasheet for the required delay after power-up). + * μs (refer to the SDRAM datasheet for the required delay after + * power-up). */ nxsig_usleep(1000); diff --git a/boards/arm/stm32/clicker2-stm32/include/board.h b/boards/arm/stm32/clicker2-stm32/include/board.h index 2c56b5f0f58..53d7c5ac76c 100644 --- a/boards/arm/stm32/clicker2-stm32/include/board.h +++ b/boards/arm/stm32/clicker2-stm32/include/board.h @@ -64,26 +64,29 @@ /* Clocking *****************************************************************/ -/* The Clicker 2 for STM32 board features a 25Hz crystal and 32.768kHz RTC crystal. +/* The Clicker 2 for STM32 board features a 25Hz crystal and 32.768kHz RTC + * crystal. * * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL configuration - * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL) - * PLLM : 25 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 168000000 Determined by PLL configuration + * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 25000000 (STM32_BOARD_XTAL) + * PLLM : 25 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator + * output voltage : Scale1 mode Needed for high speed SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for + * USB OTG FS, : Enabled * SDIO and RNG clock */ @@ -200,14 +203,15 @@ # define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) #endif -/* LED definitions ******************************************************************/ +/* LED definitions **********************************************************/ + /* The Mikroe Clicker2 STM32 has two user controllable LEDs: * * LD1 - PE12, Active high output illuminates * LD2 - PE15, Active high output illuminates * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any - * way. The following definitions are used to access individual LEDs. + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. */ /* LED index values for use with board_userled() */ @@ -221,8 +225,9 @@ #define BOARD_LED1_BIT (1 << BOARD_LED1) #define BOARD_LED2_BIT (1 << BOARD_LED2) -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on board the - * Clicker2 for STM32. The following definitions describe how NuttX controls the LEDs: +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 2 LEDs on + * board the Clicker2 for STM32. + * The following definitions describe how NuttX controls the LEDs: * * SYMBOL Meaning LED state * LED1 LED2 @@ -276,7 +281,7 @@ #define GPIO_USART2_TX GPIO_USART2_TX_2 /* PD5 */ #define GPIO_USART3_RX GPIO_USART3_RX_3 /* PD9 */ -#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 / +#define GPIO_USART3_TX GPIO_USART3_TX_3 /* PD8 */ /* SPI * @@ -319,10 +324,10 @@ #define GPIO_TIM1_CH1OUT GPIO_TIM1_CH1OUT_2 /* PE9 */ #define GPIO_TIM4_CH1OUT GPIO_TIM4_CH1OUT_2 /* PD12 */ -/* DMA Channel/Stream Selections *********************************************/ +/* DMA Channel/Stream Selections ********************************************/ -/* Stream selections are arbitrary for now but might become important in the future - * if we set aside more DMA channels/streams. +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. * * SDIO DMA * DMAMAP_SDIO_1 = Channel 4, Stream 3 diff --git a/boards/arm/stm32/clicker2-stm32/src/stm32_automount.c b/boards/arm/stm32/clicker2-stm32/src/stm32_automount.c index 8dea55688ed..4e2202efb40 100644 --- a/boards/arm/stm32/clicker2-stm32/src/stm32_automount.c +++ b/boards/arm/stm32/clicker2-stm32/src/stm32_automount.c @@ -62,6 +62,7 @@ /**************************************************************************** * Private Types ****************************************************************************/ + /* This structure represents the changeable state of the automounter */ struct stm32_automount_state_s @@ -76,8 +77,8 @@ struct stm32_automount_state_s struct stm32_automount_config_s { - /* This must be first thing in structure so that we can simply cast from struct - * automount_lower_s to struct stm32_automount_config_s + /* This must be first thing in structure so that we can simply cast from + * struct automount_lower_s to struct stm32_automount_config_s */ struct automount_lower_s lower; /* Publicly visible part */ @@ -90,8 +91,9 @@ struct stm32_automount_config_s ****************************************************************************/ static int stm32_attach(FAR const struct automount_lower_s *lower, - automount_handler_t isr, FAR void *arg); -static void stm32_enable(FAR const struct automount_lower_s *lower, bool enable); + automount_handler_t isr, FAR void *arg); +static void stm32_enable(FAR const struct automount_lower_s *lower, + bool enable); static bool stm32_inserted(FAR const struct automount_lower_s *lower); /**************************************************************************** @@ -107,8 +109,10 @@ static const struct stm32_automount_config_s g_mb1_mmcsdconfig = .fstype = CONFIG_CLICKER2_STM32_MB1_MMCSD_AUTOMOUNT_FSTYPE, .blockdev = CONFIG_CLICKER2_STM32_MB1_MMCSD_AUTOMOUNT_BLKDEV, .mountpoint = CONFIG_CLICKER2_STM32_MB1_MMCSD_AUTOMOUNT_MOUNTPOINT, - .ddelay = MSEC2TICK(CONFIG_CLICKER2_STM32_MB1_MMCSD_AUTOMOUNT_DDELAY), - .udelay = MSEC2TICK(CONFIG_CLICKER2_STM32_MB1_MMCSD_AUTOMOUNT_UDELAY), + .ddelay = MSEC2TICK( + CONFIG_CLICKER2_STM32_MB1_MMCSD_AUTOMOUNT_DDELAY), + .udelay = MSEC2TICK( + CONFIG_CLICKER2_STM32_MB1_MMCSD_AUTOMOUNT_UDELAY), .attach = stm32_attach, .enable = stm32_enable, .inserted = stm32_inserted @@ -127,8 +131,10 @@ static const struct stm32_automount_config_s g_mb2_mmcsdconfig = .fstype = CONFIG_CLICKER2_STM32_MB2_MMCSD_AUTOMOUNT_FSTYPE, .blockdev = CONFIG_CLICKER2_STM32_MB2_MMCSD_AUTOMOUNT_BLKDEV, .mountpoint = CONFIG_CLICKER2_STM32_MB2_MMCSD_AUTOMOUNT_MOUNTPOINT, - .ddelay = MSEC2TICK(CONFIG_CLICKER2_STM32_MB2_MMCSD_AUTOMOUNT_DDELAY), - .udelay = MSEC2TICK(CONFIG_CLICKER2_STM32_MB2_MMCSD_AUTOMOUNT_UDELAY), + .ddelay = MSEC2TICK( + CONFIG_CLICKER2_STM32_MB2_MMCSD_AUTOMOUNT_DDELAY), + .udelay = MSEC2TICK( + CONFIG_CLICKER2_STM32_MB2_MMCSD_AUTOMOUNT_UDELAY), .attach = stm32_attach, .enable = stm32_enable, .inserted = stm32_inserted @@ -197,7 +203,8 @@ static int stm32_attach(FAR const struct automount_lower_s *lower, * ****************************************************************************/ -static void stm32_enable(FAR const struct automount_lower_s *lower, bool enable) +static void stm32_enable(FAR const struct automount_lower_s *lower, + bool enable) { FAR const struct stm32_automount_config_s *config; FAR struct stm32_automount_state_s *state; @@ -310,16 +317,16 @@ int stm32_automount_initialize(void) * Name: stm32_automount_event * * Description: - * The HSMCI card detection logic has detected an insertion or removal event. It - * has already scheduled the MMC/SD block driver operations. Now we need to - * schedule the auto-mount event which will occur with a substantial delay to make - * sure that everything has settle down. + * The HSMCI card detection logic has detected an insertion or removal + * event. It has already scheduled the MMC/SD block driver operations. + * Now we need to schedule the auto-mount event which will occur with a + * substantial delay to make sure that everything has settle down. * * Input Parameters: - * slotno - Identifies the MB slot: MB1_MMCSD_SLOTNO or MB2_MMCSD_SLOTNO. There is a - * terminology problem here: Each HSMCI supports two slots, slot A and slot B. - * Only slot A is used. So this is not a really a slot, but an HSCMI peripheral - * number. + * slotno - Identifies the MB slot: MB1_MMCSD_SLOTNO or MB2_MMCSD_SLOTNO. + * There is a terminology problem here: Each HSMCI supports two slots, + * slot A and slot B. Only slot A is used. So this is not a really a + * slot, but an HSCMI peripheral number. * inserted - True if the card is inserted in the slot. False otherwise. * * Returned Value: diff --git a/boards/arm/stm32/cloudctrl/include/board.h b/boards/arm/stm32/cloudctrl/include/board.h index b8894320030..f185ce0e55f 100644 --- a/boards/arm/stm32/cloudctrl/include/board.h +++ b/boards/arm/stm32/cloudctrl/include/board.h @@ -56,7 +56,7 @@ * Pre-processor Definitions ****************************************************************************/ -/* Clocking *************************************************************************/ +/* Clocking *****************************************************************/ /* HSI - 8 MHz RC factory-trimmed * LSI - 40 KHz RC (30-60KHz, uncalibrated) @@ -110,7 +110,8 @@ #define STM32_APB1_TIM6_CLKIN (2*STM32_PCLK1_FREQUENCY) #define STM32_APB1_TIM7_CLKIN (2*STM32_PCLK1_FREQUENCY) -/* MCO output driven by PLL3. From above, we already have PLL3 input frequency as: +/* MCO output driven by PLL3. From above, we already have PLL3 input + * frequency as: * * STM32_PLL_PREDIV2 = 5, 25MHz / 5 => 5MHz */ @@ -120,9 +121,10 @@ # define STM32_PLL_PLL3MUL RCC_CFGR2_PLL3MULx10 /* MCO 5MHz * 10 = 50MHz */ #endif -/* LED definitions ******************************************************************/ -/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any - * way. The following definitions are used to access individual LEDs. +/* LED definitions **********************************************************/ + +/* If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. The following definitions are used to access individual LEDs. */ /* LED index values for use with board_userled() */ @@ -140,8 +142,9 @@ #define BOARD_LED3_BIT (1 << BOARD_LED3) #define BOARD_LED4_BIT (1 << BOARD_LED4) -/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on board the - * STM3240G-EVAL. The following definitions describe how NuttX controls the LEDs: +/* If CONFIG_ARCH_LEDs is defined, then NuttX will control the 4 LEDs on + * board the STM3240G-EVAL. + * The following definitions describe how NuttX controls the LEDs: */ #define LED_STARTED 0 /* LED1 */ @@ -153,7 +156,8 @@ #define LED_ASSERTION 6 /* LED1 + LED2 + LED3 */ #define LED_PANIC 7 /* N/C + N/C + N/C + LED4 */ -/* Button definitions ***************************************************************/ +/* Button definitions *******************************************************/ + /* The STM3240G-EVAL supports three buttons: */ #define BUTTON_KEY1 0 /* Name printed on board */ @@ -177,16 +181,17 @@ #define NUM_RELAYS 2 -/* Pin selections ******************************************************************/ +/* Pin selections ***********************************************************/ + /* Ethernet * - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * PN NAME SIGNAL NOTES - * -- ---- -------------- ---------------------------------------------------------- - * 24 PA1 MII_RX_CLK Ethernet PHY NOTE: Despite the MII labeling of these - * RMII_REF_CLK Ethernet PHY signals, the DM916AEP is actually configured - * 25 PA2 MII_MDIO Ethernet PHY to work in RMII mode. - * 48 PB11 MII_TX_EN Ethernet PHY + * -- ---- -------------- --------------------------------------------------- + * 24 PA1 MII_RX_CLK Ethernet PHY NOTE: Despite the MII labeling of + * RMII_REF_CLK Ethernet PHY these signals, the DM916AEP is + * 25 PA2 MII_MDIO Ethernet PHY actually configured to work in + * 48 PB11 MII_TX_EN Ethernet PHY RMII mode. * 51 PB12 MII_TXD0 Ethernet PHY * 52 PB13 MII_TXD1 Ethernet PHY * 16 PC1 MII_MDC Ethernet PHY @@ -216,9 +221,9 @@ /* USB * - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * PN NAME SIGNAL NOTES - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * 68 PA9 USB_VBUS MINI-USB-AB. JP3 * 69 PA10 USB_ID MINI-USB-AB. JP5 * 70 PA11 USB_DM MINI-USB-AB @@ -228,9 +233,9 @@ /* UARTS/USARTS * - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * PN NAME SIGNAL NOTES - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * 68 PA9 USART1_TX MAX3232 to CN5. Requires CONFIG_STM32_USART1_REMAP * 69 PA10 USART1_RX MAX3232 to CN5. Requires CONFIG_STM32_USART1_REMAP * 86 PD5 USART2_TX MAX3232 to CN6. Requires CONFIG_STM32_USART2_REMAP @@ -249,20 +254,23 @@ /* SPI * - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * PN NAME SIGNAL NOTES - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * 30 PA5 SPI1_SCK To the SD card, SPI FLASH. * Requires !CONFIG_STM32_SPI1_REMAP * 31 PA6 SPI1_MISO To the SD card, SPI FLASH. * Requires !CONFIG_STM32_SPI1_REMAP * 32 PA7 SPI1_MOSI To the SD card, SPI FLASH. * Requires !CONFIG_STM32_SPI1_REMAP - * 78 PC10 SPI3_SCK To TFT LCD (CN13), the NRF24L01 2.4G wireless module. + * 78 PC10 SPI3_SCK To TFT LCD (CN13), + * the NRF24L01 2.4G wireless module. * Requires CONFIG_STM32_SPI3_REMAP. - * 79 PC11 SPI3_MISO To TFT LCD (CN13), the NRF24L01 2.4G wireless module. + * 79 PC11 SPI3_MISO To TFT LCD (CN13), + * the NRF24L01 2.4G wireless module. * Requires CONFIG_STM32_SPI3_REMAP. - * 80 PC12 SPI3_MOSI To TFT LCD (CN13), the NRF24L01 2.4G wireless module. + * 80 PC12 SPI3_MOSI To TFT LCD (CN13), + * the NRF24L01 2.4G wireless module. * Requires CONFIG_STM32_SPI3_REMAP. */ @@ -276,18 +284,18 @@ /* DAC * - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * PN NAME SIGNAL NOTES - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * 29 PA4 DAC_OUT1 To CON5(CN14) * 30 PA5 DAC_OUT2 To CON5(CN14). JP10 */ /* ADC * - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * PN NAME SIGNAL NOTES - * -- ---- -------------- ---------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * 35 PB0 ADC_IN1 GPIO_ADC12_IN8. To CON5(CN14) * 36 PB1 ADC_IN2 GPIO_ADC12_IN9. To CON5(CN14) * 15 PC0 POTENTIO_METER GPIO_ADC12_IN10 @@ -302,7 +310,8 @@ #undef EXTERN #if defined(__cplusplus) #define EXTERN extern "C" -extern "C" { +extern "C" +{ #else #define EXTERN extern #endif @@ -315,10 +324,11 @@ extern "C" { * Name: stm32_lcdclear * * Description: - * This is a non-standard LCD interface just for the Shenzhou board. Because - * of the various rotations, clearing the display in the normal way by writing a - * sequences of runs that covers the entire display can be very slow. Here the - * display is cleared by simply setting all GRAM memory to the specified color. + * This is a non-standard LCD interface just for the Shenzhou board. + * Because of the various rotations, clearing the display in the normal + * way by writing a sequences of runs that covers the entire display can + * be very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. * ****************************************************************************/ diff --git a/boards/arm/stm32/cloudctrl/src/stm32_adc.c b/boards/arm/stm32/cloudctrl/src/stm32_adc.c index 8791f855527..c99e112ebe0 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_adc.c +++ b/boards/arm/stm32/cloudctrl/src/stm32_adc.c @@ -58,7 +58,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Configuration ********************************************************************/ + +/* Configuration ************************************************************/ + /* Up to 3 ADC interfaces are supported */ #if STM32_NADC < 3 @@ -86,8 +88,8 @@ * Private Data ****************************************************************************/ -/* Identifying number of each ADC channel. The only internal signal for ADC testing - * is the potentiometer input: +/* Identifying number of each ADC channel. The only internal signal for ADC + * testing is the potentiometer input: * * ADC1_IN10(PC0) Potentiometer * @@ -98,11 +100,19 @@ */ #ifdef CONFIG_STM32_ADC1 -static const uint8_t g_chanlist[ADC1_NCHANNELS] = {10}; //{10, 8, 9}; +static const uint8_t g_chanlist[ADC1_NCHANNELS] = +{ + 10 /* {10, 8, 9}; */ +}; /* Configurations of pins used by each ADC channel */ -static const uint32_t g_pinlist[ADC1_NCHANNELS] = {GPIO_ADC12_IN10}; //{GPIO_ADC12_IN10, GPIO_ADC12_IN8, GPIO_ADC12_IN9}; +static const uint32_t g_pinlist[ADC1_NCHANNELS] = +{ + GPIO_ADC12_IN10 +}; + +/* {GPIO_ADC12_IN10, GPIO_ADC12_IN8, GPIO_ADC12_IN9}; */ #endif /**************************************************************************** diff --git a/boards/arm/stm32/cloudctrl/src/stm32_appinit.c b/boards/arm/stm32/cloudctrl/src/stm32_appinit.c index 714c07d6b7c..d4707c9753a 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_appinit.c +++ b/boards/arm/stm32/cloudctrl/src/stm32_appinit.c @@ -53,6 +53,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ /* Assume that we support everything until convinced otherwise */ @@ -141,8 +142,8 @@ int board_app_initialize(uintptr_t arg) } #endif - /* Initialize USB host operation. stm32_usbhost_initialize() starts a thread - * will monitor for USB connection and disconnection events. + /* Initialize USB host operation. stm32_usbhost_initialize() starts a + * thread will monitor for USB connection and disconnection events. */ #ifdef HAVE_USBHOST diff --git a/boards/arm/stm32/cloudctrl/src/stm32_autoleds.c b/boards/arm/stm32/cloudctrl/src/stm32_autoleds.c index 4618f7694a9..98ce7e7d091 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_autoleds.c +++ b/boards/arm/stm32/cloudctrl/src/stm32_autoleds.c @@ -146,28 +146,28 @@ static int led_pm_prepare(struct pm_callback_s *cb, int domain, static const uint16_t g_ledbits[8] = { (LED_STARTED_ON_SETBITS | LED_STARTED_ON_CLRBITS | - LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), + LED_STARTED_OFF_SETBITS | LED_STARTED_OFF_CLRBITS), (LED_HEAPALLOCATE_ON_SETBITS | LED_HEAPALLOCATE_ON_CLRBITS | - LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), + LED_HEAPALLOCATE_OFF_SETBITS | LED_HEAPALLOCATE_OFF_CLRBITS), (LED_IRQSENABLED_ON_SETBITS | LED_IRQSENABLED_ON_CLRBITS | - LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), + LED_IRQSENABLED_OFF_SETBITS | LED_IRQSENABLED_OFF_CLRBITS), (LED_STACKCREATED_ON_SETBITS | LED_STACKCREATED_ON_CLRBITS | - LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), + LED_STACKCREATED_OFF_SETBITS | LED_STACKCREATED_OFF_CLRBITS), (LED_INIRQ_ON_SETBITS | LED_INIRQ_ON_CLRBITS | - LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), + LED_INIRQ_OFF_SETBITS | LED_INIRQ_OFF_CLRBITS), (LED_SIGNAL_ON_SETBITS | LED_SIGNAL_ON_CLRBITS | - LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), + LED_SIGNAL_OFF_SETBITS | LED_SIGNAL_OFF_CLRBITS), (LED_ASSERTION_ON_SETBITS | LED_ASSERTION_ON_CLRBITS | - LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), + LED_ASSERTION_OFF_SETBITS | LED_ASSERTION_OFF_CLRBITS), (LED_PANIC_ON_SETBITS | LED_PANIC_ON_CLRBITS | - LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) + LED_PANIC_OFF_SETBITS | LED_PANIC_OFF_CLRBITS) }; #ifdef CONFIG_PM @@ -213,7 +213,6 @@ static inline void led_clrbits(unsigned int clrbits) { stm32_gpiowrite(GPIO_LED4, true); } - } /**************************************************************************** @@ -247,7 +246,6 @@ static inline void led_setbits(unsigned int setbits) { stm32_gpiowrite(GPIO_LED4, false); } - } /**************************************************************************** @@ -282,35 +280,30 @@ static void led_pm_notify(struct pm_callback_s *cb, int domain, case(PM_NORMAL): { /* Restore normal LEDs operation */ - } break; case(PM_IDLE): { /* Entering IDLE mode - Turn leds off */ - } break; case(PM_STANDBY): { /* Entering STANDBY mode - Logic for PM_STANDBY goes here */ - } break; case(PM_SLEEP): { /* Entering SLEEP mode - Logic for PM_SLEEP goes here */ - } break; default: { /* Should not get here */ - } break; } @@ -352,12 +345,12 @@ static int led_pm_prepare(struct pm_callback_s *cb, int domain, #ifdef CONFIG_ARCH_LEDS void board_autoled_initialize(void) { - /* Configure LED1-4 GPIOs for output */ + /* Configure LED1-4 GPIOs for output */ - stm32_configgpio(GPIO_LED1); - stm32_configgpio(GPIO_LED2); - stm32_configgpio(GPIO_LED3); - stm32_configgpio(GPIO_LED4); + stm32_configgpio(GPIO_LED1); + stm32_configgpio(GPIO_LED2); + stm32_configgpio(GPIO_LED3); + stm32_configgpio(GPIO_LED4); } /**************************************************************************** @@ -389,7 +382,7 @@ void up_ledpminitialize(void) int ret = pm_register(&g_ledscb); if (ret != OK) - { + { board_autoled_on(LED_ASSERTION); } } diff --git a/boards/arm/stm32/cloudctrl/src/stm32_boot.c b/boards/arm/stm32/cloudctrl/src/stm32_boot.c index bdd008b7799..17bacc5a1b9 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_boot.c +++ b/boards/arm/stm32/cloudctrl/src/stm32_boot.c @@ -64,16 +64,17 @@ * Name: stm32_boardinitialize * * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. * ****************************************************************************/ void stm32_boardinitialize(void) { - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function - * stm32_spidev_initialize() has been brought into the link. + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. */ #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI3) @@ -84,8 +85,8 @@ void stm32_boardinitialize(void) #endif /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been brought - * into the build. + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. */ #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) diff --git a/boards/arm/stm32/cloudctrl/src/stm32_relays.c b/boards/arm/stm32/cloudctrl/src/stm32_relays.c index c5874a1224a..b8aa9970d3e 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_relays.c +++ b/boards/arm/stm32/cloudctrl/src/stm32_relays.c @@ -195,7 +195,7 @@ void up_relaysinit(void) g_relays_init = true; } -void relays_setstat(int relays,bool stat) +void relays_setstat(int relays, bool stat) { if ((unsigned)relays < NUM_RELAYS) { @@ -227,7 +227,7 @@ void relays_setstats(uint32_t relays_stat) for (i = 0; i < NUM_RELAYS; i++) { - relays_setstat(i, (relays_stat & (1<0) + if (mdelay > 0) { if (relays_getstat(relays)) { relays_setstat(relays, false); - nxsig_usleep(RELAYS_MIN_RESET_TIME*1000*1000); + nxsig_usleep(RELAYS_MIN_RESET_TIME * 1000 * 1000); } - relays_setstat(relays,true); - nxsig_usleep(mdelay*100*1000); + relays_setstat(relays, true); + nxsig_usleep(mdelay * 100 * 1000); relays_setstat(relays, false); } } diff --git a/boards/arm/stm32/cloudctrl/src/stm32_spi.c b/boards/arm/stm32/cloudctrl/src/stm32_spi.c index 0096a82d9c2..c4f1ee2a76d 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_spi.c +++ b/boards/arm/stm32/cloudctrl/src/stm32_spi.c @@ -91,31 +91,34 @@ void weak_function stm32_spidev_initialize(void) * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); /* SPI1 connects to the SD CARD and to the SPI FLASH */ @@ -129,16 +132,16 @@ void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) { - return SPI_STATUS_PRESENT; } #endif #ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); - + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) diff --git a/boards/arm/stm32/cloudctrl/src/stm32_usbmsc.c b/boards/arm/stm32/cloudctrl/src/stm32_usbmsc.c index b36762d43a5..cc85e8f5937 100644 --- a/boards/arm/stm32/cloudctrl/src/stm32_usbmsc.c +++ b/boards/arm/stm32/cloudctrl/src/stm32_usbmsc.c @@ -53,6 +53,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ #ifndef CONFIG_SYSTEM_USBMSC_DEVMINOR1 @@ -74,7 +75,8 @@ int board_usbmsc_initialize(int port) { /* If system/usbmsc is built as an NSH command, then SD slot should - * already have been initized in board_app_initialize() (see stm32_appinit.c). + * already have been initized in board_app_initialize() + * (see stm32_appinit.c). * In this case, there is nothing further to be done here. */ diff --git a/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c b/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c index efa3cf50854..250c48749ac 100644 --- a/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c +++ b/boards/arm/stm32/hymini-stm32v/src/stm32_r61505u.c @@ -85,7 +85,10 @@ #define LCD_BL_TIMER_PERIOD 8999 -/* LCD is connected to the FSMC_Bank1_NOR/SRAM1 and NE1 is used as ship select signal */ +/* LCD is connected to the FSMC_Bank1_NOR/SRAM1 and NE1 is used as ship + * select signal + */ + /* RS <==> A16 */ #define LCD_REG (*((volatile unsigned short *) 0x60000000)) /* RS = 0 */ @@ -132,17 +135,18 @@ static void lcd_clear(uint16_t color); /* LCD Data Transfer Methods */ -static int lcd_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffer, - size_t npixels); -static int lcd_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, - size_t npixels); +static int lcd_putrun(fb_coord_t row, fb_coord_t col, + FAR const uint8_t *buffer, size_t npixels); +static int lcd_getrun(fb_coord_t row, fb_coord_t col, + FAR uint8_t *buffer, size_t npixels); /* LCD Configuration */ static int lcd_getvideoinfo(FAR struct lcd_dev_s *dev, - FAR struct fb_videoinfo_s *vinfo); -static int lcd_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno, - FAR struct lcd_planeinfo_s *pinfo); + FAR struct fb_videoinfo_s *vinfo); +static int lcd_getplaneinfo(FAR struct lcd_dev_s *dev, + unsigned int planeno, + FAR struct lcd_planeinfo_s *pinfo); /* LCD RGB Mapping */ @@ -161,7 +165,8 @@ static int lcd_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno, static int lcd_getpower(struct lcd_dev_s *dev); static int lcd_setpower(struct lcd_dev_s *dev, int power); static int lcd_getcontrast(struct lcd_dev_s *dev); -static int lcd_setcontrast(struct lcd_dev_s *dev, unsigned int contrast); +static int lcd_setcontrast(struct lcd_dev_s *dev, + unsigned int contrast); /* Initialization (LCD ctrl / backlight) */ @@ -187,9 +192,9 @@ static const uint16_t fsmc_gpios[] = /* D0... D15 */ GPIO_NPS_D0, GPIO_NPS_D1, GPIO_NPS_D2, GPIO_NPS_D3, - GPIO_NPS_D4, GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7, GPIO_NPS_D8, GPIO_NPS_D9, - GPIO_NPS_D10, GPIO_NPS_D11, GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, - GPIO_NPS_D15, + GPIO_NPS_D4, GPIO_NPS_D5, GPIO_NPS_D6, GPIO_NPS_D7, + GPIO_NPS_D8, GPIO_NPS_D9, GPIO_NPS_D10, GPIO_NPS_D11, + GPIO_NPS_D12, GPIO_NPS_D13, GPIO_NPS_D14, GPIO_NPS_D15, /* NOE, NWE */ @@ -229,10 +234,10 @@ static const struct fb_videoinfo_s g_videoinfo = static const struct lcd_planeinfo_s g_planeinfo = { - .putrun = lcd_putrun, /* Put a run into LCD memory */ - .getrun = lcd_getrun, /* Get a run from LCD memory */ - .buffer = (uint8_t*) g_runbuffer, /* Run scratch buffer */ - .bpp = LCD_BPP, /* Bits-per-pixel */ + .putrun = lcd_putrun, /* Put a run into LCD memory */ + .getrun = lcd_getrun, /* Get a run from LCD memory */ + .buffer = (uint8_t *) g_runbuffer, /* Run scratch buffer */ + .bpp = LCD_BPP, /* Bits-per-pixel */ }; /* This is the standard, NuttX LCD driver object */ @@ -246,6 +251,7 @@ static struct mylcd_dev_s g_lcddev = .getplaneinfo = lcd_getplaneinfo, /* LCD RGB Mapping -- Not supported */ + /* Cursor Controls -- Not supported */ /* LCD Specific Controls */ @@ -306,7 +312,7 @@ static void stm32_selectlcd(void) /* Bank1 NOR/SRAM timing register configuration */ - putreg32(FSMC_BTR_ADDSET(2) | FSMC_BTR_ADDHLD(0) |FSMC_BTR_DATAST(2) | + putreg32(FSMC_BTR_ADDSET(2) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(2) | FSMC_BTR_BUSTURN(0) | FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | FSMC_BTR_ACCMODA, STM32_FSMC_BTR1); @@ -413,15 +419,15 @@ static void lcd_setcursor(unsigned int x, unsigned int y) x = (LCD_XRES - 1) - x; y = (LCD_YRES - 1) - y; # endif - write_reg(0x20,x); /* Row */ - write_reg(0x21,y); /* Line */ + write_reg(0x20, x); /* Row */ + write_reg(0x21, y); /* Line */ #endif #if defined(CONFIG_LCD_LANDSCAPE) y = (LCD_YRES - 1) - y; - write_reg(0x20,x); /* Row */ - write_reg(0x21,y); /* Line */ + write_reg(0x20, x); /* Row */ + write_reg(0x21, y); /* Line */ #endif } @@ -439,11 +445,12 @@ static void lcd_setcursor(unsigned int x, unsigned int y) * ****************************************************************************/ -static int lcd_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffer, +static int lcd_putrun(fb_coord_t row, fb_coord_t col, + FAR const uint8_t *buffer, size_t npixels) { int i; - FAR const uint16_t *src = (FAR const uint16_t*) buffer; + FAR const uint16_t *src = (FAR const uint16_t *) buffer; /* Buffer must be provided and aligned to a 16-bit address boundary */ @@ -479,7 +486,7 @@ static int lcd_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffer, static int lcd_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, size_t npixels) { - FAR uint16_t *dest = (FAR uint16_t*) buffer; + FAR uint16_t *dest = (FAR uint16_t *) buffer; int i; /* Buffer must be provided and aligned to a 16-bit address boundary */ @@ -516,7 +523,8 @@ static int lcd_getvideoinfo(FAR struct lcd_dev_s *dev, { DEBUGASSERT(dev && vinfo); ginfo("fmt: %d xres: %d yres: %d nplanes: %d\n", - g_videoinfo.fmt, g_videoinfo.xres, g_videoinfo.yres, g_videoinfo.nplanes); + g_videoinfo.fmt, g_videoinfo.xres, + g_videoinfo.yres, g_videoinfo.nplanes); memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); return OK; @@ -544,7 +552,8 @@ static int lcd_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno, * Name: lcd_getpower * * Description: - * Get the LCD panel power status (0: full off - CONFIG_LCD_MAXPOWER: full on). On + * Get the LCD panel power status + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On * backlit LCDs, this setting may correspond to the backlight setting. * ****************************************************************************/ @@ -559,7 +568,8 @@ static int lcd_getpower(struct lcd_dev_s *dev) * Name: lcd_setpower * * Description: - * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: full on). + * Enable/disable LCD panel power + * (0: full off - CONFIG_LCD_MAXPOWER: full on). * Used here to set pwm duty on timer used for backlight. * ****************************************************************************/ @@ -586,7 +596,8 @@ static int lcd_setpower(struct lcd_dev_s *dev, int power) * maximum power setting. */ - duty = ((uint32_t)LCD_BL_TIMER_PERIOD * (uint32_t)power) / CONFIG_LCD_MAXPOWER; + duty = ((uint32_t)LCD_BL_TIMER_PERIOD * (uint32_t)power) / + CONFIG_LCD_MAXPOWER; if (duty >= LCD_BL_TIMER_PERIOD) { duty = LCD_BL_TIMER_PERIOD - 1; @@ -647,93 +658,93 @@ static int lcd_setcontrast(struct lcd_dev_s *dev, unsigned int contrast) static inline void lcd_initialize(void) { - /* Second release on 3/5 ,luminance is acceptable,water wave appear during camera - * preview + /* Second release on 3/5 ,luminance is acceptable,water wave appear + * during camera preview */ - write_reg(0x07,0x0000); - up_mdelay(5); /* Delay 50 ms */ - write_reg(0x12,0x011C); /* Why need to set several times? */ - write_reg(0xA4,0x0001); /* NVM */ - write_reg(0x08,0x000F); - write_reg(0x0A,0x0008); - write_reg(0x0D,0x0008); + write_reg(0x07, 0x0000); + up_mdelay(5); /* Delay 50 ms */ + write_reg(0x12, 0x011c); /* Why need to set several times? */ + write_reg(0xa4, 0x0001); /* NVM */ + write_reg(0x08, 0x000f); + write_reg(0x0a, 0x0008); + write_reg(0x0d, 0x0008); /* GAMMA CONTROL */ - write_reg(0x30,0x0707); - write_reg(0x31,0x0007); - write_reg(0x32,0x0603); - write_reg(0x33,0x0700); - write_reg(0x34,0x0202); - write_reg(0x35,0x0002); - write_reg(0x36,0x1F0F); - write_reg(0x37,0x0707); - write_reg(0x38,0x0000); - write_reg(0x39,0x0000); - write_reg(0x3A,0x0707); - write_reg(0x3B,0x0000); - write_reg(0x3C,0x0007); - write_reg(0x3D,0x0000); - up_mdelay(5); /* Delay 50 ms */ - write_reg(0x07,0x0001); - write_reg(0x17,0x0001); /* Power supply startup enable */ - up_mdelay(5); /* Delay 50 ms */ + write_reg(0x30, 0x0707); + write_reg(0x31, 0x0007); + write_reg(0x32, 0x0603); + write_reg(0x33, 0x0700); + write_reg(0x34, 0x0202); + write_reg(0x35, 0x0002); + write_reg(0x36, 0x1f0f); + write_reg(0x37, 0x0707); + write_reg(0x38, 0x0000); + write_reg(0x39, 0x0000); + write_reg(0x3a, 0x0707); + write_reg(0x3b, 0x0000); + write_reg(0x3c, 0x0007); + write_reg(0x3d, 0x0000); + up_mdelay(5); /* Delay 50 ms */ + write_reg(0x07, 0x0001); + write_reg(0x17, 0x0001); /* Power supply startup enable */ + up_mdelay(5); /* Delay 50 ms */ /* Power control */ - write_reg(0x10,0x17A0); - write_reg(0x11,0x0217); /* Feference voltage VC[2:0] Vciout = 1.00*Vcivl */ - write_reg(0x12,0x011E); /* Vreg1out = Vcilvl*1.80 is it the same as Vgama1out ? */ - write_reg(0x13,0x0F00); /* VDV[4:0]-->VCOM Amplitude VcomL = VcomH - Vcom Ampl */ - write_reg(0x2A,0x0000); - write_reg(0x29,0x000A); /* Vcomh = VCM1[4:0]*Vreg1out gate source voltage?? */ - write_reg(0x12,0x013E); /* Power supply on */ + write_reg(0x10, 0x17a0); + write_reg(0x11, 0x0217); /* Feference voltage VC[2:0] Vciout = 1.00*Vcivl */ + write_reg(0x12, 0x011e); /* Vreg1out = Vcilvl*1.80 is it the same as Vgama1out ? */ + write_reg(0x13, 0x0f00); /* VDV[4:0]-->VCOM Amplitude VcomL = VcomH - Vcom Ampl */ + write_reg(0x2a, 0x0000); + write_reg(0x29, 0x000a); /* Vcomh = VCM1[4:0]*Vreg1out gate source voltage?? */ + write_reg(0x12, 0x013e); /* Power supply on */ /* Coordinates Control */ - write_reg(0x50,0x0000); - write_reg(0x51,0x00EF); - write_reg(0x52,0x0000); - write_reg(0x53,0x013F); + write_reg(0x50, 0x0000); + write_reg(0x51, 0x00ef); + write_reg(0x52, 0x0000); + write_reg(0x53, 0x013f); /* Panel Image Control */ - write_reg(0x60,0x2700); - write_reg(0x61,0x0001); - write_reg(0x6A,0x0000); - write_reg(0x80,0x0000); + write_reg(0x60, 0x2700); + write_reg(0x61, 0x0001); + write_reg(0x6a, 0x0000); + write_reg(0x80, 0x0000); /* Partial Image Control */ - write_reg(0x81,0x0000); - write_reg(0x82,0x0000); - write_reg(0x83,0x0000); - write_reg(0x84,0x0000); - write_reg(0x85,0x0000); + write_reg(0x81, 0x0000); + write_reg(0x82, 0x0000); + write_reg(0x83, 0x0000); + write_reg(0x84, 0x0000); + write_reg(0x85, 0x0000); /* Panel Interface Control */ - write_reg(0x90,0x0013); /* Frequency */ - write_reg(0x92,0x0300); - write_reg(0x93,0x0005); - write_reg(0x95,0x0000); - write_reg(0x97,0x0000); - write_reg(0x98,0x0000); + write_reg(0x90, 0x0013); /* Frequency */ + write_reg(0x92, 0x0300); + write_reg(0x93, 0x0005); + write_reg(0x95, 0x0000); + write_reg(0x97, 0x0000); + write_reg(0x98, 0x0000); - write_reg(0x01,0x0100); - write_reg(0x02,0x0700); - write_reg(0x03,0x1030); - write_reg(0x04,0x0000); - write_reg(0x0C,0x0000); - write_reg(0x0F,0x0000); - write_reg(0x20,0x0000); - write_reg(0x21,0x0000); - write_reg(0x07,0x0021); + write_reg(0x01, 0x0100); + write_reg(0x02, 0x0700); + write_reg(0x03, 0x1030); + write_reg(0x04, 0x0000); + write_reg(0x0c, 0x0000); + write_reg(0x0f, 0x0000); + write_reg(0x20, 0x0000); + write_reg(0x21, 0x0000); + write_reg(0x07, 0x0021); up_mdelay(20); /* Delay 200 ms */ - write_reg(0x07,0x0061); + write_reg(0x07, 0x0061); up_mdelay(20); /* Delay 200 ms */ - write_reg(0x07,0x0173); + write_reg(0x07, 0x0173); up_mdelay(20); /* Delay 200 ms */ } @@ -806,7 +817,10 @@ static void lcd_backlight(void) /* Set the capture compare register value (50% duty) */ - // FIXME should be set to 0 (appl needs to call setpower to change it) + /* FIXME should be set to 0 + * (appl needs to call setpower to change it) + */ + g_lcddev.power = (CONFIG_LCD_MAXPOWER + 1) / 2; putreg16((LCD_BL_TIMER_PERIOD + 1) / 2, STM32_TIM3_CCR2); @@ -814,7 +828,7 @@ static void lcd_backlight(void) ccer &= !ATIM_CCER_CC2P; - /* Enable channel 2*/ + /* Enable channel 2 */ ccer |= ATIM_CCER_CC2E; @@ -827,7 +841,7 @@ static void lcd_backlight(void) modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_ARPE); - /* Enable Backlight Timer !!!!*/ + /* Enable Backlight Timer !!!! */ modifyreg16(STM32_TIM3_CR1, 0, ATIM_CR1_CEN); @@ -864,9 +878,9 @@ static void lcd_backlight(void) * Name: board_lcd_initialize * * Description: - * Initialize the LCD video hardware. The initial state of the LCD is fully - * initialized, display memory cleared, and the LCD ready to use, but with the power - * setting at 0 (full off). + * Initialize the LCD video hardware. The initial state of the LCD is + * fully initialized, display memory cleared, and the LCD ready to use, + * but with the power setting at 0 (full off). * ****************************************************************************/ @@ -913,8 +927,8 @@ int board_lcd_initialize(void) * Name: board_lcd_getdev * * Description: - * Return a a reference to the LCD object for the specified LCD. This allows support - * for multiple LCD devices. + * Return a a reference to the LCD object for the specified LCD. + * This allows support for multiple LCD devices. * ****************************************************************************/ diff --git a/boards/arm/stm32/maple/include/board.h b/boards/arm/stm32/maple/include/board.h index aa356b4ab1d..825d14a72cc 100644 --- a/boards/arm/stm32/maple/include/board.h +++ b/boards/arm/stm32/maple/include/board.h @@ -54,13 +54,15 @@ * Pre-processor Definitions ****************************************************************************/ -/* Clocking *************************************************************************/ +/* Clocking *****************************************************************/ /* On-board crystal frequency is 8MHz (HSE) */ #define STM32_BOARD_XTAL 8000000ul -/* PLL source is HSE/1, PLL multipler is 9: PLL frequency is 8MHz (XTAL) x 9 = 72MHz */ +/* PLL source is HSE/1, PLL multipler is 9: + * PLL frequency is 8MHz (XTAL) x 9 = 72MHz + */ #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC #define STM32_CFGR_PLLXTPRE 0 @@ -109,7 +111,8 @@ /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. - * Note: TIM1,8 are on APB2, others on APB1 */ + * Note: TIM1,8 are on APB2, others on APB1 + */ #define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY @@ -150,9 +153,10 @@ # define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) #endif -/* LED definitions ******************************************************************/ +/* LED definitions **********************************************************/ /* The board has only one controllable LED */ + #define LED_STARTED 0 /* No LEDs */ #define LED_HEAPALLOCATE 1 /* LED1 on */ #define LED_IRQSENABLED 2 /* LED2 on */ diff --git a/boards/arm/stm32/maple/src/stm32_boot.c b/boards/arm/stm32/maple/src/stm32_boot.c index 1c60dd87c10..7db2fd0c47c 100644 --- a/boards/arm/stm32/maple/src/stm32_boot.c +++ b/boards/arm/stm32/maple/src/stm32_boot.c @@ -64,9 +64,10 @@ * Name: stm32_boardinitialize * * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. * ****************************************************************************/ @@ -78,8 +79,8 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function - * stm32_spidev_initialize() has been brought into the link. + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. */ #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) @@ -87,8 +88,8 @@ void stm32_boardinitialize(void) #endif /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been brought - * into the build. + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. */ #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) diff --git a/boards/arm/stm32/maple/src/stm32_lcd.c b/boards/arm/stm32/maple/src/stm32_lcd.c index 09c66083894..09a0568fe02 100644 --- a/boards/arm/stm32/maple/src/stm32_lcd.c +++ b/boards/arm/stm32/maple/src/stm32_lcd.c @@ -62,6 +62,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ #define EXTCOMIN_FREQ 24 diff --git a/boards/arm/stm32/maple/src/stm32_leds.c b/boards/arm/stm32/maple/src/stm32_leds.c index f91d590f96a..c0a264d41a5 100644 --- a/boards/arm/stm32/maple/src/stm32_leds.c +++ b/boards/arm/stm32/maple/src/stm32_leds.c @@ -98,6 +98,7 @@ void board_autoled_on(int led) break; case LED_PANIC: + /* For panic state, the LED is blinking */ set_led(true); @@ -120,6 +121,7 @@ void board_autoled_off(int led) { case LED_STARTED: case LED_PANIC: + /* For panic state, the LED is blinking */ set_led(false); diff --git a/boards/arm/stm32/maple/src/stm32_spi.c b/boards/arm/stm32/maple/src/stm32_spi.c index d24a361039d..eec64e5b06e 100644 --- a/boards/arm/stm32/maple/src/stm32_spi.c +++ b/boards/arm/stm32/maple/src/stm32_spi.c @@ -82,22 +82,23 @@ void weak_function stm32_spidev_initialize(void) * Name: stm32_spi1/2select and stm32_spi1/2status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * @@ -107,7 +108,8 @@ void weak_function stm32_spidev_initialize(void) void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); # if defined(CONFIG_LCD_SHARP_MEMLCD) if (devid == SPIDEV_DISPLAY(0)) @@ -122,7 +124,8 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) return 0; } -int stm32_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi1cmddata(FAR struct spi_dev_s *dev, + uint32_t devid, bool cmd) { return -ENODEV; } @@ -139,7 +142,8 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) return 0; } -int stm32_spi1cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) +int stm32_spi1cmddata(FAR struct spi_dev_s *dev, + uint32_t devid, bool cmd) { return -ENODEV; } diff --git a/boards/arm/stm32/maple/src/stm32_usbdev.c b/boards/arm/stm32/maple/src/stm32_usbdev.c index a3e3d0f9331..96444ba62e7 100644 --- a/boards/arm/stm32/maple/src/stm32_usbdev.c +++ b/boards/arm/stm32/maple/src/stm32_usbdev.c @@ -85,11 +85,11 @@ void stm32_usbinitialize(void) * Name: stm32_usbpullup * * Description: - * If USB is supported and the board supports a pullup via GPIO (for USB software - * connect and disconnect), then the board software must provide stm32_pullup. - * See include/nuttx/usb/usbdev.h for additional description of this method. - * Alternatively, if no pull-up GPIO the following EXTERN can be redefined to be - * NULL. + * If USB is supported and the board supports a pullup via GPIO (for USB + * software connect and disconnect), then the board software must provide + * stm32_pullup. See include/nuttx/usb/usbdev.h for additional description + * of this method. Alternatively, if no pull-up GPIO the following EXTERN + * can be redefined to be NULL. * ****************************************************************************/ @@ -104,10 +104,10 @@ int stm32_usbpullup(FAR struct usbdev_s *dev, bool enable) * Name: stm32_usbsuspend * * Description: - * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver is - * used. This function is called whenever the USB enters or leaves suspend mode. - * This is an opportunity for the board logic to shutdown clocks, power, etc. - * while the USB is suspended. + * Board logic must provide the stm32_usbsuspend logic if the USBDEV driver + * is used. This function is called whenever the USB enters or leaves + * suspend mode. This is an opportunity for the board logic to shutdown + * clocks, power, etc. while the USB is suspended. * ****************************************************************************/ diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_clockconfig.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_clockconfig.c index c2b733ff2b0..1d894e5c3fb 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_clockconfig.c +++ b/boards/arm/stm32/mikroe-stm32f4/src/stm32_clockconfig.c @@ -62,10 +62,11 @@ * Name: stm32_board_clockconfig * * Description: - * The Mikroe-STM32F4 board does not have an external crystal, so it must rely - * on the internal 16Mhz RC oscillator. The default clock configuration in the - * OS for the STM32 architecture assumes an external crystal, so we must provide - * a board specific clock configuration routine. + * The Mikroe-STM32F4 board does not have an external crystal, so it must + * rely on the internal 16Mhz RC oscillator. The default clock + * configuration in the OS for the STM32 architecture assumes an external + * crystal, so we must provide a board specific clock configuration + * routine. * ****************************************************************************/ @@ -111,7 +112,7 @@ void stm32_board_clockconfig(void) /* Set the PLL dividers and multipliers to configure the main PLL */ - regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN |STM32_PLLCFG_PLLP | + regval = (STM32_PLLCFG_PLLM | STM32_PLLCFG_PLLN | STM32_PLLCFG_PLLP | RCC_PLLCFG_PLLSRC_HSI | STM32_PLLCFG_PLLQ); putreg32(regval, STM32_RCC_PLLCFG); @@ -126,10 +127,13 @@ void stm32_board_clockconfig(void) while ((getreg32(STM32_RCC_CR) & RCC_CR_PLLRDY) == 0) ; - /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */ + /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait + * states + */ #ifdef CONFIG_STM32_FLASH_PREFETCH - regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); + regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | + FLASH_ACR_DCEN | FLASH_ACR_PRFTEN); #else regval = (FLASH_ACR_LATENCY_5 | FLASH_ACR_ICEN | FLASH_ACR_DCEN); #endif diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_idle.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_idle.c index 221ad833a92..a51c65c7807 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_idle.c +++ b/boards/arm/stm32/mikroe-stm32f4/src/stm32_idle.c @@ -61,7 +61,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ + /* Does the board support an IDLE LED to indicate that the board is in the * IDLE state? */ diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c index 28e09dd0e96..11a6af600bb 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c +++ b/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c @@ -1,7 +1,8 @@ /**************************************************************************** * boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt2.c * - * Interface definition for the MI0283QT-2 LCD from Multi-Inno Technology Co., Ltd. + * Interface definition for the MI0283QT-2 LCD from Multi-Inno Technology + * Co., Ltd. * This LCD is based on the Himax HX8347-D LCD controller. * * Copyright (C) 2012-2013 Gregory Nutt. All rights reserved. @@ -68,38 +69,40 @@ * Pre-processor Definitions ****************************************************************************/ -/* Mikroe-STM32F4 Hardware Definitions ************************************************/ -/* --- ---------------------------------- -------------------- ------------------------ - * PIN CONFIGURATIONS SIGNAL NAME ON-BOARD CONNECTIONS - * (Family Data Sheet Table 1-1) (PIC32MX7 Schematic) - * --- ---------------------------------- -------------------- ------------------------ - * 39 PE8 LCD_RST TFT display - * 46 PE15 LCD-CS# TFT display - * 40 PE9 LCD_BLED LCD backlight LED - * 43 PE12 LCD-RS TFT display +/* Mikroe-STM32F4 Hardware Definitions **************************************/ + +/* --- --------------------- -------------------- ------------------------ + * PIN CONFIGURATIONS SIGNAL NAME ON-BOARD CONNECTIONS + * (Family Data Sheet + * Table 1-1) (PIC32MX7 Schematic) + * --- --------------------- -------------------- ------------------------ + * 39 PE8 LCD_RST TFT display + * 46 PE15 LCD-CS# TFT display + * 40 PE9 LCD_BLED LCD backlight LED + * 43 PE12 LCD-RS TFT display * * - * 97 RE0 T_D0 TFT display - * 98 RE1 T_D1 TFT display - * 1 RE2 T_D2 TFT display - * 2 RE3 T_D3 TFT display - * 3 RE4 T_D4 TFT display - * 4 RE5 T_D5 TFT display - * 5 RE6 T_D6 TFT display - * 38 RE7 T_D7 TFT display + * 97 RE0 T_D0 TFT display + * 98 RE1 T_D1 TFT display + * 1 RE2 T_D2 TFT display + * 2 RE3 T_D3 TFT display + * 3 RE4 T_D4 TFT display + * 4 RE5 T_D5 TFT display + * 5 RE6 T_D6 TFT display + * 38 RE7 T_D7 TFT display * - * 41 PE10 PMPRD - * 42 RE11 PMPWR + * 41 PE10 PMPRD + * 42 RE11 PMPWR * * TOUCHSCREEN PIN CONFIGURATIONS - * PIN CONFIGURATIONS SIGNAL NAME ON-BOARD CONNECTIONS - * --- ---------------------------------- -------------------- ------------------------ - * 35 PB0 LCD-YD TFT display - * ? LCD-XR TFT display - * ? LCD-YU TFT display - * 36 PB1 LCD-XL TFT display - * 95 PB8 DRIVEA TFT display - * 96 PB9 DRIVEB TFT display + * PIN CONFIGURATIONS SIGNAL NAME ON-BOARD CONNECTIONS + * --- --------------------- -------------------- ------------------------ + * 35 PB0 LCD-YD TFT display + * ? LCD-XR TFT display + * ? LCD-YU TFT display + * 36 PB1 LCD-XL TFT display + * 95 PB8 DRIVEA TFT display + * 96 PB9 DRIVEB TFT display */ /**************************************************************************** @@ -108,15 +111,16 @@ struct stm32f4_dev_s { - struct mio283qt2_lcd_s dev; /* The externally visible part of the driver */ - bool grammode; /* true=Writing to GRAM (16-bit write vs 8-bit) */ - bool firstread;/* First GRAM read? */ - FAR struct lcd_dev_s *drvr; /* The saved instance of the LCD driver */ + struct mio283qt2_lcd_s dev; /* The externally visible part of the driver */ + bool grammode; /* true=Writing to GRAM (16-bit write vs 8-bit) */ + bool firstread; /* First GRAM read? */ + FAR struct lcd_dev_s *drvr; /* The saved instance of the LCD driver */ }; /**************************************************************************** * Private Function Protototypes ****************************************************************************/ + /* Low Level LCD access */ static void stm32_select(FAR struct mio283qt2_lcd_s *dev); @@ -132,7 +136,9 @@ static void stm32_backlight(FAR struct mio283qt2_lcd_s *dev, int power); * Private Data ****************************************************************************/ -/* This is the driver state structure (there is no retained state information) */ +/* This is the driver state structure + * (there is no retained state information) + */ static struct stm32f4_dev_s g_stm32f4_lcd = { @@ -248,11 +254,12 @@ static void stm32_index(FAR struct mio283qt2_lcd_s *dev, uint8_t index) stm32_command(); - /* Write the index register to the 8-bit GPIO pin bus. We are violating the - * datasheet here a little by driving the WR pin low at the same time as - * the data, but the fact is that all ASIC logic will latch on the rising - * edge of WR anyway, not the falling edge. We are just shaving off a few - * cycles every time this routine is called, which will be farirly often. + /* Write the index register to the 8-bit GPIO pin bus. We are violating + * the datasheet here a little by driving the WR pin low at the same time + * as the data, but the fact is that all ASIC logic will latch on the + * rising edge of WR anyway, not the falling edge. We are just shaving off + * a few cycles every time this routine is called, which will be farirly + * often. */ *g_portsetreset = index | ((uint8_t) (~index) << 16) | @@ -294,13 +301,13 @@ static uint16_t stm32_read(FAR struct mio283qt2_lcd_s *dev) /* Set the I/O Port to input mode. Ugly, but fast. */ - *portmode &= 0xFFFF0000; + *portmode &= 0xffff0000; /* Read the data */ *portsetreset = (1 << LCD_PMPRD_PIN) << 16; stm32_tinydelay(); - data = *portinput & 0x00FF; + data = *portinput & 0x00ff; *portsetreset = (1 << LCD_PMPRD_PIN); /* Test if a 16-bit read is needed (GRAM mode) */ @@ -316,7 +323,7 @@ static uint16_t stm32_read(FAR struct mio283qt2_lcd_s *dev) stm32_tinydelay(); data = *portinput; *portsetreset = (1 << LCD_PMPRD_PIN); - } + } /* Okay, a 16-bit read is actually a 24-bit read from the LCD. * this is because the read color format of the MIO283QT-2 is a bit @@ -327,20 +334,20 @@ static uint16_t stm32_read(FAR struct mio283qt2_lcd_s *dev) /* Clip RED sample to 5-bits and shit to MSB */ - data = (data & 0xF8) << 8; + data = (data & 0xf8) << 8; /* Now read Green sample */ *portsetreset = (1 << LCD_PMPRD_PIN) << 16; stm32_tinydelay(); - data |= (*portinput & 0x00FC) << 3; + data |= (*portinput & 0x00fc) << 3; *portsetreset = (1 << LCD_PMPRD_PIN); /* Now read Blue sample */ *portsetreset = (1 << LCD_PMPRD_PIN) << 16; stm32_tinydelay(); - data |= (*portinput & 0x00F8) >> 3; + data |= (*portinput & 0x00f8) >> 3; *portsetreset = (1 << LCD_PMPRD_PIN); } @@ -373,18 +380,20 @@ static void stm32_write(FAR struct mio283qt2_lcd_s *dev, uint16_t data) if (priv->grammode) { - /* Need to write 16-bit pixel data (16 BPP). Write the upper pixel data first */ + /* Need to write 16-bit pixel data (16 BPP). + * Write the upper pixel data first + */ - *g_portsetreset = ((data>>8) & 0xFF) | (((~data>>8) & 0xFF) << 16) | - ((1 << LCD_PMPWR_PIN) << 16); + *g_portsetreset = ((data >> 8) & 0xff) | (((~data >> 8) & 0xff) << + 16) | ((1 << LCD_PMPWR_PIN) << 16); stm32_tinydelay(); *g_portsetreset = (1 << LCD_PMPWR_PIN); } /* Now write the lower 8-bit of data */ - *g_portsetreset = (data & 0xFF) | ((~data & 0xFF) << 16) | - ((1 << LCD_PMPWR_PIN) << 16); + *g_portsetreset = (data & 0xff) | ((~data & 0xff) << 16) | + ((1 << LCD_PMPWR_PIN) << 16); stm32_tinydelay(); *g_portsetreset = (1 << LCD_PMPWR_PIN); } @@ -399,9 +408,9 @@ static void stm32_write(FAR struct mio283qt2_lcd_s *dev, uint16_t data) static void stm32_backlight(FAR struct mio283qt2_lcd_s *dev, int power) { - /* For now, we just control the backlight as a discrete. Pulse width modulation - * would be required to vary the backlight level. A low value turns the backlight - * off. + /* For now, we just control the backlight as a discrete. Pulse width + * modulation would be required to vary the backlight level. A low value + * turns the backlight off. */ stm32_gpiowrite(GPIO_LCD_BLED, power > 0); @@ -431,31 +440,31 @@ void stm32_lcdinitialize(void) */ #ifdef CONFIG_LCD_MIO283QT2 - stm32_configgpio(GPIO_LCD_RST); - stm32_configgpio(GPIO_LCD_CS); - stm32_configgpio(GPIO_LCD_BLED); - stm32_gpiowrite(GPIO_LCD_BLED, false); - stm32_configgpio(GPIO_LCD_RS); - stm32_configgpio(GPIO_LCD_PMPWR); - stm32_configgpio(GPIO_LCD_PMPRD); + stm32_configgpio(GPIO_LCD_RST); + stm32_configgpio(GPIO_LCD_CS); + stm32_configgpio(GPIO_LCD_BLED); + stm32_gpiowrite(GPIO_LCD_BLED, false); + stm32_configgpio(GPIO_LCD_RS); + stm32_configgpio(GPIO_LCD_PMPWR); + stm32_configgpio(GPIO_LCD_PMPRD); - /* Configure PE0-7 for output */ + /* Configure PE0-7 for output */ - stm32_configgpio(GPIO_LCD_T_D0); - stm32_configgpio(GPIO_LCD_T_D1); - stm32_configgpio(GPIO_LCD_T_D2); - stm32_configgpio(GPIO_LCD_T_D3); - stm32_configgpio(GPIO_LCD_T_D4); - stm32_configgpio(GPIO_LCD_T_D5); - stm32_configgpio(GPIO_LCD_T_D6); - stm32_configgpio(GPIO_LCD_T_D7); + stm32_configgpio(GPIO_LCD_T_D0); + stm32_configgpio(GPIO_LCD_T_D1); + stm32_configgpio(GPIO_LCD_T_D2); + stm32_configgpio(GPIO_LCD_T_D3); + stm32_configgpio(GPIO_LCD_T_D4); + stm32_configgpio(GPIO_LCD_T_D5); + stm32_configgpio(GPIO_LCD_T_D6); + stm32_configgpio(GPIO_LCD_T_D7); #else /* Just configure the backlight control as an output and turn off the * backlight for now. */ - stm32_configgpio(GPIO_LCD_BLED); + stm32_configgpio(GPIO_LCD_BLED); #endif } @@ -463,15 +472,16 @@ void stm32_lcdinitialize(void) * Name: board_lcd_initialize * * Description: - * Initialize the LCD video hardware. The initial state of the LCD is fully - * initialized, display memory cleared, and the LCD ready to use, but with the power - * setting at 0 (full off). + * Initialize the LCD video hardware. The initial state of the LCD is + * fully initialized, display memory cleared, and the LCD ready to use, + * but with the power setting at 0 (full off). * ****************************************************************************/ int board_lcd_initialize(void) { - /* Only initialize the driver once. NOTE: The LCD GPIOs were already configured + /* Only initialize the driver once. + * NOTE: The LCD GPIOs were already configured * by stm32_lcdinitialize. */ @@ -509,8 +519,8 @@ int board_lcd_initialize(void) * Name: board_lcd_getdev * * Description: - * Return a a reference to the LCD object for the specified LCD. This allows support - * for multiple LCD devices. + * Return a a reference to the LCD object for the specified LCD. + * This allows support for multiple LCD devices. * ****************************************************************************/ diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c index 469de4d6ae3..a375793b671 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c +++ b/boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c @@ -1,7 +1,8 @@ /**************************************************************************** * boards/arm/stm32/mikroe-stm32f4/src/stm32_mio283qt9a.c * - * Interface definition for the MI0283QT-9A LCD from Multi-Inno Technology Co., Ltd. + * Interface definition for the MI0283QT-9A LCD from Multi-Inno Technology + * Co., Ltd. * LCD is based on the Ilitek ILI9341 LCD controller. * * Copyright (C) 2012-2014 Gregory Nutt. All rights reserved. @@ -69,38 +70,40 @@ * Pre-processor Definitions ****************************************************************************/ -/* Mikroe-STM32F4 Hardware Definitions ************************************************/ -/* --- ---------------------------------- -------------------- ------------------------ - * PIN CONFIGURATIONS SIGNAL NAME ON-BOARD CONNECTIONS - * (Family Data Sheet Table 1-1) (PIC32MX7 Schematic) - * --- ---------------------------------- -------------------- ------------------------ - * 39 PE8 LCD_RST TFT display - * 46 PE15 LCD-CS# TFT display - * 40 PE9 LCD_BLED LCD backlight LED - * 43 PE12 LCD-RS TFT display +/* Mikroe-STM32F4 Hardware Definitions **************************************/ + +/* --- ------------------ -------------------- ------------------------ + * PIN CONFIGURATIONS SIGNAL NAME ON-BOARD CONNECTIONS + * (Family Data Sheet + * Table 1-1) (PIC32MX7 Schematic) + * --- ------------------ -------------------- ------------------------ + * 39 PE8 LCD_RST TFT display + * 46 PE15 LCD-CS# TFT display + * 40 PE9 LCD_BLED LCD backlight LED + * 43 PE12 LCD-RS TFT display * * - * 97 RE0 T_D0 TFT display - * 98 RE1 T_D1 TFT display - * 1 RE2 T_D2 TFT display - * 2 RE3 T_D3 TFT display - * 3 RE4 T_D4 TFT display - * 4 RE5 T_D5 TFT display - * 5 RE6 T_D6 TFT display - * 38 RE7 T_D7 TFT display + * 97 RE0 T_D0 TFT display + * 98 RE1 T_D1 TFT display + * 1 RE2 T_D2 TFT display + * 2 RE3 T_D3 TFT display + * 3 RE4 T_D4 TFT display + * 4 RE5 T_D5 TFT display + * 5 RE6 T_D6 TFT display + * 38 RE7 T_D7 TFT display * - * 41 PE10 PMPRD - * 42 RE11 PMPWR + * 41 PE10 PMPRD + * 42 RE11 PMPWR * * TOUCHSCREEN PIN CONFIGURATIONS - * PIN CONFIGURATIONS SIGNAL NAME ON-BOARD CONNECTIONS - * --- ---------------------------------- -------------------- ------------------------ - * 35 PB0 LCD-YD TFT display - * ? LCD-XR TFT display - * ? LCD-YU TFT display - * 36 PB1 LCD-XL TFT display - * 95 PB8 DRIVEA TFT display - * 96 PB9 DRIVEB TFT display + * PIN CONFIGURATIONS SIGNAL NAME ON-BOARD CONNECTIONS + * --- ------------------ ----------------- -------------------------- + * 35 PB0 LCD-YD TFT display + * ? LCD-XR TFT display + * ? LCD-YU TFT display + * 36 PB1 LCD-XL TFT display + * 95 PB8 DRIVEA TFT display + * 96 PB9 DRIVEB TFT display */ /**************************************************************************** @@ -118,6 +121,7 @@ struct stm32f4_dev_s /**************************************************************************** * Private Function Protototypes ****************************************************************************/ + /* Low Level LCD access */ static void stm32_select(FAR struct mio283qt9a_lcd_s *dev); @@ -133,7 +137,9 @@ static void stm32_backlight(FAR struct mio283qt9a_lcd_s *dev, int power); * Private Data ****************************************************************************/ -/* This is the driver state structure (there is no retained state information) */ +/* This is the driver state structure + * (there is no retained state information) + */ static struct stm32f4_dev_s g_stm32f4_lcd = { @@ -249,11 +255,12 @@ static void stm32_index(FAR struct mio283qt9a_lcd_s *dev, uint8_t index) stm32_command(); - /* Write the index register to the 8-bit GPIO pin bus. We are violating the - * datasheet here a little by driving the WR pin low at the same time as - * the data, but the fact is that all ASIC logic will latch on the rising - * edge of WR anyway, not the falling edge. We are just shaving off a few - * cycles every time this routine is called, which will be fairly often. + /* Write the index register to the 8-bit GPIO pin bus. We are violating + * the datasheet here a little by driving the WR pin low at the same time + * as the data, but the fact is that all ASIC logic will latch on the + * rising edge of WR anyway, not the falling edge. We are just shaving off + * a few cycles every time this routine is called, which will be fairly + * often. */ *g_portsetreset = index | ((uint8_t) (~index) << 16) | @@ -295,13 +302,13 @@ static uint16_t stm32_read(FAR struct mio283qt9a_lcd_s *dev) /* Set the I/O Port to input mode. Ugly, but fast. */ - *portmode &= 0xFFFF0000; + *portmode &= 0xffff0000; /* Read the data */ *portsetreset = (1 << LCD_PMPRD_PIN) << 16; stm32_tinydelay(); - data = *portinput & 0x00FF; + data = *portinput & 0x00ff; *portsetreset = (1 << LCD_PMPRD_PIN); /* Test if a 16-bit read is needed (GRAM mode) */ @@ -328,20 +335,20 @@ static uint16_t stm32_read(FAR struct mio283qt9a_lcd_s *dev) /* Clip RED sample to 5-bits and shit to MSB */ - data = (data & 0xF8) << 8; + data = (data & 0xf8) << 8; /* Now read Green sample */ *portsetreset = (1 << LCD_PMPRD_PIN) << 16; stm32_tinydelay(); - data |= (*portinput & 0x00FC) << 3; + data |= (*portinput & 0x00fc) << 3; *portsetreset = (1 << LCD_PMPRD_PIN); /* Now read Blue sample */ *portsetreset = (1 << LCD_PMPRD_PIN) << 16; stm32_tinydelay(); - data |= (*portinput & 0x00F8) >> 3; + data |= (*portinput & 0x00f8) >> 3; *portsetreset = (1 << LCD_PMPRD_PIN); } @@ -374,17 +381,19 @@ static void stm32_write(FAR struct mio283qt9a_lcd_s *dev, uint16_t data) if (priv->grammode) { - /* Need to write 16-bit pixel data (16 BPP). Write the upper pixel data first */ + /* Need to write 16-bit pixel data (16 BPP). + * Write the upper pixel data first + */ - *g_portsetreset = ((data>>8) & 0xFF) | (((~data>>8) & 0xFF) << 16) | - ((1 << LCD_PMPWR_PIN) << 16); + *g_portsetreset = ((data >> 8) & 0xff) | (((~data >> 8) & 0xff) << + 16) | ((1 << LCD_PMPWR_PIN) << 16); stm32_tinydelay(); *g_portsetreset = (1 << LCD_PMPWR_PIN); } /* Now write the lower 8-bit of data */ - *g_portsetreset = (data & 0xFF) | ((~data & 0xFF) << 16) | + *g_portsetreset = (data & 0xff) | ((~data & 0xff) << 16) | ((1 << LCD_PMPWR_PIN) << 16); stm32_tinydelay(); *g_portsetreset = (1 << LCD_PMPWR_PIN); @@ -400,9 +409,9 @@ static void stm32_write(FAR struct mio283qt9a_lcd_s *dev, uint16_t data) static void stm32_backlight(FAR struct mio283qt9a_lcd_s *dev, int power) { - /* For now, we just control the backlight as a discrete. Pulse width modulation - * would be required to vary the backlight level. A low value turns the backlight - * off. + /* For now, we just control the backlight as a discrete. Pulse width + * modulation would be required to vary the backlight level. A low value + * turns the backlight off. */ stm32_gpiowrite(GPIO_LCD_BLED, power > 0); @@ -432,31 +441,31 @@ void stm32_lcdinitialize(void) */ #ifdef CONFIG_LCD_MIO283QT9A - stm32_configgpio(GPIO_LCD_RST); - stm32_configgpio(GPIO_LCD_CS); - stm32_configgpio(GPIO_LCD_BLED); - stm32_gpiowrite(GPIO_LCD_BLED, false); - stm32_configgpio(GPIO_LCD_RS); - stm32_configgpio(GPIO_LCD_PMPWR); - stm32_configgpio(GPIO_LCD_PMPRD); + stm32_configgpio(GPIO_LCD_RST); + stm32_configgpio(GPIO_LCD_CS); + stm32_configgpio(GPIO_LCD_BLED); + stm32_gpiowrite(GPIO_LCD_BLED, false); + stm32_configgpio(GPIO_LCD_RS); + stm32_configgpio(GPIO_LCD_PMPWR); + stm32_configgpio(GPIO_LCD_PMPRD); - /* Configure PE0-7 for output */ + /* Configure PE0-7 for output */ - stm32_configgpio(GPIO_LCD_T_D0); - stm32_configgpio(GPIO_LCD_T_D1); - stm32_configgpio(GPIO_LCD_T_D2); - stm32_configgpio(GPIO_LCD_T_D3); - stm32_configgpio(GPIO_LCD_T_D4); - stm32_configgpio(GPIO_LCD_T_D5); - stm32_configgpio(GPIO_LCD_T_D6); - stm32_configgpio(GPIO_LCD_T_D7); + stm32_configgpio(GPIO_LCD_T_D0); + stm32_configgpio(GPIO_LCD_T_D1); + stm32_configgpio(GPIO_LCD_T_D2); + stm32_configgpio(GPIO_LCD_T_D3); + stm32_configgpio(GPIO_LCD_T_D4); + stm32_configgpio(GPIO_LCD_T_D5); + stm32_configgpio(GPIO_LCD_T_D6); + stm32_configgpio(GPIO_LCD_T_D7); #else /* Just configure the backlight control as an output and turn off the * backlight for now. */ - stm32_configgpio(GPIO_LCD_BLED); + stm32_configgpio(GPIO_LCD_BLED); #endif } @@ -464,16 +473,16 @@ void stm32_lcdinitialize(void) * Name: board_lcd_initialize * * Description: - * Initialize the LCD video hardware. The initial state of the LCD is fully - * initialized, display memory cleared, and the LCD ready to use, but with the power - * setting at 0 (full off). + * Initialize the LCD video hardware. The initial state of the LCD is + * fully initialized, display memory cleared, and the LCD ready to use, + * but with the power setting at 0 (full off). * ****************************************************************************/ int board_lcd_initialize(void) { - /* Only initialize the driver once. NOTE: The LCD GPIOs were already configured - * by stm32_lcdinitialize. + /* Only initialize the driver once. + * NOTE: The LCD GPIOs were already configured by stm32_lcdinitialize. */ if (!g_stm32f4_lcd.drvr) @@ -510,8 +519,8 @@ int board_lcd_initialize(void) * Name: board_lcd_getdev * * Description: - * Return a a reference to the LCD object for the specified LCD. This allows support - * for multiple LCD devices. + * Return a a reference to the LCD object for the specified LCD. This + * allows support for multiple LCD devices. * ****************************************************************************/ diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c index 1e93ed321e3..e32c3af3c3e 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c +++ b/boards/arm/stm32/mikroe-stm32f4/src/stm32_spi.c @@ -67,7 +67,8 @@ * Name: stm32_spidev_initialize * * Description: - * Called to configure SPI chip select GPIO pins for the mikroe_stm32f4 board. + * Called to configure SPI chip select GPIO pins for the mikroe_stm32f4 + * board. * ****************************************************************************/ @@ -90,6 +91,7 @@ void weak_function stm32_spidev_initialize(void) #endif /* Configure the EXP I/O cs for SPI3 */ + stm32_configgpio(GPIO_CS_EXP_SPI3); /* Expander chip select */ #endif @@ -99,32 +101,34 @@ void weak_function stm32_spidev_initialize(void) * Name: stm32_spi1/2/3select and stm32_spi1/2/3status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); #if defined(CONFIG_AUDIO_VS1053) if (devid == SPIDEV_AUDIO_DATA(0)) @@ -183,9 +187,11 @@ uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -195,9 +201,11 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) diff --git a/boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c b/boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c index 10bb4471362..3e3746e8419 100644 --- a/boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c +++ b/boards/arm/stm32/mikroe-stm32f4/src/stm32_vs1053.c @@ -100,6 +100,7 @@ static int up_read_dreq(FAR const struct vs1053_lower_s *lower); * following structure provides an MCU-independent mechanixm for controlling * the VS1053 GPIO interrupt. */ + static struct stm32_lower_s g_vs1053lower = { .lower = @@ -165,7 +166,7 @@ static int up_read_dreq(FAR const struct vs1053_lower_s *lower) * Name: up_vs1053initialize ****************************************************************************/ -void up_vs1053initialize(FAR struct spi_dev_s* spi) +void up_vs1053initialize(FAR struct spi_dev_s * spi) { int ret; char name[8]; @@ -173,7 +174,8 @@ void up_vs1053initialize(FAR struct spi_dev_s* spi) /* Assumptions: * 1) SPI pins were configured in up_spi.c early in the boot-up phase. - * 2) Clocking for the SPI3 peripheral was also provided earlier in boot-up. + * 2) Clocking for the SPI3 peripheral was also provided earlier in + * boot-up. */ /* NOTE: The RST line should be asserted early in the boot process @@ -182,7 +184,7 @@ void up_vs1053initialize(FAR struct spi_dev_s* spi) * until the RST line is asserted. */ - //(void)stm32_configgpio(GPIO_VS1053_RST); + /* (void)stm32_configgpio(GPIO_VS1053_RST); */ /* Initialize the VS1053 DREQ GPIO line */ @@ -193,7 +195,8 @@ void up_vs1053initialize(FAR struct spi_dev_s* spi) pVs1053 = vs1053_initialize(spi, &g_vs1053lower.lower, VS1053_DEVNO); if (pVs1053 == NULL) { - auderr("ERROR: Failed to bind SPI port %d VS1053 device\n", VS1053_DEVNO); + auderr("ERROR: Failed to bind SPI port %d VS1053 device\n", + VS1053_DEVNO); return; } diff --git a/boards/arm/stm32/nucleo-f303re/src/nucleo-f303re.h b/boards/arm/stm32/nucleo-f303re/src/nucleo-f303re.h index c5c369c9573..b16c814c12c 100644 --- a/boards/arm/stm32/nucleo-f303re/src/nucleo-f303re.h +++ b/boards/arm/stm32/nucleo-f303re/src/nucleo-f303re.h @@ -49,6 +49,7 @@ ****************************************************************************/ /* LED definitions **********************************************************/ + /* The Nucleo F303RE board has three LEDs. Two of these are controlled by * logic on the board and are not available for software control: * @@ -72,6 +73,7 @@ #define LED_DRIVER_PATH "/dev/userleds" /* Button definitions *******************************************************/ + /* The Nucleo F303RE supports two buttons; only one button is controllable * by software: * @@ -89,6 +91,7 @@ #define GPIO_BTN_USER (GPIO_INPUT|GPIO_FLOAT|GPIO_EXTI|GPIO_PORTC|GPIO_PIN13) /* PWM definitions **********************************************************/ + /* The Nucleo F303RE has no real on-board PWM devices, but the board can be * configured to output a pulse train using variously unused pins on the * board for PWM output (see board.h for details of pins). @@ -142,7 +145,8 @@ void weak_function stm32_spidev_initialize(void); * Configure the timer driver. * * Input Parameters: - * devpath - The full path to the timer device. This should be of the form /dev/timer0 + * devpath - The full path to the timer device. + * This should be of the form /dev/timer0 * timer - The timer's number. * * Returned Value: diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_adc.c b/boards/arm/stm32/nucleo-f303re/src/stm32_adc.c index 9019d9ffeaa..0e1a88bb987 100644 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_adc.c +++ b/boards/arm/stm32/nucleo-f303re/src/stm32_adc.c @@ -104,6 +104,7 @@ #endif /* The number of ADC channels in the conversion list */ + /* TODO DMA */ #define ADC1_NCHANNELS 4 @@ -325,6 +326,7 @@ int stm32_adc_setup(void) int i; /* DEV1 */ + /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < DEV1_NCHANNELS; i++) @@ -353,6 +355,7 @@ int stm32_adc_setup(void) #ifdef DEV2_PORT /* DEV2 */ + /* Configure the pins as analog inputs for the selected channels */ for (i = 0; i < DEV2_NCHANNELS; i++) diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_appinitialize.c b/boards/arm/stm32/nucleo-f303re/src/stm32_appinitialize.c index b76576b0df2..f0a9405404c 100644 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_appinitialize.c +++ b/boards/arm/stm32/nucleo-f303re/src/stm32_appinitialize.c @@ -118,8 +118,8 @@ int board_app_initialize(uintptr_t arg) } #endif - /* Contrairement à l'ADC, il n'y a pas de BOARDIOC_DAC_SETUP spécifique. Il - * faut le faire ici + /* Contrairement à l'ADC, il n'y a pas de BOARDIOC_DAC_SETUP spécifique. + * Il faut le faire ici */ #ifdef HAVE_DAC diff --git a/boards/arm/stm32/nucleo-f303re/src/stm32_spi.c b/boards/arm/stm32/nucleo-f303re/src/stm32_spi.c index 4763d1bc5e0..5d37d6ff2f7 100644 --- a/boards/arm/stm32/nucleo-f303re/src/stm32_spi.c +++ b/boards/arm/stm32/nucleo-f303re/src/stm32_spi.c @@ -84,8 +84,8 @@ void weak_function stm32_spidev_initialize(void) * must be provided by board-specific logic. They are implementations of * the select and status methods of the SPI interface defined by struct * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including - * stm32_spibus_initialize()) are provided by common STM32 logic. To use this - * common SPI logic on your board: + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: * * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select * pins. @@ -93,10 +93,10 @@ void weak_function stm32_spidev_initialize(void) * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind - * the SPI driver to higher level logic (e.g., calling + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * @@ -106,7 +106,8 @@ void weak_function stm32_spidev_initialize(void) void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); #if defined(CONFIG_LCD_SSD1351) if (devid == SPIDEV_DISPLAY(0)) @@ -126,7 +127,8 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -139,7 +141,8 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) diff --git a/boards/arm/stm32/nucleo-f4x1re/src/stm32_boot.c b/boards/arm/stm32/nucleo-f4x1re/src/stm32_boot.c index bb13505bbb3..fcec6fc8f82 100644 --- a/boards/arm/stm32/nucleo-f4x1re/src/stm32_boot.c +++ b/boards/arm/stm32/nucleo-f4x1re/src/stm32_boot.c @@ -60,9 +60,10 @@ * Name: stm32_boardinitialize * * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. * ****************************************************************************/ @@ -74,8 +75,8 @@ void stm32_boardinitialize(void) board_autoled_initialize(); #endif - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak function - * stm32_spidev_initialize() has been brought into the link. + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. */ #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) @@ -83,8 +84,8 @@ void stm32_boardinitialize(void) #endif /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32_usbinitialize() has been brought - * into the build. + * disabled, and 3) the weak function stm32_usbinitialize() has been + * brought into the build. */ #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32_USB) @@ -96,19 +97,22 @@ void stm32_boardinitialize(void) * Name: board_late_initialize * * Description: - * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional initialization - * call will be performed in the boot-up sequence to a function called - * board_late_initialize(). board_late_initialize() will be called immediately - * after up_initialize() is called and just before the initial application is - * started. This additional initialization phase may be used, for example, to - * initialize board-specific device drivers. + * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional + * initialization call will be performed in the boot-up sequence to a + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. * ****************************************************************************/ #ifdef CONFIG_BOARD_LATE_INITIALIZE void board_late_initialize(void) { - /* Perform board initialization here instead of from the board_app_initialize(). */ + /* Perform board initialization here instead of from the + * board_app_initialize(). + */ stm32_bringup(); } diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_mrf24j40.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_mrf24j40.c index efafb29e4d5..5295e7ee9d5 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_mrf24j40.c +++ b/boards/arm/stm32/olimex-stm32-e407/src/stm32_mrf24j40.c @@ -248,7 +248,8 @@ static int stm32_mrf24j40_devsetup(FAR struct stm32_priv_s *priv) ret = mac802154dev_register(mac, 0); if (ret < 0) { - wlerr("ERROR: Failed to register the MAC character driver /dev/ieee%d: %d\n", + wlerr("ERROR: " + "Failed to register the MAC character driver /dev/ieee%d: %d\n", 0, ret); return ret; } diff --git a/boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c b/boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c index 25c13c680bb..9665ff7605a 100644 --- a/boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c +++ b/boards/arm/stm32/olimex-stm32-e407/src/stm32_spi.c @@ -134,8 +134,8 @@ void stm32_spidev_initialize(void) * in your board-specific logic. These functions will perform chip * selection and status operations using GPIOs in the way your board is * configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic * 4. The handle returned by stm32_spibus_initialize() may then be used to * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to diff --git a/boards/arm/stm32/omnibusf4/include/board.h b/boards/arm/stm32/omnibusf4/include/board.h index 5a726d03a96..0ccaec9c300 100644 --- a/boards/arm/stm32/omnibusf4/include/board.h +++ b/boards/arm/stm32/omnibusf4/include/board.h @@ -53,28 +53,30 @@ * Pre-processor Definitions ****************************************************************************/ -/* Clocking *************************************************************************/ +/* Clocking *****************************************************************/ /* The OMNIBUSF4 board uses a single 8MHz crystal. * * This is the canonical configuration: - * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 168000000 Determined by PLL configuration - * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) - * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) - * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) - * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) - * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) - * PLLM : 8 (STM32_PLLCFG_PLLM) - * PLLN : 336 (STM32_PLLCFG_PLLN) - * PLLP : 2 (STM32_PLLCFG_PLLP) - * PLLQ : 7 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK - * Flash Latency(WS) : 5 - * Prefetch Buffer : OFF - * Instruction cache : ON - * Data cache : ON - * Require 48MHz for USB OTG FS, : Enabled + * System Clock source : PLL (HSE) + * SYSCLK(Hz) : 168000000 Determined by PLL configuration + * HCLK(Hz) : 168000000 (STM32_RCC_CFGR_HPRE) + * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) + * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) + * APB2 Prescaler : 2 (STM32_RCC_CFGR_PPRE2) + * HSE Frequency(Hz) : 8000000 (STM32_BOARD_XTAL) + * PLLM : 8 (STM32_PLLCFG_PLLM) + * PLLN : 336 (STM32_PLLCFG_PLLN) + * PLLP : 2 (STM32_PLLCFG_PLLP) + * PLLQ : 7 (STM32_PLLCFG_PLLQ) + * Main regulator + * output voltage : Scale1 mode Needed for high speed SYSCLK + * Flash Latency(WS) : 5 + * Prefetch Buffer : OFF + * Instruction cache : ON + * Data cache : ON + * Require 48MHz for + * USB OTG FS, : Enabled * SDIO and RNG clock */ @@ -161,7 +163,7 @@ #define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) #define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY -/* Pin configurations **************************************************************/ +/* Pin configurations *******************************************************/ #define BOARD_NLEDS 2 /* One literal LED, one beeper */ #define GPIO_LED1 (GPIO_OUTPUT | GPIO_PUSHPULL | GPIO_SPEED_50MHz |\ @@ -246,7 +248,8 @@ /* SPI3 : * - * OMNIBUSF4SD targets use PA15 for NSS; others use PB4 (? BF code says "PB3"). + * OMNIBUSF4SD targets use PA15 for NSS; others use PB4 + * (? BF code says "PB3"). * define GPIO_SPI3_NSS GPIO_SPI3_NSS_2 PB4 * * Barometer and/or MAX7456, depending on the target. diff --git a/boards/arm/stm32/omnibusf4/src/stm32_boot.c b/boards/arm/stm32/omnibusf4/src/stm32_boot.c index b680e419b10..1376ce6f1d3 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_boot.c +++ b/boards/arm/stm32/omnibusf4/src/stm32_boot.c @@ -95,9 +95,11 @@ void stm32_boardinitialize(void) #endif #ifdef CONFIG_STM32_OTGFS - /* Initialize USB if the 1) OTG FS controller is in the configuration and 2) - * disabled, and 3) the weak function stm32_usbinitialize() has been brought - * into the build. Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also + /* Initialize USB if the + * 1) OTG FS controller is in the configuration and + * 2) disabled, and + * 3) the weak function stm32_usbinitialize() has been brought into the + * build. Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also * selected. */ diff --git a/boards/arm/stm32/omnibusf4/src/stm32_max7456.c b/boards/arm/stm32/omnibusf4/src/stm32_max7456.c index 615c2314666..46bd98ce802 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_max7456.c +++ b/boards/arm/stm32/omnibusf4/src/stm32_max7456.c @@ -88,6 +88,7 @@ int stm32_max7456_initialize(void) { .spi_devid = minor, }; + UNUSED(cs); /* Get the spi bus instance. */ diff --git a/boards/arm/stm32/omnibusf4/src/stm32_mpu6000.c b/boards/arm/stm32/omnibusf4/src/stm32_mpu6000.c index b3de3021682..697e0b15979 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_mpu6000.c +++ b/boards/arm/stm32/omnibusf4/src/stm32_mpu6000.c @@ -100,6 +100,7 @@ int stm32_mpu6000_initialize(void) { .spi_devid = minor, }; + UNUSED(cs); UNUSED(exti); diff --git a/boards/arm/stm32/omnibusf4/src/stm32_pwm.c b/boards/arm/stm32/omnibusf4/src/stm32_pwm.c index 9234aafb9e4..9ebb4d5e089 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_pwm.c +++ b/boards/arm/stm32/omnibusf4/src/stm32_pwm.c @@ -123,5 +123,6 @@ int stm32_pwm_setup(void) pwm_register(ppwm, pwm); } + return 0; } diff --git a/boards/arm/stm32/omnibusf4/src/stm32_reset.c b/boards/arm/stm32/omnibusf4/src/stm32_reset.c index 4a39cbd02a5..3c07de24b58 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_reset.c +++ b/boards/arm/stm32/omnibusf4/src/stm32_reset.c @@ -49,7 +49,7 @@ #ifdef CONFIG_BOARDCTL_RESET /**************************************************************************** - * Included Files + * Public Functions ****************************************************************************/ int board_reset(int mode) diff --git a/boards/arm/stm32/omnibusf4/src/stm32_spi.c b/boards/arm/stm32/omnibusf4/src/stm32_spi.c index fd7a67ad8af..a9b32ea5db7 100644 --- a/boards/arm/stm32/omnibusf4/src/stm32_spi.c +++ b/boards/arm/stm32/omnibusf4/src/stm32_spi.c @@ -122,6 +122,7 @@ void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, stm32_gpiowrite(GPIO_CS_MPU6000, !selected); } + uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) { return 0; @@ -139,6 +140,7 @@ void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, stm32_gpiowrite(GPIO_MMCSD_NSS, selected ? 0 : 1); } + uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) { /* Note: SD_DET is pulled high when there's no SD card present. */ @@ -158,6 +160,7 @@ void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, stm32_gpiowrite(GPIO_CS_MAX7456, selected ? 0 : 1); } + uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) { return 0; diff --git a/boards/arm/stm32/photon/include/board.h b/boards/arm/stm32/photon/include/board.h index 999c035e4e8..4d2920a0e36 100644 --- a/boards/arm/stm32/photon/include/board.h +++ b/boards/arm/stm32/photon/include/board.h @@ -53,12 +53,14 @@ * Pre-processor Definitions ****************************************************************************/ -/* Clocking *************************************************************************/ +/* Clocking *****************************************************************/ + /* The Particle photon board features a single 26MHz crystal. * * This is the canonical configuration: * System Clock source : PLL (HSE) - * SYSCLK(Hz) : 120000000 Determined by PLL configuration + * SYSCLK(Hz) : 120000000 Determined by PLL + * configuration * HCLK(Hz) : 120000000 (STM32_RCC_CFGR_HPRE) * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) @@ -68,7 +70,8 @@ * PLLN : 240 (STM32_PLLCFG_PLLN) * PLLP : 2 (STM32_PLLCFG_PLLP) * PLLQ : 5 (STM32_PLLCFG_PLLQ) - * Main regulator output voltage : Scale1 mode Needed for high speed SYSCLK + * Main regulator output voltage : Scale1 mode Needed for high speed + * SYSCLK * Flash Latency(WS) : 3 * Prefetch Buffer : OFF * Instruction cache : ON @@ -160,12 +163,14 @@ #define BOARD_TIM7_FREQUENCY (STM32_HCLK_FREQUENCY / 2) #define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY -/* USB OTG HS definitions ***********************************************************/ +/* USB OTG HS definitions ***************************************************/ + /* Do not enable external PHY clock or OTG_HS module will not work */ #undef BOARD_ENABLE_USBOTG_HSULPI -/* LED definitions ******************************************************************/ +/* LED definitions **********************************************************/ + /* LEDs * * A single LED is available driven by PA13. @@ -187,7 +192,8 @@ * * ------------------- ---------------------------- ------ * SYMBOL Meaning LED - * ------------------- ---------------------------- ------ */ + * ------------------- ---------------------------- ------ + */ #define LED_STARTED 0 /* NuttX has been started OFF */ #define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ @@ -224,13 +230,14 @@ #define RGBLED_BPWMTIMER 2 #define RGBLED_BPWMCHANNEL 4 -/* Button definitions ***************************************************************/ +/* Button definitions *******************************************************/ #define BOARD_BUTTON1 0 #define NUM_BUTTONS 1 #define BOARD_BUTTON1_BIT (1 << BOARD_BUTTON1) -/* Alternate function pin selections ************************************************/ +/* Alternate function pin selections ****************************************/ + /* UART1 */ #ifdef CONFIG_STM32_USART1 @@ -250,7 +257,7 @@ #define GPIO_SPI3_MOSI GPIO_SPI3_MOSI_1 /* PB5 */ #define GPIO_SPI3_SCK GPIO_SPI3_SCK_1 /* PB3 */ -/* SDIO definitions *****************************************************************/ +/* SDIO definitions *********************************************************/ /* Note that slower clocking is required when DMA is disabled in order * to avoid RX overrun/TX underrun errors due to delayed responses @@ -283,9 +290,10 @@ # define SDIO_SDXFR_CLKDIV (2 << SDIO_CLKCR_CLKDIV_SHIFT) #endif -/* DMA Channel/Stream Selections *****************************************************/ -/* Stream selections are arbitrary for now but might become important in the future - * if we set aside more DMA channels/streams. +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. * * SDIO DMA * DMAMAP_SDIO_1 = Channel 4, Stream 3 diff --git a/boards/arm/stm32/photon/src/dfu_signature.c b/boards/arm/stm32/photon/src/dfu_signature.c index cfee1dca6b4..83e4786fabb 100644 --- a/boards/arm/stm32/photon/src/dfu_signature.c +++ b/boards/arm/stm32/photon/src/dfu_signature.c @@ -73,5 +73,9 @@ __attribute__((externally_visible, section(".dfu_signature"))) {0, 0, 0, 0}, /* reserved */ 6, /* Current board is photon */ 4, 1, /* Firmware is "system-part1" */ - {0, 0, 0, 0, 0, 0, 0, 0} /* reserved */ + {0, 0, 0, 0, 0, 0, 0, 0}, /* reserved */ }; + +/**************************************************************************** + * Private Functions + ****************************************************************************/ diff --git a/boards/arm/stm32/photon/src/stm32_boot.c b/boards/arm/stm32/photon/src/stm32_boot.c index e61746dfe12..b6af82e5bb8 100644 --- a/boards/arm/stm32/photon/src/stm32_boot.c +++ b/boards/arm/stm32/photon/src/stm32_boot.c @@ -53,17 +53,18 @@ * Name: stm32_boardinitialize * * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. * ****************************************************************************/ void stm32_boardinitialize(void) { #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function - * stm32_spidev_initialize() has been brought into the link. + /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak + * function stm32_spidev_initialize() has been brought into the link. */ if (stm32_spidev_initialize) @@ -73,9 +74,11 @@ void stm32_boardinitialize(void) #endif #ifdef CONFIG_STM32_OTGHS - /* Initialize USB if the 1) OTG HS controller is in the configuration and 2) - * disabled, and 3) the weak function stm32_usbinitialize() has been brought - * into the build. Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also + /* Initialize USB if the + * 1) OTG HS controller is in the configuration and + * 2) disabled, and + * 3) the weak function stm32_usbinitialize() has been brought into + * the build. Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also * selected. */ @@ -98,10 +101,11 @@ void stm32_boardinitialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_intitialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_intitialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. * ****************************************************************************/ diff --git a/boards/arm/stm32/photon/src/stm32_wlan.c b/boards/arm/stm32/photon/src/stm32_wlan.c index 3d8e333e663..fa5c17e6e6b 100644 --- a/boards/arm/stm32/photon/src/stm32_wlan.c +++ b/boards/arm/stm32/photon/src/stm32_wlan.c @@ -153,6 +153,7 @@ int photon_wlan_initialize() wlerr("ERROR: Failed to bind SDIO to bcmf driver\n"); /* FIXME deinitialize sdio device */ + return ERROR; } diff --git a/boards/arm/stm32/photon/src/stm32_wlan_firmware.c b/boards/arm/stm32/photon/src/stm32_wlan_firmware.c index 0760be94a32..310a99a2827 100644 --- a/boards/arm/stm32/photon/src/stm32_wlan_firmware.c +++ b/boards/arm/stm32/photon/src/stm32_wlan_firmware.c @@ -1,51 +1,58 @@ -/* +/**************************************************************************** * boards/arm/stm32/photon/src/stm32_wlan_firmware.c * All rights reserved. * - * Redistribution and use in source and binary forms, with or without modification, - * are permitted provided that the following conditions are met: + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions are + * met: * - * 1. Redistributions of source code must retain the above copyright notice, this - * list of conditions and the following disclaimer. + * 1. Redistributions of source code must retain the above copyright notice, + * this list of conditions and the following disclaimer. * - * 2. Redistributions in binary form must reproduce the above copyright notice, this - * list of conditions and the following disclaimer in the documentation and/or - * other materials provided with the distribution. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in the + * documentation and/or other materials provided with the distribution. * - * 3. Neither the name of Broadcom nor the names of other contributors to this - * software may be used to endorse or promote products derived from this software - * without specific prior written permission. + * 3. Neither the name of Broadcom nor the names of other contributors to + * this software may be used to endorse or promote products derived from + * this software without specific prior written permission. * - * 4. This software may not be used as a standalone product, and may only be used as - * incorporated in your product or device that incorporates Broadcom wireless connectivity - * products and solely for the purpose of enabling the functionalities of such Broadcom products. + * 4. This software may not be used as a standalone product, and may only be + * used as incorporated in your product or device that incorporates Broadcom + * wireless connectivity products and solely for the purpose of enabling the + * functionalities of such Broadcom products. * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY WARRANTIES OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, + * BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY, FITNESS FOR + * A PARTICULAR PURPOSE AND NON-INFRINGEMENT, ARE DISCLAIMED. IN NO EVENT + * SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, + * INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES + * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR + * SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER + * CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY + * OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF + * SUCH DAMAGE. * - * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND - * ANY WARRANTIES OF ANY KIND, EXPRESS OR IMPLIED, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED - * WARRANTIES OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT, ARE - * DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR - * ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES - * (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; - * LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON - * ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT - * (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS - * SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE. - */ + ****************************************************************************/ -/** @file - * - * BCM43362 NVRAM variables for WM-N-BM-09 USI SiP - * - */ +/* BCM43362 NVRAM variables for WM-N-BM-09 USI SiP */ + +/**************************************************************************** + * Included Files + ****************************************************************************/ #include -/** - * Character array of NVRAM image - */ +/**************************************************************************** + * Public Data + ****************************************************************************/ -const char __attribute__((section(".wlan_nvram_image"))) bcm43362_nvram_image[] = +/* Character array of NVRAM image */ + +const char +__attribute__((section(".wlan_nvram_image"))) bcm43362_nvram_image[] = "manfid=0x2d0" "\x00" "prodid=0x492" "\x00" "vendid=0x14e4" "\x00" @@ -65,7 +72,7 @@ const char __attribute__((section(".wlan_nvram_image"))) bcm43362_nvram_image[] "mcs2gpo0=0x4444" "\x00" "mcs2gpo1=0x6444" "\x00" "pa0maxpwr=80" "\x00" - "pa0b0=5264" "\x00" /*PA params*/ + "pa0b0=5264" "\x00" /* PA params */ "pa0b1=64897" "\x00" "pa0b2=65359" "\x00" "pa0itssit=62" "\x00" @@ -109,7 +116,8 @@ const char __attribute__((section(".wlan_nvram_image"))) bcm43362_nvram_image[] const unsigned int bcm43362_nvram_image_len = sizeof(bcm43362_nvram_image); const uint8_t -__attribute__((section(".wlan_firmware_image"))) bcm43362_firmware_image[] = { +__attribute__((section(".wlan_firmware_image"))) bcm43362_firmware_image[] = +{ 0x00, 0x00, 0x00, 0x00, 0xcd, 0xc2, 0x00, 0x00, 0x91, 0xc1, 0x00, 0x00, 0x91, 0xc1, 0x00, 0x00, 0x91, 0xc1, 0x00, 0x00, 0x91, 0xc1, 0x00, 0x00, 0x91, 0xc1, 0x00, 0x00, 0x91, 0xc1, 0x00, 0x00, 0x91, 0xc1, 0x00, 0x00, @@ -17647,4 +17655,9 @@ __attribute__((section(".wlan_firmware_image"))) bcm43362_firmware_image[] = { 0xd2, 0x58, 0x82, 0x92 }; -const unsigned int bcm43362_firmware_image_len = sizeof(bcm43362_firmware_image); +const unsigned +int bcm43362_firmware_image_len = sizeof(bcm43362_firmware_image); + +/**************************************************************************** + * Public Functions + ****************************************************************************/ diff --git a/boards/arm/stm32/shenzhou/src/stm32_ili93xx.c b/boards/arm/stm32/shenzhou/src/stm32_ili93xx.c index 73c6a60af62..bdc0f2db74a 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_ili93xx.c +++ b/boards/arm/stm32/shenzhou/src/stm32_ili93xx.c @@ -33,22 +33,26 @@ * POSSIBILITY OF SUCH DAMAGE. * ****************************************************************************/ + /* TFT LCD * - * -- ---- -------------- ----------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * PN NAME SIGNAL NOTES - * -- ---- -------------- ----------------------------------------------------------- + * -- ---- -------------- --------------------------------------------------- * 37 PB2 DATA_LE To TFT LCD (CN13, ping 28) - * 96 PB9 F_CS To both the TFT LCD (CN13, pin 30) and to the W25X16 SPI FLASH + * 96 PB9 F_CS To both the TFT LCD (CN13, pin 30) and + * to the W25X16 SPI FLASH * 34 PC5 TP_INT JP6. To TFT LCD (CN13) module (CN13, pin 26) * 65 PC8 LCD_CS Active low: Pulled high (CN13, pin 19) * 66 PC9 TP_CS Active low: Pulled high (CN13, pin 31) * 78 PC10 SPI3_SCK To TFT LCD (CN13, pin 29) * 79 PC11 SPI3_MISO To TFT LCD (CN13, pin 25) * 80 PC12 SPI3_MOSI To TFT LCD (CN13, pin 27) - * 58 PD11 SD_CS Active low: Pulled high (See also TFT LCD CN13, pin 32) + * 58 PD11 SD_CS Active low: Pulled high + * (See also TFT LCD CN13, pin 32) * 60 PD13 LCD_RS To TFT LCD (CN13, pin 20) - * 61 PD14 LCD_WR To TFT LCD (CN13, pin 21). Schematic is wrong LCD_WR is PB14. + * 61 PD14 LCD_WR To TFT LCD (CN13, pin 21). + * Schematic is wrong LCD_WR is PB14. * 62 PD15 LCD_RD To TFT LCD (CN13, pin 22) * 97 PE0 DB00 To TFT LCD (CN13, pin 3) * 98 PE1 DB01 To TFT LCD (CN13, pin 4) @@ -67,13 +71,14 @@ * 45 PE14 DB14 To TFT LCD (CN13, pin 17) * 46 PE15 DB15 To TFT LCD (CN13, pin 18) * - * NOTE: The backlight signal NC_BL (CN13, pin 24) is pulled high and not under + * NOTE: + * The backlight signal NC_BL (CN13, pin 24) is pulled high and not under * software control * * On LCD module: - * -- -------------- ------------------------------------------------------------------- + * -- -------------- -------------------------------------------------------- * PN SIGNAL NOTES - * -- -------------- ------------------------------------------------------------------- + * -- -------------- -------------------------------------------------------- * 3 DB01 To LCD DB1 * 4 DB00 To LCD DB0 * 5 DB03 To LCD DB3 @@ -133,7 +138,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Configuration **********************************************************************/ + +/* Configuration ************************************************************/ + /* CONFIG_STM32_ILI1505_DISABLE may be defined to disable the LCD_ILI1505 * CONFIG_STM32_ILI9300_DISABLE may be defined to disable the LCD_ILI9300 * CONFIG_STM32_ILI9320_DISABLE may be defined to disable the LCD_ILI9320 @@ -202,7 +209,8 @@ #undef CONFIG_LCD_FASTCONFIG #define CONFIG_LCD_FASTCONFIG 1 -/* Display/Color Properties ***********************************************************/ +/* Display/Color Properties *************************************************/ + /* Display Resolution */ #if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) @@ -218,7 +226,8 @@ #define STM32_BPP 16 #define STM32_COLORFMT FB_FMT_RGB16_565 -/* Shenzhou LCD Hardware Definitions **************************************************/ +/* Shenzhou LCD Hardware Definitions ****************************************/ + /* LCD /CS is CE4, Bank 3 of NOR/SRAM Bank 1~4 */ #define STM32_LCDBASE ((uintptr_t)(0x60000000 | 0x08000000)) @@ -398,10 +407,12 @@ struct stm32_dev_s /**************************************************************************** * Private Function Protototypes ****************************************************************************/ + /* Low Level LCD access */ #ifdef CONFIG_LCD_REGDEBUG -static void stm32_lcdshow(FAR struct stm32_lower_s *priv, FAR const char *msg); +static void stm32_lcdshow(FAR struct stm32_lower_s *priv, + FAR const char *msg); #else # define stm32_lcdshow(p,m) #endif @@ -412,23 +423,27 @@ static uint16_t stm32_readreg(FAR struct stm32_dev_s *priv, uint8_t regaddr); static void stm32_gramselect(FAR struct stm32_dev_s *priv); static void stm32_writegram(FAR struct stm32_dev_s *priv, uint16_t rgbval); static inline uint16_t stm32_readgram(FAR struct stm32_dev_s *priv); -static void stm32_readnosetup(FAR struct stm32_dev_s *priv, FAR uint16_t *accum); -static uint16_t stm32_readnoshift(FAR struct stm32_dev_s *priv, FAR uint16_t *accum); -static void stm32_setcursor(FAR struct stm32_dev_s *priv, uint16_t col, uint16_t row); +static void stm32_readnosetup(FAR struct stm32_dev_s *priv, + FAR uint16_t *accum); +static uint16_t stm32_readnoshift(FAR struct stm32_dev_s *priv, + FAR uint16_t *accum); +static void stm32_setcursor(FAR struct stm32_dev_s *priv, + uint16_t col, uint16_t row); /* LCD Data Transfer Methods */ -static int stm32_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffer, - size_t npixels); -static int stm32_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, - size_t npixels); +static int stm32_putrun(fb_coord_t row, fb_coord_t col, + FAR const uint8_t *buffer, size_t npixels); +static int stm32_getrun(fb_coord_t row, fb_coord_t col, + FAR uint8_t *buffer, size_t npixels); /* LCD Configuration */ static int stm32_getvideoinfo(FAR struct lcd_dev_s *dev, - FAR struct fb_videoinfo_s *vinfo); -static int stm32_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno, - FAR struct lcd_planeinfo_s *pinfo); + FAR struct fb_videoinfo_s *vinfo); +static int stm32_getplaneinfo(FAR struct lcd_dev_s *dev, + unsigned int planeno, + FAR struct lcd_planeinfo_s *pinfo); /* LCD RGB Mapping */ @@ -455,10 +470,12 @@ static void stm32_lcdinput(FAR struct stm32_dev_s *priv); static void stm32_lcdoutput(FAR struct stm32_dev_s *priv); #if !defined(CONFIG_STM32_ILI9300_DISABLE) || !defined(CONFIG_STM32_ILI9320_DISABLE) || !defined(CONFIG_STM32_ILI9321_DISABLE) -static void stm32_lcd9300init(FAR struct stm32_dev_s *priv, enum lcd_type_e lcdtype); +static void stm32_lcd9300init(FAR struct stm32_dev_s *priv, + enum lcd_type_e lcdtype); #endif #if !defined(CONFIG_STM32_ILI9325_DISABLE) || !defined(CONFIG_STM32_ILI9328_DISABLE) -static void stm32_lcd9325init(FAR struct stm32_dev_s *priv, enum lcd_type_e lcdtype); +static void stm32_lcd9325init(FAR struct stm32_dev_s *priv, + enum lcd_type_e lcdtype); #endif #ifndef CONFIG_STM32_ILI9919_DISABLE static inline void stm32_lcd9919init(FAR struct stm32_dev_s *priv); @@ -471,6 +488,7 @@ static inline int stm32_lcdinitialize(FAR struct stm32_dev_s *priv); /**************************************************************************** * Private Data ****************************************************************************/ + /* LCD GPIO configurations */ #ifndef CONFIG_LCD_FASTCONFIG @@ -518,17 +536,17 @@ static const struct fb_videoinfo_s g_videoinfo = .fmt = STM32_COLORFMT, /* Color format: RGB16-565: RRRR RGGG GGGB BBBB */ .xres = STM32_XRES, /* Horizontal resolution in pixel columns */ .yres = STM32_YRES, /* Vertical resolution in pixel rows */ - .nplanes = 1, /* Number of color planes supported */ + .nplanes = 1, /* Number of color planes supported */ }; /* This is the standard, NuttX Plane information object */ static const struct lcd_planeinfo_s g_planeinfo = { - .putrun = stm32_putrun, /* Put a run into LCD memory */ - .getrun = stm32_getrun, /* Get a run from LCD memory */ - .buffer = (uint8_t*)g_runbuffer, /* Run scratch buffer */ - .bpp = STM32_BPP, /* Bits-per-pixel */ + .putrun = stm32_putrun, /* Put a run into LCD memory */ + .getrun = stm32_getrun, /* Get a run from LCD memory */ + .buffer = (uint8_t *)g_runbuffer, /* Run scratch buffer */ + .bpp = STM32_BPP, /* Bits-per-pixel */ }; /* This is the standard, NuttX LCD driver object */ @@ -543,6 +561,7 @@ static struct stm32_dev_s g_lcddev = .getplaneinfo = stm32_getplaneinfo, /* LCD RGB Mapping -- Not supported */ + /* Cursor Controls -- Not supported */ /* LCD Specific Controls */ @@ -567,7 +586,8 @@ static struct stm32_dev_s g_lcddev = ****************************************************************************/ #ifdef CONFIG_LCD_REGDEBUG -static void stm32_lcdshow(FAR struct stm32_lower_s *priv, FAR const char *msg) +static void stm32_lcdshow(FAR struct stm32_lower_s *priv, + FAR const char *msg) { _info("%s:\n", msg); _info(" CRTL RS: %d CS: %d RD: %d WR: %d LE: %d\n", @@ -593,7 +613,8 @@ static void stm32_lcdshow(FAR struct stm32_lower_s *priv, FAR const char *msg) * ****************************************************************************/ -static void stm32_writereg(FAR struct stm32_dev_s *priv, uint8_t regaddr, uint16_t regval) +static void stm32_writereg(FAR struct stm32_dev_s *priv, + uint8_t regaddr, uint16_t regval) { /* Make sure that we are configured for output */ @@ -624,7 +645,8 @@ static void stm32_writereg(FAR struct stm32_dev_s *priv, uint8_t regaddr, uint16 * ****************************************************************************/ -static uint16_t stm32_readreg(FAR struct stm32_dev_s *priv, uint8_t regaddr) +static uint16_t stm32_readreg(FAR struct stm32_dev_s *priv, + uint8_t regaddr) { uint16_t regval; @@ -687,7 +709,8 @@ static void stm32_gramselect(FAR struct stm32_dev_s *priv) * ****************************************************************************/ -static inline void stm32_writegram(FAR struct stm32_dev_s *priv, uint16_t rgbval) +static inline void stm32_writegram(FAR struct stm32_dev_s *priv, + uint16_t rgbval) { /* Make sure that we are configured for output */ @@ -735,15 +758,16 @@ static inline uint16_t stm32_readgram(FAR struct stm32_dev_s *priv) * Name: stm32_readnosetup * * Description: - * Prime the operation by reading one pixel from the GRAM memory if necessary for - * this LCD type. When reading 16-bit gram data, there may be some shifts in the - * returned data: + * Prime the operation by reading one pixel from the GRAM memory if + * necessary for this LCD type. When reading 16-bit gram data, there may + * be some shifts in the returned data: * * - ILI932x: Discard first dummy read; no shift in the return data * ****************************************************************************/ -static void stm32_readnosetup(FAR struct stm32_dev_s *priv, FAR uint16_t *accum) +static void stm32_readnosetup(FAR struct stm32_dev_s *priv, + FAR uint16_t *accum) { /* Read-ahead one pixel */ @@ -754,14 +778,16 @@ static void stm32_readnosetup(FAR struct stm32_dev_s *priv, FAR uint16_t *accum) * Name: stm32_readnoshift * * Description: - * Read one correctly aligned pixel from the GRAM memory. Possibly shifting the - * data and possibly swapping red and green components. + * Read one correctly aligned pixel from the GRAM memory. + * Possibly shifting the data and possibly swapping red and green + * components. * * - ILI932x: Unknown -- assuming colors are in the color order * ****************************************************************************/ -static uint16_t stm32_readnoshift(FAR struct stm32_dev_s *priv, FAR uint16_t *accum) +static uint16_t stm32_readnoshift(FAR struct stm32_dev_s *priv, + FAR uint16_t *accum) { /* Read the value (GRAM register already selected) */ @@ -772,12 +798,14 @@ static uint16_t stm32_readnoshift(FAR struct stm32_dev_s *priv, FAR uint16_t *ac * Name: stm32_setcursor * * Description: - * Set the cursor position. In landscape mode, the "column" is actually the physical + * Set the cursor position. + * In landscape mode, the "column" is actually the physical * Y position and the "row" is the physical X position. * ****************************************************************************/ -static void stm32_setcursor(FAR struct stm32_dev_s *priv, uint16_t col, uint16_t row) +static void stm32_setcursor(FAR struct stm32_dev_s *priv, + uint16_t col, uint16_t row) { if (priv->type == LCD_TYPE_ILI9919) { @@ -803,9 +831,11 @@ static void stm32_setcursor(FAR struct stm32_dev_s *priv, uint16_t col, uint16_t ****************************************************************************/ #if 0 /* Sometimes useful */ -static void stm32_dumprun(FAR const char *msg, FAR uint16_t *run, size_t npixels) +static void stm32_dumprun(FAR const char *msg, + FAR uint16_t *run, size_t npixels) { - int i, j; + int i; + int j; syslog(LOG_DEBUG, "\n%s:\n", msg); for (i = 0; i < npixels; i += 16) @@ -836,11 +866,11 @@ static void stm32_dumprun(FAR const char *msg, FAR uint16_t *run, size_t npixels * ****************************************************************************/ -static int stm32_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffer, - size_t npixels) +static int stm32_putrun(fb_coord_t row, fb_coord_t col, + FAR const uint8_t *buffer, size_t npixels) { FAR struct stm32_dev_s *priv = &g_lcddev; - FAR const uint16_t *src = (FAR const uint16_t*)buffer; + FAR const uint16_t *src = (FAR const uint16_t *)buffer; int i; /* Buffer must be provided and aligned to a 16-bit address boundary */ @@ -870,8 +900,8 @@ static int stm32_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffe #elif defined(CONFIG_LCD_RLANDSCAPE) /* Convert coordinates */ - col = (STM32_XRES-1) - col; - row = (STM32_YRES-1) - row; + col = (STM32_XRES - 1) - col; + row = (STM32_YRES - 1) - row; /* Set the cursor position */ @@ -882,14 +912,16 @@ static int stm32_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffe stm32_gramselect(priv); for (i = 0; i < npixels; i++) { - /* Write the next pixel to this position (auto-decrements to the next column) */ + /* Write the next pixel to this position + * (auto-decrements to the next column) + */ stm32_writegram(priv, *src++); } #elif defined(CONFIG_LCD_PORTRAIT) /* Convert coordinates */ - col = (STM32_XRES-1) - col; + col = (STM32_XRES - 1) - col; /* Then write the GRAM data, manually incrementing Y (which is col) */ @@ -906,9 +938,10 @@ static int stm32_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffe col--; } #else /* CONFIG_LCD_RPORTRAIT */ + /* Convert coordinates */ - row = (STM32_YRES-1) - row; + row = (STM32_YRES - 1) - row; /* Then write the GRAM data, manually incrementing Y (which is col) */ @@ -925,6 +958,7 @@ static int stm32_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffe col++; } #endif + return OK; } @@ -942,11 +976,11 @@ static int stm32_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffe * ****************************************************************************/ -static int stm32_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, - size_t npixels) +static int stm32_getrun(fb_coord_t row, fb_coord_t col, + FAR uint8_t *buffer, size_t npixels) { FAR struct stm32_dev_s *priv = &g_lcddev; - FAR uint16_t *dest = (FAR uint16_t*)buffer; + FAR uint16_t *dest = (FAR uint16_t *)buffer; void (*readsetup)(FAR struct stm32_dev_s *priv, FAR uint16_t *accum); uint16_t (*readgram)(FAR struct stm32_dev_s *priv, FAR uint16_t *accum); uint16_t accum; @@ -957,7 +991,9 @@ static int stm32_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); - /* Configure according to the LCD type. Kind of silly with only one LCD type */ + /* Configure according to the LCD type. + * Kind of silly with only one LCD type + */ switch (priv->type) { @@ -1000,8 +1036,8 @@ static int stm32_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, #elif defined(CONFIG_LCD_RLANDSCAPE) /* Convert coordinates */ - col = (STM32_XRES-1) - col; - row = (STM32_YRES-1) - row; + col = (STM32_XRES - 1) - col; + row = (STM32_YRES - 1) - row; /* Set the cursor position */ @@ -1018,14 +1054,16 @@ static int stm32_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, for (i = 0; i < npixels; i++) { - /* Read the next pixel from this position (autoincrements to the next row) */ + /* Read the next pixel from this position + * (autoincrements to the next row) + */ *dest++ = readgram(priv, &accum); } #elif defined(CONFIG_LCD_PORTRAIT) /* Convert coordinates */ - col = (STM32_XRES-1) - col; + col = (STM32_XRES - 1) - col; /* Then read the GRAM data, manually incrementing Y (which is col) */ @@ -1046,7 +1084,7 @@ static int stm32_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, #else /* CONFIG_LCD_RPORTRAIT */ /* Convert coordinates */ - row = (STM32_YRES-1) - row; + row = (STM32_YRES - 1) - row; /* Then write the GRAM data, manually incrementing Y (which is col) */ @@ -1082,7 +1120,8 @@ static int stm32_getvideoinfo(FAR struct lcd_dev_s *dev, { DEBUGASSERT(dev && vinfo); lcdinfo("fmt: %d xres: %d yres: %d nplanes: %d\n", - g_videoinfo.fmt, g_videoinfo.xres, g_videoinfo.yres, g_videoinfo.nplanes); + g_videoinfo.fmt, g_videoinfo.xres, + g_videoinfo.yres, g_videoinfo.nplanes); memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); return OK; } @@ -1095,7 +1134,8 @@ static int stm32_getvideoinfo(FAR struct lcd_dev_s *dev, * ****************************************************************************/ -static int stm32_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno, +static int stm32_getplaneinfo(FAR struct lcd_dev_s *dev, + unsigned int planeno, FAR struct lcd_planeinfo_s *pinfo) { DEBUGASSERT(dev && pinfo && planeno == 0); @@ -1108,8 +1148,9 @@ static int stm32_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno, * Name: stm32_getpower * * Description: - * Get the LCD panel power status (0: full off - CONFIG_LCD_MAXPOWER: full on). On - * backlit LCDs, this setting may correspond to the backlight setting. + * Get the LCD panel power status + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. * ****************************************************************************/ @@ -1125,8 +1166,9 @@ static int stm32_getpower(struct lcd_dev_s *dev) * Name: stm32_poweroff * * Description: - * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: full on). On - * backlit LCDs, this setting may correspond to the backlight setting. + * Enable/disable LCD panel power + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. * ****************************************************************************/ @@ -1146,8 +1188,9 @@ static int stm32_poweroff(FAR struct stm32_dev_s *priv) * Name: stm32_setpower * * Description: - * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: full on). On - * backlit LCDs, this setting may correspond to the backlight setting. + * Enable/disable LCD panel power + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. * ****************************************************************************/ @@ -1302,6 +1345,7 @@ static void stm32_lcdinput(FAR struct stm32_dev_s *priv) stm32_configgpio(g_lcdin[i]); } #endif + /* No longer configured for output */ priv->output = false; @@ -1337,6 +1381,7 @@ static void stm32_lcdoutput(FAR struct stm32_dev_s *priv) stm32_configgpio(g_lcdout[i]); } #endif + /* Now we are configured for output */ priv->output = true; @@ -1352,18 +1397,21 @@ static void stm32_lcdoutput(FAR struct stm32_dev_s *priv) ****************************************************************************/ #if !defined(CONFIG_STM32_ILI9300_DISABLE) || !defined(CONFIG_STM32_ILI9320_DISABLE) || !defined(CONFIG_STM32_ILI9321_DISABLE) -static void stm32_lcd9300init(FAR struct stm32_dev_s *priv, enum lcd_type_e lcdtype) +static void stm32_lcd9300init(FAR struct stm32_dev_s *priv, + enum lcd_type_e lcdtype) { stm32_writereg(priv, LCD_REG_0, 0x0001); /* Start internal OSC */ stm32_writereg(priv, LCD_REG_1, 0x0100); /* Driver Output Control */ stm32_writereg(priv, LCD_REG_2, 0x0700); /* LCD Driver Waveform Control */ - stm32_writereg(priv, LCD_REG_3, 0x1018); /* Set GRAM write direction and BGR=1 (0x1030)*/ + stm32_writereg(priv, LCD_REG_3, 0x1018); /* Set GRAM write direction and BGR=1 (0x1030) */ stm32_writereg(priv, LCD_REG_4, 0x0000); /* Scalling Control */ stm32_writereg(priv, LCD_REG_8, 0x0202); /* Set the back porch and front porch (0x0207) */ stm32_writereg(priv, LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ stm32_writereg(priv, LCD_REG_10, 0x0000); /* Frame Cycle Control */ - stm32_writereg(priv, LCD_REG_12, (1<<0)); /* RGB interface setting (0x0000) */ + + stm32_writereg(priv, LCD_REG_12, (1 << 0)); /* RGB interface setting (0x0000) */ + stm32_writereg(priv, LCD_REG_13, 0x0000); /* Frame Maker Position */ stm32_writereg(priv, LCD_REG_15, 0x0000); /* RGB interface polarity */ @@ -1373,13 +1421,16 @@ static void stm32_lcd9300init(FAR struct stm32_dev_s *priv, enum lcd_type_e lcdt /* Power On sequence */ - stm32_writereg(priv, LCD_REG_16, (1<<12)|(0<<8)|(1<<7)|(1<<6)|(0<<4)); /* Power Control 1 (0x16b0) */ + stm32_writereg(priv, LCD_REG_16, (1 << 12) | (0 << 8) | (1 << 7) | (1 << 6) | (0 << 4)); /* Power Control 1 (0x16b0) */ + stm32_writereg(priv, LCD_REG_17, 0x0007); /* Power Control 2 (0x0001) */ - stm32_writereg(priv, LCD_REG_18, (1<<8)|(1<<4)|(0<<0)); /* Power Control 3 (0x0138) */ + + stm32_writereg(priv, LCD_REG_18, (1 << 8) | (1 << 4) | (0 << 0)); /* Power Control 3 (0x0138) */ + stm32_writereg(priv, LCD_REG_19, 0x0b00); /* VDV[4:0] for VCOM amplitude */ stm32_writereg(priv, LCD_REG_41, 0x0000); /* VCM[4:0] for VCOMH */ - stm32_writereg(priv, LCD_REG_43, (1<<14)|(1<<4)); + stm32_writereg(priv, LCD_REG_43, (1 << 14) | (1 << 4)); stm32_writereg(priv, LCD_REG_80, 0); /* Set X Start */ stm32_writereg(priv, LCD_REG_81, 239); /* Set X End */ @@ -1397,11 +1448,12 @@ static void stm32_lcd9300init(FAR struct stm32_dev_s *priv, enum lcd_type_e lcdt stm32_writereg(priv, LCD_REG_132, 0x0000); /* RAM Address Start? Partial Display 2 */ stm32_writereg(priv, LCD_REG_133, 0x0000); /* RAM Address End? Partial Display 2 */ - stm32_writereg(priv, LCD_REG_144, (0<<7)|(16<<0)); /* Frame Cycle Control (0x0013) */ + stm32_writereg(priv, LCD_REG_144, (0 << 7) | (16 << 0)); /* Frame Cycle Control (0x0013) */ + stm32_writereg(priv, LCD_REG_146, 0x0000); /* Panel Interface Control 2 */ stm32_writereg(priv, LCD_REG_147, 0x0001); /* Panel Interface Control 3 */ stm32_writereg(priv, LCD_REG_149, 0x0110); /* Frame Cycle Control */ - stm32_writereg(priv, LCD_REG_151, (0<<8)); + stm32_writereg(priv, LCD_REG_151, (0 << 8)); stm32_writereg(priv, LCD_REG_152, 0x0000); /* Frame Cycle Control */ up_mdelay(50); stm32_writereg(priv, LCD_REG_7, 0x0000); /* Display off */ @@ -1498,16 +1550,21 @@ static void stm32_lcd9331init(FAR struct stm32_dev_s *priv) ****************************************************************************/ #if !defined(CONFIG_STM32_ILI9325_DISABLE) || !defined(CONFIG_STM32_ILI9328_DISABLE) -static void stm32_lcd9325init(FAR struct stm32_dev_s *priv, enum lcd_type_e lcdtype) +static void stm32_lcd9325init(FAR struct stm32_dev_s *priv, + enum lcd_type_e lcdtype) { stm32_writereg(priv, LCD_REG_227, 0x3008); stm32_writereg(priv, LCD_REG_231, 0x0012); stm32_writereg(priv, LCD_REG_239, 0x1231); /* Set the internal vcore voltage */ -/*stm32_writereg(priv, LCD_REG_231, 0x0010); */ + + /* stm32_writereg(priv, LCD_REG_231, 0x0010); */ + stm32_writereg(priv, LCD_REG_0, 0x0001); /* Start internal osc */ stm32_writereg(priv, LCD_REG_1, 0x0100); /* Set SS and SM bit */ stm32_writereg(priv, LCD_REG_2, 0x0700); /* Power on sequence */ - stm32_writereg(priv, LCD_REG_3, (1<<12)|(1<<5)|(1<<4) ); /* 65K */ + + stm32_writereg(priv, LCD_REG_3, (1 << 12) | (1 << 5) | (1 << 4)); /* 65K */ + stm32_writereg(priv, LCD_REG_4, 0x0000); /* Resize register */ stm32_writereg(priv, LCD_REG_8, 0x0207); /* Set the back porch and front porch */ stm32_writereg(priv, LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ @@ -1843,9 +1900,10 @@ static inline int stm32_lcdinitialize(FAR struct stm32_dev_s *priv) * Name: board_lcd_initialize * * Description: - * Initialize the LCD video hardware. The initial state of the LCD is fully - * initialized, display memory cleared, and the LCD ready to use, but with the power - * setting at 0 (full off). + * Initialize the LCD video hardware. + * The initial state of the LCD is fully initialized, display memory + * cleared, and the LCD ready to use, but with the power setting at 0 + * (full off). * ****************************************************************************/ @@ -1892,8 +1950,8 @@ int board_lcd_initialize(void) * Name: board_lcd_getdev * * Description: - * Return a a reference to the LCD object for the specified LCD. This allows support - * for multiple LCD devices. + * Return a a reference to the LCD object for the specified LCD. + * This allows support for multiple LCD devices. * ****************************************************************************/ @@ -1928,10 +1986,11 @@ void board_lcd_uninitialize(void) * Name: stm32_lcdclear * * Description: - * This is a non-standard LCD interface just for the Shenzhou board. Because - * of the various rotations, clearing the display in the normal way by writing a - * sequences of runs that covers the entire display can be very slow. Here the - * display is cleared by simply setting all GRAM memory to the specified color. + * This is a non-standard LCD interface just for the Shenzhou board. + * Because of the various rotations, clearing the display in the normal + * way by writing a sequences of runs that covers the entire display can + * be very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. * ****************************************************************************/ @@ -1958,7 +2017,7 @@ void stm32_lcdclear(uint16_t color) putreg32(1, LCD_WR_SET); } - putreg32(1, LCD_CS_SET); + putreg32(1, LCD_CS_SET); } #endif /* !HAVE_LCD */ diff --git a/boards/arm/stm32/shenzhou/src/stm32_relays.c b/boards/arm/stm32/shenzhou/src/stm32_relays.c index 3700f3cacc4..c489637da27 100644 --- a/boards/arm/stm32/shenzhou/src/stm32_relays.c +++ b/boards/arm/stm32/shenzhou/src/stm32_relays.c @@ -195,7 +195,7 @@ void up_relaysinit(void) g_relays_init = true; } -void relays_setstat(int relays,bool stat) +void relays_setstat(int relays, bool stat) { if ((unsigned)relays < NUM_RELAYS) { @@ -227,7 +227,7 @@ void relays_setstats(uint32_t relays_stat) for (i = 0; i < NUM_RELAYS; i++) { - relays_setstat(i, (relays_stat & (1<0) + if (mdelay > 0) { if (relays_getstat(relays)) { relays_setstat(relays, false); - nxsig_usleep(RELAYS_MIN_RESET_TIME*1000*1000); + nxsig_usleep(RELAYS_MIN_RESET_TIME * 1000 * 1000); } - relays_setstat(relays,true); - nxsig_usleep(mdelay*100*1000); + relays_setstat(relays, true); + nxsig_usleep(mdelay * 100 * 1000); relays_setstat(relays, false); } } diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_idle.c b/boards/arm/stm32/stm3210e-eval/src/stm32_idle.c index 834af55196d..f807e18506c 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_idle.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_idle.c @@ -62,7 +62,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ + /* Does the board support an IDLE LED to indicate that the board is in the * IDLE state? */ @@ -105,10 +107,10 @@ # error "CONFIG_RTC_ALARM should be enabled to use CONFIG_PM_SLEEP_WAKEUP" # endif - /* If CONFIG_PM_SLEEP_WAKEUP is defined, then CONFIG_PM_SLEEP_WAKEUP_SEC - * and CONFIG_PM_SLEEP_WAKEUP_NSEC define the delay until the STM32 - * awakens from PM_SLEEP mode. - */ +/* If CONFIG_PM_SLEEP_WAKEUP is defined, then CONFIG_PM_SLEEP_WAKEUP_SEC + * and CONFIG_PM_SLEEP_WAKEUP_NSEC define the delay until the STM32 + * awakens from PM_SLEEP mode. + */ # ifndef CONFIG_PM_SLEEP_WAKEUP_SEC # define CONFIG_PM_SLEEP_WAKEUP_SEC 10 @@ -369,6 +371,7 @@ static void stm32_idlepm(void) swarn("WARNING: Cancel alarm failed\n"); } #endif + /* Note: See the additional PM_STANDBY related logic at the * beginning of this function. That logic is executed after * this point. @@ -385,7 +388,8 @@ static void stm32_idlepm(void) /* Configure the RTC alarm to Auto Reset the system */ #ifdef CONFIG_PM_SLEEP_WAKEUP - stm32_rtc_alarm(CONFIG_PM_SLEEP_WAKEUP_SEC, CONFIG_PM_SLEEP_WAKEUP_NSEC, false); + stm32_rtc_alarm(CONFIG_PM_SLEEP_WAKEUP_SEC, + CONFIG_PM_SLEEP_WAKEUP_NSEC, false); #endif /* Wait 10ms */ diff --git a/boards/arm/stm32/stm3210e-eval/src/stm32_pmbuttons.c b/boards/arm/stm32/stm3210e-eval/src/stm32_pmbuttons.c index 882447c7b40..dfc9883b366 100644 --- a/boards/arm/stm32/stm3210e-eval/src/stm32_pmbuttons.c +++ b/boards/arm/stm32/stm3210e-eval/src/stm32_pmbuttons.c @@ -59,6 +59,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ #ifndef CONFIG_ARCH_BUTTONS @@ -148,6 +149,7 @@ * Handle a button wake-up interrupt * ****************************************************************************/ + static int button_handler(int irq, FAR void *context, FAR void *arg) { /* At this point the MCU should have already awakened. The state @@ -189,7 +191,7 @@ void stm32_pmbuttons(void) #ifdef CONFIG_ARCH_IRQBUTTONS for (i = CONFIG_PM_IRQBUTTONS_MIN; i <= CONFIG_PM_IRQBUTTONS_MAX; i++) { - ret = board_button_irq(i, button_handler, (void*)i); + ret = board_button_irq(i, button_handler, (void *)i); if (ret < 0) { serr("ERROR: board_button_irq failed: %d\n", ret); diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c b/boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c index 83b7cf2690d..0bde4497b16 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c +++ b/boards/arm/stm32/stm3220g-eval/src/stm32_lcd.c @@ -69,11 +69,13 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Configuration **********************************************************************/ -/* CONFIG_STM32_ILI9320_DISABLE may be defined to disabled the AM-240320L8TNQW00H - * (LCD_ILI9320 or LCD_ILI9321) - * CONFIG_STM32_ILI9325_DISABLE may be defined to disabled the AM-240320D5TOQW01H - * (LCD_ILI9325) + +/* Configuration ************************************************************/ + +/* CONFIG_STM32_ILI9320_DISABLE may be defined to disabled the + * AM-240320L8TNQW00H (LCD_ILI9320 or LCD_ILI9321) + * CONFIG_STM32_ILI9325_DISABLE may be defined to disabled the + * AM-240320D5TOQW01H (LCD_ILI9325) */ /* Check contrast selection */ @@ -110,7 +112,8 @@ # define CONFIG_LCD_LANDSCAPE 1 #endif -/* Display/Color Properties ***********************************************************/ +/* Display/Color Properties *************************************************/ + /* Display Resolution */ #if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) @@ -126,7 +129,8 @@ #define STM3220G_BPP 16 #define STM3220G_COLORFMT FB_FMT_RGB16_565 -/* STM3220G-EVAL LCD Hardware Definitions *********************************************/ +/* STM3220G-EVAL LCD Hardware Definitions ***********************************/ + /* LCD /CS is CE4, Bank 3 of NOR/SRAM Bank 1~4 */ #define STM3220G_LCDBASE ((uintptr_t)(0x60000000 | 0x08000000)) @@ -287,6 +291,7 @@ struct stm3220g_dev_s /**************************************************************************** * Private Function Protototypes ****************************************************************************/ + /* Low Level LCD access */ static void stm3220g_writereg(uint8_t regaddr, uint16_t regval); @@ -299,17 +304,18 @@ static void stm3220g_setcursor(uint16_t col, uint16_t row); /* LCD Data Transfer Methods */ -static int stm3220g_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffer, - size_t npixels); -static int stm3220g_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, - size_t npixels); +static int stm3220g_putrun(fb_coord_t row, fb_coord_t col, + FAR const uint8_t *buffer, size_t npixels); +static int stm3220g_getrun(fb_coord_t row, fb_coord_t col, + FAR uint8_t *buffer, size_t npixels); /* LCD Configuration */ static int stm3220g_getvideoinfo(FAR struct lcd_dev_s *dev, FAR struct fb_videoinfo_s *vinfo); -static int stm3220g_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno, - FAR struct lcd_planeinfo_s *pinfo); +static int stm3220g_getplaneinfo(FAR struct lcd_dev_s *dev, + unsigned int planeno, + FAR struct lcd_planeinfo_s *pinfo); /* LCD RGB Mapping */ @@ -328,7 +334,8 @@ static int stm3220g_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno static int stm3220g_getpower(struct lcd_dev_s *dev); static int stm3220g_setpower(struct lcd_dev_s *dev, int power); static int stm3220g_getcontrast(struct lcd_dev_s *dev); -static int stm3220g_setcontrast(struct lcd_dev_s *dev, unsigned int contrast); +static int stm3220g_setcontrast(struct lcd_dev_s *dev, + unsigned int contrast); /* Initialization */ @@ -365,10 +372,10 @@ static const struct fb_videoinfo_s g_videoinfo = static const struct lcd_planeinfo_s g_planeinfo = { - .putrun = stm3220g_putrun, /* Put a run into LCD memory */ - .getrun = stm3220g_getrun, /* Get a run from LCD memory */ - .buffer = (uint8_t*)g_runbuffer, /* Run scratch buffer */ - .bpp = STM3220G_BPP, /* Bits-per-pixel */ + .putrun = stm3220g_putrun, /* Put a run into LCD memory */ + .getrun = stm3220g_getrun, /* Get a run from LCD memory */ + .buffer = (uint8_t *)g_runbuffer, /* Run scratch buffer */ + .bpp = STM3220G_BPP, /* Bits-per-pixel */ }; /* This is the standard, NuttX LCD driver object */ @@ -383,6 +390,7 @@ static struct stm3220g_dev_s g_lcddev = .getplaneinfo = stm3220g_getplaneinfo, /* LCD RGB Mapping -- Not supported */ + /* Cursor Controls -- Not supported */ /* LCD Specific Controls */ @@ -462,9 +470,9 @@ static inline void stm3220g_writegram(uint16_t rgbval) * Name: stm3220g_readnosetup * * Description: - * Prime the operation by reading one pixel from the GRAM memory if necessary for - * this LCD type. When reading 16-bit gram data, there may be some shifts in the - * returned data: + * Prime the operation by reading one pixel from the GRAM memory if + * necessary for this LCD type. When reading 16-bit gram data, there may + * be some shifts in the returned data: * * - ILI932x: Discard first dummy read; no shift in the return data * @@ -481,8 +489,9 @@ static void stm3220g_readnosetup(FAR uint16_t *accum) * Name: stm3220g_readnoshift * * Description: - * Read one correctly aligned pixel from the GRAM memory. Possibly shifting the - * data and possibly swapping red and green components. + * Read one correctly aligned pixel from the GRAM memory. + * Possibly shifting the data and possibly swapping red and green + * components. * * - ILI932x: Unknown -- assuming colors are in the color order * @@ -499,8 +508,8 @@ static uint16_t stm3220g_readnoshift(FAR uint16_t *accum) * Name: stm3220g_setcursor * * Description: - * Set the cursor position. In landscape mode, the "column" is actually the physical - * Y position and the "row" is the physical X position. + * Set the cursor position. In landscape mode, the "column" is actually + * the physical Y position and the "row" is the physical X position. * ****************************************************************************/ @@ -522,9 +531,11 @@ static void stm3220g_setcursor(uint16_t col, uint16_t row) ****************************************************************************/ #if 0 /* Sometimes useful */ -static void stm3220g_dumprun(FAR const char *msg, FAR uint16_t *run, size_t npixels) +static void stm3220g_dumprun(FAR const char *msg, + FAR uint16_t *run, size_t npixels) { - int i, j; + int i; + int j; syslog(LOG_DEBUG, "\n%s:\n", msg); for (i = 0; i < npixels; i += 16) @@ -555,10 +566,12 @@ static void stm3220g_dumprun(FAR const char *msg, FAR uint16_t *run, size_t npix * ****************************************************************************/ -static int stm3220g_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffer, - size_t npixels) +static int stm3220g_putrun(fb_coord_t row, + fb_coord_t col, + FAR const uint8_t *buffer, + size_t npixels) { - FAR const uint16_t *src = (FAR const uint16_t*)buffer; + FAR const uint16_t *src = (FAR const uint16_t *)buffer; int i; /* Buffer must be provided and aligned to a 16-bit address boundary */ @@ -592,8 +605,8 @@ static int stm3220g_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *bu * the STM3220G-EVAL is used as the top. */ - col = (STM3220G_XRES-1) - col; - row = (STM3220G_YRES-1) - row; + col = (STM3220G_XRES - 1) - col; + row = (STM3220G_YRES - 1) - row; /* Set the cursor position */ @@ -604,17 +617,20 @@ static int stm3220g_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *bu stm3220g_gramselect(); for (i = 0; i < npixels; i++) { - /* Write the next pixel to this position (auto-decrements to the next column) */ + /* Write the next pixel to this position + * (auto-decrements to the next column) + */ stm3220g_writegram(*src++); } #elif defined(CONFIG_LCD_PORTRAIT) - /* Convert coordinates. In this configuration, the top of the display is to the left - * of the buttons (if the board is held so that the buttons are at the bottom of the - * board). + /* Convert coordinates. + * In this configuration, the top of the display is to the left + * of the buttons (if the board is held so that the buttons are at the + * bottom of the board). */ - col = (STM3220G_XRES-1) - col; + col = (STM3220G_XRES - 1) - col; /* Then write the GRAM data, manually incrementing Y (which is col) */ @@ -631,12 +647,13 @@ static int stm3220g_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *bu col--; } #else /* CONFIG_LCD_RPORTRAIT */ - /* Convert coordinates. In this configuration, the top of the display is to the right - * of the buttons (if the board is held so that the buttons are at the bottom of the - * board). + /* Convert coordinates. + * In this configuration, the top of the display is to the right of the + * buttons (if the board is held so that the buttons are at the bottom of + * the board). */ - row = (STM3220G_YRES-1) - row; + row = (STM3220G_YRES - 1) - row; /* Then write the GRAM data, manually incrementing Y (which is col) */ @@ -653,6 +670,7 @@ static int stm3220g_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *bu col++; } #endif + return OK; } @@ -670,10 +688,10 @@ static int stm3220g_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *bu * ****************************************************************************/ -static int stm3220g_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, - size_t npixels) +static int stm3220g_getrun(fb_coord_t row, fb_coord_t col, + FAR uint8_t *buffer, size_t npixels) { - FAR uint16_t *dest = (FAR uint16_t*)buffer; + FAR uint16_t *dest = (FAR uint16_t *)buffer; void (*readsetup)(FAR uint16_t *accum); uint16_t (*readgram)(FAR uint16_t *accum); uint16_t accum; @@ -684,7 +702,9 @@ static int stm3220g_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); - /* Configure according to the LCD type. Kind of silly with only one LCD type. */ + /* Configure according to the LCD type. + * Kind of silly with only one LCD type. + */ switch (g_lcddev.type) { @@ -723,8 +743,8 @@ static int stm3220g_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, * the STM3220G-EVAL is used as the top. */ - col = (STM3220G_XRES-1) - col; - row = (STM3220G_YRES-1) - row; + col = (STM3220G_XRES - 1) - col; + row = (STM3220G_YRES - 1) - row; /* Set the cursor position */ @@ -740,17 +760,20 @@ static int stm3220g_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, for (i = 0; i < npixels; i++) { - /* Read the next pixel from this position (autoincrements to the next row) */ + /* Read the next pixel from this position + * (autoincrements to the next row) + */ *dest++ = readgram(&accum); } #elif defined(CONFIG_LCD_PORTRAIT) - /* Convert coordinates. In this configuration, the top of the display is to the left - * of the buttons (if the board is held so that the buttons are at the bottom of the - * board). + /* Convert coordinates. + * In this configuration, the top of the display is to the left + * of the buttons (if the board is held so that the buttons are + * at the bottom of the board). */ - col = (STM3220G_XRES-1) - col; + col = (STM3220G_XRES - 1) - col; /* Then read the GRAM data, manually incrementing Y (which is col) */ @@ -768,12 +791,13 @@ static int stm3220g_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, col--; } #else /* CONFIG_LCD_RPORTRAIT */ - /* Convert coordinates. In this configuration, the top of the display is to the right - * of the buttons (if the board is held so that the buttons are at the bottom of the - * board). + /* Convert coordinates. + * In this configuration, the top of the display is to the right + * of the buttons (if the board is held so that the buttons are + * at the bottom of the board). */ - row = (STM3220G_YRES-1) - row; + row = (STM3220G_YRES - 1) - row; /* Then write the GRAM data, manually incrementing Y (which is col) */ @@ -808,7 +832,8 @@ static int stm3220g_getvideoinfo(FAR struct lcd_dev_s *dev, { DEBUGASSERT(dev && vinfo); lcdinfo("fmt: %d xres: %d yres: %d nplanes: %d\n", - g_videoinfo.fmt, g_videoinfo.xres, g_videoinfo.yres, g_videoinfo.nplanes); + g_videoinfo.fmt, g_videoinfo.xres, + g_videoinfo.yres, g_videoinfo.nplanes); memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); return OK; } @@ -821,8 +846,9 @@ static int stm3220g_getvideoinfo(FAR struct lcd_dev_s *dev, * ****************************************************************************/ -static int stm3220g_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno, - FAR struct lcd_planeinfo_s *pinfo) +static int stm3220g_getplaneinfo(FAR struct lcd_dev_s *dev, + unsigned int planeno, + FAR struct lcd_planeinfo_s *pinfo) { DEBUGASSERT(dev && pinfo && planeno == 0); lcdinfo("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp); @@ -834,8 +860,9 @@ static int stm3220g_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno * Name: stm3220g_getpower * * Description: - * Get the LCD panel power status (0: full off - CONFIG_LCD_MAXPOWER: full on). On - * backlit LCDs, this setting may correspond to the backlight setting. + * Get the LCD panel power status + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. * ****************************************************************************/ @@ -849,8 +876,9 @@ static int stm3220g_getpower(struct lcd_dev_s *dev) * Name: stm3220g_poweroff * * Description: - * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: full on). On - * backlit LCDs, this setting may correspond to the backlight setting. + * Enable/disable LCD panel power + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. * ****************************************************************************/ @@ -870,8 +898,9 @@ static int stm3220g_poweroff(void) * Name: stm3220g_setpower * * Description: - * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: full on). On - * backlit LCDs, this setting may correspond to the backlight setting. + * Enable/disable LCD panel power + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. * ****************************************************************************/ @@ -981,7 +1010,11 @@ static inline void stm3220g_lcdinitialize(void) stm3220g_writereg(LCD_REG_1, 0x0100); /* Set SS and SM bit */ stm3220g_writereg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ stm3220g_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ - //stm3220g_writereg(LCD_REG_3, 0x1018); /* Set GRAM write direction and BGR=1. */ + + /* stm3220g_writereg(LCD_REG_3, 0x1018); + * Set GRAM write direction and BGR=1. + */ + stm3220g_writereg(LCD_REG_4, 0x0000); /* Resize register */ stm3220g_writereg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ stm3220g_writereg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ @@ -1016,39 +1049,40 @@ static inline void stm3220g_lcdinitialize(void) #if !defined(CONFIG_STM32_ILI9320_DISABLE) # if !defined(CONFIG_STM32_ILI9325_DISABLE) - if (g_lcddev.type == LCD_TYPE_ILI9320) + if (g_lcddev.type == LCD_TYPE_ILI9320) # endif - { - stm3220g_writereg(LCD_REG_48, 0x0006); - stm3220g_writereg(LCD_REG_49, 0x0101); - stm3220g_writereg(LCD_REG_50, 0x0003); - stm3220g_writereg(LCD_REG_53, 0x0106); - stm3220g_writereg(LCD_REG_54, 0x0b02); - stm3220g_writereg(LCD_REG_55, 0x0302); - stm3220g_writereg(LCD_REG_56, 0x0707); - stm3220g_writereg(LCD_REG_57, 0x0007); - stm3220g_writereg(LCD_REG_60, 0x0600); - stm3220g_writereg(LCD_REG_61, 0x020b); - } + { + stm3220g_writereg(LCD_REG_48, 0x0006); + stm3220g_writereg(LCD_REG_49, 0x0101); + stm3220g_writereg(LCD_REG_50, 0x0003); + stm3220g_writereg(LCD_REG_53, 0x0106); + stm3220g_writereg(LCD_REG_54, 0x0b02); + stm3220g_writereg(LCD_REG_55, 0x0302); + stm3220g_writereg(LCD_REG_56, 0x0707); + stm3220g_writereg(LCD_REG_57, 0x0007); + stm3220g_writereg(LCD_REG_60, 0x0600); + stm3220g_writereg(LCD_REG_61, 0x020b); + } #endif + /* Adjust the Gamma Curve (ILI9325) */ #if !defined(CONFIG_STM32_ILI9325_DISABLE) # if !defined(CONFIG_STM32_ILI9320_DISABLE) - else + else # endif - { - stm3220g_writereg(LCD_REG_48, 0x0007); - stm3220g_writereg(LCD_REG_49, 0x0302); - stm3220g_writereg(LCD_REG_50, 0x0105); - stm3220g_writereg(LCD_REG_53, 0x0206); - stm3220g_writereg(LCD_REG_54, 0x0808); - stm3220g_writereg(LCD_REG_55, 0x0206); - stm3220g_writereg(LCD_REG_56, 0x0504); - stm3220g_writereg(LCD_REG_57, 0x0007); - stm3220g_writereg(LCD_REG_60, 0x0105); - stm3220g_writereg(LCD_REG_61, 0x0808); - } + { + stm3220g_writereg(LCD_REG_48, 0x0007); + stm3220g_writereg(LCD_REG_49, 0x0302); + stm3220g_writereg(LCD_REG_50, 0x0105); + stm3220g_writereg(LCD_REG_53, 0x0206); + stm3220g_writereg(LCD_REG_54, 0x0808); + stm3220g_writereg(LCD_REG_55, 0x0206); + stm3220g_writereg(LCD_REG_56, 0x0504); + stm3220g_writereg(LCD_REG_57, 0x0007); + stm3220g_writereg(LCD_REG_60, 0x0105); + stm3220g_writereg(LCD_REG_61, 0x0808); + } #endif /* Set GRAM area */ @@ -1058,7 +1092,11 @@ static inline void stm3220g_lcdinitialize(void) stm3220g_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ stm3220g_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ stm3220g_writereg(LCD_REG_96, 0x2700); /* Gate Scan Line */ - //stm3220g_writereg(LCD_REG_96, 0xa700); /* Gate Scan Line(GS=1, scan direction is G320~G1) */ + + /* stm3220g_writereg(LCD_REG_96, 0xa700); + * Gate Scan Line(GS=1, scan direction is G320~G1) + */ + stm3220g_writereg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ stm3220g_writereg(LCD_REG_106, 0x0000); /* Set scrolling line */ @@ -1103,9 +1141,10 @@ static inline void stm3220g_lcdinitialize(void) * Name: board_lcd_initialize * * Description: - * Initialize the LCD video hardware. The initial state of the LCD is fully - * initialized, display memory cleared, and the LCD ready to use, but with the power - * setting at 0 (full off). + * Initialize the LCD video hardware. + * The initial state of the LCD is fully initialized, display memory + * cleared, and the LCD ready to use, but with the power setting at 0 + * (full off). * ****************************************************************************/ @@ -1136,8 +1175,8 @@ int board_lcd_initialize(void) * Name: board_lcd_getdev * * Description: - * Return a a reference to the LCD object for the specified LCD. This allows support - * for multiple LCD devices. + * Return a a reference to the LCD object for the specified LCD. + * This allows support for multiple LCD devices. * ****************************************************************************/ @@ -1165,10 +1204,11 @@ void board_lcd_uninitialize(void) * Name: stm3220g_lcdclear * * Description: - * This is a non-standard LCD interface just for the stm3220g-EVAL board. Because - * of the various rotations, clearing the display in the normal way by writing a - * sequences of runs that covers the entire display can be very slow. Here the - * display is cleared by simply setting all GRAM memory to the specified color. + * This is a non-standard LCD interface just for the stm3220g-EVAL board. + * Because of the various rotations, clearing the display in the normal + * way by writing a sequences of runs that covers the entire display can + * be very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. * ****************************************************************************/ @@ -1176,7 +1216,7 @@ void stm3220g_lcdclear(uint16_t color) { uint32_t i = 0; - stm3220g_setcursor(0, STM3220G_XRES-1); + stm3220g_setcursor(0, STM3220G_XRES - 1); stm3220g_gramselect(); for (i = 0; i < STM3220G_XRES * STM3220G_YRES; i++) { diff --git a/boards/arm/stm32/stm3220g-eval/src/stm32_selectlcd.c b/boards/arm/stm32/stm3220g-eval/src/stm32_selectlcd.c index 533c614a64d..752bdbc35a1 100644 --- a/boards/arm/stm32/stm3220g-eval/src/stm32_selectlcd.c +++ b/boards/arm/stm32/stm3220g-eval/src/stm32_selectlcd.c @@ -153,14 +153,17 @@ void stm32_selectlcd(void) /* Bank3 NOR/SRAM timing register configuration */ - putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(0) | - FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); + putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | + FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(0) | + FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | + FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); putreg32(0xffffffff, STM32_FSMC_BWTR3); /* Enable the bank by setting the MBKEN bit */ - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); } #endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c b/boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c index 4d6a12e1225..3a81f7ef5b4 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c +++ b/boards/arm/stm32/stm3240g-eval/src/stm32_lcd.c @@ -69,11 +69,13 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ -/* Configuration **********************************************************************/ -/* CONFIG_STM3240G_ILI9320_DISABLE may be defined to disabled the AM-240320L8TNQW00H - * (LCD_ILI9320 or LCD_ILI9321) - * CONFIG_STM3240G_ILI9325_DISABLE may be defined to disabled the AM-240320D5TOQW01H - * (LCD_ILI9325) + +/* Configuration ************************************************************/ + +/* CONFIG_STM3240G_ILI9320_DISABLE may be defined to disabled the + * AM-240320L8TNQW00H(LCD_ILI9320 or LCD_ILI9321) + * CONFIG_STM3240G_ILI9325_DISABLE may be defined to disabled the + * AM-240320D5TOQW01H(LCD_ILI9325) */ /* Check contrast selection */ @@ -110,7 +112,8 @@ # define CONFIG_LCD_LANDSCAPE 1 #endif -/* Display/Color Properties ***********************************************************/ +/* Display/Color Properties *************************************************/ + /* Display Resolution */ #if defined(CONFIG_LCD_LANDSCAPE) || defined(CONFIG_LCD_RLANDSCAPE) @@ -126,7 +129,8 @@ #define STM3240G_BPP 16 #define STM3240G_COLORFMT FB_FMT_RGB16_565 -/* STM3240G-EVAL LCD Hardware Definitions *********************************************/ +/* STM3240G-EVAL LCD Hardware Definitions ***********************************/ + /* LCD /CS is CE4, Bank 3 of NOR/SRAM Bank 1~4 */ #define STM3240G_LCDBASE ((uintptr_t)(0x60000000 | 0x08000000)) @@ -287,6 +291,7 @@ struct stm3240g_dev_s /**************************************************************************** * Private Function Protototypes ****************************************************************************/ + /* Low Level LCD access */ static void stm3240g_writereg(uint8_t regaddr, uint16_t regval); @@ -299,17 +304,18 @@ static void stm3240g_setcursor(uint16_t col, uint16_t row); /* LCD Data Transfer Methods */ -static int stm3240g_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffer, - size_t npixels); -static int stm3240g_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, - size_t npixels); +static int stm3240g_putrun(fb_coord_t row, fb_coord_t col, + FAR const uint8_t *buffer, size_t npixels); +static int stm3240g_getrun(fb_coord_t row, fb_coord_t col, + FAR uint8_t *buffer, size_t npixels); /* LCD Configuration */ static int stm3240g_getvideoinfo(FAR struct lcd_dev_s *dev, FAR struct fb_videoinfo_s *vinfo); -static int stm3240g_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno, - FAR struct lcd_planeinfo_s *pinfo); +static int stm3240g_getplaneinfo(FAR struct lcd_dev_s *dev, + unsigned int planeno, + FAR struct lcd_planeinfo_s *pinfo); /* LCD RGB Mapping */ @@ -328,7 +334,8 @@ static int stm3240g_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno static int stm3240g_getpower(struct lcd_dev_s *dev); static int stm3240g_setpower(struct lcd_dev_s *dev, int power); static int stm3240g_getcontrast(struct lcd_dev_s *dev); -static int stm3240g_setcontrast(struct lcd_dev_s *dev, unsigned int contrast); +static int stm3240g_setcontrast(struct lcd_dev_s *dev, + unsigned int contrast); /* Initialization */ @@ -365,10 +372,10 @@ static const struct fb_videoinfo_s g_videoinfo = static const struct lcd_planeinfo_s g_planeinfo = { - .putrun = stm3240g_putrun, /* Put a run into LCD memory */ - .getrun = stm3240g_getrun, /* Get a run from LCD memory */ - .buffer = (uint8_t*)g_runbuffer, /* Run scratch buffer */ - .bpp = STM3240G_BPP, /* Bits-per-pixel */ + .putrun = stm3240g_putrun, /* Put a run into LCD memory */ + .getrun = stm3240g_getrun, /* Get a run from LCD memory */ + .buffer = (uint8_t *)g_runbuffer, /* Run scratch buffer */ + .bpp = STM3240G_BPP, /* Bits-per-pixel */ }; /* This is the standard, NuttX LCD driver object */ @@ -383,6 +390,7 @@ static struct stm3240g_dev_s g_lcddev = .getplaneinfo = stm3240g_getplaneinfo, /* LCD RGB Mapping -- Not supported */ + /* Cursor Controls -- Not supported */ /* LCD Specific Controls */ @@ -462,9 +470,9 @@ static inline void stm3240g_writegram(uint16_t rgbval) * Name: stm3240g_readnosetup * * Description: - * Prime the operation by reading one pixel from the GRAM memory if necessary for - * this LCD type. When reading 16-bit gram data, there may be some shifts in the - * returned data: + * Prime the operation by reading one pixel from the GRAM memory if + * necessary for this LCD type. When reading 16-bit gram data, there may + * be some shifts in the returned data: * * - ILI932x: Discard first dummy read; no shift in the return data * @@ -481,8 +489,8 @@ static void stm3240g_readnosetup(FAR uint16_t *accum) * Name: stm3240g_readnoshift * * Description: - * Read one correctly aligned pixel from the GRAM memory. Possibly shifting the - * data and possibly swapping red and green components. + * Read one correctly aligned pixel from the GRAM memory. Possibly + * shifting the data and possibly swapping red and green components. * * - ILI932x: Unknown -- assuming colors are in the color order * @@ -499,8 +507,8 @@ static uint16_t stm3240g_readnoshift(FAR uint16_t *accum) * Name: stm3240g_setcursor * * Description: - * Set the cursor position. In landscape mode, the "column" is actually the physical - * Y position and the "row" is the physical X position. + * Set the cursor position. In landscape mode, the "column" is actually + * the physical Y position and the "row" is the physical X position. * ****************************************************************************/ @@ -522,9 +530,11 @@ static void stm3240g_setcursor(uint16_t col, uint16_t row) ****************************************************************************/ #if 0 /* Sometimes useful */ -static void stm3240g_dumprun(FAR const char *msg, FAR uint16_t *run, size_t npixels) +static void stm3240g_dumprun(FAR const char *msg, + FAR uint16_t *run, size_t npixels) { - int i, j; + int i; + int j; syslog(LOG_DEBUG, "\n%s:\n", msg); for (i = 0; i < npixels; i += 16) @@ -535,6 +545,7 @@ static void stm3240g_dumprun(FAR const char *msg, FAR uint16_t *run, size_t npix { syslog(LOG_DEBUG, " %04x", *run++); } + up_putc('\n'); } } @@ -554,10 +565,11 @@ static void stm3240g_dumprun(FAR const char *msg, FAR uint16_t *run, size_t npix * ****************************************************************************/ -static int stm3240g_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *buffer, - size_t npixels) +static int stm3240g_putrun(fb_coord_t row, fb_coord_t col, + FAR const uint8_t *buffer, + size_t npixels) { - FAR const uint16_t *src = (FAR const uint16_t*)buffer; + FAR const uint16_t *src = (FAR const uint16_t *)buffer; int i; /* Buffer must be provided and aligned to a 16-bit address boundary */ @@ -591,8 +603,8 @@ static int stm3240g_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *bu * the STM3240G-EVAL is used as the top. */ - col = (STM3240G_XRES-1) - col; - row = (STM3240G_YRES-1) - row; + col = (STM3240G_XRES - 1) - col; + row = (STM3240G_YRES - 1) - row; /* Set the cursor position */ @@ -603,17 +615,21 @@ static int stm3240g_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *bu stm3240g_gramselect(); for (i = 0; i < npixels; i++) { - /* Write the next pixel to this position (auto-decrements to the next column) */ + /* Write the next pixel to this position + * (auto-decrements to the next column) + */ stm3240g_writegram(*src++); } #elif defined(CONFIG_LCD_PORTRAIT) - /* Convert coordinates. In this configuration, the top of the display is to the left - * of the buttons (if the board is held so that the buttons are at the bottom of the - * board). + + /* Convert coordinates. + * In this configuration, the top of the display is to the left of the + * buttons (if the board is held so that the buttons are at the bottom of + * the board). */ - col = (STM3240G_XRES-1) - col; + col = (STM3240G_XRES - 1) - col; /* Then write the GRAM data, manually incrementing Y (which is col) */ @@ -630,12 +646,14 @@ static int stm3240g_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *bu col--; } #else /* CONFIG_LCD_RPORTRAIT */ - /* Convert coordinates. In this configuration, the top of the display is to the right - * of the buttons (if the board is held so that the buttons are at the bottom of the - * board). + + /* Convert coordinates. + * In this configuration, the top of the display is to the right of the + * buttons (if the board is held so that the buttons are at the bottom of + * the board). */ - row = (STM3240G_YRES-1) - row; + row = (STM3240G_YRES - 1) - row; /* Then write the GRAM data, manually incrementing Y (which is col) */ @@ -652,6 +670,7 @@ static int stm3240g_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *bu col++; } #endif + return OK; } @@ -669,10 +688,10 @@ static int stm3240g_putrun(fb_coord_t row, fb_coord_t col, FAR const uint8_t *bu * ****************************************************************************/ -static int stm3240g_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, - size_t npixels) +static int stm3240g_getrun(fb_coord_t row, fb_coord_t col, + FAR uint8_t *buffer, size_t npixels) { - FAR uint16_t *dest = (FAR uint16_t*)buffer; + FAR uint16_t *dest = (FAR uint16_t *)buffer; void (*readsetup)(FAR uint16_t *accum); uint16_t (*readgram)(FAR uint16_t *accum); uint16_t accum; @@ -683,7 +702,9 @@ static int stm3240g_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, lcdinfo("row: %d col: %d npixels: %d\n", row, col, npixels); DEBUGASSERT(buffer && ((uintptr_t)buffer & 1) == 0); - /* Configure according to the LCD type. Kind of silly with only one LCD type. */ + /* Configure according to the LCD type. + * Kind of silly with only one LCD type. + */ switch (g_lcddev.type) { @@ -722,8 +743,8 @@ static int stm3240g_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, * the STM3240G-EVAL is used as the top. */ - col = (STM3240G_XRES-1) - col; - row = (STM3240G_YRES-1) - row; + col = (STM3240G_XRES - 1) - col; + row = (STM3240G_YRES - 1) - row; /* Set the cursor position */ @@ -739,17 +760,20 @@ static int stm3240g_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, for (i = 0; i < npixels; i++) { - /* Read the next pixel from this position (autoincrements to the next row) */ + /* Read the next pixel from this position + * (autoincrements to the next row) + */ *dest++ = readgram(&accum); } #elif defined(CONFIG_LCD_PORTRAIT) - /* Convert coordinates. In this configuration, the top of the display is to the left - * of the buttons (if the board is held so that the buttons are at the bottom of the - * board). + /* Convert coordinates. + * In this configuration, the top of the display is to the left of the + * buttons (if the board is held so that the buttons are at the bottom of + * the board). */ - col = (STM3240G_XRES-1) - col; + col = (STM3240G_XRES - 1) - col; /* Then read the GRAM data, manually incrementing Y (which is col) */ @@ -767,12 +791,13 @@ static int stm3240g_getrun(fb_coord_t row, fb_coord_t col, FAR uint8_t *buffer, col--; } #else /* CONFIG_LCD_RPORTRAIT */ - /* Convert coordinates. In this configuration, the top of the display is to the right - * of the buttons (if the board is held so that the buttons are at the bottom of the - * board). + /* Convert coordinates. + * In this configuration, the top of the display is to the right of the + * buttons (if the board is held so that the buttons are at the bottom of + * the board). */ - row = (STM3240G_YRES-1) - row; + row = (STM3240G_YRES - 1) - row; /* Then write the GRAM data, manually incrementing Y (which is col) */ @@ -807,7 +832,8 @@ static int stm3240g_getvideoinfo(FAR struct lcd_dev_s *dev, { DEBUGASSERT(dev && vinfo); lcdinfo("fmt: %d xres: %d yres: %d nplanes: %d\n", - g_videoinfo.fmt, g_videoinfo.xres, g_videoinfo.yres, g_videoinfo.nplanes); + g_videoinfo.fmt, g_videoinfo.xres, + g_videoinfo.yres, g_videoinfo.nplanes); memcpy(vinfo, &g_videoinfo, sizeof(struct fb_videoinfo_s)); return OK; } @@ -820,8 +846,9 @@ static int stm3240g_getvideoinfo(FAR struct lcd_dev_s *dev, * ****************************************************************************/ -static int stm3240g_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno, - FAR struct lcd_planeinfo_s *pinfo) +static int stm3240g_getplaneinfo(FAR struct lcd_dev_s *dev, + unsigned int planeno, + FAR struct lcd_planeinfo_s *pinfo) { DEBUGASSERT(dev && pinfo && planeno == 0); lcdinfo("planeno: %d bpp: %d\n", planeno, g_planeinfo.bpp); @@ -833,8 +860,9 @@ static int stm3240g_getplaneinfo(FAR struct lcd_dev_s *dev, unsigned int planeno * Name: stm3240g_getpower * * Description: - * Get the LCD panel power status (0: full off - CONFIG_LCD_MAXPOWER: full on). On - * backlit LCDs, this setting may correspond to the backlight setting. + * Get the LCD panel power status + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. * ****************************************************************************/ @@ -848,8 +876,9 @@ static int stm3240g_getpower(struct lcd_dev_s *dev) * Name: stm3240g_poweroff * * Description: - * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: full on). On - * backlit LCDs, this setting may correspond to the backlight setting. + * Enable/disable LCD panel power + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. * ****************************************************************************/ @@ -869,8 +898,9 @@ static int stm3240g_poweroff(void) * Name: stm3240g_setpower * * Description: - * Enable/disable LCD panel power (0: full off - CONFIG_LCD_MAXPOWER: full on). On - * backlit LCDs, this setting may correspond to the backlight setting. + * Enable/disable LCD panel power + * (0: full off - CONFIG_LCD_MAXPOWER: full on). On backlit LCDs, + * this setting may correspond to the backlight setting. * ****************************************************************************/ @@ -955,7 +985,9 @@ static inline void stm3240g_lcdinitialize(void) if (id == ILI9325_ID) #endif { - /* Save the LCD type (not actually used at for anything important) */ + /* Save the LCD type + * (not actually used at for anything important) + */ #if !defined(CONFIG_STM3240G_ILI9320_DISABLE) # if !defined(CONFIG_STM3240G_ILI9325_DISABLE) @@ -980,7 +1012,11 @@ static inline void stm3240g_lcdinitialize(void) stm3240g_writereg(LCD_REG_1, 0x0100); /* Set SS and SM bit */ stm3240g_writereg(LCD_REG_2, 0x0700); /* Set 1 line inversion */ stm3240g_writereg(LCD_REG_3, 0x1030); /* Set GRAM write direction and BGR=1. */ - //stm3240g_writereg(LCD_REG_3, 0x1018); /* Set GRAM write direction and BGR=1. */ + + /* stm3240g_writereg(LCD_REG_3, 0x1018); + * Set GRAM write direction and BGR=1. + */ + stm3240g_writereg(LCD_REG_4, 0x0000); /* Resize register */ stm3240g_writereg(LCD_REG_8, 0x0202); /* Set the back porch and front porch */ stm3240g_writereg(LCD_REG_9, 0x0000); /* Set non-display area refresh cycle ISC[3:0] */ @@ -1015,39 +1051,40 @@ static inline void stm3240g_lcdinitialize(void) #if !defined(CONFIG_STM3240G_ILI9320_DISABLE) # if !defined(CONFIG_STM3240G_ILI9325_DISABLE) - if (g_lcddev.type == LCD_TYPE_ILI9320) + if (g_lcddev.type == LCD_TYPE_ILI9320) # endif - { - stm3240g_writereg(LCD_REG_48, 0x0006); - stm3240g_writereg(LCD_REG_49, 0x0101); - stm3240g_writereg(LCD_REG_50, 0x0003); - stm3240g_writereg(LCD_REG_53, 0x0106); - stm3240g_writereg(LCD_REG_54, 0x0b02); - stm3240g_writereg(LCD_REG_55, 0x0302); - stm3240g_writereg(LCD_REG_56, 0x0707); - stm3240g_writereg(LCD_REG_57, 0x0007); - stm3240g_writereg(LCD_REG_60, 0x0600); - stm3240g_writereg(LCD_REG_61, 0x020b); - } + { + stm3240g_writereg(LCD_REG_48, 0x0006); + stm3240g_writereg(LCD_REG_49, 0x0101); + stm3240g_writereg(LCD_REG_50, 0x0003); + stm3240g_writereg(LCD_REG_53, 0x0106); + stm3240g_writereg(LCD_REG_54, 0x0b02); + stm3240g_writereg(LCD_REG_55, 0x0302); + stm3240g_writereg(LCD_REG_56, 0x0707); + stm3240g_writereg(LCD_REG_57, 0x0007); + stm3240g_writereg(LCD_REG_60, 0x0600); + stm3240g_writereg(LCD_REG_61, 0x020b); + } #endif + /* Adjust the Gamma Curve (ILI9325) */ #if !defined(CONFIG_STM3240G_ILI9325_DISABLE) # if !defined(CONFIG_STM3240G_ILI9320_DISABLE) - else + else # endif - { - stm3240g_writereg(LCD_REG_48, 0x0007); - stm3240g_writereg(LCD_REG_49, 0x0302); - stm3240g_writereg(LCD_REG_50, 0x0105); - stm3240g_writereg(LCD_REG_53, 0x0206); - stm3240g_writereg(LCD_REG_54, 0x0808); - stm3240g_writereg(LCD_REG_55, 0x0206); - stm3240g_writereg(LCD_REG_56, 0x0504); - stm3240g_writereg(LCD_REG_57, 0x0007); - stm3240g_writereg(LCD_REG_60, 0x0105); - stm3240g_writereg(LCD_REG_61, 0x0808); - } + { + stm3240g_writereg(LCD_REG_48, 0x0007); + stm3240g_writereg(LCD_REG_49, 0x0302); + stm3240g_writereg(LCD_REG_50, 0x0105); + stm3240g_writereg(LCD_REG_53, 0x0206); + stm3240g_writereg(LCD_REG_54, 0x0808); + stm3240g_writereg(LCD_REG_55, 0x0206); + stm3240g_writereg(LCD_REG_56, 0x0504); + stm3240g_writereg(LCD_REG_57, 0x0007); + stm3240g_writereg(LCD_REG_60, 0x0105); + stm3240g_writereg(LCD_REG_61, 0x0808); + } #endif /* Set GRAM area */ @@ -1057,7 +1094,11 @@ static inline void stm3240g_lcdinitialize(void) stm3240g_writereg(LCD_REG_82, 0x0000); /* Vertical GRAM Start Address */ stm3240g_writereg(LCD_REG_83, 0x013f); /* Vertical GRAM End Address */ stm3240g_writereg(LCD_REG_96, 0x2700); /* Gate Scan Line */ - //stm3240g_writereg(LCD_REG_96, 0xa700); /* Gate Scan Line(GS=1, scan direction is G320~G1) */ + + /* stm3240g_writereg(LCD_REG_96, 0xa700); + * Gate Scan Line(GS=1, scan direction is G320~G1) + */ + stm3240g_writereg(LCD_REG_97, 0x0001); /* NDL,VLE, REV */ stm3240g_writereg(LCD_REG_106, 0x0000); /* Set scrolling line */ @@ -1102,9 +1143,9 @@ static inline void stm3240g_lcdinitialize(void) * Name: board_lcd_initialize * * Description: - * Initialize the LCD video hardware. The initial state of the LCD is fully - * initialized, display memory cleared, and the LCD ready to use, but with the power - * setting at 0 (full off). + * Initialize the LCD video hardware. The initial state of the LCD is + * fully initialized, display memory cleared, and the LCD ready to use, + * but with the power setting at 0 (full off). * ****************************************************************************/ @@ -1135,8 +1176,8 @@ int board_lcd_initialize(void) * Name: board_lcd_getdev * * Description: - * Return a a reference to the LCD object for the specified LCD. This allows support - * for multiple LCD devices. + * Return a a reference to the LCD object for the specified LCD. + * This allows support for multiple LCD devices. * ****************************************************************************/ @@ -1164,10 +1205,11 @@ void board_lcd_uninitialize(void) * Name: stm3240g_lcdclear * * Description: - * This is a non-standard LCD interface just for the stm3240g-EVAL board. Because - * of the various rotations, clearing the display in the normal way by writing a - * sequences of runs that covers the entire display can be very slow. Here the - * display is cleared by simply setting all GRAM memory to the specified color. + * This is a non-standard LCD interface just for the stm3240g-EVAL board. + * Because of the various rotations, clearing the display in the normal way + * by writing a sequences of runs that covers the entire display can be + * very slow. Here the display is cleared by simply setting all GRAM + * memory to the specified color. * ****************************************************************************/ @@ -1175,7 +1217,7 @@ void stm3240g_lcdclear(uint16_t color) { uint32_t i = 0; - stm3240g_setcursor(0, STM3240G_XRES-1); + stm3240g_setcursor(0, STM3240G_XRES - 1); stm3240g_gramselect(); for (i = 0; i < STM3240G_XRES * STM3240G_YRES; i++) { diff --git a/boards/arm/stm32/stm3240g-eval/src/stm32_selectlcd.c b/boards/arm/stm32/stm3240g-eval/src/stm32_selectlcd.c index da2093fa2ac..63a0e61ea01 100644 --- a/boards/arm/stm32/stm3240g-eval/src/stm32_selectlcd.c +++ b/boards/arm/stm32/stm3240g-eval/src/stm32_selectlcd.c @@ -153,14 +153,17 @@ void stm32_selectlcd(void) /* Bank3 NOR/SRAM timing register configuration */ - putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(0) | - FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); + putreg32(FSMC_BTR_ADDSET(5) | FSMC_BTR_ADDHLD(0) | + FSMC_BTR_DATAST(9) | FSMC_BTR_BUSTURN(0) | + FSMC_BTR_CLKDIV(0) | FSMC_BTR_DATLAT(0) | + FSMC_BTR_ACCMODA, STM32_FSMC_BTR3); putreg32(0xffffffff, STM32_FSMC_BWTR3); /* Enable the bank by setting the MBKEN bit */ - putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); + putreg32(FSMC_BCR_MBKEN | FSMC_BCR_SRAM | + FSMC_BCR_MWID16 | FSMC_BCR_WREN, STM32_FSMC_BCR3); } #endif /* CONFIG_STM32_FSMC */ diff --git a/boards/arm/stm32/stm32butterfly2/include/board.h b/boards/arm/stm32/stm32butterfly2/include/board.h index e6e7fd18b9b..9dd0d633d91 100644 --- a/boards/arm/stm32/stm32butterfly2/include/board.h +++ b/boards/arm/stm32/stm32butterfly2/include/board.h @@ -108,7 +108,8 @@ /* LED definitions **********************************************************/ /* There are four LEDs on stm32butterfly2 board that can be controlled by - * software. All pulled high and van be illuminated by driving the output low. + * software. + * All pulled high and van be illuminated by driving the output low. * * LED1 PB0 * LED2 PB1 @@ -131,9 +132,10 @@ #define BOARD_LED3_BIT (1 << BOARD_LED3) #define BOARD_LED4_BIT (1 << BOARD_LED4) -/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is defined. - * In thath case, the usage by the board port is defined in include/board.h and - * src/stm32_leds.c. The LEDs are used to encode OS-related events as follows: +/* These LEDs are not used by the board port unless CONFIG_ARCH_LEDS is + * defined. In thath case, the usage by the board port is defined in + * include/board.h and src/stm32_leds.c. The LEDs are used to encode + * OS-related events as follows: * * SYMBOL Val Meaning LED state * LED1 LED2 LED3 LED4 @@ -150,12 +152,14 @@ #define LED_PANIC 8 /* The system has crashed N/C N/C N/C FLASH */ #undef LED_IDLE /* MCU is is sleep mode Not used */ -/* After booting, LED1-3 are not longer used by the system and can be used for - * other purposes by the application (Of course, all LEDs are available to the - * application if CONFIG_ARCH_LEDS is not defined. +/* After booting, LED1-3 are not longer used by the system and can be used + * for other purposes by the application (Of course, all LEDs are available + * to the application if CONFIG_ARCH_LEDS is not defined. */ -/* ADC configuration. Right now only ADC12_IN10 is supported (potentiometer) */ +/* ADC configuration. Right now only ADC12_IN10 is supported + * (potentiometer) + */ #ifdef CONFIG_STM32_ADC2 # error "CONFIG_STM32_ADC2 is not supported" diff --git a/boards/arm/stm32/stm32f411e-disco/include/board.h b/boards/arm/stm32/stm32f411e-disco/include/board.h index 1edaccc45da..3cf9ab8e7a3 100644 --- a/boards/arm/stm32/stm32f411e-disco/include/board.h +++ b/boards/arm/stm32/stm32f411e-disco/include/board.h @@ -53,10 +53,11 @@ * Pre-processor Definitions ****************************************************************************/ -/* Clocking *************************************************************************/ -/* - * System Clock source : PLLCLK (HSE) - * SYSCLK(Hz) : 96000000 Determined by PLL configuration +/* Clocking *****************************************************************/ + +/* System Clock source : PLLCLK (HSE) + * SYSCLK(Hz) : 96000000 Determined by PLL + * configuration * HCLK(Hz) : 96000000 (STM32_RCC_CFGR_HPRE) * AHB Prescaler : 1 (STM32_RCC_CFGR_HPRE) * APB1 Prescaler : 4 (STM32_RCC_CFGR_PPRE1) @@ -90,13 +91,18 @@ * * Formulae: * - * VCO input frequency = PLL input clock frequency / PLLM, 2 <= PLLM <= 63 - * VCO output frequency = VCO input frequency × PLLN, 192 <= PLLN <= 432 - * PLL output clock frequency = VCO frequency / PLLP, PLLP = 2, 4, 6, or 8 - * USB OTG FS clock frequency = VCO frequency / PLLQ, 2 <= PLLQ <= 15 + * VCO input frequency = PLL input clock frequency / PLLM, + * 2 <= PLLM <= 63 + * VCO output frequency = VCO input frequency × PLLN, + * 192 <= PLLN <= 432 + * PLL output clock frequency = VCO frequency / PLLP, + * PLLP = 2, 4, 6, or 8 + * USB OTG FS clock frequency = VCO frequency / PLLQ, + * 2 <= PLLQ <= 15 * * There is no config for 100 MHz and 48 MHz for usb, - * so we would like to have SYSYCLK=96MHz and we must have the USB clock= 48MHz. + * so we would like to have SYSYCLK=96MHz and we must have the + * USB clock= 48MHz. * * PLLQ = 8 PLLP = 4 PLLN=192 PLLM=4 * @@ -132,6 +138,7 @@ #define STM32_PCLK1_FREQUENCY (STM32_HCLK_FREQUENCY/4) /* Timers driven from APB1 will be twice PCLK1 */ + /* REVISIT */ #define STM32_APB1_TIM2_CLKIN (2*STM32_PCLK1_FREQUENCY) @@ -161,6 +168,7 @@ * otherwise frequency is 2xAPBx. * Note: TIM1,8 are on APB2, others on APB1 */ + /* REVISIT */ #define BOARD_TIM1_FREQUENCY (2 * STM32_PCLK2_FREQUENCY) @@ -179,6 +187,7 @@ * * HCLK=72MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(178+2)=400 KHz */ + /* REVISIT */ #define SDIO_INIT_CLKDIV (178 << SDIO_CLKCR_CLKDIV_SHIFT) @@ -186,6 +195,7 @@ /* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(2+2)=18 MHz * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz */ + /* REVISIT */ #ifdef CONFIG_SDIO_DMA @@ -197,6 +207,7 @@ /* DMA ON: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(1+2)=24 MHz * DMA OFF: HCLK=72 MHz, SDIOCLK=72MHz, SDIO_CK=HCLK/(3+2)=14.4 MHz */ + /* REVISIT */ #ifdef CONFIG_SDIO_DMA @@ -205,9 +216,10 @@ # define SDIO_SDXFR_CLKDIV (3 << SDIO_CLKCR_CLKDIV_SHIFT) #endif -/* DMA Channel/Stream Selections ****************************************************/ -/* Stream selections are arbitrary for now but might become important in the future - * is we set aside more DMA channels/streams. +/* DMA Channel/Stream Selections ********************************************/ + +/* Stream selections are arbitrary for now but might become important in the + * future is we set aside more DMA channels/streams. * * SDIO DMA *   DMAMAP_SDIO_1 = Channel 4, Stream 3 <- may later be used by SPI DMA @@ -223,7 +235,7 @@ #define DMACHAN_SPI2_RX DMAMAP_SPI2_RX #define DMACHAN_SPI2_TX DMAMAP_SPI2_TX -/* Alternate function pin selections ************************************************/ +/* Alternate function pin selections ****************************************/ /* USART1: * RXD: PA10 CN9 pin 3, CN10 pin 33 @@ -303,7 +315,8 @@ /* LEDs * - * The STM32F411E Discovery board has four user leds but only one is configured so far. + * The STM32F411E Discovery board has four user leds but only one is + * configured so far. * LD2 connected to PD12. */ diff --git a/boards/arm/stm32/stm32f411e-disco/src/stm32_boot.c b/boards/arm/stm32/stm32f411e-disco/src/stm32_boot.c index 05fb917ed5e..858d77e9315 100644 --- a/boards/arm/stm32/stm32f411e-disco/src/stm32_boot.c +++ b/boards/arm/stm32/stm32f411e-disco/src/stm32_boot.c @@ -58,9 +58,10 @@ * Name: stm32_boardinitialize * * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. * ****************************************************************************/ @@ -96,10 +97,11 @@ void stm32_boardinitialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. * ****************************************************************************/ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_extmem.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_extmem.c index ad1b8eb2350..428afd2deec 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_extmem.c +++ b/boards/arm/stm32/stm32f429i-disco/src/stm32_extmem.c @@ -86,17 +86,23 @@ /* GPIO configurations common to most external memories */ -static const uint32_t g_sdram_config[] = { +static const uint32_t g_sdram_config[] = +{ /* 16 data lines */ + GPIO_FMC_D0, GPIO_FMC_D1, GPIO_FMC_D2, GPIO_FMC_D3, GPIO_FMC_D4, GPIO_FMC_D5, GPIO_FMC_D6, GPIO_FMC_D7, GPIO_FMC_D8, GPIO_FMC_D9, GPIO_FMC_D10, GPIO_FMC_D11, GPIO_FMC_D12, GPIO_FMC_D13, GPIO_FMC_D14, GPIO_FMC_D15, + /* 12 address lines */ + GPIO_FMC_A0, GPIO_FMC_A1, GPIO_FMC_A2, GPIO_FMC_A3, GPIO_FMC_A4, GPIO_FMC_A5, GPIO_FMC_A6, GPIO_FMC_A7, GPIO_FMC_A8, GPIO_FMC_A9, GPIO_FMC_A10, GPIO_FMC_A11, + /* control lines */ + GPIO_FMC_SDCKE1, GPIO_FMC_SDNE1, GPIO_FMC_SDNWE, GPIO_FMC_NBL0, GPIO_FMC_SDNRAS, GPIO_FMC_NBL1, GPIO_FMC_BA0, GPIO_FMC_BA1, GPIO_FMC_SDCLK, GPIO_FMC_SDNCAS, @@ -127,12 +133,14 @@ void stm32_sdram_initialize(void) volatile int count; /* Enable GPIOs as FMC / memory pins */ + for (i = 0; i < NUM_SDRAM_GPIOS; i++) { stm32_configgpio(g_sdram_config[i]); } /* Enable AHB clocking to the FMC */ + stm32_fmc_enable(); /* Configure and enable the SDRAM bank1 @@ -141,6 +149,7 @@ void stm32_sdram_initialize(void) * 90MHz = 11,11 ns * All timings from the datasheet for Speedgrade -7 (=7ns) */ + val = FMC_SDCR_RPIPE_1 | /* rpipe = 1 hclk */ FMC_SDCR_SDCLK_2X | /* sdclk = 2 hclk */ FMC_SDCR_CAS_LATENCY_3 | /* cas latency = 3 cycles */ @@ -161,6 +170,7 @@ void stm32_sdram_initialize(void) stm32_fmc_sdram_set_timing(2, val); /* SDRAM Initialization sequence */ + stm32_fmc_sdram_command(STM32_SDRAM_CLKEN); /* Clock enable command */ for (count = 0; count < 10000; count++); /* Delay */ stm32_fmc_sdram_command(STM32_SDRAM_PALL); /* Precharge ALL command */ @@ -173,8 +183,10 @@ void stm32_sdram_initialize(void) * Refresh_Rate = 7.81us * Counter = (FMC_CLK * Refresh_Rate) - 20 */ + stm32_fmc_sdram_set_refresh_rate(683); /* Disable write protection */ - // stm32_fmc_sdram_write_protect(2, false); + + /* stm32_fmc_sdram_write_protect(2, false); */ } diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_idle.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_idle.c index dcfe97aad00..abea2a6a0ab 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_idle.c +++ b/boards/arm/stm32/stm32f429i-disco/src/stm32_idle.c @@ -61,7 +61,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ + /* Does the board support an IDLE LED to indicate that the board is in the * IDLE state? */ diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_lcd.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_lcd.c index 2111ce4f3a1..796ff26575e 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_lcd.c +++ b/boards/arm/stm32/stm32f429i-disco/src/stm32_lcd.c @@ -126,8 +126,7 @@ /* Memory access control (MADCTL) */ -/* - * Landscape: 00100000 / 00101000 / h28 +/* Landscape: 00100000 / 00101000 / h28 * * MY: 0 * MX: 0 @@ -241,7 +240,6 @@ ILI9341_MADCTL_RPORTRAIT_BGR | \ ILI9341_MADCTL_RPORTRAIT_MH) - /* Set the display orientation */ #if defined(CONFIG_STM32F429I_DISCO_ILI9341_FBIFACE_LANDSCAPE) @@ -420,7 +418,6 @@ void board_lcd_uninitialize(void) g_lcd = NULL; } - /**************************************************************************** * Name: board_lcd_getdev * @@ -545,7 +542,8 @@ int up_fbinitialize(int display) * * Description: * Return a a reference to the framebuffer object for the specified video - * plane of the specified plane. Many OSDs support multiple planes of video. + * plane of the specified plane. + * Many OSDs support multiple planes of video. * * Input Parameters: * display - In the case of hardware with multiple displays, this diff --git a/boards/arm/stm32/stm32f429i-disco/src/stm32_spi.c b/boards/arm/stm32/stm32f429i-disco/src/stm32_spi.c index 980d5dfaf53..a3d96584860 100644 --- a/boards/arm/stm32/stm32f429i-disco/src/stm32_spi.c +++ b/boards/arm/stm32/stm32f429i-disco/src/stm32_spi.c @@ -56,7 +56,8 @@ FAR struct spi_dev_s *g_spidev5 = NULL; * Name: stm32_spidev_initialize * * Description: - * Called to configure SPI chip select GPIO pins for the stm32f429i-disco board. + * Called to configure SPI chip select GPIO pins for the stm32f429i-disco + * board. * ****************************************************************************/ @@ -77,31 +78,35 @@ void weak_function stm32_spidev_initialize(void) * Name: stm32_spi1/2/3/4/5select and stm32_spi1/2/3/4/5status * * Description: - * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status must be - * provided by board-specific logic. They are implementations of the select - * and status methods of the SPI interface defined by struct spi_ops_s (see - * include/nuttx/spi/spi.h). All other methods (including stm32_spibus_initialize()) - * are provided by common STM32 logic. To use this common SPI logic on your - * board: + * The external functions, stm32_spi1/2/3select and stm32_spi1/2/3status + * must be provided by board-specific logic. They are implementations of + * the select and status methods of the SPI interface defined by struct + * spi_ops_s (see include/nuttx/spi/spi.h). All other methods (including + * stm32_spibus_initialize()) are provided by common STM32 logic. + * To use this common SPI logic on your board: * - * 1. Provide logic in stm32_boardinitialize() to configure SPI chip select - * pins. - * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions in your - * board-specific logic. These functions will perform chip selection and - * status operations using GPIOs in the way your board is configured. - * 3. Add a calls to stm32_spibus_initialize() in your low level application - * initialization logic - * 4. The handle returned by stm32_spibus_initialize() may then be used to bind the - * SPI driver to higher level logic (e.g., calling + * 1. Provide logic in stm32_boardinitialize() to configure SPI chip + * select pins. + * 2. Provide stm32_spi1/2/3select() and stm32_spi1/2/3status() functions + * in your board-specific logic. These functions will perform chip + * selection and status operations using GPIOs in the way your board is + * configured. + * 3. Add a calls to stm32_spibus_initialize() in your low level + * application initialization logic + * 4. The handle returned by stm32_spibus_initialize() may then be used to + * bind the SPI driver to higher level logic (e.g., calling * mmcsd_spislotinitialize(), for example, will bind the SPI driver to * the SPI MMC/SD driver). * ****************************************************************************/ #ifdef CONFIG_STM32_SPI1 -void stm32_spi1select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi1select(FAR struct spi_dev_s *dev, + uint32_t devid, + bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -111,9 +116,12 @@ uint8_t stm32_spi1status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI2 -void stm32_spi2select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi2select(FAR struct spi_dev_s *dev, + uint32_t devid, + bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -123,9 +131,11 @@ uint8_t stm32_spi2status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI3 -void stm32_spi3select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi3select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); } uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) @@ -135,7 +145,8 @@ uint8_t stm32_spi3status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI4 -void stm32_spi4select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi4select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { #if defined(CONFIG_MTD_SST25XX) if (devid == SPIDEV_FLASH(0)) @@ -152,9 +163,11 @@ uint8_t stm32_spi4status(FAR struct spi_dev_s *dev, uint32_t devid) #endif #ifdef CONFIG_STM32_SPI5 -void stm32_spi5select(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) +void stm32_spi5select(FAR struct spi_dev_s *dev, + uint32_t devid, bool selected) { - spiinfo("devid: %d CS: %s\n", (int)devid, selected ? "assert" : "de-assert"); + spiinfo("devid: %d CS: %s\n", + (int)devid, selected ? "assert" : "de-assert"); #if defined(CONFIG_STM32F429I_DISCO_ILI9341) if (devid == SPIDEV_DISPLAY(0)) @@ -254,14 +267,14 @@ int stm32_spi5cmddata(FAR struct spi_dev_s *dev, uint32_t devid, bool cmd) * * Description: * Initialize the selected SPI port. - * As long as the method stm32_spibus_initialize recognized the initialized state of - * the spi device by the spi enable flag of the cr1 register, it isn't safe to - * disable the spi device outside of the nuttx spi interface structure. But - * this has to be done as long as the nuttx spi interface doesn't support - * bidirectional data transfer for multiple devices share one spi bus. This - * wrapper does nothing else than store the initialized state of the spi - * device after the first initializing and should be used by each driver who - * shares the spi5 bus. + * As long as the method stm32_spibus_initialize recognized the initialized + * state of the spi device by the spi enable flag of the cr1 register, it + * isn't safe to disable the spi device outside of the nuttx spi interface + * structure. But this has to be done as long as the nuttx spi interface + * doesn't support bidirectional data transfer for multiple devices share + * one spi bus. This wrapper does nothing else than store the initialized + * state of the spi device after the first initializing and should be used + * by each driver who shares the spi5 bus. * * Input Parameters: * diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_enc28j60.c b/boards/arm/stm32/stm32f4discovery/src/stm32_enc28j60.c index dc4f3d482cf..acd7dd7b35b 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_enc28j60.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_enc28j60.c @@ -20,14 +20,14 @@ /* 2MBit SPI FLASH OR ENC28J60 * - * --- ------ -------------- ----------------------------------------------------- + * -- ---- ------------ ----------------------------------------------------- * PIN NAME SIGNAL NOTES - * --- ------ -------------- ----------------------------------------------------- + * -- ---- ------------ ----------------------------------------------------- * - * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH */ /**************************************************************************** @@ -62,15 +62,19 @@ /* ENC28J60 * - * --- ------ -------------- ----------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * PIN NAME SIGNAL NOTES - * --- ------ -------------- ----------------------------------------------------- + * --- ------ -------------- ------------------------------------------------ * * 29 PA4 PA4-SPI1-NSS 10Mbit ENC28J60, SPI 2M FLASH - * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, 10Mbit ENC28J60, SPI 2M FLASH - * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, 10Mbit EN28J60 Reset + * 30 PA5 PA5-SPI1-SCK 2.4" TFT + Touchscreen, + * 10Mbit ENC28J60, SPI 2M FLASH + * 31 PA6 PA6-SPI1-MISO 2.4" TFT + Touchscreen, + * 10Mbit ENC28J60, SPI 2M FLASH + * 32 PA7 PA7-SPI1-MOSI 2.4" TFT + Touchscreen, + * 10Mbit ENC28J60, SPI 2M FLASH + * 98 PE1 PE1-FSMC_NBL1 2.4" TFT + Touchscreen, + * 10Mbit EN28J60 Reset * 4 PE5 (no name) 10Mbps ENC28J60 Interrupt */ @@ -181,7 +185,8 @@ void arm_netinitialize(void) /* Assumptions: * 1) ENC28J60 pins were configured in up_spi.c early in the boot-up phase. - * 2) Clocking for the SPI1 peripheral was also provided earlier in boot-up. + * 2) Clocking for the SPI1 peripheral was also provided earlier in + * boot-up. */ spi = stm32_spibus_initialize(ENC28J60_SPI_PORTNO); @@ -191,7 +196,7 @@ void arm_netinitialize(void) return; } - /* Take ENC28J60 out of reset (active low)*/ + /* Take ENC28J60 out of reset (active low) */ stm32_gpiowrite(GPIO_ENC28J60_RESET, true); diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_idle.c b/boards/arm/stm32/stm32f4discovery/src/stm32_idle.c index 0412fe62868..9d062d53e39 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_idle.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_idle.c @@ -61,7 +61,9 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ + /* Does the board support an IDLE LED to indicate that the board is in the * IDLE state? */ diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_pmbuttons.c b/boards/arm/stm32/stm32f4discovery/src/stm32_pmbuttons.c index 10082ad70d3..d9495cd0f5b 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_pmbuttons.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_pmbuttons.c @@ -59,6 +59,7 @@ /**************************************************************************** * Pre-processor Definitions ****************************************************************************/ + /* Configuration ************************************************************/ #ifndef CONFIG_ARCH_BUTTONS diff --git a/boards/arm/stm32/stm32f4discovery/src/stm32_timer.c b/boards/arm/stm32/stm32f4discovery/src/stm32_timer.c index b41f7e1a249..8776124c181 100644 --- a/boards/arm/stm32/stm32f4discovery/src/stm32_timer.c +++ b/boards/arm/stm32/stm32f4discovery/src/stm32_timer.c @@ -64,7 +64,8 @@ * Configure the timer driver. * * Input Parameters: - * devpath - The full path to the timer device. This should be of the form /dev/timer0 + * devpath - The full path to the timer device. + * This should be of the form /dev/timer0 * timer - The timer's number. * * Returned Value: diff --git a/boards/arm/stm32/stm32vldiscovery/include/board.h b/boards/arm/stm32/stm32vldiscovery/include/board.h index a55d1634e4f..590f500983f 100644 --- a/boards/arm/stm32/stm32vldiscovery/include/board.h +++ b/boards/arm/stm32/stm32vldiscovery/include/board.h @@ -52,13 +52,15 @@ * Pre-processor Definitions ****************************************************************************/ -/* Clocking *************************************************************************/ +/* Clocking *****************************************************************/ /* On-board crystal frequency is 8MHz (HSE) */ #define STM32_BOARD_XTAL 8000000ul -/* PLL source is HSE / 1, PLL multiplier is 3: PLL output frequency is 8MHz (XTAL) x 3 = 24MHz */ +/* PLL source is HSE / 1, + * PLL multiplier is 3: PLL output frequency is 8MHz (XTAL) x 3 = 24MHz + */ #define STM32_CFGR2_PREDIV1 RCC_CFGR2_PREDIV1d1 #define STM32_CFGR_PLLSRC RCC_CFGR_PLLSRC @@ -108,7 +110,8 @@ /* Timer Frequencies, if APBx is set to 1, frequency is same to APBx * otherwise frequency is 2xAPBx. - * Note: TIM1,15-17 are on APB2, others on APB1 */ + * Note: TIM1,15-17 are on APB2, others on APB1 + */ #define BOARD_TIM1_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_TIM2_FREQUENCY STM32_HCLK_FREQUENCY @@ -119,11 +122,12 @@ #define BOARD_TIM7_FREQUENCY STM32_HCLK_FREQUENCY #define BOARD_TIM8_FREQUENCY STM32_HCLK_FREQUENCY -/* LED definitions ******************************************************************/ +/* LED definitions **********************************************************/ -/* It is assumed that a generic board has 1 LED. Thus only two different states - * can be shown. Statuses defined as "1" will light the LED, the ones defined as - * "0" will turn the LED off. */ +/* It is assumed that a generic board has 1 LED. Thus only two different + * states can be shown. Statuses defined as "1" will light the LED, the + * ones defined as "0" will turn the LED off. + */ #define LED_STARTED 1 #define LED_HEAPALLOCATE 1 @@ -134,7 +138,7 @@ #define LED_ASSERTION 0 #define LED_PANIC 0 -/* Button definitions ***************************************************************/ +/* Button definitions *******************************************************/ /* It is assumed that a generic board has 1 button. */ diff --git a/boards/arm/stm32/stm32vldiscovery/src/stm32_boot.c b/boards/arm/stm32/stm32vldiscovery/src/stm32_boot.c index a0fafc632b7..a05b19d69c3 100644 --- a/boards/arm/stm32/stm32vldiscovery/src/stm32_boot.c +++ b/boards/arm/stm32/stm32vldiscovery/src/stm32_boot.c @@ -56,9 +56,10 @@ * Name: stm32_boardinitialize * * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All STM32 architectures must provide the following entry point. + * This entry point is called early in the initialization -- after all + * memory has been configured and mapped but before any devices have been + * initialized. * ****************************************************************************/ @@ -77,10 +78,11 @@ void stm32_boardinitialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. * ****************************************************************************/ diff --git a/boards/arm/stm32/stm32vldiscovery/src/stm32_leds.c b/boards/arm/stm32/stm32vldiscovery/src/stm32_leds.c index 4da35b668f4..96dcbbde07c 100644 --- a/boards/arm/stm32/stm32vldiscovery/src/stm32_leds.c +++ b/boards/arm/stm32/stm32vldiscovery/src/stm32_leds.c @@ -75,9 +75,9 @@ void stm32_led_initialize(void) void board_autoled_on(int led) { if (led == 1) - { - stm32_gpiowrite(GPIO_LED1, true); - } + { + stm32_gpiowrite(GPIO_LED1, true); + } } /**************************************************************************** @@ -88,7 +88,7 @@ void board_autoled_off(int led) { if (led == 0) { - stm32_gpiowrite(GPIO_LED1, false); + stm32_gpiowrite(GPIO_LED1, false); } } diff --git a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c index 266e9d36967..2e22e0d6454 100644 --- a/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c +++ b/boards/arm/stm32f0l0g0/nucleo-g070rb/src/stm32_boot.c @@ -94,7 +94,9 @@ void stm32_boardinitialize(void) #ifdef CONFIG_BOARD_LATE_INITIALIZE void board_late_initialize(void) { - /* Perform board bring-up here instead of from the board_app_initialize(). */ + /* Perform board bring-up here instead of from the + * board_app_initialize(). + */ stm32_bringup(); } diff --git a/boards/arm/stm32f7/nucleo-144/src/stm32_dma_alloc.c b/boards/arm/stm32f7/nucleo-144/src/stm32_dma_alloc.c index a16d6a067c5..8e571be05dd 100644 --- a/boards/arm/stm32f7/nucleo-144/src/stm32_dma_alloc.c +++ b/boards/arm/stm32f7/nucleo-144/src/stm32_dma_alloc.c @@ -65,14 +65,16 @@ static GRAN_HANDLE dma_allocator; /* The DMA heap size constrains the total number of things that can be * ready to do DMA at a time. * - * For example, FAT DMA depends on one sector-sized buffer per filesystem plus - * one sector-sized buffer per file. + * For example, FAT DMA depends on one sector-sized buffer per filesystem + * plus one sector-sized buffer per file. * * We use a fundamental alignment / granule size of 64B; this is sufficient - * to guarantee alignment for the largest STM32 DMA burst (16 beats x 32bits). + * to guarantee alignment for the largest STM32 DMA burst + * (16 beats x 32bits). */ -static uint8_t g_dma_heap[BOARD_DMA_ALLOC_POOL_SIZE] __attribute__((aligned(64))); +static +uint8_t g_dma_heap[BOARD_DMA_ALLOC_POOL_SIZE] __attribute__((aligned(64))); /**************************************************************************** * Public Functions diff --git a/boards/arm/stm32f7/stm32f746-ws/include/board.h b/boards/arm/stm32f7/stm32f746-ws/include/board.h index 1e5de30363f..1257a06ea4f 100644 --- a/boards/arm/stm32f7/stm32f746-ws/include/board.h +++ b/boards/arm/stm32f7/stm32f746-ws/include/board.h @@ -57,8 +57,10 @@ /* The STM32F7 Discovery board provides the following clock sources: * - * X1: 24 MHz oscillator for USB OTG HS PHY and camera module (daughter board) - * X2: 25 MHz oscillator for STM32F746NGH6 microcontroller and Ethernet PHY. + * X1: 24 MHz oscillator for USB OTG HS PHY and camera module + * (daughter board) + * X2: 25 MHz oscillator for STM32F746NGH6 microcontroller and + * Ethernet PHY. * X3: 32.768 KHz crystal for STM32F746NGH6 embedded RTC * * So we have these clock source available within the STM32 @@ -249,8 +251,8 @@ /* SDMMC */ -/* Stream selections are arbitrary for now but might become important in the future - * if we set aside more DMA channels/streams. +/* Stream selections are arbitrary for now but might become important in the + * future if we set aside more DMA channels/streams. * * SDIO DMA * DMAMAP_SDMMC1_1 = Channel 4, Stream 3 diff --git a/boards/arm/stm32f7/stm32f746-ws/src/stm32_dma_alloc.c b/boards/arm/stm32f7/stm32f746-ws/src/stm32_dma_alloc.c index e55573e4a7e..1748f06ff19 100644 --- a/boards/arm/stm32f7/stm32f746-ws/src/stm32_dma_alloc.c +++ b/boards/arm/stm32f7/stm32f746-ws/src/stm32_dma_alloc.c @@ -65,14 +65,16 @@ static GRAN_HANDLE dma_allocator; /* The DMA heap size constrains the total number of things that can be * ready to do DMA at a time. * - * For example, FAT DMA depends on one sector-sized buffer per filesystem plus - * one sector-sized buffer per file. + * For example, FAT DMA depends on one sector-sized buffer per filesystem + * plus one sector-sized buffer per file. * * We use a fundamental alignment / granule size of 64B; this is sufficient - * to guarantee alignment for the largest STM32 DMA burst (16 beats x 32bits). + * to guarantee alignment for the largest STM32 DMA burst + * (16 beats x 32bits). */ -static uint8_t g_dma_heap[BOARD_DMA_ALLOC_POOL_SIZE] __attribute__((aligned(64))); +static +uint8_t g_dma_heap[BOARD_DMA_ALLOC_POOL_SIZE] __attribute__((aligned(64))); /**************************************************************************** * Public Functions diff --git a/boards/arm/stm32h7/nucleo-h743zi/include/board.h b/boards/arm/stm32h7/nucleo-h743zi/include/board.h index 8f32ce614dd..02b57e6f804 100644 --- a/boards/arm/stm32h7/nucleo-h743zi/include/board.h +++ b/boards/arm/stm32h7/nucleo-h743zi/include/board.h @@ -86,7 +86,8 @@ * - SB148, SB8 and SB9 OFF * - SB112 and SB149 ON * - * When STM32_HSE_FREQUENCY / PLLM <= 2MHz VCOL must be selected. VCOH otherwise. + * When STM32_HSE_FREQUENCY / PLLM <= 2MHz VCOL must be selected. + * VCOH otherwise. * * PLL_VCOx = (STM32_HSE_FREQUENCY / PLLM) * PLLN * Subject to: @@ -287,7 +288,9 @@ #define STM32_SDMMC_INIT_CLKDIV (250 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) -/* Just set these to 25 MHz for now, PLL1Q/(2*4), for default speed 12.5MB/s */ +/* Just set these to 25 MHz for now, + * PLL1Q/(2*4), for default speed 12.5MB/s + */ #define STM32_SDMMC_MMCXFR_CLKDIV (4 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) #define STM32_SDMMC_SDXFR_CLKDIV (4 << STM32_SDMMC_CLKCR_CLKDIV_SHIFT) @@ -302,11 +305,12 @@ /* LED definitions **********************************************************/ -/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, LD2 a Blue - * LED and LD3 a Red LED, that can be controlled by software. The following - * definitions assume the default Solder Bridges are installed. +/* The Nucleo-144 board has numerous LEDs but only three, LD1 a Green LED, + * LD2 a Blue LED and LD3 a Red LED, that can be controlled by software. + * The following definitions assume the default Solder Bridges are installed. * - * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in any way. + * If CONFIG_ARCH_LEDS is not defined, then the user can control the LEDs in + * any way. * The following definitions are used to access individual LEDs. */ @@ -328,13 +332,14 @@ #define BOARD_LED3_BIT (1 << BOARD_LED3) /* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in - * include/board.h and src/stm32_leds.c. The LEDs are used to encode OS-related - * events as follows: + * include/board.h and src/stm32_leds.c. + * The LEDs are used to encode OS-related events as follows: * * * SYMBOL Meaning LED state * Red Green Blue - * ---------------------- -------------------------- ------ ------ ----*/ + * ---------------------- -------------------------- ------ ------ --- + */ #define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ #define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/include/board.h b/boards/arm/stm32l4/b-l475e-iot01a/include/board.h index 17f845eb8ef..3aa220c0086 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/include/board.h +++ b/boards/arm/stm32l4/b-l475e-iot01a/include/board.h @@ -79,7 +79,8 @@ * * ------------------- ---------------------------- ------ * SYMBOL Meaning LED - * ------------------- ---------------------------- ------ */ + * ------------------- ---------------------------- ------ + */ #define LED_STARTED 0 /* NuttX has been started OFF */ #define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ diff --git a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c index 1535a3a254d..bf2a5f895c2 100644 --- a/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c +++ b/boards/arm/stm32l4/b-l475e-iot01a/src/stm32_boot.c @@ -54,16 +54,18 @@ * Name: stm32l4_board_initialize * * Description: - * All STM32L4 architectures must provide the following entry point. This entry - * point is called early in the initialization -- after all memory has been - * configured and mapped but before any devices have been initialized. + * All STM32L4 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. * ****************************************************************************/ void stm32l4_board_initialize(void) { #if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || defined(CONFIG_STM32L4_SPI3) - /* Configure SPI chip selects if 1) SPI is not disabled, and 2) the weak function + /* Configure SPI chip selects if + * 1) SPI is not disabled, and 2) the weak function * stm32l4_spidev_initialize() has been brought into the link. */ @@ -86,10 +88,11 @@ void stm32l4_board_initialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_intitialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_intitialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. * ****************************************************************************/ diff --git a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c index 09c253ddbb3..ee8a74ea8eb 100644 --- a/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c +++ b/boards/arm/stm32l4/nucleo-l476rg/src/stm32_boot.c @@ -59,9 +59,10 @@ * Name: stm32l4_board_initialize * * Description: - * All STM32L4 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All STM32L4 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. * ****************************************************************************/ @@ -73,8 +74,8 @@ void stm32l4_board_initialize(void) board_autoled_initialize(); #endif - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak function - * stm32l4_spiinitialize() has been brought into the link. + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak + * function stm32l4_spiinitialize() has been brought into the link. */ #if defined(CONFIG_STM32L4_SPI1) || defined(CONFIG_STM32L4_SPI2) || defined(CONFIG_STM32L4_SPI3) @@ -82,8 +83,8 @@ void stm32l4_board_initialize(void) #endif /* Initialize USB is 1) USBDEV is selected, 2) the USB controller is not - * disabled, and 3) the weak function stm32l4_usbinitialize() has been brought - * into the build. + * disabled, and 3) the weak function stm32l4_usbinitialize() has been + * brought into the build. */ #if defined(CONFIG_USBDEV) && defined(CONFIG_STM32L4_USB) @@ -97,10 +98,11 @@ void stm32l4_board_initialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase phase may be used, for example, to initialize board-specific + * device drivers. * ****************************************************************************/ @@ -108,8 +110,8 @@ void stm32l4_board_initialize(void) void board_late_initialize(void) { /* Perform NSH initialization here instead of from the NSH. This - * alternative NSH initialization is necessary when NSH is ran in user-space - * but the initialization function must run in kernel space. + * alternative NSH initialization is necessary when NSH is ran in + * user-space but the initialization function must run in kernel space. */ #if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_NSH_ARCHINIT) diff --git a/boards/arm/stm32l4/nucleo-l496zg/include/board.h b/boards/arm/stm32l4/nucleo-l496zg/include/board.h index 4cd3f8af09d..675efe017a9 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/include/board.h +++ b/boards/arm/stm32l4/nucleo-l496zg/include/board.h @@ -88,9 +88,10 @@ /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz * - * XXX NOTE: currently the main PLL is implicitly turned on and is implicitly - * the system clock; this should be configurable since not all applications may - * want things done this way. + * XXX NOTE: + * currently the main PLL is implicitly turned on and is implicitly + * the system clock; this should be configurable since not all + * applications may want things done this way. */ #define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) @@ -198,9 +199,10 @@ /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 8 MHz / 1 * 20 / 2 = 80 MHz * - * XXX NOTE: currently the main PLL is implicitly turned on and is implicitly - * the system clock; this should be configurable since not all applications may - * want things done this way. + * XXX NOTE: + * currently the main PLL is implicitly turned on and is implicitly + * the system clock; this should be configurable since not all + * applications may want things done this way. */ #define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(20) @@ -309,9 +311,10 @@ /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 4 MHz / 1 * 40 / 2 = 80 MHz * - * XXX NOTE: currently the main PLL is implicitly turned on and is implicitly - * the system clock; this should be configurable since not all applications may - * want things done this way. + * XXX NOTE: + * currently the main PLL is implicitly turned on and is implicitly + * the system clock; this should be configurable since not all + * applications may want things done this way. */ #define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(40) @@ -429,7 +432,8 @@ #define BOARD_LPTIM1_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) #define BOARD_LPTIM2_FREQUENCY (STM32L4_HCLK_FREQUENCY / 2) -/* SDMMC dividers. Note that slower clocking is required when DMA is disabled +/* SDMMC dividers. + * Note that slower clocking is required when DMA is disabled * in order to avoid RX overrun/TX underrun errors due to delayed responses * to service FIFOs in interrupt driven mode. These values have not been * tuned!!! @@ -485,7 +489,6 @@ #define DMAMAP_SDMMC1 DMACHAN_SDMMC_1 #define DMAMAP_SDMMC2 DMACHAN_SDMMC_2 - /* FLASH wait states * * --------- ---------- ----------- @@ -529,13 +532,14 @@ #define BOARD_LED3_BIT (1 << BOARD_LED3) /* If CONFIG_ARCH_LEDS is defined, the usage by the board port is defined in - * include/board.h and src/stm32_autoleds.c. The LEDs are used to encode OS-related - * events as follows: + * include/board.h and src/stm32_autoleds.c. The LEDs are used to encode + * OS-related events as follows: * * * SYMBOL Meaning LED state * Red Green Blue - * ---------------------- -------------------------- ------ ------ ----*/ + * ---------------------- -------------------------- ------ ------ ---- + */ #define LED_STARTED 0 /* NuttX has been started OFF OFF OFF */ #define LED_HEAPALLOCATE 1 /* Heap has been allocated OFF OFF ON */ @@ -574,8 +578,8 @@ #if defined(CONFIG_NUCLEO_CONSOLE_ARDUINO) /* USART6: * - * These configurations assume that you are using a standard Arduio RS-232 shield - * with the serial interface with RX on pin D0 and TX on pin D1: + * These configurations assume that you are using a standard Arduio RS-232 + * shield with the serial interface with RX on pin D0 and TX on pin D1: * * -------- --------------- * STM32F7 @@ -595,7 +599,9 @@ */ #if defined(CONFIG_NUCLEO_CONSOLE_VIRTUAL) -/* LPUART1 is connector to Virtual COM port PG6 and PG7, but there is no lpserial. */ +/* LPUART1 is connector to Virtual COM port PG6 and PG7, + * but there is no lpserial. + */ /* #define GPIO_USART2_TX GPIO_LPUART1_TX_3 */ @@ -688,9 +694,10 @@ extern "C" * Name: stm32l4_board_initialize * * Description: - * All STM32 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All STM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. * ****************************************************************************/ diff --git a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dma_alloc.c b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dma_alloc.c index c5c3b3a4736..9fe2e05a641 100644 --- a/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dma_alloc.c +++ b/boards/arm/stm32l4/nucleo-l496zg/src/stm32_dma_alloc.c @@ -65,14 +65,16 @@ static GRAN_HANDLE dma_allocator; /* The DMA heap size constrains the total number of things that can be * ready to do DMA at a time. * - * For example, FAT DMA depends on one sector-sized buffer per filesystem plus - * one sector-sized buffer per file. + * For example, FAT DMA depends on one sector-sized buffer per filesystem + * plus one sector-sized buffer per file. * * We use a fundamental alignment / granule size of 64B; this is sufficient - * to guarantee alignment for the largest STM32 DMA burst (16 beats x 32bits). + * to guarantee alignment for the largest STM32 DMA burst + * (16 beats x 32bits). */ -static uint8_t g_dma_heap[BOARD_DMA_ALLOC_POOL_SIZE] __attribute__((aligned(64))); +static +uint8_t g_dma_heap[BOARD_DMA_ALLOC_POOL_SIZE] __attribute__((aligned(64))); /**************************************************************************** * Public Functions diff --git a/boards/arm/stm32l4/stm32l476-mdk/include/board.h b/boards/arm/stm32l4/stm32l476-mdk/include/board.h index 2cad21659da..8157e655c96 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/include/board.h +++ b/boards/arm/stm32l4/stm32l476-mdk/include/board.h @@ -122,8 +122,8 @@ * When the I/O is HIGH value, the LED is OFF. * When the I/O is LOW, the LED is ON. * - * Following this convention, only the white LED is made available even though they - * all could be user-application controlled if desired. + * Following this convention, only the white LED is made available even + * though they all could be user-application controlled if desired. */ /* LED index values for use with board_userled() */ @@ -145,14 +145,15 @@ # define BOARD_WHITE_LED_BIT (1 << BOARD_WHITE_LED) #endif -/* None of the LEDs are used by the board port unless CONFIG_ARCH_LEDS is defined. - * In that case, the white LED (only) will be controlled. Usage by the board port - * is defined in include/board.h and src/stm32_autoleds.c. The white LED will be - * used to encode OS-related events as follows: +/* None of the LEDs are used by the board port unless CONFIG_ARCH_LEDS is + * defined. In that case, the white LED (only) will be controlled. Usage by + * the board port is defined in include/board.h and src/stm32_autoleds.c. + * The white LED will be used to encode OS-related events as follows: * * ------------------- ---------------------------- ------ * SYMBOL Meaning LED - * ------------------- ---------------------------- ------ */ + * ------------------- ---------------------------- ------ + */ #define LED_STARTED 0 /* NuttX has been started OFF */ #define LED_HEAPALLOCATE 0 /* Heap has been allocated OFF */ @@ -164,9 +165,10 @@ #define LED_PANIC 3 /* The system has crashed FLASH */ #undef LED_IDLE /* MCU is is sleep mode Not used */ -/* Thus if the white LED is statically on, NuttX has successfully booted and is, - * apparently, running normally. If white LED is flashing at approximately 2Hz, - * then a fatal error has been detected and the system has halted. +/* Thus if the white LED is statically on, NuttX has successfully booted and + * is, apparently, running normally. If white LED is flashing at + * approximately 2Hz, then a fatal error has been detected and the system has + * halted. */ /* Buttons ******************************************************************/ @@ -200,9 +202,10 @@ extern "C" * Name: stm32l4_board_initialize * * Description: - * All STM32L4 architectures must provide the following entry point. This entry - * point is called early in the initialization -- after all memory has been - * configured and mapped but before any devices have been initialized. + * All STM32L4 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. * ****************************************************************************/ diff --git a/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h b/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h index 1ba4f854c6b..586168d0a9e 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h +++ b/boards/arm/stm32l4/stm32l476-mdk/include/stm32l476-mdk-clocking.h @@ -81,16 +81,18 @@ #define STM32L4_BOARD_USEHSI 1 /* Prescaler common to all PLL inputs; will be 1 (XXX source is implicitly - as per comment above HSI) */ + * as per comment above HSI) + */ #define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz * - * XXX NOTE: currently the main PLL is implicitly turned on and is implicitly - * the system clock; this should be configurable since not all applications may - * want things done this way. + * XXX NOTE: + * currently the main PLL is implicitly turned on and is implicitly the + * system clock; this should be configurable since not all applications + * may want things done this way. */ #define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c index e2db217ee17..243efe06b6e 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_boot.c @@ -59,9 +59,10 @@ * Name: stm32l4_board_initialize * * Description: - * All STM32L4 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All STM32L4 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. * ****************************************************************************/ @@ -74,7 +75,8 @@ void stm32l4_board_initialize(void) #endif #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak function + /* Configure SPI chip selects if + * 1) SP2 is not disabled, and 2) the weak function * stm32_spiinitialize() has been brought into the link. */ @@ -88,10 +90,11 @@ void stm32l4_board_initialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. * ****************************************************************************/ diff --git a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c index 21ff558b62f..fb51034c564 100644 --- a/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l476-mdk/src/stm32_clockconfig.c @@ -55,12 +55,13 @@ * Name: stm32_board_clockconfig * * Description: - * I provided this module when I was doing some debugging of a problem I had with - * clocking (it was helpful to do A/B tests). I'm leaving it here in the config - * partially because I expect to have similar problems again as I develop more of - * the various peripheral support, but also because it may become necessary in the - * end for certain project configurations which have specialized clock - * configurationsthat aren't appropriate to expose in the 'arch' default code. + * I provided this module when I was doing some debugging of a problem I + * had with clocking (it was helpful to do A/B tests). I'm leaving it + * here in the config partially because I expect to have similar problems + * again as I develop more of the various peripheral support, but also + * because it may become necessary in the end for certain project + * configurations which have specialized clock configurationsthat aren't + * appropriate to expose in the 'arch' default code. * ****************************************************************************/ @@ -107,6 +108,7 @@ void stm32l4_board_clockconfig(void) regval = getreg32(STM32L4_RCC_PLLCFG); /* Configure Main PLL */ + /* Set the PLL dividers and multipliers to configure the main PLL */ regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP @@ -163,6 +165,7 @@ void stm32l4_board_clockconfig(void) regval = getreg32(STM32L4_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ + /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | @@ -181,7 +184,9 @@ void stm32l4_board_clockconfig(void) { } - /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */ + /* Enable FLASH prefetch, instruction cache, data cache, + * and 5 wait states + */ #ifdef CONFIG_STM32L4_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | @@ -200,7 +205,8 @@ void stm32l4_board_clockconfig(void) /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) + while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + RCC_CFGR_SWS_PLL) { } @@ -208,7 +214,7 @@ void stm32l4_board_clockconfig(void) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32l4_rcc_enablelsi(); #endif #if defined(STM32L4_USE_LSE) diff --git a/boards/arm/stm32l4/stm32l476vg-disco/include/board.h b/boards/arm/stm32l4/stm32l476vg-disco/include/board.h index 0c2e6717106..d60092b0519 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/include/board.h +++ b/boards/arm/stm32l4/stm32l476vg-disco/include/board.h @@ -67,10 +67,10 @@ #if 0 -#define DMACHAN_SDMMC DMACHAN_SDMMC_1 /* 2 choices * / +#define DMACHAN_SDMMC DMACHAN_SDMMC_1 /* 2 choices */ -#define DMACHAN_SPI1_RX DMACHAN_SPI1_RX_1 /* 2 choices * / -#define DMACHAN_SPI1_TX DMACHAN_SPI1_TX_1 /* 2 choices * / +#define DMACHAN_SPI1_RX DMACHAN_SPI1_RX_1 /* 2 choices */ +#define DMACHAN_SPI1_TX DMACHAN_SPI1_TX_1 /* 2 choices */ /* UART RX DMA configurations */ @@ -204,7 +204,8 @@ /* LEDs * - * The STM32L476VG-DISCO board provides two user LEDs, LD4 (red) and LD5 (green). + * The STM32L476VG-DISCO board provides two user LEDs, LD4 (red) and LD5 + * (green). * * PB2 is LD4 (red) * PE8 is LD5 (green) @@ -228,8 +229,8 @@ * include/board.h and src/stm32_autoleds.c. The LEDs are used to encode * OS-related events as follows when the red and green LEDs are available: * - * SYMBOL Meaning BOARD_LED_GRN BOARD_LED_RED - * ------------------- ----------------------- ----------- ------------ + * SYMBOL Meaning BOARD_LED_GRN BOARD_LED_RED + * ------------------- ---------------------- ----------- ------------ * LED_STARTED NuttX has been started * LED_HEAPALLOCATE Heap has been allocated * LED_IRQSENABLED Interrupts enabled @@ -240,9 +241,9 @@ * LED_PANIC The system has crashed Blinking * LED_IDLE MCU is is sleep mode ON * - * Thus if BOARD_LED_GRN, NuttX has successfully booted and is, apparently, running - * normally. If BOARD_LED_RED is flashing at approximately 2Hz, then a fatal error - * has been detected and the system has halted. + * Thus if BOARD_LED_GRN, NuttX has successfully booted and is, apparently, + * running normally. If BOARD_LED_RED is flashing at approximately 2Hz, then + * a fatal error has been detected and the system has halted. */ #define LED_STARTED 0 diff --git a/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h b/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h index f5f50796335..a4aee34f5a5 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h +++ b/boards/arm/stm32l4/stm32l476vg-disco/include/stm32l476vg-disco-clocking.h @@ -91,16 +91,17 @@ #define STM32L4_BOARD_USEHSI 1 /* Prescaler common to all PLL inputs; will be 1 (XXX source is implicitly - as per comment above HSI) */ + * as per comment above HSI) + */ #define STM32L4_PLLCFG_PLLM RCC_PLLCFG_PLLM(1) /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 10 / 2 = 80 MHz * - * XXX NOTE: currently the main PLL is implicitly turned on and is implicitly - * the system clock; this should be configurable since not all applications may - * want things done this way. + * XXX NOTE: currently the main PLL is implicitly turned on and is implicitly + * the system clock; this should be configurable since not all applications + * may want things done this way. */ #define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(10) @@ -352,8 +353,9 @@ #endif /* The timer clock frequencies are automatically defined by hardware. - * If the APB prescaler equals 1, the timer clock frequencies are set to the same - * frequency as that of the APB domain. Otherwise they are set to twice. + * If the APB prescaler equals 1, the timer clock frequencies are set to + * the same frequency as that of the APB domain. Otherwise they are set to + * twice. * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c index 26b6e92a443..ec2632aaab0 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_boot.c @@ -59,9 +59,10 @@ * Name: stm32l4_board_initialize * * Description: - * All STM32L4 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All STM32L4 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. * ****************************************************************************/ @@ -73,8 +74,8 @@ void stm32l4_board_initialize(void) board_autoled_initialize(); #endif - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak function - * stm32_spiinitialize() has been brought into the link. + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak + * function stm32_spiinitialize() has been brought into the link. */ #if defined(CONFIG_STM32_SPI1) || defined(CONFIG_STM32_SPI2) || defined(CONFIG_STM32_SPI3) @@ -82,11 +83,14 @@ void stm32l4_board_initialize(void) #endif #ifdef CONFIG_STM32L4_OTGFS - /* Initialize USB if the 1) OTG FS controller is in the configuration and 2) - * disabled, and 3) the weak function stm32_usbinitialize() has been brought - * into the build. Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also + /* Initialize USB if the + * 1) OTG FS controller is in the configuration and + * 2) disabled, and + * 3) the weak function stm32_usbinitialize() has been brought into the + * build. Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also * selected. */ + stm32l4_usbinitialize(); #endif } @@ -97,10 +101,11 @@ void stm32l4_board_initialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. * ****************************************************************************/ @@ -108,8 +113,8 @@ void stm32l4_board_initialize(void) void board_late_initialize(void) { /* Perform NSH initialization here instead of from the NSH. This - * alternative NSH initialization is necessary when NSH is ran in user-space - * but the initialization function must run in kernel space. + * alternative NSH initialization is necessary when NSH is ran in + * user-space but the initialization function must run in kernel space. */ #if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_NSH_ARCHINIT) diff --git a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c index d296f37949a..3020ca875c8 100644 --- a/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c +++ b/boards/arm/stm32l4/stm32l476vg-disco/src/stm32_clockconfig.c @@ -55,12 +55,13 @@ * Name: stm32_board_clockconfig * * Description: - * I provided this module when I was doing some debugging of a problem I had with - * clocking (it was helpful to do A/B tests). I'm leaving it here in the config - * partially because I expect to have similar problems again as I develop more of - * the various peripheral support, but also because it may become necessary in the - * end for certain project configurations which have specialized clock configurations - * that aren't appropriate to expose in the 'arch' default code. + * I provided this module when I was doing some debugging of a problem I + * had with clocking (it was helpful to do A/B tests). I'm leaving it here + * in the config partially because I expect to have similar problems again + * as I develop more of the various peripheral support, but also because it + * may become necessary in the end for certain project configurations which + * have specialized clock configurations that aren't appropriate to expose + * in the 'arch' default code. * ****************************************************************************/ @@ -107,6 +108,7 @@ void stm32l4_board_clockconfig(void) regval = getreg32(STM32L4_RCC_PLLCFG); /* Configure Main PLL */ + /* Set the PLL dividers and multipliers to configure the main PLL */ regval = (STM32L4_PLLCFG_PLLM | STM32L4_PLLCFG_PLLN | STM32L4_PLLCFG_PLLP @@ -163,6 +165,7 @@ void stm32l4_board_clockconfig(void) regval = getreg32(STM32L4_RCC_PLLSAI2CFG); /* Enable the SAI2 PLL */ + /* Set the PLL dividers and multipliers to configure the SAI2 PLL */ regval = (STM32L4_PLLSAI2CFG_PLLN | STM32L4_PLLSAI2CFG_PLLP | @@ -181,7 +184,9 @@ void stm32l4_board_clockconfig(void) { } - /* Enable FLASH prefetch, instruction cache, data cache, and 5 wait states */ + /* Enable FLASH prefetch, instruction cache, data cache, + * and 5 wait states + */ #ifdef CONFIG_STM32L4_FLASH_PREFETCH regval = (FLASH_ACR_LATENCY_4 | FLASH_ACR_ICEN | FLASH_ACR_DCEN | @@ -200,7 +205,8 @@ void stm32l4_board_clockconfig(void) /* Wait until the PLL source is used as the system clock source */ - while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != RCC_CFGR_SWS_PLL) + while ((getreg32(STM32L4_RCC_CFGR) & RCC_CFGR_SWS_MASK) != + RCC_CFGR_SWS_PLL) { } @@ -208,7 +214,7 @@ void stm32l4_board_clockconfig(void) /* Low speed internal clock source LSI */ - stm32l4_rcc_enablelsi(); + stm32l4_rcc_enablelsi(); #endif #if defined(STM32L4_USE_LSE) diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h b/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h index 0b1ad2b4f06..41b308dcb89 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/include/stm32l4r9ai-disco-clocking.h @@ -51,11 +51,12 @@ /* Clocking *****************************************************************/ -/* The stm32l4r9ai-disco supports both HSE and LSE crystals. As shipped, the HSE - * is a 16 MHz crystal X2. Therefore the stm32l4r9ai-disco can run off the 16MHz - * HSI clock, or the MSI, or the HSE. Here we configure HSE to give us 120MHz system - * clock (maximum supported for STM32L4+ chips) instead of the more traditional 80MHz - * that is used by most STM32L4 boards supported by NuttX. +/* The stm32l4r9ai-disco supports both HSE and LSE crystals. As shipped, + * the HSE is a 16 MHz crystal X2. Therefore the stm32l4r9ai-disco can run + * off the 16MHz HSI clock, or the MSI, or the HSE. Here we configure HSE + * to give us 120MHz system clock (maximum supported for STM32L4+ chips) + * instead of the more traditional 80MHz that is used by most STM32L4 boards + * supported by NuttX. */ /* HSI - 16 MHz RC factory-trimmed @@ -102,9 +103,10 @@ /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 15 / 2 = 120 MHz * - * XXX NOTE: currently the main PLL is implicitly turned on and is implicitly - * the system clock; this should be configurable since not all applications may - * want things done this way. + * XXX NOTE: + * currently the main PLL is implicitly turned on and is implicitly + * the system clock; this should be configurable since not all + * applications may want things done this way. */ #define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(15) @@ -212,9 +214,10 @@ /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 16 MHz / 1 * 15 / 2 = 120 MHz * - * XXX NOTE: currently the main PLL is implicitly turned on and is implicitly - * the system clock; this should be configurable since not all applications may - * want things done this way. + * XXX NOTE: + * currently the main PLL is implicitly turned on and is implicitly + * the system clock; this should be configurable since not all + * applications may want things done this way. */ #define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(15) @@ -309,9 +312,10 @@ /* 'main' PLL config; we use this to generate our system clock via the R * output. We set it up as 4 MHz / 1 * 60 / 2 = 120 MHz * - * XXX NOTE: currently the main PLL is implicitly turned on and is implicitly - * the system clock; this should be configurable since not all applications may - * want things done this way. + * XXX NOTE: + * currently the main PLL is implicitly turned on and is implicitly + * the system clock; this should be configurable since not all + * applications may want things done this way. */ #define STM32L4_PLLCFG_PLLN RCC_PLLCFG_PLLN(60) @@ -395,8 +399,8 @@ #endif /* clock selection */ /* The timer clock frequencies are automatically defined by hardware. - * If the APB prescaler equals 1, the timer clock frequencies are set to the same - * frequency as that of the APB domain. Otherwise they are set to twice. + * If the APB prescaler equals 1, the timer clock frequencies are set to the + * same frequency as that of the APB domain. Otherwise they are set to twice. * Note: TIM1,8,15,16,17 are on APB2, others on APB1 */ diff --git a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c index 9879a90214e..0c82a9ecfd6 100644 --- a/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c +++ b/boards/arm/stm32l4/stm32l4r9ai-disco/src/stm32_boot.c @@ -51,13 +51,18 @@ #include "arm_arch.h" #include "stm32l4r9ai-disco.h" +/**************************************************************************** + * Public Functions + ****************************************************************************/ + /**************************************************************************** * Name: stm32l4_board_initialize * * Description: - * All STM32L4 architectures must provide the following entry point. This entry point - * is called early in the initialization -- after all memory has been configured - * and mapped but before any devices have been initialized. + * All STM32L4 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. * ****************************************************************************/ @@ -69,8 +74,8 @@ void stm32l4_board_initialize(void) board_autoled_initialize(); #endif - /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak function - * stm32_spiinitialize() has been brought into the link. + /* Configure SPI chip selects if 1) SP2 is not disabled, and 2) the weak + * function stm32_spiinitialize() has been brought into the link. */ #ifdef CONFIG_STM32L4_SPI @@ -78,11 +83,14 @@ void stm32l4_board_initialize(void) #endif #ifdef CONFIG_STM32L4_OTGFS - /* Initialize USB if the 1) OTG FS controller is in the configuration and 2) - * disabled, and 3) the weak function stm32_usbinitialize() has been brought - * into the build. Presumably either CONFIG_USBDEV or CONFIG_USBHOST is also - * selected. + /* Initialize USB if the + * 1) OTG FS controller is in the configuration and + * 2) disabled, and + * 3) the weak function stm32_usbinitialize() has been brought + * into the build. Presumably either CONFIG_USBDEV or CONFIG_USBHOST is + * also selected. */ + stm32l4_usbinitialize(); #endif } @@ -93,10 +101,11 @@ void stm32l4_board_initialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. * ****************************************************************************/ @@ -104,8 +113,8 @@ void stm32l4_board_initialize(void) void board_late_initialize(void) { /* Perform NSH initialization here instead of from the NSH. This - * alternative NSH initialization is necessary when NSH is ran in user-space - * but the initialization function must run in kernel space. + * alternative NSH initialization is necessary when NSH is ran in + * user-space but the initialization function must run in kernel space. */ #if defined(CONFIG_NSH_LIBRARY) && !defined(CONFIG_NSH_ARCHINIT) diff --git a/boards/arm/tiva/ekk-lm3s9b96/src/lm_ssi.c b/boards/arm/tiva/ekk-lm3s9b96/src/lm_ssi.c index 1cad595a229..6e9a7aa1595 100644 --- a/boards/arm/tiva/ekk-lm3s9b96/src/lm_ssi.c +++ b/boards/arm/tiva/ekk-lm3s9b96/src/lm_ssi.c @@ -128,6 +128,7 @@ void tiva_ssiselect(FAR struct spi_dev_s *dev, uint32_t devid, bool selected) tiva_gpiowrite(OLEDCS_GPIO, !selected); } #endif + ssi_dumpgpio("tiva_ssiselect() Exit"); } diff --git a/boards/arm/tms570/tms570ls31x-usb-kit/include/nsh_romfsimg.h b/boards/arm/tms570/tms570ls31x-usb-kit/include/nsh_romfsimg.h index 15e4e7a8d5a..ba67daa17ec 100644 --- a/boards/arm/tms570/tms570ls31x-usb-kit/include/nsh_romfsimg.h +++ b/boards/arm/tms570/tms570ls31x-usb-kit/include/nsh_romfsimg.h @@ -1,5 +1,5 @@ /**************************************************************************** - * + * boards/arm/tms570/tms570ls31x-usb-kit/include/nsh_romfsimg.h * Copyright (C) 2013 PX4 Development Team. All rights reserved. * * Redistribution and use in source and binary forms, with or without diff --git a/boards/misoc/lm32/misoc/src/lm32_boot.c b/boards/misoc/lm32/misoc/src/lm32_boot.c index d8fa000f2fe..589171373a4 100644 --- a/boards/misoc/lm32/misoc/src/lm32_boot.c +++ b/boards/misoc/lm32/misoc/src/lm32_boot.c @@ -52,9 +52,10 @@ * Name: lm32_board_initialize * * Description: - * All LM32 architectures must provide the following entry point. This entry - * point is called early in the initialization -- after all memory has been - * configured and mapped but before any devices have been initialized. + * All LM32 architectures must provide the following entry point. This + * entry point is called early in the initialization -- after all memory + * has been configured and mapped but before any devices have been + * initialized. * ****************************************************************************/ diff --git a/boards/or1k/mor1kx/or1k/src/or1k_boot.c b/boards/or1k/mor1kx/or1k/src/or1k_boot.c index 0efe8c2661b..4181472505d 100644 --- a/boards/or1k/mor1kx/or1k/src/or1k_boot.c +++ b/boards/or1k/mor1kx/or1k/src/or1k_boot.c @@ -75,10 +75,11 @@ void or1k_board_initialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. * ****************************************************************************/ diff --git a/boards/z80/ez80/z20x/src/ez80_boot.c b/boards/z80/ez80/z20x/src/ez80_boot.c index dc5885090e7..0dc6560b3a1 100644 --- a/boards/z80/ez80/z20x/src/ez80_boot.c +++ b/boards/z80/ez80/z20x/src/ez80_boot.c @@ -70,10 +70,11 @@ void ez80_board_initialize(void) * Description: * If CONFIG_BOARD_LATE_INITIALIZE is selected, then an additional * initialization call will be performed in the boot-up sequence to a - * function called board_late_initialize(). board_late_initialize() will be - * called immediately after up_initialize() is called and just before the - * initial application is started. This additional initialization phase - * may be used, for example, to initialize board-specific device drivers. + * function called board_late_initialize(). board_late_initialize() will + * be called immediately after up_initialize() is called and just before + * the initial application is started. This additional initialization + * phase may be used, for example, to initialize board-specific device + * drivers. * ****************************************************************************/ diff --git a/boards/z80/ez80/z20x/src/ez80_spimmcsd.c b/boards/z80/ez80/z20x/src/ez80_spimmcsd.c index 2cf01ba8eff..b75256fdb54 100644 --- a/boards/z80/ez80/z20x/src/ez80_spimmcsd.c +++ b/boards/z80/ez80/z20x/src/ez80_spimmcsd.c @@ -78,7 +78,9 @@ int ez80_mmcsd_initialize(void) return -ENODEV; } - /* Register the MMC/SD block driver for slot 0 with device minor number 0. */ + /* Register the MMC/SD block driver for + * slot 0 with device minor number 0. + */ ret = mmcsd_spislotinitialize(0, 0, spi); if (ret < 0)