Merged in david_s5/nuttx/upstream_nucleo-144 (pull request #83)

Upstream_nucleo 144

arch/arm/src/stm32/stm32_bbsram.c

@@ -593,8 +593,9 @@ static int stm32_bbsram_ioctl(FAR struct file *filep, int cmd,
           bbrr->fileno = bbr->bbf->fileno;
           bbrr->lastwrite = bbr->bbf->lastwrite;
           bbrr->len = bbr->bbf->len;
-          bbrr->flags = (bbr->bbf->crc == stm32_bbsram_crc(bbr->bbf)) ? eCRCValid : 0;
+          bbrr->flags = ((bbr->bbf->crc == stm32_bbsram_crc(bbr->bbf))
-          bbrr->flags = (bbr->bbf->dirty) ? eDirty : 0;
+                          ? BBSRAM_CRC_VALID : 0);
+          bbrr->flags |= ((bbr->bbf->dirty) ? BBSRAM_DIRTY : 0);
           ret = OK;
         }
 

arch/arm/src/stm32/stm32_bbsram.h

@@ -83,8 +83,8 @@
 
 enum bbsramdf_e
 {
-  eCRCValid = 1,  /* The crc is valid */
+  BBSRAM_CRC_VALID = 1,  /* The crc is valid */
-  eDirty    = 2,  /* The file was closed */
+  BBSRAM_DIRTY     = 2,  /* The file was closed */
 
 };
 

arch/arm/src/stm32f7/chip/stm32_dbgmcu.h

@@ -0,0 +1,55 @@
+/****************************************************************************
+ * arch/arm/src/stm32f7/chip/stm32_dbgmcu.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32_DBGMCU_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32_DBGMCU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+#include "chip.h"
+
+#if defined(CONFIG_STM32F7_STM32F74XX) || defined(CONFIG_STM32F7_STM32F75XX)
+#  include "chip/stm32f74xx75xx_dbgmcu.h"
+#elif defined(CONFIG_STM32F7_STM32F76XX) || defined(CONFIG_STM32F7_STM32F77XX)
+#  include "chip/stm32f76xx77xx_dbgmcu.h"
+#else
+#  error "Unsupported STM32 F7 part"
+#endif
+
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32_DBGMCU_H */

arch/arm/src/stm32f7/chip/stm32f74xx75xx_dbgmcu.h

@@ -0,0 +1,112 @@
+/****************************************************************************
+ * arch/arm/src/stm32f7/chip/stm32f74xx75xx_dbgmcu.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XXDBGMCU_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XXDBGMCU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Addresses *******************************************************/
+
+#define STM32_DBGMCU_IDCODE       0xe0042000  /* MCU identifier */
+#define STM32_DBGMCU_CR           0xe0042004  /* MCU debug */
+#define STM32_DBGMCU_APB1_FZ      0xe0042008  /* Debug MCU APB1 freeze register */
+#define STM32_DBGMCU_APB2_FZ      0xe004200c  /* Debug MCU APB2 freeze register */
+
+/* Register Bitfield Definitions ********************************************/
+
+/* MCU identifier */
+
+#define DBGMCU_IDCODE_DEVID_SHIFT (0)       /* Bits 11-0: Device Identifier */
+#define DBGMCU_IDCODE_DEVID_MASK  (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT)
+#define DBGMCU_IDCODE_REVID_SHIFT (16)      /* Bits 31-16:  Revision Identifier */
+#define DBGMCU_IDCODE_REVID_MASK  (0xffff << DBGMCU_IDCODE_REVID_SHIFT)
+
+/* MCU debug */
+
+#define DBGMCU_CR_SLEEP           (1 << 0)  /* Bit 0: Debug Sleep Mode */
+#define DBGMCU_CR_STOP            (1 << 1)  /* Bit 1: Debug Stop Mode */
+#define DBGMCU_CR_STANDBY         (1 << 2)  /* Bit 2: Debug Standby mode */
+#define DBGMCU_CR_TRACEIOEN       (1 << 5)  /* Bit 5: Trace enabled */
+
+#define DBGMCU_CR_TRACEMODE_SHIFT (6)        /* Bits 7-6: Trace mode pin assignement */
+#define DBGMCU_CR_TRACEMODE_MASK  (3 << DBGMCU_CR_TRACEMODE_SHIFT)
+#define DBGMCU_CR_ASYNCH          (0 << DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */
+#define DBGMCU_CR_SYNCH1          (1 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=1 */
+#define DBGMCU_CR_SYNCH2          (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */
+#define DBGMCU_CR_SYNCH4          (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */
+
+/* Debug MCU APB1 freeze register */
+
+#define DBGMCU_APB1_TIM2STOP      (1 << 0)   /* Bit 0: TIM2 stopped when core is halted */
+#define DBGMCU_APB1_TIM3STOP      (1 << 1)   /* Bit 1: TIM3 stopped when core is halted */
+#define DBGMCU_APB1_TIM4STOP      (1 << 2)   /* Bit 2: TIM4 stopped when core is halted */
+#define DBGMCU_APB1_TIM5STOP      (1 << 3)   /* Bit 3: TIM5 stopped when core is halted */
+#define DBGMCU_APB1_TIM6STOP      (1 << 4)   /* Bit 4: TIM6 stopped when core is halted */
+#define DBGMCU_APB1_TIM7STOP      (1 << 5)   /* Bit 5: TIM7 stopped when core is halted */
+#define DBGMCU_APB1_TIM12STOP     (1 << 6)   /* Bit 6: TIM12 stopped when core is halted */
+#define DBGMCU_APB1_TIM13STOP     (1 << 7)   /* Bit 7: TIM13 stopped when core is halted */
+#define DBGMCU_APB1_TIM14STOP     (1 << 8)   /* Bit 8: TIM14 stopped when core is halted */
+#define DBGMCU_APB1_LPTIM1STOP    (1 << 9)   /* Bit 9: LPTIM1 stopped when core is halted */
+#define DBGMCU_APB1_RTCSTOP       (1 << 10)  /* Bit 10: RTC stopped when Core is halted */
+#define DBGMCU_APB1_WWDGSTOP      (1 << 11)  /* Bit 11: Window Watchdog stopped when core is halted */
+#define DBGMCU_APB1_IWDGSTOP      (1 << 12)  /* Bit 12: Independent Watchdog stopped when core is halted */
+#define DBGMCU_APB1_I2C1STOP      (1 << 21)  /* Bit 21: I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_I2C2STOP      (1 << 22)  /* Bit 22: I2C2 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_I2C3STOP      (1 << 23)  /* Bit 23: I2C3 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_I2C4STOP      (1 << 24)  /* Bit 24: I2C4 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_CAN1STOP      (1 << 25)  /* Bit 25: CAN1 stopped when core is halted */
+#define DBGMCU_APB1_CAN2STOP      (1 << 26)  /* Bit 26: CAN2 stopped when core is halted */
+
+/* Debug MCU APB2 freeze register */
+
+#define DBGMCU_APB2_TIM1STOP      (1 << 0)   /* Bit 0:  TIM1 stopped when core is halted */
+#define DBGMCU_APB2_TIM8STOP      (1 << 1)   /* Bit 1:  TIM8 stopped when core is halted */
+#define DBGMCU_APB2_TIM9STOP      (1 << 16)  /* Bit 16: TIM9 stopped when core is halted */
+#define DBGMCU_APB2_TIM10STOP     (1 << 17)  /* Bit 17: TIM10 stopped when core is halted */
+#define DBGMCU_APB2_TIM11STOP     (1 << 18)  /* Bit 18: TIM11 stopped when core is halted */
+
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F74XX75XXDBGMCU_H */

arch/arm/src/stm32f7/chip/stm32f76xx77xx_dbgmcu.h

@@ -0,0 +1,113 @@
+/****************************************************************************
+ * arch/arm/src/stm32f7/chip/stm32f76xx77xx_dbgmcu.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XXDBGMCU_H
+#define __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XXDBGMCU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/* Register Addresses *******************************************************/
+
+#define STM32_DBGMCU_IDCODE       0xe0042000  /* MCU identifier */
+#define STM32_DBGMCU_CR           0xe0042004  /* MCU debug */
+#define STM32_DBGMCU_APB1_FZ      0xe0042008  /* Debug MCU APB1 freeze register */
+#define STM32_DBGMCU_APB2_FZ      0xe004200c  /* Debug MCU APB2 freeze register */
+
+/* Register Bitfield Definitions ********************************************/
+
+/* MCU identifier */
+
+#define DBGMCU_IDCODE_DEVID_SHIFT (0)       /* Bits 11-0: Device Identifier */
+#define DBGMCU_IDCODE_DEVID_MASK  (0x0fff << DBGMCU_IDCODE_DEVID_SHIFT)
+#define DBGMCU_IDCODE_REVID_SHIFT (16)      /* Bits 31-16:  Revision Identifier */
+#define DBGMCU_IDCODE_REVID_MASK  (0xffff << DBGMCU_IDCODE_REVID_SHIFT)
+
+/* MCU debug */
+
+#define DBGMCU_CR_SLEEP           (1 << 0)  /* Bit 0: Debug Sleep Mode */
+#define DBGMCU_CR_STOP            (1 << 1)  /* Bit 1: Debug Stop Mode */
+#define DBGMCU_CR_STANDBY         (1 << 2)  /* Bit 2: Debug Standby mode */
+#define DBGMCU_CR_TRACEIOEN       (1 << 5)  /* Bit 5: Trace enabled */
+
+#define DBGMCU_CR_TRACEMODE_SHIFT (6)        /* Bits 7-6: Trace mode pin assignement */
+#define DBGMCU_CR_TRACEMODE_MASK  (3 << DBGMCU_CR_TRACEMODE_SHIFT)
+#define DBGMCU_CR_ASYNCH          (0 << DBGMCU_CR_TRACEMODE_SHIFT) /* Asynchronous Mode */
+#define DBGMCU_CR_SYNCH1          (1 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=1 */
+#define DBGMCU_CR_SYNCH2          (2 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=2 */
+#define DBGMCU_CR_SYNCH4          (3 << DBGMCU_CR_TRACEMODE_SHIFT) /* Synchronous Mode, TRACEDATA size=4 */
+
+/* Debug MCU APB1 freeze register */
+
+#define DBGMCU_APB1_TIM2STOP      (1 << 0)   /* Bit 0: TIM2 stopped when core is halted */
+#define DBGMCU_APB1_TIM3STOP      (1 << 1)   /* Bit 1: TIM3 stopped when core is halted */
+#define DBGMCU_APB1_TIM4STOP      (1 << 2)   /* Bit 2: TIM4 stopped when core is halted */
+#define DBGMCU_APB1_TIM5STOP      (1 << 3)   /* Bit 3: TIM5 stopped when core is halted */
+#define DBGMCU_APB1_TIM6STOP      (1 << 4)   /* Bit 4: TIM6 stopped when core is halted */
+#define DBGMCU_APB1_TIM7STOP      (1 << 5)   /* Bit 5: TIM7 stopped when core is halted */
+#define DBGMCU_APB1_TIM12STOP     (1 << 6)   /* Bit 6: TIM12 stopped when core is halted */
+#define DBGMCU_APB1_TIM13STOP     (1 << 7)   /* Bit 7: TIM13 stopped when core is halted */
+#define DBGMCU_APB1_TIM14STOP     (1 << 8)   /* Bit 8: TIM14 stopped when core is halted */
+#define DBGMCU_APB1_LPTIM1STOP    (1 << 9)   /* Bit 9: LPTIM1 stopped when core is halted */
+#define DBGMCU_APB1_RTCSTOP       (1 << 10)  /* Bit 10: RTC stopped when Core is halted */
+#define DBGMCU_APB1_WWDGSTOP      (1 << 11)  /* Bit 11: Window Watchdog stopped when core is halted */
+#define DBGMCU_APB1_IWDGSTOP      (1 << 12)  /* Bit 12: Independent Watchdog stopped when core is halted */
+#define DBGMCU_APB1_CAN3STOP      (1 << 13)  /* Bit 13: CAN3 stopped when Core is halted */
+#define DBGMCU_APB1_I2C1STOP      (1 << 21)  /* Bit 21: I2C1 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_I2C2STOP      (1 << 22)  /* Bit 22: I2C2 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_I2C3STOP      (1 << 23)  /* Bit 23: I2C3 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_I2C4STOP      (1 << 24)  /* Bit 24: I2C4 SMBUS timeout mode stopped when Core is halted */
+#define DBGMCU_APB1_CAN1STOP      (1 << 25)  /* Bit 25: CAN1 stopped when core is halted */
+#define DBGMCU_APB1_CAN2STOP      (1 << 26)  /* Bit 26: CAN2 stopped when core is halted */
+
+/* Debug MCU APB2 freeze register */
+
+#define DBGMCU_APB2_TIM1STOP      (1 << 0)   /* Bit 0:  TIM1 stopped when core is halted */
+#define DBGMCU_APB2_TIM8STOP      (1 << 1)   /* Bit 1:  TIM8 stopped when core is halted */
+#define DBGMCU_APB2_TIM9STOP      (1 << 16)  /* Bit 16: TIM9 stopped when core is halted */
+#define DBGMCU_APB2_TIM10STOP     (1 << 17)  /* Bit 17: TIM10 stopped when core is halted */
+#define DBGMCU_APB2_TIM11STOP     (1 << 18)  /* Bit 18: TIM11 stopped when core is halted */
+
+#endif /* __ARCH_ARM_SRC_STM32F7_CHIP_STM32F76XX77XXDBGMCU_H */

arch/arm/src/stm32f7/stm32_bbsram.c

@@ -593,8 +593,9 @@ static int stm32_bbsram_ioctl(FAR struct file *filep, int cmd,
           bbrr->fileno = bbr->bbf->fileno;
           bbrr->lastwrite = bbr->bbf->lastwrite;
           bbrr->len = bbr->bbf->len;
-          bbrr->flags = (bbr->bbf->crc == stm32_bbsram_crc(bbr->bbf)) ? eCRCValid : 0;
+          bbrr->flags = ((bbr->bbf->crc == stm32_bbsram_crc(bbr->bbf))
-          bbrr->flags = (bbr->bbf->dirty) ? eDirty : 0;
+                          ? BBSRAM_CRC_VALID : 0);
+          bbrr->flags |= ((bbr->bbf->dirty) ? BBSRAM_DIRTY : 0);
           ret = OK;
         }
 

arch/arm/src/stm32f7/stm32_bbsram.h

@@ -2,8 +2,8 @@
  * arch/arm/src/stm32f7/stm32_bbsram.h
  *
  *   Copyright (C) 2015-2016 Gregory Nutt. All rights reserved.
- *   Author: Gregory Nutt <gnutt@nuttx.org>
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
- *           David Sidrane <david_s5@nscdg.com>
+ *            David Sidrane <david_s5@nscdg.com>
  *
  * Redistribution and use in source and binary forms, with or without
  * modification, are permitted provided that the following conditions
@@ -83,8 +83,8 @@
 
 enum bbsramdf_e
 {
-  eCRCValid = 1,  /* The crc is valid */
+  BBSRAM_CRC_VALID = 1,  /* The crc is valid */
-  eDirty    = 2,  /* The file was closed */
+  BBSRAM_DIRTY     = 2,  /* The file was closed */
 
 };
 

arch/arm/src/stm32f7/stm32_dbgmcu.h

@@ -0,0 +1,64 @@
+/****************************************************************************
+ * arch/arm/src/stm32f7/stm32_dbgmcu.h
+ *
+ *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
+ *   Authors: Gregory Nutt <gnutt@nuttx.org>
+ *            David Sidrane <david_s5@nscdg.com>
+ *
+ * Redistribution and use in source and binary forms, with or without
+ * modification, are permitted provided that the following conditions
+ * are met:
+ *
+ * 1. Redistributions of source code must retain the above copyright
+ *    notice, this list of conditions and the following disclaimer.
+ * 2. Redistributions in binary form must reproduce the above copyright
+ *    notice, this list of conditions and the following disclaimer in
+ *    the documentation and/or other materials provided with the
+ *    distribution.
+ * 3. Neither the name NuttX nor the names of its contributors may be
+ *    used to endorse or promote products derived from this software
+ *    without specific prior written permission.
+ *
+ * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS
+ * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT
+ * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS
+ * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE
+ * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT,
+ * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING,
+ * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS
+ * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED
+ * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT
+ * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN
+ * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
+ * POSSIBILITY OF SUCH DAMAGE.
+ *
+ ****************************************************************************/
+
+#ifndef __ARCH_ARM_SRC_STM32F7_STM32_DBGMCU_H
+#define __ARCH_ARM_SRC_STM32F7_STM32_DBGMCU_H
+
+/****************************************************************************
+ * Included Files
+ ****************************************************************************/
+
+#include <nuttx/config.h>
+
+#include "chip/stm32_dbgmcu.h"
+
+/****************************************************************************
+ * Pre-processor Definitions
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Types
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Data
+ ****************************************************************************/
+
+/****************************************************************************
+ * Public Functions
+ ****************************************************************************/
+
+#endif /* __ARCH_ARM_SRC_STM32F7_STM32_DBGMCU_H */

configs/nucleo-144/src/stm32_bbsram.c

@@ -1,4 +1,4 @@
-/************************************************************************************
+/****************************************************************************
  * configs/nucleo-144/src/stm32_bbsram.c
  *
  *   Copyright (C) 2016 Gregory Nutt. All rights reserved.
@@ -31,11 +31,11 @@
  * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE
  * POSSIBILITY OF SUCH DAMAGE.
  *
- ************************************************************************************/
+ *****************************************************************************/
 
-/************************************************************************************
+/****************************************************************************
  * Included Files
- ************************************************************************************/
+ ****************************************************************************/
 
 #include <nuttx/config.h>
 
@@ -58,37 +58,76 @@
 
 #ifdef CONFIG_STM32F7_BBSRAM
 
-/************************************************************************************
+/****************************************************************************
  * Pre-processor Definitions
- ************************************************************************************/
+ ****************************************************************************/
+
+/* Configuration ************************************************************/
+
+#define FREEZE_STR(s)          #s
+#define STRINGIFY(s)           FREEZE_STR(s)
+#define HARDFAULT_FILENO       3
+#define HARDFAULT_PATH         BBSRAM_PATH""STRINGIFY(HARDFAULT_FILENO)
+#define HARDFAULT_REBOOT_      FILENO 0
+#define HARDFAULT_REBOOT_PATH  BBSRAM_PATH""STRINGIFY(HARDFAULT_REBOOT_FILENO)
+
+#define BBSRAM_SIZE_FN0        (sizeof(int))
+#define BBSRAM_SIZE_FN1        384
+#define BBSRAM_SIZE_FN2        384
+#define BBSRAM_SIZE_FN3 -      1
+
+/* The following guides in the amount of the user and interrupt stack
+ * data we can save. The amount of storage left will dictate the actual
+ * number of entries of the user stack data saved. If it is too big
+ * It will be truncated by the call to stm32_bbsram_savepanic
+ */
+#define BBSRAM_HEADER_SIZE     20 /* This is an assumption */
+#define BBSRAM_USED            ((4*BBSRAM_HEADER_SIZE)+ \
+                                (BBSRAM_SIZE_FN0+BBSRAM_SIZE_FN1+ \
+                                 BBSRAM_SIZE_FN2))
+#define BBSRAM_REAMINING       (STM32F7_BBSRAM_SIZE-BBSRAM_USED)
+#if CONFIG_ARCH_INTERRUPTSTACK <= 3
+#  define BBSRAM_NUMBER_STACKS 1
+#else
+#  define BBSRAM_NUMBER_STACKS 2
+#endif
+#define BBSRAM_FIXED_ELEMENTS_SIZE (sizeof(info_t))
+#define BBSRAM_LEFTOVER            (BBSRAM_REAMINING-\
+                                    BBSRAM_FIXED_ELEMENTS_SIZE)
+
+#define CONFIG_ISTACK_SIZE (BBSRAM_LEFTOVER/BBSRAM_NUMBER_STACKS/ \
+                            sizeof(stack_word_t))
+#define CONFIG_USTACK_SIZE (BBSRAM_LEFTOVER/BBSRAM_NUMBER_STACKS/ \
+                            sizeof(stack_word_t))
 
-/* Configuration ********************************************************************/
 /* The path to the Battery Backed up SRAM */
 
-#define BBSRAM_PATH "/bbr"
+#define BBSRAM_PATH "/fs/bbr"
-#define HARDFAULT_FILENO 3
-#define HARDFAULT_PATH "/bbr3"
 
 /* The sizes of the files to create (-1) use rest of BBSRAM memory */
 
-#define BSRAM_FILE_SIZES \
+#define BSRAM_FILE_SIZES { \
-  { \
+  BBSRAM_SIZE_FN0,   \
-    256, \
+  BBSRAM_SIZE_FN1,   \
-    256, \
+  BBSRAM_SIZE_FN2,   \
-    1024, \
+  BBSRAM_SIZE_FN3,   \
-    -1, \
+  0                  \
-    0 \
+    }
-  }
-
-#define MAX_FILE_PATH_LENGTH 40
-#define CONFIG_ISTACK_SIZE 800
-#define CONFIG_USTACK_SIZE 800
 
 #define ARRAYSIZE(a) (sizeof((a))/sizeof(a[0]))
 
-/************************************************************************************
+/* For Assert keep this much of the file name*/
+
+#define MAX_FILE_PATH_LENGTH 40
+
+#define HEADER_TIME_FMT      "%Y-%m-%d-%H:%M:%S"
+#define HEADER_TIME_FMT_NUM  (2+ 0+ 0+ 0+ 0+ 0)
+#define HEADER_TIME_FMT_LEN  (((ARRAYSIZE(HEADER_TIME_FMT)-1) + \
+                                HEADER_TIME_FMT_NUM))
+
+/****************************************************************************
  * Private Data
- ************************************************************************************/
+ ****************************************************************************/
 
 /* Used for stack frame storage */
 
@@ -234,19 +273,19 @@ typedef struct
   stack_word_t ustack[CONFIG_ISTACK_SIZE];
 } fullcontext_t;
 
-/************************************************************************************
+/****************************************************************************
  * Private Data
- ************************************************************************************/
+ ****************************************************************************/
 
 static uint8_t g_sdata[STM32F7_BBSRAM_SIZE];
 
-/************************************************************************************
+/****************************************************************************
  * Private Functions
- ************************************************************************************/
+ ****************************************************************************/
 
-/************************************************************************************
+/****************************************************************************
  * Name: hardfault_get_desc
- ************************************************************************************/
+ ****************************************************************************/
 
 static int hardfault_get_desc(struct bbsramd_s *desc)
 {
@@ -256,8 +295,8 @@ static int hardfault_get_desc(struct bbsramd_s *desc)
 
   if (fd < 0)
     {
-      syslog(LOG_INFO, "stm32 bbsram: Failed to open Fault Log file [%s] (%d)\n",
+      syslog(LOG_INFO, "stm32 bbsram: Failed to open Fault Log file [%s] "
-             HARDFAULT_PATH, fd);
+          "(%d)\n", HARDFAULT_PATH, fd);
     }
   else
     {
@@ -271,17 +310,17 @@ static int hardfault_get_desc(struct bbsramd_s *desc)
         }
       else
         {
-          syslog(LOG_INFO, "stm32 bbsram: Failed to get Fault Log descriptor (%d)\n",
+          syslog(LOG_INFO, "stm32 bbsram: Failed to get Fault Log descriptor "
-                 rv);
+              "(%d)\n", rv);
         }
     }
 
   return ret;
 }
 
-/************************************************************************************
+/****************************************************************************
  * Name: copy_reverse
- ************************************************************************************/
+ ****************************************************************************/
 
 #if defined(CONFIG_STM32F7_SAVE_CRASHDUMP)
 static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size)
@@ -293,19 +332,24 @@ static void copy_reverse(stack_word_t *dest, stack_word_t *src, int size)
 }
 #endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */
 
-/************************************************************************************
+/****************************************************************************
  * Public Functions
- ************************************************************************************/
+ ****************************************************************************/
 
-/************************************************************************************
+/****************************************************************************
  * Name: stm32_bbsram_int
- ************************************************************************************/
+ ****************************************************************************/
 
 int stm32_bbsram_int(void)
 {
   int filesizes[CONFIG_STM32F7_BBSRAM_FILES + 1] = BSRAM_FILE_SIZES;
+  char buf[HEADER_TIME_FMT_LEN + 1];
   struct bbsramd_s desc;
   int rv;
+  int state;
+  struct tm tt;
+  time_t time_sec;
+
 
   /* Using Battery Backed Up SRAM */
 
@@ -319,11 +363,23 @@ int stm32_bbsram_int(void)
   if (rv >= OK)
     {
       printf("There is a hard fault logged.\n");
-
+      state = (desc.lastwrite.tv_sec || desc.lastwrite.tv_nsec) ?  OK : 1;
+      syslog(LOG_INFO, "Fault Log info File No %d Length %d flags:0x%02x "
+          "state:%d\n",(unsigned int)desc.fileno, (unsigned int) desc.len,
+          (unsigned int)desc.flags, state);
+      if (state == OK)
+        {
+          time_sec = desc.lastwrite.tv_sec + (desc.lastwrite.tv_nsec / 1e9);
+          gmtime_r(&time_sec, &tt);
+          strftime(buf, HEADER_TIME_FMT_LEN , HEADER_TIME_FMT , &tt);
+          syslog(LOG_INFO, "Fault Logged on %s - Valid\n", buf);
+        }
+      close(rv);
       rv = unlink(HARDFAULT_PATH);
       if (rv < 0)
         {
-          syslog(LOG_INFO, "stm32 bbsram: Failed to unlink Fault Log file [%s] (%d)\n", HARDFAULT_PATH, rv);
+          syslog(LOG_INFO, "stm32 bbsram: Failed to unlink Fault Log file [%s"
+                 "] (%d)\n", HARDFAULT_PATH, rv);
         }
     }
 #endif /* CONFIG_STM32F7_SAVE_CRASHDUMP */
@@ -331,9 +387,9 @@ int stm32_bbsram_int(void)
   return rv;
 }
 
-/************************************************************************************
+/****************************************************************************
  * Name: board_crashdump
- ************************************************************************************/
+ ****************************************************************************/
 
 #if defined(CONFIG_STM32F7_SAVE_CRASHDUMP)
 void board_crashdump(uintptr_t currentsp, FAR void *tcb,
@@ -393,8 +449,10 @@ void board_crashdump(uintptr_t currentsp, FAR void *tcb,
   if (CURRENT_REGS)
     {
       pdump->info.stacks.interrupt.sp = currentsp;
-      pdump->info.flags |= (REGS_PRESENT | USERSTACK_PRESENT | INTSTACK_PRESENT);
+      pdump->info.flags |= (REGS_PRESENT | USERSTACK_PRESENT | \
-      memcpy(pdump->info.regs, (void *)CURRENT_REGS, sizeof(pdump->info.regs));
+                            INTSTACK_PRESENT);
+      memcpy(pdump->info.regs, (void *)CURRENT_REGS,
+             sizeof(pdump->info.regs));
       pdump->info.stacks.user.sp = pdump->info.regs[REG_R13];
     }
   else
@@ -413,7 +471,7 @@ void board_crashdump(uintptr_t currentsp, FAR void *tcb,
   else
     {
       pdump->info.stacks.user.top = (uint32_t) rtcb->adj_stack_ptr;
-      pdump->info.stacks.user.size = (uint32_t) rtcb->adj_stack_size;;
+      pdump->info.stacks.user.size = (uint32_t) rtcb->adj_stack_size;
     }
 
 #if CONFIG_ARCH_INTERRUPTSTACK > 3