diff --git a/arch/arm/src/kinetis/kinetis_slcd.h b/arch/arm/src/kinetis/chip/kinetis_slcd.h similarity index 99% rename from arch/arm/src/kinetis/kinetis_slcd.h rename to arch/arm/src/kinetis/chip/kinetis_slcd.h index d56ee5c41ea..d4a68f07f5a 100644 --- a/arch/arm/src/kinetis/kinetis_slcd.h +++ b/arch/arm/src/kinetis/chip/kinetis_slcd.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_slcd.h + * arch/arm/src/kinetis/chip/kinetis_slcd.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_SLCD_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_SLCD_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SLCD_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SLCD_H /************************************************************************************ * Included Files @@ -417,4 +417,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_SLCD_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SLCD_H */ diff --git a/arch/arm/src/kinetis/kinetis_smc.h b/arch/arm/src/kinetis/chip/kinetis_smc.h similarity index 96% rename from arch/arm/src/kinetis/kinetis_smc.h rename to arch/arm/src/kinetis/chip/kinetis_smc.h index 213ea807759..19a9d9d14b8 100644 --- a/arch/arm/src/kinetis/kinetis_smc.h +++ b/arch/arm/src/kinetis/chip/kinetis_smc.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_smc.h + * arch/arm/src/kinetis/chip/kinetis_smc.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_SMC_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_SMC_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SMC_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SMC_H /************************************************************************************ * Included Files @@ -119,4 +119,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_SMC_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_SMC_H */ diff --git a/arch/arm/src/kinetis/kinetis_tsi.h b/arch/arm/src/kinetis/chip/kinetis_tsi.h similarity index 98% rename from arch/arm/src/kinetis/kinetis_tsi.h rename to arch/arm/src/kinetis/chip/kinetis_tsi.h index ea52c0fd1db..6881150160f 100644 --- a/arch/arm/src/kinetis/kinetis_tsi.h +++ b/arch/arm/src/kinetis/chip/kinetis_tsi.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_tsi.h + * arch/arm/src/kinetis/chip/kinetis_tsi.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_TSI_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_TSI_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_TSI_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_TSI_H /************************************************************************************ * Included Files @@ -308,4 +308,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_TSI_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_TSI_H */ diff --git a/arch/arm/src/kinetis/kinetis_uart.h b/arch/arm/src/kinetis/chip/kinetis_uart.h similarity index 99% rename from arch/arm/src/kinetis/kinetis_uart.h rename to arch/arm/src/kinetis/chip/kinetis_uart.h index 27dd40467c2..537332ee786 100644 --- a/arch/arm/src/kinetis/kinetis_uart.h +++ b/arch/arm/src/kinetis/chip/kinetis_uart.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_uart.h + * arch/arm/src/kinetis/chip/kinetis_uart.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_UART_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_UART_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_UART_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_UART_H /************************************************************************************ * Included Files @@ -508,4 +508,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_UART_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_UART_H */ diff --git a/arch/arm/src/kinetis/kinetis_usbdcd.h b/arch/arm/src/kinetis/chip/kinetis_usbdcd.h similarity index 87% rename from arch/arm/src/kinetis/kinetis_usbdcd.h rename to arch/arm/src/kinetis/chip/kinetis_usbdcd.h index fad76d1500e..6c4297ff7af 100644 --- a/arch/arm/src/kinetis/kinetis_usbdcd.h +++ b/arch/arm/src/kinetis/chip/kinetis_usbdcd.h @@ -1,7 +1,7 @@ /************************************************************************************ - * arch/arm/src/kinetis/kinetis_usbdcd.h + * arch/arm/src/kinetis/chip/kinetis_usbdcd.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_USBDCD_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_USBDCD_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBDCD_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBDCD_H /************************************************************************************ * Included Files @@ -50,12 +50,17 @@ /* Register Offsets *****************************************************************/ -#define KINETIS_USBDCD_CONTROL_OFFSET 0x0000 /* Control Register */ -#define KINETIS_USBDCD_CLOCK_OFFSET 0x0004 /* Clock Register */ -#define KINETIS_USBDCD_STATUS_OFFSET 0x0008 /* Status Register */ -#define KINETIS_USBDCD_TIMER0_OFFSET 0x0010 /* TIMER0 Register */ -#define KINETIS_USBDCD_TIMER1_OFFSET 0x0014 /* TIMER1 Register */ -#define KINETIS_USBDCD_TIMER2_OFFSET 0x0018 /* TIMER2 Register */ +#define KINETIS_USBDCD_CONTROL_OFFSET 0x0000 /* Control Register */ +#define KINETIS_USBDCD_CLOCK_OFFSET 0x0004 /* Clock Register */ +#define KINETIS_USBDCD_STATUS_OFFSET 0x0008 /* Status Register */ +#define KINETIS_USBDCD_TIMER0_OFFSET 0x0010 /* TIMER0 Register */ +#define KINETIS_USBDCD_TIMER1_OFFSET 0x0014 /* TIMER1 Register */ +#ifdef KINETIS_K64 +# define KINETIS_USBDCD_TIMER2_BC11_OFFSET 0x0018 /* TIMER2_BC11 Register */ +# define KINETIS_USBDCD_TIMER2_BC12_OFFSET 0x001c /* TIMER2_BC12 Register */ +#else +# define KINETIS_USBDCD_TIMER2_OFFSET 0x0018 /* TIMER2 Register */ +#endif /* Register Addresses ***************************************************************/ @@ -64,7 +69,12 @@ #define KINETIS_USBDCD_STATUS (KINETIS_USBDCD_BASE+KINETIS_USBDCD_STATUS_OFFSET) #define KINETIS_USBDCD_TIMER0 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER0_OFFSET) #define KINETIS_USBDCD_TIMER1 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER1_OFFSET) -#define KINETIS_USBDCD_TIMER2 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER2_OFFSET) +#ifdef KINETIS_K64 +# define KINETIS_USBDCD_TIMER2_BC11 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER2_BC11_OFFSET) +# define KINETIS_USBDCD_TIMER2_BC12 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER2_BC12_OFFSET) +#else +# define KINETIS_USBDCD_TIMER2 (KINETIS_USBDCD_BASE+KINETIS_USBDCD_TIMER2_OFFSET) +#endif /* Register Bit Definitions *********************************************************/ @@ -138,4 +148,4 @@ * Public Functions ************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_USBDCD_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBDCD_H */ diff --git a/arch/arm/src/kinetis/chip/kinetis_usbotg.h b/arch/arm/src/kinetis/chip/kinetis_usbotg.h new file mode 100644 index 00000000000..16cecc22610 --- /dev/null +++ b/arch/arm/src/kinetis/chip/kinetis_usbotg.h @@ -0,0 +1,377 @@ +/******************************************************************************************** + * arch/arm/src/kinetis/chip/kinetis_usbotg.h + * + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. + * Author: Gregory Nutt + * + * Redistribution and use in source and binary forms, with or without + * modification, are permitted provided that the following conditions + * are met: + * + * 1. Redistributions of source code must retain the above copyright + * notice, this list of conditions and the following disclaimer. + * 2. Redistributions in binary form must reproduce the above copyright + * notice, this list of conditions and the following disclaimer in + * the documentation and/or other materials provided with the + * distribution. + * 3. Neither the name NuttX nor the names of its contributors may be + * used to endorse or promote products derived from this software + * without specific prior written permission. + * + * THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS + * "AS IS" AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT + * LIMITED TO, THE IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS + * FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL THE + * COPYRIGHT OWNER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, + * INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, + * BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR SERVICES; LOSS + * OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED + * AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT + * LIABILITY, OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN + * ANY WAY OUT OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE + * POSSIBILITY OF SUCH DAMAGE. + * + ********************************************************************************************/ + +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBOTG_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBOTG_H + +/******************************************************************************************** + * Included Files + ********************************************************************************************/ + +#include + +#include "chip.h" + +/******************************************************************************************** + * Pre-processor Definitions + ********************************************************************************************/ + +/* Register Offsets *************************************************************************/ + +#define KINETIS_USB_PERID_OFFSET 0x0000 /* Peripheral ID Register */ +#define KINETIS_USB_IDCOMP_OFFSET 0x0004 /* Peripheral ID Complement Register */ +#define KINETIS_USB_REV_OFFSET 0x0008 /* Peripheral Revision Register */ +#define KINETIS_USB_ADDINFO_OFFSET 0x000c /* Peripheral Additional Info Register */ +#define KINETIS_USB_OTGISTAT_OFFSET 0x0010 /* OTG Interrupt Status Register */ +#define KINETIS_USB_OTGICR_OFFSET 0x0014 /* OTG Interrupt Control Register */ +#define KINETIS_USB_OTGSTAT_OFFSET 0x0018 /* OTG Status Register */ +#define KINETIS_USB_OTGCTL_OFFSET 0x001c /* OTG Control Register */ +#define KINETIS_USB_ISTAT_OFFSET 0x0080 /* Interrupt Status Register */ +#define KINETIS_USB_INTEN_OFFSET 0x0084 /* Interrupt Enable Register */ +#define KINETIS_USB_ERRSTAT_OFFSET 0x0088 /* Error Interrupt Status Register */ +#define KINETIS_USB_ERREN_OFFSET 0x008c /* Error Interrupt Enable Register */ +#define KINETIS_USB_STAT_OFFSET 0x0090 /* Status Register */ +#define KINETIS_USB_CTL_OFFSET 0x0094 /* Control Register */ +#define KINETIS_USB_ADDR_OFFSET 0x0098 /* Address Register */ +#define KINETIS_USB_BDTPAGE1_OFFSET 0x009c /* BDT Page Register 1 */ +#define KINETIS_USB_FRMNUML_OFFSET 0x00a0 /* Frame Number Register Low */ +#define KINETIS_USB_FRMNUMH_OFFSET 0x00a4 /* Frame Number Register High */ +#define KINETIS_USB_TOKEN_OFFSET 0x00a8 /* Token Register */ +#define KINETIS_USB_SOFTHLD_OFFSET 0x00ac /* SOF Threshold Register */ +#define KINETIS_USB_BDTPAGE2_OFFSET 0x00b0 /* BDT Page Register 2 */ +#define KINETIS_USB_BDTPAGE3_OFFSET 0x00b4 /* BDT Page Register 3 */ + +#define KINETIS_USB_ENDPT_OFFSET(n) (0x00c0+((n)<<2)) /* Endpoint n Control Register */ +#define KINETIS_USB_ENDPT0_OFFSET 0x00c0 /* Endpoint 0 Control Register */ +#define KINETIS_USB_ENDPT1_OFFSET 0x00c4 /* Endpoint 1 Control Register */ +#define KINETIS_USB_ENDPT2_OFFSET 0x00c8 /* Endpoint 2 Control Register */ +#define KINETIS_USB_ENDPT3_OFFSET 0x00cc /* Endpoint 3 Control Register */ +#define KINETIS_USB_ENDPT4_OFFSET 0x00d0 /* Endpoint 4 Control Register */ +#define KINETIS_USB_ENDPT5_OFFSET 0x00d4 /* Endpoint 5 Control Register */ +#define KINETIS_USB_ENDPT6_OFFSET 0x00d8 /* Endpoint 6 Control Register */ +#define KINETIS_USB_ENDPT7_OFFSET 0x00dc /* Endpoint 7 Control Register */ +#define KINETIS_USB_ENDPT8_OFFSET 0x00e0 /* Endpoint 8 Control Register */ +#define KINETIS_USB_ENDPT9_OFFSET 0x00e4 /* Endpoint 9 Control Register */ +#define KINETIS_USB_ENDPT10_OFFSET 0x00e8 /* Endpoint 10 Control Register */ +#define KINETIS_USB_ENDPT11_OFFSET 0x00ec /* Endpoint 11 Control Register */ +#define KINETIS_USB_ENDPT12_OFFSET 0x00f0 /* Endpoint 12 Control Register */ +#define KINETIS_USB_ENDPT13_OFFSET 0x00f4 /* Endpoint 13 Control Register */ +#define KINETIS_USB_ENDPT14_OFFSET 0x00f8 /* Endpoint 14 Control Register */ +#define KINETIS_USB_ENDPT15_OFFSET 0x00fc /* Endpoint 15 Control Register */ + +#define KINETIS_USB_USBCTRL_OFFSET 0x0100 /* USB Control Register */ +#define KINETIS_USB_OBSERVE_OFFSET 0x0104 /* USB OTG Observe Register */ +#define KINETIS_USB_CONTROL_OFFSET 0x0108 /* USB OTG Control Register */ +#define KINETIS_USB_USBTRC0_OFFSET 0x010c /* USB Transceiver Control Register 0 */ + +#ifdef KINETIS_K64 +# define KINETIS_USB_USBFRMADJUST_OFFSET 0x114 /* Frame Adjust Register */ +# define KINETIS_USB_USB0_CLK_RECOVER_CTRL_OFFSET 0x140 /* USB Clock recovery control */ +# define KINETIS_USB_USB0_CLK_RECOVER_IRC_EN_OFFSET 0x144 /* IRC48M oscillator enable register */ +# define KINETIS_USB_USB0_CLK_RECOVER_INT_STATUS_OFFSET 0x15c /* Clock recovery sperated interrupt status */ +#endif + +/* Register Addresses ***********************************************************************/ + +#define KINETIS_USB0_PERID (KINETIS_USB0_BASE+KINETIS_USB_PERID_OFFSET) +#define KINETIS_USB0_IDCOMP (KINETIS_USB0_BASE+KINETIS_USB_IDCOMP_OFFSET) +#define KINETIS_USB0_REV (KINETIS_USB0_BASE+KINETIS_USB_REV_OFFSET) +#define KINETIS_USB0_ADDINFO (KINETIS_USB0_BASE+KINETIS_USB_ADDINFO_OFFSET) +#define KINETIS_USB0_OTGISTAT (KINETIS_USB0_BASE+KINETIS_USB_OTGISTAT_OFFSET) +#define KINETIS_USB0_OTGICR (KINETIS_USB0_BASE+KINETIS_USB_OTGICR_OFFSET) +#define KINETIS_USB0_OTGSTAT (KINETIS_USB0_BASE+KINETIS_USB_OTGSTAT_OFFSET) +#define KINETIS_USB0_OTGCTL (KINETIS_USB0_BASE+KINETIS_USB_OTGCTL_OFFSET) +#define KINETIS_USB0_ISTAT (KINETIS_USB0_BASE+KINETIS_USB_ISTAT_OFFSET) +#define KINETIS_USB0_INTEN (KINETIS_USB0_BASE+KINETIS_USB_INTEN_OFFSET) +#define KINETIS_USB0_ERRSTAT (KINETIS_USB0_BASE+KINETIS_USB_ERRSTAT_OFFSET) +#define KINETIS_USB0_ERREN (KINETIS_USB0_BASE+KINETIS_USB_ERREN_OFFSET) +#define KINETIS_USB0_STAT (KINETIS_USB0_BASE+KINETIS_USB_STAT_OFFSET) +#define KINETIS_USB0_CTL (KINETIS_USB0_BASE+KINETIS_USB_CTL_OFFSET) +#define KINETIS_USB0_ADDR (KINETIS_USB0_BASE+KINETIS_USB_ADDR_OFFSET) +#define KINETIS_USB0_BDTPAGE1 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE1_OFFSET) +#define KINETIS_USB0_FRMNUML (KINETIS_USB0_BASE+KINETIS_USB_FRMNUML_OFFSET) +#define KINETIS_USB0_FRMNUMH (KINETIS_USB0_BASE+KINETIS_USB_FRMNUMH_OFFSET) +#define KINETIS_USB0_TOKEN (KINETIS_USB0_BASE+KINETIS_USB_TOKEN_OFFSET) +#define KINETIS_USB0_SOFTHLD (KINETIS_USB0_BASE+KINETIS_USB_SOFTHLD_OFFSET) +#define KINETIS_USB0_BDTPAGE2 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE2_OFFSET) +#define KINETIS_USB0_BDTPAGE3 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE3_OFFSET) + +#define KINETIS_USB0_ENDPT(n) (KINETIS_USB0_BASE+KINETIS_USB_ENDPT_OFFSET(n)) +#define KINETIS_USB0_ENDPT0 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT0_OFFSET) +#define KINETIS_USB0_ENDPT1 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT1_OFFSET) +#define KINETIS_USB0_ENDPT2 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT2_OFFSET) +#define KINETIS_USB0_ENDPT3 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT3_OFFSET) +#define KINETIS_USB0_ENDPT4 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT4_OFFSET) +#define KINETIS_USB0_ENDPT5 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT5_OFFSET) +#define KINETIS_USB0_ENDPT6 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT6_OFFSET) +#define KINETIS_USB0_ENDPT7 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT7_OFFSET) +#define KINETIS_USB0_ENDPT8 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT8_OFFSET) +#define KINETIS_USB0_ENDPT9 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT9_OFFSET) +#define KINETIS_USB0_ENDPT10 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT10_OFFSET) +#define KINETIS_USB0_ENDPT11 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT11_OFFSET) +#define KINETIS_USB0_ENDPT12 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT12_OFFSET) +#define KINETIS_USB0_ENDPT13 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT13_OFFSET) +#define KINETIS_USB0_ENDPT14 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT14_OFFSET) +#define KINETIS_USB0_ENDPT15 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT15_OFFSET) + +#define KINETIS_USB0_USBCTRL (KINETIS_USB0_BASE+KINETIS_USB_USBCTRL_OFFSET) +#define KINETIS_USB0_OBSERVE (KINETIS_USB0_BASE+KINETIS_USB_OBSERVE_OFFSET) +#define KINETIS_USB0_CONTROL (KINETIS_USB0_BASE+KINETIS_USB_CONTROL_OFFSET) +#define KINETIS_USB0_USBTRC0 (KINETIS_USB0_BASE+KINETIS_USB_USBTRC0_OFFSET) + +#ifdef KINETIS_K64 +# define KINETIS_USB_USBFRMADJUST \ + (KINETIS_USB0_BASE+KINETIS_USB_USBFRMADJUST_OFFSET) +# define KINETIS_USB_USB0_CLK_RECOVER_CTRL \ + (KINETIS_USB0_BASE+KINETIS_USB_USB0_CLK_RECOVER_CTRL_OFFSET) +# define KINETIS_USB_USB0_CLK_RECOVER_IRC_EN \ + (KINETIS_USB0_BASE+KINETIS_USB_USB0_CLK_RECOVER_IRC_EN_OFFSET) +# define KINETIS_USB_USB0_CLK_RECOVER_INT_STATUS \ + (KINETIS_USB0_BASE+KINETIS_USB_USB0_CLK_RECOVER_INT_STATUS_OFFSET) +#endif + +/* Register Bit Definitions *****************************************************************/ + +/* Peripheral ID Register (8-bit) */ + /* Bits 6-7: Reserved */ +#define USB_PERID_MASK (0x3f) /* Bits 0-5: Peripheral identification bits */ + +/* Peripheral ID Complement Register (8-bit) */ +#define USB_IDCOMP_ + /* Bits 6-7: Reserved */ +#define USB_IDCOMP_MASK (0x3f) /* Bits 0-5: Ones complement of peripheral identification bits */ + +/* Peripheral Revision Register (8-bit revision number) */ + +/* Peripheral Additional Info Register (8-bit) */ + +#define USB_ADDINFO_IEHOST (1 << 0) /* Bit 0: This bit is set if host mode is enabled */ + /* Bits 1-2: Reserved */ +#define USB_ADDINFO_IRQNUM_SHIFT (3) /* Bits 3-7: Assigned Interrupt Request Number */ +#define USB_ADDINFO_IRQNUM_MASK (31 << USB_ADDINFO_IRQNUM_SHIFT) + +/* OTG Interrupt Status Register(8-bit) */ + +#define USB_OTGISTAT_AVBUSCHG (1 << 0) /* Bit 0: Change in VBUS is detected on an A device */ + /* Bit 1: Reserved */ +#define USB_OTGISTAT_B_SESS_CHG (1 << 2) /* Bit 2: Change in VBUS is detected on a B device */ +#define USB_OTGISTAT_SESSVLDCHG (1 << 3) /* Bit 3: Change in VBUS is detected */ + /* Bit 4: Reserved */ +#define USB_OTGISTAT_LINE_STATE_CHG (1 << 5) /* Bit 5: Change USB line state */ +#define USB_OTGISTAT_ONEMSEC (1 << 6) /* Bit 6: Set when the 1 millisecond timer expires */ +#define USB_OTGISTAT_IDCHG (1 << 7) /* Bit 7: Change in ID Signal from the USB connector */ + +/* OTG Interrupt Control Register (8-bit) */ + +#define USB_OTGICR_AVBUSEN (1 << 0) /* Bit 0: A VBUS Valid interrupt enable */ + /* Bit 1: Reserved */ +#define USB_OTGICR_BSESSEN (1 << 2) /* Bit 2: B Session END interrupt enable */ +#define USB_OTGICR_SESSVLDEN (1 << 3) /* Bit 3: Session valid interrupt enable */ + /* Bit 4: Reserved */ +#define USB_OTGICR_LINESTATEEN (1 << 5) /* Bit 5: Line State change interrupt enable */ +#define USB_OTGICR_ONEMSECEN (1 << 6) /* Bit 6: 1 millisecond interrupt enable */ +#define USB_OTGICR_IDEN (1 << 7) /* Bit 7: ID interrupt enable */ + +/* OTG Status Register (8-bit) */ + +#define USB_OTGSTAT_AVBUSVLD (1 << 0) /* Bit 0: A VBUS Valid */ + /* Bit 1: Reserved */ +#define USB_OTGSTAT_BSESSEND (1 << 2) /* Bit 2: B Session END */ +#define USB_OTGSTAT_SESS_VLD (1 << 3) /* Bit 3: Session valid */ + /* Bit 4: Reserved */ +#define USB_OTGSTAT_LINESTATESTABLE (1 << 5) /* Bit 5: OTGISTAT LINE_STATE_CHG bit stable */ +#define USB_OTGSTAT_ONEMSECEN (1 << 6) /* Bit 6: Reserved for the 1msec count */ +#define USB_OTGSTAT_ID (1 << 7) /* Bit 7: Current state of the ID pin on the USB connector */ + +/* OTG Control Register (8-bit) */ + /* Bits 0-1: Reserved */ +#define USB_OTGCTL_OTGEN (1 << 2) /* Bit 2: On-The-Go pullup/pulldown resistor enable */ + /* Bit 3: Reserved */ +#define USB_OTGCTL_DMLOW (1 << 4) /* Bit 4: D- Data Line pull-down resistor enable */ +#define USB_OTGCTL_DPLOW (1 << 5) /* Bit 5: D+ Data Line pull-down resistor enable */ + /* Bit 6: Reserved */ +#define USB_OTGCTL_DPHIGH (1 << 7) /* Bit 7: D+ Data Line pullup resistor enable */ + +/* Interrupt Status Register Interrupt Enable Register (8-bit) */ + +#define USB_INT_USBRST (1 << 0) /* Bit 0: USB Module has decoded a valid USB reset */ +#define USB_INT_ERROR (1 << 1) /* Bit 1: Any of the error conditions within the ERRSTAT register */ +#define USB_INT_SOFTOK (1 << 2) /* Bit 2: USB Module received a Start Of Frame (SOF) token */ +#define USB_INT_TOKDNE (1 << 3) /* Bit 3: Current token being processed has completed */ +#define USB_INT_SLEEP (1 << 4) /* Bit 4: Constant idle on the USB bus for 3 milliseconds */ +#define USB_INT_RESUME (1 << 5) /* Bit 5: Signal remote wake-up signaling */ +#define USB_INT_ATTACH (1 << 6) /* Bit 6: Attach Interrupt */ +#define USB_INT_STALL (1 << 7) /* Bit 7: Stall Interrupt */ + +#define USB_INT_ALL 0xFF + +/* Error Interrupt Status Register and Error Interrupt Enable Register (8-bit) */ + +#define USB_ERRSTAT_PIDERR (1 << 0) /* Bit 0: This bit is set when the PID check field fails */ +#define USB_ERRSTAT_CRC5EOF (1 << 1) /* Bit 1: Host data CRC error or End of frame errors */ +#define USB_ERRSTAT_CRC16 (1 << 2) /* Bit 2: Data packet is rejected due to a CRC16 error */ +#define USB_ERRSTAT_DFN8 (1 << 3) /* Bit 3: Data field received was not 8 bits in length */ +#define USB_ERRSTAT_BTOERR (1 << 4) /* Bit 4: Bus turnaround timeout error occurred */ +#define USB_ERRSTAT_DMAERR (1 << 5) /* Bit 5: DMA error */ + /* Bit 6: Reserved */ +#define USB_ERRSTAT_BTSERR (1 << 7) /* Bit 7: Bit stuff error is detected */ + +#define USB_EINT_ALL 0xBF + +/* Status Register (8-bit) */ + + /* Bits 0-1: Reserved */ +#define USB_STAT_ODD (1 << 2) /* Bit 2: Last Buffer Descriptor was in the odd bank of the BDT */ +#define USB_STAT_TX (1 << 3) /* Bit 3: Transmit Indicator */ +#define USB_STAT_ENDP_SHIFT (4) /* Bits 4-7: Endpoint address that received or transmitted the token */ +#define USB_STAT_ENDP_MASK (15 << USB_STAT_ENDP_SHIFT) + +/* Control Register (8-bit) */ + +#define USB_CTL_USBENSOFEN (1 << 0) /* Bit 0: USB Enable */ +#define USB_CTL_ODDRST (1 << 1) /* Bit 1: Resets all the BDT ODD ping/pong bits to 0 */ +#define USB_CTL_RESUME (1 << 2) /* Bit 2: Enables the USB Module to execute resume signaling */ +#define USB_CTL_HOSTMODEEN (1 << 3) /* Bit 3: Enables the USB Module to operate in Host mode */ +#define USB_CTL_RESET (1 << 4) /* Bit 4: Enables the USB Module to generate USB reset signaling */ +#define USB_CTL_TXSUSPENDTOKENBUSY (1 << 5) /* Bit 5: USB Module is busy executing a USB token */ +#define USB_CTL_SE0 (1 << 6) /* Bit 6: Live USB Single Ended Zero signal */ +#define USB_CTL_JSTATE (1 << 7) /* Bit 7: Live USB differential receiver JSTATE signal */ + +/* Address Register (8-bit) */ + +#define USB_ADDR_LSEN (1 << 7) /* Bit 7: Low Speed Enable bit */ +#define USB_ADDR_SHIFT (0) /* Bits 0-6: USB address */ +#define USB_ADDR_MASK (0x7f << USB_ADDR_SHIFT) + +/* BDT Page Register 1 (8-bit) */ + /* Bit 0: Reserved */ +#define USB_BDTPAGE1_SHIFT (1) /* Bits 1-7: Address bits 9-15 of the BDT base address */ +#define USB_BDTPAGE1_MASK (0x7f << USB_BDTPAGE1_SHIFT) + +/* Frame Number Register Low (8-bit, bits 0-7 of the 11 bit frame number) */ +#define USB_FRMNUML_MASK 0xFF +/* Frame Number Register High (8-bit) */ + /* Bits 3-7: Reserved */ +#define USB_FRMNUMH_SHIFT (0) /* Bits 0-2: Bits 8-10 of the 11-bit frame number */ +#define USB_FRMNUMH_MASK (7 << USB_FRMNUMH_SHIFT) + +/* Token Register (8-bit) */ + +#define USB_TOKEN_ENDPT_SHIFT (0) /* Bits 0-3: Endpoint address for the token command */ +#define USB_TOKEN_ENDPT_MASK (15 << USB_TOKEN_ENDPT_SHIFT) +#define USB_TOKEN_PID_SHIFT (4) /* Bits 4-7: Token type executed by the USB Module */ +#define USB_TOKEN_PID_MASK (15 << USB_TOKEN_PID_SHIFT) +# define USB_TOKEN_PID_OUT (1 << USB_TOKEN_PID_SHIFT) /* OUT Token */ +# define USB_TOKEN_PID_IN (9 << USB_TOKEN_PID_SHIFT) /* IN Token */ +# define USB_TOKEN_PID_SETUP (13 << USB_TOKEN_PID_SHIFT) /* SETUP Token */ + +/* SOF Threshold Register (8-bit count value) */ +/* BDT Page Register 2/3 (16 bit address in two 8-bit registers) */ + +/* Endpoint n Control Register (8-bit) */ + +#define USB_ENDPT_EPHSHK (1 << 0) /* Bit 0: Enable handshaking during a transaction to the endpoint */ +#define USB_ENDPT_EPSTALL (1 << 1) /* Bit 1: Endpoint is stalled */ +#define USB_ENDPT_EPTXEN (1 << 2) /* Bit 2: Enable the endpoint for TX transfers */ +#define USB_ENDPT_EPRXEN (1 << 3) /* Bit 3: Enable the endpoint for RX transfers */ +#define USB_ENDPT_EPCTLDIS (1 << 4) /* Bit 4: Disable control (SETUP) transfers */ + /* Bit 5: Reserved */ +#define USB_ENDPT_RETRYDIS (1 << 6) /* Bit 6: Disable host retry NAK'ed transactions (host EP0) */ +#define USB_ENDPT_HOSTWOHUB (1 << 7) /* Bit 7: Allows the host to communicate to a low speed device (host EP0) */ + +/* USB Control Register (8-bit) */ + /* Bits 0-5: Reserved */ +#define USB_USBCTRL_PDE (1 << 6) /* Bit 6: Enables the weak pulldowns on the USB transceiver */ +#define USB_USBCTRL_SUSP (1 << 7) /* Bit 7: Places the USB transceiver into the suspend state */ + +/* USB OTG Observe Register (8-bit) */ + /* Bits 0-3: Reserved */ +#define USB_OBSERVE_DMPD (1 << 4) /* Bit 4: D- Pull Down signal output from the USB OTG module */ + /* Bit 5: Reserved */ +#define USB_OBSERVE_DPPD (1 << 6) /* Bit 6: D+ Pull Down signal output from the USB OTG module */ +#define USB_OBSERVE_DPPU (1 << 7) /* Bit 7: D+ Pull Up signal output from the USB OTG module */ + +/* USB OTG Control Register (8-bit) */ + /* Bits 0-3: Reserved */ +#define USB_CONTROL_DPPULLUPNONOTG (1 << 4) /* Bit 4: Controls of the DP PULLUP in the USB OTG module */ + /* Bits 5-7: Reserved */ +/* USB Transceiver Control Register 0 (8-bit) */ + +#define USB_USBTRC0_USBRESET (1 << 7) /* Bit 7: USB reset */ + /* Bit 6: Reserved */ +#define USB_USBTRC0_USBRESMEN (1 << 5) /* Bit 5: Asynchronous Resume Interrupt Enable */ + /* Bits 2-4: Reserved */ +#define USB_USBTRC0_SYNC_DET (1 << 1) /* Bit 1: Synchronous USB Interrupt Detect */ +#define USB_USBTRC0_RESUME_INT (1 << 0) /* Bit 0: USB Asynchronous Interrupt */ + +/* Buffer Descriptor Table (BDT) ****************************************************/ +/* Offset 0: On write (software->hardware) */ + +#define USB_BDT_STATUS_MASK 0xfc /* Bits 2-7: Status bits */ +#define USB_BDT_BSTALL (1 << 2) /* Bit 2: Buffer Stall Enable bit */ +#define USB_BDT_DTS (1 << 3) /* Bit 3: Data Toggle Synchronization Enable bit */ +#define USB_BDT_NINC (1 << 4) /* Bit 4: DMA Address Increment Disable bit */ +#define USB_BDT_KEEP (1 << 5) /* Bit 5: BD Keep Enable bit */ +#define USB_BDT_DATA01 (1 << 6) /* Bit 6: Data Toggle Packet bit */ +#define USB_BDT_UOWN (1 << 7) /* Bit 7: USB Own bit */ +#define USB_BDT_BYTECOUNT_SHIFT (16) /* Bits 16-25: Byte Count bits */ +#define USB_BDT_BYTECOUNT_MASK (0x3ff << USB_BDT_BYTECOUNT_SHIFT) + +#define USB_BDT_DATA0 0 /* DATA0 packet expected next */ +#define USB_BDT_DATA1 USB_BDT_DATA01 /* DATA1 packet expected next */ +#define USB_BDT_COWN 0 /* CPU owns the descriptor */ + +/* Offset 0: On read (hardware->software) */ + +#define USB_BDT_PID_SHIFT (2) /* Bits 2-5: Packet Identifier bits */ +#define USB_BDT_PID_MASK (15 << USB_BDT_PID_SHIFT) + /* Bit 7: USB Own bit (same) */ + /* Bits 16-25: Byte Count bits (same) */ + +/* Offset 4: BUFFER_ADDRESS, 32-bit Buffer Address bits */ + +#define USB_BDT_BYTES_SIZE 8 /* Eight bytes per BDT */ +#define USB_BDT_WORD_SIZE 2 /* Two 32-bit words per BDT */ +#define USB_NBDTS_PER_EP 4 /* Number of BDTS per endpoint: IN/OUT and EVEN/ODD */ + +/************************************************************************************ + * Public Types + ************************************************************************************/ + +/******************************************************************************************** + * Public Functions + ********************************************************************************************/ + +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_USBOTG_H */ diff --git a/arch/arm/src/kinetis/kinetis_vrefv1.h b/arch/arm/src/kinetis/chip/kinetis_vrefv1.h similarity index 94% rename from arch/arm/src/kinetis/kinetis_vrefv1.h rename to arch/arm/src/kinetis/chip/kinetis_vrefv1.h index ed9a1ff95c5..29c871dd22d 100644 --- a/arch/arm/src/kinetis/kinetis_vrefv1.h +++ b/arch/arm/src/kinetis/chip/kinetis_vrefv1.h @@ -1,7 +1,7 @@ /******************************************************************************************** - * arch/arm/src/kinetis/kinetis_vrefv1.h + * arch/arm/src/kinetis/chip/kinetis_vrefv1.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ********************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_VREFV1_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_VREFV1_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_VREFV1_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_VREFV1_H /******************************************************************************************** * Included Files @@ -89,4 +89,4 @@ * Public Functions ********************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_VREFV1_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_VREFV1_H */ diff --git a/arch/arm/src/kinetis/kinetis_wdog.h b/arch/arm/src/kinetis/chip/kinetis_wdog.h similarity index 95% rename from arch/arm/src/kinetis/kinetis_wdog.h rename to arch/arm/src/kinetis/chip/kinetis_wdog.h index 326c2cf628f..6f503860499 100644 --- a/arch/arm/src/kinetis/kinetis_wdog.h +++ b/arch/arm/src/kinetis/chip/kinetis_wdog.h @@ -1,7 +1,7 @@ /******************************************************************************************** - * arch/arm/src/kinetis/kinetis_wdog.h + * arch/arm/src/kinetis/chip/kinetis_wdog.h * - * Copyright (C) 2011 Gregory Nutt. All rights reserved. + * Copyright (C) 2011, 2016 Gregory Nutt. All rights reserved. * Author: Gregory Nutt * * Redistribution and use in source and binary forms, with or without @@ -33,8 +33,8 @@ * ********************************************************************************************/ -#ifndef __ARCH_ARM_SRC_KINETIS_KINETIS_WDOG_H -#define __ARCH_ARM_SRC_KINETIS_KINETIS_WDOG_H +#ifndef __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_WDOG_H +#define __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_WDOG_H /******************************************************************************************** * Included Files @@ -90,7 +90,9 @@ #define WDOG_STCTRLH_DBGEN (1 << 5) /* Bit 5: Enables or disables WDOG in Debug mode */ #define WDOG_STCTRLH_STOPEN (1 << 6) /* Bit 6: Enables or disables WDOG in stop mode */ #define WDOG_STCTRLH_WAITEN (1 << 7) /* Bit 7: Enables or disables WDOG in wait mode */ -#define WDOG_STCTRLH_STNDBYEN (1 << 8) /* Bit 8: Enables or disables WDOG in Standby mode */ +#ifndef KINETIS_K64 +# define WDOG_STCTRLH_STNDBYEN (1 << 8) /* Bit 8: Enables or disables WDOG in Standby mode */ +#endif /* Bit 9: Reserved */ #define WDOG_STCTRLH_TESTWDOG (1 << 10) /* Bit 10: Selects functional test mode */ #define WDOG_STCTRLH_TESTSEL (1 << 11) /* Bit 11: Selects the test to be run */ @@ -132,4 +134,4 @@ * Public Functions ********************************************************************************************/ -#endif /* __ARCH_ARM_SRC_KINETIS_KINETIS_WDOG_H */ +#endif /* __ARCH_ARM_SRC_KINETIS_CHIP_KINETIS_WDOG_H */ diff --git a/arch/arm/src/kinetis/kinetis_lowputc.c b/arch/arm/src/kinetis/kinetis_lowputc.c index 989efada5ea..ec85713c933 100644 --- a/arch/arm/src/kinetis/kinetis_lowputc.c +++ b/arch/arm/src/kinetis/kinetis_lowputc.c @@ -49,7 +49,7 @@ #include "kinetis_config.h" #include "kinetis.h" -#include "kinetis_uart.h" +#include "chip/kinetis_uart.h" #include "chip/kinetis_sim.h" #include "chip/kinetis_pinmux.h" diff --git a/arch/arm/src/kinetis/kinetis_serial.c b/arch/arm/src/kinetis/kinetis_serial.c index d47235ba90b..53fd7e2b4ab 100644 --- a/arch/arm/src/kinetis/kinetis_serial.c +++ b/arch/arm/src/kinetis/kinetis_serial.c @@ -59,7 +59,7 @@ #include "kinetis_config.h" #include "chip.h" -#include "kinetis_uart.h" +#include "chip/kinetis_uart.h" #include "kinetis.h" /**************************************************************************** diff --git a/arch/arm/src/kinetis/kinetis_start.c b/arch/arm/src/kinetis/kinetis_start.c index 8de2524ef56..21885d92682 100644 --- a/arch/arm/src/kinetis/kinetis_start.c +++ b/arch/arm/src/kinetis/kinetis_start.c @@ -51,7 +51,7 @@ #include "up_internal.h" #include "kinetis.h" -#include "kinetis_smc.h" +#include "chip/kinetis_smc.h" #include "kinetis_userspace.h" /**************************************************************************** diff --git a/arch/arm/src/kinetis/kinetis_usbotg.h b/arch/arm/src/kinetis/kinetis_usbotg.h index de53d512933..655c7ccee9c 100644 --- a/arch/arm/src/kinetis/kinetis_usbotg.h +++ b/arch/arm/src/kinetis/kinetis_usbotg.h @@ -42,311 +42,7 @@ #include -#include "chip.h" - -/******************************************************************************************** - * Pre-processor Definitions - ********************************************************************************************/ - -/* Register Offsets *************************************************************************/ - -#define KINETIS_USB_PERID_OFFSET 0x0000 /* Peripheral ID Register */ -#define KINETIS_USB_IDCOMP_OFFSET 0x0004 /* Peripheral ID Complement Register */ -#define KINETIS_USB_REV_OFFSET 0x0008 /* Peripheral Revision Register */ -#define KINETIS_USB_ADDINFO_OFFSET 0x000c /* Peripheral Additional Info Register */ -#define KINETIS_USB_OTGISTAT_OFFSET 0x0010 /* OTG Interrupt Status Register */ -#define KINETIS_USB_OTGICR_OFFSET 0x0014 /* OTG Interrupt Control Register */ -#define KINETIS_USB_OTGSTAT_OFFSET 0x0018 /* OTG Status Register */ -#define KINETIS_USB_OTGCTL_OFFSET 0x001c /* OTG Control Register */ -#define KINETIS_USB_ISTAT_OFFSET 0x0080 /* Interrupt Status Register */ -#define KINETIS_USB_INTEN_OFFSET 0x0084 /* Interrupt Enable Register */ -#define KINETIS_USB_ERRSTAT_OFFSET 0x0088 /* Error Interrupt Status Register */ -#define KINETIS_USB_ERREN_OFFSET 0x008c /* Error Interrupt Enable Register */ -#define KINETIS_USB_STAT_OFFSET 0x0090 /* Status Register */ -#define KINETIS_USB_CTL_OFFSET 0x0094 /* Control Register */ -#define KINETIS_USB_ADDR_OFFSET 0x0098 /* Address Register */ -#define KINETIS_USB_BDTPAGE1_OFFSET 0x009c /* BDT Page Register 1 */ -#define KINETIS_USB_FRMNUML_OFFSET 0x00a0 /* Frame Number Register Low */ -#define KINETIS_USB_FRMNUMH_OFFSET 0x00a4 /* Frame Number Register High */ -#define KINETIS_USB_TOKEN_OFFSET 0x00a8 /* Token Register */ -#define KINETIS_USB_SOFTHLD_OFFSET 0x00ac /* SOF Threshold Register */ -#define KINETIS_USB_BDTPAGE2_OFFSET 0x00b0 /* BDT Page Register 2 */ -#define KINETIS_USB_BDTPAGE3_OFFSET 0x00b4 /* BDT Page Register 3 */ - -#define KINETIS_USB_ENDPT_OFFSET(n) (0x00c0+((n)<<2)) /* Endpoint n Control Register */ -#define KINETIS_USB_ENDPT0_OFFSET 0x00c0 /* Endpoint 0 Control Register */ -#define KINETIS_USB_ENDPT1_OFFSET 0x00c4 /* Endpoint 1 Control Register */ -#define KINETIS_USB_ENDPT2_OFFSET 0x00c8 /* Endpoint 2 Control Register */ -#define KINETIS_USB_ENDPT3_OFFSET 0x00cc /* Endpoint 3 Control Register */ -#define KINETIS_USB_ENDPT4_OFFSET 0x00d0 /* Endpoint 4 Control Register */ -#define KINETIS_USB_ENDPT5_OFFSET 0x00d4 /* Endpoint 5 Control Register */ -#define KINETIS_USB_ENDPT6_OFFSET 0x00d8 /* Endpoint 6 Control Register */ -#define KINETIS_USB_ENDPT7_OFFSET 0x00dc /* Endpoint 7 Control Register */ -#define KINETIS_USB_ENDPT8_OFFSET 0x00e0 /* Endpoint 8 Control Register */ -#define KINETIS_USB_ENDPT9_OFFSET 0x00e4 /* Endpoint 9 Control Register */ -#define KINETIS_USB_ENDPT10_OFFSET 0x00e8 /* Endpoint 10 Control Register */ -#define KINETIS_USB_ENDPT11_OFFSET 0x00ec /* Endpoint 11 Control Register */ -#define KINETIS_USB_ENDPT12_OFFSET 0x00f0 /* Endpoint 12 Control Register */ -#define KINETIS_USB_ENDPT13_OFFSET 0x00f4 /* Endpoint 13 Control Register */ -#define KINETIS_USB_ENDPT14_OFFSET 0x00f8 /* Endpoint 14 Control Register */ -#define KINETIS_USB_ENDPT15_OFFSET 0x00fc /* Endpoint 15 Control Register */ - -#define KINETIS_USB_USBCTRL_OFFSET 0x0100 /* USB Control Register */ -#define KINETIS_USB_OBSERVE_OFFSET 0x0104 /* USB OTG Observe Register */ -#define KINETIS_USB_CONTROL_OFFSET 0x0108 /* USB OTG Control Register */ -#define KINETIS_USB_USBTRC0_OFFSET 0x010c /* USB Transceiver Control Register 0 */ - -/* Register Addresses ***********************************************************************/ - -#define KINETIS_USB0_PERID (KINETIS_USB0_BASE+KINETIS_USB_PERID_OFFSET) -#define KINETIS_USB0_IDCOMP (KINETIS_USB0_BASE+KINETIS_USB_IDCOMP_OFFSET) -#define KINETIS_USB0_REV (KINETIS_USB0_BASE+KINETIS_USB_REV_OFFSET) -#define KINETIS_USB0_ADDINFO (KINETIS_USB0_BASE+KINETIS_USB_ADDINFO_OFFSET) -#define KINETIS_USB0_OTGISTAT (KINETIS_USB0_BASE+KINETIS_USB_OTGISTAT_OFFSET) -#define KINETIS_USB0_OTGICR (KINETIS_USB0_BASE+KINETIS_USB_OTGICR_OFFSET) -#define KINETIS_USB0_OTGSTAT (KINETIS_USB0_BASE+KINETIS_USB_OTGSTAT_OFFSET) -#define KINETIS_USB0_OTGCTL (KINETIS_USB0_BASE+KINETIS_USB_OTGCTL_OFFSET) -#define KINETIS_USB0_ISTAT (KINETIS_USB0_BASE+KINETIS_USB_ISTAT_OFFSET) -#define KINETIS_USB0_INTEN (KINETIS_USB0_BASE+KINETIS_USB_INTEN_OFFSET) -#define KINETIS_USB0_ERRSTAT (KINETIS_USB0_BASE+KINETIS_USB_ERRSTAT_OFFSET) -#define KINETIS_USB0_ERREN (KINETIS_USB0_BASE+KINETIS_USB_ERREN_OFFSET) -#define KINETIS_USB0_STAT (KINETIS_USB0_BASE+KINETIS_USB_STAT_OFFSET) -#define KINETIS_USB0_CTL (KINETIS_USB0_BASE+KINETIS_USB_CTL_OFFSET) -#define KINETIS_USB0_ADDR (KINETIS_USB0_BASE+KINETIS_USB_ADDR_OFFSET) -#define KINETIS_USB0_BDTPAGE1 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE1_OFFSET) -#define KINETIS_USB0_FRMNUML (KINETIS_USB0_BASE+KINETIS_USB_FRMNUML_OFFSET) -#define KINETIS_USB0_FRMNUMH (KINETIS_USB0_BASE+KINETIS_USB_FRMNUMH_OFFSET) -#define KINETIS_USB0_TOKEN (KINETIS_USB0_BASE+KINETIS_USB_TOKEN_OFFSET) -#define KINETIS_USB0_SOFTHLD (KINETIS_USB0_BASE+KINETIS_USB_SOFTHLD_OFFSET) -#define KINETIS_USB0_BDTPAGE2 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE2_OFFSET) -#define KINETIS_USB0_BDTPAGE3 (KINETIS_USB0_BASE+KINETIS_USB_BDTPAGE3_OFFSET) - -#define KINETIS_USB0_ENDPT(n) (KINETIS_USB0_BASE+KINETIS_USB_ENDPT_OFFSET(n)) -#define KINETIS_USB0_ENDPT0 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT0_OFFSET) -#define KINETIS_USB0_ENDPT1 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT1_OFFSET) -#define KINETIS_USB0_ENDPT2 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT2_OFFSET) -#define KINETIS_USB0_ENDPT3 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT3_OFFSET) -#define KINETIS_USB0_ENDPT4 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT4_OFFSET) -#define KINETIS_USB0_ENDPT5 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT5_OFFSET) -#define KINETIS_USB0_ENDPT6 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT6_OFFSET) -#define KINETIS_USB0_ENDPT7 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT7_OFFSET) -#define KINETIS_USB0_ENDPT8 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT8_OFFSET) -#define KINETIS_USB0_ENDPT9 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT9_OFFSET) -#define KINETIS_USB0_ENDPT10 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT10_OFFSET) -#define KINETIS_USB0_ENDPT11 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT11_OFFSET) -#define KINETIS_USB0_ENDPT12 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT12_OFFSET) -#define KINETIS_USB0_ENDPT13 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT13_OFFSET) -#define KINETIS_USB0_ENDPT14 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT14_OFFSET) -#define KINETIS_USB0_ENDPT15 (KINETIS_USB0_BASE+KINETIS_USB_ENDPT15_OFFSET) - -#define KINETIS_USB0_USBCTRL (KINETIS_USB0_BASE+KINETIS_USB_USBCTRL_OFFSET) -#define KINETIS_USB0_OBSERVE (KINETIS_USB0_BASE+KINETIS_USB_OBSERVE_OFFSET) -#define KINETIS_USB0_CONTROL (KINETIS_USB0_BASE+KINETIS_USB_CONTROL_OFFSET) -#define KINETIS_USB0_USBTRC0 (KINETIS_USB0_BASE+KINETIS_USB_USBTRC0_OFFSET) - -/* Register Bit Definitions *****************************************************************/ - -/* Peripheral ID Register (8-bit) */ - /* Bits 6-7: Reserved */ -#define USB_PERID_MASK (0x3f) /* Bits 0-5: Peripheral identification bits */ - -/* Peripheral ID Complement Register (8-bit) */ -#define USB_IDCOMP_ - /* Bits 6-7: Reserved */ -#define USB_IDCOMP_MASK (0x3f) /* Bits 0-5: Ones complement of peripheral identification bits */ - -/* Peripheral Revision Register (8-bit revision number) */ - -/* Peripheral Additional Info Register (8-bit) */ - -#define USB_ADDINFO_IEHOST (1 << 0) /* Bit 0: This bit is set if host mode is enabled */ - /* Bits 1-2: Reserved */ -#define USB_ADDINFO_IRQNUM_SHIFT (3) /* Bits 3-7: Assigned Interrupt Request Number */ -#define USB_ADDINFO_IRQNUM_MASK (31 << USB_ADDINFO_IRQNUM_SHIFT) - -/* OTG Interrupt Status Register(8-bit) */ - -#define USB_OTGISTAT_AVBUSCHG (1 << 0) /* Bit 0: Change in VBUS is detected on an A device */ - /* Bit 1: Reserved */ -#define USB_OTGISTAT_B_SESS_CHG (1 << 2) /* Bit 2: Change in VBUS is detected on a B device */ -#define USB_OTGISTAT_SESSVLDCHG (1 << 3) /* Bit 3: Change in VBUS is detected */ - /* Bit 4: Reserved */ -#define USB_OTGISTAT_LINE_STATE_CHG (1 << 5) /* Bit 5: Change USB line state */ -#define USB_OTGISTAT_ONEMSEC (1 << 6) /* Bit 6: Set when the 1 millisecond timer expires */ -#define USB_OTGISTAT_IDCHG (1 << 7) /* Bit 7: Change in ID Signal from the USB connector */ - -/* OTG Interrupt Control Register (8-bit) */ - -#define USB_OTGICR_AVBUSEN (1 << 0) /* Bit 0: A VBUS Valid interrupt enable */ - /* Bit 1: Reserved */ -#define USB_OTGICR_BSESSEN (1 << 2) /* Bit 2: B Session END interrupt enable */ -#define USB_OTGICR_SESSVLDEN (1 << 3) /* Bit 3: Session valid interrupt enable */ - /* Bit 4: Reserved */ -#define USB_OTGICR_LINESTATEEN (1 << 5) /* Bit 5: Line State change interrupt enable */ -#define USB_OTGICR_ONEMSECEN (1 << 6) /* Bit 6: 1 millisecond interrupt enable */ -#define USB_OTGICR_IDEN (1 << 7) /* Bit 7: ID interrupt enable */ - -/* OTG Status Register (8-bit) */ - -#define USB_OTGSTAT_AVBUSVLD (1 << 0) /* Bit 0: A VBUS Valid */ - /* Bit 1: Reserved */ -#define USB_OTGSTAT_BSESSEND (1 << 2) /* Bit 2: B Session END */ -#define USB_OTGSTAT_SESS_VLD (1 << 3) /* Bit 3: Session valid */ - /* Bit 4: Reserved */ -#define USB_OTGSTAT_LINESTATESTABLE (1 << 5) /* Bit 5: OTGISTAT LINE_STATE_CHG bit stable */ -#define USB_OTGSTAT_ONEMSECEN (1 << 6) /* Bit 6: Reserved for the 1msec count */ -#define USB_OTGSTAT_ID (1 << 7) /* Bit 7: Current state of the ID pin on the USB connector */ - -/* OTG Control Register (8-bit) */ - /* Bits 0-1: Reserved */ -#define USB_OTGCTL_OTGEN (1 << 2) /* Bit 2: On-The-Go pullup/pulldown resistor enable */ - /* Bit 3: Reserved */ -#define USB_OTGCTL_DMLOW (1 << 4) /* Bit 4: D- Data Line pull-down resistor enable */ -#define USB_OTGCTL_DPLOW (1 << 5) /* Bit 5: D+ Data Line pull-down resistor enable */ - /* Bit 6: Reserved */ -#define USB_OTGCTL_DPHIGH (1 << 7) /* Bit 7: D+ Data Line pullup resistor enable */ - -/* Interrupt Status Register Interrupt Enable Register (8-bit) */ - -#define USB_INT_USBRST (1 << 0) /* Bit 0: USB Module has decoded a valid USB reset */ -#define USB_INT_ERROR (1 << 1) /* Bit 1: Any of the error conditions within the ERRSTAT register */ -#define USB_INT_SOFTOK (1 << 2) /* Bit 2: USB Module received a Start Of Frame (SOF) token */ -#define USB_INT_TOKDNE (1 << 3) /* Bit 3: Current token being processed has completed */ -#define USB_INT_SLEEP (1 << 4) /* Bit 4: Constant idle on the USB bus for 3 milliseconds */ -#define USB_INT_RESUME (1 << 5) /* Bit 5: Signal remote wake-up signaling */ -#define USB_INT_ATTACH (1 << 6) /* Bit 6: Attach Interrupt */ -#define USB_INT_STALL (1 << 7) /* Bit 7: Stall Interrupt */ - -#define USB_INT_ALL 0xFF - -/* Error Interrupt Status Register and Error Interrupt Enable Register (8-bit) */ - -#define USB_ERRSTAT_PIDERR (1 << 0) /* Bit 0: This bit is set when the PID check field fails */ -#define USB_ERRSTAT_CRC5EOF (1 << 1) /* Bit 1: Host data CRC error or End of frame errors */ -#define USB_ERRSTAT_CRC16 (1 << 2) /* Bit 2: Data packet is rejected due to a CRC16 error */ -#define USB_ERRSTAT_DFN8 (1 << 3) /* Bit 3: Data field received was not 8 bits in length */ -#define USB_ERRSTAT_BTOERR (1 << 4) /* Bit 4: Bus turnaround timeout error occurred */ -#define USB_ERRSTAT_DMAERR (1 << 5) /* Bit 5: DMA error */ - /* Bit 6: Reserved */ -#define USB_ERRSTAT_BTSERR (1 << 7) /* Bit 7: Bit stuff error is detected */ - -#define USB_EINT_ALL 0xBF - -/* Status Register (8-bit) */ - - /* Bits 0-1: Reserved */ -#define USB_STAT_ODD (1 << 2) /* Bit 2: Last Buffer Descriptor was in the odd bank of the BDT */ -#define USB_STAT_TX (1 << 3) /* Bit 3: Transmit Indicator */ -#define USB_STAT_ENDP_SHIFT (4) /* Bits 4-7: Endpoint address that received or transmitted the token */ -#define USB_STAT_ENDP_MASK (15 << USB_STAT_ENDP_SHIFT) - -/* Control Register (8-bit) */ - -#define USB_CTL_USBENSOFEN (1 << 0) /* Bit 0: USB Enable */ -#define USB_CTL_ODDRST (1 << 1) /* Bit 1: Resets all the BDT ODD ping/pong bits to 0 */ -#define USB_CTL_RESUME (1 << 2) /* Bit 2: Enables the USB Module to execute resume signaling */ -#define USB_CTL_HOSTMODEEN (1 << 3) /* Bit 3: Enables the USB Module to operate in Host mode */ -#define USB_CTL_RESET (1 << 4) /* Bit 4: Enables the USB Module to generate USB reset signaling */ -#define USB_CTL_TXSUSPENDTOKENBUSY (1 << 5) /* Bit 5: USB Module is busy executing a USB token */ -#define USB_CTL_SE0 (1 << 6) /* Bit 6: Live USB Single Ended Zero signal */ -#define USB_CTL_JSTATE (1 << 7) /* Bit 7: Live USB differential receiver JSTATE signal */ - -/* Address Register (8-bit) */ - -#define USB_ADDR_LSEN (1 << 7) /* Bit 7: Low Speed Enable bit */ -#define USB_ADDR_SHIFT (0) /* Bits 0-6: USB address */ -#define USB_ADDR_MASK (0x7f << USB_ADDR_SHIFT) - -/* BDT Page Register 1 (8-bit) */ - /* Bit 0: Reserved */ -#define USB_BDTPAGE1_SHIFT (1) /* Bits 1-7: Address bits 9-15 of the BDT base address */ -#define USB_BDTPAGE1_MASK (0x7f << USB_BDTPAGE1_SHIFT) - -/* Frame Number Register Low (8-bit, bits 0-7 of the 11 bit frame number) */ -#define USB_FRMNUML_MASK 0xFF -/* Frame Number Register High (8-bit) */ - /* Bits 3-7: Reserved */ -#define USB_FRMNUMH_SHIFT (0) /* Bits 0-2: Bits 8-10 of the 11-bit frame number */ -#define USB_FRMNUMH_MASK (7 << USB_FRMNUMH_SHIFT) - -/* Token Register (8-bit) */ - -#define USB_TOKEN_ENDPT_SHIFT (0) /* Bits 0-3: Endpoint address for the token command */ -#define USB_TOKEN_ENDPT_MASK (15 << USB_TOKEN_ENDPT_SHIFT) -#define USB_TOKEN_PID_SHIFT (4) /* Bits 4-7: Token type executed by the USB Module */ -#define USB_TOKEN_PID_MASK (15 << USB_TOKEN_PID_SHIFT) -# define USB_TOKEN_PID_OUT (1 << USB_TOKEN_PID_SHIFT) /* OUT Token */ -# define USB_TOKEN_PID_IN (9 << USB_TOKEN_PID_SHIFT) /* IN Token */ -# define USB_TOKEN_PID_SETUP (13 << USB_TOKEN_PID_SHIFT) /* SETUP Token */ - -/* SOF Threshold Register (8-bit count value) */ -/* BDT Page Register 2/3 (16 bit address in two 8-bit registers) */ - -/* Endpoint n Control Register (8-bit) */ - -#define USB_ENDPT_EPHSHK (1 << 0) /* Bit 0: Enable handshaking during a transaction to the endpoint */ -#define USB_ENDPT_EPSTALL (1 << 1) /* Bit 1: Endpoint is stalled */ -#define USB_ENDPT_EPTXEN (1 << 2) /* Bit 2: Enable the endpoint for TX transfers */ -#define USB_ENDPT_EPRXEN (1 << 3) /* Bit 3: Enable the endpoint for RX transfers */ -#define USB_ENDPT_EPCTLDIS (1 << 4) /* Bit 4: Disable control (SETUP) transfers */ - /* Bit 5: Reserved */ -#define USB_ENDPT_RETRYDIS (1 << 6) /* Bit 6: Disable host retry NAK'ed transactions (host EP0) */ -#define USB_ENDPT_HOSTWOHUB (1 << 7) /* Bit 7: Allows the host to communicate to a low speed device (host EP0) */ - -/* USB Control Register (8-bit) */ - /* Bits 0-5: Reserved */ -#define USB_USBCTRL_PDE (1 << 6) /* Bit 6: Enables the weak pulldowns on the USB transceiver */ -#define USB_USBCTRL_SUSP (1 << 7) /* Bit 7: Places the USB transceiver into the suspend state */ - -/* USB OTG Observe Register (8-bit) */ - /* Bits 0-3: Reserved */ -#define USB_OBSERVE_DMPD (1 << 4) /* Bit 4: D- Pull Down signal output from the USB OTG module */ - /* Bit 5: Reserved */ -#define USB_OBSERVE_DPPD (1 << 6) /* Bit 6: D+ Pull Down signal output from the USB OTG module */ -#define USB_OBSERVE_DPPU (1 << 7) /* Bit 7: D+ Pull Up signal output from the USB OTG module */ - -/* USB OTG Control Register (8-bit) */ - /* Bits 0-3: Reserved */ -#define USB_CONTROL_DPPULLUPNONOTG (1 << 4) /* Bit 4: Controls of the DP PULLUP in the USB OTG module */ - /* Bits 5-7: Reserved */ -/* USB Transceiver Control Register 0 (8-bit) */ - -#define USB_USBTRC0_USBRESET (1 << 7) /* Bit 7: USB reset */ - /* Bit 6: Reserved */ -#define USB_USBTRC0_USBRESMEN (1 << 5) /* Bit 5: Asynchronous Resume Interrupt Enable */ - /* Bits 2-4: Reserved */ -#define USB_USBTRC0_SYNC_DET (1 << 1) /* Bit 1: Synchronous USB Interrupt Detect */ -#define USB_USBTRC0_RESUME_INT (1 << 0) /* Bit 0: USB Asynchronous Interrupt */ - -/* Buffer Descriptor Table (BDT) ****************************************************/ -/* Offset 0: On write (software->hardware) */ - -#define USB_BDT_STATUS_MASK 0xfc /* Bits 2-7: Status bits */ -#define USB_BDT_BSTALL (1 << 2) /* Bit 2: Buffer Stall Enable bit */ -#define USB_BDT_DTS (1 << 3) /* Bit 3: Data Toggle Synchronization Enable bit */ -#define USB_BDT_NINC (1 << 4) /* Bit 4: DMA Address Increment Disable bit */ -#define USB_BDT_KEEP (1 << 5) /* Bit 5: BD Keep Enable bit */ -#define USB_BDT_DATA01 (1 << 6) /* Bit 6: Data Toggle Packet bit */ -#define USB_BDT_UOWN (1 << 7) /* Bit 7: USB Own bit */ -#define USB_BDT_BYTECOUNT_SHIFT (16) /* Bits 16-25: Byte Count bits */ -#define USB_BDT_BYTECOUNT_MASK (0x3ff << USB_BDT_BYTECOUNT_SHIFT) - -#define USB_BDT_DATA0 0 /* DATA0 packet expected next */ -#define USB_BDT_DATA1 USB_BDT_DATA01 /* DATA1 packet expected next */ -#define USB_BDT_COWN 0 /* CPU owns the descriptor */ - -/* Offset 0: On read (hardware->software) */ - -#define USB_BDT_PID_SHIFT (2) /* Bits 2-5: Packet Identifier bits */ -#define USB_BDT_PID_MASK (15 << USB_BDT_PID_SHIFT) - /* Bit 7: USB Own bit (same) */ - /* Bits 16-25: Byte Count bits (same) */ - -/* Offset 4: BUFFER_ADDRESS, 32-bit Buffer Address bits */ - -#define USB_BDT_BYTES_SIZE 8 /* Eight bytes per BDT */ -#define USB_BDT_WORD_SIZE 2 /* Two 32-bit words per BDT */ -#define USB_NBDTS_PER_EP 4 /* Number of BDTS per endpoint: IN/OUT and EVEN/ODD */ +#include "chip/kinetis_usbotg.h" /************************************************************************************ * Public Types diff --git a/arch/arm/src/kinetis/kinetis_vectors.S b/arch/arm/src/kinetis/kinetis_vectors.S index 75c295ae033..39f07fc000f 100644 --- a/arch/arm/src/kinetis/kinetis_vectors.S +++ b/arch/arm/src/kinetis/kinetis_vectors.S @@ -42,6 +42,7 @@ #include +#include "chip.h" #include "exc_return.h" /************************************************************************************************ @@ -160,7 +161,7 @@ _vectors: * K20P64M72SF1RM */ -#if defined(CONFIG_ARCH_CHIP_MK20DX256VLH7) +#if defined(KINETIS_K20) .word kinetis_dmach0 /* Vector 16: DMA channel 0 transfer complete */ .word kinetis_dmach1 /* Vector 17: DMA channel 1 transfer complete */ .word kinetis_dmach2 /* Vector 18: DMA channel 2 transfer complete */ @@ -263,9 +264,7 @@ _vectors: * K40P144M100SF2RM */ -#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100) +#elif defined(KINETIS_K40) .word kinetis_dmach0 /* Vector 16: DMA channel 0 transfer complete */ .word kinetis_dmach1 /* Vector 17: DMA channel 1 transfer complete */ @@ -369,10 +368,7 @@ _vectors: * K60P144M100SF2RM */ -#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) || defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) || \ - defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK60N256VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK60X256VMD100) || defined(CONFIG_ARCH_CHIP_MK60N512VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK60N512VLL100) +#elif defined(KINETIS_K60) .word kinetis_dmach0 /* Vector 16: DMA channel 0 transfer complete */ .word kinetis_dmach1 /* Vector 17: DMA channel 1 transfer complete */ @@ -478,6 +474,102 @@ _vectors: .word kinetis_reserved /* Vector 117: Reserved */ .word kinetis_reserved /* Vector 118: Reserved */ .word kinetis_reserved /* Vector 119: Reserved */ + +/* K64 Family *********************************************************************************** + * + * The memory map for the following parts is defined in Freescale document + * MK64FX512VLL12 + */ + +#elif defined(KINETIS_K64) + + .word kinetis_dmach0 /* Vector 16: DMA channel 0 transfer complete */ + .word kinetis_dmach1 /* Vector 17: DMA channel 1 transfer complete */ + .word kinetis_dmach2 /* Vector 18: DMA channel 2 transfer complete */ + .word kinetis_dmach3 /* Vector 19: DMA channel 3 transfer complete */ + .word kinetis_dmach4 /* Vector 20: DMA channel 4 transfer complete */ + .word kinetis_dmach5 /* Vector 21: DMA channel 5 transfer complete */ + .word kinetis_dmach6 /* Vector 22: DMA channel 6 transfer complete */ + .word kinetis_dmach7 /* Vector 23: DMA channel 7 transfer complete */ + .word kinetis_dmach8 /* Vector 24: DMA channel 8 transfer complete */ + .word kinetis_dmach9 /* Vector 25: DMA channel 9 transfer complete */ + .word kinetis_dmach10 /* Vector 26: DMA channel 10 transfer complete */ + .word kinetis_dmach11 /* Vector 27: DMA channel 11 transfer complete */ + .word kinetis_dmach12 /* Vector 28: DMA channel 12 transfer complete */ + .word kinetis_dmach13 /* Vector 29: DMA channel 13 transfer complete */ + .word kinetis_dmach14 /* Vector 30: DMA channel 14 transfer complete */ + .word kinetis_dmach15 /* Vector 31: DMA channel 15 transfer complete */ + .word kinetis_dmaerr /* Vector 32: DMA error interrupt channels 0-15 */ + .word kinetis_mcm /* Vector 33: MCM Normal interrupt */ + .word kinetis_flashcc /* Vector 34: Flash memory command complete */ + .word kinetis_flashrc /* Vector 35: Flash memory read collision */ + .word kinetis_smclvd /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */ + .word kinetis_llwu /* Vector 37: LLWU Normal Low Leakage Wakeup */ + .word kinetis_wdog /* Vector 38: Watchdog */ + .word kinetis_rngb /* Vector 39: Random number generator */ + .word kinetis_i2c0 /* Vector 40: I2C0 */ + .word kinetis_i2c1 /* Vector 41: I2C1 */ + .word kinetis_spi0 /* Vector 42: SPI0 all sources */ + .word kinetis_spi1 /* Vector 43: SPI1 all sources */ + .word kinetis_i2s0 /* Vector 44: Transmit */ + .word kinetis_i2s1 /* Vector 45: Transmit */ + .word kinetis_reserved /* Vector 46: Reserved */ + .word kinetis_uart0s /* Vector 47: UART0 status */ + .word kinetis_uart0e /* Vector 48: UART0 error */ + .word kinetis_uart1s /* Vector 49: UART1 status */ + .word kinetis_uart1e /* Vector 50: UART1 error */ + .word kinetis_uart2s /* Vector 51: UART2 status */ + .word kinetis_uart2e /* Vector 52: UART2 error */ + .word kinetis_uart3s /* Vector 53: UART3 status */ + .word kinetis_uart3e /* Vector 54: UART3 error */ + .word kinetis_adc0 /* Vector 55: ADC0 */ + .word kinetis_cmp0 /* Vector 56: CMP0 */ + .word kinetis_cmp1 /* Vector 57: CMP1 */ + .word kinetis_ftm0 /* Vector 58: FTM0 all sources */ + .word kinetis_ftm1 /* Vector 59: FTM1 all sources */ + .word kinetis_ftm2 /* Vector 60: FTM2 all sources */ + .word kinetis_cmt /* Vector 61: CMT */ + .word kinetis_rtc0 /* Vector 62: RTC alarm interrupt */ + .word kinetis_rtc1 /* Vector 63: RTC seconds interrupt */ + .word kinetis_pitch0 /* Vector 64: PIT channel 0 */ + .word kinetis_pitch1 /* Vector 65: PIT channel 1 */ + .word kinetis_pitch2 /* Vector 66: PIT channel 2 */ + .word kinetis_pitch3 /* Vector 67: PIT channel 3 */ + .word kinetis_pdb /* Vector 68: PDB */ + .word kinetis_usbotg /* Vector 68: USB OTG */ + .word kinetis_usbcd /* Vector 70: USB charger detect */ + .word kinetis_reserved /* Vector 71: Reserved */ + .word kinetis_dac0 /* Vector 72: DAC0 */ + .word kinetis_mcg /* Vector 73: MCG */ + .word kinetis_lpt /* Vector 74: Low power timer */ + .word kinetis_porta /* Vector 75: Pin detect port A */ + .word kinetis_portb /* Vector 76: Pin detect port B */ + .word kinetis_portc /* Vector 77: Pin detect port C */ + .word kinetis_portd /* Vector 78: Pin detect port D */ + .word kinetis_porte /* Vector 79: Pin detect port E */ + .word kinetis_software /* Vector 80: Software interrupt */ + .word kinetis_spi2 /* Vector 81: SPI2 all sources */ + .word kinetis_uart4s /* Vector 82: UART4 status */ + .word kinetis_uart4e /* Vector 83: UART4 error */ + .word kinetis_uart5s /* Vector 84: UART5 status */ + .word kinetis_uart5e /* Vector 85: UART5 error */ + .word kinetis_cmp2 /* Vector 86: CMP2 */ + .word kinetis_ftm3 /* Vector 87: FTM3 all sources */ + .word kinetis_dac1 /* Vector 88: DAC1 */ + .word kinetis_adc1 /* Vector 89: ADC1 */ + .word kinetis_i2c2 /* Vector 90: I2C2 */ + .word kinetis_can0mb /* Vector 91: CAN0 ORed Message buffer (0-15) */ + .word kinetis_can0bo /* Vector 92: CAN0 Bus Off */ + .word kinetis_can0err /* Vector 93: CAN0 Error */ + .word kinetis_can0tw /* Vector 94: CAN0 Transmit Warning */ + .word kinetis_can0rw /* Vector 95: CAN0 Receive Warning */ + .word kinetis_can0wu /* Vector 96: CAN0 Wake UP */ + .word kinetis_sdhc /* Vector 97: SDHC */ + .word kinetis_emactmr /* Vector 91: Ethernet MAC IEEE 1588 timer interrupt */ + .word kinetis_emactx /* Vector 92: Ethernet MAC transmit interrupt */ + .word kinetis_emacrx /* Vector 93: Ethernet MAC receive interrupt */ + .word kinetis_emacmisc /* Vector 94: Ethernet MAC error and misc interrupt */ + #else # error "No vectors for this Kinetis part" #endif @@ -505,13 +597,13 @@ handlers: HANDLER kinetis_systick, KINETIS_IRQ_SYSTICK /* Vector 15: System tick */ /* External Interrupts **************************************************************************/ -/* K40 Family *********************************************************************************** +/* K20 Family *********************************************************************************** * * The interrupt vectors for the following parts is defined in Freescale document * K20P64M72SF1RM */ -#if defined(CONFIG_ARCH_CHIP_MK20DX256VLH7) +#if defined(KINETIS_K20) HANDLER kinetis_dmach0, KINETIS_IRQ_DMACH0 /* Vector 16: DMA channel 0 transfer complete */ HANDLER kinetis_dmach1, KINETIS_IRQ_DMACH1 /* Vector 17: DMA channel 1 transfer complete */ @@ -585,9 +677,7 @@ handlers: * K40P144M100SF2RM */ -#elif defined(CONFIG_ARCH_CHIP_MK40X128VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X128VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK40X256VLQ100) || defined(CONFIG_ARCH_CHIP_MK40X256VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK40N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK40N512VMD100) +#elif defined(KINETIS_K40) HANDLER kinetis_dmach0, KINETIS_IRQ_DMACH0 /* Vector 16: DMA channel 0 transfer complete */ HANDLER kinetis_dmach1, KINETIS_IRQ_DMACH1 /* Vector 17: DMA channel 1 transfer complete */ @@ -679,10 +769,7 @@ handlers: * K60P144M100SF2RM */ -#elif defined(CONFIG_ARCH_CHIP_MK60N256VLQ100) || defined(CONFIG_ARCH_CHIP_MK60X256VLQ100) || \ - defined(CONFIG_ARCH_CHIP_MK60N512VLQ100) || defined(CONFIG_ARCH_CHIP_MK60N256VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK60X256VMD100) || defined(CONFIG_ARCH_CHIP_MK60N512VMD100) || \ - defined(CONFIG_ARCH_CHIP_MK60N512VLL100) +#elif defined(KINETIS_K60) HANDLER kinetis_dmach0, KINETIS_IRQ_DMACH0 /* Vector 16: DMA channel 0 transfer complete */ HANDLER kinetis_dmach1, KINETIS_IRQ_DMACH1 /* Vector 17: DMA channel 1 transfer complete */ @@ -771,6 +858,99 @@ handlers: HANDLER kinetis_portd, KINETIS_IRQ_PORTD /* Vector 106: Pin detect port D */ HANDLER kinetis_porte, KINETIS_IRQ_PORTE /* Vector 107: Pin detect port E */ +/* K64 Family *********************************************************************************** + * + * The memory map for the following parts is defined in Freescale document + * MK64FX512VLL12 + */ + +#elif defined(KINETIS_K64) + + HANDLER kinetis_dmach0, KINETIS_IRQ_DMACH0 /* Vector 16: DMA channel 0 transfer complete */ + HANDLER kinetis_dmach1, KINETIS_IRQ_DMACH1 /* Vector 17: DMA channel 1 transfer complete */ + HANDLER kinetis_dmach2, KINETIS_IRQ_DMACH2 /* Vector 18: DMA channel 2 transfer complete */ + HANDLER kinetis_dmach3, KINETIS_IRQ_DMACH3 /* Vector 19: DMA channel 3 transfer complete */ + HANDLER kinetis_dmach4, KINETIS_IRQ_DMACH4 /* Vector 20: DMA channel 4 transfer complete */ + HANDLER kinetis_dmach5, KINETIS_IRQ_DMACH5 /* Vector 21: DMA channel 5 transfer complete */ + HANDLER kinetis_dmach6, KINETIS_IRQ_DMACH6 /* Vector 22: DMA channel 6 transfer complete */ + HANDLER kinetis_dmach7, KINETIS_IRQ_DMACH7 /* Vector 23: DMA channel 7 transfer complete */ + HANDLER kinetis_dmach8, KINETIS_IRQ_DMACH8 /* Vector 24: DMA channel 8 transfer complete */ + HANDLER kinetis_dmach9, KINETIS_IRQ_DMACH9 /* Vector 25: DMA channel 9 transfer complete */ + HANDLER kinetis_dmach10, KINETIS_IRQ_DMACH10 /* Vector 26: DMA channel 10 transfer complete */ + HANDLER kinetis_dmach11, KINETIS_IRQ_DMACH11 /* Vector 27: DMA channel 11 transfer complete */ + HANDLER kinetis_dmach12, KINETIS_IRQ_DMACH12 /* Vector 28: DMA channel 12 transfer complete */ + HANDLER kinetis_dmach13, KINETIS_IRQ_DMACH13 /* Vector 29: DMA channel 13 transfer complete */ + HANDLER kinetis_dmach14, KINETIS_IRQ_DMACH14 /* Vector 30: DMA channel 14 transfer complete */ + HANDLER kinetis_dmach15, KINETIS_IRQ_DMACH15 /* Vector 31: DMA channel 15 transfer complete */ + HANDLER kinetis_dmaerr, KINETIS_IRQ_DMAERR /* Vector 32: DMA error interrupt channels 0-15 */ + HANDLER kinetis_mcm, KINETIS_IRQ_MCM /* Vector 33: MCM Normal interrupt */ + HANDLER kinetis_flashcc, KINETIS_IRQ_FLASHCC /* Vector 34: Flash memory command complete */ + HANDLER kinetis_flashrc, KINETIS_IRQ_FLASHRC /* Vector 35: Flash memory read collision */ + HANDLER kinetis_smclvd, KINETIS_IRQ_SMCLVD /* Vector 36: Mode Controller low-voltage detect, low-voltage warning */ + HANDLER kinetis_llwu, KINETIS_IRQ_LLWU /* Vector 37: LLWU Normal Low Leakage Wakeup */ + HANDLER kinetis_wdog, KINETIS_IRQ_WDOG /* Vector 38: Watchdog */ + HANDLER kinetis_rngb, KINETIS_IRQ_RNGB /* Vector 39: Random number generator */ + HANDLER kinetis_i2c0, KINETIS_IRQ_I2C0 /* Vector 40: I2C0 */ + HANDLER kinetis_i2c1, KINETIS_IRQ_I2C1 /* Vector 41: I2C1 */ + HANDLER kinetis_spi0, KINETIS_IRQ_SPI0 /* Vector 42: SPI0 all sources */ + HANDLER kinetis_spi1, KINETIS_IRQ_SPI1 /* Vector 43: SPI1 all sources */ + HANDLER kinetis_i2s0, KINETIS_IRQ_I2S0 /* Vector 44: Transmit */ + HANDLER kinetis_i2s1, KINETIS_IRQ_I2S1 /* Vector 45: Transmit */ + HANDLER kinetis_uart0s, KINETIS_IRQ_UART0S /* Vector 47: UART0 status */ + HANDLER kinetis_uart0e, KINETIS_IRQ_UART0E /* Vector 48: UART0 error */ + HANDLER kinetis_uart1s, KINETIS_IRQ_UART1S /* Vector 49: UART1 status */ + HANDLER kinetis_uart1e, KINETIS_IRQ_UART1E /* Vector 50: UART1 error */ + HANDLER kinetis_uart2s, KINETIS_IRQ_UART2S /* Vector 51: UART2 status */ + HANDLER kinetis_uart2e, KINETIS_IRQ_UART2E /* Vector 52: UART2 error */ + HANDLER kinetis_uart3s, KINETIS_IRQ_UART3S /* Vector 53: UART3 status */ + HANDLER kinetis_uart3e, KINETIS_IRQ_UART3E /* Vector 54: UART3 error */ + HANDLER kinetis_adc0, KINETIS_IRQ_ADC0 /* Vector 55: ADC0 */ + HANDLER kinetis_cmp0, KINETIS_IRQ_CMP0 /* Vector 56: CMP0 */ + HANDLER kinetis_cmp1, KINETIS_IRQ_CMP1 /* Vector 57: CMP1 */ + HANDLER kinetis_ftm0, KINETIS_IRQ_FTM0 /* Vector 58: FTM0 all sources */ + HANDLER kinetis_ftm1, KINETIS_IRQ_FTM1 /* Vector 59: FTM1 all sources */ + HANDLER kinetis_ftm2, KINETIS_IRQ_FTM2 /* Vector 60: FTM2 all sources */ + HANDLER kinetis_cmt, KINETIS_IRQ_CMT /* Vector 61: CMT */ + HANDLER kinetis_rtc0, KINETIS_IRQ_RTC0 /* Vector 62: RTC alarm interrupt */ + HANDLER kinetis_rtc1, KINETIS_IRQ_RTC1 /* Vector 63: RTC seconds interrupt */ + HANDLER kinetis_pitch0, KINETIS_IRQ_PITCH0 /* Vector 64: PIT channel 0 */ + HANDLER kinetis_pitch1, KINETIS_IRQ_PITCH1 /* Vector 65: PIT channel 1 */ + HANDLER kinetis_pitch2, KINETIS_IRQ_PITCH2 /* Vector 66: PIT channel 2 */ + HANDLER kinetis_pitch3, KINETIS_IRQ_PITCH3 /* Vector 67: PIT channel 3 */ + HANDLER kinetis_pdb, KINETIS_IRQ_PDB /* Vector 68: PDB */ + HANDLER kinetis_usbotg, KINETIS_IRQ_USBOTG /* Vector 68: USB OTG */ + HANDLER kinetis_usbcd, KINETIS_IRQ_USBCD /* Vector 70: USB charger detect */ + HANDLER kinetis_dac0, KINETIS_IRQ_DAC0 /* Vector 72: DAC0 */ + HANDLER kinetis_mcg, KINETIS_IRQ_MCG /* Vector 73: MCG */ + HANDLER kinetis_lpt, KINETIS_IRQ_LPT /* Vector 74: Low power timer */ + HANDLER kinetis_porta, KINETIS_IRQ_PORTA /* Vector 75: Pin detect port A */ + HANDLER kinetis_portb, KINETIS_IRQ_PORTB /* Vector 76: Pin detect port B */ + HANDLER kinetis_portc, KINETIS_IRQ_PORTC /* Vector 77: Pin detect port C */ + HANDLER kinetis_portd, KINETIS_IRQ_PORTD /* Vector 78: Pin detect port D */ + HANDLER kinetis_porte, KINETIS_IRQ_PORTE /* Vector 79: Pin detect port E */ + HANDLER kinetis_software, KINETIS_IRQ_SOFTWARE /* Vector 80: Software interrupt */ + HANDLER kinetis_spi2, KINETIS_IRQ_SPI2 /* Vector 81: SPI2 all sources */ + HANDLER kinetis_uart4s, KINETIS_IRQ_UART4S /* Vector 82: UART4 status */ + HANDLER kinetis_uart4e, KINETIS_IRQ_UART4E /* Vector 83: UART4 error */ + HANDLER kinetis_uart5s, KINETIS_IRQ_UART5S /* Vector 84: UART5 status */ + HANDLER kinetis_uart5e, KINETIS_IRQ_UART5E /* Vector 85: UART5 error */ + HANDLER kinetis_cmp2, KINETIS_IRQ_CMP2 /* Vector 86: CMP2 */ + HANDLER kinetis_ftm3, KINETIS_IRQ_FTM3 /* Vector 87: FTM3 all sources */ + HANDLER kinetis_dac1, KINETIS_IRQ_DAC1 /* Vector 88: DAC1 */ + HANDLER kinetis_adc1, KINETIS_IRQ_ADC1 /* Vector 89: ADC1 */ + HANDLER kinetis_i2c2, KINETIS_IRQ_I2C2 /* Vector 90: I2C2 */ + HANDLER kinetis_can0mb, KINETIS_IRQ_CAN0MB /* Vector 91: CAN0 ORed Message buffer (0-15) */ + HANDLER kinetis_can0bo, KINETIS_IRQ_CAN0BO /* Vector 92: CAN0 Bus Off */ + HANDLER kinetis_can0err, KINETIS_IRQ_CAN0ERR /* Vector 93: CAN0 Error */ + HANDLER kinetis_can0tw, KINETIS_IRQ_CAN0TW /* Vector 94: CAN0 Transmit Warning */ + HANDLER kinetis_can0rw, KINETIS_IRQ_CAN0RW /* Vector 95: CAN0 Receive Warning */ + HANDLER kinetis_can0wu, KINETIS_IRQ_CAN0WU /* Vector 96: CAN0 Wake UP */ + HANDLER kinetis_sdhc, KINETIS_IRQ_SDHC /* Vector 97: SDHC */ + HANDLER kinetis_emactmr, KINETIS_IRQ_EMACTMR /* Vector 91: Ethernet MAC IEEE 1588 timer interrupt */ + HANDLER kinetis_emactx, KINETIS_IRQ_EMACTX /* Vector 92: Ethernet MAC transmit interrupt */ + HANDLER kinetis_emacrx, KINETIS_IRQ_EMACRX /* Vector 93: Ethernet MAC receive interrupt */ + HANDLER kinetis_emacmisc, KINETIS_IRQ_EMACMISC /* Vector 94: Ethernet MAC error and misc interrupt */ + #else # error "No handlers for this Kinetis part" #endif diff --git a/arch/arm/src/kinetis/kinetis_wdog.c b/arch/arm/src/kinetis/kinetis_wdog.c index 9dc29b80d89..3beaad8d4bc 100644 --- a/arch/arm/src/kinetis/kinetis_wdog.c +++ b/arch/arm/src/kinetis/kinetis_wdog.c @@ -1,6 +1,5 @@ /**************************************************************************** * arch/arm/src/kinetis/kinetis_wdog.c - * arch/arm/src/chip/kinetis_wdog.c * * Copyright (C) 2011 Gregory Nutt. All rights reserved. * Author: Gregory Nutt @@ -44,19 +43,7 @@ #include "up_arch.h" #include "kinetis.h" -#include "kinetis_wdog.h" - -/**************************************************************************** - * Pre-processor Definitions - ****************************************************************************/ - -/**************************************************************************** - * Private Data - ****************************************************************************/ - -/**************************************************************************** - * Public Data - ****************************************************************************/ +#include "chip/kinetis_wdog.h" /**************************************************************************** * Private Functions