diff --git a/arch/arm/src/sama5/sam_pio.c b/arch/arm/src/sama5/sam_pio.c
index eb336db25f6..44d1f0103f1 100644
--- a/arch/arm/src/sama5/sam_pio.c
+++ b/arch/arm/src/sama5/sam_pio.c
@@ -137,7 +137,7 @@ static inline int sam_piopin(pio_pinset_t cfgset)
 static inline int sam_configinput(uintptr_t base, uint32_t pin,
                                   pio_pinset_t cfgset)
 {
-#if defined(PIO_HAVE_SCHMITT) || defined(PIO_HAVE_DRIVE) || defined(SAM_PIO_ISLR_OFFSET)
+#if defined(PIO_HAVE_SCHMITT) || defined(PIO_HAVE_DRIVE)
   uint32_t regval;
 #endif
 #if defined(PIO_HAVE_DRIVE)
@@ -151,14 +151,6 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
 
   putreg32(pin, base + SAM_PIO_IDR_OFFSET);
 
-#if defined(SAM_PIO_ISLR_OFFSET)
-  /* Assume unsecure */
-
-  regval  = getreg32(base + SAM_PIO_ISLR_OFFSET);
-  regval |= pin;
-  putreg32(regval, base + SAM_PIO_ISLR_OFFSET);
-#endif
-
   /* Enable/disable the pull-up as requested */
 
   if ((cfgset & PIO_CFG_PULLUP) != 0)
@@ -256,22 +248,10 @@ static inline int sam_configinput(uintptr_t base, uint32_t pin,
 static inline int sam_configoutput(uintptr_t base, uint32_t pin,
                                    pio_pinset_t cfgset)
 {
-#if defined(SAM_PIO_ISLR_OFFSET)
-  uint32_t regval;
-#endif
-
   /* Disable interrupts on the pin */
 
   putreg32(pin, base + SAM_PIO_IDR_OFFSET);
 
-#if defined(SAM_PIO_ISLR_OFFSET)
-  /* Assume unsecure */
-
-  regval  = getreg32(base + SAM_PIO_ISLR_OFFSET);
-  regval |= pin;
-  putreg32(regval, base + SAM_PIO_ISLR_OFFSET);
-#endif
-
   /* Enable/disable the pull-up as requested */
 
   if ((cfgset & PIO_CFG_PULLUP) != 0)
@@ -343,14 +323,6 @@ static inline int sam_configperiph(uintptr_t base, uint32_t pin,
 
   putreg32(pin, base + SAM_PIO_IDR_OFFSET);
 
-#if defined(SAM_PIO_ISLR_OFFSET)
-  /* Assume unsecure */
-
-  regval = getreg32(base + SAM_PIO_ISLR_OFFSET);
-  regval |= pin;
-  putreg32(regval, base + SAM_PIO_ISLR_OFFSET);
-#endif
-
   /* Enable/disable the pull-up as requested */
 
   if ((cfgset & PIO_CFG_PULLUP) != 0)
@@ -466,7 +438,21 @@ int sam_configpio(pio_pinset_t cfgset)
 
   flags = irqsave();
 
-  /* Enable writing to PIO registers */
+  /* Enable writing to PIO registers.  The following registers are protected:
+   *
+   *  - PIO Enable/Disable Registers (PER/PDR)
+   *  - PIO Output Enable/Disable Registers (OER/ODR)
+   *  - PIO Interrupt Security Level Register (ISLR)
+   *  - PIO Input Filter Enable/Disable Registers (IFER/IFDR)
+   *  - PIO Multi-driver Enable/Disable Registers (MDER/MDDR)
+   *  - PIO Pull-Up Enable/Disable Registers (PUER/PUDR)
+   *  - PIO Peripheral ABCD Select Register 1/2 (ABCDSR1/2)
+   *  - PIO Output Write Enable/Disable Registers
+   *  - PIO Pad Pull-Down Enable/Disable Registers (PPER/PPDR)
+   *
+   * I suspect that the default state is the WPMR is unprotected, so these
+   * operations could probably all be avoided.
+   */
 
   putreg32(PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET);
 
diff --git a/arch/arm/src/sama5/sam_pioirq.c b/arch/arm/src/sama5/sam_pioirq.c
index 0d9269a465d..4557eb48f58 100644
--- a/arch/arm/src/sama5/sam_pioirq.c
+++ b/arch/arm/src/sama5/sam_pioirq.c
@@ -375,22 +375,48 @@ void sam_pioirqinitialize(void)
 
 void sam_pioirq(pio_pinset_t pinset)
 {
+#if defined(SAM_PIO_ISLR_OFFSET)
+  uint32_t regval;
+#endif
   uint32_t base = sam_piobase(pinset);
   int      pin  = sam_piopin(pinset);
 
-  /* Enable writing to PIO registers */
+#if defined(SAM_PIO_ISLR_OFFSET)
+  /* Enable writing to PIO registers.  The following registers are protected:
+   *
+   *  - PIO Enable/Disable Registers (PER/PDR)
+   *  - PIO Output Enable/Disable Registers (OER/ODR)
+   *  - PIO Interrupt Security Level Register (ISLR)
+   *  - PIO Input Filter Enable/Disable Registers (IFER/IFDR)
+   *  - PIO Multi-driver Enable/Disable Registers (MDER/MDDR)
+   *  - PIO Pull-Up Enable/Disable Registers (PUER/PUDR)
+   *  - PIO Peripheral ABCD Select Register 1/2 (ABCDSR1/2)
+   *  - PIO Output Write Enable/Disable Registers
+   *  - PIO Pad Pull-Down Enable/Disable Registers (PPER/PPDR)
+   *
+   * I suspect that the default state is the WPMR is unprotected, so these
+   * operations could probably all be avoided.
+   */
 
   putreg32(PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET);
 
-#if defined(SAMA5_SAIC) && defined(SAM_PIO_ISLR_OFFSET)
   /* Is the interrupt secure? */
 
+   regval = getreg32(base + SAM_PIO_ISLR_OFFSET);
    if ((pinset & PIO_INT_SECURE) != 0)
      {
-       uint32_t regval = getreg32(base + SAM_PIO_ISLR_OFFSET);
+       /* Yes.. make sure that the corresponding bit in ISLR is cleared */
+
        regval &= ~pin;
-       putreg32(regval, base + SAM_PIO_ISLR_OFFSET);
      }
+   else
+     {
+       /* Yes.. make sure that the corresponding bit in ISLR is set */
+
+       regval |= pin;
+     }
+
+   putreg32(regval, base + SAM_PIO_ISLR_OFFSET);
 #endif
 
    /* Are any additional interrupt modes selected? */
@@ -430,9 +456,11 @@ void sam_pioirq(pio_pinset_t pinset)
        putreg32(pin, base + SAM_PIO_AIMDR_OFFSET);
      }
 
+#if defined(SAM_PIO_ISLR_OFFSET)
   /* Disable writing to PIO registers */
 
   putreg32(PIO_WPMR_WPEN | PIO_WPMR_WPKEY, base + SAM_PIO_WPMR_OFFSET);
+#endif
 }
 
 /************************************************************************************